1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include "rge.h" 29 30 #define REG32(rgep, reg) ((uint32_t *)(rgep->io_regs+(reg))) 31 #define REG16(rgep, reg) ((uint16_t *)(rgep->io_regs+(reg))) 32 #define REG8(rgep, reg) ((uint8_t *)(rgep->io_regs+(reg))) 33 #define PIO_ADDR(rgep, offset) ((void *)(rgep->io_regs+(offset))) 34 35 /* 36 * Patchable globals: 37 * 38 * rge_autorecover 39 * Enables/disables automatic recovery after fault detection 40 */ 41 static uint32_t rge_autorecover = 1; 42 43 /* 44 * globals: 45 */ 46 #define RGE_DBG RGE_DBG_REGS /* debug flag for this code */ 47 static uint32_t rge_watchdog_count = 1 << 16; 48 49 /* 50 * Operating register get/set access routines 51 */ 52 53 static uint32_t rge_reg_get32(rge_t *rgep, uintptr_t regno); 54 #pragma inline(rge_reg_get32) 55 56 static uint32_t 57 rge_reg_get32(rge_t *rgep, uintptr_t regno) 58 { 59 RGE_TRACE(("rge_reg_get32($%p, 0x%lx)", 60 (void *)rgep, regno)); 61 62 return (ddi_get32(rgep->io_handle, REG32(rgep, regno))); 63 } 64 65 static void rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data); 66 #pragma inline(rge_reg_put32) 67 68 static void 69 rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data) 70 { 71 RGE_TRACE(("rge_reg_put32($%p, 0x%lx, 0x%x)", 72 (void *)rgep, regno, data)); 73 74 ddi_put32(rgep->io_handle, REG32(rgep, regno), data); 75 } 76 77 static void rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits); 78 #pragma inline(rge_reg_set32) 79 80 static void 81 rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits) 82 { 83 uint32_t regval; 84 85 RGE_TRACE(("rge_reg_set32($%p, 0x%lx, 0x%x)", 86 (void *)rgep, regno, bits)); 87 88 regval = rge_reg_get32(rgep, regno); 89 regval |= bits; 90 rge_reg_put32(rgep, regno, regval); 91 } 92 93 static void rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits); 94 #pragma inline(rge_reg_clr32) 95 96 static void 97 rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits) 98 { 99 uint32_t regval; 100 101 RGE_TRACE(("rge_reg_clr32($%p, 0x%lx, 0x%x)", 102 (void *)rgep, regno, bits)); 103 104 regval = rge_reg_get32(rgep, regno); 105 regval &= ~bits; 106 rge_reg_put32(rgep, regno, regval); 107 } 108 109 static uint16_t rge_reg_get16(rge_t *rgep, uintptr_t regno); 110 #pragma inline(rge_reg_get16) 111 112 static uint16_t 113 rge_reg_get16(rge_t *rgep, uintptr_t regno) 114 { 115 RGE_TRACE(("rge_reg_get16($%p, 0x%lx)", 116 (void *)rgep, regno)); 117 118 return (ddi_get16(rgep->io_handle, REG16(rgep, regno))); 119 } 120 121 static void rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data); 122 #pragma inline(rge_reg_put16) 123 124 static void 125 rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data) 126 { 127 RGE_TRACE(("rge_reg_put16($%p, 0x%lx, 0x%x)", 128 (void *)rgep, regno, data)); 129 130 ddi_put16(rgep->io_handle, REG16(rgep, regno), data); 131 } 132 133 static uint8_t rge_reg_get8(rge_t *rgep, uintptr_t regno); 134 #pragma inline(rge_reg_get8) 135 136 static uint8_t 137 rge_reg_get8(rge_t *rgep, uintptr_t regno) 138 { 139 RGE_TRACE(("rge_reg_get8($%p, 0x%lx)", 140 (void *)rgep, regno)); 141 142 return (ddi_get8(rgep->io_handle, REG8(rgep, regno))); 143 } 144 145 static void rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data); 146 #pragma inline(rge_reg_put8) 147 148 static void 149 rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data) 150 { 151 RGE_TRACE(("rge_reg_put8($%p, 0x%lx, 0x%x)", 152 (void *)rgep, regno, data)); 153 154 ddi_put8(rgep->io_handle, REG8(rgep, regno), data); 155 } 156 157 static void rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits); 158 #pragma inline(rge_reg_set8) 159 160 static void 161 rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits) 162 { 163 uint8_t regval; 164 165 RGE_TRACE(("rge_reg_set8($%p, 0x%lx, 0x%x)", 166 (void *)rgep, regno, bits)); 167 168 regval = rge_reg_get8(rgep, regno); 169 regval |= bits; 170 rge_reg_put8(rgep, regno, regval); 171 } 172 173 static void rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits); 174 #pragma inline(rge_reg_clr8) 175 176 static void 177 rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits) 178 { 179 uint8_t regval; 180 181 RGE_TRACE(("rge_reg_clr8($%p, 0x%lx, 0x%x)", 182 (void *)rgep, regno, bits)); 183 184 regval = rge_reg_get8(rgep, regno); 185 regval &= ~bits; 186 rge_reg_put8(rgep, regno, regval); 187 } 188 189 uint16_t rge_mii_get16(rge_t *rgep, uintptr_t mii); 190 #pragma no_inline(rge_mii_get16) 191 192 uint16_t 193 rge_mii_get16(rge_t *rgep, uintptr_t mii) 194 { 195 uint32_t regval; 196 uint32_t val32; 197 uint32_t i; 198 199 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 200 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 201 202 /* 203 * Waiting for PHY reading OK 204 */ 205 for (i = 0; i < PHY_RESET_LOOP; i++) { 206 drv_usecwait(1000); 207 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 208 if (val32 & PHY_ACCESS_WR_FLAG) 209 return ((uint16_t)(val32 & 0xffff)); 210 } 211 212 RGE_REPORT((rgep, "rge_mii_get16(0x%x) fail, val = %x", mii, val32)); 213 return ((uint16_t)~0u); 214 } 215 216 void rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data); 217 #pragma no_inline(rge_mii_put16) 218 219 void 220 rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data) 221 { 222 uint32_t regval; 223 uint32_t val32; 224 uint32_t i; 225 226 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 227 regval |= data & PHY_DATA_MASK; 228 regval |= PHY_ACCESS_WR_FLAG; 229 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 230 231 /* 232 * Waiting for PHY writing OK 233 */ 234 for (i = 0; i < PHY_RESET_LOOP; i++) { 235 drv_usecwait(1000); 236 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 237 if (!(val32 & PHY_ACCESS_WR_FLAG)) 238 return; 239 } 240 RGE_REPORT((rgep, "rge_mii_put16(0x%lx, 0x%x) fail", 241 mii, data)); 242 } 243 244 void rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data); 245 #pragma no_inline(rge_ephy_put16) 246 247 void 248 rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data) 249 { 250 uint32_t regval; 251 uint32_t val32; 252 uint32_t i; 253 254 regval = (emii & EPHY_REG_MASK) << EPHY_REG_SHIFT; 255 regval |= data & EPHY_DATA_MASK; 256 regval |= EPHY_ACCESS_WR_FLAG; 257 rge_reg_put32(rgep, EPHY_ACCESS_REG, regval); 258 259 /* 260 * Waiting for PHY writing OK 261 */ 262 for (i = 0; i < PHY_RESET_LOOP; i++) { 263 drv_usecwait(1000); 264 val32 = rge_reg_get32(rgep, EPHY_ACCESS_REG); 265 if (!(val32 & EPHY_ACCESS_WR_FLAG)) 266 return; 267 } 268 RGE_REPORT((rgep, "rge_ephy_put16(0x%lx, 0x%x) fail", 269 emii, data)); 270 } 271 272 /* 273 * Atomically shift a 32-bit word left, returning 274 * the value it had *before* the shift was applied 275 */ 276 static uint32_t rge_atomic_shl32(uint32_t *sp, uint_t count); 277 #pragma inline(rge_mii_put16) 278 279 static uint32_t 280 rge_atomic_shl32(uint32_t *sp, uint_t count) 281 { 282 uint32_t oldval; 283 uint32_t newval; 284 285 /* ATOMICALLY */ 286 do { 287 oldval = *sp; 288 newval = oldval << count; 289 } while (cas32(sp, oldval, newval) != oldval); 290 291 return (oldval); 292 } 293 294 /* 295 * PHY operation routines 296 */ 297 #if RGE_DEBUGGING 298 299 void 300 rge_phydump(rge_t *rgep) 301 { 302 uint16_t regs[32]; 303 int i; 304 305 ASSERT(mutex_owned(rgep->genlock)); 306 307 for (i = 0; i < 32; ++i) { 308 regs[i] = rge_mii_get16(rgep, i); 309 } 310 311 for (i = 0; i < 32; i += 8) 312 RGE_DEBUG(("rge_phydump: " 313 "0x%04x %04x %04x %04x %04x %04x %04x %04x", 314 regs[i+0], regs[i+1], regs[i+2], regs[i+3], 315 regs[i+4], regs[i+5], regs[i+6], regs[i+7])); 316 } 317 318 #endif /* RGE_DEBUGGING */ 319 320 static void 321 rge_phy_check(rge_t *rgep) 322 { 323 uint16_t gig_ctl; 324 325 if (rgep->param_link_up == LINK_STATE_DOWN) { 326 /* 327 * RTL8169S/8110S PHY has the "PCS bug". Need reset PHY 328 * every 15 seconds whin link down & advertise is 1000. 329 */ 330 if (rgep->chipid.phy_ver == PHY_VER_S) { 331 gig_ctl = rge_mii_get16(rgep, MII_1000BASE_T_CONTROL); 332 if (gig_ctl & MII_1000BT_CTL_ADV_FDX) { 333 rgep->link_down_count++; 334 if (rgep->link_down_count > 15) { 335 (void) rge_phy_reset(rgep); 336 rgep->stats.phy_reset++; 337 rgep->link_down_count = 0; 338 } 339 } 340 } 341 } else { 342 rgep->link_down_count = 0; 343 } 344 } 345 346 /* 347 * Basic low-level function to reset the PHY. 348 * Doesn't incorporate any special-case workarounds. 349 * 350 * Returns TRUE on success, FALSE if the RESET bit doesn't clear 351 */ 352 boolean_t 353 rge_phy_reset(rge_t *rgep) 354 { 355 uint16_t control; 356 uint_t count; 357 358 /* 359 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear 360 */ 361 control = rge_mii_get16(rgep, MII_CONTROL); 362 rge_mii_put16(rgep, MII_CONTROL, control | MII_CONTROL_RESET); 363 for (count = 0; count < 5; count++) { 364 drv_usecwait(100); 365 control = rge_mii_get16(rgep, MII_CONTROL); 366 if (BIC(control, MII_CONTROL_RESET)) 367 return (B_TRUE); 368 } 369 370 RGE_REPORT((rgep, "rge_phy_reset: FAILED, control now 0x%x", control)); 371 return (B_FALSE); 372 } 373 374 /* 375 * Synchronise the PHY's speed/duplex/autonegotiation capabilities 376 * and advertisements with the required settings as specified by the various 377 * param_* variables that can be poked via the NDD interface. 378 * 379 * We always reset the PHY and reprogram *all* the relevant registers, 380 * not just those changed. This should cause the link to go down, and then 381 * back up again once the link is stable and autonegotiation (if enabled) 382 * is complete. We should get a link state change interrupt somewhere along 383 * the way ... 384 * 385 * NOTE: <genlock> must already be held by the caller 386 */ 387 void 388 rge_phy_update(rge_t *rgep) 389 { 390 boolean_t adv_autoneg; 391 boolean_t adv_pause; 392 boolean_t adv_asym_pause; 393 boolean_t adv_1000fdx; 394 boolean_t adv_1000hdx; 395 boolean_t adv_100fdx; 396 boolean_t adv_100hdx; 397 boolean_t adv_10fdx; 398 boolean_t adv_10hdx; 399 400 uint16_t control; 401 uint16_t gigctrl; 402 uint16_t anar; 403 404 ASSERT(mutex_owned(rgep->genlock)); 405 406 RGE_DEBUG(("rge_phy_update: autoneg %d " 407 "pause %d asym_pause %d " 408 "1000fdx %d 1000hdx %d " 409 "100fdx %d 100hdx %d " 410 "10fdx %d 10hdx %d ", 411 rgep->param_adv_autoneg, 412 rgep->param_adv_pause, rgep->param_adv_asym_pause, 413 rgep->param_adv_1000fdx, rgep->param_adv_1000hdx, 414 rgep->param_adv_100fdx, rgep->param_adv_100hdx, 415 rgep->param_adv_10fdx, rgep->param_adv_10hdx)); 416 417 control = gigctrl = anar = 0; 418 419 /* 420 * PHY settings are normally based on the param_* variables, 421 * but if any loopback mode is in effect, that takes precedence. 422 * 423 * RGE supports MAC-internal loopback, PHY-internal loopback, 424 * and External loopback at a variety of speeds (with a special 425 * cable). In all cases, autoneg is turned OFF, full-duplex 426 * is turned ON, and the speed/mastership is forced. 427 */ 428 switch (rgep->param_loop_mode) { 429 case RGE_LOOP_NONE: 430 default: 431 adv_autoneg = rgep->param_adv_autoneg; 432 adv_pause = rgep->param_adv_pause; 433 adv_asym_pause = rgep->param_adv_asym_pause; 434 adv_1000fdx = rgep->param_adv_1000fdx; 435 adv_1000hdx = rgep->param_adv_1000hdx; 436 adv_100fdx = rgep->param_adv_100fdx; 437 adv_100hdx = rgep->param_adv_100hdx; 438 adv_10fdx = rgep->param_adv_10fdx; 439 adv_10hdx = rgep->param_adv_10hdx; 440 break; 441 442 case RGE_LOOP_INTERNAL_PHY: 443 case RGE_LOOP_INTERNAL_MAC: 444 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 445 adv_1000fdx = adv_100fdx = adv_10fdx = B_FALSE; 446 adv_1000hdx = adv_100hdx = adv_10hdx = B_FALSE; 447 rgep->param_link_duplex = LINK_DUPLEX_FULL; 448 449 switch (rgep->param_loop_mode) { 450 case RGE_LOOP_INTERNAL_PHY: 451 if (rgep->chipid.mac_ver != MAC_VER_8101E) { 452 rgep->param_link_speed = 1000; 453 adv_1000fdx = B_TRUE; 454 } else { 455 rgep->param_link_speed = 100; 456 adv_100fdx = B_TRUE; 457 } 458 control = MII_CONTROL_LOOPBACK; 459 break; 460 461 case RGE_LOOP_INTERNAL_MAC: 462 if (rgep->chipid.mac_ver != MAC_VER_8101E) { 463 rgep->param_link_speed = 1000; 464 adv_1000fdx = B_TRUE; 465 } else { 466 rgep->param_link_speed = 100; 467 adv_100fdx = B_TRUE; 468 break; 469 } 470 } 471 472 RGE_DEBUG(("rge_phy_update: autoneg %d " 473 "pause %d asym_pause %d " 474 "1000fdx %d 1000hdx %d " 475 "100fdx %d 100hdx %d " 476 "10fdx %d 10hdx %d ", 477 adv_autoneg, 478 adv_pause, adv_asym_pause, 479 adv_1000fdx, adv_1000hdx, 480 adv_100fdx, adv_100hdx, 481 adv_10fdx, adv_10hdx)); 482 483 /* 484 * We should have at least one technology capability set; 485 * if not, we select a default of 1000Mb/s full-duplex 486 */ 487 if (!adv_1000fdx && !adv_100fdx && !adv_10fdx && 488 !adv_1000hdx && !adv_100hdx && !adv_10hdx) { 489 if (rgep->chipid.mac_ver != MAC_VER_8101E) 490 adv_1000fdx = B_TRUE; 491 } else { 492 adv_1000fdx = B_FALSE; 493 adv_100fdx = B_TRUE; 494 } 495 } 496 497 /* 498 * Now transform the adv_* variables into the proper settings 499 * of the PHY registers ... 500 * 501 * If autonegotiation is (now) enabled, we want to trigger 502 * a new autonegotiation cycle once the PHY has been 503 * programmed with the capabilities to be advertised. 504 * 505 * RTL8169/8110 doesn't support 1000Mb/s half-duplex. 506 */ 507 if (adv_autoneg) 508 control |= MII_CONTROL_ANE|MII_CONTROL_RSAN; 509 510 if (adv_1000fdx) 511 control |= MII_CONTROL_1000MB|MII_CONTROL_FDUPLEX; 512 else if (adv_1000hdx) 513 control |= MII_CONTROL_1000MB; 514 else if (adv_100fdx) 515 control |= MII_CONTROL_100MB|MII_CONTROL_FDUPLEX; 516 else if (adv_100hdx) 517 control |= MII_CONTROL_100MB; 518 else if (adv_10fdx) 519 control |= MII_CONTROL_FDUPLEX; 520 else if (adv_10hdx) 521 control |= 0; 522 else 523 { _NOTE(EMPTY); } /* Can't get here anyway ... */ 524 525 if (adv_1000fdx) { 526 gigctrl |= MII_1000BT_CTL_ADV_FDX; 527 /* 528 * Chipset limitation: need set other capabilities to true 529 */ 530 if (rgep->chipid.is_pcie) 531 adv_1000hdx = B_TRUE; 532 adv_100fdx = B_TRUE; 533 adv_100hdx = B_TRUE; 534 adv_10fdx = B_TRUE; 535 adv_10hdx = B_TRUE; 536 } 537 538 if (adv_1000hdx) 539 gigctrl |= MII_1000BT_CTL_ADV_HDX; 540 541 if (adv_100fdx) 542 anar |= MII_ABILITY_100BASE_TX_FD; 543 if (adv_100hdx) 544 anar |= MII_ABILITY_100BASE_TX; 545 if (adv_10fdx) 546 anar |= MII_ABILITY_10BASE_T_FD; 547 if (adv_10hdx) 548 anar |= MII_ABILITY_10BASE_T; 549 550 if (adv_pause) 551 anar |= MII_ABILITY_PAUSE; 552 if (adv_asym_pause) 553 anar |= MII_ABILITY_ASYM_PAUSE; 554 555 /* 556 * Munge in any other fixed bits we require ... 557 */ 558 anar |= MII_AN_SELECTOR_8023; 559 560 /* 561 * Restart the PHY and write the new values. Note the 562 * time, so that we can say whether subsequent link state 563 * changes can be attributed to our reprogramming the PHY 564 */ 565 rge_phy_init(rgep); 566 if (rgep->chipid.mac_ver == MAC_VER_8168B_B || 567 rgep->chipid.mac_ver == MAC_VER_8168B_C) { 568 /* power up PHY for RTL8168B chipset */ 569 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 570 rge_mii_put16(rgep, PHY_0E_REG, 0x0000); 571 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 572 } 573 rge_mii_put16(rgep, MII_AN_ADVERT, anar); 574 rge_mii_put16(rgep, MII_1000BASE_T_CONTROL, gigctrl); 575 rge_mii_put16(rgep, MII_CONTROL, control); 576 577 RGE_DEBUG(("rge_phy_update: anar <- 0x%x", anar)); 578 RGE_DEBUG(("rge_phy_update: control <- 0x%x", control)); 579 RGE_DEBUG(("rge_phy_update: gigctrl <- 0x%x", gigctrl)); 580 } 581 582 void rge_phy_init(rge_t *rgep); 583 #pragma no_inline(rge_phy_init) 584 585 void 586 rge_phy_init(rge_t *rgep) 587 { 588 rgep->phy_mii_addr = 1; 589 590 /* 591 * Below phy config steps are copied from the Programming Guide 592 * (there's no detail comments for these steps.) 593 */ 594 switch (rgep->chipid.mac_ver) { 595 case MAC_VER_8169S_D: 596 case MAC_VER_8169S_E : 597 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 598 rge_mii_put16(rgep, PHY_15_REG, 0x1000); 599 rge_mii_put16(rgep, PHY_18_REG, 0x65c7); 600 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 601 rge_mii_put16(rgep, PHY_ID_REG_2, 0x00a1); 602 rge_mii_put16(rgep, PHY_ID_REG_1, 0x0008); 603 rge_mii_put16(rgep, PHY_BMSR_REG, 0x1020); 604 rge_mii_put16(rgep, PHY_BMCR_REG, 0x1000); 605 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0800); 606 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 607 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 608 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 609 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde60); 610 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 611 rge_mii_put16(rgep, PHY_BMCR_REG, 0x0077); 612 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7800); 613 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 614 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 615 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 616 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 617 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 618 rge_mii_put16(rgep, PHY_BMCR_REG, 0xfa00); 619 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa800); 620 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 621 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 622 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 623 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde20); 624 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 625 rge_mii_put16(rgep, PHY_BMCR_REG, 0x00bb); 626 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb800); 627 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 628 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 629 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 630 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 631 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 632 rge_mii_put16(rgep, PHY_BMCR_REG, 0xbf00); 633 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf800); 634 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 635 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 636 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 637 rge_mii_put16(rgep, PHY_0B_REG, 0x0000); 638 break; 639 640 case MAC_VER_8169SB: 641 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 642 rge_mii_put16(rgep, PHY_1B_REG, 0xD41E); 643 rge_mii_put16(rgep, PHY_0E_REG, 0x7bff); 644 rge_mii_put16(rgep, PHY_GBCR_REG, GBCR_DEFAULT); 645 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 646 rge_mii_put16(rgep, PHY_BMSR_REG, 0x90D0); 647 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 648 break; 649 650 case MAC_VER_8169SC: 651 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 652 rge_mii_put16(rgep, PHY_ANER_REG, 0x0078); 653 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x05dc); 654 rge_mii_put16(rgep, PHY_GBCR_REG, 0x2672); 655 rge_mii_put16(rgep, PHY_GBSR_REG, 0x6a14); 656 rge_mii_put16(rgep, PHY_0B_REG, 0x7cb0); 657 rge_mii_put16(rgep, PHY_0C_REG, 0xdb80); 658 rge_mii_put16(rgep, PHY_1B_REG, 0xc414); 659 rge_mii_put16(rgep, PHY_1C_REG, 0xef03); 660 rge_mii_put16(rgep, PHY_1D_REG, 0x3dc8); 661 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 662 rge_mii_put16(rgep, PHY_13_REG, 0x0600); 663 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 664 break; 665 666 case MAC_VER_8168: 667 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 668 rge_mii_put16(rgep, PHY_ANER_REG, 0x00aa); 669 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x3173); 670 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x08fc); 671 rge_mii_put16(rgep, PHY_GBCR_REG, 0xe2d0); 672 rge_mii_put16(rgep, PHY_0B_REG, 0x941a); 673 rge_mii_put16(rgep, PHY_18_REG, 0x65fe); 674 rge_mii_put16(rgep, PHY_1C_REG, 0x1e02); 675 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 676 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x103e); 677 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 678 break; 679 680 case MAC_VER_8168B_B: 681 case MAC_VER_8168B_C: 682 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 683 rge_mii_put16(rgep, PHY_0B_REG, 0x94b0); 684 rge_mii_put16(rgep, PHY_1B_REG, 0xc416); 685 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 686 rge_mii_put16(rgep, PHY_12_REG, 0x6096); 687 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 688 break; 689 } 690 } 691 692 void rge_chip_ident(rge_t *rgep); 693 #pragma no_inline(rge_chip_ident) 694 695 void 696 rge_chip_ident(rge_t *rgep) 697 { 698 chip_id_t *chip = &rgep->chipid; 699 uint32_t val32; 700 uint16_t val16; 701 702 /* 703 * Read and record MAC version 704 */ 705 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 706 val32 &= HW_VERSION_ID_0 | HW_VERSION_ID_1; 707 chip->mac_ver = val32; 708 switch (chip->mac_ver) { 709 case MAC_VER_8168: 710 case MAC_VER_8168B_B: 711 case MAC_VER_8168B_C: 712 case MAC_VER_8101E: 713 chip->is_pcie = B_TRUE; 714 break; 715 716 default: 717 chip->is_pcie = B_FALSE; 718 break; 719 } 720 721 /* 722 * Read and record PHY version 723 */ 724 val16 = rge_mii_get16(rgep, PHY_ID_REG_2); 725 val16 &= PHY_VER_MASK; 726 chip->phy_ver = val16; 727 728 /* set pci latency timer */ 729 if (chip->mac_ver == MAC_VER_8169 || 730 chip->mac_ver == MAC_VER_8169S_D || 731 chip->mac_ver == MAC_VER_8169SC) 732 pci_config_put8(rgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 0x40); 733 734 if (chip->mac_ver == MAC_VER_8169SC) { 735 val16 = rge_reg_get16(rgep, RT_CONFIG_1_REG); 736 val16 &= 0x0300; 737 if (val16 == 0x1) /* 66Mhz PCI */ 738 pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ff00ff); 739 else if (val16 == 0x0) /* 33Mhz PCI */ 740 pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ffff00); 741 } 742 743 /* 744 * PCIE chipset require the Rx buffer start address must be 745 * 8-byte alignment and the Rx buffer size must be multiple of 8. 746 * We'll just use bcopy in receive procedure for the PCIE chipset. 747 */ 748 if (chip->is_pcie) { 749 rgep->chip_flags |= CHIP_FLAG_FORCE_BCOPY; 750 if (rgep->default_mtu > ETHERMTU) { 751 rge_notice(rgep, "Jumbo packets not supported " 752 "for this PCIE chipset"); 753 rgep->default_mtu = ETHERMTU; 754 } 755 } 756 if (rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY) 757 rgep->head_room = 0; 758 else 759 rgep->head_room = RGE_HEADROOM; 760 761 /* 762 * Initialize other variables. 763 */ 764 if (rgep->default_mtu < ETHERMTU || rgep->default_mtu > RGE_JUMBO_MTU) 765 rgep->default_mtu = ETHERMTU; 766 if (rgep->default_mtu > ETHERMTU) { 767 rgep->rxbuf_size = RGE_BUFF_SIZE_JUMBO; 768 rgep->txbuf_size = RGE_BUFF_SIZE_JUMBO; 769 rgep->ethmax_size = RGE_JUMBO_SIZE; 770 } else { 771 rgep->rxbuf_size = RGE_BUFF_SIZE_STD; 772 rgep->txbuf_size = RGE_BUFF_SIZE_STD; 773 rgep->ethmax_size = ETHERMAX; 774 } 775 chip->rxconfig = RX_CONFIG_DEFAULT; 776 chip->txconfig = TX_CONFIG_DEFAULT; 777 778 RGE_TRACE(("%s: MAC version = %x, PHY version = %x", 779 rgep->ifname, chip->mac_ver, chip->phy_ver)); 780 } 781 782 /* 783 * Perform first-stage chip (re-)initialisation, using only config-space 784 * accesses: 785 * 786 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 787 * returning the data in the structure pointed to by <idp>. 788 * + Enable Memory Space accesses. 789 * + Enable Bus Mastering according. 790 */ 791 void rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp); 792 #pragma no_inline(rge_chip_cfg_init) 793 794 void 795 rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp) 796 { 797 ddi_acc_handle_t handle; 798 uint16_t commd; 799 800 handle = rgep->cfg_handle; 801 802 /* 803 * Save PCI cache line size and subsystem vendor ID 804 */ 805 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 806 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 807 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 808 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 809 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 810 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 811 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 812 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 813 814 /* 815 * Turn on Master Enable (DMA) and IO Enable bits. 816 * Enable PCI Memory Space accesses 817 */ 818 commd = cidp->command; 819 commd |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 820 pci_config_put16(handle, PCI_CONF_COMM, commd); 821 822 RGE_DEBUG(("rge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 823 cidp->vendor, cidp->device, cidp->revision)); 824 RGE_DEBUG(("rge_chip_cfg_init: subven 0x%x subdev 0x%x", 825 cidp->subven, cidp->subdev)); 826 RGE_DEBUG(("rge_chip_cfg_init: clsize %d latency %d command 0x%x", 827 cidp->clsize, cidp->latency, cidp->command)); 828 } 829 830 int rge_chip_reset(rge_t *rgep); 831 #pragma no_inline(rge_chip_reset) 832 833 int 834 rge_chip_reset(rge_t *rgep) 835 { 836 int i; 837 uint8_t val8; 838 839 /* 840 * Chip should be in STOP state 841 */ 842 rge_reg_clr8(rgep, RT_COMMAND_REG, 843 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 844 845 /* 846 * Disable interrupt 847 */ 848 rgep->int_mask = INT_MASK_NONE; 849 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 850 851 /* 852 * Clear pended interrupt 853 */ 854 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 855 856 /* 857 * Reset chip 858 */ 859 rge_reg_set8(rgep, RT_COMMAND_REG, RT_COMMAND_RESET); 860 861 /* 862 * Wait for reset success 863 */ 864 for (i = 0; i < CHIP_RESET_LOOP; i++) { 865 drv_usecwait(10); 866 val8 = rge_reg_get8(rgep, RT_COMMAND_REG); 867 if (!(val8 & RT_COMMAND_RESET)) { 868 rgep->rge_chip_state = RGE_CHIP_RESET; 869 return (0); 870 } 871 } 872 RGE_REPORT((rgep, "rge_chip_reset fail.")); 873 return (-1); 874 } 875 876 void rge_chip_init(rge_t *rgep); 877 #pragma no_inline(rge_chip_init) 878 879 void 880 rge_chip_init(rge_t *rgep) 881 { 882 uint32_t val32; 883 uint32_t val16; 884 uint32_t *hashp; 885 chip_id_t *chip = &rgep->chipid; 886 887 if (chip->is_pcie) { 888 /* 889 * Increase the threshold voltage of RX sensitivity 890 */ 891 if (chip->mac_ver != MAC_VER_8168) 892 rge_ephy_put16(rgep, 0x01, 0x1bd3); 893 894 val16 = rge_reg_get8(rgep, PHY_STATUS_REG); 895 val16 = 0x12<<8 | val16; 896 if (rgep->chipid.mac_ver != MAC_VER_8101E && 897 rgep->chipid.mac_ver != MAC_VER_8168B_C) { 898 rge_reg_put16(rgep, PHY_STATUS_REG, val16); 899 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00021c01); 900 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f088); 901 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00004000); 902 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f0b0); 903 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x0000f068); 904 val32 = rge_reg_get32(rgep, RT_CSI_DATA_REG); 905 val32 |= 0x7000; 906 val32 &= 0xffff5fff; 907 rge_reg_put32(rgep, RT_CSI_DATA_REG, val32); 908 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f068); 909 } 910 } 911 912 /* 913 * Config MII register 914 */ 915 rgep->param_link_up = LINK_STATE_DOWN; 916 rge_phy_update(rgep); 917 918 /* 919 * Enable Rx checksum offload. 920 * Then for vlan support, we must enable receive vlan de-tagging. 921 * Otherwise, there'll be checksum error. 922 */ 923 val16 = rge_reg_get16(rgep, CPLUS_COMMAND_REG); 924 val16 |= RX_CKSM_OFFLOAD | RX_VLAN_DETAG; 925 if (chip->mac_ver == MAC_VER_8169S_D) { 926 val16 |= CPLUS_BIT14 | MUL_PCI_RW_ENABLE; 927 rge_reg_put8(rgep, RESV_82_REG, 0x01); 928 } 929 rge_reg_put16(rgep, CPLUS_COMMAND_REG, val16 & (~0x03)); 930 931 /* 932 * Start transmit/receive before set tx/rx configuration register 933 */ 934 if (!chip->is_pcie) 935 rge_reg_set8(rgep, RT_COMMAND_REG, 936 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 937 938 /* 939 * Set dump tally counter register 940 */ 941 val32 = rgep->dma_area_stats.cookie.dmac_laddress >> 32; 942 rge_reg_put32(rgep, DUMP_COUNTER_REG_1, val32); 943 val32 = rge_reg_get32(rgep, DUMP_COUNTER_REG_0); 944 val32 &= DUMP_COUNTER_REG_RESV; 945 val32 |= rgep->dma_area_stats.cookie.dmac_laddress; 946 rge_reg_put32(rgep, DUMP_COUNTER_REG_0, val32); 947 948 /* 949 * Change to config register write enable mode 950 */ 951 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 952 953 /* 954 * Set Tx/Rx maximum packet size 955 */ 956 if (rgep->default_mtu > ETHERMTU) { 957 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_JUMBO); 958 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_JUMBO); 959 } else if (rgep->chipid.mac_ver != MAC_VER_8101E) { 960 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD); 961 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD); 962 } else { 963 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD_8101E); 964 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD_8101E); 965 } 966 967 /* 968 * Set receive configuration register 969 */ 970 val32 = rge_reg_get32(rgep, RX_CONFIG_REG); 971 val32 &= RX_CONFIG_REG_RESV; 972 if (rgep->promisc) 973 val32 |= RX_ACCEPT_ALL_PKT; 974 rge_reg_put32(rgep, RX_CONFIG_REG, val32 | chip->rxconfig); 975 976 /* 977 * Set transmit configuration register 978 */ 979 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 980 val32 &= TX_CONFIG_REG_RESV; 981 rge_reg_put32(rgep, TX_CONFIG_REG, val32 | chip->txconfig); 982 983 /* 984 * Set Tx/Rx descriptor register 985 */ 986 val32 = rgep->tx_desc.cookie.dmac_laddress; 987 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_LO_REG, val32); 988 val32 = rgep->tx_desc.cookie.dmac_laddress >> 32; 989 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_HI_REG, val32); 990 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_LO_REG, 0); 991 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_HI_REG, 0); 992 val32 = rgep->rx_desc.cookie.dmac_laddress; 993 rge_reg_put32(rgep, RX_RING_ADDR_LO_REG, val32); 994 val32 = rgep->rx_desc.cookie.dmac_laddress >> 32; 995 rge_reg_put32(rgep, RX_RING_ADDR_HI_REG, val32); 996 997 /* 998 * Suggested setting from Realtek 999 */ 1000 if (rgep->chipid.mac_ver != MAC_VER_8101E) 1001 rge_reg_put16(rgep, RESV_E2_REG, 0x282a); 1002 else 1003 rge_reg_put16(rgep, RESV_E2_REG, 0x0000); 1004 1005 /* 1006 * Set multicast register 1007 */ 1008 hashp = (uint32_t *)rgep->mcast_hash; 1009 rge_reg_put32(rgep, MULTICAST_0_REG, hashp[0]); 1010 rge_reg_put32(rgep, MULTICAST_4_REG, hashp[1]); 1011 1012 /* 1013 * Msic register setting: 1014 * -- Missed packet counter: clear it 1015 * -- TimerInt Register 1016 * -- Timer count register 1017 */ 1018 rge_reg_put32(rgep, RX_PKT_MISS_COUNT_REG, 0); 1019 rge_reg_put32(rgep, TIMER_INT_REG, TIMER_INT_NONE); 1020 rge_reg_put32(rgep, TIMER_COUNT_REG, 0); 1021 1022 /* 1023 * Return to normal network/host communication mode 1024 */ 1025 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1026 drv_usecwait(20); 1027 } 1028 1029 /* 1030 * rge_chip_start() -- start the chip transmitting and/or receiving, 1031 * including enabling interrupts 1032 */ 1033 void rge_chip_start(rge_t *rgep); 1034 #pragma no_inline(rge_chip_start) 1035 1036 void 1037 rge_chip_start(rge_t *rgep) 1038 { 1039 /* 1040 * Clear statistics 1041 */ 1042 bzero(&rgep->stats, sizeof (rge_stats_t)); 1043 DMA_ZERO(rgep->dma_area_stats); 1044 1045 /* 1046 * Start transmit/receive 1047 */ 1048 rge_reg_set8(rgep, RT_COMMAND_REG, 1049 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1050 1051 /* 1052 * Enable interrupt 1053 */ 1054 rgep->int_mask = RGE_INT_MASK; 1055 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1056 1057 /* 1058 * All done! 1059 */ 1060 rgep->rge_chip_state = RGE_CHIP_RUNNING; 1061 } 1062 1063 /* 1064 * rge_chip_stop() -- stop board receiving 1065 */ 1066 void rge_chip_stop(rge_t *rgep, boolean_t fault); 1067 #pragma no_inline(rge_chip_stop) 1068 1069 void 1070 rge_chip_stop(rge_t *rgep, boolean_t fault) 1071 { 1072 /* 1073 * Disable interrupt 1074 */ 1075 rgep->int_mask = INT_MASK_NONE; 1076 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1077 1078 /* 1079 * Clear pended interrupt 1080 */ 1081 if (!rgep->suspended) { 1082 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 1083 } 1084 1085 /* 1086 * Stop the board and disable transmit/receive 1087 */ 1088 rge_reg_clr8(rgep, RT_COMMAND_REG, 1089 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1090 1091 if (fault) 1092 rgep->rge_chip_state = RGE_CHIP_FAULT; 1093 else 1094 rgep->rge_chip_state = RGE_CHIP_STOPPED; 1095 } 1096 1097 /* 1098 * rge_get_mac_addr() -- get the MAC address on NIC 1099 */ 1100 static void rge_get_mac_addr(rge_t *rgep); 1101 #pragma inline(rge_get_mac_addr) 1102 1103 static void 1104 rge_get_mac_addr(rge_t *rgep) 1105 { 1106 uint8_t *macaddr = rgep->netaddr; 1107 uint32_t val32; 1108 1109 /* 1110 * Read first 4-byte of mac address 1111 */ 1112 val32 = rge_reg_get32(rgep, ID_0_REG); 1113 macaddr[0] = val32 & 0xff; 1114 val32 = val32 >> 8; 1115 macaddr[1] = val32 & 0xff; 1116 val32 = val32 >> 8; 1117 macaddr[2] = val32 & 0xff; 1118 val32 = val32 >> 8; 1119 macaddr[3] = val32 & 0xff; 1120 1121 /* 1122 * Read last 2-byte of mac address 1123 */ 1124 val32 = rge_reg_get32(rgep, ID_4_REG); 1125 macaddr[4] = val32 & 0xff; 1126 val32 = val32 >> 8; 1127 macaddr[5] = val32 & 0xff; 1128 } 1129 1130 static void rge_set_mac_addr(rge_t *rgep); 1131 #pragma inline(rge_set_mac_addr) 1132 1133 static void 1134 rge_set_mac_addr(rge_t *rgep) 1135 { 1136 uint8_t *p = rgep->netaddr; 1137 uint32_t val32; 1138 1139 /* 1140 * Change to config register write enable mode 1141 */ 1142 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1143 1144 /* 1145 * Get first 4 bytes of mac address 1146 */ 1147 val32 = p[3]; 1148 val32 = val32 << 8; 1149 val32 |= p[2]; 1150 val32 = val32 << 8; 1151 val32 |= p[1]; 1152 val32 = val32 << 8; 1153 val32 |= p[0]; 1154 1155 /* 1156 * Set first 4 bytes of mac address 1157 */ 1158 rge_reg_put32(rgep, ID_0_REG, val32); 1159 1160 /* 1161 * Get last 2 bytes of mac address 1162 */ 1163 val32 = p[5]; 1164 val32 = val32 << 8; 1165 val32 |= p[4]; 1166 1167 /* 1168 * Set last 2 bytes of mac address 1169 */ 1170 val32 |= rge_reg_get32(rgep, ID_4_REG) & ~0xffff; 1171 rge_reg_put32(rgep, ID_4_REG, val32); 1172 1173 /* 1174 * Return to normal network/host communication mode 1175 */ 1176 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1177 } 1178 1179 static void rge_set_multi_addr(rge_t *rgep); 1180 #pragma inline(rge_set_multi_addr) 1181 1182 static void 1183 rge_set_multi_addr(rge_t *rgep) 1184 { 1185 uint32_t *hashp; 1186 1187 hashp = (uint32_t *)rgep->mcast_hash; 1188 1189 /* 1190 * Change to config register write enable mode 1191 */ 1192 if (rgep->chipid.mac_ver == MAC_VER_8169SC) 1193 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1194 1195 rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0])); 1196 rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1])); 1197 1198 /* 1199 * Return to normal network/host communication mode 1200 */ 1201 if (rgep->chipid.mac_ver == MAC_VER_8169SC) 1202 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1203 } 1204 1205 static void rge_set_promisc(rge_t *rgep); 1206 #pragma inline(rge_set_promisc) 1207 1208 static void 1209 rge_set_promisc(rge_t *rgep) 1210 { 1211 if (rgep->promisc) 1212 rge_reg_set32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1213 else 1214 rge_reg_clr32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1215 } 1216 1217 /* 1218 * rge_chip_sync() -- program the chip with the unicast MAC address, 1219 * the multicast hash table, the required level of promiscuity, and 1220 * the current loopback mode ... 1221 */ 1222 void rge_chip_sync(rge_t *rgep, enum rge_sync_op todo); 1223 #pragma no_inline(rge_chip_sync) 1224 1225 void 1226 rge_chip_sync(rge_t *rgep, enum rge_sync_op todo) 1227 { 1228 switch (todo) { 1229 case RGE_GET_MAC: 1230 rge_get_mac_addr(rgep); 1231 break; 1232 case RGE_SET_MAC: 1233 /* Reprogram the unicast MAC address(es) ... */ 1234 rge_set_mac_addr(rgep); 1235 break; 1236 case RGE_SET_MUL: 1237 /* Reprogram the hashed multicast address table ... */ 1238 rge_set_multi_addr(rgep); 1239 break; 1240 case RGE_SET_PROMISC: 1241 /* Set or clear the PROMISCUOUS mode bit */ 1242 rge_set_promisc(rgep); 1243 break; 1244 default: 1245 break; 1246 } 1247 } 1248 1249 void rge_chip_blank(void *arg, time_t ticks, uint_t count); 1250 #pragma no_inline(rge_chip_blank) 1251 1252 void 1253 rge_chip_blank(void *arg, time_t ticks, uint_t count) 1254 { 1255 _NOTE(ARGUNUSED(arg, ticks, count)); 1256 } 1257 1258 void rge_tx_trigger(rge_t *rgep); 1259 #pragma no_inline(rge_tx_trigger) 1260 1261 void 1262 rge_tx_trigger(rge_t *rgep) 1263 { 1264 rge_reg_set8(rgep, TX_RINGS_POLL_REG, NORMAL_TX_RING_POLL); 1265 } 1266 1267 void rge_hw_stats_dump(rge_t *rgep); 1268 #pragma no_inline(rge_tx_trigger) 1269 1270 void 1271 rge_hw_stats_dump(rge_t *rgep) 1272 { 1273 int i = 0; 1274 1275 while (rge_reg_get32(rgep, DUMP_COUNTER_REG_0) & DUMP_START) { 1276 drv_usecwait(100); 1277 if (++i > STATS_DUMP_LOOP) { 1278 RGE_DEBUG(("rge h/w statistics dump fail!")); 1279 rgep->rge_chip_state = RGE_CHIP_ERROR; 1280 return; 1281 } 1282 } 1283 DMA_SYNC(rgep->dma_area_stats, DDI_DMA_SYNC_FORKERNEL); 1284 1285 /* 1286 * Start H/W statistics dump for RTL8169 chip 1287 */ 1288 rge_reg_set32(rgep, DUMP_COUNTER_REG_0, DUMP_START); 1289 } 1290 1291 /* 1292 * ========== Hardware interrupt handler ========== 1293 */ 1294 1295 #undef RGE_DBG 1296 #define RGE_DBG RGE_DBG_INT /* debug flag for this code */ 1297 1298 static void rge_wake_factotum(rge_t *rgep); 1299 #pragma inline(rge_wake_factotum) 1300 1301 static void 1302 rge_wake_factotum(rge_t *rgep) 1303 { 1304 if (rgep->factotum_flag == 0) { 1305 rgep->factotum_flag = 1; 1306 (void) ddi_intr_trigger_softint(rgep->factotum_hdl, NULL); 1307 } 1308 } 1309 1310 /* 1311 * rge_intr() -- handle chip interrupts 1312 */ 1313 uint_t rge_intr(caddr_t arg1, caddr_t arg2); 1314 #pragma no_inline(rge_intr) 1315 1316 uint_t 1317 rge_intr(caddr_t arg1, caddr_t arg2) 1318 { 1319 rge_t *rgep = (rge_t *)arg1; 1320 uint16_t int_status; 1321 1322 _NOTE(ARGUNUSED(arg2)) 1323 1324 mutex_enter(rgep->genlock); 1325 1326 if (rgep->suspended) { 1327 mutex_exit(rgep->genlock); 1328 return (DDI_INTR_UNCLAIMED); 1329 } 1330 1331 /* 1332 * Was this interrupt caused by our device... 1333 */ 1334 int_status = rge_reg_get16(rgep, INT_STATUS_REG); 1335 if (!(int_status & rgep->int_mask)) { 1336 mutex_exit(rgep->genlock); 1337 return (DDI_INTR_UNCLAIMED); 1338 /* indicate it wasn't our interrupt */ 1339 } 1340 rgep->stats.intr++; 1341 1342 /* 1343 * Clear interrupt 1344 * For PCIE chipset, we need disable interrupt first. 1345 */ 1346 if (rgep->chipid.is_pcie) 1347 rge_reg_put16(rgep, INT_MASK_REG, INT_MASK_NONE); 1348 rge_reg_put16(rgep, INT_STATUS_REG, int_status); 1349 1350 /* 1351 * Cable link change interrupt 1352 */ 1353 if (int_status & LINK_CHANGE_INT) { 1354 rge_chip_cyclic(rgep); 1355 } 1356 1357 mutex_exit(rgep->genlock); 1358 1359 /* 1360 * Receive interrupt 1361 */ 1362 if (int_status & RGE_RX_INT) 1363 rge_receive(rgep); 1364 1365 /* 1366 * Re-enable interrupt for PCIE chipset 1367 */ 1368 if (rgep->chipid.is_pcie) 1369 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1370 1371 return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */ 1372 } 1373 1374 /* 1375 * ========== Factotum, implemented as a softint handler ========== 1376 */ 1377 1378 #undef RGE_DBG 1379 #define RGE_DBG RGE_DBG_FACT /* debug flag for this code */ 1380 1381 static boolean_t rge_factotum_link_check(rge_t *rgep); 1382 #pragma no_inline(rge_factotum_link_check) 1383 1384 static boolean_t 1385 rge_factotum_link_check(rge_t *rgep) 1386 { 1387 uint8_t media_status; 1388 int32_t link; 1389 1390 media_status = rge_reg_get8(rgep, PHY_STATUS_REG); 1391 link = (media_status & PHY_STATUS_LINK_UP) ? 1392 LINK_STATE_UP : LINK_STATE_DOWN; 1393 if (rgep->param_link_up != link) { 1394 /* 1395 * Link change. 1396 */ 1397 rgep->param_link_up = link; 1398 1399 if (link == LINK_STATE_UP) { 1400 if (media_status & PHY_STATUS_1000MF) { 1401 rgep->param_link_speed = RGE_SPEED_1000M; 1402 rgep->param_link_duplex = LINK_DUPLEX_FULL; 1403 } else { 1404 rgep->param_link_speed = 1405 (media_status & PHY_STATUS_100M) ? 1406 RGE_SPEED_100M : RGE_SPEED_10M; 1407 rgep->param_link_duplex = 1408 (media_status & PHY_STATUS_DUPLEX_FULL) ? 1409 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF; 1410 } 1411 } 1412 return (B_TRUE); 1413 } 1414 return (B_FALSE); 1415 } 1416 1417 /* 1418 * Factotum routine to check for Tx stall, using the 'watchdog' counter 1419 */ 1420 static boolean_t rge_factotum_stall_check(rge_t *rgep); 1421 #pragma no_inline(rge_factotum_stall_check) 1422 1423 static boolean_t 1424 rge_factotum_stall_check(rge_t *rgep) 1425 { 1426 uint32_t dogval; 1427 1428 ASSERT(mutex_owned(rgep->genlock)); 1429 1430 /* 1431 * Specific check for Tx stall ... 1432 * 1433 * The 'watchdog' counter is incremented whenever a packet 1434 * is queued, reset to 1 when some (but not all) buffers 1435 * are reclaimed, reset to 0 (disabled) when all buffers 1436 * are reclaimed, and shifted left here. If it exceeds the 1437 * threshold value, the chip is assumed to have stalled and 1438 * is put into the ERROR state. The factotum will then reset 1439 * it on the next pass. 1440 * 1441 * All of which should ensure that we don't get into a state 1442 * where packets are left pending indefinitely! 1443 */ 1444 if (rgep->resched_needed) 1445 (void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL); 1446 dogval = rge_atomic_shl32(&rgep->watchdog, 1); 1447 if (dogval < rge_watchdog_count) 1448 return (B_FALSE); 1449 1450 RGE_REPORT((rgep, "Tx stall detected, watchdog code 0x%x", dogval)); 1451 return (B_TRUE); 1452 1453 } 1454 1455 /* 1456 * The factotum is woken up when there's something to do that we'd rather 1457 * not do from inside a hardware interrupt handler or high-level cyclic. 1458 * Its two main tasks are: 1459 * reset & restart the chip after an error 1460 * check the link status whenever necessary 1461 */ 1462 uint_t rge_chip_factotum(caddr_t arg1, caddr_t arg2); 1463 #pragma no_inline(rge_chip_factotum) 1464 1465 uint_t 1466 rge_chip_factotum(caddr_t arg1, caddr_t arg2) 1467 { 1468 rge_t *rgep; 1469 uint_t result; 1470 boolean_t error; 1471 boolean_t linkchg; 1472 1473 rgep = (rge_t *)arg1; 1474 _NOTE(ARGUNUSED(arg2)) 1475 1476 if (rgep->factotum_flag == 0) 1477 return (DDI_INTR_UNCLAIMED); 1478 1479 rgep->factotum_flag = 0; 1480 result = DDI_INTR_CLAIMED; 1481 error = B_FALSE; 1482 linkchg = B_FALSE; 1483 1484 mutex_enter(rgep->genlock); 1485 switch (rgep->rge_chip_state) { 1486 default: 1487 break; 1488 1489 case RGE_CHIP_RUNNING: 1490 linkchg = rge_factotum_link_check(rgep); 1491 error = rge_factotum_stall_check(rgep); 1492 break; 1493 1494 case RGE_CHIP_ERROR: 1495 error = B_TRUE; 1496 break; 1497 1498 case RGE_CHIP_FAULT: 1499 /* 1500 * Fault detected, time to reset ... 1501 */ 1502 if (rge_autorecover) { 1503 RGE_REPORT((rgep, "automatic recovery activated")); 1504 rge_restart(rgep); 1505 } 1506 break; 1507 } 1508 1509 /* 1510 * If an error is detected, stop the chip now, marking it as 1511 * faulty, so that it will be reset next time through ... 1512 */ 1513 if (error) 1514 rge_chip_stop(rgep, B_TRUE); 1515 mutex_exit(rgep->genlock); 1516 1517 /* 1518 * If the link state changed, tell the world about it. 1519 * Note: can't do this while still holding the mutex. 1520 */ 1521 if (linkchg) 1522 mac_link_update(rgep->mh, rgep->param_link_up); 1523 1524 return (result); 1525 } 1526 1527 /* 1528 * High-level cyclic handler 1529 * 1530 * This routine schedules a (low-level) softint callback to the 1531 * factotum, and prods the chip to update the status block (which 1532 * will cause a hardware interrupt when complete). 1533 */ 1534 void rge_chip_cyclic(void *arg); 1535 #pragma no_inline(rge_chip_cyclic) 1536 1537 void 1538 rge_chip_cyclic(void *arg) 1539 { 1540 rge_t *rgep; 1541 1542 rgep = arg; 1543 1544 switch (rgep->rge_chip_state) { 1545 default: 1546 return; 1547 1548 case RGE_CHIP_RUNNING: 1549 rge_phy_check(rgep); 1550 break; 1551 1552 case RGE_CHIP_FAULT: 1553 case RGE_CHIP_ERROR: 1554 break; 1555 } 1556 1557 rge_wake_factotum(rgep); 1558 } 1559 1560 1561 /* 1562 * ========== Ioctl subfunctions ========== 1563 */ 1564 1565 #undef RGE_DBG 1566 #define RGE_DBG RGE_DBG_PPIO /* debug flag for this code */ 1567 1568 #if RGE_DEBUGGING || RGE_DO_PPIO 1569 1570 static void rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1571 #pragma no_inline(rge_chip_peek_cfg) 1572 1573 static void 1574 rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1575 { 1576 uint64_t regval; 1577 uint64_t regno; 1578 1579 RGE_TRACE(("rge_chip_peek_cfg($%p, $%p)", 1580 (void *)rgep, (void *)ppd)); 1581 1582 regno = ppd->pp_acc_offset; 1583 1584 switch (ppd->pp_acc_size) { 1585 case 1: 1586 regval = pci_config_get8(rgep->cfg_handle, regno); 1587 break; 1588 1589 case 2: 1590 regval = pci_config_get16(rgep->cfg_handle, regno); 1591 break; 1592 1593 case 4: 1594 regval = pci_config_get32(rgep->cfg_handle, regno); 1595 break; 1596 1597 case 8: 1598 regval = pci_config_get64(rgep->cfg_handle, regno); 1599 break; 1600 } 1601 1602 ppd->pp_acc_data = regval; 1603 } 1604 1605 static void rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1606 #pragma no_inline(rge_chip_poke_cfg) 1607 1608 static void 1609 rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1610 { 1611 uint64_t regval; 1612 uint64_t regno; 1613 1614 RGE_TRACE(("rge_chip_poke_cfg($%p, $%p)", 1615 (void *)rgep, (void *)ppd)); 1616 1617 regno = ppd->pp_acc_offset; 1618 regval = ppd->pp_acc_data; 1619 1620 switch (ppd->pp_acc_size) { 1621 case 1: 1622 pci_config_put8(rgep->cfg_handle, regno, regval); 1623 break; 1624 1625 case 2: 1626 pci_config_put16(rgep->cfg_handle, regno, regval); 1627 break; 1628 1629 case 4: 1630 pci_config_put32(rgep->cfg_handle, regno, regval); 1631 break; 1632 1633 case 8: 1634 pci_config_put64(rgep->cfg_handle, regno, regval); 1635 break; 1636 } 1637 } 1638 1639 static void rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1640 #pragma no_inline(rge_chip_peek_reg) 1641 1642 static void 1643 rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1644 { 1645 uint64_t regval; 1646 void *regaddr; 1647 1648 RGE_TRACE(("rge_chip_peek_reg($%p, $%p)", 1649 (void *)rgep, (void *)ppd)); 1650 1651 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1652 1653 switch (ppd->pp_acc_size) { 1654 case 1: 1655 regval = ddi_get8(rgep->io_handle, regaddr); 1656 break; 1657 1658 case 2: 1659 regval = ddi_get16(rgep->io_handle, regaddr); 1660 break; 1661 1662 case 4: 1663 regval = ddi_get32(rgep->io_handle, regaddr); 1664 break; 1665 1666 case 8: 1667 regval = ddi_get64(rgep->io_handle, regaddr); 1668 break; 1669 } 1670 1671 ppd->pp_acc_data = regval; 1672 } 1673 1674 static void rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1675 #pragma no_inline(rge_chip_peek_reg) 1676 1677 static void 1678 rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1679 { 1680 uint64_t regval; 1681 void *regaddr; 1682 1683 RGE_TRACE(("rge_chip_poke_reg($%p, $%p)", 1684 (void *)rgep, (void *)ppd)); 1685 1686 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1687 regval = ppd->pp_acc_data; 1688 1689 switch (ppd->pp_acc_size) { 1690 case 1: 1691 ddi_put8(rgep->io_handle, regaddr, regval); 1692 break; 1693 1694 case 2: 1695 ddi_put16(rgep->io_handle, regaddr, regval); 1696 break; 1697 1698 case 4: 1699 ddi_put32(rgep->io_handle, regaddr, regval); 1700 break; 1701 1702 case 8: 1703 ddi_put64(rgep->io_handle, regaddr, regval); 1704 break; 1705 } 1706 } 1707 1708 static void rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1709 #pragma no_inline(rge_chip_peek_mii) 1710 1711 static void 1712 rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1713 { 1714 RGE_TRACE(("rge_chip_peek_mii($%p, $%p)", 1715 (void *)rgep, (void *)ppd)); 1716 1717 ppd->pp_acc_data = rge_mii_get16(rgep, ppd->pp_acc_offset/2); 1718 } 1719 1720 static void rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1721 #pragma no_inline(rge_chip_poke_mii) 1722 1723 static void 1724 rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1725 { 1726 RGE_TRACE(("rge_chip_poke_mii($%p, $%p)", 1727 (void *)rgep, (void *)ppd)); 1728 1729 rge_mii_put16(rgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 1730 } 1731 1732 static void rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1733 #pragma no_inline(rge_chip_peek_mem) 1734 1735 static void 1736 rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1737 { 1738 uint64_t regval; 1739 void *vaddr; 1740 1741 RGE_TRACE(("rge_chip_peek_rge($%p, $%p)", 1742 (void *)rgep, (void *)ppd)); 1743 1744 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1745 1746 switch (ppd->pp_acc_size) { 1747 case 1: 1748 regval = *(uint8_t *)vaddr; 1749 break; 1750 1751 case 2: 1752 regval = *(uint16_t *)vaddr; 1753 break; 1754 1755 case 4: 1756 regval = *(uint32_t *)vaddr; 1757 break; 1758 1759 case 8: 1760 regval = *(uint64_t *)vaddr; 1761 break; 1762 } 1763 1764 RGE_DEBUG(("rge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 1765 (void *)rgep, (void *)ppd, regval, vaddr)); 1766 1767 ppd->pp_acc_data = regval; 1768 } 1769 1770 static void rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1771 #pragma no_inline(rge_chip_poke_mem) 1772 1773 static void 1774 rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1775 { 1776 uint64_t regval; 1777 void *vaddr; 1778 1779 RGE_TRACE(("rge_chip_poke_mem($%p, $%p)", 1780 (void *)rgep, (void *)ppd)); 1781 1782 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1783 regval = ppd->pp_acc_data; 1784 1785 RGE_DEBUG(("rge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 1786 (void *)rgep, (void *)ppd, regval, vaddr)); 1787 1788 switch (ppd->pp_acc_size) { 1789 case 1: 1790 *(uint8_t *)vaddr = (uint8_t)regval; 1791 break; 1792 1793 case 2: 1794 *(uint16_t *)vaddr = (uint16_t)regval; 1795 break; 1796 1797 case 4: 1798 *(uint32_t *)vaddr = (uint32_t)regval; 1799 break; 1800 1801 case 8: 1802 *(uint64_t *)vaddr = (uint64_t)regval; 1803 break; 1804 } 1805 } 1806 1807 static enum ioc_reply rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 1808 struct iocblk *iocp); 1809 #pragma no_inline(rge_pp_ioctl) 1810 1811 static enum ioc_reply 1812 rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 1813 { 1814 void (*ppfn)(rge_t *rgep, rge_peekpoke_t *ppd); 1815 rge_peekpoke_t *ppd; 1816 dma_area_t *areap; 1817 uint64_t sizemask; 1818 uint64_t mem_va; 1819 uint64_t maxoff; 1820 boolean_t peek; 1821 1822 switch (cmd) { 1823 default: 1824 /* NOTREACHED */ 1825 rge_error(rgep, "rge_pp_ioctl: invalid cmd 0x%x", cmd); 1826 return (IOC_INVAL); 1827 1828 case RGE_PEEK: 1829 peek = B_TRUE; 1830 break; 1831 1832 case RGE_POKE: 1833 peek = B_FALSE; 1834 break; 1835 } 1836 1837 /* 1838 * Validate format of ioctl 1839 */ 1840 if (iocp->ioc_count != sizeof (rge_peekpoke_t)) 1841 return (IOC_INVAL); 1842 if (mp->b_cont == NULL) 1843 return (IOC_INVAL); 1844 ppd = (rge_peekpoke_t *)mp->b_cont->b_rptr; 1845 1846 /* 1847 * Validate request parameters 1848 */ 1849 switch (ppd->pp_acc_space) { 1850 default: 1851 return (IOC_INVAL); 1852 1853 case RGE_PP_SPACE_CFG: 1854 /* 1855 * Config space 1856 */ 1857 sizemask = 8|4|2|1; 1858 mem_va = 0; 1859 maxoff = PCI_CONF_HDR_SIZE; 1860 ppfn = peek ? rge_chip_peek_cfg : rge_chip_poke_cfg; 1861 break; 1862 1863 case RGE_PP_SPACE_REG: 1864 /* 1865 * Memory-mapped I/O space 1866 */ 1867 sizemask = 8|4|2|1; 1868 mem_va = 0; 1869 maxoff = RGE_REGISTER_MAX; 1870 ppfn = peek ? rge_chip_peek_reg : rge_chip_poke_reg; 1871 break; 1872 1873 case RGE_PP_SPACE_MII: 1874 /* 1875 * PHY's MII registers 1876 * NB: all PHY registers are two bytes, but the 1877 * addresses increment in ones (word addressing). 1878 * So we scale the address here, then undo the 1879 * transformation inside the peek/poke functions. 1880 */ 1881 ppd->pp_acc_offset *= 2; 1882 sizemask = 2; 1883 mem_va = 0; 1884 maxoff = (MII_MAXREG+1)*2; 1885 ppfn = peek ? rge_chip_peek_mii : rge_chip_poke_mii; 1886 break; 1887 1888 case RGE_PP_SPACE_RGE: 1889 /* 1890 * RGE data structure! 1891 */ 1892 sizemask = 8|4|2|1; 1893 mem_va = (uintptr_t)rgep; 1894 maxoff = sizeof (*rgep); 1895 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 1896 break; 1897 1898 case RGE_PP_SPACE_STATISTICS: 1899 case RGE_PP_SPACE_TXDESC: 1900 case RGE_PP_SPACE_TXBUFF: 1901 case RGE_PP_SPACE_RXDESC: 1902 case RGE_PP_SPACE_RXBUFF: 1903 /* 1904 * Various DMA_AREAs 1905 */ 1906 switch (ppd->pp_acc_space) { 1907 case RGE_PP_SPACE_TXDESC: 1908 areap = &rgep->dma_area_txdesc; 1909 break; 1910 case RGE_PP_SPACE_RXDESC: 1911 areap = &rgep->dma_area_rxdesc; 1912 break; 1913 case RGE_PP_SPACE_STATISTICS: 1914 areap = &rgep->dma_area_stats; 1915 break; 1916 } 1917 1918 sizemask = 8|4|2|1; 1919 mem_va = (uintptr_t)areap->mem_va; 1920 maxoff = areap->alength; 1921 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 1922 break; 1923 } 1924 1925 switch (ppd->pp_acc_size) { 1926 default: 1927 return (IOC_INVAL); 1928 1929 case 8: 1930 case 4: 1931 case 2: 1932 case 1: 1933 if ((ppd->pp_acc_size & sizemask) == 0) 1934 return (IOC_INVAL); 1935 break; 1936 } 1937 1938 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 1939 return (IOC_INVAL); 1940 1941 if (ppd->pp_acc_offset >= maxoff) 1942 return (IOC_INVAL); 1943 1944 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 1945 return (IOC_INVAL); 1946 1947 /* 1948 * All OK - go do it! 1949 */ 1950 ppd->pp_acc_offset += mem_va; 1951 (*ppfn)(rgep, ppd); 1952 return (peek ? IOC_REPLY : IOC_ACK); 1953 } 1954 1955 static enum ioc_reply rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 1956 struct iocblk *iocp); 1957 #pragma no_inline(rge_diag_ioctl) 1958 1959 static enum ioc_reply 1960 rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 1961 { 1962 ASSERT(mutex_owned(rgep->genlock)); 1963 1964 switch (cmd) { 1965 default: 1966 /* NOTREACHED */ 1967 rge_error(rgep, "rge_diag_ioctl: invalid cmd 0x%x", cmd); 1968 return (IOC_INVAL); 1969 1970 case RGE_DIAG: 1971 /* 1972 * Currently a no-op 1973 */ 1974 return (IOC_ACK); 1975 1976 case RGE_PEEK: 1977 case RGE_POKE: 1978 return (rge_pp_ioctl(rgep, cmd, mp, iocp)); 1979 1980 case RGE_PHY_RESET: 1981 return (IOC_RESTART_ACK); 1982 1983 case RGE_SOFT_RESET: 1984 case RGE_HARD_RESET: 1985 /* 1986 * Reset and reinitialise the 570x hardware 1987 */ 1988 rge_restart(rgep); 1989 return (IOC_ACK); 1990 } 1991 1992 /* NOTREACHED */ 1993 } 1994 1995 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 1996 1997 static enum ioc_reply rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 1998 struct iocblk *iocp); 1999 #pragma no_inline(rge_mii_ioctl) 2000 2001 static enum ioc_reply 2002 rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 2003 { 2004 struct rge_mii_rw *miirwp; 2005 2006 /* 2007 * Validate format of ioctl 2008 */ 2009 if (iocp->ioc_count != sizeof (struct rge_mii_rw)) 2010 return (IOC_INVAL); 2011 if (mp->b_cont == NULL) 2012 return (IOC_INVAL); 2013 miirwp = (struct rge_mii_rw *)mp->b_cont->b_rptr; 2014 2015 /* 2016 * Validate request parameters ... 2017 */ 2018 if (miirwp->mii_reg > MII_MAXREG) 2019 return (IOC_INVAL); 2020 2021 switch (cmd) { 2022 default: 2023 /* NOTREACHED */ 2024 rge_error(rgep, "rge_mii_ioctl: invalid cmd 0x%x", cmd); 2025 return (IOC_INVAL); 2026 2027 case RGE_MII_READ: 2028 miirwp->mii_data = rge_mii_get16(rgep, miirwp->mii_reg); 2029 return (IOC_REPLY); 2030 2031 case RGE_MII_WRITE: 2032 rge_mii_put16(rgep, miirwp->mii_reg, miirwp->mii_data); 2033 return (IOC_ACK); 2034 } 2035 2036 /* NOTREACHED */ 2037 } 2038 2039 enum ioc_reply rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, 2040 struct iocblk *iocp); 2041 #pragma no_inline(rge_chip_ioctl) 2042 2043 enum ioc_reply 2044 rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 2045 { 2046 int cmd; 2047 2048 RGE_TRACE(("rge_chip_ioctl($%p, $%p, $%p, $%p)", 2049 (void *)rgep, (void *)wq, (void *)mp, (void *)iocp)); 2050 2051 ASSERT(mutex_owned(rgep->genlock)); 2052 2053 cmd = iocp->ioc_cmd; 2054 switch (cmd) { 2055 default: 2056 /* NOTREACHED */ 2057 rge_error(rgep, "rge_chip_ioctl: invalid cmd 0x%x", cmd); 2058 return (IOC_INVAL); 2059 2060 case RGE_DIAG: 2061 case RGE_PEEK: 2062 case RGE_POKE: 2063 case RGE_PHY_RESET: 2064 case RGE_SOFT_RESET: 2065 case RGE_HARD_RESET: 2066 #if RGE_DEBUGGING || RGE_DO_PPIO 2067 return (rge_diag_ioctl(rgep, cmd, mp, iocp)); 2068 #else 2069 return (IOC_INVAL); 2070 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 2071 2072 case RGE_MII_READ: 2073 case RGE_MII_WRITE: 2074 return (rge_mii_ioctl(rgep, cmd, mp, iocp)); 2075 2076 } 2077 2078 /* NOTREACHED */ 2079 } 2080