1 /* 2 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2005, 2006 8 * Damien Bergamini <damien.bergamini@free.fr> 9 * 10 * Permission to use, copy, modify, and distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23 /* 24 * Ralink Technology RT2560 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28 #include <sys/types.h> 29 #include <sys/byteorder.h> 30 #include <sys/conf.h> 31 #include <sys/cmn_err.h> 32 #include <sys/stat.h> 33 #include <sys/ddi.h> 34 #include <sys/sunddi.h> 35 #include <sys/strsubr.h> 36 #include <sys/ethernet.h> 37 #include <inet/common.h> 38 #include <inet/nd.h> 39 #include <inet/mi.h> 40 #include <sys/note.h> 41 #include <sys/stream.h> 42 #include <sys/strsun.h> 43 #include <sys/modctl.h> 44 #include <sys/devops.h> 45 #include <sys/dlpi.h> 46 #include <sys/mac.h> 47 #include <sys/mac_wifi.h> 48 #include <sys/net80211.h> 49 #include <sys/net80211_proto.h> 50 #include <sys/varargs.h> 51 #include <sys/policy.h> 52 #include <sys/pci.h> 53 #include <sys/crypto/common.h> 54 #include <sys/crypto/api.h> 55 #include <inet/wifi_ioctl.h> 56 57 #include "ral_rate.h" 58 #include "rt2560_reg.h" 59 #include "rt2560_var.h" 60 61 62 static void *ral_soft_state_p = NULL; 63 64 #define RAL_TXBUF_SIZE (IEEE80211_MAX_LEN) 65 #define RAL_RXBUF_SIZE (IEEE80211_MAX_LEN) 66 67 /* quickly determine if a given rate is CCK or OFDM */ 68 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 69 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 70 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 71 #define RAL_SIFS 10 /* us */ 72 #define RT2560_TXRX_TURNAROUND 10 /* us */ 73 74 /* 75 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 76 */ 77 static const struct ieee80211_rateset rt2560_rateset_11a = 78 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 79 80 static const struct ieee80211_rateset rt2560_rateset_11b = 81 { 4, { 2, 4, 11, 22 } }; 82 83 static const struct ieee80211_rateset rt2560_rateset_11g = 84 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 85 86 static const struct { 87 uint32_t reg; 88 uint32_t val; 89 } rt2560_def_mac[] = { 90 RT2560_DEF_MAC 91 }; 92 93 static const struct { 94 uint8_t reg; 95 uint8_t val; 96 } rt2560_def_bbp[] = { 97 RT2560_DEF_BBP 98 }; 99 100 static const uint32_t rt2560_rf2522_r2[] = RT2560_RF2522_R2; 101 static const uint32_t rt2560_rf2523_r2[] = RT2560_RF2523_R2; 102 static const uint32_t rt2560_rf2524_r2[] = RT2560_RF2524_R2; 103 static const uint32_t rt2560_rf2525_r2[] = RT2560_RF2525_R2; 104 static const uint32_t rt2560_rf2525_hi_r2[] = RT2560_RF2525_HI_R2; 105 static const uint32_t rt2560_rf2525e_r2[] = RT2560_RF2525E_R2; 106 static const uint32_t rt2560_rf2526_r2[] = RT2560_RF2526_R2; 107 static const uint32_t rt2560_rf2526_hi_r2[] = RT2560_RF2526_HI_R2; 108 109 static const struct { 110 uint8_t chan; 111 uint32_t r1, r2, r4; 112 } rt2560_rf5222[] = { 113 RT2560_RF5222 114 }; 115 116 /* 117 * PIO access attributes for registers 118 */ 119 static ddi_device_acc_attr_t ral_csr_accattr = { 120 DDI_DEVICE_ATTR_V0, 121 DDI_STRUCTURE_LE_ACC, 122 DDI_STRICTORDER_ACC 123 }; 124 125 /* 126 * DMA access attributes for descriptors: NOT to be byte swapped. 127 */ 128 static ddi_device_acc_attr_t ral_desc_accattr = { 129 DDI_DEVICE_ATTR_V0, 130 DDI_STRUCTURE_LE_ACC, 131 DDI_STRICTORDER_ACC 132 }; 133 134 /* 135 * Describes the chip's DMA engine 136 */ 137 static ddi_dma_attr_t ral_dma_attr = { 138 DMA_ATTR_V0, /* dma_attr version */ 139 0x0000000000000000ull, /* dma_attr_addr_lo */ 140 0xFFFFFFFF, /* dma_attr_addr_hi */ 141 0x00000000FFFFFFFFull, /* dma_attr_count_max */ 142 0x0000000000000001ull, /* dma_attr_align */ 143 0x00000FFF, /* dma_attr_burstsizes */ 144 0x00000001, /* dma_attr_minxfer */ 145 0x000000000000FFFFull, /* dma_attr_maxxfer */ 146 0xFFFFFFFFFFFFFFFFull, /* dma_attr_seg */ 147 1, /* dma_attr_sgllen */ 148 0x00000001, /* dma_attr_granular */ 149 0 /* dma_attr_flags */ 150 }; 151 152 /* 153 * device operations 154 */ 155 static int rt2560_attach(dev_info_t *, ddi_attach_cmd_t); 156 static int rt2560_detach(dev_info_t *, ddi_detach_cmd_t); 157 static int32_t rt2560_quiesce(dev_info_t *); 158 159 /* 160 * Module Loading Data & Entry Points 161 */ 162 DDI_DEFINE_STREAM_OPS(ral_dev_ops, nulldev, nulldev, rt2560_attach, 163 rt2560_detach, nodev, NULL, D_MP, NULL, rt2560_quiesce); 164 165 static struct modldrv ral_modldrv = { 166 &mod_driverops, /* Type of module. This one is a driver */ 167 "Ralink RT2500 driver v1.5", /* short description */ 168 &ral_dev_ops /* driver specific ops */ 169 }; 170 171 static struct modlinkage modlinkage = { 172 MODREV_1, 173 (void *)&ral_modldrv, 174 NULL 175 }; 176 177 static int rt2560_m_stat(void *, uint_t, uint64_t *); 178 static int rt2560_m_start(void *); 179 static void rt2560_m_stop(void *); 180 static int rt2560_m_promisc(void *, boolean_t); 181 static int rt2560_m_multicst(void *, boolean_t, const uint8_t *); 182 static int rt2560_m_unicst(void *, const uint8_t *); 183 static mblk_t *rt2560_m_tx(void *, mblk_t *); 184 static void rt2560_m_ioctl(void *, queue_t *, mblk_t *); 185 static int rt2560_m_setprop(void *, const char *, mac_prop_id_t, 186 uint_t, const void *); 187 static int rt2560_m_getprop(void *, const char *, mac_prop_id_t, 188 uint_t, uint_t, void *, uint_t *); 189 190 static mac_callbacks_t rt2560_m_callbacks = { 191 MC_IOCTL | MC_SETPROP | MC_GETPROP, 192 rt2560_m_stat, 193 rt2560_m_start, 194 rt2560_m_stop, 195 rt2560_m_promisc, 196 rt2560_m_multicst, 197 rt2560_m_unicst, 198 rt2560_m_tx, 199 NULL, /* mc_resources; */ 200 rt2560_m_ioctl, 201 NULL, /* mc_getcapab */ 202 NULL, 203 NULL, 204 rt2560_m_setprop, 205 rt2560_m_getprop 206 }; 207 208 uint32_t ral_dbg_flags = 0; 209 210 void 211 ral_debug(uint32_t dbg_flags, const int8_t *fmt, ...) 212 { 213 va_list args; 214 215 if (dbg_flags & ral_dbg_flags) { 216 va_start(args, fmt); 217 vcmn_err(CE_CONT, fmt, args); 218 va_end(args); 219 } 220 } 221 222 static void 223 rt2560_set_basicrates(struct rt2560_softc *sc) 224 { 225 struct ieee80211com *ic = &sc->sc_ic; 226 227 /* update basic rate set */ 228 if (ic->ic_curmode == IEEE80211_MODE_11B) { 229 /* 11b basic rates: 1, 2Mbps */ 230 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x3); 231 } else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) { 232 /* 11a basic rates: 6, 12, 24Mbps */ 233 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x150); 234 } else { 235 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 236 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x15f); 237 } 238 } 239 240 static void 241 rt2560_update_led(struct rt2560_softc *sc, int led1, int led2) 242 { 243 uint32_t tmp; 244 245 /* set ON period to 70ms and OFF period to 30ms */ 246 tmp = led1 << 16 | led2 << 17 | 70 << 8 | 30; 247 RAL_WRITE(sc, RT2560_LEDCSR, tmp); 248 } 249 250 static void 251 rt2560_set_bssid(struct rt2560_softc *sc, uint8_t *bssid) 252 { 253 uint32_t tmp; 254 255 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 256 RAL_WRITE(sc, RT2560_CSR5, tmp); 257 258 tmp = bssid[4] | bssid[5] << 8; 259 RAL_WRITE(sc, RT2560_CSR6, tmp); 260 261 RAL_DEBUG(RAL_DBG_HW, "setting BSSID to " MACSTR "\n", MAC2STR(bssid)); 262 } 263 264 265 static void 266 rt2560_bbp_write(struct rt2560_softc *sc, uint8_t reg, uint8_t val) 267 { 268 uint32_t tmp; 269 int ntries; 270 271 for (ntries = 0; ntries < 100; ntries++) { 272 if (!(RAL_READ(sc, RT2560_BBPCSR) & RT2560_BBP_BUSY)) 273 break; 274 drv_usecwait(1); 275 } 276 if (ntries == 100) { 277 RAL_DEBUG(RAL_DBG_HW, "could not write to BBP\n"); 278 return; 279 } 280 281 tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val; 282 RAL_WRITE(sc, RT2560_BBPCSR, tmp); 283 284 RAL_DEBUG(RAL_DBG_HW, "BBP R%u <- 0x%02x\n", reg, val); 285 } 286 287 static uint8_t 288 rt2560_bbp_read(struct rt2560_softc *sc, uint8_t reg) 289 { 290 uint32_t val; 291 int ntries; 292 293 val = RT2560_BBP_BUSY | reg << 8; 294 RAL_WRITE(sc, RT2560_BBPCSR, val); 295 296 for (ntries = 0; ntries < 100; ntries++) { 297 val = RAL_READ(sc, RT2560_BBPCSR); 298 if (!(val & RT2560_BBP_BUSY)) 299 return (val & 0xff); 300 drv_usecwait(1); 301 } 302 303 RAL_DEBUG(RAL_DBG_HW, "could not read from BBP\n"); 304 return (0); 305 } 306 307 static void 308 rt2560_rf_write(struct rt2560_softc *sc, uint8_t reg, uint32_t val) 309 { 310 uint32_t tmp; 311 int ntries; 312 313 for (ntries = 0; ntries < 100; ntries++) { 314 if (!(RAL_READ(sc, RT2560_RFCSR) & RT2560_RF_BUSY)) 315 break; 316 drv_usecwait(1); 317 } 318 if (ntries == 100) { 319 RAL_DEBUG(RAL_DBG_HW, "could not write to RF\n"); 320 return; 321 } 322 323 tmp = RT2560_RF_BUSY | RT2560_RF_20BIT | (val & 0xfffff) << 2 | 324 (reg & 0x3); 325 RAL_WRITE(sc, RT2560_RFCSR, tmp); 326 327 /* remember last written value in sc */ 328 sc->rf_regs[reg] = val; 329 330 RAL_DEBUG(RAL_DBG_HW, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff); 331 } 332 333 static void 334 rt2560_set_chan(struct rt2560_softc *sc, struct ieee80211_channel *c) 335 { 336 struct ieee80211com *ic = &sc->sc_ic; 337 uint8_t power, tmp; 338 uint_t i, chan; 339 340 chan = ieee80211_chan2ieee(ic, c); 341 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 342 return; 343 344 if (IEEE80211_IS_CHAN_2GHZ(c)) 345 power = min(sc->txpow[chan - 1], 31); 346 else 347 power = 31; 348 349 /* adjust txpower using ifconfig settings */ 350 power -= (100 - ic->ic_txpowlimit) / 8; 351 352 RAL_DEBUG(RAL_DBG_CHAN, "setting channel to %u, txpower to %u\n", 353 chan, power); 354 355 switch (sc->rf_rev) { 356 case RT2560_RF_2522: 357 rt2560_rf_write(sc, RAL_RF1, 0x00814); 358 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2522_r2[chan - 1]); 359 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 360 break; 361 362 case RT2560_RF_2523: 363 rt2560_rf_write(sc, RAL_RF1, 0x08804); 364 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2523_r2[chan - 1]); 365 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x38044); 366 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 367 break; 368 369 case RT2560_RF_2524: 370 rt2560_rf_write(sc, RAL_RF1, 0x0c808); 371 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2524_r2[chan - 1]); 372 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 373 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 374 break; 375 376 case RT2560_RF_2525: 377 rt2560_rf_write(sc, RAL_RF1, 0x08808); 378 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2525_hi_r2[chan - 1]); 379 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 380 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 381 382 rt2560_rf_write(sc, RAL_RF1, 0x08808); 383 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2525_r2[chan - 1]); 384 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 385 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 386 break; 387 388 case RT2560_RF_2525E: 389 rt2560_rf_write(sc, RAL_RF1, 0x08808); 390 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2525e_r2[chan - 1]); 391 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 392 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); 393 break; 394 395 case RT2560_RF_2526: 396 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2526_hi_r2[chan - 1]); 397 rt2560_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 398 rt2560_rf_write(sc, RAL_RF1, 0x08804); 399 400 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2526_r2[chan - 1]); 401 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 402 rt2560_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 403 break; 404 405 /* dual-band RF */ 406 case RT2560_RF_5222: 407 for (i = 0; rt2560_rf5222[i].chan != chan; i++) { 408 } 409 410 rt2560_rf_write(sc, RAL_RF1, rt2560_rf5222[i].r1); 411 rt2560_rf_write(sc, RAL_RF2, rt2560_rf5222[i].r2); 412 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 413 rt2560_rf_write(sc, RAL_RF4, rt2560_rf5222[i].r4); 414 break; 415 } 416 417 if (ic->ic_state != IEEE80211_S_SCAN) { 418 /* set Japan filter bit for channel 14 */ 419 tmp = rt2560_bbp_read(sc, 70); 420 421 tmp &= ~RT2560_JAPAN_FILTER; 422 if (chan == 14) 423 tmp |= RT2560_JAPAN_FILTER; 424 425 rt2560_bbp_write(sc, 70, tmp); 426 427 /* clear CRC errors */ 428 (void) RAL_READ(sc, RT2560_CNT0); 429 } 430 } 431 432 /* 433 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF 434 * synchronization. 435 */ 436 static void 437 rt2560_enable_tsf_sync(struct rt2560_softc *sc) 438 { 439 struct ieee80211com *ic = &sc->sc_ic; 440 uint16_t logcwmin, preload; 441 uint32_t tmp; 442 443 /* first, disable TSF synchronization */ 444 RAL_WRITE(sc, RT2560_CSR14, 0); 445 446 tmp = 16 * ic->ic_bss->in_intval; 447 RAL_WRITE(sc, RT2560_CSR12, tmp); 448 449 RAL_WRITE(sc, RT2560_CSR13, 0); 450 451 logcwmin = 5; 452 preload = (ic->ic_opmode == IEEE80211_M_STA) ? 384 : 1024; 453 tmp = logcwmin << 16 | preload; 454 RAL_WRITE(sc, RT2560_BCNOCSR, tmp); 455 456 /* finally, enable TSF synchronization */ 457 tmp = RT2560_ENABLE_TSF | RT2560_ENABLE_TBCN; 458 if (ic->ic_opmode == IEEE80211_M_STA) 459 tmp |= RT2560_ENABLE_TSF_SYNC(1); 460 else 461 tmp |= RT2560_ENABLE_TSF_SYNC(2) | 462 RT2560_ENABLE_BEACON_GENERATOR; 463 RAL_WRITE(sc, RT2560_CSR14, tmp); 464 465 RAL_DEBUG(RAL_DBG_HW, "enabling TSF synchronization\n"); 466 } 467 468 static void 469 rt2560_update_plcp(struct rt2560_softc *sc) 470 { 471 struct ieee80211com *ic = &sc->sc_ic; 472 473 /* no short preamble for 1Mbps */ 474 RAL_WRITE(sc, RT2560_PLCP1MCSR, 0x00700400); 475 476 if (!(ic->ic_flags & IEEE80211_F_SHPREAMBLE)) { 477 /* values taken from the reference driver */ 478 RAL_WRITE(sc, RT2560_PLCP2MCSR, 0x00380401); 479 RAL_WRITE(sc, RT2560_PLCP5p5MCSR, 0x00150402); 480 RAL_WRITE(sc, RT2560_PLCP11MCSR, 0x000b8403); 481 } else { 482 /* same values as above or'ed 0x8 */ 483 RAL_WRITE(sc, RT2560_PLCP2MCSR, 0x00380409); 484 RAL_WRITE(sc, RT2560_PLCP5p5MCSR, 0x0015040a); 485 RAL_WRITE(sc, RT2560_PLCP11MCSR, 0x000b840b); 486 } 487 488 RAL_DEBUG(RAL_DBG_HW, "updating PLCP for %s preamble\n", 489 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) ? "short" : "long"); 490 } 491 492 /* 493 * This function can be called by ieee80211_set_shortslottime(). Refer to 494 * IEEE Std 802.11-1999 pp. 85 to know how these values are computed. 495 */ 496 void 497 rt2560_update_slot(struct ieee80211com *ic, int onoff) 498 { 499 struct rt2560_softc *sc = (struct rt2560_softc *)ic; 500 uint8_t slottime; 501 uint16_t tx_sifs, tx_pifs, tx_difs, eifs; 502 uint32_t tmp; 503 504 /* slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; */ 505 slottime = (onoff ? 9 : 20); 506 507 /* update the MAC slot boundaries */ 508 tx_sifs = RAL_SIFS - RT2560_TXRX_TURNAROUND; 509 tx_pifs = tx_sifs + slottime; 510 tx_difs = tx_sifs + 2 * slottime; 511 eifs = (ic->ic_curmode == IEEE80211_MODE_11B) ? 364 : 60; 512 513 tmp = RAL_READ(sc, RT2560_CSR11); 514 tmp = (tmp & ~0x1f00) | slottime << 8; 515 RAL_WRITE(sc, RT2560_CSR11, tmp); 516 517 tmp = tx_pifs << 16 | tx_sifs; 518 RAL_WRITE(sc, RT2560_CSR18, tmp); 519 520 tmp = eifs << 16 | tx_difs; 521 RAL_WRITE(sc, RT2560_CSR19, tmp); 522 523 RAL_DEBUG(RAL_DBG_HW, "setting slottime to %uus\n", slottime); 524 } 525 526 int 527 ral_dma_region_alloc(struct rt2560_softc *sc, struct dma_region *dr, 528 size_t size, uint_t alloc_flags, uint_t bind_flags) 529 { 530 dev_info_t *dip = sc->sc_dev; 531 int err; 532 533 RAL_DEBUG(RAL_DBG_DMA, "ral_dma_region_alloc() size=%u\n", size); 534 535 err = ddi_dma_alloc_handle(dip, &ral_dma_attr, DDI_DMA_SLEEP, NULL, 536 &dr->dr_hnd); 537 if (err != DDI_SUCCESS) 538 goto fail1; 539 540 err = ddi_dma_mem_alloc(dr->dr_hnd, size, &ral_desc_accattr, 541 alloc_flags, DDI_DMA_SLEEP, NULL, 542 &dr->dr_base, &dr->dr_size, &dr->dr_acc); 543 if (err != DDI_SUCCESS) 544 goto fail2; 545 546 err = ddi_dma_addr_bind_handle(dr->dr_hnd, NULL, 547 dr->dr_base, dr->dr_size, 548 bind_flags, DDI_DMA_SLEEP, NULL, &dr->dr_cookie, &dr->dr_ccnt); 549 if (err != DDI_SUCCESS) 550 goto fail3; 551 552 if (dr->dr_ccnt != 1) { 553 err = DDI_FAILURE; 554 goto fail4; 555 } 556 557 dr->dr_pbase = dr->dr_cookie.dmac_address; 558 RAL_DEBUG(RAL_DBG_DMA, "get physical-base=0x%08x\n", dr->dr_pbase); 559 560 return (DDI_SUCCESS); 561 562 fail4: 563 (void) ddi_dma_unbind_handle(dr->dr_hnd); 564 fail3: 565 ddi_dma_mem_free(&dr->dr_acc); 566 fail2: 567 ddi_dma_free_handle(&dr->dr_hnd); 568 fail1: 569 return (err); 570 } 571 572 /* ARGSUSED */ 573 void 574 ral_dma_region_free(struct rt2560_softc *sc, struct dma_region *dr) 575 { 576 (void) ddi_dma_unbind_handle(dr->dr_hnd); 577 ddi_dma_mem_free(&dr->dr_acc); 578 ddi_dma_free_handle(&dr->dr_hnd); 579 } 580 581 int 582 rt2560_alloc_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring, 583 int count) 584 { 585 int i, err; 586 int size; 587 588 ring->count = count; 589 ring->queued = 0; 590 ring->cur = ring->next = 0; 591 ring->cur_encrypt = ring->next_encrypt = 0; 592 593 ring->data = kmem_zalloc(count * (sizeof (struct rt2560_tx_data)), 594 KM_SLEEP); 595 ring->dr_txbuf = kmem_zalloc(count * (sizeof (struct dma_region)), 596 KM_SLEEP); 597 598 err = ral_dma_region_alloc(sc, &ring->dr_desc, 599 count * (sizeof (struct rt2560_tx_desc)), 600 DDI_DMA_CONSISTENT, DDI_DMA_RDWR | DDI_DMA_CONSISTENT); 601 602 if (err != DDI_SUCCESS) 603 goto fail1; 604 605 size = roundup(RAL_TXBUF_SIZE, sc->sc_cachelsz); 606 for (i = 0; i < count; i++) { 607 err = ral_dma_region_alloc(sc, &ring->dr_txbuf[i], size, 608 DDI_DMA_STREAMING, DDI_DMA_WRITE | DDI_DMA_STREAMING); 609 if (err != DDI_SUCCESS) { 610 while (i >= 0) { 611 ral_dma_region_free(sc, &ring->dr_txbuf[i]); 612 i--; 613 } 614 goto fail2; 615 } 616 } 617 618 ring->physaddr = LE_32(ring->dr_desc.dr_pbase); 619 ring->desc = (struct rt2560_tx_desc *)ring->dr_desc.dr_base; 620 621 for (i = 0; i < count; i++) { 622 ring->desc[i].physaddr = LE_32(ring->dr_txbuf[i].dr_pbase); 623 ring->data[i].buf = ring->dr_txbuf[i].dr_base; 624 } 625 626 return (DDI_SUCCESS); 627 fail2: 628 ral_dma_region_free(sc, &ring->dr_desc); 629 fail1: 630 return (err); 631 } 632 633 /* ARGSUSED */ 634 void 635 rt2560_reset_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring) 636 { 637 struct rt2560_tx_desc *desc; 638 struct rt2560_tx_data *data; 639 int i; 640 641 for (i = 0; i < ring->count; i++) { 642 desc = &ring->desc[i]; 643 data = &ring->data[i]; 644 645 if (data->ni != NULL) { 646 ieee80211_free_node(data->ni); 647 data->ni = NULL; 648 } 649 650 desc->flags = 0; 651 } 652 653 (void) ddi_dma_sync(ring->dr_desc.dr_hnd, 0, 654 ring->count * sizeof (struct rt2560_tx_desc), DDI_DMA_SYNC_FORDEV); 655 656 ring->queued = 0; 657 ring->cur = ring->next = 0; 658 ring->cur_encrypt = ring->next_encrypt = 0; 659 } 660 661 void 662 rt2560_free_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring) 663 { 664 struct rt2560_tx_data *data; 665 int i; 666 667 ral_dma_region_free(sc, &ring->dr_desc); 668 /* tx buf */ 669 for (i = 0; i < ring->count; i++) { 670 data = &ring->data[i]; 671 if (data->ni != NULL) { 672 ieee80211_free_node(data->ni); 673 data->ni = NULL; 674 } 675 676 ral_dma_region_free(sc, &ring->dr_txbuf[i]); 677 } 678 679 kmem_free(ring->data, ring->count * (sizeof (struct rt2560_tx_data))); 680 kmem_free(ring->dr_txbuf, ring->count * (sizeof (struct dma_region))); 681 } 682 683 void 684 rt2560_ring_hwsetup(struct rt2560_softc *sc) 685 { 686 uint32_t tmp; 687 688 /* setup tx rings */ 689 tmp = ((uint32_t)RT2560_PRIO_RING_COUNT << 24) | 690 RT2560_ATIM_RING_COUNT << 16 | 691 RT2560_TX_RING_COUNT << 8 | 692 RT2560_TX_DESC_SIZE; 693 694 /* rings must be initialized in this exact order */ 695 RAL_WRITE(sc, RT2560_TXCSR2, tmp); 696 RAL_WRITE(sc, RT2560_TXCSR3, sc->txq.physaddr); 697 RAL_WRITE(sc, RT2560_TXCSR5, sc->prioq.physaddr); 698 699 /* setup rx ring */ 700 tmp = RT2560_RX_RING_COUNT << 8 | RT2560_RX_DESC_SIZE; 701 702 RAL_WRITE(sc, RT2560_RXCSR1, tmp); 703 RAL_WRITE(sc, RT2560_RXCSR2, sc->rxq.physaddr); 704 } 705 706 int 707 rt2560_alloc_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring, 708 int count) 709 { 710 struct rt2560_rx_desc *desc; 711 struct rt2560_rx_data *data; 712 int i, err; 713 int size; 714 715 ring->count = count; 716 ring->cur = ring->next = 0; 717 ring->cur_decrypt = 0; 718 719 ring->data = kmem_zalloc(count * (sizeof (struct rt2560_rx_data)), 720 KM_SLEEP); 721 ring->dr_rxbuf = kmem_zalloc(count * (sizeof (struct dma_region)), 722 KM_SLEEP); 723 724 err = ral_dma_region_alloc(sc, &ring->dr_desc, 725 count * (sizeof (struct rt2560_rx_desc)), 726 DDI_DMA_CONSISTENT, DDI_DMA_RDWR | DDI_DMA_CONSISTENT); 727 728 if (err != DDI_SUCCESS) 729 goto fail1; 730 731 size = roundup(RAL_RXBUF_SIZE, sc->sc_cachelsz); 732 for (i = 0; i < count; i++) { 733 err = ral_dma_region_alloc(sc, &ring->dr_rxbuf[i], size, 734 DDI_DMA_STREAMING, DDI_DMA_READ | DDI_DMA_STREAMING); 735 if (err != DDI_SUCCESS) { 736 while (i >= 0) { 737 ral_dma_region_free(sc, &ring->dr_rxbuf[i]); 738 i--; 739 } 740 goto fail2; 741 } 742 } 743 744 ring->physaddr = ring->dr_desc.dr_pbase; 745 ring->desc = (struct rt2560_rx_desc *)ring->dr_desc.dr_base; 746 747 for (i = 0; i < count; i++) { 748 desc = &ring->desc[i]; 749 data = &ring->data[i]; 750 751 desc->physaddr = LE_32(ring->dr_rxbuf[i].dr_pbase); 752 desc->flags = LE_32(RT2560_RX_BUSY); 753 754 data->buf = ring->dr_rxbuf[i].dr_base; 755 } 756 757 return (DDI_SUCCESS); 758 fail2: 759 ral_dma_region_free(sc, &ring->dr_desc); 760 fail1: 761 return (err); 762 } 763 764 /* ARGSUSED */ 765 static void 766 rt2560_reset_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring) 767 { 768 int i; 769 770 for (i = 0; i < ring->count; i++) { 771 ring->desc[i].flags = LE_32(RT2560_RX_BUSY); 772 ring->data[i].drop = 0; 773 } 774 775 (void) ddi_dma_sync(ring->dr_desc.dr_hnd, 0, 776 ring->count * sizeof (struct rt2560_rx_desc), 777 DDI_DMA_SYNC_FORKERNEL); 778 779 ring->cur = ring->next = 0; 780 ring->cur_decrypt = 0; 781 } 782 783 static void 784 rt2560_free_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring) 785 { 786 int i; 787 788 ral_dma_region_free(sc, &ring->dr_desc); 789 /* rx buf */ 790 for (i = 0; i < ring->count; i++) 791 ral_dma_region_free(sc, &ring->dr_rxbuf[i]); 792 793 kmem_free(ring->data, ring->count * (sizeof (struct rt2560_rx_data))); 794 kmem_free(ring->dr_rxbuf, ring->count * (sizeof (struct dma_region))); 795 } 796 797 /* ARGSUSED */ 798 static struct ieee80211_node * 799 rt2560_node_alloc(ieee80211com_t *ic) 800 { 801 struct rt2560_node *rn; 802 803 rn = kmem_zalloc(sizeof (struct rt2560_node), KM_SLEEP); 804 return ((rn != NULL) ? &rn->ni : NULL); 805 } 806 807 static void 808 rt2560_node_free(struct ieee80211_node *in) 809 { 810 ieee80211com_t *ic = in->in_ic; 811 812 ic->ic_node_cleanup(in); 813 if (in->in_wpa_ie != NULL) 814 ieee80211_free(in->in_wpa_ie); 815 kmem_free(in, sizeof (struct rt2560_node)); 816 } 817 818 /* 819 * This function is called periodically (every 200ms) during scanning to 820 * switch from one channel to another. 821 */ 822 static void 823 rt2560_next_scan(void *arg) 824 { 825 struct rt2560_softc *sc = arg; 826 struct ieee80211com *ic = &sc->sc_ic; 827 828 if (ic->ic_state == IEEE80211_S_SCAN) 829 (void) ieee80211_next_scan(ic); 830 } 831 832 /* 833 * This function is called for each node present in the node station table. 834 */ 835 /* ARGSUSED */ 836 static void 837 rt2560_iter_func(void *arg, struct ieee80211_node *ni) 838 { 839 struct rt2560_node *rn = (struct rt2560_node *)ni; 840 841 ral_rssadapt_updatestats(&rn->rssadapt); 842 } 843 844 /* 845 * This function is called periodically (every 100ms) in RUN state to update 846 * the rate adaptation statistics. 847 */ 848 static void 849 rt2560_update_rssadapt(void *arg) 850 { 851 struct rt2560_softc *sc = arg; 852 struct ieee80211com *ic = &sc->sc_ic; 853 854 ieee80211_iterate_nodes(&ic->ic_sta, rt2560_iter_func, arg); 855 sc->sc_rssadapt_id = timeout(rt2560_update_rssadapt, (void *)sc, 856 drv_usectohz(100 * 1000)); 857 } 858 859 static void 860 rt2560_statedog(void *arg) 861 { 862 struct rt2560_softc *sc = arg; 863 struct ieee80211com *ic = &sc->sc_ic; 864 enum ieee80211_state state; 865 866 RAL_LOCK(sc); 867 868 RAL_DEBUG(RAL_DBG_MSG, "rt2560_statedog(...)\n"); 869 870 sc->sc_state_id = 0; 871 state = ic->ic_state; 872 ic->ic_state = sc->sc_ostate; 873 874 RAL_UNLOCK(sc); 875 876 ieee80211_new_state(ic, state, -1); 877 878 } 879 880 static int 881 rt2560_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 882 { 883 struct rt2560_softc *sc = (struct rt2560_softc *)ic; 884 enum ieee80211_state ostate; 885 struct ieee80211_node *ni; 886 int err; 887 888 RAL_LOCK(sc); 889 890 ostate = ic->ic_state; 891 sc->sc_ostate = ostate; 892 893 if (sc->sc_scan_id != 0) { 894 (void) untimeout(sc->sc_scan_id); 895 sc->sc_scan_id = 0; 896 } 897 898 if (sc->sc_rssadapt_id != 0) { 899 (void) untimeout(sc->sc_rssadapt_id); 900 sc->sc_rssadapt_id = 0; 901 } 902 903 if (sc->sc_state_id != 0) { 904 (void) untimeout(sc->sc_state_id); 905 sc->sc_state_id = 0; 906 } 907 908 switch (nstate) { 909 case IEEE80211_S_INIT: 910 if (ostate == IEEE80211_S_RUN) { 911 /* abort TSF synchronization */ 912 RAL_WRITE(sc, RT2560_CSR14, 0); 913 /* turn association led off */ 914 rt2560_update_led(sc, 0, 0); 915 } 916 break; 917 918 case IEEE80211_S_SCAN: 919 rt2560_set_chan(sc, ic->ic_curchan); 920 sc->sc_scan_id = timeout(rt2560_next_scan, (void *)sc, 921 drv_usectohz(sc->dwelltime * 1000)); 922 break; 923 924 case IEEE80211_S_AUTH: 925 RAL_DEBUG(RAL_DBG_STATE, "-> IEEE80211_S_AUTH ...\n"); 926 rt2560_set_chan(sc, ic->ic_curchan); 927 break; 928 929 case IEEE80211_S_ASSOC: 930 RAL_DEBUG(RAL_DBG_STATE, "-> IEEE80211_S_ASSOC ...\n"); 931 rt2560_set_chan(sc, ic->ic_curchan); 932 933 drv_usecwait(10 * 1000); /* dlink */ 934 sc->sc_state_id = timeout(rt2560_statedog, (void *)sc, 935 drv_usectohz(300 * 1000)); /* ap7-3 */ 936 break; 937 938 case IEEE80211_S_RUN: 939 RAL_DEBUG(RAL_DBG_STATE, "-> IEEE80211_S_RUN ...\n"); 940 rt2560_set_chan(sc, ic->ic_curchan); 941 942 ni = ic->ic_bss; 943 944 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 945 rt2560_update_plcp(sc); 946 rt2560_set_basicrates(sc); 947 rt2560_set_bssid(sc, ni->in_bssid); 948 } 949 950 /* turn assocation led on */ 951 rt2560_update_led(sc, 1, 0); 952 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 953 sc->sc_rssadapt_id = timeout(rt2560_update_rssadapt, 954 (void *)sc, drv_usectohz(100 * 1000)); 955 rt2560_enable_tsf_sync(sc); 956 } 957 break; 958 } 959 960 RAL_UNLOCK(sc); 961 962 err = sc->sc_newstate(ic, nstate, arg); 963 /* 964 * Finally, start any timers. 965 */ 966 if (nstate == IEEE80211_S_RUN) 967 ieee80211_start_watchdog(ic, 1); 968 969 return (err); 970 } 971 972 /* 973 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 974 * 93C66). 975 */ 976 static uint16_t 977 rt2560_eeprom_read(struct rt2560_softc *sc, uint8_t addr) 978 { 979 uint32_t tmp; 980 uint16_t val; 981 int n; 982 983 /* clock C once before the first command */ 984 RT2560_EEPROM_CTL(sc, 0); 985 986 RT2560_EEPROM_CTL(sc, RT2560_S); 987 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_C); 988 RT2560_EEPROM_CTL(sc, RT2560_S); 989 990 /* write start bit (1) */ 991 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D); 992 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D | RT2560_C); 993 994 /* write READ opcode (10) */ 995 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D); 996 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D | RT2560_C); 997 RT2560_EEPROM_CTL(sc, RT2560_S); 998 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_C); 999 1000 /* write address (A5-A0 or A7-A0) */ 1001 n = (RAL_READ(sc, RT2560_CSR21) & RT2560_93C46) ? 5 : 7; 1002 for (; n >= 0; n--) { 1003 RT2560_EEPROM_CTL(sc, RT2560_S | 1004 (((addr >> n) & 1) << RT2560_SHIFT_D)); 1005 RT2560_EEPROM_CTL(sc, RT2560_S | 1006 (((addr >> n) & 1) << RT2560_SHIFT_D) | RT2560_C); 1007 } 1008 1009 RT2560_EEPROM_CTL(sc, RT2560_S); 1010 1011 /* read data Q15-Q0 */ 1012 val = 0; 1013 for (n = 15; n >= 0; n--) { 1014 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_C); 1015 tmp = RAL_READ(sc, RT2560_CSR21); 1016 val |= ((tmp & RT2560_Q) >> RT2560_SHIFT_Q) << n; 1017 RT2560_EEPROM_CTL(sc, RT2560_S); 1018 } 1019 1020 RT2560_EEPROM_CTL(sc, 0); 1021 1022 /* clear Chip Select and clock C */ 1023 RT2560_EEPROM_CTL(sc, RT2560_S); 1024 RT2560_EEPROM_CTL(sc, 0); 1025 RT2560_EEPROM_CTL(sc, RT2560_C); 1026 1027 return (val); 1028 } 1029 1030 static void 1031 rt2560_tx_intr(struct rt2560_softc *sc) 1032 { 1033 struct ieee80211com *ic = &sc->sc_ic; 1034 struct rt2560_tx_desc *desc; 1035 struct rt2560_tx_data *data; 1036 struct rt2560_node *rn; 1037 1038 struct dma_region *dr; 1039 int count; 1040 1041 dr = &sc->txq.dr_desc; 1042 count = sc->txq.count; 1043 1044 (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE, 1045 DDI_DMA_SYNC_FORKERNEL); 1046 1047 mutex_enter(&sc->txq.tx_lock); 1048 1049 for (;;) { 1050 desc = &sc->txq.desc[sc->txq.next]; 1051 data = &sc->txq.data[sc->txq.next]; 1052 1053 if ((LE_32(desc->flags) & RT2560_TX_BUSY) || 1054 (LE_32(desc->flags) & RT2560_TX_CIPHER_BUSY) || 1055 !(LE_32(desc->flags) & RT2560_TX_VALID)) 1056 break; 1057 1058 rn = (struct rt2560_node *)data->ni; 1059 1060 switch (LE_32(desc->flags) & RT2560_TX_RESULT_MASK) { 1061 case RT2560_TX_SUCCESS: 1062 RAL_DEBUG(RAL_DBG_INTR, "data frame sent success\n"); 1063 if (data->id.id_node != NULL) { 1064 ral_rssadapt_raise_rate(ic, &rn->rssadapt, 1065 &data->id); 1066 } 1067 break; 1068 1069 case RT2560_TX_SUCCESS_RETRY: 1070 RAL_DEBUG(RAL_DBG_INTR, 1071 "data frame sent after %u retries\n", 1072 (LE_32(desc->flags) >> 5) & 0x7); 1073 sc->sc_tx_retries++; 1074 break; 1075 1076 case RT2560_TX_FAIL_RETRY: 1077 RAL_DEBUG(RAL_DBG_INTR, 1078 "sending data frame failed (too much retries)\n"); 1079 if (data->id.id_node != NULL) { 1080 ral_rssadapt_lower_rate(ic, data->ni, 1081 &rn->rssadapt, &data->id); 1082 } 1083 break; 1084 1085 case RT2560_TX_FAIL_INVALID: 1086 case RT2560_TX_FAIL_OTHER: 1087 default: 1088 RAL_DEBUG(RAL_DBG_INTR, "sending data frame failed " 1089 "0x%08x\n", LE_32(desc->flags)); 1090 break; 1091 } 1092 1093 ieee80211_free_node(data->ni); 1094 data->ni = NULL; 1095 1096 /* descriptor is no longer valid */ 1097 desc->flags &= ~LE_32(RT2560_TX_VALID); 1098 1099 RAL_DEBUG(RAL_DBG_INTR, "tx done idx=%u\n", sc->txq.next); 1100 1101 sc->txq.queued--; 1102 sc->txq.next = (sc->txq.next + 1) % RT2560_TX_RING_COUNT; 1103 1104 if (sc->sc_need_sched && 1105 sc->txq.queued < (RT2560_TX_RING_COUNT - 32)) { 1106 sc->sc_need_sched = 0; 1107 mac_tx_update(ic->ic_mach); 1108 } 1109 } 1110 1111 (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE, 1112 DDI_DMA_SYNC_FORDEV); 1113 1114 sc->sc_tx_timer = 0; 1115 mutex_exit(&sc->txq.tx_lock); 1116 } 1117 1118 static void 1119 rt2560_prio_intr(struct rt2560_softc *sc) 1120 { 1121 struct rt2560_tx_desc *desc; 1122 struct rt2560_tx_data *data; 1123 1124 struct dma_region *dr; 1125 int count; 1126 1127 dr = &sc->prioq.dr_desc; 1128 count = sc->prioq.count; 1129 1130 (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE, 1131 DDI_DMA_SYNC_FORKERNEL); 1132 1133 mutex_enter(&sc->prioq.tx_lock); 1134 1135 for (;;) { 1136 desc = &sc->prioq.desc[sc->prioq.next]; 1137 data = &sc->prioq.data[sc->prioq.next]; 1138 1139 if ((LE_32(desc->flags) & RT2560_TX_BUSY) || 1140 !(LE_32(desc->flags) & RT2560_TX_VALID)) 1141 break; 1142 1143 switch (LE_32(desc->flags) & RT2560_TX_RESULT_MASK) { 1144 case RT2560_TX_SUCCESS: 1145 RAL_DEBUG(RAL_DBG_INTR, "mgt frame sent success\n"); 1146 break; 1147 1148 case RT2560_TX_SUCCESS_RETRY: 1149 RAL_DEBUG(RAL_DBG_INTR, 1150 "mgt frame sent after %u retries\n", 1151 (LE_32(desc->flags) >> 5) & 0x7); 1152 break; 1153 1154 case RT2560_TX_FAIL_RETRY: 1155 RAL_DEBUG(RAL_DBG_INTR, 1156 "sending mgt frame failed (too much " "retries)\n"); 1157 break; 1158 1159 case RT2560_TX_FAIL_INVALID: 1160 case RT2560_TX_FAIL_OTHER: 1161 default: 1162 RAL_DEBUG(RAL_DBG_INTR, "sending mgt frame failed " 1163 "0x%08x\n", LE_32(desc->flags)); 1164 } 1165 1166 ieee80211_free_node(data->ni); 1167 data->ni = NULL; 1168 1169 /* descriptor is no longer valid */ 1170 desc->flags &= ~LE_32(RT2560_TX_VALID); 1171 1172 RAL_DEBUG(RAL_DBG_INTR, "prio done idx=%u\n", sc->prioq.next); 1173 1174 sc->prioq.queued--; 1175 sc->prioq.next = (sc->prioq.next + 1) % RT2560_PRIO_RING_COUNT; 1176 } 1177 1178 (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE, 1179 DDI_DMA_SYNC_FORDEV); 1180 1181 sc->sc_tx_timer = 0; 1182 mutex_exit(&sc->prioq.tx_lock); 1183 } 1184 1185 /* 1186 * Some frames were received. Pass them to the hardware cipher engine before 1187 * sending them to the 802.11 layer. 1188 */ 1189 void 1190 rt2560_rx_intr(struct rt2560_softc *sc) 1191 { 1192 struct ieee80211com *ic = &sc->sc_ic; 1193 struct rt2560_rx_desc *desc; 1194 struct rt2560_rx_data *data; 1195 struct ieee80211_frame *wh; 1196 struct ieee80211_node *ni; 1197 struct rt2560_node *rn; 1198 1199 mblk_t *m; 1200 uint32_t len; 1201 char *rxbuf; 1202 1203 struct dma_region *dr, *dr_bf; 1204 int count; 1205 1206 dr = &sc->rxq.dr_desc; 1207 count = sc->rxq.count; 1208 1209 mutex_enter(&sc->rxq.rx_lock); 1210 1211 (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_RX_DESC_SIZE, 1212 DDI_DMA_SYNC_FORKERNEL); 1213 1214 for (;;) { 1215 desc = &sc->rxq.desc[sc->rxq.cur]; 1216 data = &sc->rxq.data[sc->rxq.cur]; 1217 1218 if ((LE_32(desc->flags) & RT2560_RX_BUSY) || 1219 (LE_32(desc->flags) & RT2560_RX_CIPHER_BUSY)) 1220 break; 1221 1222 data->drop = 0; 1223 1224 if ((LE_32(desc->flags) & RT2560_RX_PHY_ERROR) || 1225 (LE_32(desc->flags) & RT2560_RX_CRC_ERROR)) { 1226 /* 1227 * This should not happen since we did not request 1228 * to receive those frames when we filled RXCSR0. 1229 */ 1230 RAL_DEBUG(RAL_DBG_RX, "PHY or CRC error flags 0x%08x\n", 1231 LE_32(desc->flags)); 1232 data->drop = 1; 1233 } 1234 1235 if (((LE_32(desc->flags) >> 16) & 0xfff) > RAL_RXBUF_SIZE) { 1236 RAL_DEBUG(RAL_DBG_RX, "bad length\n"); 1237 data->drop = 1; 1238 } 1239 1240 if (data->drop) { 1241 sc->sc_rx_err++; 1242 goto skip; 1243 } 1244 1245 rxbuf = data->buf; 1246 len = (LE_32(desc->flags) >> 16) & 0xfff; 1247 1248 if ((len < sizeof (struct ieee80211_frame_min)) || 1249 (len > RAL_RXBUF_SIZE)) { 1250 RAL_DEBUG(RAL_DBG_RX, "bad frame length=%u\n", len); 1251 sc->sc_rx_err++; 1252 goto skip; 1253 } 1254 1255 if ((m = allocb(len, BPRI_MED)) == NULL) { 1256 RAL_DEBUG(RAL_DBG_RX, "rt2560_rx_intr():" 1257 " allocate mblk failed.\n"); 1258 sc->sc_rx_nobuf++; 1259 goto skip; 1260 } 1261 1262 dr_bf = &sc->rxq.dr_rxbuf[sc->rxq.cur]; 1263 (void) ddi_dma_sync(dr_bf->dr_hnd, 0, dr_bf->dr_size, 1264 DDI_DMA_SYNC_FORCPU); 1265 1266 bcopy(rxbuf, m->b_rptr, len); 1267 m->b_wptr += len; 1268 1269 wh = (struct ieee80211_frame *)m->b_rptr; 1270 ni = ieee80211_find_rxnode(ic, wh); 1271 1272 /* give rssi to the rate adatation algorithm */ 1273 rn = (struct rt2560_node *)ni; 1274 ral_rssadapt_input(ic, ni, &rn->rssadapt, desc->rssi); 1275 1276 /* send the frame to the 802.11 layer */ 1277 (void) ieee80211_input(ic, m, ni, desc->rssi, 0); 1278 1279 /* node is no longer needed */ 1280 ieee80211_free_node(ni); 1281 1282 skip: desc->flags = LE_32(RT2560_RX_BUSY); 1283 RAL_DEBUG(RAL_DBG_RX, "rx done idx=%u\n", sc->rxq.cur); 1284 1285 sc->rxq.cur = (sc->rxq.cur + 1) % RT2560_RX_RING_COUNT; 1286 } 1287 mutex_exit(&sc->rxq.rx_lock); 1288 1289 (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE, 1290 DDI_DMA_SYNC_FORDEV); 1291 } 1292 1293 uint_t 1294 ral_softint_handler(caddr_t data) 1295 { 1296 /* LINTED E_BAD_PTR_CAST_ALIGN */ 1297 struct rt2560_softc *sc = (struct rt2560_softc *)data; 1298 1299 /* 1300 * Check if the soft interrupt is triggered by another 1301 * driver at the same level. 1302 */ 1303 RAL_LOCK(sc); 1304 if (sc->sc_rx_pend) { 1305 sc->sc_rx_pend = 0; 1306 RAL_UNLOCK(sc); 1307 rt2560_rx_intr(sc); 1308 return (DDI_INTR_CLAIMED); 1309 } 1310 RAL_UNLOCK(sc); 1311 return (DDI_INTR_UNCLAIMED); 1312 } 1313 1314 /* 1315 * Return the expected ack rate for a frame transmitted at rate `rate'. 1316 * XXX: this should depend on the destination node basic rate set. 1317 */ 1318 static int 1319 rt2560_ack_rate(struct ieee80211com *ic, int rate) 1320 { 1321 switch (rate) { 1322 /* CCK rates */ 1323 case 2: 1324 return (2); 1325 case 4: 1326 case 11: 1327 case 22: 1328 return ((ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate); 1329 1330 /* OFDM rates */ 1331 case 12: 1332 case 18: 1333 return (12); 1334 case 24: 1335 case 36: 1336 return (24); 1337 case 48: 1338 case 72: 1339 case 96: 1340 case 108: 1341 return (48); 1342 } 1343 1344 /* default to 1Mbps */ 1345 return (2); 1346 } 1347 1348 /* 1349 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 1350 * The function automatically determines the operating mode depending on the 1351 * given rate. `flags' indicates whether short preamble is in use or not. 1352 */ 1353 static uint16_t 1354 rt2560_txtime(int len, int rate, uint32_t flags) 1355 { 1356 uint16_t txtime; 1357 1358 if (RAL_RATE_IS_OFDM(rate)) { 1359 /* IEEE Std 802.11a-1999, pp. 37 */ 1360 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 1361 txtime = 16 + 4 + 4 * txtime + 6; 1362 } else { 1363 /* IEEE Std 802.11b-1999, pp. 28 */ 1364 txtime = (16 * len + rate - 1) / rate; 1365 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 1366 txtime += 72 + 24; 1367 else 1368 txtime += 144 + 48; 1369 } 1370 1371 return (txtime); 1372 } 1373 1374 static uint8_t 1375 rt2560_plcp_signal(int rate) 1376 { 1377 switch (rate) { 1378 /* CCK rates (returned values are device-dependent) */ 1379 case 2: return (0x0); 1380 case 4: return (0x1); 1381 case 11: return (0x2); 1382 case 22: return (0x3); 1383 1384 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1385 case 12: return (0xb); 1386 case 18: return (0xf); 1387 case 24: return (0xa); 1388 case 36: return (0xe); 1389 case 48: return (0x9); 1390 case 72: return (0xd); 1391 case 96: return (0x8); 1392 case 108: return (0xc); 1393 1394 /* unsupported rates (should not get there) */ 1395 default: return (0xff); 1396 } 1397 } 1398 1399 void 1400 rt2560_setup_tx_desc(struct rt2560_softc *sc, struct rt2560_tx_desc *desc, 1401 uint32_t flags, int len, int rate, int encrypt) 1402 { 1403 struct ieee80211com *ic = &sc->sc_ic; 1404 uint16_t plcp_length; 1405 int remainder; 1406 1407 desc->flags = LE_32(flags); 1408 desc->flags |= LE_32(len << 16); 1409 desc->flags |= encrypt ? LE_32(RT2560_TX_CIPHER_BUSY) : 1410 LE_32(RT2560_TX_BUSY | RT2560_TX_VALID); 1411 1412 desc->wme = LE_16( 1413 RT2560_AIFSN(2) | 1414 RT2560_LOGCWMIN(3) | 1415 RT2560_LOGCWMAX(8)); 1416 1417 /* setup PLCP fields */ 1418 desc->plcp_signal = rt2560_plcp_signal(rate); 1419 desc->plcp_service = 4; 1420 1421 len += IEEE80211_CRC_LEN; 1422 if (RAL_RATE_IS_OFDM(rate)) { 1423 desc->flags |= LE_32(RT2560_TX_OFDM); 1424 1425 plcp_length = len & 0xfff; 1426 desc->plcp_length_hi = plcp_length >> 6; 1427 desc->plcp_length_lo = plcp_length & 0x3f; 1428 } else { 1429 plcp_length = (16 * len + rate - 1) / rate; 1430 if (rate == 22) { 1431 remainder = (16 * len) % 22; 1432 if (remainder != 0 && remainder < 7) 1433 desc->plcp_service |= RT2560_PLCP_LENGEXT; 1434 } 1435 desc->plcp_length_hi = plcp_length >> 8; 1436 desc->plcp_length_lo = plcp_length & 0xff; 1437 1438 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1439 desc->plcp_signal |= 0x08; 1440 } 1441 } 1442 1443 /* ARGSUSED */ 1444 int 1445 rt2560_mgmt_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type) 1446 { 1447 struct rt2560_softc *sc = (struct rt2560_softc *)ic; 1448 struct rt2560_tx_desc *desc; 1449 struct rt2560_tx_data *data; 1450 struct ieee80211_frame *wh; 1451 uint16_t dur; 1452 uint32_t flags = 0; 1453 int rate, err = DDI_SUCCESS; 1454 1455 int off, pktlen, mblen; 1456 caddr_t dest; 1457 mblk_t *m, *m0; 1458 1459 struct dma_region *dr; 1460 uint32_t idx; 1461 struct ieee80211_node *ni; 1462 struct ieee80211_key *k; 1463 1464 mutex_enter(&sc->prioq.tx_lock); 1465 1466 if (sc->prioq.queued >= RT2560_PRIO_RING_COUNT) { 1467 err = ENOMEM; 1468 sc->sc_tx_nobuf++; 1469 goto fail1; 1470 } 1471 1472 m = allocb(msgdsize(mp) + 32, BPRI_MED); 1473 if (m == NULL) { 1474 RAL_DEBUG(RAL_DBG_TX, "rt2560_mgmt_send: can't alloc mblk.\n"); 1475 err = DDI_FAILURE; 1476 goto fail1; 1477 } 1478 1479 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) { 1480 mblen = MBLKL(m0); 1481 (void) memcpy(m->b_rptr + off, m0->b_rptr, mblen); 1482 off += mblen; 1483 } 1484 m->b_wptr += off; 1485 1486 wh = (struct ieee80211_frame *)m->b_rptr; 1487 ni = ieee80211_find_txnode(ic, wh->i_addr1); 1488 1489 if (ni == NULL) { 1490 err = DDI_FAILURE; 1491 sc->sc_tx_err++; 1492 goto fail2; 1493 } 1494 1495 /* to support shared_key auth mode */ 1496 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1497 k = ieee80211_crypto_encap(ic, m); 1498 if (k == NULL) { 1499 err = DDI_FAILURE; 1500 sc->sc_tx_err++; 1501 goto fail3; 1502 } 1503 /* packet header may have moved, reset our local pointer */ 1504 wh = (struct ieee80211_frame *)m->b_rptr; 1505 } 1506 1507 desc = &sc->prioq.desc[sc->prioq.cur]; 1508 data = &sc->prioq.data[sc->prioq.cur]; 1509 1510 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1511 data->ni = ieee80211_ref_node(ni); 1512 1513 pktlen = msgdsize(m); 1514 dest = data->buf; 1515 bcopy(m->b_rptr, dest, pktlen); 1516 1517 wh = (struct ieee80211_frame *)m->b_rptr; 1518 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1519 flags |= RT2560_TX_ACK; 1520 1521 dur = rt2560_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + 1522 RAL_SIFS; 1523 /* LINTED E_BAD_PTR_CAST_ALIGN */ 1524 *(uint16_t *)wh->i_dur = LE_16(dur); 1525 1526 /* tell hardware to add timestamp for probe responses */ 1527 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1528 IEEE80211_FC0_TYPE_MGT && 1529 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1530 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1531 flags |= RT2560_TX_TIMESTAMP; 1532 } 1533 1534 rt2560_setup_tx_desc(sc, desc, flags, pktlen, rate, 0); 1535 1536 idx = sc->prioq.cur; 1537 1538 dr = &sc->prioq.dr_txbuf[idx]; 1539 (void) ddi_dma_sync(dr->dr_hnd, 0, RAL_TXBUF_SIZE, DDI_DMA_SYNC_FORDEV); 1540 1541 dr = &sc->prioq.dr_desc; 1542 (void) ddi_dma_sync(dr->dr_hnd, idx * RT2560_TX_DESC_SIZE, 1543 RT2560_TX_DESC_SIZE, DDI_DMA_SYNC_FORDEV); 1544 1545 RAL_DEBUG(RAL_DBG_MGMT, "sending mgt frame len=%u idx=%u rate=%u\n", 1546 pktlen, sc->prioq.cur, rate); 1547 1548 /* kick prio */ 1549 sc->prioq.queued++; /* IF > RT2560_PRIO_RING_COUNT? FULL */ 1550 sc->prioq.cur = (sc->prioq.cur + 1) % RT2560_PRIO_RING_COUNT; 1551 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_KICK_PRIO); 1552 1553 sc->sc_tx_timer = 5; 1554 1555 ic->ic_stats.is_tx_frags++; 1556 ic->ic_stats.is_tx_bytes += pktlen; 1557 1558 fail3: 1559 ieee80211_free_node(ni); 1560 fail2: 1561 freemsg(m); 1562 fail1: 1563 freemsg(mp); 1564 mutex_exit(&sc->prioq.tx_lock); 1565 1566 return (err); 1567 } 1568 1569 static int 1570 rt2560_send(ieee80211com_t *ic, mblk_t *mp) 1571 { 1572 struct rt2560_softc *sc = (struct rt2560_softc *)ic; 1573 struct rt2560_tx_desc *desc; 1574 struct rt2560_tx_data *data; 1575 struct rt2560_node *rn; 1576 struct ieee80211_rateset *rs; 1577 struct ieee80211_frame *wh; 1578 struct ieee80211_key *k; 1579 uint16_t dur; 1580 uint32_t flags = 0; 1581 int rate, err = DDI_SUCCESS; 1582 1583 struct ieee80211_node *ni; 1584 mblk_t *m, *m0; 1585 int off, mblen, pktlen; 1586 caddr_t dest; 1587 1588 struct dma_region *dr; 1589 uint32_t idx; 1590 1591 mutex_enter(&sc->txq.tx_lock); 1592 1593 if (sc->txq.queued >= RT2560_TX_RING_COUNT - 1) { 1594 RAL_DEBUG(RAL_DBG_TX, "ral: rt2560_tx_data(): " 1595 "no TX DMA buffer available!\n"); 1596 sc->sc_need_sched = 1; 1597 sc->sc_tx_nobuf++; 1598 err = ENOMEM; 1599 goto fail1; 1600 } 1601 1602 m = allocb(msgdsize(mp) + 32, BPRI_MED); 1603 if (m == NULL) { 1604 RAL_DEBUG(RAL_DBG_TX, "rt2560_xmit(): can't alloc mblk.\n"); 1605 err = DDI_FAILURE; 1606 goto fail1; 1607 } 1608 1609 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) { 1610 mblen = MBLKL(m0); 1611 (void) memcpy(m->b_rptr + off, m0->b_rptr, mblen); 1612 off += mblen; 1613 } 1614 m->b_wptr += off; 1615 1616 wh = (struct ieee80211_frame *)m->b_rptr; 1617 ni = ieee80211_find_txnode(ic, wh->i_addr1); 1618 1619 if (ni == NULL) { 1620 err = DDI_FAILURE; 1621 sc->sc_tx_err++; 1622 goto fail2; 1623 } 1624 1625 (void) ieee80211_encap(ic, m, ni); 1626 1627 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1628 k = ieee80211_crypto_encap(ic, m); 1629 if (k == NULL) { 1630 sc->sc_tx_err++; 1631 err = DDI_FAILURE; 1632 goto fail3; 1633 } 1634 /* packet header may have moved, reset our local pointer */ 1635 wh = (struct ieee80211_frame *)m->b_rptr; 1636 } 1637 1638 /* 1639 * RTS/CTS exchange ignore, since the max packet will less than 1640 * the rtsthreshold (2346) 1641 * Unnecessary codes deleted. 1642 */ 1643 1644 data = &sc->txq.data[sc->txq.cur]; 1645 desc = &sc->txq.desc[sc->txq.cur]; 1646 1647 data->ni = ieee80211_ref_node(ni); 1648 1649 pktlen = msgdsize(m); 1650 dest = data->buf; 1651 bcopy(m->b_rptr, dest, pktlen); 1652 1653 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1654 rs = &ic->ic_sup_rates[ic->ic_curmode]; 1655 rate = rs->ir_rates[ic->ic_fixed_rate]; 1656 } else { 1657 rs = &ni->in_rates; 1658 rn = (struct rt2560_node *)ni; 1659 ni->in_txrate = ral_rssadapt_choose(&rn->rssadapt, rs, wh, 1660 pktlen, NULL, 0); 1661 rate = rs->ir_rates[ni->in_txrate]; 1662 } 1663 1664 rate &= IEEE80211_RATE_VAL; 1665 if (rate <= 0) { 1666 rate = 2; /* basic rate */ 1667 } 1668 1669 /* remember link conditions for rate adaptation algorithm */ 1670 if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) { 1671 data->id.id_len = pktlen; 1672 data->id.id_rateidx = ni->in_txrate; 1673 data->id.id_node = ni; 1674 data->id.id_rssi = ni->in_rssi; 1675 } else 1676 data->id.id_node = NULL; 1677 1678 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1679 flags |= RT2560_TX_ACK; 1680 1681 dur = rt2560_txtime(RAL_ACK_SIZE, rt2560_ack_rate(ic, rate), 1682 ic->ic_flags) + RAL_SIFS; 1683 /* LINTED E_BAD_PTR_CAST_ALIGN */ 1684 *(uint16_t *)wh->i_dur = LE_16(dur); 1685 } 1686 1687 /* flags |= RT2560_TX_CIPHER_NONE; */ 1688 rt2560_setup_tx_desc(sc, desc, flags, pktlen, rate, 0); 1689 1690 idx = sc->txq.cur; 1691 1692 dr = &sc->txq.dr_txbuf[idx]; 1693 (void) ddi_dma_sync(dr->dr_hnd, 0, RAL_TXBUF_SIZE, DDI_DMA_SYNC_FORDEV); 1694 1695 dr = &sc->txq.dr_desc; 1696 (void) ddi_dma_sync(dr->dr_hnd, idx * RT2560_TX_DESC_SIZE, 1697 RT2560_TX_DESC_SIZE, DDI_DMA_SYNC_FORDEV); 1698 1699 RAL_DEBUG(RAL_DBG_TX, "sending data frame len=%u idx=%u rate=%u\n", 1700 pktlen, sc->txq.cur, rate); 1701 1702 /* kick tx */ 1703 sc->txq.queued++; 1704 sc->txq.cur = (sc->txq.cur + 1) % RT2560_TX_RING_COUNT; 1705 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_KICK_TX); 1706 1707 sc->sc_tx_timer = 5; 1708 1709 ic->ic_stats.is_tx_frags++; 1710 ic->ic_stats.is_tx_bytes += pktlen; 1711 1712 freemsg(mp); 1713 fail3: 1714 ieee80211_free_node(ni); 1715 fail2: 1716 freemsg(m); 1717 fail1: 1718 mutex_exit(&sc->txq.tx_lock); 1719 return (err); 1720 } 1721 1722 static mblk_t * 1723 rt2560_m_tx(void *arg, mblk_t *mp) 1724 { 1725 struct rt2560_softc *sc = (struct rt2560_softc *)arg; 1726 struct ieee80211com *ic = &sc->sc_ic; 1727 mblk_t *next; 1728 1729 /* 1730 * No data frames go out unless we're associated; this 1731 * should not happen as the 802.11 layer does not enable 1732 * the xmit queue until we enter the RUN state. 1733 */ 1734 if (ic->ic_state != IEEE80211_S_RUN) { 1735 RAL_DEBUG(RAL_DBG_TX, "ral: rt2560_tx_data(): " 1736 "discard, state %u\n", ic->ic_state); 1737 freemsgchain(mp); 1738 return (NULL); 1739 } 1740 1741 while (mp != NULL) { 1742 next = mp->b_next; 1743 mp->b_next = NULL; 1744 if (rt2560_send(ic, mp) != DDI_SUCCESS) { 1745 mp->b_next = next; 1746 freemsgchain(mp); 1747 return (NULL); 1748 } 1749 mp = next; 1750 } 1751 return (mp); 1752 } 1753 1754 static void 1755 rt2560_set_macaddr(struct rt2560_softc *sc, uint8_t *addr) 1756 { 1757 uint32_t tmp; 1758 1759 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 1760 RAL_WRITE(sc, RT2560_CSR3, tmp); 1761 1762 tmp = addr[4] | addr[5] << 8; 1763 RAL_WRITE(sc, RT2560_CSR4, tmp); 1764 1765 RAL_DEBUG(RAL_DBG_HW, 1766 "setting MAC address to " MACSTR "\n", MAC2STR(addr)); 1767 } 1768 1769 static void 1770 rt2560_get_macaddr(struct rt2560_softc *sc, uint8_t *addr) 1771 { 1772 uint32_t tmp; 1773 1774 tmp = RAL_READ(sc, RT2560_CSR3); 1775 addr[0] = tmp & 0xff; 1776 addr[1] = (tmp >> 8) & 0xff; 1777 addr[2] = (tmp >> 16) & 0xff; 1778 addr[3] = (tmp >> 24); 1779 1780 tmp = RAL_READ(sc, RT2560_CSR4); 1781 addr[4] = tmp & 0xff; 1782 addr[5] = (tmp >> 8) & 0xff; 1783 } 1784 1785 static void 1786 rt2560_update_promisc(struct rt2560_softc *sc) 1787 { 1788 uint32_t tmp; 1789 1790 tmp = RAL_READ(sc, RT2560_RXCSR0); 1791 tmp &= ~RT2560_DROP_NOT_TO_ME; 1792 if (!(sc->sc_rcr & RAL_RCR_PROMISC)) 1793 tmp |= RT2560_DROP_NOT_TO_ME; 1794 1795 RAL_WRITE(sc, RT2560_RXCSR0, tmp); 1796 RAL_DEBUG(RAL_DBG_HW, "%s promiscuous mode\n", 1797 (sc->sc_rcr & RAL_RCR_PROMISC) ? "entering" : "leaving"); 1798 } 1799 1800 static const char * 1801 rt2560_get_rf(int rev) 1802 { 1803 switch (rev) { 1804 case RT2560_RF_2522: return ("RT2522"); 1805 case RT2560_RF_2523: return ("RT2523"); 1806 case RT2560_RF_2524: return ("RT2524"); 1807 case RT2560_RF_2525: return ("RT2525"); 1808 case RT2560_RF_2525E: return ("RT2525e"); 1809 case RT2560_RF_2526: return ("RT2526"); 1810 case RT2560_RF_5222: return ("RT5222"); 1811 default: return ("unknown"); 1812 } 1813 } 1814 1815 static void 1816 rt2560_read_eeprom(struct rt2560_softc *sc) 1817 { 1818 uint16_t val; 1819 int i; 1820 1821 val = rt2560_eeprom_read(sc, RT2560_EEPROM_CONFIG0); 1822 sc->rf_rev = (val >> 11) & 0x7; 1823 sc->hw_radio = (val >> 10) & 0x1; 1824 sc->led_mode = (val >> 6) & 0x7; 1825 sc->rx_ant = (val >> 4) & 0x3; 1826 sc->tx_ant = (val >> 2) & 0x3; 1827 sc->nb_ant = val & 0x3; 1828 1829 /* read default values for BBP registers */ 1830 for (i = 0; i < 16; i++) { 1831 val = rt2560_eeprom_read(sc, RT2560_EEPROM_BBP_BASE + i); 1832 sc->bbp_prom[i].reg = val >> 8; 1833 sc->bbp_prom[i].val = val & 0xff; 1834 } 1835 1836 /* read Tx power for all b/g channels */ 1837 for (i = 0; i < 14 / 2; i++) { 1838 val = rt2560_eeprom_read(sc, RT2560_EEPROM_TXPOWER + i); 1839 sc->txpow[i * 2] = val >> 8; 1840 sc->txpow[i * 2 + 1] = val & 0xff; 1841 } 1842 } 1843 1844 static int 1845 rt2560_bbp_init(struct rt2560_softc *sc) 1846 { 1847 #define N(a) (sizeof (a) / sizeof ((a)[0])) 1848 int i, ntries; 1849 1850 /* wait for BBP to be ready */ 1851 for (ntries = 0; ntries < 100; ntries++) { 1852 if (rt2560_bbp_read(sc, RT2560_BBP_VERSION) != 0) 1853 break; 1854 drv_usecwait(1); 1855 } 1856 if (ntries == 100) { 1857 RAL_DEBUG(RAL_DBG_HW, "timeout waiting for BBP\n"); 1858 return (EIO); 1859 } 1860 /* initialize BBP registers to default values */ 1861 for (i = 0; i < N(rt2560_def_bbp); i++) { 1862 rt2560_bbp_write(sc, rt2560_def_bbp[i].reg, 1863 rt2560_def_bbp[i].val); 1864 } 1865 1866 return (0); 1867 #undef N 1868 } 1869 1870 static void 1871 rt2560_set_txantenna(struct rt2560_softc *sc, int antenna) 1872 { 1873 uint32_t tmp; 1874 uint8_t tx; 1875 1876 tx = rt2560_bbp_read(sc, RT2560_BBP_TX) & ~RT2560_BBP_ANTMASK; 1877 if (antenna == 1) 1878 tx |= RT2560_BBP_ANTA; 1879 else if (antenna == 2) 1880 tx |= RT2560_BBP_ANTB; 1881 else 1882 tx |= RT2560_BBP_DIVERSITY; 1883 1884 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 1885 if (sc->rf_rev == RT2560_RF_2525E || sc->rf_rev == RT2560_RF_2526 || 1886 sc->rf_rev == RT2560_RF_5222) 1887 tx |= RT2560_BBP_FLIPIQ; 1888 1889 rt2560_bbp_write(sc, RT2560_BBP_TX, tx); 1890 1891 /* update values for CCK and OFDM in BBPCSR1 */ 1892 tmp = RAL_READ(sc, RT2560_BBPCSR1) & ~0x00070007; 1893 tmp |= (tx & 0x7) << 16 | (tx & 0x7); 1894 RAL_WRITE(sc, RT2560_BBPCSR1, tmp); 1895 } 1896 1897 static void 1898 rt2560_set_rxantenna(struct rt2560_softc *sc, int antenna) 1899 { 1900 uint8_t rx; 1901 1902 rx = rt2560_bbp_read(sc, RT2560_BBP_RX) & ~RT2560_BBP_ANTMASK; 1903 if (antenna == 1) 1904 rx |= RT2560_BBP_ANTA; 1905 else if (antenna == 2) 1906 rx |= RT2560_BBP_ANTB; 1907 else 1908 rx |= RT2560_BBP_DIVERSITY; 1909 1910 /* need to force no I/Q flip for RF 2525e and 2526 */ 1911 if (sc->rf_rev == RT2560_RF_2525E || sc->rf_rev == RT2560_RF_2526) 1912 rx &= ~RT2560_BBP_FLIPIQ; 1913 1914 rt2560_bbp_write(sc, RT2560_BBP_RX, rx); 1915 } 1916 1917 static void 1918 rt2560_stop(struct rt2560_softc *sc) 1919 { 1920 struct ieee80211com *ic = &sc->sc_ic; 1921 1922 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1923 ieee80211_stop_watchdog(ic); /* stop the watchdog */ 1924 1925 RAL_LOCK(sc); 1926 sc->sc_tx_timer = 0; 1927 1928 /* abort Tx */ 1929 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_ABORT_TX); 1930 1931 /* disable Rx */ 1932 RAL_WRITE(sc, RT2560_RXCSR0, RT2560_DISABLE_RX); 1933 1934 /* reset ASIC (imply reset BBP) */ 1935 RAL_WRITE(sc, RT2560_CSR1, RT2560_RESET_ASIC); 1936 RAL_WRITE(sc, RT2560_CSR1, 0); 1937 1938 /* disable interrupts */ 1939 RAL_WRITE(sc, RT2560_CSR8, 0xffffffff); 1940 1941 /* reset Tx and Rx rings */ 1942 rt2560_reset_tx_ring(sc, &sc->txq); 1943 rt2560_reset_tx_ring(sc, &sc->prioq); 1944 rt2560_reset_rx_ring(sc, &sc->rxq); 1945 RAL_UNLOCK(sc); 1946 } 1947 1948 static int 1949 rt2560_init(struct rt2560_softc *sc) 1950 { 1951 #define N(a) (sizeof (a) / sizeof ((a)[0])) 1952 /* struct rt2560_softc *sc = priv; */ 1953 struct ieee80211com *ic = &sc->sc_ic; 1954 uint32_t tmp; 1955 int i; 1956 1957 rt2560_stop(sc); 1958 1959 RAL_LOCK(sc); 1960 /* setup tx/rx ring */ 1961 rt2560_ring_hwsetup(sc); 1962 1963 /* initialize MAC registers to default values */ 1964 for (i = 0; i < N(rt2560_def_mac); i++) 1965 RAL_WRITE(sc, rt2560_def_mac[i].reg, rt2560_def_mac[i].val); 1966 1967 rt2560_set_macaddr(sc, ic->ic_macaddr); 1968 1969 /* set basic rate set (will be updated later) */ 1970 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x153); 1971 1972 rt2560_set_txantenna(sc, sc->tx_ant); 1973 rt2560_set_rxantenna(sc, sc->rx_ant); 1974 rt2560_update_slot(ic, 1); 1975 rt2560_update_plcp(sc); 1976 rt2560_update_led(sc, 0, 0); 1977 1978 RAL_WRITE(sc, RT2560_CSR1, RT2560_RESET_ASIC); 1979 RAL_WRITE(sc, RT2560_CSR1, RT2560_HOST_READY); 1980 1981 if (rt2560_bbp_init(sc) != 0) { 1982 RAL_UNLOCK(sc); 1983 rt2560_stop(sc); 1984 return (DDI_FAILURE); 1985 } 1986 1987 /* set default BSS channel */ 1988 rt2560_set_chan(sc, ic->ic_curchan); 1989 1990 /* kick Rx */ 1991 tmp = RT2560_DROP_PHY_ERROR | RT2560_DROP_CRC_ERROR; 1992 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1993 tmp |= RT2560_DROP_CTL | RT2560_DROP_VERSION_ERROR; 1994 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 1995 tmp |= RT2560_DROP_TODS; 1996 if (!(sc->sc_rcr & RAL_RCR_PROMISC)) 1997 tmp |= RT2560_DROP_NOT_TO_ME; 1998 1999 } 2000 RAL_WRITE(sc, RT2560_RXCSR0, tmp); 2001 2002 /* clear old FCS and Rx FIFO errors */ 2003 (void) RAL_READ(sc, RT2560_CNT0); 2004 (void) RAL_READ(sc, RT2560_CNT4); 2005 2006 /* clear any pending interrupts */ 2007 RAL_WRITE(sc, RT2560_CSR7, 0xffffffff); 2008 /* enable interrupts */ 2009 RAL_WRITE(sc, RT2560_CSR8, RT2560_INTR_MASK); 2010 2011 RAL_UNLOCK(sc); 2012 #undef N 2013 return (DDI_SUCCESS); 2014 } 2015 2016 void 2017 rt2560_watchdog(void *arg) 2018 { 2019 struct rt2560_softc *sc = arg; 2020 struct ieee80211com *ic = &sc->sc_ic; 2021 int ntimer = 0; 2022 2023 RAL_LOCK(sc); 2024 ic->ic_watchdog_timer = 0; 2025 2026 if (!RAL_IS_RUNNING(sc)) { 2027 RAL_UNLOCK(sc); 2028 return; 2029 } 2030 2031 if (sc->sc_tx_timer > 0) { 2032 if (--sc->sc_tx_timer == 0) { 2033 RAL_DEBUG(RAL_DBG_MSG, "tx timer timeout\n"); 2034 RAL_UNLOCK(sc); 2035 (void) rt2560_init(sc); 2036 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2037 return; 2038 } 2039 } 2040 2041 if (ic->ic_state == IEEE80211_S_RUN) 2042 ntimer = 1; 2043 2044 RAL_UNLOCK(sc); 2045 2046 ieee80211_watchdog(ic); 2047 2048 if (ntimer) 2049 ieee80211_start_watchdog(ic, ntimer); 2050 } 2051 2052 static int 2053 rt2560_m_start(void *arg) 2054 { 2055 struct rt2560_softc *sc = (struct rt2560_softc *)arg; 2056 crypto_mech_type_t type; 2057 int err; 2058 2059 2060 type = crypto_mech2id(SUN_CKM_RC4); /* load rc4 module into kernel */ 2061 RAL_DEBUG(RAL_DBG_GLD, "enter rt2560_m_start(%d)\n", type); 2062 2063 /* 2064 * initialize rt2560 hardware 2065 */ 2066 err = rt2560_init(sc); 2067 if (err != DDI_SUCCESS) { 2068 RAL_DEBUG(RAL_DBG_GLD, "device configuration failed\n"); 2069 goto fail; 2070 } 2071 sc->sc_flags |= RAL_FLAG_RUNNING; /* RUNNING */ 2072 return (err); 2073 2074 fail: 2075 rt2560_stop(sc); 2076 return (err); 2077 } 2078 2079 static void 2080 rt2560_m_stop(void *arg) 2081 { 2082 struct rt2560_softc *sc = (struct rt2560_softc *)arg; 2083 2084 RAL_DEBUG(RAL_DBG_GLD, "enter rt2560_m_stop()\n"); 2085 2086 (void) rt2560_stop(sc); 2087 sc->sc_flags &= ~RAL_FLAG_RUNNING; /* STOP */ 2088 } 2089 2090 static int 2091 rt2560_m_unicst(void *arg, const uint8_t *macaddr) 2092 { 2093 struct rt2560_softc *sc = (struct rt2560_softc *)arg; 2094 struct ieee80211com *ic = &sc->sc_ic; 2095 2096 RAL_DEBUG(RAL_DBG_GLD, "rt2560_m_unicst(): " MACSTR "\n", 2097 MAC2STR(macaddr)); 2098 2099 IEEE80211_ADDR_COPY(ic->ic_macaddr, macaddr); 2100 (void) rt2560_set_macaddr(sc, (uint8_t *)macaddr); 2101 (void) rt2560_init(sc); 2102 2103 return (0); 2104 } 2105 2106 /*ARGSUSED*/ 2107 static int 2108 rt2560_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 2109 { 2110 return (0); 2111 } 2112 2113 static int 2114 rt2560_m_promisc(void *arg, boolean_t on) 2115 { 2116 struct rt2560_softc *sc = (struct rt2560_softc *)arg; 2117 2118 RAL_DEBUG(RAL_DBG_GLD, "rt2560_m_promisc()\n"); 2119 2120 if (on) { 2121 sc->sc_rcr |= RAL_RCR_PROMISC; 2122 sc->sc_rcr |= RAL_RCR_MULTI; 2123 } else { 2124 sc->sc_rcr &= ~RAL_RCR_PROMISC; 2125 sc->sc_rcr &= ~RAL_RCR_PROMISC; 2126 } 2127 2128 rt2560_update_promisc(sc); 2129 return (0); 2130 } 2131 2132 /* 2133 * callback functions for /get/set properties 2134 */ 2135 static int 2136 rt2560_m_setprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num, 2137 uint_t wldp_length, const void *wldp_buf) 2138 { 2139 struct rt2560_softc *sc = arg; 2140 struct ieee80211com *ic = &sc->sc_ic; 2141 int err; 2142 2143 err = ieee80211_setprop(ic, pr_name, wldp_pr_num, 2144 wldp_length, wldp_buf); 2145 RAL_LOCK(sc); 2146 if (err == ENETRESET) { 2147 if (RAL_IS_RUNNING(sc)) { 2148 RAL_UNLOCK(sc); 2149 (void) rt2560_init(sc); 2150 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2151 RAL_LOCK(sc); 2152 } 2153 err = 0; 2154 } 2155 RAL_UNLOCK(sc); 2156 2157 return (err); 2158 } 2159 2160 static int 2161 rt2560_m_getprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num, 2162 uint_t pr_flags, uint_t wldp_length, void *wldp_buf, uint_t *perm) 2163 { 2164 struct rt2560_softc *sc = arg; 2165 int err; 2166 2167 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num, 2168 pr_flags, wldp_length, wldp_buf, perm); 2169 2170 return (err); 2171 } 2172 2173 static void 2174 rt2560_m_ioctl(void* arg, queue_t *wq, mblk_t *mp) 2175 { 2176 struct rt2560_softc *sc = (struct rt2560_softc *)arg; 2177 struct ieee80211com *ic = &sc->sc_ic; 2178 int err; 2179 2180 err = ieee80211_ioctl(ic, wq, mp); 2181 RAL_LOCK(sc); 2182 if (err == ENETRESET) { 2183 if (RAL_IS_RUNNING(sc)) { 2184 RAL_UNLOCK(sc); 2185 (void) rt2560_init(sc); 2186 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2187 RAL_LOCK(sc); 2188 } 2189 } 2190 RAL_UNLOCK(sc); 2191 } 2192 2193 static int 2194 rt2560_m_stat(void *arg, uint_t stat, uint64_t *val) 2195 { 2196 struct rt2560_softc *sc = (struct rt2560_softc *)arg; 2197 ieee80211com_t *ic = &sc->sc_ic; 2198 ieee80211_node_t *ni = ic->ic_bss; 2199 struct ieee80211_rateset *rs = &ni->in_rates; 2200 2201 RAL_LOCK(sc); 2202 switch (stat) { 2203 case MAC_STAT_IFSPEED: 2204 *val = ((ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) ? 2205 (rs->ir_rates[ni->in_txrate] & IEEE80211_RATE_VAL) 2206 : ic->ic_fixed_rate) / 2 * 1000000; 2207 break; 2208 case MAC_STAT_NOXMTBUF: 2209 *val = sc->sc_tx_nobuf; 2210 break; 2211 case MAC_STAT_NORCVBUF: 2212 *val = sc->sc_rx_nobuf; 2213 break; 2214 case MAC_STAT_IERRORS: 2215 *val = sc->sc_rx_err; 2216 break; 2217 case MAC_STAT_RBYTES: 2218 *val = ic->ic_stats.is_rx_bytes; 2219 break; 2220 case MAC_STAT_IPACKETS: 2221 *val = ic->ic_stats.is_rx_frags; 2222 break; 2223 case MAC_STAT_OBYTES: 2224 *val = ic->ic_stats.is_tx_bytes; 2225 break; 2226 case MAC_STAT_OPACKETS: 2227 *val = ic->ic_stats.is_tx_frags; 2228 break; 2229 case MAC_STAT_OERRORS: 2230 case WIFI_STAT_TX_FAILED: 2231 *val = sc->sc_tx_err; 2232 break; 2233 case WIFI_STAT_TX_RETRANS: 2234 *val = sc->sc_tx_retries; 2235 break; 2236 case WIFI_STAT_FCS_ERRORS: 2237 case WIFI_STAT_WEP_ERRORS: 2238 case WIFI_STAT_TX_FRAGS: 2239 case WIFI_STAT_MCAST_TX: 2240 case WIFI_STAT_RTS_SUCCESS: 2241 case WIFI_STAT_RTS_FAILURE: 2242 case WIFI_STAT_ACK_FAILURE: 2243 case WIFI_STAT_RX_FRAGS: 2244 case WIFI_STAT_MCAST_RX: 2245 case WIFI_STAT_RX_DUPS: 2246 RAL_UNLOCK(sc); 2247 return (ieee80211_stat(ic, stat, val)); 2248 default: 2249 RAL_UNLOCK(sc); 2250 return (ENOTSUP); 2251 } 2252 RAL_UNLOCK(sc); 2253 2254 return (0); 2255 } 2256 2257 static uint_t 2258 rt2560_intr(caddr_t arg) 2259 { 2260 /* LINTED E_BAD_PTR_CAST_ALIGN */ 2261 struct rt2560_softc *sc = (struct rt2560_softc *)arg; 2262 uint32_t r; 2263 2264 RAL_LOCK(sc); 2265 2266 r = RAL_READ(sc, RT2560_CSR7); 2267 RAL_WRITE(sc, RT2560_CSR7, r); 2268 2269 if (r == 0xffffffff) { 2270 RAL_UNLOCK(sc); 2271 return (DDI_INTR_UNCLAIMED); 2272 } 2273 2274 if (!(r & RT2560_INTR_ALL)) { 2275 RAL_UNLOCK(sc); 2276 return (DDI_INTR_UNCLAIMED); 2277 } 2278 2279 /* disable interrupts */ 2280 RAL_WRITE(sc, RT2560_CSR8, 0xffffffff); 2281 2282 if (r & RT2560_TX_DONE) { 2283 RAL_UNLOCK(sc); 2284 rt2560_tx_intr(sc); 2285 RAL_LOCK(sc); 2286 } 2287 2288 if (r & RT2560_PRIO_DONE) { 2289 RAL_UNLOCK(sc); 2290 rt2560_prio_intr(sc); 2291 RAL_LOCK(sc); 2292 } 2293 2294 if (r & RT2560_RX_DONE) { 2295 sc->sc_rx_pend = 1; 2296 ddi_trigger_softintr(sc->sc_softint_id); 2297 } 2298 2299 /* re-enable interrupts */ 2300 RAL_WRITE(sc, RT2560_CSR8, RT2560_INTR_MASK); 2301 RAL_UNLOCK(sc); 2302 2303 return (DDI_INTR_CLAIMED); 2304 } 2305 2306 /* 2307 * quiesce(9E) entry point. 2308 * 2309 * This function is called when the system is single-threaded at high 2310 * PIL with preemption disabled. Therefore, this function must not be 2311 * blocked. 2312 * 2313 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 2314 * DDI_FAILURE indicates an error condition and should almost never happen. 2315 */ 2316 static int32_t 2317 rt2560_quiesce(dev_info_t *devinfo) 2318 { 2319 struct rt2560_softc *sc; 2320 2321 sc = ddi_get_soft_state(ral_soft_state_p, ddi_get_instance(devinfo)); 2322 if (sc == NULL) 2323 return (DDI_FAILURE); 2324 2325 /* abort Tx */ 2326 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_ABORT_TX); 2327 2328 /* disable Rx */ 2329 RAL_WRITE(sc, RT2560_RXCSR0, RT2560_DISABLE_RX); 2330 2331 /* reset ASIC (imply reset BBP) */ 2332 RAL_WRITE(sc, RT2560_CSR1, RT2560_RESET_ASIC); 2333 RAL_WRITE(sc, RT2560_CSR1, 0); 2334 2335 /* disable interrupts */ 2336 RAL_WRITE(sc, RT2560_CSR8, 0xffffffff); 2337 2338 return (DDI_SUCCESS); 2339 } 2340 2341 static int 2342 rt2560_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 2343 { 2344 struct rt2560_softc *sc; 2345 struct ieee80211com *ic; 2346 int err, i; 2347 int instance; 2348 2349 ddi_acc_handle_t ioh; 2350 caddr_t regs; 2351 uint16_t vendor_id, device_id, command; 2352 uint8_t cachelsz; 2353 char strbuf[32]; 2354 2355 wifi_data_t wd = { 0 }; 2356 mac_register_t *macp; 2357 2358 RAL_DEBUG(RAL_DBG_GLD, "enter rt2560_attach()\n"); 2359 2360 if (cmd != DDI_ATTACH) 2361 return (DDI_FAILURE); 2362 2363 instance = ddi_get_instance(devinfo); 2364 2365 if (ddi_soft_state_zalloc(ral_soft_state_p, instance) != DDI_SUCCESS) { 2366 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): " 2367 "unable to alloc soft_state_p\n"); 2368 return (DDI_FAILURE); 2369 } 2370 2371 sc = ddi_get_soft_state(ral_soft_state_p, instance); 2372 ic = (ieee80211com_t *)&sc->sc_ic; 2373 sc->sc_dev = devinfo; 2374 2375 /* pci configuration */ 2376 err = ddi_regs_map_setup(devinfo, 0, ®s, 0, 0, &ral_csr_accattr, 2377 &ioh); 2378 if (err != DDI_SUCCESS) { 2379 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): " 2380 "ddi_regs_map_setup() failed"); 2381 goto fail1; 2382 } 2383 2384 cachelsz = ddi_get8(ioh, (uint8_t *)(regs + PCI_CONF_CACHE_LINESZ)); 2385 if (cachelsz == 0) 2386 cachelsz = 0x10; 2387 sc->sc_cachelsz = cachelsz << 2; 2388 2389 vendor_id = ddi_get16(ioh, 2390 (uint16_t *)((uintptr_t)regs + PCI_CONF_VENID)); 2391 device_id = ddi_get16(ioh, 2392 (uint16_t *)((uintptr_t)regs + PCI_CONF_DEVID)); 2393 2394 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): vendor 0x%x, " 2395 "device id 0x%x, cache size %d\n", vendor_id, device_id, cachelsz); 2396 2397 /* 2398 * Enable response to memory space accesses, 2399 * and enabe bus master. 2400 */ 2401 command = PCI_COMM_MAE | PCI_COMM_ME; 2402 ddi_put16(ioh, (uint16_t *)((uintptr_t)regs + PCI_CONF_COMM), command); 2403 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): " 2404 "set command reg to 0x%x \n", command); 2405 2406 ddi_put8(ioh, (uint8_t *)(regs + PCI_CONF_LATENCY_TIMER), 0xa8); 2407 ddi_put8(ioh, (uint8_t *)(regs + PCI_CONF_ILINE), 0x10); 2408 ddi_regs_map_free(&ioh); 2409 2410 /* pci i/o space */ 2411 err = ddi_regs_map_setup(devinfo, 1, 2412 &sc->sc_rbase, 0, 0, &ral_csr_accattr, &sc->sc_ioh); 2413 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): " 2414 "regs map1 = %x err=%d\n", regs, err); 2415 if (err != DDI_SUCCESS) { 2416 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): " 2417 "ddi_regs_map_setup() failed"); 2418 goto fail1; 2419 } 2420 2421 /* initialize the ral rate */ 2422 ral_rate_init(); 2423 2424 /* retrieve RT2560 rev. no */ 2425 sc->asic_rev = RAL_READ(sc, RT2560_CSR0); 2426 2427 /* retrieve MAC address */ 2428 rt2560_get_macaddr(sc, ic->ic_macaddr); 2429 2430 /* retrieve RF rev. no and various other things from EEPROM */ 2431 rt2560_read_eeprom(sc); 2432 2433 RAL_DEBUG(RAL_DBG_GLD, "MAC/BBP RT2560 (rev 0x%02x), RF %s\n", 2434 sc->asic_rev, rt2560_get_rf(sc->rf_rev)); 2435 2436 /* 2437 * Allocate Tx and Rx rings. 2438 */ 2439 err = rt2560_alloc_tx_ring(sc, &sc->txq, RT2560_TX_RING_COUNT); 2440 if (err != DDI_SUCCESS) { 2441 RAL_DEBUG(RAL_DBG_GLD, "could not allocate Tx ring\n"); 2442 goto fail2; 2443 } 2444 err = rt2560_alloc_tx_ring(sc, &sc->prioq, RT2560_PRIO_RING_COUNT); 2445 if (err != DDI_SUCCESS) { 2446 RAL_DEBUG(RAL_DBG_GLD, "could not allocate Prio ring\n"); 2447 goto fail3; 2448 } 2449 err = rt2560_alloc_rx_ring(sc, &sc->rxq, RT2560_RX_RING_COUNT); 2450 if (err != DDI_SUCCESS) { 2451 RAL_DEBUG(RAL_DBG_GLD, "could not allocate Rx ring\n"); 2452 goto fail4; 2453 } 2454 2455 mutex_init(&sc->sc_genlock, NULL, MUTEX_DRIVER, NULL); 2456 mutex_init(&sc->txq.tx_lock, NULL, MUTEX_DRIVER, NULL); 2457 mutex_init(&sc->prioq.tx_lock, NULL, MUTEX_DRIVER, NULL); 2458 mutex_init(&sc->rxq.rx_lock, NULL, MUTEX_DRIVER, NULL); 2459 2460 2461 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 2462 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 2463 ic->ic_state = IEEE80211_S_INIT; 2464 2465 ic->ic_maxrssi = 63; 2466 ic->ic_set_shortslot = rt2560_update_slot; 2467 ic->ic_xmit = rt2560_mgmt_send; 2468 2469 /* set device capabilities */ 2470 ic->ic_caps = 2471 IEEE80211_C_TXPMGT | /* tx power management */ 2472 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 2473 IEEE80211_C_SHSLOT; /* short slot time supported */ 2474 2475 ic->ic_caps |= IEEE80211_C_WPA; /* Support WPA/WPA2 */ 2476 2477 #define IEEE80211_CHAN_A \ 2478 (IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_OFDM) 2479 2480 if (sc->rf_rev == RT2560_RF_5222) { 2481 /* set supported .11a rates */ 2482 ic->ic_sup_rates[IEEE80211_MODE_11A] = rt2560_rateset_11a; 2483 2484 /* set supported .11a channels */ 2485 for (i = 36; i <= 64; i += 4) { 2486 ic->ic_sup_channels[i].ich_freq = 2487 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 2488 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A; 2489 } 2490 for (i = 100; i <= 140; i += 4) { 2491 ic->ic_sup_channels[i].ich_freq = 2492 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 2493 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A; 2494 } 2495 for (i = 149; i <= 161; i += 4) { 2496 ic->ic_sup_channels[i].ich_freq = 2497 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 2498 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A; 2499 } 2500 } 2501 2502 /* set supported .11b and .11g rates */ 2503 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2560_rateset_11b; 2504 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2560_rateset_11g; 2505 2506 /* set supported .11b and .11g channels (1 through 14) */ 2507 for (i = 1; i <= 14; i++) { 2508 ic->ic_sup_channels[i].ich_freq = 2509 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 2510 ic->ic_sup_channels[i].ich_flags = 2511 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 2512 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 2513 } 2514 2515 ieee80211_attach(ic); 2516 2517 /* register WPA door */ 2518 ieee80211_register_door(ic, ddi_driver_name(devinfo), 2519 ddi_get_instance(devinfo)); 2520 2521 ic->ic_node_alloc = rt2560_node_alloc; 2522 ic->ic_node_free = rt2560_node_free; 2523 2524 /* override state transition machine */ 2525 sc->sc_newstate = ic->ic_newstate; 2526 ic->ic_newstate = rt2560_newstate; 2527 ic->ic_watchdog = rt2560_watchdog; 2528 ieee80211_media_init(ic); 2529 ic->ic_def_txkey = 0; 2530 2531 sc->sc_rcr = 0; 2532 sc->sc_rx_pend = 0; 2533 sc->dwelltime = 300; 2534 sc->sc_flags &= ~RAL_FLAG_RUNNING; 2535 2536 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, 2537 &sc->sc_softint_id, NULL, 0, ral_softint_handler, (caddr_t)sc); 2538 if (err != DDI_SUCCESS) { 2539 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): " 2540 "ddi_add_softintr() failed"); 2541 goto fail5; 2542 } 2543 2544 err = ddi_get_iblock_cookie(devinfo, 0, &sc->sc_iblock); 2545 if (err != DDI_SUCCESS) { 2546 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): " 2547 "Can not get iblock cookie for INT\n"); 2548 goto fail6; 2549 } 2550 2551 err = ddi_add_intr(devinfo, 0, NULL, NULL, rt2560_intr, (caddr_t)sc); 2552 if (err != DDI_SUCCESS) { 2553 RAL_DEBUG(RAL_DBG_GLD, 2554 "unable to add device interrupt handler\n"); 2555 goto fail6; 2556 } 2557 2558 /* 2559 * Provide initial settings for the WiFi plugin; whenever this 2560 * information changes, we need to call mac_plugindata_update() 2561 */ 2562 wd.wd_opmode = ic->ic_opmode; 2563 wd.wd_secalloc = WIFI_SEC_NONE; 2564 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid); 2565 2566 if ((macp = mac_alloc(MAC_VERSION)) == NULL) { 2567 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): " 2568 "MAC version mismatch\n"); 2569 goto fail7; 2570 } 2571 2572 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI; 2573 macp->m_driver = sc; 2574 macp->m_dip = devinfo; 2575 macp->m_src_addr = ic->ic_macaddr; 2576 macp->m_callbacks = &rt2560_m_callbacks; 2577 macp->m_min_sdu = 0; 2578 macp->m_max_sdu = IEEE80211_MTU; 2579 macp->m_pdata = &wd; 2580 macp->m_pdata_size = sizeof (wd); 2581 2582 err = mac_register(macp, &ic->ic_mach); 2583 mac_free(macp); 2584 if (err != 0) { 2585 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): " 2586 "mac_register err %x\n", err); 2587 goto fail7; 2588 } 2589 2590 /* 2591 * Create minor node of type DDI_NT_NET_WIFI 2592 */ 2593 (void) snprintf(strbuf, sizeof (strbuf), "%s%d", 2594 "ral", instance); 2595 err = ddi_create_minor_node(devinfo, strbuf, S_IFCHR, 2596 instance + 1, DDI_NT_NET_WIFI, 0); 2597 2598 if (err != DDI_SUCCESS) 2599 RAL_DEBUG(RAL_DBG_GLD, "ddi_create_minor_node() failed\n"); 2600 2601 /* 2602 * Notify link is down now 2603 */ 2604 mac_link_update(ic->ic_mach, LINK_STATE_DOWN); 2605 2606 RAL_DEBUG(RAL_DBG_GLD, "rt2560_attach() exit successfully.\n"); 2607 return (DDI_SUCCESS); 2608 fail7: 2609 ddi_remove_intr(devinfo, 0, sc->sc_iblock); 2610 fail6: 2611 ddi_remove_softintr(sc->sc_softint_id); 2612 fail5: 2613 mutex_destroy(&sc->sc_genlock); 2614 mutex_destroy(&sc->txq.tx_lock); 2615 mutex_destroy(&sc->prioq.tx_lock); 2616 mutex_destroy(&sc->rxq.rx_lock); 2617 2618 rt2560_free_rx_ring(sc, &sc->rxq); 2619 fail4: 2620 rt2560_free_tx_ring(sc, &sc->prioq); 2621 fail3: 2622 rt2560_free_tx_ring(sc, &sc->txq); 2623 fail2: 2624 ddi_regs_map_free(&sc->sc_ioh); 2625 fail1: 2626 ddi_soft_state_free(ral_soft_state_p, ddi_get_instance(devinfo)); 2627 2628 return (DDI_FAILURE); 2629 } 2630 2631 static int 2632 rt2560_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 2633 { 2634 struct rt2560_softc *sc; 2635 2636 RAL_DEBUG(RAL_DBG_GLD, "enter rt2560_detach()\n"); 2637 sc = ddi_get_soft_state(ral_soft_state_p, ddi_get_instance(devinfo)); 2638 2639 if (cmd != DDI_DETACH) 2640 return (DDI_FAILURE); 2641 2642 if (mac_disable(sc->sc_ic.ic_mach) != 0) 2643 return (DDI_FAILURE); 2644 2645 rt2560_stop(sc); 2646 2647 /* 2648 * Unregister from the MAC layer subsystem 2649 */ 2650 (void) mac_unregister(sc->sc_ic.ic_mach); 2651 2652 ddi_remove_intr(devinfo, 0, sc->sc_iblock); 2653 ddi_remove_softintr(sc->sc_softint_id); 2654 2655 /* 2656 * detach ieee80211 layer 2657 */ 2658 ieee80211_detach(&sc->sc_ic); 2659 2660 rt2560_free_tx_ring(sc, &sc->txq); 2661 rt2560_free_tx_ring(sc, &sc->prioq); 2662 rt2560_free_rx_ring(sc, &sc->rxq); 2663 2664 ddi_regs_map_free(&sc->sc_ioh); 2665 2666 mutex_destroy(&sc->sc_genlock); 2667 mutex_destroy(&sc->txq.tx_lock); 2668 mutex_destroy(&sc->prioq.tx_lock); 2669 mutex_destroy(&sc->rxq.rx_lock); 2670 2671 ddi_remove_minor_node(devinfo, NULL); 2672 ddi_soft_state_free(ral_soft_state_p, ddi_get_instance(devinfo)); 2673 2674 return (DDI_SUCCESS); 2675 } 2676 2677 int 2678 _info(struct modinfo *modinfop) 2679 { 2680 return (mod_info(&modlinkage, modinfop)); 2681 } 2682 2683 int 2684 _init(void) 2685 { 2686 int status; 2687 2688 status = ddi_soft_state_init(&ral_soft_state_p, 2689 sizeof (struct rt2560_softc), 1); 2690 if (status != 0) 2691 return (status); 2692 2693 mac_init_ops(&ral_dev_ops, "ral"); 2694 status = mod_install(&modlinkage); 2695 if (status != 0) { 2696 mac_fini_ops(&ral_dev_ops); 2697 ddi_soft_state_fini(&ral_soft_state_p); 2698 } 2699 return (status); 2700 } 2701 2702 int 2703 _fini(void) 2704 { 2705 int status; 2706 2707 status = mod_remove(&modlinkage); 2708 if (status == 0) { 2709 mac_fini_ops(&ral_dev_ops); 2710 ddi_soft_state_fini(&ral_soft_state_p); 2711 } 2712 return (status); 2713 } 2714