1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCIEB_H 27 #define _SYS_PCIEB_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #if defined(DEBUG) 34 #define PCIEB_DEBUG pcieb_dbg 35 extern void pcieb_dbg(uint_t bit, dev_info_t *dip, char *fmt, ...); 36 #else /* DEBUG */ 37 #define PCIEB_DEBUG 0 && 38 #endif /* DEBUG */ 39 40 typedef enum { /* same sequence as pcieb_debug_sym[] */ 41 /* 0 */ DBG_ATTACH, 42 /* 1 */ DBG_PWR, 43 /* 2 */ DBG_INTR 44 } pcieb_debug_bit_t; 45 46 /* 47 * Intel specific register offsets with bit definitions. 48 */ 49 #define PCIEB_PX_CAPABILITY_ID 0x44 50 #define PCIEB_BRIDGE_CONF 0x40 51 52 /* 53 * PCI/PCI-E Configuration register specific values. 54 */ 55 #define PX_PMODE 0x4000 /* PCI/PCIX Mode */ 56 #define PX_PFREQ_66 0x200 /* PCI clock frequency */ 57 #define PX_PFREQ_100 0x400 58 #define PX_PFREQ_133 0x600 59 #define PX_PMRE 0x80 /* Peer memory read enable */ 60 61 /* 62 * Downstream delayed transaction resource partitioning. 63 */ 64 #define PX_ODTP 0x40 /* Max. of two entries PX and PCI */ 65 66 /* 67 * Maximum upstream delayed transaction. 68 */ 69 #define PX_MDT_44 0x00 70 #define PX_MDT_11 0x01 71 #define PX_MDT_22 0x10 72 73 74 #define NUM_LOGICAL_SLOTS 32 75 #define PCIEB_RANGE_LEN 2 76 #define PCIEB_32BIT_IO 1 77 #define PCIEB_32bit_MEM 1 78 #define PCIEB_MEMGRAIN 0x100000 79 #define PCIEB_IOGRAIN 0x1000 80 81 #define PCIEB_16bit_IOADDR(addr) ((uint16_t)(((uint8_t)(addr) & 0xF0) << 8)) 82 #define PCIEB_LADDR(lo, hi) (((uint16_t)(hi) << 16) | (uint16_t)(lo)) 83 #define PCIEB_32bit_MEMADDR(addr) (PCIEB_LADDR(0, ((uint16_t)(addr) & 0xFFF0))) 84 85 /* 86 * The following typedef is used to represent an entry in the "ranges" 87 * property of a device node. 88 */ 89 typedef struct { 90 uint32_t child_high; 91 uint32_t child_mid; 92 uint32_t child_low; 93 uint32_t parent_high; 94 uint32_t parent_mid; 95 uint32_t parent_low; 96 uint32_t size_high; 97 uint32_t size_low; 98 } pcieb_ranges_t; 99 100 typedef enum { HPC_NONE, HPC_PCIE, HPC_SHPC, HPC_OUTBAND } pcieb_hpc_type_t; 101 102 typedef struct { 103 dev_info_t *pcieb_dip; 104 105 /* Hotplug support */ 106 boolean_t pcieb_hotplug_capable; 107 pcieb_hpc_type_t pcieb_hpc_type; 108 109 /* Interrupt support */ 110 ddi_intr_handle_t *pcieb_htable; /* Intr Handlers */ 111 int pcieb_htable_size; /* htable size */ 112 int pcieb_intr_count; /* Num of Intr */ 113 uint_t pcieb_intr_priority; /* Intr Priority */ 114 int pcieb_intr_type; /* (MSI | FIXED) */ 115 int pcieb_isr_tab[4]; /* MSI source offset */ 116 117 uint_t pcieb_soft_state; 118 int pcieb_init_flags; 119 kmutex_t pcieb_mutex; /* Soft state mutex */ 120 kmutex_t pcieb_intr_mutex; /* Intr handler mutex */ 121 kmutex_t pcieb_err_mutex; /* Error mutex */ 122 kmutex_t pcieb_peek_poke_mutex; /* Peekpoke mutex */ 123 124 /* FMA */ 125 boolean_t pcieb_no_aer_msi; 126 ddi_iblock_cookie_t pcieb_fm_ibc; 127 } pcieb_devstate_t; 128 129 /* 130 * soft state pointer 131 */ 132 extern void *pcieb_state; 133 134 /* soft state flags */ 135 #define PCIEB_SOFT_STATE_CLOSED 0x00 136 #define PCIEB_SOFT_STATE_OPEN 0x01 137 #define PCIEB_SOFT_STATE_OPEN_EXCL 0x02 138 139 /* init flags */ 140 #define PCIEB_INIT_MUTEX 0x01 141 #define PCIEB_INIT_HTABLE 0x02 142 #define PCIEB_INIT_ALLOC 0x04 143 #define PCIEB_INIT_HANDLER 0x08 144 #define PCIEB_INIT_ENABLE 0x10 145 #define PCIEB_INIT_BLOCK 0x20 146 #define PCIEB_INIT_FM 0x40 147 148 #define PCIEB_INTR_SRC_UNKNOWN 0x0 /* must be 0 */ 149 #define PCIEB_INTR_SRC_HP 0x1 150 #define PCIEB_INTR_SRC_PME 0x2 151 #define PCIEB_INTR_SRC_AER 0x4 152 153 /* 154 * Need to put vendor ids in a common file and not platform specific files 155 * as is done today. Until then putting this vendor id define here. 156 */ 157 #define NVIDIA_VENDOR_ID 0x10de /* Nvidia Vendor Id */ 158 159 #ifdef BCM_SW_WORKAROUNDS 160 161 /* Workaround for address space limitation in Broadcom 5714/5715 */ 162 #define PCIEB_ADDR_LIMIT_LO 0ull 163 #define PCIEB_ADDR_LIMIT_HI ((1ull << 40) - 1) 164 165 #endif /* BCM_SW_WORKAROUNDS */ 166 167 /* 168 * The following values are used to initialize the cache line size 169 * and latency timer registers for PCI, PCI-X and PCIe2PCI devices. 170 */ 171 #define PCIEB_CACHE_LINE_SIZE 0x10 /* 64 bytes in # of DWORDs */ 172 #define PCIEB_LATENCY_TIMER 0x40 /* 64 PCI cycles */ 173 174 extern void pcieb_set_pci_perf_parameters(dev_info_t *dip, 175 ddi_acc_handle_t config_handle); 176 extern void pcieb_plat_attach_workaround(dev_info_t *dip); 177 extern void pcieb_plat_intr_attach(pcieb_devstate_t *pcieb); 178 extern void pcieb_plat_initchild(dev_info_t *child); 179 extern void pcieb_plat_uninitchild(dev_info_t *child); 180 extern void pcieb_plat_ioctl_hotplug(dev_info_t *dip, int rv, int cmd); 181 extern int pcieb_plat_ctlops(dev_info_t *rdip, ddi_ctl_enum_t ctlop, 182 void *arg); 183 extern int pcieb_plat_pcishpc_probe(dev_info_t *dip, 184 ddi_acc_handle_t config_handle); 185 extern int pcieb_plat_peekpoke(dev_info_t *dip, dev_info_t *rdip, 186 ddi_ctl_enum_t ctlop, void *arg, void *result); 187 extern int pcieb_plat_intr_ops(dev_info_t *dip, dev_info_t *rdip, 188 ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result); 189 extern boolean_t pcieb_plat_msi_supported(dev_info_t *dip); 190 extern boolean_t pcieb_plat_pwr_disable(dev_info_t *dip); 191 192 #if defined(__i386) || defined(__amd64) 193 extern void pcieb_intel_error_workaround(dev_info_t *dip); 194 extern void pcieb_intel_serr_workaround(dev_info_t *dip, boolean_t mcheck); 195 extern void pcieb_intel_rber_workaround(dev_info_t *dip); 196 extern void pcieb_intel_sw_workaround(dev_info_t *dip); 197 extern void pcieb_intel_mps_workaround(dev_info_t *dip); 198 extern void pcieb_init_osc(dev_info_t *dip); 199 extern void pcieb_peekpoke_cb(dev_info_t *, ddi_fm_error_t *); 200 extern int pcishpc_init(dev_info_t *dip); 201 extern int pcishpc_uninit(dev_info_t *dip); 202 extern int pcishpc_intr(dev_info_t *dip); 203 #endif /* defined(__i386) || defined(__amd64) */ 204 205 #ifdef PX_PLX 206 extern void pcieb_attach_plx_workarounds(pcieb_devstate_t *pcieb); 207 extern int pcieb_init_plx_workarounds(pcieb_devstate_t *pcieb, 208 dev_info_t *child); 209 #endif /* PX_PLX */ 210 211 #ifdef __cplusplus 212 } 213 #endif 214 215 #endif /* _SYS_PCIEB_H */ 216