1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/nxge/nxge_impl.h> 27 #include <sys/nxge/nxge_mac.h> 28 #include <sys/nxge/nxge_hio.h> 29 30 /* 31 * Local defines for FWARC 2006/556 32 */ 33 #define NXGE_NIU_TDMA_PROP_LEN 2 34 #define NXGE_NIU_RDMA_PROP_LEN 2 35 #define NXGE_NIU_0_INTR_PROP_LEN 19 36 #define NXGE_NIU_1_INTR_PROP_LEN 17 37 38 /* 39 * Local functions. 40 */ 41 static void nxge_get_niu_property(dev_info_t *, niu_type_t *); 42 static nxge_status_t nxge_get_mac_addr_properties(p_nxge_t); 43 static nxge_status_t nxge_use_cfg_n2niu_properties(p_nxge_t); 44 static void nxge_use_cfg_neptune_properties(p_nxge_t); 45 static void nxge_use_cfg_dma_config(p_nxge_t); 46 static void nxge_use_cfg_vlan_class_config(p_nxge_t); 47 static void nxge_use_cfg_mac_class_config(p_nxge_t); 48 static void nxge_use_cfg_class_config(p_nxge_t); 49 static void nxge_use_cfg_link_cfg(p_nxge_t); 50 static void nxge_set_hw_dma_config(p_nxge_t); 51 static void nxge_set_hw_vlan_class_config(p_nxge_t); 52 static void nxge_set_hw_mac_class_config(p_nxge_t); 53 static void nxge_set_hw_class_config(p_nxge_t); 54 static nxge_status_t nxge_use_default_dma_config_n2(p_nxge_t); 55 static void nxge_ldgv_setup(p_nxge_ldg_t *, p_nxge_ldv_t *, uint8_t, 56 uint8_t, int *); 57 static void nxge_init_mmac(p_nxge_t, boolean_t); 58 static void nxge_set_rdc_intr_property(p_nxge_t); 59 60 uint32_t nxge_use_hw_property = 1; 61 uint32_t nxge_groups_per_port = 2; 62 63 extern uint32_t nxge_use_partition; 64 extern uint32_t nxge_dma_obp_props_only; 65 66 extern uint_t nxge_rx_intr(void *, void *); 67 extern uint_t nxge_tx_intr(void *, void *); 68 extern uint_t nxge_mif_intr(void *, void *); 69 extern uint_t nxge_mac_intr(void *, void *); 70 extern uint_t nxge_syserr_intr(void *, void *); 71 extern void *nxge_list; 72 73 #define NXGE_SHARED_REG_SW_SIM 74 75 #ifdef NXGE_SHARED_REG_SW_SIM 76 uint64_t global_dev_ctrl = 0; 77 #endif 78 79 #define MAX_SIBLINGS NXGE_MAX_PORTS 80 81 extern uint32_t nxge_rbr_size; 82 extern uint32_t nxge_rcr_size; 83 extern uint32_t nxge_tx_ring_size; 84 extern uint32_t nxge_rbr_spare_size; 85 86 extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t); 87 88 static uint8_t p2_tx_fair[2] = {12, 12}; 89 static uint8_t p2_tx_equal[2] = {12, 12}; 90 static uint8_t p4_tx_fair[4] = {6, 6, 6, 6}; 91 static uint8_t p4_tx_equal[4] = {6, 6, 6, 6}; 92 static uint8_t p2_rx_fair[2] = {8, 8}; 93 static uint8_t p2_rx_equal[2] = {8, 8}; 94 static uint8_t p4_rx_fair[4] = {4, 4, 4, 4}; 95 static uint8_t p4_rx_equal[4] = {4, 4, 4, 4}; 96 97 static uint8_t p2_rdcgrp_fair[2] = {4, 4}; 98 static uint8_t p2_rdcgrp_equal[2] = {4, 4}; 99 static uint8_t p4_rdcgrp_fair[4] = {2, 2, 1, 1}; 100 static uint8_t p4_rdcgrp_equal[4] = {2, 2, 2, 2}; 101 static uint8_t p2_rdcgrp_cls[2] = {1, 1}; 102 static uint8_t p4_rdcgrp_cls[4] = {1, 1, 1, 1}; 103 104 static uint8_t rx_4_1G[4] = {4, 4, 4, 4}; 105 static uint8_t rx_2_10G[2] = {8, 8}; 106 static uint8_t rx_2_10G_2_1G[4] = {6, 6, 2, 2}; 107 static uint8_t rx_1_10G_3_1G[4] = {10, 2, 2, 2}; 108 static uint8_t rx_1_1G_1_10G_2_1G[4] = {2, 10, 2, 2}; 109 110 static uint8_t tx_4_1G[4] = {6, 6, 6, 6}; 111 static uint8_t tx_2_10G[2] = {12, 12}; 112 static uint8_t tx_2_10G_2_1G[4] = {10, 10, 2, 2}; 113 static uint8_t tx_1_10G_3_1G[4] = {12, 4, 4, 4}; 114 static uint8_t tx_1_1G_1_10G_2_1G[4] = {4, 12, 4, 4}; 115 116 typedef enum { 117 DEFAULT = 0, 118 EQUAL, 119 FAIR, 120 CUSTOM, 121 CLASSIFY, 122 L2_CLASSIFY, 123 L3_DISTRIBUTE, 124 L3_CLASSIFY, 125 L3_TCAM, 126 CONFIG_TOKEN_NONE 127 } config_token_t; 128 129 static char *token_names[] = { 130 "default", 131 "equal", 132 "fair", 133 "custom", 134 "classify", 135 "l2_classify", 136 "l3_distribute", 137 "l3_classify", 138 "l3_tcam", 139 "none", 140 }; 141 142 void nxge_virint_regs_dump(p_nxge_t nxgep); 143 144 void 145 nxge_virint_regs_dump(p_nxge_t nxgep) 146 { 147 npi_handle_t handle; 148 149 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_virint_regs_dump")); 150 handle = NXGE_DEV_NPI_HANDLE(nxgep); 151 (void) npi_vir_dump_pio_fzc_regs_one(handle); 152 (void) npi_vir_dump_ldgnum(handle); 153 (void) npi_vir_dump_ldsv(handle); 154 (void) npi_vir_dump_imask0(handle); 155 (void) npi_vir_dump_sid(handle); 156 (void) npi_mac_dump_regs(handle, nxgep->function_num); 157 (void) npi_ipp_dump_regs(handle, nxgep->function_num); 158 (void) npi_fflp_dump_regs(handle); 159 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_virint_regs_dump")); 160 } 161 162 /* 163 * For now: we hard coded the DMA configurations. 164 * and assume for one partition only. 165 * 166 * OBP. Then OBP will pass this partition's 167 * Neptune configurations to fcode to create 168 * properties for them. 169 * 170 * Since Neptune(PCI-E) and NIU (Niagara-2) has 171 * different bus interfaces, the driver needs 172 * to know which bus it is connected to. 173 * Ravinder suggested: create a device property. 174 * In partitioning environment, we cannot 175 * use .conf file (need to check). If conf changes, 176 * need to reboot the system. 177 * The following function assumes that we will 178 * retrieve its properties from a virtualized nexus driver. 179 */ 180 181 nxge_status_t 182 nxge_cntlops(dev_info_t *dip, nxge_ctl_enum_t ctlop, void *arg, void *result) 183 { 184 nxge_status_t status = NXGE_OK; 185 int instance; 186 p_nxge_t nxgep; 187 188 #ifndef NXGE_SHARED_REG_SW_SIM 189 npi_handle_t handle; 190 uint16_t sr16, cr16; 191 #endif 192 instance = ddi_get_instance(dip); 193 NXGE_DEBUG_MSG((NULL, VIR_CTL, "Instance %d ", instance)); 194 195 if (nxge_list == NULL) { 196 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 197 "nxge_cntlops: nxge_list null")); 198 return (NXGE_ERROR); 199 } 200 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 201 if (nxgep == NULL) { 202 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 203 "nxge_cntlops: nxgep null")); 204 return (NXGE_ERROR); 205 } 206 #ifndef NXGE_SHARED_REG_SW_SIM 207 handle = nxgep->npi_reg_handle; 208 #endif 209 switch (ctlop) { 210 case NXGE_CTLOPS_NIUTYPE: 211 nxge_get_niu_property(dip, (niu_type_t *)result); 212 return (status); 213 214 case NXGE_CTLOPS_GET_SHARED_REG: 215 #ifdef NXGE_SHARED_REG_SW_SIM 216 *(uint64_t *)result = global_dev_ctrl; 217 return (0); 218 #else 219 status = npi_dev_func_sr_sr_get(handle, &sr16); 220 *(uint16_t *)result = sr16; 221 NXGE_DEBUG_MSG((NULL, VIR_CTL, 222 "nxge_cntlops: NXGE_CTLOPS_GET_SHARED_REG")); 223 return (0); 224 #endif 225 226 case NXGE_CTLOPS_SET_SHARED_REG_LOCK: 227 #ifdef NXGE_SHARED_REG_SW_SIM 228 global_dev_ctrl = *(uint64_t *)arg; 229 return (0); 230 #else 231 status = NPI_FAILURE; 232 while (status != NPI_SUCCESS) 233 status = npi_dev_func_sr_lock_enter(handle); 234 235 sr16 = *(uint16_t *)arg; 236 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 237 status = npi_dev_func_sr_lock_free(handle); 238 NXGE_DEBUG_MSG((NULL, VIR_CTL, 239 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 240 return (0); 241 #endif 242 243 case NXGE_CTLOPS_UPDATE_SHARED_REG: 244 #ifdef NXGE_SHARED_REG_SW_SIM 245 global_dev_ctrl |= *(uint64_t *)arg; 246 return (0); 247 #else 248 status = NPI_FAILURE; 249 while (status != NPI_SUCCESS) 250 status = npi_dev_func_sr_lock_enter(handle); 251 status = npi_dev_func_sr_sr_get(handle, &sr16); 252 sr16 |= *(uint16_t *)arg; 253 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 254 status = npi_dev_func_sr_lock_free(handle); 255 NXGE_DEBUG_MSG((NULL, VIR_CTL, 256 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 257 return (0); 258 #endif 259 260 case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG_UL: 261 #ifdef NXGE_SHARED_REG_SW_SIM 262 global_dev_ctrl |= *(uint64_t *)arg; 263 return (0); 264 #else 265 status = npi_dev_func_sr_sr_get(handle, &sr16); 266 cr16 = *(uint16_t *)arg; 267 sr16 &= ~cr16; 268 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 269 NXGE_DEBUG_MSG((NULL, VIR_CTL, 270 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 271 return (0); 272 #endif 273 274 case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG: 275 #ifdef NXGE_SHARED_REG_SW_SIM 276 global_dev_ctrl |= *(uint64_t *)arg; 277 return (0); 278 #else 279 status = NPI_FAILURE; 280 while (status != NPI_SUCCESS) 281 status = npi_dev_func_sr_lock_enter(handle); 282 status = npi_dev_func_sr_sr_get(handle, &sr16); 283 cr16 = *(uint16_t *)arg; 284 sr16 &= ~cr16; 285 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 286 status = npi_dev_func_sr_lock_free(handle); 287 NXGE_DEBUG_MSG((NULL, VIR_CTL, 288 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 289 return (0); 290 #endif 291 292 case NXGE_CTLOPS_GET_LOCK_BLOCK: 293 #ifdef NXGE_SHARED_REG_SW_SIM 294 global_dev_ctrl |= *(uint64_t *)arg; 295 return (0); 296 #else 297 status = NPI_FAILURE; 298 while (status != NPI_SUCCESS) 299 status = npi_dev_func_sr_lock_enter(handle); 300 NXGE_DEBUG_MSG((NULL, VIR_CTL, 301 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_BLOCK")); 302 return (0); 303 #endif 304 case NXGE_CTLOPS_GET_LOCK_TRY: 305 #ifdef NXGE_SHARED_REG_SW_SIM 306 global_dev_ctrl |= *(uint64_t *)arg; 307 return (0); 308 #else 309 status = npi_dev_func_sr_lock_enter(handle); 310 NXGE_DEBUG_MSG((NULL, VIR_CTL, 311 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_TRY")); 312 if (status == NPI_SUCCESS) 313 return (NXGE_OK); 314 else 315 return (NXGE_ERROR); 316 #endif 317 case NXGE_CTLOPS_FREE_LOCK: 318 #ifdef NXGE_SHARED_REG_SW_SIM 319 global_dev_ctrl |= *(uint64_t *)arg; 320 return (0); 321 #else 322 status = npi_dev_func_sr_lock_free(handle); 323 NXGE_DEBUG_MSG((NULL, VIR_CTL, 324 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_FREE")); 325 if (status == NPI_SUCCESS) 326 return (NXGE_OK); 327 else 328 return (NXGE_ERROR); 329 #endif 330 331 default: 332 status = NXGE_ERROR; 333 } 334 335 return (status); 336 } 337 338 void 339 nxge_common_lock_get(p_nxge_t nxgep) 340 { 341 uint32_t status = NPI_FAILURE; 342 npi_handle_t handle; 343 344 #if defined(NXGE_SHARE_REG_SW_SIM) 345 return; 346 #endif 347 handle = nxgep->npi_reg_handle; 348 while (status != NPI_SUCCESS) 349 status = npi_dev_func_sr_lock_enter(handle); 350 } 351 352 void 353 nxge_common_lock_free(p_nxge_t nxgep) 354 { 355 npi_handle_t handle; 356 357 #if defined(NXGE_SHARE_REG_SW_SIM) 358 return; 359 #endif 360 handle = nxgep->npi_reg_handle; 361 (void) npi_dev_func_sr_lock_free(handle); 362 } 363 364 365 static void 366 nxge_get_niu_property(dev_info_t *dip, niu_type_t *niu_type) 367 { 368 uchar_t *prop_val; 369 uint_t prop_len; 370 371 *niu_type = NIU_TYPE_NONE; 372 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, 373 "niu-type", (uchar_t **)&prop_val, 374 &prop_len) == DDI_PROP_SUCCESS) { 375 if (strncmp("niu", (caddr_t)prop_val, (size_t)prop_len) == 0) { 376 *niu_type = N2_NIU; 377 } 378 ddi_prop_free(prop_val); 379 } 380 } 381 382 static config_token_t 383 nxge_get_config_token(char *prop) 384 { 385 config_token_t token = DEFAULT; 386 387 while (token < CONFIG_TOKEN_NONE) { 388 if (strncmp(prop, token_names[token], 4) == 0) 389 break; 390 token++; 391 } 392 return (token); 393 } 394 395 /* per port */ 396 397 static nxge_status_t 398 nxge_update_rxdma_grp_properties(p_nxge_t nxgep, config_token_t token, 399 dev_info_t *s_dip[]) 400 { 401 nxge_status_t status = NXGE_OK; 402 int ddi_status; 403 int num_ports = nxgep->nports; 404 int port, bits, j; 405 uint8_t start_grp = 0, num_grps = 0; 406 p_nxge_param_t param_arr; 407 uint32_t grp_bitmap[MAX_SIBLINGS]; 408 int custom_start_grp[MAX_SIBLINGS]; 409 int custom_num_grp[MAX_SIBLINGS]; 410 uint8_t bad_config = B_FALSE; 411 char *start_prop, *num_prop, *cfg_prop; 412 413 start_grp = 0; 414 param_arr = nxgep->param_arr; 415 start_prop = param_arr[param_rdc_grps_start].fcode_name; 416 num_prop = param_arr[param_rx_rdc_grps].fcode_name; 417 418 switch (token) { 419 case FAIR: 420 cfg_prop = "fair"; 421 for (port = 0; port < num_ports; port++) { 422 custom_num_grp[port] = 423 (num_ports == 4) ? 424 p4_rdcgrp_fair[port] : 425 p2_rdcgrp_fair[port]; 426 custom_start_grp[port] = start_grp; 427 start_grp += custom_num_grp[port]; 428 } 429 break; 430 431 case EQUAL: 432 cfg_prop = "equal"; 433 for (port = 0; port < num_ports; port++) { 434 custom_num_grp[port] = 435 (num_ports == 4) ? 436 p4_rdcgrp_equal[port] : 437 p2_rdcgrp_equal[port]; 438 custom_start_grp[port] = start_grp; 439 start_grp += custom_num_grp[port]; 440 } 441 break; 442 443 444 case CLASSIFY: 445 cfg_prop = "classify"; 446 for (port = 0; port < num_ports; port++) { 447 custom_num_grp[port] = (num_ports == 4) ? 448 p4_rdcgrp_cls[port] : p2_rdcgrp_cls[port]; 449 custom_start_grp[port] = start_grp; 450 start_grp += custom_num_grp[port]; 451 } 452 break; 453 454 case CUSTOM: 455 cfg_prop = "custom"; 456 /* See if it is good config */ 457 num_grps = 0; 458 for (port = 0; port < num_ports; port++) { 459 custom_start_grp[port] = 460 ddi_prop_get_int(DDI_DEV_T_NONE, s_dip[port], 461 DDI_PROP_DONTPASS, start_prop, -1); 462 if ((custom_start_grp[port] == -1) || 463 (custom_start_grp[port] >= 464 NXGE_MAX_RDC_GRPS)) { 465 bad_config = B_TRUE; 466 break; 467 } 468 custom_num_grp[port] = ddi_prop_get_int( 469 DDI_DEV_T_NONE, 470 s_dip[port], 471 DDI_PROP_DONTPASS, 472 num_prop, -1); 473 474 if ((custom_num_grp[port] == -1) || 475 (custom_num_grp[port] > 476 NXGE_MAX_RDC_GRPS) || 477 ((custom_num_grp[port] + 478 custom_start_grp[port]) >= 479 NXGE_MAX_RDC_GRPS)) { 480 bad_config = B_TRUE; 481 break; 482 } 483 num_grps += custom_num_grp[port]; 484 if (num_grps > NXGE_MAX_RDC_GRPS) { 485 bad_config = B_TRUE; 486 break; 487 } 488 grp_bitmap[port] = 0; 489 for (bits = 0; 490 bits < custom_num_grp[port]; 491 bits++) { 492 grp_bitmap[port] |= 493 (1 << (bits + custom_start_grp[port])); 494 } 495 496 } 497 498 if (bad_config == B_FALSE) { 499 /* check for overlap */ 500 for (port = 0; port < num_ports - 1; port++) { 501 for (j = port + 1; j < num_ports; j++) { 502 if (grp_bitmap[port] & 503 grp_bitmap[j]) { 504 bad_config = B_TRUE; 505 break; 506 } 507 } 508 if (bad_config == B_TRUE) 509 break; 510 } 511 } 512 if (bad_config == B_TRUE) { 513 /* use default config */ 514 for (port = 0; port < num_ports; port++) { 515 custom_num_grp[port] = 516 (num_ports == 4) ? 517 p4_rx_fair[port] : p2_rx_fair[port]; 518 custom_start_grp[port] = start_grp; 519 start_grp += custom_num_grp[port]; 520 } 521 } 522 break; 523 524 default: 525 /* use default config */ 526 cfg_prop = "fair"; 527 for (port = 0; port < num_ports; port++) { 528 custom_num_grp[port] = (num_ports == 4) ? 529 p4_rx_fair[port] : p2_rx_fair[port]; 530 custom_start_grp[port] = start_grp; 531 start_grp += custom_num_grp[port]; 532 } 533 break; 534 } 535 536 /* Now Update the rx properties */ 537 for (port = 0; port < num_ports; port++) { 538 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port], 539 "rxdma-grp-cfg", cfg_prop); 540 if (ddi_status != DDI_PROP_SUCCESS) { 541 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 542 " property %s not updating", 543 cfg_prop)); 544 status |= NXGE_DDI_FAILED; 545 } 546 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 547 num_prop, custom_num_grp[port]); 548 549 if (ddi_status != DDI_PROP_SUCCESS) { 550 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 551 " property %s not updating", 552 num_prop)); 553 status |= NXGE_DDI_FAILED; 554 } 555 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 556 start_prop, custom_start_grp[port]); 557 558 if (ddi_status != DDI_PROP_SUCCESS) { 559 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 560 " property %s not updating", 561 start_prop)); 562 status |= NXGE_DDI_FAILED; 563 } 564 } 565 if (status & NXGE_DDI_FAILED) 566 status |= NXGE_ERROR; 567 568 return (status); 569 } 570 571 static nxge_status_t 572 nxge_update_rxdma_properties(p_nxge_t nxgep, config_token_t token, 573 dev_info_t *s_dip[]) 574 { 575 nxge_status_t status = NXGE_OK; 576 int ddi_status; 577 int num_ports = nxgep->nports; 578 int port, bits, j; 579 uint8_t start_rdc = 0, num_rdc = 0; 580 p_nxge_param_t param_arr; 581 uint32_t rdc_bitmap[MAX_SIBLINGS]; 582 int custom_start_rdc[MAX_SIBLINGS]; 583 int custom_num_rdc[MAX_SIBLINGS]; 584 uint8_t bad_config = B_FALSE; 585 int *prop_val; 586 uint_t prop_len; 587 char *start_rdc_prop, *num_rdc_prop, *cfg_prop; 588 589 start_rdc = 0; 590 param_arr = nxgep->param_arr; 591 start_rdc_prop = param_arr[param_rxdma_channels_begin].fcode_name; 592 num_rdc_prop = param_arr[param_rxdma_channels].fcode_name; 593 594 switch (token) { 595 case FAIR: 596 cfg_prop = "fair"; 597 for (port = 0; port < num_ports; port++) { 598 custom_num_rdc[port] = (num_ports == 4) ? 599 p4_rx_fair[port] : p2_rx_fair[port]; 600 custom_start_rdc[port] = start_rdc; 601 start_rdc += custom_num_rdc[port]; 602 } 603 break; 604 605 case EQUAL: 606 cfg_prop = "equal"; 607 for (port = 0; port < num_ports; port++) { 608 custom_num_rdc[port] = (num_ports == 4) ? 609 p4_rx_equal[port] : 610 p2_rx_equal[port]; 611 custom_start_rdc[port] = start_rdc; 612 start_rdc += custom_num_rdc[port]; 613 } 614 break; 615 616 case CUSTOM: 617 cfg_prop = "custom"; 618 /* See if it is good config */ 619 num_rdc = 0; 620 for (port = 0; port < num_ports; port++) { 621 ddi_status = ddi_prop_lookup_int_array( 622 DDI_DEV_T_ANY, 623 s_dip[port], 0, 624 start_rdc_prop, 625 &prop_val, 626 &prop_len); 627 if (ddi_status == DDI_SUCCESS) 628 custom_start_rdc[port] = *prop_val; 629 else { 630 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 631 " %s custom start port %d" 632 " read failed ", 633 " rxdma-cfg", port)); 634 bad_config = B_TRUE; 635 status |= NXGE_DDI_FAILED; 636 } 637 if ((custom_start_rdc[port] == -1) || 638 (custom_start_rdc[port] >= 639 NXGE_MAX_RDCS)) { 640 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 641 " %s custom start %d" 642 " out of range %x ", 643 " rxdma-cfg", 644 port, 645 custom_start_rdc[port])); 646 bad_config = B_TRUE; 647 break; 648 } 649 ddi_status = ddi_prop_lookup_int_array( 650 DDI_DEV_T_ANY, 651 s_dip[port], 652 0, 653 num_rdc_prop, 654 &prop_val, 655 &prop_len); 656 657 if (ddi_status == DDI_SUCCESS) 658 custom_num_rdc[port] = *prop_val; 659 else { 660 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 661 " %s custom num port %d" 662 " read failed ", 663 "rxdma-cfg", port)); 664 bad_config = B_TRUE; 665 status |= NXGE_DDI_FAILED; 666 } 667 668 if ((custom_num_rdc[port] == -1) || 669 (custom_num_rdc[port] > 670 NXGE_MAX_RDCS) || 671 ((custom_num_rdc[port] + 672 custom_start_rdc[port]) > 673 NXGE_MAX_RDCS)) { 674 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 675 " %s custom num %d" 676 " out of range %x ", 677 " rxdma-cfg", 678 port, custom_num_rdc[port])); 679 bad_config = B_TRUE; 680 break; 681 } 682 num_rdc += custom_num_rdc[port]; 683 if (num_rdc > NXGE_MAX_RDCS) { 684 bad_config = B_TRUE; 685 break; 686 } 687 rdc_bitmap[port] = 0; 688 for (bits = 0; 689 bits < custom_num_rdc[port]; bits++) { 690 rdc_bitmap[port] |= 691 (1 << (bits + custom_start_rdc[port])); 692 } 693 } 694 695 if (bad_config == B_FALSE) { 696 /* check for overlap */ 697 for (port = 0; port < num_ports - 1; port++) { 698 for (j = port + 1; j < num_ports; j++) { 699 if (rdc_bitmap[port] & 700 rdc_bitmap[j]) { 701 NXGE_DEBUG_MSG((nxgep, 702 CFG_CTL, 703 " rxdma-cfg" 704 " property custom" 705 " bit overlap" 706 " %d %d ", 707 port, j)); 708 bad_config = B_TRUE; 709 break; 710 } 711 } 712 if (bad_config == B_TRUE) 713 break; 714 } 715 } 716 if (bad_config == B_TRUE) { 717 /* use default config */ 718 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 719 " rxdma-cfg property:" 720 " bad custom config:" 721 " use default")); 722 for (port = 0; port < num_ports; port++) { 723 custom_num_rdc[port] = 724 (num_ports == 4) ? 725 p4_rx_fair[port] : 726 p2_rx_fair[port]; 727 custom_start_rdc[port] = start_rdc; 728 start_rdc += custom_num_rdc[port]; 729 } 730 } 731 break; 732 733 default: 734 /* use default config */ 735 cfg_prop = "fair"; 736 for (port = 0; port < num_ports; port++) { 737 custom_num_rdc[port] = (num_ports == 4) ? 738 p4_rx_fair[port] : p2_rx_fair[port]; 739 custom_start_rdc[port] = start_rdc; 740 start_rdc += custom_num_rdc[port]; 741 } 742 break; 743 } 744 745 /* Now Update the rx properties */ 746 for (port = 0; port < num_ports; port++) { 747 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 748 " update property rxdma-cfg with %s ", cfg_prop)); 749 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port], 750 "rxdma-cfg", cfg_prop); 751 if (ddi_status != DDI_PROP_SUCCESS) { 752 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 753 " property rxdma-cfg is not updating to %s", 754 cfg_prop)); 755 status |= NXGE_DDI_FAILED; 756 } 757 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 758 num_rdc_prop, custom_num_rdc[port])); 759 760 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 761 num_rdc_prop, custom_num_rdc[port]); 762 763 if (ddi_status != DDI_PROP_SUCCESS) { 764 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 765 " property %s not updating with %d", 766 num_rdc_prop, custom_num_rdc[port])); 767 status |= NXGE_DDI_FAILED; 768 } 769 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 770 start_rdc_prop, custom_start_rdc[port])); 771 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 772 start_rdc_prop, custom_start_rdc[port]); 773 774 if (ddi_status != DDI_PROP_SUCCESS) { 775 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 776 " property %s not updating with %d ", 777 start_rdc_prop, custom_start_rdc[port])); 778 status |= NXGE_DDI_FAILED; 779 } 780 } 781 if (status & NXGE_DDI_FAILED) 782 status |= NXGE_ERROR; 783 return (status); 784 } 785 786 static nxge_status_t 787 nxge_update_txdma_properties(p_nxge_t nxgep, config_token_t token, 788 dev_info_t *s_dip[]) 789 { 790 nxge_status_t status = NXGE_OK; 791 int ddi_status = DDI_SUCCESS; 792 int num_ports = nxgep->nports; 793 int port, bits, j; 794 uint8_t start_tdc, num_tdc = 0; 795 p_nxge_param_t param_arr; 796 uint32_t tdc_bitmap[MAX_SIBLINGS]; 797 int custom_start_tdc[MAX_SIBLINGS]; 798 int custom_num_tdc[MAX_SIBLINGS]; 799 uint8_t bad_config = B_FALSE; 800 int *prop_val; 801 uint_t prop_len; 802 char *start_tdc_prop, *num_tdc_prop, *cfg_prop; 803 804 start_tdc = 0; 805 param_arr = nxgep->param_arr; 806 start_tdc_prop = param_arr[param_txdma_channels_begin].fcode_name; 807 num_tdc_prop = param_arr[param_txdma_channels].fcode_name; 808 809 switch (token) { 810 case FAIR: 811 cfg_prop = "fair"; 812 for (port = 0; port < num_ports; port++) { 813 custom_num_tdc[port] = (num_ports == 4) ? 814 p4_tx_fair[port] : p2_tx_fair[port]; 815 custom_start_tdc[port] = start_tdc; 816 start_tdc += custom_num_tdc[port]; 817 } 818 break; 819 820 case EQUAL: 821 cfg_prop = "equal"; 822 for (port = 0; port < num_ports; port++) { 823 custom_num_tdc[port] = (num_ports == 4) ? 824 p4_tx_equal[port] : p2_tx_equal[port]; 825 custom_start_tdc[port] = start_tdc; 826 start_tdc += custom_num_tdc[port]; 827 } 828 break; 829 830 case CUSTOM: 831 cfg_prop = "custom"; 832 /* See if it is good config */ 833 num_tdc = 0; 834 for (port = 0; port < num_ports; port++) { 835 ddi_status = ddi_prop_lookup_int_array( 836 DDI_DEV_T_ANY, s_dip[port], 0, start_tdc_prop, 837 &prop_val, &prop_len); 838 if (ddi_status == DDI_SUCCESS) 839 custom_start_tdc[port] = *prop_val; 840 else { 841 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 842 " %s custom start port %d" 843 " read failed ", " txdma-cfg", port)); 844 bad_config = B_TRUE; 845 status |= NXGE_DDI_FAILED; 846 } 847 848 if ((custom_start_tdc[port] == -1) || 849 (custom_start_tdc[port] >= 850 NXGE_MAX_RDCS)) { 851 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 852 " %s custom start %d" 853 " out of range %x ", " txdma-cfg", 854 port, custom_start_tdc[port])); 855 bad_config = B_TRUE; 856 break; 857 } 858 859 ddi_status = ddi_prop_lookup_int_array( 860 DDI_DEV_T_ANY, s_dip[port], 0, num_tdc_prop, 861 &prop_val, &prop_len); 862 if (ddi_status == DDI_SUCCESS) 863 custom_num_tdc[port] = *prop_val; 864 else { 865 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 866 " %s custom num port %d" 867 " read failed ", " txdma-cfg", port)); 868 bad_config = B_TRUE; 869 status |= NXGE_DDI_FAILED; 870 } 871 872 if ((custom_num_tdc[port] == -1) || 873 (custom_num_tdc[port] > 874 NXGE_MAX_TDCS) || 875 ((custom_num_tdc[port] + 876 custom_start_tdc[port]) > 877 NXGE_MAX_TDCS)) { 878 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 879 " %s custom num %d" 880 " out of range %x ", " rxdma-cfg", 881 port, custom_num_tdc[port])); 882 bad_config = B_TRUE; 883 break; 884 } 885 num_tdc += custom_num_tdc[port]; 886 if (num_tdc > NXGE_MAX_TDCS) { 887 bad_config = B_TRUE; 888 break; 889 } 890 tdc_bitmap[port] = 0; 891 for (bits = 0; 892 bits < custom_num_tdc[port]; bits++) { 893 tdc_bitmap[port] |= 894 (1 << 895 (bits + custom_start_tdc[port])); 896 } 897 898 } 899 900 if (bad_config == B_FALSE) { 901 /* check for overlap */ 902 for (port = 0; port < num_ports - 1; port++) { 903 for (j = port + 1; j < num_ports; j++) { 904 if (tdc_bitmap[port] & 905 tdc_bitmap[j]) { 906 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 907 " rxdma-cfg" 908 " property custom" 909 " bit overlap" 910 " %d %d ", 911 port, j)); 912 bad_config = B_TRUE; 913 break; 914 } 915 } 916 if (bad_config == B_TRUE) 917 break; 918 } 919 } 920 if (bad_config == B_TRUE) { 921 /* use default config */ 922 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 923 " txdma-cfg property:" 924 " bad custom config:" " use default")); 925 926 for (port = 0; port < num_ports; port++) { 927 custom_num_tdc[port] = (num_ports == 4) ? 928 p4_tx_fair[port] : p2_tx_fair[port]; 929 custom_start_tdc[port] = start_tdc; 930 start_tdc += custom_num_tdc[port]; 931 } 932 } 933 break; 934 935 default: 936 /* use default config */ 937 cfg_prop = "fair"; 938 for (port = 0; port < num_ports; port++) { 939 custom_num_tdc[port] = (num_ports == 4) ? 940 p4_tx_fair[port] : p2_tx_fair[port]; 941 custom_start_tdc[port] = start_tdc; 942 start_tdc += custom_num_tdc[port]; 943 } 944 break; 945 } 946 947 /* Now Update the tx properties */ 948 for (port = 0; port < num_ports; port++) { 949 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 950 " update property txdma-cfg with %s ", cfg_prop)); 951 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port], 952 "txdma-cfg", cfg_prop); 953 if (ddi_status != DDI_PROP_SUCCESS) { 954 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 955 " property txdma-cfg is not updating to %s", 956 cfg_prop)); 957 status |= NXGE_DDI_FAILED; 958 } 959 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 960 num_tdc_prop, custom_num_tdc[port])); 961 962 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 963 num_tdc_prop, custom_num_tdc[port]); 964 965 if (ddi_status != DDI_PROP_SUCCESS) { 966 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 967 " property %s not updating with %d", 968 num_tdc_prop, 969 custom_num_tdc[port])); 970 status |= NXGE_DDI_FAILED; 971 } 972 973 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 974 start_tdc_prop, custom_start_tdc[port])); 975 976 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 977 start_tdc_prop, custom_start_tdc[port]); 978 if (ddi_status != DDI_PROP_SUCCESS) { 979 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 980 " property %s not updating with %d ", 981 start_tdc_prop, custom_start_tdc[port])); 982 status |= NXGE_DDI_FAILED; 983 } 984 } 985 if (status & NXGE_DDI_FAILED) 986 status |= NXGE_ERROR; 987 return (status); 988 } 989 990 static nxge_status_t 991 nxge_update_cfg_properties(p_nxge_t nxgep, uint32_t flags, 992 config_token_t token, dev_info_t *s_dip[]) 993 { 994 nxge_status_t status = NXGE_OK; 995 996 switch (flags) { 997 case COMMON_TXDMA_CFG: 998 if (nxge_dma_obp_props_only == 0) 999 status = nxge_update_txdma_properties(nxgep, 1000 token, s_dip); 1001 break; 1002 case COMMON_RXDMA_CFG: 1003 if (nxge_dma_obp_props_only == 0) 1004 status = nxge_update_rxdma_properties(nxgep, 1005 token, s_dip); 1006 1007 break; 1008 case COMMON_RXDMA_GRP_CFG: 1009 status = nxge_update_rxdma_grp_properties(nxgep, 1010 token, s_dip); 1011 break; 1012 default: 1013 return (NXGE_ERROR); 1014 } 1015 return (status); 1016 } 1017 1018 /* 1019 * verify consistence. 1020 * (May require publishing the properties on all the ports. 1021 * 1022 * What if properties are published on function 0 device only? 1023 * 1024 * 1025 * rxdma-cfg, txdma-cfg, rxdma-grp-cfg (required ) 1026 * What about class configs? 1027 * 1028 * If consistent, update the property on all the siblings. 1029 * set a flag on hardware shared register 1030 * The rest of the siblings will check the flag 1031 * if the flag is set, they will use the updated property 1032 * without doing any validation. 1033 */ 1034 1035 nxge_status_t 1036 nxge_cfg_verify_set_classify_prop(p_nxge_t nxgep, char *prop, 1037 uint64_t known_cfg, uint32_t override, dev_info_t *c_dip[]) 1038 { 1039 nxge_status_t status = NXGE_OK; 1040 int ddi_status = DDI_SUCCESS; 1041 int i = 0, found = 0, update_prop = B_TRUE; 1042 int *cfg_val; 1043 uint_t new_value, cfg_value[MAX_SIBLINGS]; 1044 uint_t prop_len; 1045 uint_t known_cfg_value; 1046 1047 known_cfg_value = (uint_t)known_cfg; 1048 1049 if (override == B_TRUE) { 1050 new_value = known_cfg_value; 1051 for (i = 0; i < nxgep->nports; i++) { 1052 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, 1053 c_dip[i], prop, new_value); 1054 #ifdef NXGE_DEBUG_ERROR 1055 if (ddi_status != DDI_PROP_SUCCESS) 1056 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1057 " property %s failed update ", prop)); 1058 #endif 1059 } 1060 if (ddi_status != DDI_PROP_SUCCESS) 1061 return (NXGE_ERROR | NXGE_DDI_FAILED); 1062 } 1063 for (i = 0; i < nxgep->nports; i++) { 1064 cfg_value[i] = known_cfg_value; 1065 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, c_dip[i], 0, 1066 prop, &cfg_val, 1067 &prop_len) == DDI_PROP_SUCCESS) { 1068 cfg_value[i] = *cfg_val; 1069 ddi_prop_free(cfg_val); 1070 found++; 1071 } 1072 } 1073 1074 if (found != i) { 1075 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1076 " property %s not specified on all ports", prop)); 1077 if (found == 0) { 1078 /* not specified: Use default */ 1079 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1080 " property %s not specified on any port:" 1081 " Using default", prop)); 1082 new_value = known_cfg_value; 1083 } else { 1084 /* specified on some */ 1085 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1086 " property %s not specified" 1087 " on some ports: Using default", prop)); 1088 /* ? use p0 value instead ? */ 1089 new_value = known_cfg_value; 1090 } 1091 } else { 1092 /* check type and consistence */ 1093 /* found on all devices */ 1094 for (i = 1; i < found; i++) { 1095 if (cfg_value[i] != cfg_value[i - 1]) { 1096 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1097 " property %s inconsistent:" 1098 " Using default", prop)); 1099 new_value = known_cfg_value; 1100 break; 1101 } 1102 /* 1103 * Found on all the ports and consistent. Nothing to 1104 * do. 1105 */ 1106 update_prop = B_FALSE; 1107 } 1108 } 1109 1110 if (update_prop == B_TRUE) { 1111 for (i = 0; i < nxgep->nports; i++) { 1112 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, 1113 c_dip[i], prop, new_value); 1114 #ifdef NXGE_DEBUG_ERROR 1115 if (ddi_status != DDI_SUCCESS) 1116 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1117 " property %s not updating with %d" 1118 " Using default", 1119 prop, new_value)); 1120 #endif 1121 if (ddi_status != DDI_PROP_SUCCESS) 1122 status |= NXGE_DDI_FAILED; 1123 } 1124 } 1125 if (status & NXGE_DDI_FAILED) 1126 status |= NXGE_ERROR; 1127 1128 return (status); 1129 } 1130 1131 static uint64_t 1132 nxge_class_get_known_cfg(p_nxge_t nxgep, int class_prop, int rx_quick_cfg) 1133 { 1134 int start_prop; 1135 uint64_t cfg_value; 1136 p_nxge_param_t param_arr; 1137 1138 param_arr = nxgep->param_arr; 1139 cfg_value = param_arr[class_prop].value; 1140 start_prop = param_h1_init_value; 1141 1142 /* update the properties per quick config */ 1143 switch (rx_quick_cfg) { 1144 case CFG_L3_WEB: 1145 case CFG_L3_DISTRIBUTE: 1146 cfg_value = nxge_classify_get_cfg_value(nxgep, 1147 rx_quick_cfg, class_prop - start_prop); 1148 break; 1149 default: 1150 cfg_value = param_arr[class_prop].value; 1151 break; 1152 } 1153 return (cfg_value); 1154 } 1155 1156 static nxge_status_t 1157 nxge_cfg_verify_set_classify(p_nxge_t nxgep, dev_info_t *c_dip[]) 1158 { 1159 nxge_status_t status = NXGE_OK; 1160 int rx_quick_cfg, class_prop, start_prop, end_prop; 1161 char *prop_name; 1162 int override = B_TRUE; 1163 uint64_t cfg_value; 1164 p_nxge_param_t param_arr; 1165 1166 param_arr = nxgep->param_arr; 1167 rx_quick_cfg = param_arr[param_rx_quick_cfg].value; 1168 start_prop = param_h1_init_value; 1169 end_prop = param_class_opt_ipv6_sctp; 1170 1171 /* update the properties per quick config */ 1172 if (rx_quick_cfg == CFG_NOT_SPECIFIED) 1173 override = B_FALSE; 1174 1175 /* 1176 * these parameter affect the classification outcome. 1177 * these parameters are used to configure the Flow key and 1178 * the TCAM key for each of the IP classes. 1179 * Included here are also the H1 and H2 initial values 1180 * which affect the distribution as well as final hash value 1181 * (hence the offset into RDC table and FCRAM bucket location) 1182 * 1183 */ 1184 for (class_prop = start_prop; class_prop <= end_prop; class_prop++) { 1185 prop_name = param_arr[class_prop].fcode_name; 1186 cfg_value = nxge_class_get_known_cfg(nxgep, 1187 class_prop, rx_quick_cfg); 1188 status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name, 1189 cfg_value, override, c_dip); 1190 } 1191 1192 /* 1193 * these properties do not affect the actual classification outcome. 1194 * used to enable/disable or tune the fflp hardware 1195 * 1196 * fcram_access_ratio, tcam_access_ratio, tcam_enable, llc_snap_enable 1197 * 1198 */ 1199 override = B_FALSE; 1200 for (class_prop = param_fcram_access_ratio; 1201 class_prop <= param_llc_snap_enable; class_prop++) { 1202 prop_name = param_arr[class_prop].fcode_name; 1203 cfg_value = param_arr[class_prop].value; 1204 status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name, 1205 cfg_value, override, c_dip); 1206 } 1207 1208 return (status); 1209 } 1210 1211 nxge_status_t 1212 nxge_cfg_verify_set(p_nxge_t nxgep, uint32_t flag) 1213 { 1214 nxge_status_t status = NXGE_OK; 1215 int i = 0, found = 0; 1216 int num_siblings; 1217 dev_info_t *c_dip[MAX_SIBLINGS + 1]; 1218 char *prop_val[MAX_SIBLINGS]; 1219 config_token_t c_token[MAX_SIBLINGS]; 1220 char *prop; 1221 1222 if (nxge_dma_obp_props_only) 1223 return (NXGE_OK); 1224 1225 num_siblings = 0; 1226 c_dip[num_siblings] = ddi_get_child(nxgep->p_dip); 1227 while (c_dip[num_siblings]) { 1228 c_dip[num_siblings + 1] = 1229 ddi_get_next_sibling(c_dip[num_siblings]); 1230 num_siblings++; 1231 } 1232 1233 switch (flag) { 1234 case COMMON_TXDMA_CFG: 1235 prop = "txdma-cfg"; 1236 break; 1237 case COMMON_RXDMA_CFG: 1238 prop = "rxdma-cfg"; 1239 break; 1240 case COMMON_RXDMA_GRP_CFG: 1241 prop = "rxdma-grp-cfg"; 1242 break; 1243 case COMMON_CLASS_CFG: 1244 status = nxge_cfg_verify_set_classify(nxgep, c_dip); 1245 return (status); 1246 default: 1247 return (NXGE_ERROR); 1248 } 1249 1250 i = 0; 1251 while (i < num_siblings) { 1252 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, c_dip[i], 0, prop, 1253 (char **)&prop_val[i]) == DDI_PROP_SUCCESS) { 1254 c_token[i] = nxge_get_config_token(prop_val[i]); 1255 ddi_prop_free(prop_val[i]); 1256 found++; 1257 } else 1258 c_token[i] = CONFIG_TOKEN_NONE; 1259 i++; 1260 } 1261 1262 if (found != i) { 1263 if (found == 0) { 1264 /* not specified: Use default */ 1265 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1266 " property %s not specified on any port:" 1267 " Using default", prop)); 1268 1269 status = nxge_update_cfg_properties(nxgep, 1270 flag, FAIR, c_dip); 1271 return (status); 1272 } else { 1273 /* 1274 * if the convention is to use function 0 device then 1275 * populate the other devices with this configuration. 1276 * 1277 * The other alternative is to use the default config. 1278 */ 1279 /* not specified: Use default */ 1280 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1281 " property %s not specified on some ports:" 1282 " Using default", prop)); 1283 status = nxge_update_cfg_properties(nxgep, 1284 flag, FAIR, c_dip); 1285 return (status); 1286 } 1287 } 1288 1289 /* check type and consistence */ 1290 /* found on all devices */ 1291 for (i = 1; i < found; i++) { 1292 if (c_token[i] != c_token[i - 1]) { 1293 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1294 " property %s inconsistent:" 1295 " Using default", prop)); 1296 status = nxge_update_cfg_properties(nxgep, 1297 flag, FAIR, c_dip); 1298 return (status); 1299 } 1300 } 1301 1302 /* 1303 * Found on all the ports check if it is custom configuration. if 1304 * custom, then verify consistence 1305 * 1306 * finally create soft properties 1307 */ 1308 status = nxge_update_cfg_properties(nxgep, flag, c_token[0], c_dip); 1309 return (status); 1310 } 1311 1312 nxge_status_t 1313 nxge_cfg_verify_set_quick_config(p_nxge_t nxgep) 1314 { 1315 nxge_status_t status = NXGE_OK; 1316 int ddi_status = DDI_SUCCESS; 1317 char *prop_val; 1318 char *rx_prop; 1319 char *prop; 1320 uint32_t cfg_value = CFG_NOT_SPECIFIED; 1321 p_nxge_param_t param_arr; 1322 1323 param_arr = nxgep->param_arr; 1324 rx_prop = param_arr[param_rx_quick_cfg].fcode_name; 1325 1326 prop = "rx-quick-cfg"; 1327 1328 /* 1329 * good value are 1330 * 1331 * "web-server" "generic-server" "l3-classify" "flow-classify" 1332 */ 1333 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, nxgep->dip, 0, 1334 prop, (char **)&prop_val) != DDI_PROP_SUCCESS) { 1335 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1336 " property %s not specified: using default ", prop)); 1337 cfg_value = CFG_NOT_SPECIFIED; 1338 } else { 1339 cfg_value = CFG_L3_DISTRIBUTE; 1340 if (strncmp("web-server", (caddr_t)prop_val, 8) == 0) { 1341 cfg_value = CFG_L3_WEB; 1342 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1343 " %s: web server ", prop)); 1344 } 1345 if (strncmp("generic-server", (caddr_t)prop_val, 8) == 0) { 1346 cfg_value = CFG_L3_DISTRIBUTE; 1347 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1348 " %s: distribute ", prop)); 1349 } 1350 /* more */ 1351 ddi_prop_free(prop_val); 1352 } 1353 1354 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 1355 rx_prop, cfg_value); 1356 if (ddi_status != DDI_PROP_SUCCESS) 1357 status |= NXGE_DDI_FAILED; 1358 1359 /* now handle specified cases: */ 1360 if (status & NXGE_DDI_FAILED) 1361 status |= NXGE_ERROR; 1362 return (status); 1363 } 1364 1365 /* 1366 * Device properties adv-autoneg-cap etc are defined by FWARC 1367 * http://sac.sfbay/FWARC/2002/345/20020610_asif.haswarey 1368 */ 1369 static void 1370 nxge_use_cfg_link_cfg(p_nxge_t nxgep) 1371 { 1372 int *prop_val; 1373 uint_t prop_len; 1374 dev_info_t *dip; 1375 int speed; 1376 int duplex; 1377 int adv_autoneg_cap; 1378 int adv_10gfdx_cap; 1379 int adv_10ghdx_cap; 1380 int adv_1000fdx_cap; 1381 int adv_1000hdx_cap; 1382 int adv_100fdx_cap; 1383 int adv_100hdx_cap; 1384 int adv_10fdx_cap; 1385 int adv_10hdx_cap; 1386 int status = DDI_SUCCESS; 1387 1388 dip = nxgep->dip; 1389 1390 /* 1391 * first find out the card type and the supported link speeds and 1392 * features 1393 */ 1394 /* add code for card type */ 1395 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-autoneg-cap", 1396 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1397 ddi_prop_free(prop_val); 1398 return; 1399 } 1400 1401 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10gfdx-cap", 1402 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1403 ddi_prop_free(prop_val); 1404 return; 1405 } 1406 1407 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000hdx-cap", 1408 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1409 ddi_prop_free(prop_val); 1410 return; 1411 } 1412 1413 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000fdx-cap", 1414 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1415 ddi_prop_free(prop_val); 1416 return; 1417 } 1418 1419 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100fdx-cap", 1420 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1421 ddi_prop_free(prop_val); 1422 return; 1423 } 1424 1425 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100hdx-cap", 1426 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1427 ddi_prop_free(prop_val); 1428 return; 1429 } 1430 1431 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10fdx-cap", 1432 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1433 ddi_prop_free(prop_val); 1434 return; 1435 } 1436 1437 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10hdx-cap", 1438 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1439 ddi_prop_free(prop_val); 1440 return; 1441 } 1442 1443 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "speed", 1444 (uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1445 if (strncmp("10000", (caddr_t)prop_val, 1446 (size_t)prop_len) == 0) { 1447 speed = 10000; 1448 } else if (strncmp("1000", (caddr_t)prop_val, 1449 (size_t)prop_len) == 0) { 1450 speed = 1000; 1451 } else if (strncmp("100", (caddr_t)prop_val, 1452 (size_t)prop_len) == 0) { 1453 speed = 100; 1454 } else if (strncmp("10", (caddr_t)prop_val, 1455 (size_t)prop_len) == 0) { 1456 speed = 10; 1457 } else if (strncmp("auto", (caddr_t)prop_val, 1458 (size_t)prop_len) == 0) { 1459 speed = 0; 1460 } else { 1461 NXGE_ERROR_MSG((nxgep, NXGE_NOTE, 1462 "speed property is invalid reverting to auto")); 1463 speed = 0; 1464 } 1465 ddi_prop_free(prop_val); 1466 } else 1467 speed = 0; 1468 1469 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "duplex", 1470 (uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1471 if (strncmp("full", (caddr_t)prop_val, 1472 (size_t)prop_len) == 0) { 1473 duplex = 2; 1474 } else if (strncmp("half", (caddr_t)prop_val, 1475 (size_t)prop_len) == 0) { 1476 duplex = 1; 1477 } else if (strncmp("auto", (caddr_t)prop_val, 1478 (size_t)prop_len) == 0) { 1479 duplex = 0; 1480 } else { 1481 NXGE_ERROR_MSG((nxgep, NXGE_NOTE, 1482 "duplex property is invalid" 1483 " reverting to auto")); 1484 duplex = 0; 1485 } 1486 ddi_prop_free(prop_val); 1487 } else 1488 duplex = 0; 1489 1490 /* speed == 0 or duplex == 0 means auto negotiation. */ 1491 adv_autoneg_cap = (speed == 0) || (duplex == 0); 1492 if (adv_autoneg_cap == 0) { 1493 adv_10gfdx_cap = ((speed == 10000) && (duplex == 2)); 1494 adv_10ghdx_cap = adv_10gfdx_cap; 1495 adv_10ghdx_cap |= ((speed == 10000) && (duplex == 1)); 1496 adv_1000fdx_cap = adv_10ghdx_cap; 1497 adv_1000fdx_cap |= ((speed == 1000) && (duplex == 2)); 1498 adv_1000hdx_cap = adv_1000fdx_cap; 1499 adv_1000hdx_cap |= ((speed == 1000) && (duplex == 1)); 1500 adv_100fdx_cap = adv_1000hdx_cap; 1501 adv_100fdx_cap |= ((speed == 100) && (duplex == 2)); 1502 adv_100hdx_cap = adv_100fdx_cap; 1503 adv_100hdx_cap |= ((speed == 100) && (duplex == 1)); 1504 adv_10fdx_cap = adv_100hdx_cap; 1505 adv_10fdx_cap |= ((speed == 10) && (duplex == 2)); 1506 adv_10hdx_cap = adv_10fdx_cap; 1507 adv_10hdx_cap |= ((speed == 10) && (duplex == 1)); 1508 } else if (speed == 0) { 1509 adv_10gfdx_cap = (duplex == 2); 1510 adv_10ghdx_cap = (duplex == 1); 1511 adv_1000fdx_cap = (duplex == 2); 1512 adv_1000hdx_cap = (duplex == 1); 1513 adv_100fdx_cap = (duplex == 2); 1514 adv_100hdx_cap = (duplex == 1); 1515 adv_10fdx_cap = (duplex == 2); 1516 adv_10hdx_cap = (duplex == 1); 1517 } 1518 if (duplex == 0) { 1519 adv_10gfdx_cap = (speed == 0); 1520 adv_10gfdx_cap |= (speed == 10000); 1521 adv_10ghdx_cap = adv_10gfdx_cap; 1522 adv_10ghdx_cap |= (speed == 10000); 1523 adv_1000fdx_cap = adv_10ghdx_cap; 1524 adv_1000fdx_cap |= (speed == 1000); 1525 adv_1000hdx_cap = adv_1000fdx_cap; 1526 adv_1000hdx_cap |= (speed == 1000); 1527 adv_100fdx_cap = adv_1000hdx_cap; 1528 adv_100fdx_cap |= (speed == 100); 1529 adv_100hdx_cap = adv_100fdx_cap; 1530 adv_100hdx_cap |= (speed == 100); 1531 adv_10fdx_cap = adv_100hdx_cap; 1532 adv_10fdx_cap |= (speed == 10); 1533 adv_10hdx_cap = adv_10fdx_cap; 1534 adv_10hdx_cap |= (speed == 10); 1535 } 1536 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1537 "adv-autoneg-cap", &adv_autoneg_cap, 1); 1538 if (status) 1539 return; 1540 1541 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1542 "adv-10gfdx-cap", &adv_10gfdx_cap, 1); 1543 if (status) 1544 goto nxge_map_myargs_to_gmii_fail1; 1545 1546 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1547 "adv-10ghdx-cap", &adv_10ghdx_cap, 1); 1548 if (status) 1549 goto nxge_map_myargs_to_gmii_fail2; 1550 1551 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1552 "adv-1000fdx-cap", &adv_1000fdx_cap, 1); 1553 if (status) 1554 goto nxge_map_myargs_to_gmii_fail3; 1555 1556 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1557 "adv-1000hdx-cap", &adv_1000hdx_cap, 1); 1558 if (status) 1559 goto nxge_map_myargs_to_gmii_fail4; 1560 1561 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1562 "adv-100fdx-cap", &adv_100fdx_cap, 1); 1563 if (status) 1564 goto nxge_map_myargs_to_gmii_fail5; 1565 1566 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1567 "adv-100hdx-cap", &adv_100hdx_cap, 1); 1568 if (status) 1569 goto nxge_map_myargs_to_gmii_fail6; 1570 1571 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1572 "adv-10fdx-cap", &adv_10fdx_cap, 1); 1573 if (status) 1574 goto nxge_map_myargs_to_gmii_fail7; 1575 1576 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1577 "adv-10hdx-cap", &adv_10hdx_cap, 1); 1578 if (status) 1579 goto nxge_map_myargs_to_gmii_fail8; 1580 1581 return; 1582 1583 nxge_map_myargs_to_gmii_fail9: 1584 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10hdx-cap"); 1585 1586 nxge_map_myargs_to_gmii_fail8: 1587 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10fdx-cap"); 1588 1589 nxge_map_myargs_to_gmii_fail7: 1590 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100hdx-cap"); 1591 1592 nxge_map_myargs_to_gmii_fail6: 1593 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100fdx-cap"); 1594 1595 nxge_map_myargs_to_gmii_fail5: 1596 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000hdx-cap"); 1597 1598 nxge_map_myargs_to_gmii_fail4: 1599 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000fdx-cap"); 1600 1601 nxge_map_myargs_to_gmii_fail3: 1602 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10ghdx-cap"); 1603 1604 nxge_map_myargs_to_gmii_fail2: 1605 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10gfdx-cap"); 1606 1607 nxge_map_myargs_to_gmii_fail1: 1608 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-autoneg-cap"); 1609 } 1610 1611 nxge_status_t 1612 nxge_get_config_properties(p_nxge_t nxgep) 1613 { 1614 nxge_status_t status = NXGE_OK; 1615 p_nxge_hw_list_t hw_p; 1616 1617 NXGE_DEBUG_MSG((nxgep, VPD_CTL, " ==> nxge_get_config_properties")); 1618 1619 if ((hw_p = nxgep->nxge_hw_p) == NULL) { 1620 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1621 " nxge_get_config_properties:" 1622 " common hardware not set", nxgep->niu_type)); 1623 return (NXGE_ERROR); 1624 } 1625 1626 /* 1627 * Get info on how many ports Neptune card has. 1628 */ 1629 nxgep->nports = nxge_get_nports(nxgep); 1630 if (nxgep->nports <= 0) { 1631 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1632 "<==nxge_get_config_properties: Invalid Neptune type 0x%x", 1633 nxgep->niu_type)); 1634 return (NXGE_ERROR); 1635 } 1636 nxgep->classifier.tcam_size = TCAM_NIU_TCAM_MAX_ENTRY; 1637 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1638 nxgep->classifier.tcam_size = TCAM_NXGE_TCAM_MAX_ENTRY; 1639 } 1640 if (nxgep->function_num >= nxgep->nports) { 1641 return (NXGE_ERROR); 1642 } 1643 1644 status = nxge_get_mac_addr_properties(nxgep); 1645 if (status != NXGE_OK) 1646 return (NXGE_ERROR); 1647 1648 /* 1649 * read the configuration type. If none is specified, used default. 1650 * Config types: equal: (default) DMA channels, RDC groups, TCAM, FCRAM 1651 * are shared equally across all the ports. 1652 * 1653 * Fair: DMA channels, RDC groups, TCAM, FCRAM are shared proportional 1654 * to the port speed. 1655 * 1656 * 1657 * custom: DMA channels, RDC groups, TCAM, FCRAM partition is 1658 * specified in nxge.conf. Need to read each parameter and set 1659 * up the parameters in nxge structures. 1660 * 1661 */ 1662 switch (nxgep->niu_type) { 1663 case N2_NIU: 1664 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1665 " ==> nxge_get_config_properties: N2")); 1666 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 1667 if ((hw_p->flags & COMMON_CFG_VALID) != 1668 COMMON_CFG_VALID) { 1669 status = nxge_cfg_verify_set(nxgep, 1670 COMMON_RXDMA_GRP_CFG); 1671 status = nxge_cfg_verify_set(nxgep, 1672 COMMON_CLASS_CFG); 1673 hw_p->flags |= COMMON_CFG_VALID; 1674 } 1675 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 1676 status = nxge_use_cfg_n2niu_properties(nxgep); 1677 break; 1678 default: 1679 if (!NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1680 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1681 " nxge_get_config_properties:" 1682 " unknown NIU type 0x%x", nxgep->niu_type)); 1683 return (NXGE_ERROR); 1684 } 1685 1686 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1687 " ==> nxge_get_config_properties: Neptune")); 1688 status = nxge_cfg_verify_set_quick_config(nxgep); 1689 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 1690 if ((hw_p->flags & COMMON_CFG_VALID) != 1691 COMMON_CFG_VALID) { 1692 status = nxge_cfg_verify_set(nxgep, 1693 COMMON_TXDMA_CFG); 1694 status = nxge_cfg_verify_set(nxgep, 1695 COMMON_RXDMA_CFG); 1696 status = nxge_cfg_verify_set(nxgep, 1697 COMMON_RXDMA_GRP_CFG); 1698 status = nxge_cfg_verify_set(nxgep, 1699 COMMON_CLASS_CFG); 1700 hw_p->flags |= COMMON_CFG_VALID; 1701 } 1702 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 1703 nxge_use_cfg_neptune_properties(nxgep); 1704 status = NXGE_OK; 1705 break; 1706 } 1707 1708 /* 1709 * Get the software LSO enable flag property from the 1710 * driver configuration file (nxge.conf). 1711 * This flag will be set to disable (0) if this property 1712 * does not exist. 1713 */ 1714 nxgep->soft_lso_enable = ddi_prop_get_int(DDI_DEV_T_ANY, nxgep->dip, 1715 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, "soft-lso-enable", 0); 1716 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1717 "nxge_get_config_properties: software lso %d\n", 1718 nxgep->soft_lso_enable)); 1719 1720 NXGE_DEBUG_MSG((nxgep, VPD_CTL, " <== nxge_get_config_properties")); 1721 return (status); 1722 } 1723 1724 static nxge_status_t 1725 nxge_use_cfg_n2niu_properties(p_nxge_t nxgep) 1726 { 1727 nxge_status_t status = NXGE_OK; 1728 1729 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_n2niu_properties")); 1730 1731 status = nxge_use_default_dma_config_n2(nxgep); 1732 if (status != NXGE_OK) { 1733 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1734 " ==> nxge_use_cfg_n2niu_properties (err 0x%x)", 1735 status)); 1736 return (status | NXGE_ERROR); 1737 } 1738 1739 (void) nxge_use_cfg_vlan_class_config(nxgep); 1740 (void) nxge_use_cfg_mac_class_config(nxgep); 1741 (void) nxge_use_cfg_class_config(nxgep); 1742 (void) nxge_use_cfg_link_cfg(nxgep); 1743 1744 /* 1745 * Read in the hardware (fcode) properties. Use the ndd array to read 1746 * each property. 1747 */ 1748 (void) nxge_get_param_soft_properties(nxgep); 1749 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_n2niu_properties")); 1750 1751 return (status); 1752 } 1753 1754 static void 1755 nxge_use_cfg_neptune_properties(p_nxge_t nxgep) 1756 { 1757 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_neptune_properties")); 1758 1759 (void) nxge_use_cfg_dma_config(nxgep); 1760 (void) nxge_use_cfg_vlan_class_config(nxgep); 1761 (void) nxge_use_cfg_mac_class_config(nxgep); 1762 (void) nxge_use_cfg_class_config(nxgep); 1763 (void) nxge_use_cfg_link_cfg(nxgep); 1764 1765 /* 1766 * Read in the hardware (fcode) properties. Use the ndd array to read 1767 * each property. 1768 */ 1769 (void) nxge_get_param_soft_properties(nxgep); 1770 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_neptune_properties")); 1771 } 1772 1773 /* 1774 * FWARC 2006/556 for N2 NIU. Get the properties 1775 * from the prom. 1776 */ 1777 static nxge_status_t 1778 nxge_use_default_dma_config_n2(p_nxge_t nxgep) 1779 { 1780 int ndmas; 1781 uint8_t func; 1782 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1783 p_nxge_hw_pt_cfg_t p_cfgp; 1784 int *prop_val; 1785 uint_t prop_len; 1786 int i; 1787 nxge_status_t status = NXGE_OK; 1788 1789 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2")); 1790 1791 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1792 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1793 1794 func = nxgep->function_num; 1795 p_cfgp->function_number = func; 1796 ndmas = NXGE_TDMA_PER_NIU_PORT; 1797 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 1798 "tx-dma-channels", (int **)&prop_val, 1799 &prop_len) == DDI_PROP_SUCCESS) { 1800 if (prop_len != NXGE_NIU_TDMA_PROP_LEN) { 1801 ddi_prop_free(prop_val); 1802 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1803 "==> nxge_use_default_dma_config_n2: " 1804 "get tx-dma-channels failed")); 1805 return (NXGE_DDI_FAILED); 1806 } else { 1807 p_cfgp->tdc.start = prop_val[0]; 1808 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1809 "==> nxge_use_default_dma_config_n2: tdc starts %d " 1810 "(#%d)", p_cfgp->tdc.start, prop_len)); 1811 1812 ndmas = prop_val[1]; 1813 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1814 "==> nxge_use_default_dma_config_n2: #tdc %d (#%d)", 1815 ndmas, prop_len)); 1816 ddi_prop_free(prop_val); 1817 } 1818 } else { 1819 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1820 "==> nxge_use_default_dma_config_n2: " 1821 "get tx-dma-channels failed")); 1822 return (NXGE_DDI_FAILED); 1823 } 1824 1825 p_cfgp->tdc.count = ndmas; 1826 p_cfgp->tdc.owned = p_cfgp->tdc.count; 1827 1828 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: " 1829 "p_cfgp 0x%llx max_tdcs %d start %d", 1830 p_cfgp, p_cfgp->tdc.count, p_cfgp->tdc.start)); 1831 1832 /* Receive DMA */ 1833 ndmas = NXGE_RDMA_PER_NIU_PORT; 1834 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 1835 "rx-dma-channels", (int **)&prop_val, 1836 &prop_len) == DDI_PROP_SUCCESS) { 1837 if (prop_len != NXGE_NIU_TDMA_PROP_LEN) { 1838 ddi_prop_free(prop_val); 1839 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1840 "==> nxge_use_default_dma_config_n2: " 1841 "get rx-dma-channels failed")); 1842 return (NXGE_DDI_FAILED); 1843 } else { 1844 p_cfgp->start_rdc = prop_val[0]; 1845 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1846 "==> nxge_use_default_dma_config_n2(obp):" 1847 " rdc start %d (#%d)", 1848 p_cfgp->start_rdc, prop_len)); 1849 ndmas = prop_val[1]; 1850 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1851 "==> nxge_use_default_dma_config_n2(obp): " 1852 "#rdc %d (#%d)", ndmas, prop_len)); 1853 ddi_prop_free(prop_val); 1854 } 1855 } else { 1856 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1857 "==> nxge_use_default_dma_config_n2: " 1858 "get rx-dma-channel failed")); 1859 return (NXGE_DDI_FAILED); 1860 } 1861 1862 p_cfgp->max_rdcs = ndmas; 1863 nxgep->rdc_mask = (ndmas - 1); 1864 1865 /* Hypervisor: rdc # and group # use the same # !! */ 1866 p_cfgp->max_grpids = p_cfgp->max_rdcs + p_cfgp->tdc.owned; 1867 p_cfgp->mif_ldvid = p_cfgp->mac_ldvid = p_cfgp->ser_ldvid = 0; 1868 1869 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 1870 "interrupts", (int **)&prop_val, 1871 &prop_len) == DDI_PROP_SUCCESS) { 1872 if ((prop_len != NXGE_NIU_0_INTR_PROP_LEN) && 1873 (prop_len != NXGE_NIU_1_INTR_PROP_LEN)) { 1874 ddi_prop_free(prop_val); 1875 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1876 "==> nxge_use_default_dma_config_n2: " 1877 "get interrupts failed")); 1878 return (NXGE_DDI_FAILED); 1879 } 1880 1881 /* 1882 * For each device assigned, the content of each interrupts 1883 * property is its logical device group. 1884 * 1885 * Assignment of interrupts property is in the the following 1886 * order: 1887 * 1888 * MAC MIF (if configured) SYSTEM ERROR (if configured) first 1889 * receive channel next channel...... last receive channel 1890 * first transmit channel next channel...... last transmit 1891 * channel 1892 * 1893 * prop_len should be at least for one mac and total # of rx and 1894 * tx channels. Function 0 owns MIF and ERROR 1895 */ 1896 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1897 "==> nxge_use_default_dma_config_n2(obp): " 1898 "# interrupts %d", prop_len)); 1899 1900 switch (func) { 1901 case 0: 1902 p_cfgp->ldg_chn_start = 3; 1903 p_cfgp->mac_ldvid = NXGE_MAC_LD_PORT0; 1904 p_cfgp->mif_ldvid = NXGE_MIF_LD; 1905 p_cfgp->ser_ldvid = NXGE_SYS_ERROR_LD; 1906 1907 break; 1908 case 1: 1909 p_cfgp->ldg_chn_start = 1; 1910 p_cfgp->mac_ldvid = NXGE_MAC_LD_PORT1; 1911 1912 break; 1913 default: 1914 status = NXGE_DDI_FAILED; 1915 break; 1916 } 1917 1918 if (status != NXGE_OK) 1919 return (status); 1920 1921 for (i = 0; i < prop_len; i++) { 1922 p_cfgp->ldg[i] = prop_val[i]; 1923 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1924 "==> nxge_use_default_dma_config_n2(obp): " 1925 "F%d: interrupt #%d, ldg %d", 1926 nxgep->function_num, i, p_cfgp->ldg[i])); 1927 } 1928 1929 p_cfgp->max_grpids = prop_len; 1930 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1931 "==> nxge_use_default_dma_config_n2(obp): %d " 1932 "(#%d) maxgrpids %d channel starts %d", 1933 p_cfgp->mac_ldvid, i, p_cfgp->max_grpids, 1934 p_cfgp->ldg_chn_start)); 1935 ddi_prop_free(prop_val); 1936 } else { 1937 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1938 "==> nxge_use_default_dma_config_n2: " 1939 "get interrupts failed")); 1940 return (NXGE_DDI_FAILED); 1941 } 1942 1943 p_cfgp->max_ldgs = p_cfgp->max_grpids; 1944 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1945 "==> nxge_use_default_dma_config_n2: p_cfgp 0x%llx max_rdcs %d " 1946 "max_grpids %d macid %d mifid %d serrid %d", 1947 p_cfgp, p_cfgp->max_rdcs, p_cfgp->max_grpids, 1948 p_cfgp->mac_ldvid, p_cfgp->mif_ldvid, p_cfgp->ser_ldvid)); 1949 1950 1951 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: " 1952 "p_cfgp p%p start_ldg %d nxgep->max_ldgs %d", 1953 p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs)); 1954 1955 /* 1956 * RDC groups and the beginning RDC group assigned to this function. 1957 */ 1958 p_cfgp->max_rdc_grpids = NXGE_MAX_RDC_GROUPS / nxgep->nports; 1959 p_cfgp->def_mac_rxdma_grpid = 1960 nxgep->function_num * NXGE_MAX_RDC_GROUPS / nxgep->nports; 1961 p_cfgp->def_mac_txdma_grpid = 1962 nxgep->function_num * NXGE_MAX_TDC_GROUPS / nxgep->nports; 1963 1964 if ((p_cfgp->def_mac_rxdma_grpid = nxge_fzc_rdc_tbl_bind(nxgep, 1965 p_cfgp->def_mac_rxdma_grpid, B_TRUE)) >= NXGE_MAX_RDC_GRPS) { 1966 NXGE_ERROR_MSG((nxgep, CFG_CTL, 1967 "nxge_use_default_dma_config_n2(): " 1968 "nxge_fzc_rdc_tbl_bind failed")); 1969 return (NXGE_DDI_FAILED); 1970 } 1971 1972 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 1973 "rx-rdc-grps", p_cfgp->max_rdc_grpids); 1974 if (status) { 1975 return (NXGE_DDI_FAILED); 1976 } 1977 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 1978 "rx-rdc-grps-begin", p_cfgp->def_mac_rxdma_grpid); 1979 if (status) { 1980 (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip, 1981 "rx-rdc-grps"); 1982 return (NXGE_DDI_FAILED); 1983 } 1984 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: " 1985 "p_cfgp $%p # rdc groups %d start rdc group id %d", 1986 p_cfgp, p_cfgp->max_rdc_grpids, 1987 p_cfgp->def_mac_rxdma_grpid)); 1988 1989 nxgep->intr_timeout = NXGE_RDC_RCR_TIMEOUT; 1990 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 1991 "rxdma-intr-time", (int **)&prop_val, &prop_len) == 1992 DDI_PROP_SUCCESS) { 1993 if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) { 1994 nxgep->intr_timeout = prop_val[0]; 1995 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, 1996 nxgep->dip, "rxdma-intr-time", prop_val, prop_len); 1997 } 1998 ddi_prop_free(prop_val); 1999 } 2000 2001 nxgep->intr_threshold = NXGE_RDC_RCR_THRESHOLD; 2002 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 2003 "rxdma-intr-pkts", (int **)&prop_val, &prop_len) == 2004 DDI_PROP_SUCCESS) { 2005 if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) { 2006 nxgep->intr_threshold = prop_val[0]; 2007 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, 2008 nxgep->dip, "rxdma-intr-pkts", prop_val, prop_len); 2009 } 2010 ddi_prop_free(prop_val); 2011 } 2012 2013 nxge_set_hw_dma_config(nxgep); 2014 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "<== nxge_use_default_dma_config_n2")); 2015 return (status); 2016 } 2017 2018 static void 2019 nxge_use_cfg_dma_config(p_nxge_t nxgep) 2020 { 2021 int tx_ndmas, rx_ndmas, nrxgp, st_txdma, st_rxdma; 2022 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2023 p_nxge_hw_pt_cfg_t p_cfgp; 2024 dev_info_t *dip; 2025 p_nxge_param_t param_arr; 2026 char *prop; 2027 int *prop_val; 2028 uint_t prop_len; 2029 int i; 2030 uint8_t *ch_arr_p; 2031 2032 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_dma_config")); 2033 param_arr = nxgep->param_arr; 2034 2035 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2036 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2037 dip = nxgep->dip; 2038 p_cfgp->function_number = nxgep->function_num; 2039 prop = param_arr[param_txdma_channels_begin].fcode_name; 2040 2041 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2042 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2043 p_cfgp->tdc.start = *prop_val; 2044 ddi_prop_free(prop_val); 2045 } else { 2046 switch (nxgep->niu_type) { 2047 case NEPTUNE_4_1GC: 2048 ch_arr_p = &tx_4_1G[0]; 2049 break; 2050 case NEPTUNE_2_10GF: 2051 ch_arr_p = &tx_2_10G[0]; 2052 break; 2053 case NEPTUNE_2_10GF_2_1GC: 2054 case NEPTUNE_2_10GF_2_1GRF: 2055 ch_arr_p = &tx_2_10G_2_1G[0]; 2056 break; 2057 case NEPTUNE_1_10GF_3_1GC: 2058 ch_arr_p = &tx_1_10G_3_1G[0]; 2059 break; 2060 case NEPTUNE_1_1GC_1_10GF_2_1GC: 2061 ch_arr_p = &tx_1_1G_1_10G_2_1G[0]; 2062 break; 2063 default: 2064 switch (nxgep->platform_type) { 2065 case P_NEPTUNE_ALONSO: 2066 ch_arr_p = &tx_2_10G_2_1G[0]; 2067 break; 2068 default: 2069 ch_arr_p = &p4_tx_equal[0]; 2070 break; 2071 } 2072 break; 2073 } 2074 st_txdma = 0; 2075 for (i = 0; i < nxgep->function_num; i++, ch_arr_p++) 2076 st_txdma += *ch_arr_p; 2077 2078 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2079 prop, st_txdma); 2080 p_cfgp->tdc.start = st_txdma; 2081 } 2082 2083 prop = param_arr[param_txdma_channels].fcode_name; 2084 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2085 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2086 tx_ndmas = *prop_val; 2087 ddi_prop_free(prop_val); 2088 } else { 2089 switch (nxgep->niu_type) { 2090 case NEPTUNE_4_1GC: 2091 tx_ndmas = tx_4_1G[nxgep->function_num]; 2092 break; 2093 case NEPTUNE_2_10GF: 2094 tx_ndmas = tx_2_10G[nxgep->function_num]; 2095 break; 2096 case NEPTUNE_2_10GF_2_1GC: 2097 case NEPTUNE_2_10GF_2_1GRF: 2098 tx_ndmas = tx_2_10G_2_1G[nxgep->function_num]; 2099 break; 2100 case NEPTUNE_1_10GF_3_1GC: 2101 tx_ndmas = tx_1_10G_3_1G[nxgep->function_num]; 2102 break; 2103 case NEPTUNE_1_1GC_1_10GF_2_1GC: 2104 tx_ndmas = tx_1_1G_1_10G_2_1G[nxgep->function_num]; 2105 break; 2106 default: 2107 switch (nxgep->platform_type) { 2108 case P_NEPTUNE_ALONSO: 2109 tx_ndmas = tx_2_10G_2_1G[nxgep->function_num]; 2110 break; 2111 default: 2112 tx_ndmas = p4_tx_equal[nxgep->function_num]; 2113 break; 2114 } 2115 break; 2116 } 2117 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2118 prop, tx_ndmas); 2119 } 2120 2121 p_cfgp->tdc.count = tx_ndmas; 2122 p_cfgp->tdc.owned = p_cfgp->tdc.count; 2123 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: " 2124 "p_cfgp 0x%llx max_tdcs %d", p_cfgp, p_cfgp->tdc.count)); 2125 2126 prop = param_arr[param_rxdma_channels_begin].fcode_name; 2127 2128 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2129 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2130 p_cfgp->start_rdc = *prop_val; 2131 ddi_prop_free(prop_val); 2132 } else { 2133 switch (nxgep->niu_type) { 2134 case NEPTUNE_4_1GC: 2135 ch_arr_p = &rx_4_1G[0]; 2136 break; 2137 case NEPTUNE_2_10GF: 2138 ch_arr_p = &rx_2_10G[0]; 2139 break; 2140 case NEPTUNE_2_10GF_2_1GC: 2141 case NEPTUNE_2_10GF_2_1GRF: 2142 ch_arr_p = &rx_2_10G_2_1G[0]; 2143 break; 2144 case NEPTUNE_1_10GF_3_1GC: 2145 ch_arr_p = &rx_1_10G_3_1G[0]; 2146 break; 2147 case NEPTUNE_1_1GC_1_10GF_2_1GC: 2148 ch_arr_p = &rx_1_1G_1_10G_2_1G[0]; 2149 break; 2150 default: 2151 switch (nxgep->platform_type) { 2152 case P_NEPTUNE_ALONSO: 2153 ch_arr_p = &rx_2_10G_2_1G[0]; 2154 break; 2155 default: 2156 ch_arr_p = &p4_rx_equal[0]; 2157 break; 2158 } 2159 break; 2160 } 2161 st_rxdma = 0; 2162 for (i = 0; i < nxgep->function_num; i++, ch_arr_p++) 2163 st_rxdma += *ch_arr_p; 2164 2165 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2166 prop, st_rxdma); 2167 p_cfgp->start_rdc = st_rxdma; 2168 } 2169 2170 prop = param_arr[param_rxdma_channels].fcode_name; 2171 2172 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2173 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2174 rx_ndmas = *prop_val; 2175 ddi_prop_free(prop_val); 2176 } else { 2177 switch (nxgep->niu_type) { 2178 case NEPTUNE_4_1GC: 2179 rx_ndmas = rx_4_1G[nxgep->function_num]; 2180 break; 2181 case NEPTUNE_2_10GF: 2182 rx_ndmas = rx_2_10G[nxgep->function_num]; 2183 break; 2184 case NEPTUNE_2_10GF_2_1GC: 2185 case NEPTUNE_2_10GF_2_1GRF: 2186 rx_ndmas = rx_2_10G_2_1G[nxgep->function_num]; 2187 break; 2188 case NEPTUNE_1_10GF_3_1GC: 2189 rx_ndmas = rx_1_10G_3_1G[nxgep->function_num]; 2190 break; 2191 case NEPTUNE_1_1GC_1_10GF_2_1GC: 2192 rx_ndmas = rx_1_1G_1_10G_2_1G[nxgep->function_num]; 2193 break; 2194 default: 2195 switch (nxgep->platform_type) { 2196 case P_NEPTUNE_ALONSO: 2197 rx_ndmas = rx_2_10G_2_1G[nxgep->function_num]; 2198 break; 2199 default: 2200 rx_ndmas = p4_rx_equal[nxgep->function_num]; 2201 break; 2202 } 2203 break; 2204 } 2205 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2206 prop, rx_ndmas); 2207 } 2208 2209 p_cfgp->max_rdcs = rx_ndmas; 2210 2211 /* 2212 * RDC groups and the beginning RDC group assigned to this function. 2213 * XXX: this may be wrong if prop value is used. 2214 */ 2215 p_cfgp->def_mac_rxdma_grpid = 2216 nxgep->function_num * NXGE_MAX_RDC_GROUPS / nxgep->nports; 2217 p_cfgp->def_mac_txdma_grpid = 2218 nxgep->function_num * NXGE_MAX_TDC_GROUPS / nxgep->nports; 2219 2220 if ((p_cfgp->def_mac_rxdma_grpid = nxge_fzc_rdc_tbl_bind(nxgep, 2221 p_cfgp->def_mac_rxdma_grpid, B_TRUE)) >= NXGE_MAX_RDC_GRPS) { 2222 NXGE_ERROR_MSG((nxgep, CFG_CTL, 2223 "nxge_use_default_dma_config2(): " 2224 "nxge_fzc_rdc_tbl_bind failed")); 2225 goto nxge_use_cfg_dma_config_exit; 2226 } 2227 2228 prop = param_arr[param_rx_rdc_grps].fcode_name; 2229 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2230 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2231 nrxgp = *prop_val; 2232 ddi_prop_free(prop_val); 2233 } else { 2234 nrxgp = NXGE_MAX_RDC_GRPS / nxgep->nports; 2235 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2236 prop, nrxgp); 2237 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2238 "==> nxge_use_default_dma_config: " 2239 "num_rdc_grpid not found: use def:# of " 2240 "rdc groups %d\n", nrxgp)); 2241 } 2242 p_cfgp->max_rdc_grpids = nrxgp; 2243 2244 /* 2245 * 2/4 ports have the same hard-wired logical groups assigned. 2246 */ 2247 p_cfgp->start_ldg = nxgep->function_num * NXGE_LDGRP_PER_4PORTS; 2248 p_cfgp->max_ldgs = NXGE_LDGRP_PER_4PORTS; 2249 2250 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_default_dma_config: " 2251 "p_cfgp 0x%llx max_rdcs %d max_grpids %d default_grpid %d", 2252 p_cfgp, p_cfgp->max_rdcs, p_cfgp->max_grpids, 2253 p_cfgp->def_mac_rxdma_grpid)); 2254 2255 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: " 2256 "p_cfgp 0x%016llx start_ldg %d nxgep->max_ldgs %d " 2257 "def_mac_rxdma_grpid %d", 2258 p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs, 2259 p_cfgp->def_mac_rxdma_grpid)); 2260 2261 nxgep->intr_timeout = NXGE_RDC_RCR_TIMEOUT; 2262 prop = param_arr[param_rxdma_intr_time].fcode_name; 2263 2264 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2265 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2266 if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) { 2267 nxgep->intr_timeout = prop_val[0]; 2268 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, 2269 nxgep->dip, prop, prop_val, prop_len); 2270 } 2271 ddi_prop_free(prop_val); 2272 } 2273 2274 nxgep->intr_threshold = NXGE_RDC_RCR_THRESHOLD; 2275 prop = param_arr[param_rxdma_intr_pkts].fcode_name; 2276 2277 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2278 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2279 if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) { 2280 nxgep->intr_threshold = prop_val[0]; 2281 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, 2282 nxgep->dip, prop, prop_val, prop_len); 2283 } 2284 ddi_prop_free(prop_val); 2285 } 2286 nxge_set_hw_dma_config(nxgep); 2287 2288 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config: " 2289 "sTDC[%d] nTDC[%d] sRDC[%d] nRDC[%d]", 2290 p_cfgp->tdc.start, p_cfgp->tdc.count, 2291 p_cfgp->start_rdc, p_cfgp->max_rdcs)); 2292 2293 nxge_use_cfg_dma_config_exit: 2294 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config")); 2295 } 2296 2297 void 2298 nxge_get_logical_props(p_nxge_t nxgep) 2299 { 2300 nxge_dma_pt_cfg_t *port = &nxgep->pt_config; 2301 nxge_hw_pt_cfg_t *hardware; 2302 nxge_rdc_grp_t *group; 2303 2304 (void) memset(port, 0, sizeof (*port)); 2305 2306 port->mac_port = nxgep->function_num; /* := function number */ 2307 2308 /* 2309 * alloc_buf_size: 2310 * dead variables. 2311 */ 2312 port->rbr_size = nxge_rbr_size; 2313 port->rcr_size = nxge_rcr_size; 2314 2315 port->tx_dma_map = 0; /* Transmit DMA channel bit map */ 2316 2317 nxge_set_rdc_intr_property(nxgep); 2318 2319 port->rcr_full_header = NXGE_RCR_FULL_HEADER; 2320 port->rx_drr_weight = PT_DRR_WT_DEFAULT_10G; 2321 2322 /* ----------------------------------------------------- */ 2323 hardware = &port->hw_config; 2324 2325 (void) memset(hardware, 0, sizeof (*hardware)); 2326 2327 /* 2328 * partition_id, read_write_mode: 2329 * dead variables. 2330 */ 2331 2332 /* 2333 * drr_wt, rx_full_header, *_ldg?, start_mac_entry, 2334 * mac_pref, def_mac_rxdma_grpid, start_vlan, max_vlans, 2335 * start_ldgs, max_ldgs, max_ldvs, 2336 * vlan_pref, def_vlan_rxdma_grpid are meaningful only 2337 * in the service domain. 2338 */ 2339 2340 group = &port->rdc_grps[0]; 2341 2342 group->flag = B_TRUE; /* configured */ 2343 group->config_method = RDC_TABLE_ENTRY_METHOD_REP; 2344 group->port = NXGE_GET_PORT_NUM(nxgep->function_num); 2345 2346 /* HIO futures: this is still an open question. */ 2347 hardware->max_macs = 1; 2348 } 2349 2350 static void 2351 nxge_use_cfg_vlan_class_config(p_nxge_t nxgep) 2352 { 2353 uint_t vlan_cnt; 2354 int *vlan_cfg_val; 2355 int status; 2356 p_nxge_param_t param_arr; 2357 char *prop; 2358 2359 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_vlan_config")); 2360 param_arr = nxgep->param_arr; 2361 prop = param_arr[param_vlan_2rdc_grp].fcode_name; 2362 2363 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2364 &vlan_cfg_val, &vlan_cnt); 2365 if (status == DDI_PROP_SUCCESS) { 2366 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, 2367 nxgep->dip, prop, vlan_cfg_val, vlan_cnt); 2368 ddi_prop_free(vlan_cfg_val); 2369 } 2370 nxge_set_hw_vlan_class_config(nxgep); 2371 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_vlan_config")); 2372 } 2373 2374 static void 2375 nxge_use_cfg_mac_class_config(p_nxge_t nxgep) 2376 { 2377 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2378 p_nxge_hw_pt_cfg_t p_cfgp; 2379 uint_t mac_cnt; 2380 int *mac_cfg_val; 2381 int status; 2382 p_nxge_param_t param_arr; 2383 char *prop; 2384 2385 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_mac_class_config")); 2386 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2387 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2388 p_cfgp->start_mac_entry = 0; 2389 param_arr = nxgep->param_arr; 2390 prop = param_arr[param_mac_2rdc_grp].fcode_name; 2391 2392 switch (nxgep->function_num) { 2393 case 0: 2394 case 1: 2395 /* 10G ports */ 2396 p_cfgp->max_macs = NXGE_MAX_MACS_XMACS; 2397 break; 2398 case 2: 2399 case 3: 2400 /* 1G ports */ 2401 default: 2402 p_cfgp->max_macs = NXGE_MAX_MACS_BMACS; 2403 break; 2404 } 2405 2406 p_cfgp->mac_pref = 1; 2407 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 2408 "== nxge_use_cfg_mac_class_config: " 2409 " mac_pref bit set def_mac_rxdma_grpid %d", 2410 p_cfgp->def_mac_rxdma_grpid)); 2411 2412 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2413 &mac_cfg_val, &mac_cnt); 2414 if (status == DDI_PROP_SUCCESS) { 2415 if (mac_cnt <= p_cfgp->max_macs) 2416 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, 2417 nxgep->dip, prop, mac_cfg_val, mac_cnt); 2418 ddi_prop_free(mac_cfg_val); 2419 } 2420 nxge_set_hw_mac_class_config(nxgep); 2421 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_mac_class_config")); 2422 } 2423 2424 static void 2425 nxge_use_cfg_class_config(p_nxge_t nxgep) 2426 { 2427 nxge_set_hw_class_config(nxgep); 2428 } 2429 2430 static void 2431 nxge_set_rdc_intr_property(p_nxge_t nxgep) 2432 { 2433 int i; 2434 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2435 2436 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_rdc_intr_property")); 2437 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2438 2439 for (i = 0; i < NXGE_MAX_RDCS; i++) { 2440 p_dma_cfgp->rcr_timeout[i] = nxgep->intr_timeout; 2441 p_dma_cfgp->rcr_threshold[i] = nxgep->intr_threshold; 2442 } 2443 2444 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_rdc_intr_property")); 2445 } 2446 2447 static void 2448 nxge_set_hw_dma_config(p_nxge_t nxgep) 2449 { 2450 int i, j, ngrps, bitmap, end, st_rdc; 2451 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2452 p_nxge_hw_pt_cfg_t p_cfgp; 2453 p_nxge_rdc_grp_t rdc_grp_p; 2454 p_nxge_tdc_grp_t tdc_grp_p; 2455 nxge_grp_t *group; 2456 uint8_t nrdcs; 2457 dc_map_t map = 0; 2458 2459 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_dma_config")); 2460 2461 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2462 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2463 2464 switch (nxgep->niu_type) { 2465 case NEPTUNE_4_1GC: 2466 case NEPTUNE_2_10GF_2_1GC: 2467 case NEPTUNE_1_10GF_3_1GC: 2468 case NEPTUNE_1_1GC_1_10GF_2_1GC: 2469 case NEPTUNE_2_10GF_2_1GRF: 2470 default: 2471 ngrps = 2; 2472 break; 2473 case NEPTUNE_2_10GF: 2474 case NEPTUNE_2_1GRF: 2475 case N2_NIU: 2476 ngrps = 4; 2477 break; 2478 } 2479 2480 /* 2481 * Setup TDC groups 2482 */ 2483 bitmap = 0; 2484 end = p_cfgp->tdc.start + p_cfgp->tdc.owned; 2485 for (i = p_cfgp->tdc.start; i < end; i++) { 2486 bitmap |= (1 << i); 2487 } 2488 2489 nxgep->tx_set.owned.map |= bitmap; /* Owned, & not shared. */ 2490 nxgep->tx_set.owned.count = p_cfgp->tdc.owned; 2491 p_dma_cfgp->tx_dma_map = bitmap; 2492 2493 for (i = 0; i < ngrps; i++) { 2494 group = (nxge_grp_t *)nxge_grp_add(nxgep, 2495 NXGE_TRANSMIT_GROUP); 2496 tdc_grp_p = &p_dma_cfgp->tdc_grps[ 2497 p_cfgp->def_mac_txdma_grpid + i]; 2498 if (i == 0) 2499 tdc_grp_p->map = bitmap; 2500 else 2501 tdc_grp_p->map = 0; 2502 /* no ring is associated with a group initially */ 2503 tdc_grp_p->start_tdc = 0; 2504 tdc_grp_p->max_tdcs = 0; 2505 tdc_grp_p->grp_index = group->index; 2506 } 2507 2508 for (i = 0; i < NXGE_MAX_RDCS; i++) { 2509 nxgep->rx_channel_started[i] = B_FALSE; 2510 } 2511 2512 /* 2513 * Setup RDC groups 2514 */ 2515 st_rdc = p_cfgp->start_rdc; 2516 for (i = 0; i < ngrps; i++) { 2517 /* 2518 * All rings are associated with the default group initially 2519 */ 2520 if (i == 0) { 2521 /* default group */ 2522 switch (nxgep->niu_type) { 2523 case NEPTUNE_4_1GC: 2524 nrdcs = rx_4_1G[nxgep->function_num]; 2525 break; 2526 case N2_NIU: 2527 case NEPTUNE_2_10GF: 2528 nrdcs = rx_2_10G[nxgep->function_num]; 2529 break; 2530 case NEPTUNE_2_10GF_2_1GC: 2531 nrdcs = rx_2_10G_2_1G[nxgep->function_num]; 2532 break; 2533 case NEPTUNE_1_10GF_3_1GC: 2534 nrdcs = rx_1_10G_3_1G[nxgep->function_num]; 2535 break; 2536 case NEPTUNE_1_1GC_1_10GF_2_1GC: 2537 nrdcs = rx_1_1G_1_10G_2_1G[nxgep->function_num]; 2538 break; 2539 default: 2540 switch (nxgep->platform_type) { 2541 case P_NEPTUNE_ALONSO: 2542 nrdcs = 2543 rx_2_10G_2_1G[nxgep->function_num]; 2544 break; 2545 default: 2546 nrdcs = rx_4_1G[nxgep->function_num]; 2547 break; 2548 } 2549 break; 2550 } 2551 2552 if (p_cfgp->max_rdcs < nrdcs) 2553 nrdcs = p_cfgp->max_rdcs; 2554 } else { 2555 nrdcs = 0; 2556 } 2557 2558 rdc_grp_p = &p_dma_cfgp->rdc_grps[ 2559 p_cfgp->def_mac_rxdma_grpid + i]; 2560 rdc_grp_p->start_rdc = st_rdc; 2561 rdc_grp_p->max_rdcs = nrdcs; 2562 rdc_grp_p->def_rdc = rdc_grp_p->start_rdc; 2563 2564 /* default to: 0, 1, 2, 3, ...., 0, 1, 2, 3.... */ 2565 if (nrdcs != 0) { 2566 for (j = 0; j < nrdcs; j++) { 2567 map |= (1 << j); 2568 } 2569 map <<= rdc_grp_p->start_rdc; 2570 } else 2571 map = 0; 2572 rdc_grp_p->map = map; 2573 2574 nxgep->rx_set.owned.map |= map; /* Owned, & not shared. */ 2575 nxgep->rx_set.owned.count = nrdcs; 2576 2577 group = (nxge_grp_t *)nxge_grp_add(nxgep, NXGE_RECEIVE_GROUP); 2578 2579 rdc_grp_p->config_method = RDC_TABLE_ENTRY_METHOD_SEQ; 2580 rdc_grp_p->flag = B_TRUE; /* This group has been configured. */ 2581 rdc_grp_p->grp_index = group->index; 2582 rdc_grp_p->port = NXGE_GET_PORT_NUM(nxgep->function_num); 2583 2584 map = 0; 2585 } 2586 2587 2588 /* default RDC */ 2589 p_cfgp->def_rdc = p_cfgp->start_rdc; 2590 nxgep->def_rdc = p_cfgp->start_rdc; 2591 2592 /* full 18 byte header ? */ 2593 p_dma_cfgp->rcr_full_header = NXGE_RCR_FULL_HEADER; 2594 p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_10G; 2595 if (nxgep->function_num > 1) 2596 p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_1G; 2597 p_dma_cfgp->rbr_size = nxge_rbr_size; 2598 p_dma_cfgp->rcr_size = nxge_rcr_size; 2599 2600 nxge_set_rdc_intr_property(nxgep); 2601 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_dma_config")); 2602 } 2603 2604 boolean_t 2605 nxge_check_rxdma_port_member(p_nxge_t nxgep, uint8_t rdc) 2606 { 2607 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2608 p_nxge_hw_pt_cfg_t p_cfgp; 2609 int status = B_TRUE; 2610 2611 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rxdma_port_member")); 2612 2613 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2614 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2615 2616 /* Receive DMA Channels */ 2617 if (rdc < p_cfgp->max_rdcs) 2618 status = B_TRUE; 2619 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rxdma_port_member")); 2620 return (status); 2621 } 2622 2623 boolean_t 2624 nxge_check_txdma_port_member(p_nxge_t nxgep, uint8_t tdc) 2625 { 2626 int status = B_FALSE; 2627 2628 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_txdma_port_member")); 2629 2630 if (tdc >= nxgep->pt_config.hw_config.tdc.start && 2631 tdc < nxgep->pt_config.hw_config.tdc.count) 2632 status = B_TRUE; 2633 2634 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_txdma_port_member")); 2635 return (status); 2636 } 2637 2638 boolean_t 2639 nxge_check_rxdma_rdcgrp_member(p_nxge_t nxgep, uint8_t rdc_grp, uint8_t rdc) 2640 { 2641 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2642 int status = B_TRUE; 2643 p_nxge_rdc_grp_t rdc_grp_p; 2644 2645 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2646 " ==> nxge_check_rxdma_rdcgrp_member")); 2647 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " nxge_check_rxdma_rdcgrp_member" 2648 " rdc %d group %d", rdc, rdc_grp)); 2649 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2650 2651 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 2652 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " max %d ", rdc_grp_p->max_rdcs)); 2653 if (rdc >= rdc_grp_p->max_rdcs) { 2654 status = B_FALSE; 2655 } 2656 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2657 " <== nxge_check_rxdma_rdcgrp_member")); 2658 return (status); 2659 } 2660 2661 boolean_t 2662 nxge_check_rdcgrp_port_member(p_nxge_t nxgep, uint8_t rdc_grp) 2663 { 2664 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2665 p_nxge_hw_pt_cfg_t p_cfgp; 2666 int status = B_TRUE; 2667 2668 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rdcgrp_port_member")); 2669 2670 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2671 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2672 2673 if (rdc_grp >= p_cfgp->max_rdc_grpids) 2674 status = B_FALSE; 2675 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rdcgrp_port_member")); 2676 return (status); 2677 } 2678 2679 static void 2680 nxge_set_hw_vlan_class_config(p_nxge_t nxgep) 2681 { 2682 int i; 2683 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2684 p_nxge_hw_pt_cfg_t p_cfgp; 2685 p_nxge_param_t param_arr; 2686 uint_t vlan_cnt; 2687 int *vlan_cfg_val; 2688 nxge_param_map_t *vmap; 2689 char *prop; 2690 p_nxge_class_pt_cfg_t p_class_cfgp; 2691 uint32_t good_cfg[32]; 2692 int good_count = 0; 2693 nxge_mv_cfg_t *vlan_tbl; 2694 2695 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_vlan_config")); 2696 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2697 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2698 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 2699 2700 param_arr = nxgep->param_arr; 2701 prop = param_arr[param_vlan_2rdc_grp].fcode_name; 2702 2703 /* 2704 * By default, VLAN to RDC group mapping is disabled Need to read HW or 2705 * .conf properties to find out if mapping is required 2706 * 2707 * Format 2708 * 2709 * uint32_t array, each array entry specifying the VLAN id and the 2710 * mapping 2711 * 2712 * bit[30] = add bit[29] = remove bit[28] = preference bits[23-16] = 2713 * rdcgrp bits[15-0] = VLAN ID ( ) 2714 */ 2715 2716 for (i = 0; i < NXGE_MAX_VLANS; i++) { 2717 p_class_cfgp->vlan_tbl[i].flag = 0; 2718 } 2719 2720 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 2721 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2722 &vlan_cfg_val, &vlan_cnt) == DDI_PROP_SUCCESS) { 2723 for (i = 0; i < vlan_cnt; i++) { 2724 vmap = (nxge_param_map_t *)&vlan_cfg_val[i]; 2725 if ((vmap->param_id) && 2726 (vmap->param_id < NXGE_MAX_VLANS) && 2727 (vmap->map_to < 2728 p_cfgp->max_rdc_grpids) && 2729 (vmap->map_to >= (uint8_t)0)) { 2730 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2731 " nxge_vlan_config mapping" 2732 " id %d grp %d", 2733 vmap->param_id, vmap->map_to)); 2734 good_cfg[good_count] = vlan_cfg_val[i]; 2735 if (vlan_tbl[vmap->param_id].flag == 0) 2736 good_count++; 2737 vlan_tbl[vmap->param_id].flag = 1; 2738 vlan_tbl[vmap->param_id].rdctbl = 2739 vmap->map_to + p_cfgp->def_mac_rxdma_grpid; 2740 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 2741 } 2742 } 2743 ddi_prop_free(vlan_cfg_val); 2744 if (good_count != vlan_cnt) { 2745 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, 2746 nxgep->dip, prop, (int *)good_cfg, good_count); 2747 } 2748 } 2749 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_set_hw_vlan_config")); 2750 } 2751 2752 static void 2753 nxge_set_hw_mac_class_config(p_nxge_t nxgep) 2754 { 2755 int i; 2756 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2757 p_nxge_hw_pt_cfg_t p_cfgp; 2758 p_nxge_param_t param_arr; 2759 uint_t mac_cnt; 2760 int *mac_cfg_val; 2761 nxge_param_map_t *mac_map; 2762 char *prop; 2763 p_nxge_class_pt_cfg_t p_class_cfgp; 2764 int good_count = 0; 2765 int good_cfg[NXGE_MAX_MACS]; 2766 nxge_mv_cfg_t *mac_host_info; 2767 2768 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_mac_config")); 2769 2770 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2771 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2772 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 2773 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 2774 2775 param_arr = nxgep->param_arr; 2776 prop = param_arr[param_mac_2rdc_grp].fcode_name; 2777 2778 for (i = 0; i < NXGE_MAX_MACS; i++) { 2779 p_class_cfgp->mac_host_info[i].flag = 0; 2780 p_class_cfgp->mac_host_info[i].rdctbl = 2781 p_cfgp->def_mac_rxdma_grpid; 2782 } 2783 2784 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2785 &mac_cfg_val, &mac_cnt) == DDI_PROP_SUCCESS) { 2786 for (i = 0; i < mac_cnt; i++) { 2787 mac_map = (nxge_param_map_t *)&mac_cfg_val[i]; 2788 if ((mac_map->param_id < p_cfgp->max_macs) && 2789 (mac_map->map_to < 2790 p_cfgp->max_rdc_grpids) && 2791 (mac_map->map_to >= (uint8_t)0)) { 2792 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2793 " nxge_mac_config mapping" 2794 " id %d grp %d", 2795 mac_map->param_id, mac_map->map_to)); 2796 mac_host_info[mac_map->param_id].mpr_npr = 2797 p_cfgp->mac_pref; 2798 mac_host_info[mac_map->param_id].rdctbl = 2799 mac_map->map_to + 2800 p_cfgp->def_mac_rxdma_grpid; 2801 good_cfg[good_count] = mac_cfg_val[i]; 2802 if (mac_host_info[mac_map->param_id].flag == 0) 2803 good_count++; 2804 mac_host_info[mac_map->param_id].flag = 1; 2805 } 2806 } 2807 ddi_prop_free(mac_cfg_val); 2808 if (good_count != mac_cnt) { 2809 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, 2810 nxgep->dip, prop, good_cfg, good_count); 2811 } 2812 } 2813 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_set_hw_mac_config")); 2814 } 2815 2816 static void 2817 nxge_set_hw_class_config(p_nxge_t nxgep) 2818 { 2819 int i; 2820 p_nxge_param_t param_arr; 2821 int *int_prop_val; 2822 uint32_t cfg_value; 2823 char *prop; 2824 p_nxge_class_pt_cfg_t p_class_cfgp; 2825 int start_prop, end_prop; 2826 uint_t prop_cnt; 2827 int start_class, j = 0; 2828 2829 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_class_config")); 2830 2831 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 2832 param_arr = nxgep->param_arr; 2833 start_prop = param_class_opt_ipv4_tcp; 2834 end_prop = param_class_opt_ipv6_sctp; 2835 start_class = TCAM_CLASS_TCP_IPV4; 2836 2837 for (i = start_prop, j = 0; i <= end_prop; i++, j++) { 2838 prop = param_arr[i].fcode_name; 2839 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 2840 0, prop, &int_prop_val, 2841 &prop_cnt) == DDI_PROP_SUCCESS) { 2842 cfg_value = (uint32_t)*int_prop_val; 2843 ddi_prop_free(int_prop_val); 2844 } else { 2845 cfg_value = (uint32_t)param_arr[i].value; 2846 } 2847 p_class_cfgp->class_cfg[start_class + j] = cfg_value; 2848 } 2849 2850 prop = param_arr[param_h1_init_value].fcode_name; 2851 2852 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2853 &int_prop_val, &prop_cnt) == DDI_PROP_SUCCESS) { 2854 cfg_value = (uint32_t)*int_prop_val; 2855 ddi_prop_free(int_prop_val); 2856 } else { 2857 cfg_value = (uint32_t)param_arr[param_h1_init_value].value; 2858 } 2859 2860 p_class_cfgp->init_h1 = (uint32_t)cfg_value; 2861 prop = param_arr[param_h2_init_value].fcode_name; 2862 2863 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2864 &int_prop_val, &prop_cnt) == DDI_PROP_SUCCESS) { 2865 cfg_value = (uint32_t)*int_prop_val; 2866 ddi_prop_free(int_prop_val); 2867 } else { 2868 cfg_value = (uint32_t)param_arr[param_h2_init_value].value; 2869 } 2870 2871 p_class_cfgp->init_h2 = (uint16_t)cfg_value; 2872 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_class_config")); 2873 } 2874 2875 nxge_status_t 2876 nxge_ldgv_init_n2(p_nxge_t nxgep, int *navail_p, int *nrequired_p) 2877 { 2878 int i, maxldvs, maxldgs, nldvs; 2879 int ldv, endldg; 2880 uint8_t func; 2881 uint8_t channel; 2882 uint8_t chn_start; 2883 boolean_t own_sys_err = B_FALSE, own_fzc = B_FALSE; 2884 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2885 p_nxge_hw_pt_cfg_t p_cfgp; 2886 p_nxge_ldgv_t ldgvp; 2887 p_nxge_ldg_t ldgp, ptr; 2888 p_nxge_ldv_t ldvp, sysldvp; 2889 nxge_status_t status = NXGE_OK; 2890 nxge_grp_set_t *set; 2891 2892 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2")); 2893 if (!*navail_p) { 2894 *nrequired_p = 0; 2895 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2896 "<== nxge_ldgv_init:no avail")); 2897 return (NXGE_ERROR); 2898 } 2899 /* 2900 * N2/NIU: one logical device owns one logical group. and each 2901 * device/group will be assigned one vector by Hypervisor. 2902 */ 2903 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2904 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2905 maxldgs = p_cfgp->max_ldgs; 2906 if (!maxldgs) { 2907 /* No devices configured. */ 2908 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init_n2: " 2909 "no logical groups configured.")); 2910 return (NXGE_ERROR); 2911 } else { 2912 maxldvs = maxldgs + 1; 2913 } 2914 2915 /* 2916 * If function zero instance, it needs to handle the system and MIF 2917 * error interrupts. MIF interrupt may not be needed for N2/NIU. 2918 */ 2919 func = nxgep->function_num; 2920 if (func == 0) { 2921 own_sys_err = B_TRUE; 2922 if (!p_cfgp->ser_ldvid) { 2923 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2924 "nxge_ldgv_init_n2: func 0, ERR ID not set!")); 2925 } 2926 /* MIF interrupt */ 2927 if (!p_cfgp->mif_ldvid) { 2928 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2929 "nxge_ldgv_init_n2: func 0, MIF ID not set!")); 2930 } 2931 } 2932 2933 /* 2934 * Assume single partition, each function owns mac. 2935 */ 2936 if (!nxge_use_partition) 2937 own_fzc = B_TRUE; 2938 2939 ldgvp = nxgep->ldgvp; 2940 if (ldgvp == NULL) { 2941 ldgvp = KMEM_ZALLOC(sizeof (nxge_ldgv_t), KM_SLEEP); 2942 nxgep->ldgvp = ldgvp; 2943 ldgvp->maxldgs = (uint8_t)maxldgs; 2944 ldgvp->maxldvs = (uint8_t)maxldvs; 2945 ldgp = ldgvp->ldgp = KMEM_ZALLOC( 2946 sizeof (nxge_ldg_t) * maxldgs, KM_SLEEP); 2947 ldvp = ldgvp->ldvp = KMEM_ZALLOC( 2948 sizeof (nxge_ldv_t) * maxldvs, KM_SLEEP); 2949 } else { 2950 ldgp = ldgvp->ldgp; 2951 ldvp = ldgvp->ldvp; 2952 } 2953 2954 ldgvp->ndma_ldvs = p_cfgp->tdc.owned + p_cfgp->max_rdcs; 2955 ldgvp->tmres = NXGE_TIMER_RESO; 2956 2957 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2958 "==> nxge_ldgv_init_n2: maxldvs %d maxldgs %d", 2959 maxldvs, maxldgs)); 2960 2961 /* logical start_ldg is ldv */ 2962 ptr = ldgp; 2963 for (i = 0; i < maxldgs; i++) { 2964 ptr->func = func; 2965 ptr->arm = B_TRUE; 2966 ptr->vldg_index = (uint8_t)i; 2967 ptr->ldg_timer = NXGE_TIMER_LDG; 2968 ptr->ldg = p_cfgp->ldg[i]; 2969 ptr->sys_intr_handler = nxge_intr; 2970 ptr->nldvs = 0; 2971 ptr->ldvp = NULL; 2972 ptr->nxgep = nxgep; 2973 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2974 "==> nxge_ldgv_init_n2: maxldvs %d maxldgs %d " 2975 "ldg %d ldgptr $%p", 2976 maxldvs, maxldgs, ptr->ldg, ptr)); 2977 ptr++; 2978 } 2979 2980 endldg = NXGE_INT_MAX_LDG; 2981 nldvs = 0; 2982 ldgvp->nldvs = 0; 2983 ldgp->ldvp = NULL; 2984 *nrequired_p = 0; 2985 2986 /* 2987 * logical device group table is organized in the following order (same 2988 * as what interrupt property has). function 0: owns MAC, MIF, error, 2989 * rx, tx. function 1: owns MAC, rx, tx. 2990 */ 2991 2992 if (own_fzc && p_cfgp->mac_ldvid) { 2993 /* Each function should own MAC interrupt */ 2994 ldv = p_cfgp->mac_ldvid; 2995 ldvp->ldv = (uint8_t)ldv; 2996 ldvp->is_mac = B_TRUE; 2997 ldvp->ldv_intr_handler = nxge_mac_intr; 2998 ldvp->ldv_ldf_masks = 0; 2999 ldvp->nxgep = nxgep; 3000 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3001 "==> nxge_ldgv_init_n2(mac): maxldvs %d ldv %d " 3002 "ldg %d ldgptr $%p ldvptr $%p", 3003 maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 3004 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3005 nldvs++; 3006 } 3007 3008 if (own_fzc && p_cfgp->mif_ldvid) { 3009 ldv = p_cfgp->mif_ldvid; 3010 ldvp->ldv = (uint8_t)ldv; 3011 ldvp->is_mif = B_TRUE; 3012 ldvp->ldv_intr_handler = nxge_mif_intr; 3013 ldvp->ldv_ldf_masks = 0; 3014 ldvp->nxgep = nxgep; 3015 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3016 "==> nxge_ldgv_init_n2(mif): maxldvs %d ldv %d " 3017 "ldg %d ldgptr $%p ldvptr $%p", 3018 maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 3019 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3020 nldvs++; 3021 } 3022 3023 /* 3024 * HW based syserr interrupt for port0, and SW based syserr interrupt 3025 * for port1 3026 */ 3027 if (own_sys_err && p_cfgp->ser_ldvid) { 3028 ldv = p_cfgp->ser_ldvid; 3029 /* 3030 * Unmask the system interrupt states. 3031 */ 3032 (void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK | 3033 SYS_ERR_IPP_MASK | SYS_ERR_TXC_MASK | 3034 SYS_ERR_ZCP_MASK); 3035 3036 ldvp->use_timer = B_TRUE; 3037 ldvp->ldv = (uint8_t)ldv; 3038 ldvp->is_syserr = B_TRUE; 3039 ldvp->ldv_intr_handler = nxge_syserr_intr; 3040 ldvp->ldv_ldf_masks = 0; 3041 ldvp->nxgep = nxgep; 3042 ldgvp->ldvp_syserr = ldvp; 3043 3044 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3045 "==> nxge_ldgv_init_n2(syserr): maxldvs %d ldv %d " 3046 "ldg %d ldgptr $%p ldvptr p%p", 3047 maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 3048 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3049 nldvs++; 3050 } else { 3051 /* 3052 * SW based: allocate the ldv for the syserr since the vector 3053 * should not be consumed for port1 3054 */ 3055 sysldvp = KMEM_ZALLOC(sizeof (nxge_ldv_t), KM_SLEEP); 3056 sysldvp->use_timer = B_TRUE; 3057 sysldvp->ldv = NXGE_SYS_ERROR_LD; 3058 sysldvp->is_syserr = B_TRUE; 3059 sysldvp->ldv_intr_handler = nxge_syserr_intr; 3060 sysldvp->ldv_ldf_masks = 0; 3061 sysldvp->nxgep = nxgep; 3062 ldgvp->ldvp_syserr = sysldvp; 3063 ldgvp->ldvp_syserr_alloced = B_TRUE; 3064 } 3065 3066 3067 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 3068 "(before rx) func %d nldvs %d navail %d nrequired %d", 3069 func, nldvs, *navail_p, *nrequired_p)); 3070 3071 /* 3072 * Start with RDC to configure logical devices for each group. 3073 */ 3074 chn_start = p_cfgp->ldg_chn_start; 3075 set = &nxgep->rx_set; 3076 for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { 3077 if ((1 << channel) & set->owned.map) { 3078 ldvp->is_rxdma = B_TRUE; 3079 ldvp->ldv = (uint8_t)channel + NXGE_RDMA_LD_START; 3080 ldvp->channel = channel; 3081 ldvp->vdma_index = (uint8_t)channel; 3082 ldvp->ldv_intr_handler = nxge_rx_intr; 3083 ldvp->ldv_ldf_masks = 0; 3084 ldvp->nxgep = nxgep; 3085 ldgp->ldg = p_cfgp->ldg[chn_start]; 3086 3087 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3088 "==> nxge_ldgv_init_n2(rx%d): maxldvs %d ldv %d " 3089 "ldg %d ldgptr 0x%016llx ldvptr 0x%016llx", 3090 i, maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 3091 nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv, 3092 endldg, nrequired_p); 3093 nldvs++; 3094 chn_start++; 3095 } 3096 } 3097 3098 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 3099 "func %d nldvs %d navail %d nrequired %d", 3100 func, nldvs, *navail_p, *nrequired_p)); 3101 3102 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 3103 "func %d nldvs %d navail %d nrequired %d ldgp 0x%llx " 3104 "ldvp 0x%llx", 3105 func, nldvs, *navail_p, *nrequired_p, ldgp, ldvp)); 3106 /* 3107 * Transmit DMA channels. 3108 */ 3109 chn_start = p_cfgp->ldg_chn_start + 8; 3110 set = &nxgep->tx_set; 3111 for (channel = 0; channel < NXGE_MAX_TDCS; channel++) { 3112 if ((1 << channel) & set->owned.map) { 3113 ldvp->is_txdma = B_TRUE; 3114 ldvp->ldv = (uint8_t)channel + NXGE_TDMA_LD_START; 3115 ldvp->channel = channel; 3116 ldvp->vdma_index = (uint8_t)channel; 3117 ldvp->ldv_intr_handler = nxge_tx_intr; 3118 ldvp->ldv_ldf_masks = 0; 3119 ldgp->ldg = p_cfgp->ldg[chn_start]; 3120 ldvp->nxgep = nxgep; 3121 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3122 "==> nxge_ldgv_init_n2(tx%d): maxldvs %d ldv %d " 3123 "ldg %d ldgptr %p ldvptr %p", 3124 channel, maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 3125 nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv, 3126 endldg, nrequired_p); 3127 nldvs++; 3128 chn_start++; 3129 } 3130 } 3131 3132 ldgvp->ldg_intrs = *nrequired_p; 3133 ldgvp->nldvs = (uint8_t)nldvs; 3134 3135 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 3136 "func %d nldvs %d maxgrps %d navail %d nrequired %d", 3137 func, nldvs, maxldgs, *navail_p, *nrequired_p)); 3138 3139 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init_n2")); 3140 return (status); 3141 } 3142 3143 /* 3144 * Interrupts related interface functions. 3145 */ 3146 3147 nxge_status_t 3148 nxge_ldgv_init(p_nxge_t nxgep, int *navail_p, int *nrequired_p) 3149 { 3150 int i, maxldvs, maxldgs, nldvs; 3151 int ldv, ldg, endldg, ngrps; 3152 uint8_t func; 3153 uint8_t channel; 3154 boolean_t own_sys_err = B_FALSE, own_fzc = B_FALSE; 3155 p_nxge_dma_pt_cfg_t p_dma_cfgp; 3156 p_nxge_hw_pt_cfg_t p_cfgp; 3157 p_nxge_ldgv_t ldgvp; 3158 p_nxge_ldg_t ldgp, ptr; 3159 p_nxge_ldv_t ldvp; 3160 nxge_grp_set_t *set; 3161 3162 nxge_status_t status = NXGE_OK; 3163 3164 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init")); 3165 if (!*navail_p) { 3166 *nrequired_p = 0; 3167 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3168 "<== nxge_ldgv_init:no avail")); 3169 return (NXGE_ERROR); 3170 } 3171 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 3172 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 3173 3174 nldvs = p_cfgp->tdc.owned + p_cfgp->max_rdcs; 3175 3176 /* 3177 * If function zero instance, it needs to handle the system error 3178 * interrupts. 3179 */ 3180 func = nxgep->function_num; 3181 if (func == 0) { 3182 nldvs++; 3183 own_sys_err = B_TRUE; 3184 } else { 3185 /* use timer */ 3186 nldvs++; 3187 } 3188 3189 /* 3190 * Assume single partition, each function owns mac. 3191 */ 3192 if (!nxge_use_partition) { 3193 /* mac */ 3194 nldvs++; 3195 /* MIF */ 3196 nldvs++; 3197 own_fzc = B_TRUE; 3198 } 3199 maxldvs = nldvs; 3200 maxldgs = p_cfgp->max_ldgs; 3201 if (!maxldvs || !maxldgs) { 3202 /* No devices configured. */ 3203 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init: " 3204 "no logical devices or groups configured.")); 3205 return (NXGE_ERROR); 3206 } 3207 ldgvp = nxgep->ldgvp; 3208 if (ldgvp == NULL) { 3209 ldgvp = KMEM_ZALLOC(sizeof (nxge_ldgv_t), KM_SLEEP); 3210 nxgep->ldgvp = ldgvp; 3211 ldgvp->maxldgs = (uint8_t)maxldgs; 3212 ldgvp->maxldvs = (uint8_t)maxldvs; 3213 ldgp = ldgvp->ldgp = KMEM_ZALLOC(sizeof (nxge_ldg_t) * maxldgs, 3214 KM_SLEEP); 3215 ldvp = ldgvp->ldvp = KMEM_ZALLOC(sizeof (nxge_ldv_t) * maxldvs, 3216 KM_SLEEP); 3217 } 3218 ldgvp->ndma_ldvs = p_cfgp->tdc.owned + p_cfgp->max_rdcs; 3219 ldgvp->tmres = NXGE_TIMER_RESO; 3220 3221 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3222 "==> nxge_ldgv_init: maxldvs %d maxldgs %d nldvs %d", 3223 maxldvs, maxldgs, nldvs)); 3224 ldg = p_cfgp->start_ldg; 3225 ptr = ldgp; 3226 for (i = 0; i < maxldgs; i++) { 3227 ptr->func = func; 3228 ptr->arm = B_TRUE; 3229 ptr->vldg_index = (uint8_t)i; 3230 ptr->ldg_timer = NXGE_TIMER_LDG; 3231 ptr->ldg = ldg++; 3232 ptr->sys_intr_handler = nxge_intr; 3233 ptr->nldvs = 0; 3234 ptr->nxgep = nxgep; 3235 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3236 "==> nxge_ldgv_init: maxldvs %d maxldgs %d ldg %d", 3237 maxldvs, maxldgs, ptr->ldg)); 3238 ptr++; 3239 } 3240 3241 ldg = p_cfgp->start_ldg; 3242 if (maxldgs > *navail_p) { 3243 ngrps = *navail_p; 3244 } else { 3245 ngrps = maxldgs; 3246 } 3247 endldg = ldg + ngrps; 3248 3249 /* 3250 * Receive DMA channels. 3251 */ 3252 nldvs = 0; 3253 ldgvp->nldvs = 0; 3254 ldgp->ldvp = NULL; 3255 *nrequired_p = 0; 3256 3257 /* 3258 * Start with RDC to configure logical devices for each group. 3259 */ 3260 set = &nxgep->rx_set; 3261 for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { 3262 if ((1 << channel) & set->owned.map) { 3263 /* For now, <channel & <vdma_index> are the same. */ 3264 ldvp->is_rxdma = B_TRUE; 3265 ldvp->ldv = (uint8_t)channel + NXGE_RDMA_LD_START; 3266 ldvp->channel = channel; 3267 ldvp->vdma_index = (uint8_t)channel; 3268 ldvp->ldv_intr_handler = nxge_rx_intr; 3269 ldvp->ldv_ldf_masks = 0; 3270 ldvp->use_timer = B_FALSE; 3271 ldvp->nxgep = nxgep; 3272 nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv, 3273 endldg, nrequired_p); 3274 nldvs++; 3275 } 3276 } 3277 3278 /* 3279 * Transmit DMA channels. 3280 */ 3281 set = &nxgep->tx_set; 3282 for (channel = 0; channel < NXGE_MAX_TDCS; channel++) { 3283 if ((1 << channel) & set->owned.map) { 3284 /* For now, <channel & <vdma_index> are the same. */ 3285 ldvp->is_txdma = B_TRUE; 3286 ldvp->ldv = (uint8_t)channel + NXGE_TDMA_LD_START; 3287 ldvp->channel = channel; 3288 ldvp->vdma_index = (uint8_t)channel; 3289 ldvp->ldv_intr_handler = nxge_tx_intr; 3290 ldvp->ldv_ldf_masks = 0; 3291 ldvp->use_timer = B_FALSE; 3292 ldvp->nxgep = nxgep; 3293 nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv, 3294 endldg, nrequired_p); 3295 nldvs++; 3296 } 3297 } 3298 3299 if (own_fzc) { 3300 ldv = NXGE_MIF_LD; 3301 ldvp->ldv = (uint8_t)ldv; 3302 ldvp->is_mif = B_TRUE; 3303 ldvp->ldv_intr_handler = nxge_mif_intr; 3304 ldvp->ldv_ldf_masks = 0; 3305 ldvp->use_timer = B_FALSE; 3306 ldvp->nxgep = nxgep; 3307 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3308 nldvs++; 3309 } 3310 /* 3311 * MAC port (function zero control) 3312 */ 3313 if (own_fzc) { 3314 ldvp->is_mac = B_TRUE; 3315 ldvp->ldv_intr_handler = nxge_mac_intr; 3316 ldvp->ldv_ldf_masks = 0; 3317 ldv = func + NXGE_MAC_LD_START; 3318 ldvp->ldv = (uint8_t)ldv; 3319 ldvp->use_timer = B_FALSE; 3320 ldvp->nxgep = nxgep; 3321 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3322 nldvs++; 3323 } 3324 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: " 3325 "func %d nldvs %d navail %d nrequired %d", 3326 func, nldvs, *navail_p, *nrequired_p)); 3327 /* 3328 * Function 0 owns system error interrupts. 3329 */ 3330 ldvp->use_timer = B_TRUE; 3331 if (own_sys_err) { 3332 ldv = NXGE_SYS_ERROR_LD; 3333 ldvp->ldv = (uint8_t)ldv; 3334 ldvp->is_syserr = B_TRUE; 3335 ldvp->ldv_intr_handler = nxge_syserr_intr; 3336 ldvp->ldv_ldf_masks = 0; 3337 ldvp->nxgep = nxgep; 3338 ldgvp->ldvp_syserr = ldvp; 3339 /* 3340 * Unmask the system interrupt states. 3341 */ 3342 (void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK | 3343 SYS_ERR_IPP_MASK | SYS_ERR_TXC_MASK | 3344 SYS_ERR_ZCP_MASK); 3345 3346 (void) nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3347 nldvs++; 3348 } else { 3349 ldv = NXGE_SYS_ERROR_LD; 3350 ldvp->ldv = (uint8_t)ldv; 3351 ldvp->is_syserr = B_TRUE; 3352 ldvp->ldv_intr_handler = nxge_syserr_intr; 3353 ldvp->nxgep = nxgep; 3354 ldvp->ldv_ldf_masks = 0; 3355 ldgvp->ldvp_syserr = ldvp; 3356 } 3357 3358 ldgvp->ldg_intrs = *nrequired_p; 3359 3360 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: " 3361 "func %d nldvs %d navail %d nrequired %d", 3362 func, nldvs, *navail_p, *nrequired_p)); 3363 3364 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init")); 3365 return (status); 3366 } 3367 3368 nxge_status_t 3369 nxge_ldgv_uninit(p_nxge_t nxgep) 3370 { 3371 p_nxge_ldgv_t ldgvp; 3372 3373 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_uninit")); 3374 ldgvp = nxgep->ldgvp; 3375 if (ldgvp == NULL) { 3376 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_uninit: " 3377 "no logical group configured.")); 3378 return (NXGE_OK); 3379 } 3380 if (ldgvp->ldvp_syserr_alloced == B_TRUE) { 3381 KMEM_FREE(ldgvp->ldvp_syserr, sizeof (nxge_ldv_t)); 3382 } 3383 if (ldgvp->ldgp) { 3384 KMEM_FREE(ldgvp->ldgp, sizeof (nxge_ldg_t) * ldgvp->maxldgs); 3385 } 3386 if (ldgvp->ldvp) { 3387 KMEM_FREE(ldgvp->ldvp, sizeof (nxge_ldv_t) * ldgvp->maxldvs); 3388 } 3389 KMEM_FREE(ldgvp, sizeof (nxge_ldgv_t)); 3390 nxgep->ldgvp = NULL; 3391 3392 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_uninit")); 3393 return (NXGE_OK); 3394 } 3395 3396 nxge_status_t 3397 nxge_intr_ldgv_init(p_nxge_t nxgep) 3398 { 3399 nxge_status_t status = NXGE_OK; 3400 3401 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_ldgv_init")); 3402 /* 3403 * Configure the logical device group numbers, state vectors and 3404 * interrupt masks for each logical device. 3405 */ 3406 status = nxge_fzc_intr_init(nxgep); 3407 3408 /* 3409 * Configure logical device masks and timers. 3410 */ 3411 status = nxge_intr_mask_mgmt(nxgep); 3412 3413 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_ldgv_init")); 3414 return (status); 3415 } 3416 3417 nxge_status_t 3418 nxge_intr_mask_mgmt(p_nxge_t nxgep) 3419 { 3420 p_nxge_ldgv_t ldgvp; 3421 p_nxge_ldg_t ldgp; 3422 p_nxge_ldv_t ldvp; 3423 npi_handle_t handle; 3424 int i, j; 3425 npi_status_t rs = NPI_SUCCESS; 3426 3427 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_mask_mgmt")); 3428 3429 if ((ldgvp = nxgep->ldgvp) == NULL) { 3430 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3431 "<== nxge_intr_mask_mgmt: Null ldgvp")); 3432 return (NXGE_ERROR); 3433 } 3434 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3435 ldgp = ldgvp->ldgp; 3436 ldvp = ldgvp->ldvp; 3437 if (ldgp == NULL || ldvp == NULL) { 3438 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3439 "<== nxge_intr_mask_mgmt: Null ldgp or ldvp")); 3440 return (NXGE_ERROR); 3441 } 3442 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3443 "==> nxge_intr_mask_mgmt: # of intrs %d ", ldgvp->ldg_intrs)); 3444 /* Initialize masks. */ 3445 if (nxgep->niu_type != N2_NIU) { 3446 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3447 "==> nxge_intr_mask_mgmt(Neptune): # intrs %d ", 3448 ldgvp->ldg_intrs)); 3449 for (i = 0; i < ldgvp->ldg_intrs; i++, ldgp++) { 3450 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3451 "==> nxge_intr_mask_mgmt(Neptune): # ldv %d " 3452 "in group %d", ldgp->nldvs, ldgp->ldg)); 3453 for (j = 0; j < ldgp->nldvs; j++, ldvp++) { 3454 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3455 "==> nxge_intr_mask_mgmt: set ldv # %d " 3456 "for ldg %d", ldvp->ldv, ldgp->ldg)); 3457 rs = npi_intr_mask_set(handle, ldvp->ldv, 3458 ldvp->ldv_ldf_masks); 3459 if (rs != NPI_SUCCESS) { 3460 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3461 "<== nxge_intr_mask_mgmt: " 3462 "set mask failed " 3463 " rs 0x%x ldv %d mask 0x%x", 3464 rs, ldvp->ldv, 3465 ldvp->ldv_ldf_masks)); 3466 return (NXGE_ERROR | rs); 3467 } 3468 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3469 "==> nxge_intr_mask_mgmt: " 3470 "set mask OK " 3471 " rs 0x%x ldv %d mask 0x%x", 3472 rs, ldvp->ldv, 3473 ldvp->ldv_ldf_masks)); 3474 } 3475 } 3476 } 3477 ldgp = ldgvp->ldgp; 3478 /* Configure timer and arm bit */ 3479 for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) { 3480 rs = npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 3481 ldgp->arm, ldgp->ldg_timer); 3482 if (rs != NPI_SUCCESS) { 3483 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3484 "<== nxge_intr_mask_mgmt: " 3485 "set timer failed " 3486 " rs 0x%x dg %d timer 0x%x", 3487 rs, ldgp->ldg, ldgp->ldg_timer)); 3488 return (NXGE_ERROR | rs); 3489 } 3490 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3491 "==> nxge_intr_mask_mgmt: " 3492 "set timer OK " 3493 " rs 0x%x ldg %d timer 0x%x", 3494 rs, ldgp->ldg, ldgp->ldg_timer)); 3495 } 3496 3497 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_mask_mgmt")); 3498 return (NXGE_OK); 3499 } 3500 3501 nxge_status_t 3502 nxge_intr_mask_mgmt_set(p_nxge_t nxgep, boolean_t on) 3503 { 3504 p_nxge_ldgv_t ldgvp; 3505 p_nxge_ldg_t ldgp; 3506 p_nxge_ldv_t ldvp; 3507 npi_handle_t handle; 3508 int i, j; 3509 npi_status_t rs = NPI_SUCCESS; 3510 3511 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3512 "==> nxge_intr_mask_mgmt_set (%d)", on)); 3513 3514 if (nxgep->niu_type == N2_NIU) { 3515 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3516 "<== nxge_intr_mask_mgmt_set (%d) not set (N2/NIU)", 3517 on)); 3518 return (NXGE_ERROR); 3519 } 3520 3521 if ((ldgvp = nxgep->ldgvp) == NULL) { 3522 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3523 "==> nxge_intr_mask_mgmt_set: Null ldgvp")); 3524 return (NXGE_ERROR); 3525 } 3526 3527 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3528 ldgp = ldgvp->ldgp; 3529 ldvp = ldgvp->ldvp; 3530 if (ldgp == NULL || ldvp == NULL) { 3531 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3532 "<== nxge_intr_mask_mgmt_set: Null ldgp or ldvp")); 3533 return (NXGE_ERROR); 3534 } 3535 /* set masks. */ 3536 for (i = 0; i < ldgvp->ldg_intrs; i++, ldgp++) { 3537 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3538 "==> nxge_intr_mask_mgmt_set: flag %d ldg %d" 3539 "set mask nldvs %d", on, ldgp->ldg, ldgp->nldvs)); 3540 for (j = 0; j < ldgp->nldvs; j++, ldvp++) { 3541 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3542 "==> nxge_intr_mask_mgmt_set: " 3543 "for %d %d flag %d", i, j, on)); 3544 if (on) { 3545 ldvp->ldv_ldf_masks = 0; 3546 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3547 "==> nxge_intr_mask_mgmt_set: " 3548 "ON mask off")); 3549 } else if (!on) { 3550 ldvp->ldv_ldf_masks = (uint8_t)LD_IM1_MASK; 3551 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3552 "==> nxge_intr_mask_mgmt_set:mask on")); 3553 } 3554 rs = npi_intr_mask_set(handle, ldvp->ldv, 3555 ldvp->ldv_ldf_masks); 3556 if (rs != NPI_SUCCESS) { 3557 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3558 "==> nxge_intr_mask_mgmt_set: " 3559 "set mask failed " 3560 " rs 0x%x ldv %d mask 0x%x", 3561 rs, ldvp->ldv, ldvp->ldv_ldf_masks)); 3562 return (NXGE_ERROR | rs); 3563 } 3564 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3565 "==> nxge_intr_mask_mgmt_set: flag %d" 3566 "set mask OK " 3567 " ldv %d mask 0x%x", 3568 on, ldvp->ldv, ldvp->ldv_ldf_masks)); 3569 } 3570 } 3571 3572 ldgp = ldgvp->ldgp; 3573 /* set the arm bit */ 3574 for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) { 3575 if (on && !ldgp->arm) { 3576 ldgp->arm = B_TRUE; 3577 } else if (!on && ldgp->arm) { 3578 ldgp->arm = B_FALSE; 3579 } 3580 rs = npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 3581 ldgp->arm, ldgp->ldg_timer); 3582 if (rs != NPI_SUCCESS) { 3583 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3584 "<== nxge_intr_mask_mgmt_set: " 3585 "set timer failed " 3586 " rs 0x%x ldg %d timer 0x%x", 3587 rs, ldgp->ldg, ldgp->ldg_timer)); 3588 return (NXGE_ERROR | rs); 3589 } 3590 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3591 "==> nxge_intr_mask_mgmt_set: OK (flag %d) " 3592 "set timer " 3593 " ldg %d timer 0x%x", 3594 on, ldgp->ldg, ldgp->ldg_timer)); 3595 } 3596 3597 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_mask_mgmt_set")); 3598 return (NXGE_OK); 3599 } 3600 3601 static nxge_status_t 3602 nxge_get_mac_addr_properties(p_nxge_t nxgep) 3603 { 3604 #if defined(_BIG_ENDIAN) 3605 uchar_t *prop_val; 3606 uint_t prop_len; 3607 uint_t j; 3608 #endif 3609 uint_t i; 3610 uint8_t func_num; 3611 boolean_t compute_macs = B_TRUE; 3612 3613 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_mac_addr_properties ")); 3614 3615 #if defined(_BIG_ENDIAN) 3616 /* 3617 * Get the ethernet address. 3618 */ 3619 (void) localetheraddr((struct ether_addr *)NULL, &nxgep->ouraddr); 3620 3621 /* 3622 * Check if it is an adapter with its own local mac address If it is 3623 * present, override the system mac address. 3624 */ 3625 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3626 "local-mac-address", &prop_val, 3627 &prop_len) == DDI_PROP_SUCCESS) { 3628 if (prop_len == ETHERADDRL) { 3629 nxgep->factaddr = *(p_ether_addr_t)prop_val; 3630 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Local mac address = " 3631 "%02x:%02x:%02x:%02x:%02x:%02x", 3632 prop_val[0], prop_val[1], prop_val[2], 3633 prop_val[3], prop_val[4], prop_val[5])); 3634 } 3635 ddi_prop_free(prop_val); 3636 } 3637 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3638 "local-mac-address?", &prop_val, 3639 &prop_len) == DDI_PROP_SUCCESS) { 3640 if (strncmp("true", (caddr_t)prop_val, (size_t)prop_len) == 0) { 3641 nxgep->ouraddr = nxgep->factaddr; 3642 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 3643 "Using local MAC address")); 3644 } 3645 ddi_prop_free(prop_val); 3646 } else { 3647 nxgep->ouraddr = nxgep->factaddr; 3648 } 3649 3650 if ((!nxgep->vpd_info.present) || 3651 (nxge_is_valid_local_mac(nxgep->factaddr))) 3652 goto got_mac_addr; 3653 3654 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_get_mac_addr_properties: " 3655 "MAC address from properties is not valid...reading from PROM")); 3656 3657 #endif 3658 if (!nxgep->vpd_info.ver_valid) { 3659 (void) nxge_espc_mac_addrs_get(nxgep); 3660 if (!nxge_is_valid_local_mac(nxgep->factaddr)) { 3661 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Failed to get " 3662 "MAC address")); 3663 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version " 3664 "[%s] invalid...please update", 3665 nxgep->vpd_info.ver)); 3666 return (NXGE_ERROR); 3667 } 3668 nxgep->ouraddr = nxgep->factaddr; 3669 goto got_mac_addr; 3670 } 3671 /* 3672 * First get the MAC address from the info in the VPD data read 3673 * from the EEPROM. 3674 */ 3675 nxge_espc_get_next_mac_addr(nxgep->vpd_info.mac_addr, 3676 nxgep->function_num, &nxgep->factaddr); 3677 3678 if (!nxge_is_valid_local_mac(nxgep->factaddr)) { 3679 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 3680 "nxge_get_mac_addr_properties: " 3681 "MAC address in EEPROM VPD data not valid" 3682 "...reading from NCR registers")); 3683 (void) nxge_espc_mac_addrs_get(nxgep); 3684 if (!nxge_is_valid_local_mac(nxgep->factaddr)) { 3685 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Failed to get " 3686 "MAC address")); 3687 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version " 3688 "[%s] invalid...please update", 3689 nxgep->vpd_info.ver)); 3690 return (NXGE_ERROR); 3691 } 3692 } 3693 3694 nxgep->ouraddr = nxgep->factaddr; 3695 3696 got_mac_addr: 3697 func_num = nxgep->function_num; 3698 3699 /* 3700 * Note: mac-addresses property is the list of mac addresses for a 3701 * port. NXGE_MAX_MMAC_ADDRS is the total number of MAC addresses 3702 * allocated for a board. 3703 */ 3704 nxgep->nxge_mmac_info.total_factory_macs = NXGE_MAX_MMAC_ADDRS; 3705 3706 #if defined(_BIG_ENDIAN) 3707 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3708 "mac-addresses", &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 3709 /* 3710 * XAUI may have up to 18 MACs, more than the XMAC can 3711 * use (1 unique MAC plus 16 alternate MACs) 3712 */ 3713 nxgep->nxge_mmac_info.num_factory_mmac = 3714 prop_len / ETHERADDRL - 1; 3715 if (nxgep->nxge_mmac_info.num_factory_mmac > 3716 XMAC_MAX_ALT_ADDR_ENTRY) { 3717 nxgep->nxge_mmac_info.num_factory_mmac = 3718 XMAC_MAX_ALT_ADDR_ENTRY; 3719 } 3720 3721 for (i = 1; i <= nxgep->nxge_mmac_info.num_factory_mmac; i++) { 3722 for (j = 0; j < ETHERADDRL; j++) { 3723 nxgep->nxge_mmac_info.factory_mac_pool[i][j] = 3724 *(prop_val + (i * ETHERADDRL) + j); 3725 } 3726 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 3727 "nxge_get_mac_addr_properties: Alt mac[%d] from " 3728 "mac-addresses property[%2x:%2x:%2x:%2x:%2x:%2x]", 3729 i, nxgep->nxge_mmac_info.factory_mac_pool[i][0], 3730 nxgep->nxge_mmac_info.factory_mac_pool[i][1], 3731 nxgep->nxge_mmac_info.factory_mac_pool[i][2], 3732 nxgep->nxge_mmac_info.factory_mac_pool[i][3], 3733 nxgep->nxge_mmac_info.factory_mac_pool[i][4], 3734 nxgep->nxge_mmac_info.factory_mac_pool[i][5])); 3735 } 3736 3737 compute_macs = B_FALSE; 3738 ddi_prop_free(prop_val); 3739 goto got_mmac_info; 3740 } 3741 #endif 3742 /* 3743 * total_factory_macs = 32 3744 * num_factory_mmac = (32 >> (nports/2)) - 1 3745 * So if nports = 4, then num_factory_mmac = 7 3746 * if nports = 2, then num_factory_mmac = 15 3747 */ 3748 nxgep->nxge_mmac_info.num_factory_mmac = 3749 ((nxgep->nxge_mmac_info.total_factory_macs >> 3750 (nxgep->nports >> 1))) - 1; 3751 3752 got_mmac_info: 3753 3754 if ((nxgep->function_num < 2) && 3755 (nxgep->nxge_mmac_info.num_factory_mmac > 3756 XMAC_MAX_ALT_ADDR_ENTRY)) { 3757 nxgep->nxge_mmac_info.num_factory_mmac = 3758 XMAC_MAX_ALT_ADDR_ENTRY; 3759 } else if ((nxgep->function_num > 1) && 3760 (nxgep->nxge_mmac_info.num_factory_mmac > 3761 BMAC_MAX_ALT_ADDR_ENTRY)) { 3762 nxgep->nxge_mmac_info.num_factory_mmac = 3763 BMAC_MAX_ALT_ADDR_ENTRY; 3764 } 3765 3766 for (i = 0; i <= nxgep->nxge_mmac_info.num_mmac; i++) { 3767 (void) npi_mac_altaddr_disable(nxgep->npi_handle, 3768 NXGE_GET_PORT_NUM(func_num), i); 3769 } 3770 3771 (void) nxge_init_mmac(nxgep, compute_macs); 3772 return (NXGE_OK); 3773 } 3774 3775 void 3776 nxge_get_xcvr_properties(p_nxge_t nxgep) 3777 { 3778 uchar_t *prop_val; 3779 uint_t prop_len; 3780 3781 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_xcvr_properties")); 3782 3783 /* 3784 * Read the type of physical layer interface being used. 3785 */ 3786 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 3787 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3788 "phy-type", &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 3789 if (strncmp("pcs", (caddr_t)prop_val, 3790 (size_t)prop_len) == 0) { 3791 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 3792 } else { 3793 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 3794 } 3795 ddi_prop_free(prop_val); 3796 } else if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3797 "phy-interface", &prop_val, 3798 &prop_len) == DDI_PROP_SUCCESS) { 3799 if (strncmp("pcs", (caddr_t)prop_val, (size_t)prop_len) == 0) { 3800 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 3801 } else { 3802 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 3803 } 3804 ddi_prop_free(prop_val); 3805 } 3806 } 3807 3808 /* 3809 * Static functions start here. 3810 */ 3811 3812 static void 3813 nxge_ldgv_setup(p_nxge_ldg_t *ldgp, p_nxge_ldv_t *ldvp, uint8_t ldv, 3814 uint8_t endldg, int *ngrps) 3815 { 3816 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup")); 3817 /* Assign the group number for each device. */ 3818 (*ldvp)->ldg_assigned = (*ldgp)->ldg; 3819 (*ldvp)->ldgp = *ldgp; 3820 (*ldvp)->ldv = ldv; 3821 3822 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup: " 3823 "ldv %d endldg %d ldg %d, ldvp $%p", 3824 ldv, endldg, (*ldgp)->ldg, (*ldgp)->ldvp)); 3825 3826 (*ldgp)->nldvs++; 3827 if ((*ldgp)->ldg == (endldg - 1)) { 3828 if ((*ldgp)->ldvp == NULL) { 3829 (*ldgp)->ldvp = *ldvp; 3830 *ngrps += 1; 3831 NXGE_DEBUG_MSG((NULL, INT_CTL, 3832 "==> nxge_ldgv_setup: ngrps %d", *ngrps)); 3833 } 3834 NXGE_DEBUG_MSG((NULL, INT_CTL, 3835 "==> nxge_ldgv_setup: ldvp $%p ngrps %d", 3836 *ldvp, *ngrps)); 3837 ++*ldvp; 3838 } else { 3839 (*ldgp)->ldvp = *ldvp; 3840 *ngrps += 1; 3841 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup(done): " 3842 "ldv %d endldg %d ldg %d, ldvp $%p", 3843 ldv, endldg, (*ldgp)->ldg, (*ldgp)->ldvp)); 3844 (*ldvp) = ++*ldvp; 3845 (*ldgp) = ++*ldgp; 3846 NXGE_DEBUG_MSG((NULL, INT_CTL, 3847 "==> nxge_ldgv_setup: new ngrps %d", *ngrps)); 3848 } 3849 3850 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup: " 3851 "ldv %d ldvp $%p endldg %d ngrps %d", 3852 ldv, ldvp, endldg, *ngrps)); 3853 3854 NXGE_DEBUG_MSG((NULL, INT_CTL, "<== nxge_ldgv_setup")); 3855 } 3856 3857 /* 3858 * Note: This function assumes the following distribution of mac 3859 * addresses among 4 ports in neptune: 3860 * 3861 * ------------- 3862 * 0| |0 - local-mac-address for fn 0 3863 * ------------- 3864 * 1| |1 - local-mac-address for fn 1 3865 * ------------- 3866 * 2| |2 - local-mac-address for fn 2 3867 * ------------- 3868 * 3| |3 - local-mac-address for fn 3 3869 * ------------- 3870 * | |4 - Start of alt. mac addr. for fn 0 3871 * | | 3872 * | | 3873 * | |10 3874 * -------------- 3875 * | |11 - Start of alt. mac addr. for fn 1 3876 * | | 3877 * | | 3878 * | |17 3879 * -------------- 3880 * | |18 - Start of alt. mac addr. for fn 2 3881 * | | 3882 * | | 3883 * | |24 3884 * -------------- 3885 * | |25 - Start of alt. mac addr. for fn 3 3886 * | | 3887 * | | 3888 * | |31 3889 * -------------- 3890 * 3891 * For N2/NIU the mac addresses is from XAUI card. 3892 * 3893 * When 'compute_addrs' is true, the alternate mac addresses are computed 3894 * using the unique mac address as base. Otherwise the alternate addresses 3895 * are assigned from the list read off the 'mac-addresses' property. 3896 */ 3897 3898 static void 3899 nxge_init_mmac(p_nxge_t nxgep, boolean_t compute_addrs) 3900 { 3901 int slot; 3902 uint8_t func_num; 3903 uint16_t *base_mmac_addr; 3904 uint32_t alt_mac_ls4b; 3905 uint16_t *mmac_addr; 3906 uint32_t base_mac_ls4b; /* least significant 4 bytes */ 3907 nxge_mmac_t *mmac_info; 3908 npi_mac_addr_t mac_addr; 3909 3910 func_num = nxgep->function_num; 3911 base_mmac_addr = (uint16_t *)&nxgep->factaddr; 3912 mmac_info = (nxge_mmac_t *)&nxgep->nxge_mmac_info; 3913 3914 if (compute_addrs) { 3915 base_mac_ls4b = ((uint32_t)base_mmac_addr[1]) << 16 | 3916 base_mmac_addr[2]; 3917 3918 if (nxgep->niu_type == N2_NIU) { 3919 /* ls4b of 1st altmac */ 3920 alt_mac_ls4b = base_mac_ls4b + 1; 3921 } else { /* Neptune */ 3922 alt_mac_ls4b = base_mac_ls4b + 3923 (nxgep->nports - func_num) + 3924 (func_num * (mmac_info->num_factory_mmac)); 3925 } 3926 } 3927 3928 /* Set flags for unique MAC */ 3929 mmac_info->mac_pool[0].flags |= MMAC_SLOT_USED | MMAC_VENDOR_ADDR; 3930 3931 /* Clear flags of all alternate MAC slots */ 3932 for (slot = 1; slot <= mmac_info->num_mmac; slot++) { 3933 if (slot <= mmac_info->num_factory_mmac) 3934 mmac_info->mac_pool[slot].flags = MMAC_VENDOR_ADDR; 3935 else 3936 mmac_info->mac_pool[slot].flags = 0; 3937 } 3938 3939 /* Generate and store factory alternate MACs */ 3940 for (slot = 1; slot <= mmac_info->num_factory_mmac; slot++) { 3941 mmac_addr = (uint16_t *)&mmac_info->factory_mac_pool[slot]; 3942 if (compute_addrs) { 3943 mmac_addr[0] = base_mmac_addr[0]; 3944 mac_addr.w2 = mmac_addr[0]; 3945 3946 mmac_addr[1] = (alt_mac_ls4b >> 16) & 0x0FFFF; 3947 mac_addr.w1 = mmac_addr[1]; 3948 3949 mmac_addr[2] = alt_mac_ls4b & 0x0FFFF; 3950 mac_addr.w0 = mmac_addr[2]; 3951 3952 alt_mac_ls4b++; 3953 } else { 3954 mac_addr.w2 = mmac_addr[0]; 3955 mac_addr.w1 = mmac_addr[1]; 3956 mac_addr.w0 = mmac_addr[2]; 3957 } 3958 3959 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 3960 "mac_pool_addr[%2x:%2x:%2x:%2x:%2x:%2x] npi_addr[%x%x%x]", 3961 mmac_info->factory_mac_pool[slot][0], 3962 mmac_info->factory_mac_pool[slot][1], 3963 mmac_info->factory_mac_pool[slot][2], 3964 mmac_info->factory_mac_pool[slot][3], 3965 mmac_info->factory_mac_pool[slot][4], 3966 mmac_info->factory_mac_pool[slot][5], 3967 mac_addr.w0, mac_addr.w1, mac_addr.w2)); 3968 /* 3969 * slot minus 1 because npi_mac_altaddr_entry expects 0 3970 * for the first alternate mac address. 3971 */ 3972 (void) npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET, 3973 NXGE_GET_PORT_NUM(func_num), slot - 1, &mac_addr); 3974 } 3975 /* Initialize the first two parameters for mmac kstat */ 3976 nxgep->statsp->mmac_stats.mmac_max_cnt = mmac_info->num_mmac; 3977 nxgep->statsp->mmac_stats.mmac_avail_cnt = mmac_info->num_mmac; 3978 } 3979 3980 /* 3981 * Convert an RDC group index into a port ring index. That is, map 3982 * <groupid> to an index into nxgep->rx_ring_handles. 3983 * (group ring index -> port ring index) 3984 */ 3985 int 3986 nxge_get_rxring_index(p_nxge_t nxgep, int groupid, int ringidx) 3987 { 3988 int i; 3989 int index = 0; 3990 p_nxge_rdc_grp_t rdc_grp_p; 3991 p_nxge_dma_pt_cfg_t p_dma_cfgp; 3992 p_nxge_hw_pt_cfg_t p_cfgp; 3993 3994 p_dma_cfgp = &nxgep->pt_config; 3995 p_cfgp = &p_dma_cfgp->hw_config; 3996 3997 for (i = 0; i < groupid; i++) { 3998 rdc_grp_p = 3999 &p_dma_cfgp->rdc_grps[p_cfgp->def_mac_rxdma_grpid + i]; 4000 index += rdc_grp_p->max_rdcs; 4001 } 4002 4003 return (index + ringidx); 4004 } 4005