1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <sys/nxge/nxge_hio.h> 30 #include <npi_tx_wr64.h> 31 32 /* Software LSO required header files */ 33 #include <netinet/tcp.h> 34 #include <inet/ip_impl.h> 35 #include <inet/tcp.h> 36 37 static mblk_t *nxge_lso_eliminate(mblk_t *); 38 static mblk_t *nxge_do_softlso(mblk_t *mp, uint32_t mss); 39 static void nxge_lso_info_get(mblk_t *, uint32_t *, uint32_t *); 40 static void nxge_hcksum_retrieve(mblk_t *, 41 uint32_t *, uint32_t *, uint32_t *, 42 uint32_t *, uint32_t *); 43 static uint32_t nxge_csgen(uint16_t *, int); 44 45 extern uint32_t nxge_reclaim_pending; 46 extern uint32_t nxge_bcopy_thresh; 47 extern uint32_t nxge_dvma_thresh; 48 extern uint32_t nxge_dma_stream_thresh; 49 extern uint32_t nxge_tx_minfree; 50 extern uint32_t nxge_tx_intr_thres; 51 extern uint32_t nxge_tx_max_gathers; 52 extern uint32_t nxge_tx_tiny_pack; 53 extern uint32_t nxge_tx_use_bcopy; 54 extern uint32_t nxge_tx_lb_policy; 55 extern uint32_t nxge_no_tx_lb; 56 extern nxge_tx_mode_t nxge_tx_scheme; 57 uint32_t nxge_lso_kick_cnt = 2; 58 59 typedef struct _mac_tx_hint { 60 uint16_t sap; 61 uint16_t vid; 62 void *hash; 63 } mac_tx_hint_t, *p_mac_tx_hint_t; 64 65 int nxge_tx_lb_ring_1(p_mblk_t, uint32_t, p_mac_tx_hint_t); 66 67 int 68 nxge_start(p_nxge_t nxgep, p_tx_ring_t tx_ring_p, p_mblk_t mp) 69 { 70 int status = 0; 71 p_tx_desc_t tx_desc_ring_vp; 72 npi_handle_t npi_desc_handle; 73 nxge_os_dma_handle_t tx_desc_dma_handle; 74 p_tx_desc_t tx_desc_p; 75 p_tx_msg_t tx_msg_ring; 76 p_tx_msg_t tx_msg_p; 77 tx_desc_t tx_desc, *tmp_desc_p; 78 tx_desc_t sop_tx_desc, *sop_tx_desc_p; 79 p_tx_pkt_header_t hdrp; 80 p_tx_pkt_hdr_all_t pkthdrp; 81 uint8_t npads = 0; 82 uint64_t dma_ioaddr; 83 uint32_t dma_flags; 84 int last_bidx; 85 uint8_t *b_rptr; 86 caddr_t kaddr; 87 uint32_t nmblks; 88 uint32_t ngathers; 89 uint32_t clen; 90 int len; 91 uint32_t pkt_len, pack_len, min_len; 92 uint32_t bcopy_thresh; 93 int i, cur_index, sop_index; 94 uint16_t tail_index; 95 boolean_t tail_wrap = B_FALSE; 96 nxge_dma_common_t desc_area; 97 nxge_os_dma_handle_t dma_handle; 98 ddi_dma_cookie_t dma_cookie; 99 npi_handle_t npi_handle; 100 p_mblk_t nmp; 101 p_mblk_t t_mp; 102 uint32_t ncookies; 103 boolean_t good_packet; 104 boolean_t mark_mode = B_FALSE; 105 p_nxge_stats_t statsp; 106 p_nxge_tx_ring_stats_t tdc_stats; 107 t_uscalar_t start_offset = 0; 108 t_uscalar_t stuff_offset = 0; 109 t_uscalar_t end_offset = 0; 110 t_uscalar_t value = 0; 111 t_uscalar_t cksum_flags = 0; 112 boolean_t cksum_on = B_FALSE; 113 uint32_t boff = 0; 114 uint64_t tot_xfer_len = 0, tmp_len = 0; 115 boolean_t header_set = B_FALSE; 116 #ifdef NXGE_DEBUG 117 p_tx_desc_t tx_desc_ring_pp; 118 p_tx_desc_t tx_desc_pp; 119 tx_desc_t *save_desc_p; 120 int dump_len; 121 int sad_len; 122 uint64_t sad; 123 int xfer_len; 124 uint32_t msgsize; 125 #endif 126 p_mblk_t mp_chain = NULL; 127 boolean_t is_lso = B_FALSE; 128 boolean_t lso_again; 129 int cur_index_lso; 130 p_mblk_t nmp_lso_save; 131 uint32_t lso_ngathers; 132 boolean_t lso_tail_wrap = B_FALSE; 133 134 NXGE_DEBUG_MSG((nxgep, TX_CTL, 135 "==> nxge_start: tx dma channel %d", tx_ring_p->tdc)); 136 NXGE_DEBUG_MSG((nxgep, TX_CTL, 137 "==> nxge_start: Starting tdc %d desc pending %d", 138 tx_ring_p->tdc, tx_ring_p->descs_pending)); 139 140 statsp = nxgep->statsp; 141 142 if (!isLDOMguest(nxgep)) { 143 switch (nxgep->mac.portmode) { 144 default: 145 if (nxgep->statsp->port_stats.lb_mode == 146 nxge_lb_normal) { 147 if (!statsp->mac_stats.link_up) { 148 freemsg(mp); 149 NXGE_DEBUG_MSG((nxgep, TX_CTL, 150 "==> nxge_start: " 151 "link not up")); 152 goto nxge_start_fail1; 153 } 154 } 155 break; 156 case PORT_10G_FIBER: 157 /* 158 * For the following modes, check the link status 159 * before sending the packet out: 160 * nxge_lb_normal, nxge_lb_ext10g, nxge_lb_phy10g 161 */ 162 if (nxgep->statsp->port_stats.lb_mode < 163 nxge_lb_serdes10g) { 164 if (!statsp->mac_stats.link_up) { 165 freemsg(mp); 166 NXGE_DEBUG_MSG((nxgep, TX_CTL, 167 "==> nxge_start: " 168 "link not up")); 169 goto nxge_start_fail1; 170 } 171 } 172 break; 173 } 174 } 175 176 if ((!(nxgep->drv_state & STATE_HW_INITIALIZED)) || 177 (nxgep->nxge_mac_state != NXGE_MAC_STARTED)) { 178 NXGE_DEBUG_MSG((nxgep, TX_CTL, 179 "==> nxge_start: hardware not initialized or stopped")); 180 freemsg(mp); 181 goto nxge_start_fail1; 182 } 183 184 if (nxgep->soft_lso_enable) { 185 mp_chain = nxge_lso_eliminate(mp); 186 NXGE_DEBUG_MSG((nxgep, TX_CTL, 187 "==> nxge_start(0): LSO mp $%p mp_chain $%p", 188 mp, mp_chain)); 189 if (mp_chain == NULL) { 190 NXGE_ERROR_MSG((nxgep, TX_CTL, 191 "==> nxge_send(0): NULL mp_chain $%p != mp $%p", 192 mp_chain, mp)); 193 goto nxge_start_fail1; 194 } 195 if (mp_chain != mp) { 196 NXGE_DEBUG_MSG((nxgep, TX_CTL, 197 "==> nxge_send(1): IS LSO mp_chain $%p != mp $%p", 198 mp_chain, mp)); 199 is_lso = B_TRUE; 200 mp = mp_chain; 201 mp_chain = mp_chain->b_next; 202 mp->b_next = NULL; 203 } 204 } 205 206 hcksum_retrieve(mp, NULL, NULL, &start_offset, 207 &stuff_offset, &end_offset, &value, &cksum_flags); 208 if (!NXGE_IS_VLAN_PACKET(mp->b_rptr)) { 209 start_offset += sizeof (ether_header_t); 210 stuff_offset += sizeof (ether_header_t); 211 } else { 212 start_offset += sizeof (struct ether_vlan_header); 213 stuff_offset += sizeof (struct ether_vlan_header); 214 } 215 216 if (cksum_flags & HCK_PARTIALCKSUM) { 217 NXGE_DEBUG_MSG((nxgep, TX_CTL, 218 "==> nxge_start: mp $%p len %d " 219 "cksum_flags 0x%x (partial checksum) ", 220 mp, MBLKL(mp), cksum_flags)); 221 cksum_on = B_TRUE; 222 } 223 224 lso_again = B_FALSE; 225 lso_ngathers = 0; 226 227 MUTEX_ENTER(&tx_ring_p->lock); 228 cur_index_lso = tx_ring_p->wr_index; 229 lso_tail_wrap = tx_ring_p->wr_index_wrap; 230 start_again: 231 ngathers = 0; 232 sop_index = tx_ring_p->wr_index; 233 #ifdef NXGE_DEBUG 234 if (tx_ring_p->descs_pending) { 235 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: " 236 "desc pending %d ", tx_ring_p->descs_pending)); 237 } 238 239 dump_len = (int)(MBLKL(mp)); 240 dump_len = (dump_len > 128) ? 128: dump_len; 241 242 NXGE_DEBUG_MSG((nxgep, TX_CTL, 243 "==> nxge_start: tdc %d: dumping ...: b_rptr $%p " 244 "(Before header reserve: ORIGINAL LEN %d)", 245 tx_ring_p->tdc, 246 mp->b_rptr, 247 dump_len)); 248 249 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: dump packets " 250 "(IP ORIGINAL b_rptr $%p): %s", mp->b_rptr, 251 nxge_dump_packet((char *)mp->b_rptr, dump_len))); 252 #endif 253 254 tdc_stats = tx_ring_p->tdc_stats; 255 mark_mode = (tx_ring_p->descs_pending && 256 ((tx_ring_p->tx_ring_size - tx_ring_p->descs_pending) 257 < nxge_tx_minfree)); 258 259 NXGE_DEBUG_MSG((nxgep, TX_CTL, 260 "TX Descriptor ring is channel %d mark mode %d", 261 tx_ring_p->tdc, mark_mode)); 262 263 if (!nxge_txdma_reclaim(nxgep, tx_ring_p, nxge_tx_minfree)) { 264 NXGE_DEBUG_MSG((nxgep, TX_CTL, 265 "TX Descriptor ring is full: channel %d", 266 tx_ring_p->tdc)); 267 NXGE_DEBUG_MSG((nxgep, TX_CTL, 268 "TX Descriptor ring is full: channel %d", 269 tx_ring_p->tdc)); 270 if (is_lso) { 271 /* free the current mp and mp_chain if not FULL */ 272 tdc_stats->tx_no_desc++; 273 NXGE_DEBUG_MSG((nxgep, TX_CTL, 274 "LSO packet: TX Descriptor ring is full: " 275 "channel %d", 276 tx_ring_p->tdc)); 277 goto nxge_start_fail_lso; 278 } else { 279 cas32((uint32_t *)&tx_ring_p->queueing, 0, 1); 280 tdc_stats->tx_no_desc++; 281 MUTEX_EXIT(&tx_ring_p->lock); 282 if (nxgep->resched_needed && !nxgep->resched_running) { 283 nxgep->resched_running = B_TRUE; 284 ddi_trigger_softintr(nxgep->resched_id); 285 } 286 status = 1; 287 goto nxge_start_fail1; 288 } 289 } 290 291 nmp = mp; 292 i = sop_index = tx_ring_p->wr_index; 293 nmblks = 0; 294 ngathers = 0; 295 pkt_len = 0; 296 pack_len = 0; 297 clen = 0; 298 last_bidx = -1; 299 good_packet = B_TRUE; 300 301 desc_area = tx_ring_p->tdc_desc; 302 npi_handle = desc_area.npi_handle; 303 npi_desc_handle.regh = (nxge_os_acc_handle_t) 304 DMA_COMMON_ACC_HANDLE(desc_area); 305 tx_desc_ring_vp = (p_tx_desc_t)DMA_COMMON_VPTR(desc_area); 306 tx_desc_dma_handle = (nxge_os_dma_handle_t) 307 DMA_COMMON_HANDLE(desc_area); 308 tx_msg_ring = tx_ring_p->tx_msg_ring; 309 310 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: wr_index %d i %d", 311 sop_index, i)); 312 313 #ifdef NXGE_DEBUG 314 msgsize = msgdsize(nmp); 315 NXGE_DEBUG_MSG((nxgep, TX_CTL, 316 "==> nxge_start(1): wr_index %d i %d msgdsize %d", 317 sop_index, i, msgsize)); 318 #endif 319 /* 320 * The first 16 bytes of the premapped buffer are reserved 321 * for header. No padding will be used. 322 */ 323 pkt_len = pack_len = boff = TX_PKT_HEADER_SIZE; 324 if (nxge_tx_use_bcopy && (nxgep->niu_type != N2_NIU)) { 325 bcopy_thresh = (nxge_bcopy_thresh - TX_PKT_HEADER_SIZE); 326 } else { 327 bcopy_thresh = (TX_BCOPY_SIZE - TX_PKT_HEADER_SIZE); 328 } 329 while (nmp) { 330 good_packet = B_TRUE; 331 b_rptr = nmp->b_rptr; 332 len = MBLKL(nmp); 333 if (len <= 0) { 334 nmp = nmp->b_cont; 335 continue; 336 } 337 nmblks++; 338 339 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start(1): nmblks %d " 340 "len %d pkt_len %d pack_len %d", 341 nmblks, len, pkt_len, pack_len)); 342 /* 343 * Hardware limits the transfer length to 4K for NIU and 344 * 4076 (TX_MAX_TRANSFER_LENGTH) for Neptune. But we just 345 * use TX_MAX_TRANSFER_LENGTH as the limit for both. 346 * If len is longer than the limit, then we break nmp into 347 * two chunks: Make the first chunk equal to the limit and 348 * the second chunk for the remaining data. If the second 349 * chunk is still larger than the limit, then it will be 350 * broken into two in the next pass. 351 */ 352 if (len > TX_MAX_TRANSFER_LENGTH - TX_PKT_HEADER_SIZE) { 353 if ((t_mp = dupb(nmp)) != NULL) { 354 nmp->b_wptr = nmp->b_rptr + 355 (TX_MAX_TRANSFER_LENGTH 356 - TX_PKT_HEADER_SIZE); 357 t_mp->b_rptr = nmp->b_wptr; 358 t_mp->b_cont = nmp->b_cont; 359 nmp->b_cont = t_mp; 360 len = MBLKL(nmp); 361 } else { 362 if (is_lso) { 363 NXGE_DEBUG_MSG((nxgep, TX_CTL, 364 "LSO packet: dupb failed: " 365 "channel %d", 366 tx_ring_p->tdc)); 367 mp = nmp; 368 goto nxge_start_fail_lso; 369 } else { 370 good_packet = B_FALSE; 371 goto nxge_start_fail2; 372 } 373 } 374 } 375 tx_desc.value = 0; 376 tx_desc_p = &tx_desc_ring_vp[i]; 377 #ifdef NXGE_DEBUG 378 tx_desc_pp = &tx_desc_ring_pp[i]; 379 #endif 380 tx_msg_p = &tx_msg_ring[i]; 381 #if defined(__i386) 382 npi_desc_handle.regp = (uint32_t)tx_desc_p; 383 #else 384 npi_desc_handle.regp = (uint64_t)tx_desc_p; 385 #endif 386 if (!header_set && 387 ((!nxge_tx_use_bcopy && (len > TX_BCOPY_SIZE)) || 388 (len >= bcopy_thresh))) { 389 header_set = B_TRUE; 390 bcopy_thresh += TX_PKT_HEADER_SIZE; 391 boff = 0; 392 pack_len = 0; 393 kaddr = (caddr_t)DMA_COMMON_VPTR(tx_msg_p->buf_dma); 394 hdrp = (p_tx_pkt_header_t)kaddr; 395 clen = pkt_len; 396 dma_handle = tx_msg_p->buf_dma_handle; 397 dma_ioaddr = DMA_COMMON_IOADDR(tx_msg_p->buf_dma); 398 (void) ddi_dma_sync(dma_handle, 399 i * nxge_bcopy_thresh, nxge_bcopy_thresh, 400 DDI_DMA_SYNC_FORDEV); 401 402 tx_msg_p->flags.dma_type = USE_BCOPY; 403 goto nxge_start_control_header_only; 404 } 405 406 pkt_len += len; 407 pack_len += len; 408 409 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start(3): " 410 "desc entry %d " 411 "DESC IOADDR $%p " 412 "desc_vp $%p tx_desc_p $%p " 413 "desc_pp $%p tx_desc_pp $%p " 414 "len %d pkt_len %d pack_len %d", 415 i, 416 DMA_COMMON_IOADDR(desc_area), 417 tx_desc_ring_vp, tx_desc_p, 418 tx_desc_ring_pp, tx_desc_pp, 419 len, pkt_len, pack_len)); 420 421 if (len < bcopy_thresh) { 422 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start(4): " 423 "USE BCOPY: ")); 424 if (nxge_tx_tiny_pack) { 425 uint32_t blst = 426 TXDMA_DESC_NEXT_INDEX(i, -1, 427 tx_ring_p->tx_wrap_mask); 428 NXGE_DEBUG_MSG((nxgep, TX_CTL, 429 "==> nxge_start(5): pack")); 430 if ((pack_len <= bcopy_thresh) && 431 (last_bidx == blst)) { 432 NXGE_DEBUG_MSG((nxgep, TX_CTL, 433 "==> nxge_start: pack(6) " 434 "(pkt_len %d pack_len %d)", 435 pkt_len, pack_len)); 436 i = blst; 437 tx_desc_p = &tx_desc_ring_vp[i]; 438 #ifdef NXGE_DEBUG 439 tx_desc_pp = &tx_desc_ring_pp[i]; 440 #endif 441 tx_msg_p = &tx_msg_ring[i]; 442 boff = pack_len - len; 443 ngathers--; 444 } else if (pack_len > bcopy_thresh && 445 header_set) { 446 pack_len = len; 447 boff = 0; 448 bcopy_thresh = nxge_bcopy_thresh; 449 NXGE_DEBUG_MSG((nxgep, TX_CTL, 450 "==> nxge_start(7): > max NEW " 451 "bcopy thresh %d " 452 "pkt_len %d pack_len %d(next)", 453 bcopy_thresh, 454 pkt_len, pack_len)); 455 } 456 last_bidx = i; 457 } 458 kaddr = (caddr_t)DMA_COMMON_VPTR(tx_msg_p->buf_dma); 459 if ((boff == TX_PKT_HEADER_SIZE) && (nmblks == 1)) { 460 hdrp = (p_tx_pkt_header_t)kaddr; 461 header_set = B_TRUE; 462 NXGE_DEBUG_MSG((nxgep, TX_CTL, 463 "==> nxge_start(7_x2): " 464 "pkt_len %d pack_len %d (new hdrp $%p)", 465 pkt_len, pack_len, hdrp)); 466 } 467 tx_msg_p->flags.dma_type = USE_BCOPY; 468 kaddr += boff; 469 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start(8): " 470 "USE BCOPY: before bcopy " 471 "DESC IOADDR $%p entry %d " 472 "bcopy packets %d " 473 "bcopy kaddr $%p " 474 "bcopy ioaddr (SAD) $%p " 475 "bcopy clen %d " 476 "bcopy boff %d", 477 DMA_COMMON_IOADDR(desc_area), i, 478 tdc_stats->tx_hdr_pkts, 479 kaddr, 480 dma_ioaddr, 481 clen, 482 boff)); 483 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: " 484 "1USE BCOPY: ")); 485 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: " 486 "2USE BCOPY: ")); 487 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: " 488 "last USE BCOPY: copy from b_rptr $%p " 489 "to KADDR $%p (len %d offset %d", 490 b_rptr, kaddr, len, boff)); 491 492 bcopy(b_rptr, kaddr, len); 493 494 #ifdef NXGE_DEBUG 495 dump_len = (len > 128) ? 128: len; 496 NXGE_DEBUG_MSG((nxgep, TX_CTL, 497 "==> nxge_start: dump packets " 498 "(After BCOPY len %d)" 499 "(b_rptr $%p): %s", len, nmp->b_rptr, 500 nxge_dump_packet((char *)nmp->b_rptr, 501 dump_len))); 502 #endif 503 504 dma_handle = tx_msg_p->buf_dma_handle; 505 dma_ioaddr = DMA_COMMON_IOADDR(tx_msg_p->buf_dma); 506 (void) ddi_dma_sync(dma_handle, 507 i * nxge_bcopy_thresh, nxge_bcopy_thresh, 508 DDI_DMA_SYNC_FORDEV); 509 clen = len + boff; 510 tdc_stats->tx_hdr_pkts++; 511 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start(9): " 512 "USE BCOPY: " 513 "DESC IOADDR $%p entry %d " 514 "bcopy packets %d " 515 "bcopy kaddr $%p " 516 "bcopy ioaddr (SAD) $%p " 517 "bcopy clen %d " 518 "bcopy boff %d", 519 DMA_COMMON_IOADDR(desc_area), 520 i, 521 tdc_stats->tx_hdr_pkts, 522 kaddr, 523 dma_ioaddr, 524 clen, 525 boff)); 526 } else { 527 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start(12): " 528 "USE DVMA: len %d", len)); 529 tx_msg_p->flags.dma_type = USE_DMA; 530 dma_flags = DDI_DMA_WRITE; 531 if (len < nxge_dma_stream_thresh) { 532 dma_flags |= DDI_DMA_CONSISTENT; 533 } else { 534 dma_flags |= DDI_DMA_STREAMING; 535 } 536 537 dma_handle = tx_msg_p->dma_handle; 538 status = ddi_dma_addr_bind_handle(dma_handle, NULL, 539 (caddr_t)b_rptr, len, dma_flags, 540 DDI_DMA_DONTWAIT, NULL, 541 &dma_cookie, &ncookies); 542 if (status == DDI_DMA_MAPPED) { 543 dma_ioaddr = dma_cookie.dmac_laddress; 544 len = (int)dma_cookie.dmac_size; 545 clen = (uint32_t)dma_cookie.dmac_size; 546 NXGE_DEBUG_MSG((nxgep, TX_CTL, 547 "==> nxge_start(12_1): " 548 "USE DVMA: len %d clen %d " 549 "ngathers %d", 550 len, clen, 551 ngathers)); 552 #if defined(__i386) 553 npi_desc_handle.regp = (uint32_t)tx_desc_p; 554 #else 555 npi_desc_handle.regp = (uint64_t)tx_desc_p; 556 #endif 557 while (ncookies > 1) { 558 ngathers++; 559 /* 560 * this is the fix for multiple 561 * cookies, which are basically 562 * a descriptor entry, we don't set 563 * SOP bit as well as related fields 564 */ 565 566 (void) npi_txdma_desc_gather_set( 567 npi_desc_handle, 568 &tx_desc, 569 (ngathers -1), 570 mark_mode, 571 ngathers, 572 dma_ioaddr, 573 clen); 574 575 tx_msg_p->tx_msg_size = clen; 576 NXGE_DEBUG_MSG((nxgep, TX_CTL, 577 "==> nxge_start: DMA " 578 "ncookie %d " 579 "ngathers %d " 580 "dma_ioaddr $%p len %d" 581 "desc $%p descp $%p (%d)", 582 ncookies, 583 ngathers, 584 dma_ioaddr, clen, 585 *tx_desc_p, tx_desc_p, i)); 586 587 ddi_dma_nextcookie(dma_handle, 588 &dma_cookie); 589 dma_ioaddr = 590 dma_cookie.dmac_laddress; 591 592 len = (int)dma_cookie.dmac_size; 593 clen = (uint32_t)dma_cookie.dmac_size; 594 NXGE_DEBUG_MSG((nxgep, TX_CTL, 595 "==> nxge_start(12_2): " 596 "USE DVMA: len %d clen %d ", 597 len, clen)); 598 599 i = TXDMA_DESC_NEXT_INDEX(i, 1, 600 tx_ring_p->tx_wrap_mask); 601 tx_desc_p = &tx_desc_ring_vp[i]; 602 603 npi_desc_handle.regp = 604 #if defined(__i386) 605 (uint32_t)tx_desc_p; 606 #else 607 (uint64_t)tx_desc_p; 608 #endif 609 tx_msg_p = &tx_msg_ring[i]; 610 tx_msg_p->flags.dma_type = USE_NONE; 611 tx_desc.value = 0; 612 613 ncookies--; 614 } 615 tdc_stats->tx_ddi_pkts++; 616 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start:" 617 "DMA: ddi packets %d", 618 tdc_stats->tx_ddi_pkts)); 619 } else { 620 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 621 "dma mapping failed for %d " 622 "bytes addr $%p flags %x (%d)", 623 len, b_rptr, status, status)); 624 good_packet = B_FALSE; 625 tdc_stats->tx_dma_bind_fail++; 626 tx_msg_p->flags.dma_type = USE_NONE; 627 if (is_lso) { 628 mp = nmp; 629 goto nxge_start_fail_lso; 630 } else { 631 goto nxge_start_fail2; 632 } 633 } 634 } /* ddi dvma */ 635 636 if (is_lso) { 637 nmp_lso_save = nmp; 638 } 639 nmp = nmp->b_cont; 640 nxge_start_control_header_only: 641 #if defined(__i386) 642 npi_desc_handle.regp = (uint32_t)tx_desc_p; 643 #else 644 npi_desc_handle.regp = (uint64_t)tx_desc_p; 645 #endif 646 ngathers++; 647 648 if (ngathers == 1) { 649 #ifdef NXGE_DEBUG 650 save_desc_p = &sop_tx_desc; 651 #endif 652 sop_tx_desc_p = &sop_tx_desc; 653 sop_tx_desc_p->value = 0; 654 sop_tx_desc_p->bits.hdw.tr_len = clen; 655 sop_tx_desc_p->bits.hdw.sad = dma_ioaddr >> 32; 656 sop_tx_desc_p->bits.ldw.sad = dma_ioaddr & 0xffffffff; 657 } else { 658 #ifdef NXGE_DEBUG 659 save_desc_p = &tx_desc; 660 #endif 661 tmp_desc_p = &tx_desc; 662 tmp_desc_p->value = 0; 663 tmp_desc_p->bits.hdw.tr_len = clen; 664 tmp_desc_p->bits.hdw.sad = dma_ioaddr >> 32; 665 tmp_desc_p->bits.ldw.sad = dma_ioaddr & 0xffffffff; 666 667 tx_desc_p->value = tmp_desc_p->value; 668 } 669 670 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start(13): " 671 "Desc_entry %d ngathers %d " 672 "desc_vp $%p tx_desc_p $%p " 673 "len %d clen %d pkt_len %d pack_len %d nmblks %d " 674 "dma_ioaddr (SAD) $%p mark %d", 675 i, ngathers, 676 tx_desc_ring_vp, tx_desc_p, 677 len, clen, pkt_len, pack_len, nmblks, 678 dma_ioaddr, mark_mode)); 679 680 #ifdef NXGE_DEBUG 681 npi_desc_handle.nxgep = nxgep; 682 npi_desc_handle.function.function = nxgep->function_num; 683 npi_desc_handle.function.instance = nxgep->instance; 684 sad = (save_desc_p->value & TX_PKT_DESC_SAD_MASK); 685 xfer_len = ((save_desc_p->value & TX_PKT_DESC_TR_LEN_MASK) >> 686 TX_PKT_DESC_TR_LEN_SHIFT); 687 688 689 NXGE_DEBUG_MSG((nxgep, TX_CTL, "\n\t: value 0x%llx\n" 690 "\t\tsad $%p\ttr_len %d len %d\tnptrs %d\t" 691 "mark %d sop %d\n", 692 save_desc_p->value, 693 sad, 694 save_desc_p->bits.hdw.tr_len, 695 xfer_len, 696 save_desc_p->bits.hdw.num_ptr, 697 save_desc_p->bits.hdw.mark, 698 save_desc_p->bits.hdw.sop)); 699 700 npi_txdma_dump_desc_one(npi_desc_handle, NULL, i); 701 #endif 702 703 tx_msg_p->tx_msg_size = clen; 704 i = TXDMA_DESC_NEXT_INDEX(i, 1, tx_ring_p->tx_wrap_mask); 705 if (ngathers > nxge_tx_max_gathers) { 706 good_packet = B_FALSE; 707 hcksum_retrieve(mp, NULL, NULL, &start_offset, 708 &stuff_offset, &end_offset, &value, 709 &cksum_flags); 710 711 NXGE_DEBUG_MSG((NULL, TX_CTL, 712 "==> nxge_start(14): pull msg - " 713 "len %d pkt_len %d ngathers %d", 714 len, pkt_len, ngathers)); 715 /* Pull all message blocks from b_cont */ 716 if (is_lso) { 717 mp = nmp_lso_save; 718 goto nxge_start_fail_lso; 719 } 720 if ((msgpullup(mp, -1)) == NULL) { 721 goto nxge_start_fail2; 722 } 723 goto nxge_start_fail2; 724 } 725 } /* while (nmp) */ 726 727 tx_msg_p->tx_message = mp; 728 tx_desc_p = &tx_desc_ring_vp[sop_index]; 729 #if defined(__i386) 730 npi_desc_handle.regp = (uint32_t)tx_desc_p; 731 #else 732 npi_desc_handle.regp = (uint64_t)tx_desc_p; 733 #endif 734 735 pkthdrp = (p_tx_pkt_hdr_all_t)hdrp; 736 pkthdrp->reserved = 0; 737 hdrp->value = 0; 738 739 (void) nxge_fill_tx_hdr(mp, B_FALSE, cksum_on, 740 (pkt_len - TX_PKT_HEADER_SIZE), npads, pkthdrp); 741 742 if (pkt_len > NXGE_MTU_DEFAULT_MAX) { 743 tdc_stats->tx_jumbo_pkts++; 744 } 745 746 min_len = (ETHERMIN + TX_PKT_HEADER_SIZE + (npads * 2)); 747 if (pkt_len < min_len) { 748 /* Assume we use bcopy to premapped buffers */ 749 kaddr = (caddr_t)DMA_COMMON_VPTR(tx_msg_p->buf_dma); 750 NXGE_DEBUG_MSG((NULL, TX_CTL, 751 "==> nxge_start(14-1): < (msg_min + 16)" 752 "len %d pkt_len %d min_len %d bzero %d ngathers %d", 753 len, pkt_len, min_len, (min_len - pkt_len), ngathers)); 754 bzero((kaddr + pkt_len), (min_len - pkt_len)); 755 pkt_len = tx_msg_p->tx_msg_size = min_len; 756 757 sop_tx_desc_p->bits.hdw.tr_len = min_len; 758 759 NXGE_MEM_PIO_WRITE64(npi_desc_handle, sop_tx_desc_p->value); 760 tx_desc_p->value = sop_tx_desc_p->value; 761 762 NXGE_DEBUG_MSG((NULL, TX_CTL, 763 "==> nxge_start(14-2): < msg_min - " 764 "len %d pkt_len %d min_len %d ngathers %d", 765 len, pkt_len, min_len, ngathers)); 766 } 767 768 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: cksum_flags 0x%x ", 769 cksum_flags)); 770 if (cksum_flags & HCK_PARTIALCKSUM) { 771 NXGE_DEBUG_MSG((nxgep, TX_CTL, 772 "==> nxge_start: cksum_flags 0x%x (partial checksum) ", 773 cksum_flags)); 774 cksum_on = B_TRUE; 775 NXGE_DEBUG_MSG((nxgep, TX_CTL, 776 "==> nxge_start: from IP cksum_flags 0x%x " 777 "(partial checksum) " 778 "start_offset %d stuff_offset %d", 779 cksum_flags, start_offset, stuff_offset)); 780 tmp_len = (uint64_t)(start_offset >> 1); 781 hdrp->value |= (tmp_len << TX_PKT_HEADER_L4START_SHIFT); 782 tmp_len = (uint64_t)(stuff_offset >> 1); 783 hdrp->value |= (tmp_len << TX_PKT_HEADER_L4STUFF_SHIFT); 784 785 NXGE_DEBUG_MSG((nxgep, TX_CTL, 786 "==> nxge_start: from IP cksum_flags 0x%x " 787 "(partial checksum) " 788 "after SHIFT start_offset %d stuff_offset %d", 789 cksum_flags, start_offset, stuff_offset)); 790 } 791 { 792 uint64_t tmp_len; 793 794 /* pkt_len already includes 16 + paddings!! */ 795 /* Update the control header length */ 796 tot_xfer_len = (pkt_len - TX_PKT_HEADER_SIZE); 797 tmp_len = hdrp->value | 798 (tot_xfer_len << TX_PKT_HEADER_TOT_XFER_LEN_SHIFT); 799 800 NXGE_DEBUG_MSG((nxgep, TX_CTL, 801 "==> nxge_start(15_x1): setting SOP " 802 "tot_xfer_len 0x%llx (%d) pkt_len %d tmp_len " 803 "0x%llx hdrp->value 0x%llx", 804 tot_xfer_len, tot_xfer_len, pkt_len, 805 tmp_len, hdrp->value)); 806 #if defined(_BIG_ENDIAN) 807 hdrp->value = ddi_swap64(tmp_len); 808 #else 809 hdrp->value = tmp_len; 810 #endif 811 NXGE_DEBUG_MSG((nxgep, 812 TX_CTL, "==> nxge_start(15_x2): setting SOP " 813 "after SWAP: tot_xfer_len 0x%llx pkt_len %d " 814 "tmp_len 0x%llx hdrp->value 0x%llx", 815 tot_xfer_len, pkt_len, 816 tmp_len, hdrp->value)); 817 } 818 819 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start(15): setting SOP " 820 "wr_index %d " 821 "tot_xfer_len (%d) pkt_len %d npads %d", 822 sop_index, 823 tot_xfer_len, pkt_len, 824 npads)); 825 826 sop_tx_desc_p->bits.hdw.sop = 1; 827 sop_tx_desc_p->bits.hdw.mark = mark_mode; 828 sop_tx_desc_p->bits.hdw.num_ptr = ngathers; 829 830 NXGE_MEM_PIO_WRITE64(npi_desc_handle, sop_tx_desc_p->value); 831 832 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start(16): set SOP done")); 833 834 #ifdef NXGE_DEBUG 835 npi_desc_handle.nxgep = nxgep; 836 npi_desc_handle.function.function = nxgep->function_num; 837 npi_desc_handle.function.instance = nxgep->instance; 838 839 NXGE_DEBUG_MSG((nxgep, TX_CTL, "\n\t: value 0x%llx\n" 840 "\t\tsad $%p\ttr_len %d len %d\tnptrs %d\tmark %d sop %d\n", 841 save_desc_p->value, 842 sad, 843 save_desc_p->bits.hdw.tr_len, 844 xfer_len, 845 save_desc_p->bits.hdw.num_ptr, 846 save_desc_p->bits.hdw.mark, 847 save_desc_p->bits.hdw.sop)); 848 (void) npi_txdma_dump_desc_one(npi_desc_handle, NULL, sop_index); 849 850 dump_len = (pkt_len > 128) ? 128: pkt_len; 851 NXGE_DEBUG_MSG((nxgep, TX_CTL, 852 "==> nxge_start: dump packets(17) (after sop set, len " 853 " (len/dump_len/pkt_len/tot_xfer_len) %d/%d/%d/%d):\n" 854 "ptr $%p: %s", len, dump_len, pkt_len, tot_xfer_len, 855 (char *)hdrp, 856 nxge_dump_packet((char *)hdrp, dump_len))); 857 NXGE_DEBUG_MSG((nxgep, TX_CTL, 858 "==> nxge_start(18): TX desc sync: sop_index %d", 859 sop_index)); 860 #endif 861 862 if ((ngathers == 1) || tx_ring_p->wr_index < i) { 863 (void) ddi_dma_sync(tx_desc_dma_handle, 864 sop_index * sizeof (tx_desc_t), 865 ngathers * sizeof (tx_desc_t), 866 DDI_DMA_SYNC_FORDEV); 867 868 NXGE_DEBUG_MSG((nxgep, TX_CTL, "nxge_start(19): sync 1 " 869 "cs_off = 0x%02X cs_s_off = 0x%02X " 870 "pkt_len %d ngathers %d sop_index %d\n", 871 stuff_offset, start_offset, 872 pkt_len, ngathers, sop_index)); 873 } else { /* more than one descriptor and wrap around */ 874 uint32_t nsdescs = tx_ring_p->tx_ring_size - sop_index; 875 (void) ddi_dma_sync(tx_desc_dma_handle, 876 sop_index * sizeof (tx_desc_t), 877 nsdescs * sizeof (tx_desc_t), 878 DDI_DMA_SYNC_FORDEV); 879 NXGE_DEBUG_MSG((nxgep, TX_CTL, "nxge_start(20): sync 1 " 880 "cs_off = 0x%02X cs_s_off = 0x%02X " 881 "pkt_len %d ngathers %d sop_index %d\n", 882 stuff_offset, start_offset, 883 pkt_len, ngathers, sop_index)); 884 885 (void) ddi_dma_sync(tx_desc_dma_handle, 886 0, 887 (ngathers - nsdescs) * sizeof (tx_desc_t), 888 DDI_DMA_SYNC_FORDEV); 889 NXGE_DEBUG_MSG((nxgep, TX_CTL, "nxge_start(21): sync 2 " 890 "cs_off = 0x%02X cs_s_off = 0x%02X " 891 "pkt_len %d ngathers %d sop_index %d\n", 892 stuff_offset, start_offset, 893 pkt_len, ngathers, sop_index)); 894 } 895 896 tail_index = tx_ring_p->wr_index; 897 tail_wrap = tx_ring_p->wr_index_wrap; 898 899 tx_ring_p->wr_index = i; 900 if (tx_ring_p->wr_index <= tail_index) { 901 tx_ring_p->wr_index_wrap = ((tail_wrap == B_TRUE) ? 902 B_FALSE : B_TRUE); 903 } 904 905 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: TX kick: " 906 "channel %d wr_index %d wrap %d ngathers %d desc_pend %d", 907 tx_ring_p->tdc, 908 tx_ring_p->wr_index, 909 tx_ring_p->wr_index_wrap, 910 ngathers, 911 tx_ring_p->descs_pending)); 912 913 if (is_lso) { 914 lso_ngathers += ngathers; 915 if (mp_chain != NULL) { 916 mp = mp_chain; 917 mp_chain = mp_chain->b_next; 918 mp->b_next = NULL; 919 if (nxge_lso_kick_cnt == lso_ngathers) { 920 tx_ring_p->descs_pending += lso_ngathers; 921 { 922 tx_ring_kick_t kick; 923 924 kick.value = 0; 925 kick.bits.ldw.wrap = 926 tx_ring_p->wr_index_wrap; 927 kick.bits.ldw.tail = 928 (uint16_t)tx_ring_p->wr_index; 929 930 /* Kick the Transmit kick register */ 931 TXDMA_REG_WRITE64( 932 NXGE_DEV_NPI_HANDLE(nxgep), 933 TX_RING_KICK_REG, 934 (uint8_t)tx_ring_p->tdc, 935 kick.value); 936 tdc_stats->tx_starts++; 937 938 NXGE_DEBUG_MSG((nxgep, TX_CTL, 939 "==> nxge_start: more LSO: " 940 "LSO_CNT %d", 941 lso_ngathers)); 942 } 943 lso_ngathers = 0; 944 ngathers = 0; 945 cur_index_lso = sop_index = tx_ring_p->wr_index; 946 lso_tail_wrap = tx_ring_p->wr_index_wrap; 947 } 948 NXGE_DEBUG_MSG((nxgep, TX_CTL, 949 "==> nxge_start: lso again: " 950 "lso_gathers %d ngathers %d cur_index_lso %d " 951 "wr_index %d sop_index %d", 952 lso_ngathers, ngathers, cur_index_lso, 953 tx_ring_p->wr_index, sop_index)); 954 955 NXGE_DEBUG_MSG((nxgep, TX_CTL, 956 "==> nxge_start: next : count %d", 957 lso_ngathers)); 958 lso_again = B_TRUE; 959 goto start_again; 960 } 961 ngathers = lso_ngathers; 962 } 963 964 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: TX KICKING: ")); 965 966 { 967 tx_ring_kick_t kick; 968 969 kick.value = 0; 970 kick.bits.ldw.wrap = tx_ring_p->wr_index_wrap; 971 kick.bits.ldw.tail = (uint16_t)tx_ring_p->wr_index; 972 973 /* Kick start the Transmit kick register */ 974 TXDMA_REG_WRITE64(NXGE_DEV_NPI_HANDLE(nxgep), 975 TX_RING_KICK_REG, 976 (uint8_t)tx_ring_p->tdc, 977 kick.value); 978 } 979 980 tx_ring_p->descs_pending += ngathers; 981 tdc_stats->tx_starts++; 982 983 tx_ring_p->tx_ring_state = TX_RING_STATE_IDLE; 984 985 MUTEX_EXIT(&tx_ring_p->lock); 986 987 NXGE_DEBUG_MSG((nxgep, TX_CTL, "<== nxge_start")); 988 989 return (status); 990 991 nxge_start_fail_lso: 992 status = 0; 993 good_packet = B_FALSE; 994 if (mp != NULL) { 995 freemsg(mp); 996 } 997 if (mp_chain != NULL) { 998 freemsg(mp_chain); 999 } 1000 if (!lso_again && !ngathers) { 1001 MUTEX_EXIT(&tx_ring_p->lock); 1002 NXGE_DEBUG_MSG((nxgep, TX_CTL, 1003 "==> nxge_start: lso exit (nothing changed)")); 1004 goto nxge_start_fail1; 1005 } 1006 1007 NXGE_DEBUG_MSG((nxgep, TX_CTL, 1008 "==> nxge_start (channel %d): before lso " 1009 "lso_gathers %d ngathers %d cur_index_lso %d " 1010 "wr_index %d sop_index %d lso_again %d", 1011 tx_ring_p->tdc, 1012 lso_ngathers, ngathers, cur_index_lso, 1013 tx_ring_p->wr_index, sop_index, lso_again)); 1014 1015 if (lso_again) { 1016 lso_ngathers += ngathers; 1017 ngathers = lso_ngathers; 1018 sop_index = cur_index_lso; 1019 tx_ring_p->wr_index = sop_index; 1020 tx_ring_p->wr_index_wrap = lso_tail_wrap; 1021 } 1022 1023 NXGE_DEBUG_MSG((nxgep, TX_CTL, 1024 "==> nxge_start (channel %d): after lso " 1025 "lso_gathers %d ngathers %d cur_index_lso %d " 1026 "wr_index %d sop_index %d lso_again %d", 1027 tx_ring_p->tdc, 1028 lso_ngathers, ngathers, cur_index_lso, 1029 tx_ring_p->wr_index, sop_index, lso_again)); 1030 1031 nxge_start_fail2: 1032 if (good_packet == B_FALSE) { 1033 cur_index = sop_index; 1034 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_start: clean up")); 1035 for (i = 0; i < ngathers; i++) { 1036 tx_desc_p = &tx_desc_ring_vp[cur_index]; 1037 #if defined(__i386) 1038 npi_handle.regp = (uint32_t)tx_desc_p; 1039 #else 1040 npi_handle.regp = (uint64_t)tx_desc_p; 1041 #endif 1042 tx_msg_p = &tx_msg_ring[cur_index]; 1043 (void) npi_txdma_desc_set_zero(npi_handle, 1); 1044 if (tx_msg_p->flags.dma_type == USE_DVMA) { 1045 NXGE_DEBUG_MSG((nxgep, TX_CTL, 1046 "tx_desc_p = %X index = %d", 1047 tx_desc_p, tx_ring_p->rd_index)); 1048 (void) dvma_unload(tx_msg_p->dvma_handle, 1049 0, -1); 1050 tx_msg_p->dvma_handle = NULL; 1051 if (tx_ring_p->dvma_wr_index == 1052 tx_ring_p->dvma_wrap_mask) 1053 tx_ring_p->dvma_wr_index = 0; 1054 else 1055 tx_ring_p->dvma_wr_index++; 1056 tx_ring_p->dvma_pending--; 1057 } else if (tx_msg_p->flags.dma_type == USE_DMA) { 1058 if (ddi_dma_unbind_handle( 1059 tx_msg_p->dma_handle)) { 1060 cmn_err(CE_WARN, "!nxge_start: " 1061 "ddi_dma_unbind_handle failed"); 1062 } 1063 } 1064 tx_msg_p->flags.dma_type = USE_NONE; 1065 cur_index = TXDMA_DESC_NEXT_INDEX(cur_index, 1, 1066 tx_ring_p->tx_wrap_mask); 1067 1068 } 1069 1070 nxgep->resched_needed = B_TRUE; 1071 } 1072 1073 tx_ring_p->tx_ring_state = TX_RING_STATE_IDLE; 1074 1075 MUTEX_EXIT(&tx_ring_p->lock); 1076 1077 nxge_start_fail1: 1078 /* Add FMA to check the access handle nxge_hregh */ 1079 1080 NXGE_DEBUG_MSG((nxgep, TX_CTL, "<== nxge_start")); 1081 1082 return (status); 1083 } 1084 1085 int 1086 nxge_serial_tx(mblk_t *mp, void *arg) 1087 { 1088 p_tx_ring_t tx_ring_p = (p_tx_ring_t)arg; 1089 p_nxge_t nxgep = tx_ring_p->nxgep; 1090 1091 return (nxge_start(nxgep, tx_ring_p, mp)); 1092 } 1093 1094 boolean_t 1095 nxge_send(p_nxge_t nxgep, mblk_t *mp, p_mac_tx_hint_t hp) 1096 { 1097 p_tx_ring_t *tx_rings; 1098 uint8_t ring_index; 1099 p_tx_ring_t tx_ring_p; 1100 nxge_grp_t *group; 1101 1102 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_send")); 1103 1104 ASSERT(mp->b_next == NULL); 1105 1106 group = nxgep->tx_set.group[0]; /* The default group */ 1107 ring_index = nxge_tx_lb_ring_1(mp, group->count, hp); 1108 1109 tx_rings = nxgep->tx_rings->rings; 1110 tx_ring_p = tx_rings[group->legend[ring_index]]; 1111 1112 MUTEX_ENTER(&tx_ring_p->lock); 1113 if (tx_ring_p->tx_ring_state == TX_RING_STATE_OFFLINE) { 1114 /* 1115 * OFFLINE means that it is in the process of being 1116 * shared - that is, it has been claimed by the HIO 1117 * code, but hasn't been unlinked from <group> yet. 1118 * So in this case use the first TDC, which always 1119 * belongs to the service domain and can't be shared. 1120 */ 1121 ring_index = 0; 1122 tx_ring_p = tx_rings[group->legend[ring_index]]; 1123 } else { 1124 /* 1125 * Otherwise, mark the TDC as BUSY: the HIO code 1126 * will wait until nxge_start() has completed. 1127 */ 1128 tx_ring_p->tx_ring_state = TX_RING_STATE_BUSY; 1129 } 1130 MUTEX_EXIT(&tx_ring_p->lock); 1131 1132 NXGE_DEBUG_MSG((nxgep, TX_CTL, "count %d, tx_rings[%d] = %p", 1133 (int)group->count, group->legend[ring_index], tx_ring_p)); 1134 1135 switch (nxge_tx_scheme) { 1136 case NXGE_USE_START: 1137 if (nxge_start(nxgep, tx_ring_p, mp)) { 1138 NXGE_DEBUG_MSG((nxgep, TX_CTL, "<== nxge_send: failed " 1139 "ring index %d", ring_index)); 1140 return (B_FALSE); 1141 } 1142 break; 1143 1144 case NXGE_USE_SERIAL: 1145 default: 1146 nxge_serialize_enter(tx_ring_p->serial, mp); 1147 break; 1148 } 1149 1150 NXGE_DEBUG_MSG((nxgep, TX_CTL, "<== nxge_send: ring index %d", 1151 ring_index)); 1152 1153 return (B_TRUE); 1154 } 1155 1156 /* 1157 * nxge_m_tx() - send a chain of packets 1158 */ 1159 mblk_t * 1160 nxge_m_tx(void *arg, mblk_t *mp) 1161 { 1162 p_nxge_t nxgep = (p_nxge_t)arg; 1163 mblk_t *next; 1164 mac_tx_hint_t hint; 1165 1166 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_m_tx")); 1167 1168 if ((!(nxgep->drv_state & STATE_HW_INITIALIZED)) || 1169 (nxgep->nxge_mac_state != NXGE_MAC_STARTED)) { 1170 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1171 "==> nxge_m_tx: hardware not initialized")); 1172 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1173 "<== nxge_m_tx")); 1174 freemsgchain(mp); 1175 mp = NULL; 1176 return (mp); 1177 } 1178 1179 hint.hash = NULL; 1180 hint.vid = 0; 1181 hint.sap = 0; 1182 1183 while (mp != NULL) { 1184 next = mp->b_next; 1185 mp->b_next = NULL; 1186 1187 /* 1188 * Until Nemo tx resource works, the mac driver 1189 * does the load balancing based on TCP port, 1190 * or CPU. For debugging, we use a system 1191 * configurable parameter. 1192 */ 1193 if (!nxge_send(nxgep, mp, &hint)) { 1194 mp->b_next = next; 1195 break; 1196 } 1197 1198 mp = next; 1199 1200 NXGE_DEBUG_MSG((NULL, TX_CTL, 1201 "==> nxge_m_tx: (go back to loop) mp $%p next $%p", 1202 mp, next)); 1203 } 1204 1205 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_m_tx")); 1206 return (mp); 1207 } 1208 1209 int 1210 nxge_tx_lb_ring_1(p_mblk_t mp, uint32_t maxtdcs, p_mac_tx_hint_t hp) 1211 { 1212 uint8_t ring_index = 0; 1213 uint8_t *tcp_port; 1214 p_mblk_t nmp; 1215 size_t mblk_len; 1216 size_t iph_len; 1217 size_t hdrs_size; 1218 uint8_t hdrs_buf[sizeof (struct ether_header) + 1219 IP_MAX_HDR_LENGTH + sizeof (uint32_t)]; 1220 /* 1221 * allocate space big enough to cover 1222 * the max ip header length and the first 1223 * 4 bytes of the TCP/IP header. 1224 */ 1225 1226 boolean_t qos = B_FALSE; 1227 1228 NXGE_DEBUG_MSG((NULL, TX_CTL, "==> nxge_tx_lb_ring")); 1229 1230 if (hp->vid) { 1231 qos = B_TRUE; 1232 } 1233 switch (nxge_tx_lb_policy) { 1234 case NXGE_TX_LB_TCPUDP: /* default IPv4 TCP/UDP */ 1235 default: 1236 tcp_port = mp->b_rptr; 1237 if (!nxge_no_tx_lb && !qos && 1238 (ntohs(((p_ether_header_t)tcp_port)->ether_type) 1239 == ETHERTYPE_IP)) { 1240 nmp = mp; 1241 mblk_len = MBLKL(nmp); 1242 tcp_port = NULL; 1243 if (mblk_len > sizeof (struct ether_header) + 1244 sizeof (uint8_t)) { 1245 tcp_port = nmp->b_rptr + 1246 sizeof (struct ether_header); 1247 mblk_len -= sizeof (struct ether_header); 1248 iph_len = ((*tcp_port) & 0x0f) << 2; 1249 if (mblk_len > (iph_len + sizeof (uint32_t))) { 1250 tcp_port = nmp->b_rptr; 1251 } else { 1252 tcp_port = NULL; 1253 } 1254 } 1255 if (tcp_port == NULL) { 1256 hdrs_size = 0; 1257 ((p_ether_header_t)hdrs_buf)->ether_type = 0; 1258 while ((nmp) && (hdrs_size < 1259 sizeof (hdrs_buf))) { 1260 mblk_len = MBLKL(nmp); 1261 if (mblk_len >= 1262 (sizeof (hdrs_buf) - hdrs_size)) 1263 mblk_len = sizeof (hdrs_buf) - 1264 hdrs_size; 1265 bcopy(nmp->b_rptr, 1266 &hdrs_buf[hdrs_size], mblk_len); 1267 hdrs_size += mblk_len; 1268 nmp = nmp->b_cont; 1269 } 1270 tcp_port = hdrs_buf; 1271 } 1272 tcp_port += sizeof (ether_header_t); 1273 if (!(tcp_port[6] & 0x3f) && !(tcp_port[7] & 0xff)) { 1274 switch (tcp_port[9]) { 1275 case IPPROTO_TCP: 1276 case IPPROTO_UDP: 1277 case IPPROTO_ESP: 1278 tcp_port += ((*tcp_port) & 0x0f) << 2; 1279 ring_index = 1280 ((tcp_port[0] ^ 1281 tcp_port[1] ^ 1282 tcp_port[2] ^ 1283 tcp_port[3]) % maxtdcs); 1284 break; 1285 1286 case IPPROTO_AH: 1287 /* SPI starts at the 4th byte */ 1288 tcp_port += ((*tcp_port) & 0x0f) << 2; 1289 ring_index = 1290 ((tcp_port[4] ^ 1291 tcp_port[5] ^ 1292 tcp_port[6] ^ 1293 tcp_port[7]) % maxtdcs); 1294 break; 1295 1296 default: 1297 ring_index = tcp_port[19] % maxtdcs; 1298 break; 1299 } 1300 } else { /* fragmented packet */ 1301 ring_index = tcp_port[19] % maxtdcs; 1302 } 1303 } else { 1304 ring_index = mp->b_band % maxtdcs; 1305 } 1306 break; 1307 1308 case NXGE_TX_LB_HASH: 1309 if (hp->hash) { 1310 #if defined(__i386) 1311 ring_index = ((uint32_t)(hp->hash) % maxtdcs); 1312 #else 1313 ring_index = ((uint64_t)(hp->hash) % maxtdcs); 1314 #endif 1315 } else { 1316 ring_index = mp->b_band % maxtdcs; 1317 } 1318 break; 1319 1320 case NXGE_TX_LB_DEST_MAC: /* Use destination MAC address */ 1321 tcp_port = mp->b_rptr; 1322 ring_index = tcp_port[5] % maxtdcs; 1323 break; 1324 } 1325 1326 NXGE_DEBUG_MSG((NULL, TX_CTL, "<== nxge_tx_lb_ring")); 1327 1328 return (ring_index); 1329 } 1330 1331 uint_t 1332 nxge_reschedule(caddr_t arg) 1333 { 1334 p_nxge_t nxgep; 1335 1336 nxgep = (p_nxge_t)arg; 1337 1338 NXGE_DEBUG_MSG((nxgep, TX_CTL, "==> nxge_reschedule")); 1339 1340 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED && 1341 nxgep->resched_needed) { 1342 if (!isLDOMguest(nxgep)) 1343 mac_tx_update(nxgep->mach); 1344 #if defined(sun4v) 1345 else { /* isLDOMguest(nxgep) */ 1346 nxge_hio_data_t *nhd = (nxge_hio_data_t *) 1347 nxgep->nxge_hw_p->hio; 1348 nx_vio_fp_t *vio = &nhd->hio.vio; 1349 1350 /* Call back vnet. */ 1351 if (vio->cb.vio_net_tx_update) { 1352 (*vio->cb.vio_net_tx_update) 1353 (nxgep->hio_vr->vhp); 1354 } 1355 } 1356 #endif 1357 nxgep->resched_needed = B_FALSE; 1358 nxgep->resched_running = B_FALSE; 1359 } 1360 1361 NXGE_DEBUG_MSG((NULL, TX_CTL, "<== nxge_reschedule")); 1362 return (DDI_INTR_CLAIMED); 1363 } 1364 1365 1366 /* Software LSO starts here */ 1367 static void 1368 nxge_hcksum_retrieve(mblk_t *mp, 1369 uint32_t *start, uint32_t *stuff, uint32_t *end, 1370 uint32_t *value, uint32_t *flags) 1371 { 1372 if (mp->b_datap->db_type == M_DATA) { 1373 if (flags != NULL) { 1374 *flags = DB_CKSUMFLAGS(mp) & (HCK_IPV4_HDRCKSUM | 1375 HCK_PARTIALCKSUM | HCK_FULLCKSUM | 1376 HCK_FULLCKSUM_OK); 1377 if ((*flags & (HCK_PARTIALCKSUM | 1378 HCK_FULLCKSUM)) != 0) { 1379 if (value != NULL) 1380 *value = (uint32_t)DB_CKSUM16(mp); 1381 if ((*flags & HCK_PARTIALCKSUM) != 0) { 1382 if (start != NULL) 1383 *start = 1384 (uint32_t)DB_CKSUMSTART(mp); 1385 if (stuff != NULL) 1386 *stuff = 1387 (uint32_t)DB_CKSUMSTUFF(mp); 1388 if (end != NULL) 1389 *end = 1390 (uint32_t)DB_CKSUMEND(mp); 1391 } 1392 } 1393 } 1394 } 1395 } 1396 1397 static void 1398 nxge_lso_info_get(mblk_t *mp, uint32_t *mss, uint32_t *flags) 1399 { 1400 ASSERT(DB_TYPE(mp) == M_DATA); 1401 1402 *mss = 0; 1403 if (flags != NULL) { 1404 *flags = DB_CKSUMFLAGS(mp) & HW_LSO; 1405 if ((*flags != 0) && (mss != NULL)) { 1406 *mss = (uint32_t)DB_LSOMSS(mp); 1407 } 1408 NXGE_DEBUG_MSG((NULL, TX_CTL, 1409 "==> nxge_lso_info_get(flag !=NULL): mss %d *flags 0x%x", 1410 *mss, *flags)); 1411 } 1412 1413 NXGE_DEBUG_MSG((NULL, TX_CTL, 1414 "<== nxge_lso_info_get: mss %d", *mss)); 1415 } 1416 1417 /* 1418 * Do Soft LSO on the oversized packet. 1419 * 1420 * 1. Create a chain of message for headers. 1421 * 2. Fill up header messages with proper information. 1422 * 3. Copy Eithernet, IP, and TCP headers from the original message to 1423 * each new message with necessary adjustments. 1424 * * Unchange the ethernet header for DIX frames. (by default) 1425 * * IP Total Length field is updated to MSS or less(only for the last one). 1426 * * IP Identification value is incremented by one for each packet. 1427 * * TCP sequence Number is recalculated according to the payload length. 1428 * * Set FIN and/or PSH flags for the *last* packet if applied. 1429 * * TCP partial Checksum 1430 * 4. Update LSO information in the first message header. 1431 * 5. Release the original message header. 1432 */ 1433 static mblk_t * 1434 nxge_do_softlso(mblk_t *mp, uint32_t mss) 1435 { 1436 uint32_t hckflags; 1437 int pktlen; 1438 int hdrlen; 1439 int segnum; 1440 int i; 1441 struct ether_vlan_header *evh; 1442 int ehlen, iphlen, tcphlen; 1443 struct ip *oiph, *niph; 1444 struct tcphdr *otcph, *ntcph; 1445 int available, len, left; 1446 uint16_t ip_id; 1447 uint32_t tcp_seq; 1448 #ifdef __sparc 1449 uint32_t tcp_seq_tmp; 1450 #endif 1451 mblk_t *datamp; 1452 uchar_t *rptr; 1453 mblk_t *nmp; 1454 mblk_t *cmp; 1455 mblk_t *mp_chain; 1456 boolean_t do_cleanup = B_FALSE; 1457 t_uscalar_t start_offset = 0; 1458 t_uscalar_t stuff_offset = 0; 1459 t_uscalar_t value = 0; 1460 uint16_t l4_len; 1461 ipaddr_t src, dst; 1462 uint32_t cksum, sum, l4cksum; 1463 1464 NXGE_DEBUG_MSG((NULL, TX_CTL, 1465 "==> nxge_do_softlso")); 1466 /* 1467 * check the length of LSO packet payload and calculate the number of 1468 * segments to be generated. 1469 */ 1470 pktlen = msgsize(mp); 1471 evh = (struct ether_vlan_header *)mp->b_rptr; 1472 1473 /* VLAN? */ 1474 if (evh->ether_tpid == htons(ETHERTYPE_VLAN)) 1475 ehlen = sizeof (struct ether_vlan_header); 1476 else 1477 ehlen = sizeof (struct ether_header); 1478 oiph = (struct ip *)(mp->b_rptr + ehlen); 1479 iphlen = oiph->ip_hl * 4; 1480 otcph = (struct tcphdr *)(mp->b_rptr + ehlen + iphlen); 1481 tcphlen = otcph->th_off * 4; 1482 1483 l4_len = pktlen - ehlen - iphlen; 1484 1485 NXGE_DEBUG_MSG((NULL, TX_CTL, 1486 "==> nxge_do_softlso: mss %d oiph $%p " 1487 "original ip_sum oiph->ip_sum 0x%x " 1488 "original tcp_sum otcph->th_sum 0x%x " 1489 "oiph->ip_len %d pktlen %d ehlen %d " 1490 "l4_len %d (0x%x) ip_len - iphlen %d ", 1491 mss, 1492 oiph, 1493 oiph->ip_sum, 1494 otcph->th_sum, 1495 ntohs(oiph->ip_len), pktlen, 1496 ehlen, 1497 l4_len, 1498 l4_len, 1499 ntohs(oiph->ip_len) - iphlen)); 1500 1501 /* IPv4 + TCP */ 1502 if (!(oiph->ip_v == IPV4_VERSION)) { 1503 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 1504 "<== nxge_do_softlso: not IPV4 " 1505 "oiph->ip_len %d pktlen %d ehlen %d tcphlen %d", 1506 ntohs(oiph->ip_len), pktlen, ehlen, 1507 tcphlen)); 1508 freemsg(mp); 1509 return (NULL); 1510 } 1511 1512 if (!(oiph->ip_p == IPPROTO_TCP)) { 1513 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 1514 "<== nxge_do_softlso: not TCP " 1515 "oiph->ip_len %d pktlen %d ehlen %d tcphlen %d", 1516 ntohs(oiph->ip_len), pktlen, ehlen, 1517 tcphlen)); 1518 freemsg(mp); 1519 return (NULL); 1520 } 1521 1522 if (!(ntohs(oiph->ip_len) == pktlen - ehlen)) { 1523 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 1524 "<== nxge_do_softlso: len not matched " 1525 "oiph->ip_len %d pktlen %d ehlen %d tcphlen %d", 1526 ntohs(oiph->ip_len), pktlen, ehlen, 1527 tcphlen)); 1528 freemsg(mp); 1529 return (NULL); 1530 } 1531 1532 otcph = (struct tcphdr *)(mp->b_rptr + ehlen + iphlen); 1533 tcphlen = otcph->th_off * 4; 1534 1535 /* TCP flags can not include URG, RST, or SYN */ 1536 VERIFY((otcph->th_flags & (TH_SYN | TH_RST | TH_URG)) == 0); 1537 1538 hdrlen = ehlen + iphlen + tcphlen; 1539 1540 VERIFY(MBLKL(mp) >= hdrlen); 1541 1542 if (MBLKL(mp) > hdrlen) { 1543 datamp = mp; 1544 rptr = mp->b_rptr + hdrlen; 1545 } else { /* = */ 1546 datamp = mp->b_cont; 1547 rptr = datamp->b_rptr; 1548 } 1549 1550 NXGE_DEBUG_MSG((NULL, TX_CTL, 1551 "nxge_do_softlso: otcph $%p pktlen: %d, " 1552 "hdrlen %d ehlen %d iphlen %d tcphlen %d " 1553 "mblkl(mp): %d, mblkl(datamp): %d", 1554 otcph, 1555 pktlen, hdrlen, ehlen, iphlen, tcphlen, 1556 (int)MBLKL(mp), (int)MBLKL(datamp))); 1557 1558 hckflags = 0; 1559 nxge_hcksum_retrieve(mp, 1560 &start_offset, &stuff_offset, &value, NULL, &hckflags); 1561 1562 dst = oiph->ip_dst.s_addr; 1563 src = oiph->ip_src.s_addr; 1564 1565 cksum = (dst >> 16) + (dst & 0xFFFF) + 1566 (src >> 16) + (src & 0xFFFF); 1567 l4cksum = cksum + IP_TCP_CSUM_COMP; 1568 1569 sum = l4_len + l4cksum; 1570 sum = (sum & 0xFFFF) + (sum >> 16); 1571 1572 NXGE_DEBUG_MSG((NULL, TX_CTL, 1573 "==> nxge_do_softlso: dst 0x%x src 0x%x sum 0x%x ~new 0x%x " 1574 "hckflags 0x%x start_offset %d stuff_offset %d " 1575 "value (original) 0x%x th_sum 0x%x " 1576 "pktlen %d l4_len %d (0x%x) " 1577 "MBLKL(mp): %d, MBLKL(datamp): %d dump header %s", 1578 dst, src, 1579 (sum & 0xffff), (~sum & 0xffff), 1580 hckflags, start_offset, stuff_offset, 1581 value, otcph->th_sum, 1582 pktlen, 1583 l4_len, 1584 l4_len, 1585 ntohs(oiph->ip_len) - (int)MBLKL(mp), 1586 (int)MBLKL(datamp), 1587 nxge_dump_packet((char *)evh, 12))); 1588 1589 /* 1590 * Start to process. 1591 */ 1592 available = pktlen - hdrlen; 1593 segnum = (available - 1) / mss + 1; 1594 1595 NXGE_DEBUG_MSG((NULL, TX_CTL, 1596 "==> nxge_do_softlso: pktlen %d " 1597 "MBLKL(mp): %d, MBLKL(datamp): %d " 1598 "available %d mss %d segnum %d", 1599 pktlen, (int)MBLKL(mp), (int)MBLKL(datamp), 1600 available, 1601 mss, 1602 segnum)); 1603 1604 VERIFY(segnum >= 2); 1605 1606 /* 1607 * Try to pre-allocate all header messages 1608 */ 1609 mp_chain = NULL; 1610 for (i = 0; i < segnum; i++) { 1611 if ((nmp = allocb(hdrlen, 0)) == NULL) { 1612 /* Clean up the mp_chain */ 1613 while (mp_chain != NULL) { 1614 nmp = mp_chain; 1615 mp_chain = mp_chain->b_next; 1616 freemsg(nmp); 1617 } 1618 NXGE_DEBUG_MSG((NULL, TX_CTL, 1619 "<== nxge_do_softlso: " 1620 "Could not allocate enough messages for headers!")); 1621 freemsg(mp); 1622 return (NULL); 1623 } 1624 nmp->b_next = mp_chain; 1625 mp_chain = nmp; 1626 1627 NXGE_DEBUG_MSG((NULL, TX_CTL, 1628 "==> nxge_do_softlso: " 1629 "mp $%p nmp $%p mp_chain $%p mp_chain->b_next $%p", 1630 mp, nmp, mp_chain, mp_chain->b_next)); 1631 } 1632 1633 NXGE_DEBUG_MSG((NULL, TX_CTL, 1634 "==> nxge_do_softlso: mp $%p nmp $%p mp_chain $%p", 1635 mp, nmp, mp_chain)); 1636 1637 /* 1638 * Associate payload with new packets 1639 */ 1640 cmp = mp_chain; 1641 left = available; 1642 while (cmp != NULL) { 1643 nmp = dupb(datamp); 1644 if (nmp == NULL) { 1645 do_cleanup = B_TRUE; 1646 NXGE_DEBUG_MSG((NULL, TX_CTL, 1647 "==>nxge_do_softlso: " 1648 "Can not dupb(datamp), have to do clean up")); 1649 goto cleanup_allocated_msgs; 1650 } 1651 1652 NXGE_DEBUG_MSG((NULL, TX_CTL, 1653 "==> nxge_do_softlso: (loop) before mp $%p cmp $%p " 1654 "dupb nmp $%p len %d left %d msd %d ", 1655 mp, cmp, nmp, len, left, mss)); 1656 1657 cmp->b_cont = nmp; 1658 nmp->b_rptr = rptr; 1659 len = (left < mss) ? left : mss; 1660 left -= len; 1661 1662 NXGE_DEBUG_MSG((NULL, TX_CTL, 1663 "==> nxge_do_softlso: (loop) after mp $%p cmp $%p " 1664 "dupb nmp $%p len %d left %d mss %d ", 1665 mp, cmp, nmp, len, left, mss)); 1666 NXGE_DEBUG_MSG((NULL, TX_CTL, 1667 "nxge_do_softlso: before available: %d, " 1668 "left: %d, len: %d, segnum: %d MBLK(nmp): %d", 1669 available, left, len, segnum, (int)MBLKL(nmp))); 1670 1671 len -= MBLKL(nmp); 1672 NXGE_DEBUG_MSG((NULL, TX_CTL, 1673 "nxge_do_softlso: after available: %d, " 1674 "left: %d, len: %d, segnum: %d MBLK(nmp): %d", 1675 available, left, len, segnum, (int)MBLKL(nmp))); 1676 1677 while (len > 0) { 1678 mblk_t *mmp = NULL; 1679 1680 NXGE_DEBUG_MSG((NULL, TX_CTL, 1681 "nxge_do_softlso: (4) len > 0 available: %d, " 1682 "left: %d, len: %d, segnum: %d MBLK(nmp): %d", 1683 available, left, len, segnum, (int)MBLKL(nmp))); 1684 1685 if (datamp->b_cont != NULL) { 1686 datamp = datamp->b_cont; 1687 rptr = datamp->b_rptr; 1688 mmp = dupb(datamp); 1689 if (mmp == NULL) { 1690 do_cleanup = B_TRUE; 1691 NXGE_DEBUG_MSG((NULL, TX_CTL, 1692 "==> nxge_do_softlso: " 1693 "Can not dupb(datamp) (1), :" 1694 "have to do clean up")); 1695 NXGE_DEBUG_MSG((NULL, TX_CTL, 1696 "==> nxge_do_softlso: " 1697 "available: %d, left: %d, " 1698 "len: %d, MBLKL(nmp): %d", 1699 available, left, len, 1700 (int)MBLKL(nmp))); 1701 goto cleanup_allocated_msgs; 1702 } 1703 } else { 1704 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 1705 "==> nxge_do_softlso: " 1706 "(1)available: %d, left: %d, " 1707 "len: %d, MBLKL(nmp): %d", 1708 available, left, len, 1709 (int)MBLKL(nmp))); 1710 cmn_err(CE_PANIC, 1711 "==> nxge_do_softlso: " 1712 "Pointers must have been corrupted!\n" 1713 "datamp: $%p, nmp: $%p, rptr: $%p", 1714 (void *)datamp, 1715 (void *)nmp, 1716 (void *)rptr); 1717 } 1718 nmp->b_cont = mmp; 1719 nmp = mmp; 1720 len -= MBLKL(nmp); 1721 } 1722 if (len < 0) { 1723 nmp->b_wptr += len; 1724 rptr = nmp->b_wptr; 1725 NXGE_DEBUG_MSG((NULL, TX_CTL, 1726 "(5) len < 0 (less than 0)" 1727 "available: %d, left: %d, len: %d, MBLKL(nmp): %d", 1728 available, left, len, (int)MBLKL(nmp))); 1729 1730 } else if (len == 0) { 1731 if (datamp->b_cont != NULL) { 1732 NXGE_DEBUG_MSG((NULL, TX_CTL, 1733 "(5) len == 0" 1734 "available: %d, left: %d, len: %d, " 1735 "MBLKL(nmp): %d", 1736 available, left, len, (int)MBLKL(nmp))); 1737 datamp = datamp->b_cont; 1738 rptr = datamp->b_rptr; 1739 } else { 1740 NXGE_DEBUG_MSG((NULL, TX_CTL, 1741 "(6)available b_cont == NULL : %d, " 1742 "left: %d, len: %d, MBLKL(nmp): %d", 1743 available, left, len, (int)MBLKL(nmp))); 1744 1745 VERIFY(cmp->b_next == NULL); 1746 VERIFY(left == 0); 1747 break; /* Done! */ 1748 } 1749 } 1750 cmp = cmp->b_next; 1751 1752 NXGE_DEBUG_MSG((NULL, TX_CTL, 1753 "(7) do_softlso: " 1754 "next mp in mp_chain available len != 0 : %d, " 1755 "left: %d, len: %d, MBLKL(nmp): %d", 1756 available, left, len, (int)MBLKL(nmp))); 1757 } 1758 1759 /* 1760 * From now, start to fill up all headers for the first message 1761 * Hardware checksum flags need to be updated separately for FULLCKSUM 1762 * and PARTIALCKSUM cases. For full checksum, copy the original flags 1763 * into every new packet is enough. But for HCK_PARTIALCKSUM, all 1764 * required fields need to be updated properly. 1765 */ 1766 nmp = mp_chain; 1767 bcopy(mp->b_rptr, nmp->b_rptr, hdrlen); 1768 nmp->b_wptr = nmp->b_rptr + hdrlen; 1769 niph = (struct ip *)(nmp->b_rptr + ehlen); 1770 niph->ip_len = htons(mss + iphlen + tcphlen); 1771 ip_id = ntohs(niph->ip_id); 1772 ntcph = (struct tcphdr *)(nmp->b_rptr + ehlen + iphlen); 1773 #ifdef __sparc 1774 bcopy((char *)&ntcph->th_seq, &tcp_seq_tmp, 4); 1775 tcp_seq = ntohl(tcp_seq_tmp); 1776 #else 1777 tcp_seq = ntohl(ntcph->th_seq); 1778 #endif 1779 1780 ntcph->th_flags &= ~(TH_FIN | TH_PUSH | TH_RST); 1781 1782 DB_CKSUMFLAGS(nmp) = (uint16_t)hckflags; 1783 DB_CKSUMSTART(nmp) = start_offset; 1784 DB_CKSUMSTUFF(nmp) = stuff_offset; 1785 1786 /* calculate IP checksum and TCP pseudo header checksum */ 1787 niph->ip_sum = 0; 1788 niph->ip_sum = (uint16_t)nxge_csgen((uint16_t *)niph, iphlen); 1789 1790 l4_len = mss + tcphlen; 1791 sum = htons(l4_len) + l4cksum; 1792 sum = (sum & 0xFFFF) + (sum >> 16); 1793 ntcph->th_sum = (sum & 0xffff); 1794 1795 NXGE_DEBUG_MSG((NULL, TX_CTL, 1796 "==> nxge_do_softlso: first mp $%p (mp_chain $%p) " 1797 "mss %d pktlen %d l4_len %d (0x%x) " 1798 "MBLKL(mp): %d, MBLKL(datamp): %d " 1799 "ip_sum 0x%x " 1800 "th_sum 0x%x sum 0x%x ) " 1801 "dump first ip->tcp %s", 1802 nmp, mp_chain, 1803 mss, 1804 pktlen, 1805 l4_len, 1806 l4_len, 1807 (int)MBLKL(mp), (int)MBLKL(datamp), 1808 niph->ip_sum, 1809 ntcph->th_sum, 1810 sum, 1811 nxge_dump_packet((char *)niph, 52))); 1812 1813 cmp = nmp; 1814 while ((nmp = nmp->b_next)->b_next != NULL) { 1815 NXGE_DEBUG_MSG((NULL, TX_CTL, 1816 "==>nxge_do_softlso: middle l4_len %d ", l4_len)); 1817 bcopy(cmp->b_rptr, nmp->b_rptr, hdrlen); 1818 nmp->b_wptr = nmp->b_rptr + hdrlen; 1819 niph = (struct ip *)(nmp->b_rptr + ehlen); 1820 niph->ip_id = htons(++ip_id); 1821 niph->ip_len = htons(mss + iphlen + tcphlen); 1822 ntcph = (struct tcphdr *)(nmp->b_rptr + ehlen + iphlen); 1823 tcp_seq += mss; 1824 1825 ntcph->th_flags &= ~(TH_FIN | TH_PUSH | TH_RST | TH_URG); 1826 1827 #ifdef __sparc 1828 tcp_seq_tmp = htonl(tcp_seq); 1829 bcopy(&tcp_seq_tmp, (char *)&ntcph->th_seq, 4); 1830 #else 1831 ntcph->th_seq = htonl(tcp_seq); 1832 #endif 1833 DB_CKSUMFLAGS(nmp) = (uint16_t)hckflags; 1834 DB_CKSUMSTART(nmp) = start_offset; 1835 DB_CKSUMSTUFF(nmp) = stuff_offset; 1836 1837 /* calculate IP checksum and TCP pseudo header checksum */ 1838 niph->ip_sum = 0; 1839 niph->ip_sum = (uint16_t)nxge_csgen((uint16_t *)niph, iphlen); 1840 ntcph->th_sum = (sum & 0xffff); 1841 1842 NXGE_DEBUG_MSG((NULL, TX_CTL, 1843 "==> nxge_do_softlso: middle ip_sum 0x%x " 1844 "th_sum 0x%x " 1845 " mp $%p (mp_chain $%p) pktlen %d " 1846 "MBLKL(mp): %d, MBLKL(datamp): %d ", 1847 niph->ip_sum, 1848 ntcph->th_sum, 1849 nmp, mp_chain, 1850 pktlen, (int)MBLKL(mp), (int)MBLKL(datamp))); 1851 } 1852 1853 /* Last segment */ 1854 /* 1855 * Set FIN and/or PSH flags if present only in the last packet. 1856 * The ip_len could be different from prior packets. 1857 */ 1858 bcopy(cmp->b_rptr, nmp->b_rptr, hdrlen); 1859 nmp->b_wptr = nmp->b_rptr + hdrlen; 1860 niph = (struct ip *)(nmp->b_rptr + ehlen); 1861 niph->ip_id = htons(++ip_id); 1862 niph->ip_len = htons(msgsize(nmp->b_cont) + iphlen + tcphlen); 1863 ntcph = (struct tcphdr *)(nmp->b_rptr + ehlen + iphlen); 1864 tcp_seq += mss; 1865 #ifdef __sparc 1866 tcp_seq_tmp = htonl(tcp_seq); 1867 bcopy(&tcp_seq_tmp, (char *)&ntcph->th_seq, 4); 1868 #else 1869 ntcph->th_seq = htonl(tcp_seq); 1870 #endif 1871 ntcph->th_flags = (otcph->th_flags & ~TH_URG); 1872 1873 DB_CKSUMFLAGS(nmp) = (uint16_t)hckflags; 1874 DB_CKSUMSTART(nmp) = start_offset; 1875 DB_CKSUMSTUFF(nmp) = stuff_offset; 1876 1877 /* calculate IP checksum and TCP pseudo header checksum */ 1878 niph->ip_sum = 0; 1879 niph->ip_sum = (uint16_t)nxge_csgen((uint16_t *)niph, iphlen); 1880 1881 l4_len = ntohs(niph->ip_len) - iphlen; 1882 sum = htons(l4_len) + l4cksum; 1883 sum = (sum & 0xFFFF) + (sum >> 16); 1884 ntcph->th_sum = (sum & 0xffff); 1885 1886 NXGE_DEBUG_MSG((NULL, TX_CTL, 1887 "==> nxge_do_softlso: last next " 1888 "niph->ip_sum 0x%x " 1889 "ntcph->th_sum 0x%x sum 0x%x " 1890 "dump last ip->tcp %s " 1891 "cmp $%p mp $%p (mp_chain $%p) pktlen %d (0x%x) " 1892 "l4_len %d (0x%x) " 1893 "MBLKL(mp): %d, MBLKL(datamp): %d ", 1894 niph->ip_sum, 1895 ntcph->th_sum, sum, 1896 nxge_dump_packet((char *)niph, 52), 1897 cmp, nmp, mp_chain, 1898 pktlen, pktlen, 1899 l4_len, 1900 l4_len, 1901 (int)MBLKL(mp), (int)MBLKL(datamp))); 1902 1903 cleanup_allocated_msgs: 1904 if (do_cleanup) { 1905 NXGE_DEBUG_MSG((NULL, TX_CTL, 1906 "==> nxge_do_softlso: " 1907 "Failed allocating messages, " 1908 "have to clean up and fail!")); 1909 while (mp_chain != NULL) { 1910 nmp = mp_chain; 1911 mp_chain = mp_chain->b_next; 1912 freemsg(nmp); 1913 } 1914 } 1915 /* 1916 * We're done here, so just free the original message and return the 1917 * new message chain, that could be NULL if failed, back to the caller. 1918 */ 1919 freemsg(mp); 1920 1921 NXGE_DEBUG_MSG((NULL, TX_CTL, 1922 "<== nxge_do_softlso:mp_chain $%p", mp_chain)); 1923 return (mp_chain); 1924 } 1925 1926 /* 1927 * Will be called before NIC driver do further operation on the message. 1928 * The input message may include LSO information, if so, go to softlso logic 1929 * to eliminate the oversized LSO packet for the incapable underlying h/w. 1930 * The return could be the same non-LSO message or a message chain for LSO case. 1931 * 1932 * The driver needs to call this function per packet and process the whole chain 1933 * if applied. 1934 */ 1935 static mblk_t * 1936 nxge_lso_eliminate(mblk_t *mp) 1937 { 1938 uint32_t lsoflags; 1939 uint32_t mss; 1940 1941 NXGE_DEBUG_MSG((NULL, TX_CTL, 1942 "==>nxge_lso_eliminate:")); 1943 nxge_lso_info_get(mp, &mss, &lsoflags); 1944 1945 if (lsoflags & HW_LSO) { 1946 mblk_t *nmp; 1947 1948 NXGE_DEBUG_MSG((NULL, TX_CTL, 1949 "==>nxge_lso_eliminate:" 1950 "HW_LSO:mss %d mp $%p", 1951 mss, mp)); 1952 if ((nmp = nxge_do_softlso(mp, mss)) != NULL) { 1953 NXGE_DEBUG_MSG((NULL, TX_CTL, 1954 "<== nxge_lso_eliminate: " 1955 "LSO: nmp not NULL nmp $%p mss %d mp $%p", 1956 nmp, mss, mp)); 1957 return (nmp); 1958 } else { 1959 NXGE_DEBUG_MSG((NULL, TX_CTL, 1960 "<== nxge_lso_eliminate_ " 1961 "LSO: failed nmp NULL nmp $%p mss %d mp $%p", 1962 nmp, mss, mp)); 1963 return (NULL); 1964 } 1965 } 1966 1967 NXGE_DEBUG_MSG((NULL, TX_CTL, 1968 "<== nxge_lso_eliminate")); 1969 return (mp); 1970 } 1971 1972 static uint32_t 1973 nxge_csgen(uint16_t *adr, int len) 1974 { 1975 int i, odd; 1976 uint32_t sum = 0; 1977 uint32_t c = 0; 1978 1979 odd = len % 2; 1980 for (i = 0; i < (len / 2); i++) { 1981 sum += (adr[i] & 0xffff); 1982 } 1983 if (odd) { 1984 sum += adr[len / 2] & 0xff00; 1985 } 1986 while ((c = ((sum & 0xffff0000) >> 16)) != 0) { 1987 sum &= 0xffff; 1988 sum += c; 1989 } 1990 return (~sum & 0xffff); 1991 } 1992