1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <sys/nxge/nxge_rxdma.h> 30 31 #define NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp) \ 32 (rdcgrp + nxgep->pt_config.hw_config.start_rdc_grpid) 33 #define NXGE_ACTUAL_RDC(nxgep, rdc) \ 34 (rdc + nxgep->pt_config.hw_config.start_rdc) 35 36 /* 37 * Globals: tunable parameters (/etc/system or adb) 38 * 39 */ 40 extern uint32_t nxge_rbr_size; 41 extern uint32_t nxge_rcr_size; 42 extern uint32_t nxge_rbr_spare_size; 43 44 extern uint32_t nxge_mblks_pending; 45 46 /* 47 * Tunable to reduce the amount of time spent in the 48 * ISR doing Rx Processing. 49 */ 50 extern uint32_t nxge_max_rx_pkts; 51 boolean_t nxge_jumbo_enable; 52 53 /* 54 * Tunables to manage the receive buffer blocks. 55 * 56 * nxge_rx_threshold_hi: copy all buffers. 57 * nxge_rx_bcopy_size_type: receive buffer block size type. 58 * nxge_rx_threshold_lo: copy only up to tunable block size type. 59 */ 60 extern nxge_rxbuf_threshold_t nxge_rx_threshold_hi; 61 extern nxge_rxbuf_type_t nxge_rx_buf_size_type; 62 extern nxge_rxbuf_threshold_t nxge_rx_threshold_lo; 63 64 static nxge_status_t nxge_map_rxdma(p_nxge_t); 65 static void nxge_unmap_rxdma(p_nxge_t); 66 67 static nxge_status_t nxge_rxdma_hw_start_common(p_nxge_t); 68 static void nxge_rxdma_hw_stop_common(p_nxge_t); 69 70 static nxge_status_t nxge_rxdma_hw_start(p_nxge_t); 71 static void nxge_rxdma_hw_stop(p_nxge_t); 72 73 static nxge_status_t nxge_map_rxdma_channel(p_nxge_t, uint16_t, 74 p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 75 uint32_t, 76 p_nxge_dma_common_t *, p_rx_rcr_ring_t *, 77 p_rx_mbox_t *); 78 static void nxge_unmap_rxdma_channel(p_nxge_t, uint16_t, 79 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 80 81 static nxge_status_t nxge_map_rxdma_channel_cfg_ring(p_nxge_t, 82 uint16_t, 83 p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 84 p_rx_rcr_ring_t *, p_rx_mbox_t *); 85 static void nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t, 86 p_rx_rcr_ring_t, p_rx_mbox_t); 87 88 static nxge_status_t nxge_map_rxdma_channel_buf_ring(p_nxge_t, 89 uint16_t, 90 p_nxge_dma_common_t *, 91 p_rx_rbr_ring_t *, uint32_t); 92 static void nxge_unmap_rxdma_channel_buf_ring(p_nxge_t, 93 p_rx_rbr_ring_t); 94 95 static nxge_status_t nxge_rxdma_start_channel(p_nxge_t, uint16_t, 96 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 97 static nxge_status_t nxge_rxdma_stop_channel(p_nxge_t, uint16_t); 98 99 mblk_t * 100 nxge_rx_pkts(p_nxge_t, uint_t, p_nxge_ldv_t, 101 p_rx_rcr_ring_t *, rx_dma_ctl_stat_t); 102 103 static void nxge_receive_packet(p_nxge_t, 104 p_rx_rcr_ring_t, 105 p_rcr_entry_t, 106 boolean_t *, 107 mblk_t **, mblk_t **); 108 109 nxge_status_t nxge_disable_rxdma_channel(p_nxge_t, uint16_t); 110 111 static p_rx_msg_t nxge_allocb(size_t, uint32_t, p_nxge_dma_common_t); 112 static void nxge_freeb(p_rx_msg_t); 113 static void nxge_rx_pkts_vring(p_nxge_t, uint_t, 114 p_nxge_ldv_t, rx_dma_ctl_stat_t); 115 static nxge_status_t nxge_rx_err_evnts(p_nxge_t, uint_t, 116 p_nxge_ldv_t, rx_dma_ctl_stat_t); 117 118 static nxge_status_t nxge_rxdma_handle_port_errors(p_nxge_t, 119 uint32_t, uint32_t); 120 121 static nxge_status_t nxge_rxbuf_index_info_init(p_nxge_t, 122 p_rx_rbr_ring_t); 123 124 125 static nxge_status_t 126 nxge_rxdma_fatal_err_recover(p_nxge_t, uint16_t); 127 128 nxge_status_t 129 nxge_rx_port_fatal_err_recover(p_nxge_t); 130 131 static uint16_t 132 nxge_get_pktbuf_size(p_nxge_t nxgep, int bufsz_type, rbr_cfig_b_t rbr_cfgb); 133 134 nxge_status_t 135 nxge_init_rxdma_channels(p_nxge_t nxgep) 136 { 137 nxge_status_t status = NXGE_OK; 138 139 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_init_rxdma_channels")); 140 141 status = nxge_map_rxdma(nxgep); 142 if (status != NXGE_OK) { 143 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 144 "<== nxge_init_rxdma: status 0x%x", status)); 145 return (status); 146 } 147 148 status = nxge_rxdma_hw_start_common(nxgep); 149 if (status != NXGE_OK) { 150 nxge_unmap_rxdma(nxgep); 151 } 152 153 status = nxge_rxdma_hw_start(nxgep); 154 if (status != NXGE_OK) { 155 nxge_unmap_rxdma(nxgep); 156 } 157 158 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 159 "<== nxge_init_rxdma_channels: status 0x%x", status)); 160 161 return (status); 162 } 163 164 void 165 nxge_uninit_rxdma_channels(p_nxge_t nxgep) 166 { 167 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channels")); 168 169 nxge_rxdma_hw_stop(nxgep); 170 nxge_rxdma_hw_stop_common(nxgep); 171 nxge_unmap_rxdma(nxgep); 172 173 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 174 "<== nxge_uinit_rxdma_channels")); 175 } 176 177 nxge_status_t 178 nxge_reset_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 179 { 180 npi_handle_t handle; 181 npi_status_t rs = NPI_SUCCESS; 182 nxge_status_t status = NXGE_OK; 183 184 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_reset_rxdma_channel")); 185 186 handle = NXGE_DEV_NPI_HANDLE(nxgep); 187 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 188 189 if (rs != NPI_SUCCESS) { 190 status = NXGE_ERROR | rs; 191 } 192 193 return (status); 194 } 195 196 void 197 nxge_rxdma_regs_dump_channels(p_nxge_t nxgep) 198 { 199 int i, ndmas; 200 uint16_t channel; 201 p_rx_rbr_rings_t rx_rbr_rings; 202 p_rx_rbr_ring_t *rbr_rings; 203 npi_handle_t handle; 204 205 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_regs_dump_channels")); 206 207 handle = NXGE_DEV_NPI_HANDLE(nxgep); 208 (void) npi_rxdma_dump_fzc_regs(handle); 209 210 rx_rbr_rings = nxgep->rx_rbr_rings; 211 if (rx_rbr_rings == NULL) { 212 NXGE_DEBUG_MSG((nxgep, RX_CTL, 213 "<== nxge_rxdma_regs_dump_channels: " 214 "NULL ring pointer")); 215 return; 216 } 217 if (rx_rbr_rings->rbr_rings == NULL) { 218 NXGE_DEBUG_MSG((nxgep, RX_CTL, 219 "<== nxge_rxdma_regs_dump_channels: " 220 " NULL rbr rings pointer")); 221 return; 222 } 223 224 ndmas = rx_rbr_rings->ndmas; 225 if (!ndmas) { 226 NXGE_DEBUG_MSG((nxgep, RX_CTL, 227 "<== nxge_rxdma_regs_dump_channels: no channel")); 228 return; 229 } 230 231 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 232 "==> nxge_rxdma_regs_dump_channels (ndmas %d)", ndmas)); 233 234 rbr_rings = rx_rbr_rings->rbr_rings; 235 for (i = 0; i < ndmas; i++) { 236 if (rbr_rings == NULL || rbr_rings[i] == NULL) { 237 continue; 238 } 239 channel = rbr_rings[i]->rdc; 240 (void) nxge_dump_rxdma_channel(nxgep, channel); 241 } 242 243 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_regs_dump")); 244 245 } 246 247 nxge_status_t 248 nxge_dump_rxdma_channel(p_nxge_t nxgep, uint8_t channel) 249 { 250 npi_handle_t handle; 251 npi_status_t rs = NPI_SUCCESS; 252 nxge_status_t status = NXGE_OK; 253 254 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_dump_rxdma_channel")); 255 256 handle = NXGE_DEV_NPI_HANDLE(nxgep); 257 rs = npi_rxdma_dump_rdc_regs(handle, channel); 258 259 if (rs != NPI_SUCCESS) { 260 status = NXGE_ERROR | rs; 261 } 262 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dump_rxdma_channel")); 263 return (status); 264 } 265 266 nxge_status_t 267 nxge_init_rxdma_channel_event_mask(p_nxge_t nxgep, uint16_t channel, 268 p_rx_dma_ent_msk_t mask_p) 269 { 270 npi_handle_t handle; 271 npi_status_t rs = NPI_SUCCESS; 272 nxge_status_t status = NXGE_OK; 273 274 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 275 "<== nxge_init_rxdma_channel_event_mask")); 276 277 handle = NXGE_DEV_NPI_HANDLE(nxgep); 278 rs = npi_rxdma_event_mask(handle, OP_SET, channel, mask_p); 279 if (rs != NPI_SUCCESS) { 280 status = NXGE_ERROR | rs; 281 } 282 283 return (status); 284 } 285 286 nxge_status_t 287 nxge_init_rxdma_channel_cntl_stat(p_nxge_t nxgep, uint16_t channel, 288 p_rx_dma_ctl_stat_t cs_p) 289 { 290 npi_handle_t handle; 291 npi_status_t rs = NPI_SUCCESS; 292 nxge_status_t status = NXGE_OK; 293 294 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 295 "<== nxge_init_rxdma_channel_cntl_stat")); 296 297 handle = NXGE_DEV_NPI_HANDLE(nxgep); 298 rs = npi_rxdma_control_status(handle, OP_SET, channel, cs_p); 299 300 if (rs != NPI_SUCCESS) { 301 status = NXGE_ERROR | rs; 302 } 303 304 return (status); 305 } 306 307 nxge_status_t 308 nxge_rxdma_cfg_rdcgrp_default_rdc(p_nxge_t nxgep, uint8_t rdcgrp, 309 uint8_t rdc) 310 { 311 npi_handle_t handle; 312 npi_status_t rs = NPI_SUCCESS; 313 p_nxge_dma_pt_cfg_t p_dma_cfgp; 314 p_nxge_rdc_grp_t rdc_grp_p; 315 uint8_t actual_rdcgrp, actual_rdc; 316 317 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 318 " ==> nxge_rxdma_cfg_rdcgrp_default_rdc")); 319 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 320 321 handle = NXGE_DEV_NPI_HANDLE(nxgep); 322 323 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdcgrp]; 324 rdc_grp_p->rdc[0] = rdc; 325 326 actual_rdcgrp = NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp); 327 actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc); 328 329 rs = npi_rxdma_cfg_rdc_table_default_rdc(handle, actual_rdcgrp, 330 actual_rdc); 331 332 if (rs != NPI_SUCCESS) { 333 return (NXGE_ERROR | rs); 334 } 335 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 336 " <== nxge_rxdma_cfg_rdcgrp_default_rdc")); 337 return (NXGE_OK); 338 } 339 340 nxge_status_t 341 nxge_rxdma_cfg_port_default_rdc(p_nxge_t nxgep, uint8_t port, uint8_t rdc) 342 { 343 npi_handle_t handle; 344 345 uint8_t actual_rdc; 346 npi_status_t rs = NPI_SUCCESS; 347 348 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 349 " ==> nxge_rxdma_cfg_port_default_rdc")); 350 351 handle = NXGE_DEV_NPI_HANDLE(nxgep); 352 actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc); 353 rs = npi_rxdma_cfg_default_port_rdc(handle, port, actual_rdc); 354 355 356 if (rs != NPI_SUCCESS) { 357 return (NXGE_ERROR | rs); 358 } 359 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 360 " <== nxge_rxdma_cfg_port_default_rdc")); 361 362 return (NXGE_OK); 363 } 364 365 nxge_status_t 366 nxge_rxdma_cfg_rcr_threshold(p_nxge_t nxgep, uint8_t channel, 367 uint16_t pkts) 368 { 369 npi_status_t rs = NPI_SUCCESS; 370 npi_handle_t handle; 371 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 372 " ==> nxge_rxdma_cfg_rcr_threshold")); 373 handle = NXGE_DEV_NPI_HANDLE(nxgep); 374 375 rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, pkts); 376 377 if (rs != NPI_SUCCESS) { 378 return (NXGE_ERROR | rs); 379 } 380 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_threshold")); 381 return (NXGE_OK); 382 } 383 384 nxge_status_t 385 nxge_rxdma_cfg_rcr_timeout(p_nxge_t nxgep, uint8_t channel, 386 uint16_t tout, uint8_t enable) 387 { 388 npi_status_t rs = NPI_SUCCESS; 389 npi_handle_t handle; 390 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " ==> nxge_rxdma_cfg_rcr_timeout")); 391 handle = NXGE_DEV_NPI_HANDLE(nxgep); 392 if (enable == 0) { 393 rs = npi_rxdma_cfg_rdc_rcr_timeout_disable(handle, channel); 394 } else { 395 rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 396 tout); 397 } 398 399 if (rs != NPI_SUCCESS) { 400 return (NXGE_ERROR | rs); 401 } 402 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_timeout")); 403 return (NXGE_OK); 404 } 405 406 nxge_status_t 407 nxge_enable_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 408 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 409 { 410 npi_handle_t handle; 411 rdc_desc_cfg_t rdc_desc; 412 p_rcrcfig_b_t cfgb_p; 413 npi_status_t rs = NPI_SUCCESS; 414 415 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel")); 416 handle = NXGE_DEV_NPI_HANDLE(nxgep); 417 /* 418 * Use configuration data composed at init time. 419 * Write to hardware the receive ring configurations. 420 */ 421 rdc_desc.mbox_enable = 1; 422 rdc_desc.mbox_addr = mbox_p->mbox_addr; 423 NXGE_DEBUG_MSG((nxgep, RX_CTL, 424 "==> nxge_enable_rxdma_channel: mboxp $%p($%p)", 425 mbox_p->mbox_addr, rdc_desc.mbox_addr)); 426 427 rdc_desc.rbr_len = rbr_p->rbb_max; 428 rdc_desc.rbr_addr = rbr_p->rbr_addr; 429 430 switch (nxgep->rx_bksize_code) { 431 case RBR_BKSIZE_4K: 432 rdc_desc.page_size = SIZE_4KB; 433 break; 434 case RBR_BKSIZE_8K: 435 rdc_desc.page_size = SIZE_8KB; 436 break; 437 case RBR_BKSIZE_16K: 438 rdc_desc.page_size = SIZE_16KB; 439 break; 440 case RBR_BKSIZE_32K: 441 rdc_desc.page_size = SIZE_32KB; 442 break; 443 } 444 445 rdc_desc.size0 = rbr_p->npi_pkt_buf_size0; 446 rdc_desc.valid0 = 1; 447 448 rdc_desc.size1 = rbr_p->npi_pkt_buf_size1; 449 rdc_desc.valid1 = 1; 450 451 rdc_desc.size2 = rbr_p->npi_pkt_buf_size2; 452 rdc_desc.valid2 = 1; 453 454 rdc_desc.full_hdr = rcr_p->full_hdr_flag; 455 rdc_desc.offset = rcr_p->sw_priv_hdr_len; 456 457 rdc_desc.rcr_len = rcr_p->comp_size; 458 rdc_desc.rcr_addr = rcr_p->rcr_addr; 459 460 cfgb_p = &(rcr_p->rcr_cfgb); 461 rdc_desc.rcr_threshold = cfgb_p->bits.ldw.pthres; 462 rdc_desc.rcr_timeout = cfgb_p->bits.ldw.timeout; 463 rdc_desc.rcr_timeout_enable = cfgb_p->bits.ldw.entout; 464 465 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 466 "rbr_len qlen %d pagesize code %d rcr_len %d", 467 rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len)); 468 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 469 "size 0 %d size 1 %d size 2 %d", 470 rbr_p->npi_pkt_buf_size0, rbr_p->npi_pkt_buf_size1, 471 rbr_p->npi_pkt_buf_size2)); 472 473 rs = npi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc, &rdc_desc); 474 if (rs != NPI_SUCCESS) { 475 return (NXGE_ERROR | rs); 476 } 477 478 /* 479 * Enable the timeout and threshold. 480 */ 481 rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, 482 rdc_desc.rcr_threshold); 483 if (rs != NPI_SUCCESS) { 484 return (NXGE_ERROR | rs); 485 } 486 487 rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 488 rdc_desc.rcr_timeout); 489 if (rs != NPI_SUCCESS) { 490 return (NXGE_ERROR | rs); 491 } 492 493 /* Enable the DMA */ 494 rs = npi_rxdma_cfg_rdc_enable(handle, channel); 495 if (rs != NPI_SUCCESS) { 496 return (NXGE_ERROR | rs); 497 } 498 499 /* Kick the DMA engine. */ 500 npi_rxdma_rdc_rbr_kick(handle, channel, rbr_p->rbb_max); 501 /* Clear the rbr empty bit */ 502 (void) npi_rxdma_channel_rbr_empty_clear(handle, channel); 503 504 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_enable_rxdma_channel")); 505 506 return (NXGE_OK); 507 } 508 509 nxge_status_t 510 nxge_disable_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 511 { 512 npi_handle_t handle; 513 npi_status_t rs = NPI_SUCCESS; 514 515 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_disable_rxdma_channel")); 516 handle = NXGE_DEV_NPI_HANDLE(nxgep); 517 518 /* disable the DMA */ 519 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 520 if (rs != NPI_SUCCESS) { 521 NXGE_DEBUG_MSG((nxgep, RX_CTL, 522 "<== nxge_disable_rxdma_channel:failed (0x%x)", 523 rs)); 524 return (NXGE_ERROR | rs); 525 } 526 527 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_disable_rxdma_channel")); 528 return (NXGE_OK); 529 } 530 531 nxge_status_t 532 nxge_rxdma_channel_rcrflush(p_nxge_t nxgep, uint8_t channel) 533 { 534 npi_handle_t handle; 535 nxge_status_t status = NXGE_OK; 536 537 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 538 "<== nxge_init_rxdma_channel_rcrflush")); 539 540 handle = NXGE_DEV_NPI_HANDLE(nxgep); 541 npi_rxdma_rdc_rcr_flush(handle, channel); 542 543 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 544 "<== nxge_init_rxdma_channel_rcrflsh")); 545 return (status); 546 547 } 548 549 #define MID_INDEX(l, r) ((r + l + 1) >> 1) 550 551 #define TO_LEFT -1 552 #define TO_RIGHT 1 553 #define BOTH_RIGHT (TO_RIGHT + TO_RIGHT) 554 #define BOTH_LEFT (TO_LEFT + TO_LEFT) 555 #define IN_MIDDLE (TO_RIGHT + TO_LEFT) 556 #define NO_HINT 0xffffffff 557 558 /*ARGSUSED*/ 559 nxge_status_t 560 nxge_rxbuf_pp_to_vp(p_nxge_t nxgep, p_rx_rbr_ring_t rbr_p, 561 uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp, 562 uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index) 563 { 564 int bufsize; 565 uint64_t pktbuf_pp; 566 uint64_t dvma_addr; 567 rxring_info_t *ring_info; 568 int base_side, end_side; 569 int r_index, l_index, anchor_index; 570 int found, search_done; 571 uint32_t offset, chunk_size, block_size, page_size_mask; 572 uint32_t chunk_index, block_index, total_index; 573 int max_iterations, iteration; 574 rxbuf_index_info_t *bufinfo; 575 576 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_rxbuf_pp_to_vp")); 577 578 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 579 "==> nxge_rxbuf_pp_to_vp: buf_pp $%p btype %d", 580 pkt_buf_addr_pp, 581 pktbufsz_type)); 582 583 pktbuf_pp = (uint64_t)pkt_buf_addr_pp; 584 585 switch (pktbufsz_type) { 586 case 0: 587 bufsize = rbr_p->pkt_buf_size0; 588 break; 589 case 1: 590 bufsize = rbr_p->pkt_buf_size1; 591 break; 592 case 2: 593 bufsize = rbr_p->pkt_buf_size2; 594 break; 595 case RCR_SINGLE_BLOCK: 596 bufsize = 0; 597 anchor_index = 0; 598 break; 599 default: 600 return (NXGE_ERROR); 601 } 602 603 if (rbr_p->num_blocks == 1) { 604 anchor_index = 0; 605 ring_info = rbr_p->ring_info; 606 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 607 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 608 "==> nxge_rxbuf_pp_to_vp: (found, 1 block) " 609 "buf_pp $%p btype %d anchor_index %d " 610 "bufinfo $%p", 611 pkt_buf_addr_pp, 612 pktbufsz_type, 613 anchor_index, 614 bufinfo)); 615 616 goto found_index; 617 } 618 619 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 620 "==> nxge_rxbuf_pp_to_vp: " 621 "buf_pp $%p btype %d anchor_index %d", 622 pkt_buf_addr_pp, 623 pktbufsz_type, 624 anchor_index)); 625 626 ring_info = rbr_p->ring_info; 627 found = B_FALSE; 628 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 629 iteration = 0; 630 max_iterations = ring_info->max_iterations; 631 /* 632 * First check if this block has been seen 633 * recently. This is indicated by a hint which 634 * is initialized when the first buffer of the block 635 * is seen. The hint is reset when the last buffer of 636 * the block has been processed. 637 * As three block sizes are supported, three hints 638 * are kept. The idea behind the hints is that once 639 * the hardware uses a block for a buffer of that 640 * size, it will use it exclusively for that size 641 * and will use it until it is exhausted. It is assumed 642 * that there would a single block being used for the same 643 * buffer sizes at any given time. 644 */ 645 if (ring_info->hint[pktbufsz_type] != NO_HINT) { 646 anchor_index = ring_info->hint[pktbufsz_type]; 647 dvma_addr = bufinfo[anchor_index].dvma_addr; 648 chunk_size = bufinfo[anchor_index].buf_size; 649 if ((pktbuf_pp >= dvma_addr) && 650 (pktbuf_pp < (dvma_addr + chunk_size))) { 651 found = B_TRUE; 652 /* 653 * check if this is the last buffer in the block 654 * If so, then reset the hint for the size; 655 */ 656 657 if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size)) 658 ring_info->hint[pktbufsz_type] = NO_HINT; 659 } 660 } 661 662 if (found == B_FALSE) { 663 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 664 "==> nxge_rxbuf_pp_to_vp: (!found)" 665 "buf_pp $%p btype %d anchor_index %d", 666 pkt_buf_addr_pp, 667 pktbufsz_type, 668 anchor_index)); 669 670 /* 671 * This is the first buffer of the block of this 672 * size. Need to search the whole information 673 * array. 674 * the search algorithm uses a binary tree search 675 * algorithm. It assumes that the information is 676 * already sorted with increasing order 677 * info[0] < info[1] < info[2] .... < info[n-1] 678 * where n is the size of the information array 679 */ 680 r_index = rbr_p->num_blocks - 1; 681 l_index = 0; 682 search_done = B_FALSE; 683 anchor_index = MID_INDEX(r_index, l_index); 684 while (search_done == B_FALSE) { 685 if ((r_index == l_index) || 686 (iteration >= max_iterations)) 687 search_done = B_TRUE; 688 end_side = TO_RIGHT; /* to the right */ 689 base_side = TO_LEFT; /* to the left */ 690 /* read the DVMA address information and sort it */ 691 dvma_addr = bufinfo[anchor_index].dvma_addr; 692 chunk_size = bufinfo[anchor_index].buf_size; 693 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 694 "==> nxge_rxbuf_pp_to_vp: (searching)" 695 "buf_pp $%p btype %d " 696 "anchor_index %d chunk_size %d dvmaaddr $%p", 697 pkt_buf_addr_pp, 698 pktbufsz_type, 699 anchor_index, 700 chunk_size, 701 dvma_addr)); 702 703 if (pktbuf_pp >= dvma_addr) 704 base_side = TO_RIGHT; /* to the right */ 705 if (pktbuf_pp < (dvma_addr + chunk_size)) 706 end_side = TO_LEFT; /* to the left */ 707 708 switch (base_side + end_side) { 709 case IN_MIDDLE: 710 /* found */ 711 found = B_TRUE; 712 search_done = B_TRUE; 713 if ((pktbuf_pp + bufsize) < 714 (dvma_addr + chunk_size)) 715 ring_info->hint[pktbufsz_type] = 716 bufinfo[anchor_index].buf_index; 717 break; 718 case BOTH_RIGHT: 719 /* not found: go to the right */ 720 l_index = anchor_index + 1; 721 anchor_index = 722 MID_INDEX(r_index, l_index); 723 break; 724 725 case BOTH_LEFT: 726 /* not found: go to the left */ 727 r_index = anchor_index - 1; 728 anchor_index = MID_INDEX(r_index, 729 l_index); 730 break; 731 default: /* should not come here */ 732 return (NXGE_ERROR); 733 } 734 iteration++; 735 } 736 737 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 738 "==> nxge_rxbuf_pp_to_vp: (search done)" 739 "buf_pp $%p btype %d anchor_index %d", 740 pkt_buf_addr_pp, 741 pktbufsz_type, 742 anchor_index)); 743 } 744 745 if (found == B_FALSE) { 746 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 747 "==> nxge_rxbuf_pp_to_vp: (search failed)" 748 "buf_pp $%p btype %d anchor_index %d", 749 pkt_buf_addr_pp, 750 pktbufsz_type, 751 anchor_index)); 752 return (NXGE_ERROR); 753 } 754 755 found_index: 756 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 757 "==> nxge_rxbuf_pp_to_vp: (FOUND1)" 758 "buf_pp $%p btype %d bufsize %d anchor_index %d", 759 pkt_buf_addr_pp, 760 pktbufsz_type, 761 bufsize, 762 anchor_index)); 763 764 /* index of the first block in this chunk */ 765 chunk_index = bufinfo[anchor_index].start_index; 766 dvma_addr = bufinfo[anchor_index].dvma_addr; 767 page_size_mask = ring_info->block_size_mask; 768 769 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 770 "==> nxge_rxbuf_pp_to_vp: (FOUND3), get chunk)" 771 "buf_pp $%p btype %d bufsize %d " 772 "anchor_index %d chunk_index %d dvma $%p", 773 pkt_buf_addr_pp, 774 pktbufsz_type, 775 bufsize, 776 anchor_index, 777 chunk_index, 778 dvma_addr)); 779 780 offset = pktbuf_pp - dvma_addr; /* offset within the chunk */ 781 block_size = rbr_p->block_size; /* System block(page) size */ 782 783 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 784 "==> nxge_rxbuf_pp_to_vp: (FOUND4), get chunk)" 785 "buf_pp $%p btype %d bufsize %d " 786 "anchor_index %d chunk_index %d dvma $%p " 787 "offset %d block_size %d", 788 pkt_buf_addr_pp, 789 pktbufsz_type, 790 bufsize, 791 anchor_index, 792 chunk_index, 793 dvma_addr, 794 offset, 795 block_size)); 796 797 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> getting total index")); 798 799 block_index = (offset / block_size); /* index within chunk */ 800 total_index = chunk_index + block_index; 801 802 803 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 804 "==> nxge_rxbuf_pp_to_vp: " 805 "total_index %d dvma_addr $%p " 806 "offset %d block_size %d " 807 "block_index %d ", 808 total_index, dvma_addr, 809 offset, block_size, 810 block_index)); 811 812 *pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr 813 + offset); 814 815 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 816 "==> nxge_rxbuf_pp_to_vp: " 817 "total_index %d dvma_addr $%p " 818 "offset %d block_size %d " 819 "block_index %d " 820 "*pkt_buf_addr_p $%p", 821 total_index, dvma_addr, 822 offset, block_size, 823 block_index, 824 *pkt_buf_addr_p)); 825 826 827 *msg_index = total_index; 828 *bufoffset = (offset & page_size_mask); 829 830 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 831 "==> nxge_rxbuf_pp_to_vp: get msg index: " 832 "msg_index %d bufoffset_index %d", 833 *msg_index, 834 *bufoffset)); 835 836 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rxbuf_pp_to_vp")); 837 838 return (NXGE_OK); 839 } 840 841 /* 842 * used by quick sort (qsort) function 843 * to perform comparison 844 */ 845 static int 846 nxge_sort_compare(const void *p1, const void *p2) 847 { 848 849 rxbuf_index_info_t *a, *b; 850 851 a = (rxbuf_index_info_t *)p1; 852 b = (rxbuf_index_info_t *)p2; 853 854 if (a->dvma_addr > b->dvma_addr) 855 return (1); 856 if (a->dvma_addr < b->dvma_addr) 857 return (-1); 858 return (0); 859 } 860 861 862 863 /* 864 * grabbed this sort implementation from common/syscall/avl.c 865 * 866 */ 867 /* 868 * Generic shellsort, from K&R (1st ed, p 58.), somewhat modified. 869 * v = Ptr to array/vector of objs 870 * n = # objs in the array 871 * s = size of each obj (must be multiples of a word size) 872 * f = ptr to function to compare two objs 873 * returns (-1 = less than, 0 = equal, 1 = greater than 874 */ 875 void 876 nxge_ksort(caddr_t v, int n, int s, int (*f)()) 877 { 878 int g, i, j, ii; 879 unsigned int *p1, *p2; 880 unsigned int tmp; 881 882 /* No work to do */ 883 if (v == NULL || n <= 1) 884 return; 885 /* Sanity check on arguments */ 886 ASSERT(((uintptr_t)v & 0x3) == 0 && (s & 0x3) == 0); 887 ASSERT(s > 0); 888 889 for (g = n / 2; g > 0; g /= 2) { 890 for (i = g; i < n; i++) { 891 for (j = i - g; j >= 0 && 892 (*f)(v + j * s, v + (j + g) * s) == 1; 893 j -= g) { 894 p1 = (unsigned *)(v + j * s); 895 p2 = (unsigned *)(v + (j + g) * s); 896 for (ii = 0; ii < s / 4; ii++) { 897 tmp = *p1; 898 *p1++ = *p2; 899 *p2++ = tmp; 900 } 901 } 902 } 903 } 904 } 905 906 /* 907 * Initialize data structures required for rxdma 908 * buffer dvma->vmem address lookup 909 */ 910 /*ARGSUSED*/ 911 static nxge_status_t 912 nxge_rxbuf_index_info_init(p_nxge_t nxgep, p_rx_rbr_ring_t rbrp) 913 { 914 915 int index; 916 rxring_info_t *ring_info; 917 int max_iteration = 0, max_index = 0; 918 919 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_rxbuf_index_info_init")); 920 921 ring_info = rbrp->ring_info; 922 ring_info->hint[0] = NO_HINT; 923 ring_info->hint[1] = NO_HINT; 924 ring_info->hint[2] = NO_HINT; 925 max_index = rbrp->num_blocks; 926 927 /* read the DVMA address information and sort it */ 928 /* do init of the information array */ 929 930 931 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 932 " nxge_rxbuf_index_info_init Sort ptrs")); 933 934 /* sort the array */ 935 nxge_ksort((void *)ring_info->buffer, max_index, 936 sizeof (rxbuf_index_info_t), nxge_sort_compare); 937 938 939 940 for (index = 0; index < max_index; index++) { 941 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 942 " nxge_rxbuf_index_info_init: sorted chunk %d " 943 " ioaddr $%p kaddr $%p size %x", 944 index, ring_info->buffer[index].dvma_addr, 945 ring_info->buffer[index].kaddr, 946 ring_info->buffer[index].buf_size)); 947 } 948 949 max_iteration = 0; 950 while (max_index >= (1ULL << max_iteration)) 951 max_iteration++; 952 ring_info->max_iterations = max_iteration + 1; 953 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 954 " nxge_rxbuf_index_info_init Find max iter %d", 955 ring_info->max_iterations)); 956 957 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxbuf_index_info_init")); 958 return (NXGE_OK); 959 } 960 961 /* ARGSUSED */ 962 void 963 nxge_dump_rcr_entry(p_nxge_t nxgep, p_rcr_entry_t entry_p) 964 { 965 #ifdef NXGE_DEBUG 966 967 uint32_t bptr; 968 uint64_t pp; 969 970 bptr = entry_p->bits.hdw.pkt_buf_addr; 971 972 NXGE_DEBUG_MSG((nxgep, RX_CTL, 973 "\trcr entry $%p " 974 "\trcr entry 0x%0llx " 975 "\trcr entry 0x%08x " 976 "\trcr entry 0x%08x " 977 "\tvalue 0x%0llx\n" 978 "\tmulti = %d\n" 979 "\tpkt_type = 0x%x\n" 980 "\tzero_copy = %d\n" 981 "\tnoport = %d\n" 982 "\tpromis = %d\n" 983 "\terror = 0x%04x\n" 984 "\tdcf_err = 0x%01x\n" 985 "\tl2_len = %d\n" 986 "\tpktbufsize = %d\n" 987 "\tpkt_buf_addr = $%p\n" 988 "\tpkt_buf_addr (<< 6) = $%p\n", 989 entry_p, 990 *(int64_t *)entry_p, 991 *(int32_t *)entry_p, 992 *(int32_t *)((char *)entry_p + 32), 993 entry_p->value, 994 entry_p->bits.hdw.multi, 995 entry_p->bits.hdw.pkt_type, 996 entry_p->bits.hdw.zero_copy, 997 entry_p->bits.hdw.noport, 998 entry_p->bits.hdw.promis, 999 entry_p->bits.hdw.error, 1000 entry_p->bits.hdw.dcf_err, 1001 entry_p->bits.hdw.l2_len, 1002 entry_p->bits.hdw.pktbufsz, 1003 bptr, 1004 entry_p->bits.ldw.pkt_buf_addr)); 1005 1006 pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) << 1007 RCR_PKT_BUF_ADDR_SHIFT; 1008 1009 NXGE_DEBUG_MSG((nxgep, RX_CTL, "rcr pp 0x%llx l2 len %d", 1010 pp, (*(int64_t *)entry_p >> 40) & 0x3fff)); 1011 #endif 1012 } 1013 1014 void 1015 nxge_rxdma_regs_dump(p_nxge_t nxgep, int rdc) 1016 { 1017 npi_handle_t handle; 1018 rbr_stat_t rbr_stat; 1019 addr44_t hd_addr; 1020 addr44_t tail_addr; 1021 uint16_t qlen; 1022 1023 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1024 "==> nxge_rxdma_regs_dump: rdc channel %d", rdc)); 1025 1026 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1027 1028 /* RBR head */ 1029 hd_addr.addr = 0; 1030 (void) npi_rxdma_rdc_rbr_head_get(handle, rdc, &hd_addr); 1031 printf("nxge_rxdma_regs_dump: got hdptr $%p \n", 1032 (void *)hd_addr.addr); 1033 1034 /* RBR stats */ 1035 (void) npi_rxdma_rdc_rbr_stat_get(handle, rdc, &rbr_stat); 1036 printf("nxge_rxdma_regs_dump: rbr len %d \n", rbr_stat.bits.ldw.qlen); 1037 1038 /* RCR tail */ 1039 tail_addr.addr = 0; 1040 (void) npi_rxdma_rdc_rcr_tail_get(handle, rdc, &tail_addr); 1041 printf("nxge_rxdma_regs_dump: got tail ptr $%p \n", 1042 (void *)tail_addr.addr); 1043 1044 /* RCR qlen */ 1045 (void) npi_rxdma_rdc_rcr_qlen_get(handle, rdc, &qlen); 1046 printf("nxge_rxdma_regs_dump: rcr len %x \n", qlen); 1047 1048 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1049 "<== nxge_rxdma_regs_dump: rdc rdc %d", rdc)); 1050 } 1051 1052 void 1053 nxge_rxdma_stop(p_nxge_t nxgep) 1054 { 1055 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop")); 1056 1057 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 1058 (void) nxge_rx_mac_disable(nxgep); 1059 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 1060 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop")); 1061 } 1062 1063 void 1064 nxge_rxdma_stop_reinit(p_nxge_t nxgep) 1065 { 1066 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_reinit")); 1067 1068 (void) nxge_rxdma_stop(nxgep); 1069 (void) nxge_uninit_rxdma_channels(nxgep); 1070 (void) nxge_init_rxdma_channels(nxgep); 1071 1072 #ifndef AXIS_DEBUG_LB 1073 (void) nxge_xcvr_init(nxgep); 1074 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 1075 #endif 1076 (void) nxge_rx_mac_enable(nxgep); 1077 1078 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_reinit")); 1079 } 1080 1081 nxge_status_t 1082 nxge_rxdma_hw_mode(p_nxge_t nxgep, boolean_t enable) 1083 { 1084 int i, ndmas; 1085 uint16_t channel; 1086 p_rx_rbr_rings_t rx_rbr_rings; 1087 p_rx_rbr_ring_t *rbr_rings; 1088 npi_handle_t handle; 1089 npi_status_t rs = NPI_SUCCESS; 1090 nxge_status_t status = NXGE_OK; 1091 1092 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1093 "==> nxge_rxdma_hw_mode: mode %d", enable)); 1094 1095 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1096 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1097 "<== nxge_rxdma_mode: not initialized")); 1098 return (NXGE_ERROR); 1099 } 1100 1101 rx_rbr_rings = nxgep->rx_rbr_rings; 1102 if (rx_rbr_rings == NULL) { 1103 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1104 "<== nxge_rxdma_mode: NULL ring pointer")); 1105 return (NXGE_ERROR); 1106 } 1107 if (rx_rbr_rings->rbr_rings == NULL) { 1108 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1109 "<== nxge_rxdma_mode: NULL rbr rings pointer")); 1110 return (NXGE_ERROR); 1111 } 1112 1113 ndmas = rx_rbr_rings->ndmas; 1114 if (!ndmas) { 1115 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1116 "<== nxge_rxdma_mode: no channel")); 1117 return (NXGE_ERROR); 1118 } 1119 1120 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1121 "==> nxge_rxdma_mode (ndmas %d)", ndmas)); 1122 1123 rbr_rings = rx_rbr_rings->rbr_rings; 1124 1125 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1126 for (i = 0; i < ndmas; i++) { 1127 if (rbr_rings == NULL || rbr_rings[i] == NULL) { 1128 continue; 1129 } 1130 channel = rbr_rings[i]->rdc; 1131 if (enable) { 1132 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1133 "==> nxge_rxdma_hw_mode: channel %d (enable)", 1134 channel)); 1135 rs = npi_rxdma_cfg_rdc_enable(handle, channel); 1136 } else { 1137 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1138 "==> nxge_rxdma_hw_mode: channel %d (disable)", 1139 channel)); 1140 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 1141 } 1142 } 1143 1144 status = ((rs == NPI_SUCCESS) ? NXGE_OK : NXGE_ERROR | rs); 1145 1146 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1147 "<== nxge_rxdma_hw_mode: status 0x%x", status)); 1148 1149 return (status); 1150 } 1151 1152 void 1153 nxge_rxdma_enable_channel(p_nxge_t nxgep, uint16_t channel) 1154 { 1155 npi_handle_t handle; 1156 1157 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 1158 "==> nxge_rxdma_enable_channel: channel %d", channel)); 1159 1160 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1161 (void) npi_rxdma_cfg_rdc_enable(handle, channel); 1162 1163 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_enable_channel")); 1164 } 1165 1166 void 1167 nxge_rxdma_disable_channel(p_nxge_t nxgep, uint16_t channel) 1168 { 1169 npi_handle_t handle; 1170 1171 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 1172 "==> nxge_rxdma_disable_channel: channel %d", channel)); 1173 1174 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1175 (void) npi_rxdma_cfg_rdc_disable(handle, channel); 1176 1177 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_disable_channel")); 1178 } 1179 1180 void 1181 nxge_hw_start_rx(p_nxge_t nxgep) 1182 { 1183 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_start_rx")); 1184 1185 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 1186 (void) nxge_rx_mac_enable(nxgep); 1187 1188 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_start_rx")); 1189 } 1190 1191 /*ARGSUSED*/ 1192 void 1193 nxge_fixup_rxdma_rings(p_nxge_t nxgep) 1194 { 1195 int i, ndmas; 1196 uint16_t rdc; 1197 p_rx_rbr_rings_t rx_rbr_rings; 1198 p_rx_rbr_ring_t *rbr_rings; 1199 p_rx_rcr_rings_t rx_rcr_rings; 1200 1201 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_fixup_rxdma_rings")); 1202 1203 rx_rbr_rings = nxgep->rx_rbr_rings; 1204 if (rx_rbr_rings == NULL) { 1205 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1206 "<== nxge_fixup_rxdma_rings: NULL ring pointer")); 1207 return; 1208 } 1209 ndmas = rx_rbr_rings->ndmas; 1210 if (!ndmas) { 1211 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1212 "<== nxge_fixup_rxdma_rings: no channel")); 1213 return; 1214 } 1215 1216 rx_rcr_rings = nxgep->rx_rcr_rings; 1217 if (rx_rcr_rings == NULL) { 1218 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1219 "<== nxge_fixup_rxdma_rings: NULL ring pointer")); 1220 return; 1221 } 1222 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1223 "==> nxge_fixup_rxdma_rings (ndmas %d)", ndmas)); 1224 1225 nxge_rxdma_hw_stop(nxgep); 1226 1227 rbr_rings = rx_rbr_rings->rbr_rings; 1228 for (i = 0; i < ndmas; i++) { 1229 rdc = rbr_rings[i]->rdc; 1230 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1231 "==> nxge_fixup_rxdma_rings: channel %d " 1232 "ring $%px", rdc, rbr_rings[i])); 1233 (void) nxge_rxdma_fixup_channel(nxgep, rdc, i); 1234 } 1235 1236 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_fixup_rxdma_rings")); 1237 } 1238 1239 void 1240 nxge_rxdma_fix_channel(p_nxge_t nxgep, uint16_t channel) 1241 { 1242 int i; 1243 1244 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fix_channel")); 1245 i = nxge_rxdma_get_ring_index(nxgep, channel); 1246 if (i < 0) { 1247 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1248 "<== nxge_rxdma_fix_channel: no entry found")); 1249 return; 1250 } 1251 1252 nxge_rxdma_fixup_channel(nxgep, channel, i); 1253 1254 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_txdma_fix_channel")); 1255 } 1256 1257 void 1258 nxge_rxdma_fixup_channel(p_nxge_t nxgep, uint16_t channel, int entry) 1259 { 1260 int ndmas; 1261 p_rx_rbr_rings_t rx_rbr_rings; 1262 p_rx_rbr_ring_t *rbr_rings; 1263 p_rx_rcr_rings_t rx_rcr_rings; 1264 p_rx_rcr_ring_t *rcr_rings; 1265 p_rx_mbox_areas_t rx_mbox_areas_p; 1266 p_rx_mbox_t *rx_mbox_p; 1267 p_nxge_dma_pool_t dma_buf_poolp; 1268 p_nxge_dma_pool_t dma_cntl_poolp; 1269 p_rx_rbr_ring_t rbrp; 1270 p_rx_rcr_ring_t rcrp; 1271 p_rx_mbox_t mboxp; 1272 p_nxge_dma_common_t dmap; 1273 nxge_status_t status = NXGE_OK; 1274 1275 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fixup_channel")); 1276 1277 (void) nxge_rxdma_stop_channel(nxgep, channel); 1278 1279 dma_buf_poolp = nxgep->rx_buf_pool_p; 1280 dma_cntl_poolp = nxgep->rx_cntl_pool_p; 1281 1282 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 1283 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1284 "<== nxge_rxdma_fixup_channel: buf not allocated")); 1285 return; 1286 } 1287 1288 ndmas = dma_buf_poolp->ndmas; 1289 if (!ndmas) { 1290 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1291 "<== nxge_rxdma_fixup_channel: no dma allocated")); 1292 return; 1293 } 1294 1295 rx_rbr_rings = nxgep->rx_rbr_rings; 1296 rx_rcr_rings = nxgep->rx_rcr_rings; 1297 rbr_rings = rx_rbr_rings->rbr_rings; 1298 rcr_rings = rx_rcr_rings->rcr_rings; 1299 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 1300 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 1301 1302 /* Reinitialize the receive block and completion rings */ 1303 rbrp = (p_rx_rbr_ring_t)rbr_rings[entry], 1304 rcrp = (p_rx_rcr_ring_t)rcr_rings[entry], 1305 mboxp = (p_rx_mbox_t)rx_mbox_p[entry]; 1306 1307 1308 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 1309 rbrp->rbr_rd_index = 0; 1310 rcrp->comp_rd_index = 0; 1311 rcrp->comp_wt_index = 0; 1312 1313 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 1314 bzero((caddr_t)dmap->kaddrp, dmap->alength); 1315 1316 status = nxge_rxdma_start_channel(nxgep, channel, 1317 rbrp, rcrp, mboxp); 1318 if (status != NXGE_OK) { 1319 goto nxge_rxdma_fixup_channel_fail; 1320 } 1321 if (status != NXGE_OK) { 1322 goto nxge_rxdma_fixup_channel_fail; 1323 } 1324 1325 nxge_rxdma_fixup_channel_fail: 1326 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1327 "==> nxge_rxdma_fixup_channel: failed (0x%08x)", status)); 1328 1329 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fixup_channel")); 1330 } 1331 1332 int 1333 nxge_rxdma_get_ring_index(p_nxge_t nxgep, uint16_t channel) 1334 { 1335 int i, ndmas; 1336 uint16_t rdc; 1337 p_rx_rbr_rings_t rx_rbr_rings; 1338 p_rx_rbr_ring_t *rbr_rings; 1339 1340 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1341 "==> nxge_rxdma_get_ring_index: channel %d", channel)); 1342 1343 rx_rbr_rings = nxgep->rx_rbr_rings; 1344 if (rx_rbr_rings == NULL) { 1345 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1346 "<== nxge_rxdma_get_ring_index: NULL ring pointer")); 1347 return (-1); 1348 } 1349 ndmas = rx_rbr_rings->ndmas; 1350 if (!ndmas) { 1351 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1352 "<== nxge_rxdma_get_ring_index: no channel")); 1353 return (-1); 1354 } 1355 1356 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1357 "==> nxge_rxdma_get_ring_index (ndmas %d)", ndmas)); 1358 1359 rbr_rings = rx_rbr_rings->rbr_rings; 1360 for (i = 0; i < ndmas; i++) { 1361 rdc = rbr_rings[i]->rdc; 1362 if (channel == rdc) { 1363 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1364 "==> nxge_rxdma_get_rbr_ring: " 1365 "channel %d (index %d) " 1366 "ring %d", channel, i, 1367 rbr_rings[i])); 1368 return (i); 1369 } 1370 } 1371 1372 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1373 "<== nxge_rxdma_get_rbr_ring_index: not found")); 1374 1375 return (-1); 1376 } 1377 1378 p_rx_rbr_ring_t 1379 nxge_rxdma_get_rbr_ring(p_nxge_t nxgep, uint16_t channel) 1380 { 1381 int i, ndmas; 1382 uint16_t rdc; 1383 p_rx_rbr_rings_t rx_rbr_rings; 1384 p_rx_rbr_ring_t *rbr_rings; 1385 1386 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1387 "==> nxge_rxdma_get_rbr_ring: channel %d", channel)); 1388 1389 rx_rbr_rings = nxgep->rx_rbr_rings; 1390 if (rx_rbr_rings == NULL) { 1391 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1392 "<== nxge_rxdma_get_rbr_ring: NULL ring pointer")); 1393 return (NULL); 1394 } 1395 ndmas = rx_rbr_rings->ndmas; 1396 if (!ndmas) { 1397 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1398 "<== nxge_rxdma_get_rbr_ring: no channel")); 1399 return (NULL); 1400 } 1401 1402 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1403 "==> nxge_rxdma_get_ring (ndmas %d)", ndmas)); 1404 1405 rbr_rings = rx_rbr_rings->rbr_rings; 1406 for (i = 0; i < ndmas; i++) { 1407 rdc = rbr_rings[i]->rdc; 1408 if (channel == rdc) { 1409 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1410 "==> nxge_rxdma_get_rbr_ring: channel %d " 1411 "ring $%p", channel, rbr_rings[i])); 1412 return (rbr_rings[i]); 1413 } 1414 } 1415 1416 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1417 "<== nxge_rxdma_get_rbr_ring: not found")); 1418 1419 return (NULL); 1420 } 1421 1422 p_rx_rcr_ring_t 1423 nxge_rxdma_get_rcr_ring(p_nxge_t nxgep, uint16_t channel) 1424 { 1425 int i, ndmas; 1426 uint16_t rdc; 1427 p_rx_rcr_rings_t rx_rcr_rings; 1428 p_rx_rcr_ring_t *rcr_rings; 1429 1430 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1431 "==> nxge_rxdma_get_rcr_ring: channel %d", channel)); 1432 1433 rx_rcr_rings = nxgep->rx_rcr_rings; 1434 if (rx_rcr_rings == NULL) { 1435 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1436 "<== nxge_rxdma_get_rcr_ring: NULL ring pointer")); 1437 return (NULL); 1438 } 1439 ndmas = rx_rcr_rings->ndmas; 1440 if (!ndmas) { 1441 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1442 "<== nxge_rxdma_get_rcr_ring: no channel")); 1443 return (NULL); 1444 } 1445 1446 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1447 "==> nxge_rxdma_get_rcr_ring (ndmas %d)", ndmas)); 1448 1449 rcr_rings = rx_rcr_rings->rcr_rings; 1450 for (i = 0; i < ndmas; i++) { 1451 rdc = rcr_rings[i]->rdc; 1452 if (channel == rdc) { 1453 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1454 "==> nxge_rxdma_get_rcr_ring: channel %d " 1455 "ring $%p", channel, rcr_rings[i])); 1456 return (rcr_rings[i]); 1457 } 1458 } 1459 1460 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1461 "<== nxge_rxdma_get_rcr_ring: not found")); 1462 1463 return (NULL); 1464 } 1465 1466 /* 1467 * Static functions start here. 1468 */ 1469 static p_rx_msg_t 1470 nxge_allocb(size_t size, uint32_t pri, p_nxge_dma_common_t dmabuf_p) 1471 { 1472 p_rx_msg_t nxge_mp = NULL; 1473 p_nxge_dma_common_t dmamsg_p; 1474 uchar_t *buffer; 1475 1476 nxge_mp = KMEM_ZALLOC(sizeof (rx_msg_t), KM_NOSLEEP); 1477 if (nxge_mp == NULL) { 1478 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 1479 "Allocation of a rx msg failed.")); 1480 goto nxge_allocb_exit; 1481 } 1482 1483 nxge_mp->use_buf_pool = B_FALSE; 1484 if (dmabuf_p) { 1485 nxge_mp->use_buf_pool = B_TRUE; 1486 dmamsg_p = (p_nxge_dma_common_t)&nxge_mp->buf_dma; 1487 *dmamsg_p = *dmabuf_p; 1488 dmamsg_p->nblocks = 1; 1489 dmamsg_p->block_size = size; 1490 dmamsg_p->alength = size; 1491 buffer = (uchar_t *)dmabuf_p->kaddrp; 1492 1493 dmabuf_p->kaddrp = (void *) 1494 ((char *)dmabuf_p->kaddrp + size); 1495 dmabuf_p->ioaddr_pp = (void *) 1496 ((char *)dmabuf_p->ioaddr_pp + size); 1497 dmabuf_p->alength -= size; 1498 dmabuf_p->offset += size; 1499 dmabuf_p->dma_cookie.dmac_laddress += size; 1500 dmabuf_p->dma_cookie.dmac_size -= size; 1501 1502 } else { 1503 buffer = KMEM_ALLOC(size, KM_NOSLEEP); 1504 if (buffer == NULL) { 1505 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 1506 "Allocation of a receive page failed.")); 1507 goto nxge_allocb_fail1; 1508 } 1509 } 1510 1511 nxge_mp->rx_mblk_p = desballoc(buffer, size, pri, &nxge_mp->freeb); 1512 if (nxge_mp->rx_mblk_p == NULL) { 1513 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "desballoc failed.")); 1514 goto nxge_allocb_fail2; 1515 } 1516 1517 nxge_mp->buffer = buffer; 1518 nxge_mp->block_size = size; 1519 nxge_mp->freeb.free_func = (void (*)())nxge_freeb; 1520 nxge_mp->freeb.free_arg = (caddr_t)nxge_mp; 1521 nxge_mp->ref_cnt = 1; 1522 nxge_mp->free = B_TRUE; 1523 nxge_mp->rx_use_bcopy = B_FALSE; 1524 1525 atomic_inc_32(&nxge_mblks_pending); 1526 1527 goto nxge_allocb_exit; 1528 1529 nxge_allocb_fail2: 1530 if (!nxge_mp->use_buf_pool) { 1531 KMEM_FREE(buffer, size); 1532 } 1533 1534 nxge_allocb_fail1: 1535 KMEM_FREE(nxge_mp, sizeof (rx_msg_t)); 1536 nxge_mp = NULL; 1537 1538 nxge_allocb_exit: 1539 return (nxge_mp); 1540 } 1541 1542 p_mblk_t 1543 nxge_dupb(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 1544 { 1545 p_mblk_t mp; 1546 1547 NXGE_DEBUG_MSG((NULL, MEM_CTL, "==> nxge_dupb")); 1548 NXGE_DEBUG_MSG((NULL, MEM_CTL, "nxge_mp = $%p " 1549 "offset = 0x%08X " 1550 "size = 0x%08X", 1551 nxge_mp, offset, size)); 1552 1553 mp = desballoc(&nxge_mp->buffer[offset], size, 1554 0, &nxge_mp->freeb); 1555 if (mp == NULL) { 1556 NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 1557 goto nxge_dupb_exit; 1558 } 1559 atomic_inc_32(&nxge_mp->ref_cnt); 1560 atomic_inc_32(&nxge_mblks_pending); 1561 1562 1563 nxge_dupb_exit: 1564 NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 1565 nxge_mp)); 1566 return (mp); 1567 } 1568 1569 p_mblk_t 1570 nxge_dupb_bcopy(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 1571 { 1572 p_mblk_t mp; 1573 uchar_t *dp; 1574 1575 mp = allocb(size + NXGE_RXBUF_EXTRA, 0); 1576 if (mp == NULL) { 1577 NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 1578 goto nxge_dupb_bcopy_exit; 1579 } 1580 dp = mp->b_rptr = mp->b_rptr + NXGE_RXBUF_EXTRA; 1581 bcopy((void *)&nxge_mp->buffer[offset], dp, size); 1582 mp->b_wptr = dp + size; 1583 1584 nxge_dupb_bcopy_exit: 1585 NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 1586 nxge_mp)); 1587 return (mp); 1588 } 1589 1590 void nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, 1591 p_rx_msg_t rx_msg_p); 1592 1593 void 1594 nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p) 1595 { 1596 1597 npi_handle_t handle; 1598 1599 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_post_page")); 1600 1601 /* Reuse this buffer */ 1602 rx_msg_p->free = B_FALSE; 1603 rx_msg_p->cur_usage_cnt = 0; 1604 rx_msg_p->max_usage_cnt = 0; 1605 rx_msg_p->pkt_buf_size = 0; 1606 1607 if (rx_rbr_p->rbr_use_bcopy) { 1608 rx_msg_p->rx_use_bcopy = B_FALSE; 1609 atomic_dec_32(&rx_rbr_p->rbr_consumed); 1610 } 1611 1612 /* 1613 * Get the rbr header pointer and its offset index. 1614 */ 1615 MUTEX_ENTER(&rx_rbr_p->post_lock); 1616 1617 1618 rx_rbr_p->rbr_wr_index = ((rx_rbr_p->rbr_wr_index + 1) & 1619 rx_rbr_p->rbr_wrap_mask); 1620 rx_rbr_p->rbr_desc_vp[rx_rbr_p->rbr_wr_index] = rx_msg_p->shifted_addr; 1621 MUTEX_EXIT(&rx_rbr_p->post_lock); 1622 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1623 npi_rxdma_rdc_rbr_kick(handle, rx_rbr_p->rdc, 1); 1624 1625 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1626 "<== nxge_post_page (channel %d post_next_index %d)", 1627 rx_rbr_p->rdc, rx_rbr_p->rbr_wr_index)); 1628 1629 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_post_page")); 1630 } 1631 1632 void 1633 nxge_freeb(p_rx_msg_t rx_msg_p) 1634 { 1635 size_t size; 1636 uchar_t *buffer = NULL; 1637 int ref_cnt; 1638 boolean_t free_state = B_FALSE; 1639 1640 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "==> nxge_freeb")); 1641 NXGE_DEBUG_MSG((NULL, MEM2_CTL, 1642 "nxge_freeb:rx_msg_p = $%p (block pending %d)", 1643 rx_msg_p, nxge_mblks_pending)); 1644 1645 atomic_dec_32(&nxge_mblks_pending); 1646 /* 1647 * First we need to get the free state, then 1648 * atomic decrement the reference count to prevent 1649 * the race condition with the interrupt thread that 1650 * is processing a loaned up buffer block. 1651 */ 1652 free_state = rx_msg_p->free; 1653 ref_cnt = atomic_add_32_nv(&rx_msg_p->ref_cnt, -1); 1654 if (!ref_cnt) { 1655 buffer = rx_msg_p->buffer; 1656 size = rx_msg_p->block_size; 1657 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "nxge_freeb: " 1658 "will free: rx_msg_p = $%p (block pending %d)", 1659 rx_msg_p, nxge_mblks_pending)); 1660 1661 if (!rx_msg_p->use_buf_pool) { 1662 KMEM_FREE(buffer, size); 1663 } 1664 1665 KMEM_FREE(rx_msg_p, sizeof (rx_msg_t)); 1666 return; 1667 } 1668 1669 /* 1670 * Repost buffer. 1671 */ 1672 if (free_state && (ref_cnt == 1)) { 1673 NXGE_DEBUG_MSG((NULL, RX_CTL, 1674 "nxge_freeb: post page $%p:", rx_msg_p)); 1675 nxge_post_page(rx_msg_p->nxgep, rx_msg_p->rx_rbr_p, 1676 rx_msg_p); 1677 } 1678 1679 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "<== nxge_freeb")); 1680 } 1681 1682 uint_t 1683 nxge_rx_intr(void *arg1, void *arg2) 1684 { 1685 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 1686 p_nxge_t nxgep = (p_nxge_t)arg2; 1687 p_nxge_ldg_t ldgp; 1688 uint8_t channel; 1689 npi_handle_t handle; 1690 rx_dma_ctl_stat_t cs; 1691 1692 #ifdef NXGE_DEBUG 1693 rxdma_cfig1_t cfg; 1694 #endif 1695 uint_t serviced = DDI_INTR_UNCLAIMED; 1696 1697 if (ldvp == NULL) { 1698 NXGE_DEBUG_MSG((NULL, INT_CTL, 1699 "<== nxge_rx_intr: arg2 $%p arg1 $%p", 1700 nxgep, ldvp)); 1701 1702 return (DDI_INTR_CLAIMED); 1703 } 1704 1705 if (arg2 == NULL || (void *)ldvp->nxgep != arg2) { 1706 nxgep = ldvp->nxgep; 1707 } 1708 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1709 "==> nxge_rx_intr: arg2 $%p arg1 $%p", 1710 nxgep, ldvp)); 1711 1712 /* 1713 * This interrupt handler is for a specific 1714 * receive dma channel. 1715 */ 1716 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1717 /* 1718 * Get the control and status for this channel. 1719 */ 1720 channel = ldvp->channel; 1721 ldgp = ldvp->ldgp; 1722 RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel, &cs.value); 1723 1724 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_intr:channel %d " 1725 "cs 0x%016llx rcrto 0x%x rcrthres %x", 1726 channel, 1727 cs.value, 1728 cs.bits.hdw.rcrto, 1729 cs.bits.hdw.rcrthres)); 1730 1731 nxge_rx_pkts_vring(nxgep, ldvp->vdma_index, ldvp, cs); 1732 serviced = DDI_INTR_CLAIMED; 1733 1734 /* error events. */ 1735 if (cs.value & RX_DMA_CTL_STAT_ERROR) { 1736 (void) nxge_rx_err_evnts(nxgep, ldvp->vdma_index, ldvp, cs); 1737 } 1738 1739 nxge_intr_exit: 1740 1741 1742 /* 1743 * Enable the mailbox update interrupt if we want 1744 * to use mailbox. We probably don't need to use 1745 * mailbox as it only saves us one pio read. 1746 * Also write 1 to rcrthres and rcrto to clear 1747 * these two edge triggered bits. 1748 */ 1749 1750 cs.value &= RX_DMA_CTL_STAT_WR1C; 1751 cs.bits.hdw.mex = 1; 1752 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, 1753 cs.value); 1754 1755 /* 1756 * Rearm this logical group if this is a single device 1757 * group. 1758 */ 1759 if (ldgp->nldvs == 1) { 1760 ldgimgm_t mgm; 1761 mgm.value = 0; 1762 mgm.bits.ldw.arm = 1; 1763 mgm.bits.ldw.timer = ldgp->ldg_timer; 1764 NXGE_REG_WR64(handle, 1765 LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg), 1766 mgm.value); 1767 } 1768 1769 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_intr: serviced %d", 1770 serviced)); 1771 return (serviced); 1772 } 1773 1774 /* 1775 * Process the packets received in the specified logical device 1776 * and pass up a chain of message blocks to the upper layer. 1777 */ 1778 static void 1779 nxge_rx_pkts_vring(p_nxge_t nxgep, uint_t vindex, p_nxge_ldv_t ldvp, 1780 rx_dma_ctl_stat_t cs) 1781 { 1782 p_mblk_t mp; 1783 p_rx_rcr_ring_t rcrp; 1784 1785 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts_vring")); 1786 if ((mp = nxge_rx_pkts(nxgep, vindex, ldvp, &rcrp, cs)) == NULL) { 1787 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1788 "<== nxge_rx_pkts_vring: no mp")); 1789 return; 1790 } 1791 1792 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts_vring: $%p", 1793 mp)); 1794 1795 #ifdef NXGE_DEBUG 1796 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1797 "==> nxge_rx_pkts_vring:calling mac_rx " 1798 "LEN %d mp $%p mp->b_cont $%p mp->b_next $%p rcrp $%p " 1799 "mac_handle $%p", 1800 mp->b_wptr - mp->b_rptr, 1801 mp, mp->b_cont, mp->b_next, 1802 rcrp, rcrp->rcr_mac_handle)); 1803 1804 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1805 "==> nxge_rx_pkts_vring: dump packets " 1806 "(mp $%p b_rptr $%p b_wptr $%p):\n %s", 1807 mp, 1808 mp->b_rptr, 1809 mp->b_wptr, 1810 nxge_dump_packet((char *)mp->b_rptr, 1811 mp->b_wptr - mp->b_rptr))); 1812 if (mp->b_cont) { 1813 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1814 "==> nxge_rx_pkts_vring: dump b_cont packets " 1815 "(mp->b_cont $%p b_rptr $%p b_wptr $%p):\n %s", 1816 mp->b_cont, 1817 mp->b_cont->b_rptr, 1818 mp->b_cont->b_wptr, 1819 nxge_dump_packet((char *)mp->b_cont->b_rptr, 1820 mp->b_cont->b_wptr - mp->b_cont->b_rptr))); 1821 } 1822 if (mp->b_next) { 1823 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1824 "==> nxge_rx_pkts_vring: dump next packets " 1825 "(b_rptr $%p): %s", 1826 mp->b_next->b_rptr, 1827 nxge_dump_packet((char *)mp->b_next->b_rptr, 1828 mp->b_next->b_wptr - mp->b_next->b_rptr))); 1829 } 1830 #endif 1831 1832 mac_rx(nxgep->mach, rcrp->rcr_mac_handle, mp); 1833 } 1834 1835 1836 /* 1837 * This routine is the main packet receive processing function. 1838 * It gets the packet type, error code, and buffer related 1839 * information from the receive completion entry. 1840 * How many completion entries to process is based on the number of packets 1841 * queued by the hardware, a hardware maintained tail pointer 1842 * and a configurable receive packet count. 1843 * 1844 * A chain of message blocks will be created as result of processing 1845 * the completion entries. This chain of message blocks will be returned and 1846 * a hardware control status register will be updated with the number of 1847 * packets were removed from the hardware queue. 1848 * 1849 */ 1850 mblk_t * 1851 nxge_rx_pkts(p_nxge_t nxgep, uint_t vindex, p_nxge_ldv_t ldvp, 1852 p_rx_rcr_ring_t *rcrp, rx_dma_ctl_stat_t cs) 1853 { 1854 npi_handle_t handle; 1855 uint8_t channel; 1856 p_rx_rcr_rings_t rx_rcr_rings; 1857 p_rx_rcr_ring_t rcr_p; 1858 uint32_t comp_rd_index; 1859 p_rcr_entry_t rcr_desc_rd_head_p; 1860 p_rcr_entry_t rcr_desc_rd_head_pp; 1861 p_mblk_t nmp, mp_cont, head_mp, *tail_mp; 1862 uint16_t qlen, nrcr_read, npkt_read; 1863 uint32_t qlen_hw; 1864 boolean_t multi; 1865 rcrcfig_b_t rcr_cfg_b; 1866 #if defined(_BIG_ENDIAN) 1867 npi_status_t rs = NPI_SUCCESS; 1868 #endif 1869 1870 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:vindex %d " 1871 "channel %d", vindex, ldvp->channel)); 1872 1873 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1874 return (NULL); 1875 } 1876 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1877 rx_rcr_rings = nxgep->rx_rcr_rings; 1878 rcr_p = rx_rcr_rings->rcr_rings[vindex]; 1879 channel = rcr_p->rdc; 1880 if (channel != ldvp->channel) { 1881 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:index %d " 1882 "channel %d, and rcr channel %d not matched.", 1883 vindex, ldvp->channel, channel)); 1884 return (NULL); 1885 } 1886 1887 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1888 "==> nxge_rx_pkts: START: rcr channel %d " 1889 "head_p $%p head_pp $%p index %d ", 1890 channel, rcr_p->rcr_desc_rd_head_p, 1891 rcr_p->rcr_desc_rd_head_pp, 1892 rcr_p->comp_rd_index)); 1893 1894 1895 #if !defined(_BIG_ENDIAN) 1896 qlen = RXDMA_REG_READ32(handle, RCRSTAT_A_REG, channel) & 0xffff; 1897 #else 1898 rs = npi_rxdma_rdc_rcr_qlen_get(handle, channel, &qlen); 1899 if (rs != NPI_SUCCESS) { 1900 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:index %d " 1901 "channel %d, get qlen failed 0x%08x", 1902 vindex, ldvp->channel, rs)); 1903 return (NULL); 1904 } 1905 #endif 1906 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:rcr channel %d " 1907 "qlen %d", channel, qlen)); 1908 1909 1910 1911 if (!qlen) { 1912 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1913 "==> nxge_rx_pkts:rcr channel %d " 1914 "qlen %d (no pkts)", channel, qlen)); 1915 1916 return (NULL); 1917 } 1918 1919 comp_rd_index = rcr_p->comp_rd_index; 1920 1921 rcr_desc_rd_head_p = rcr_p->rcr_desc_rd_head_p; 1922 rcr_desc_rd_head_pp = rcr_p->rcr_desc_rd_head_pp; 1923 nrcr_read = npkt_read = 0; 1924 1925 /* 1926 * Number of packets queued 1927 * (The jumbo or multi packet will be counted as only one 1928 * packets and it may take up more than one completion entry). 1929 */ 1930 qlen_hw = (qlen < nxge_max_rx_pkts) ? 1931 qlen : nxge_max_rx_pkts; 1932 head_mp = NULL; 1933 tail_mp = &head_mp; 1934 nmp = mp_cont = NULL; 1935 multi = B_FALSE; 1936 1937 while (qlen_hw) { 1938 1939 #ifdef NXGE_DEBUG 1940 nxge_dump_rcr_entry(nxgep, rcr_desc_rd_head_p); 1941 #endif 1942 /* 1943 * Process one completion ring entry. 1944 */ 1945 nxge_receive_packet(nxgep, 1946 rcr_p, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont); 1947 1948 /* 1949 * message chaining modes 1950 */ 1951 if (nmp) { 1952 nmp->b_next = NULL; 1953 if (!multi && !mp_cont) { /* frame fits a partition */ 1954 *tail_mp = nmp; 1955 tail_mp = &nmp->b_next; 1956 nmp = NULL; 1957 } else if (multi && !mp_cont) { /* first segment */ 1958 *tail_mp = nmp; 1959 tail_mp = &nmp->b_cont; 1960 } else if (multi && mp_cont) { /* mid of multi segs */ 1961 *tail_mp = mp_cont; 1962 tail_mp = &mp_cont->b_cont; 1963 } else if (!multi && mp_cont) { /* last segment */ 1964 *tail_mp = mp_cont; 1965 tail_mp = &nmp->b_next; 1966 nmp = NULL; 1967 } 1968 } 1969 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1970 "==> nxge_rx_pkts: loop: rcr channel %d " 1971 "before updating: multi %d " 1972 "nrcr_read %d " 1973 "npk read %d " 1974 "head_pp $%p index %d ", 1975 channel, 1976 multi, 1977 nrcr_read, npkt_read, rcr_desc_rd_head_pp, 1978 comp_rd_index)); 1979 1980 if (!multi) { 1981 qlen_hw--; 1982 npkt_read++; 1983 } 1984 1985 /* 1986 * Update the next read entry. 1987 */ 1988 comp_rd_index = NEXT_ENTRY(comp_rd_index, 1989 rcr_p->comp_wrap_mask); 1990 1991 rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p, 1992 rcr_p->rcr_desc_first_p, 1993 rcr_p->rcr_desc_last_p); 1994 1995 nrcr_read++; 1996 1997 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1998 "<== nxge_rx_pkts: (SAM, process one packet) " 1999 "nrcr_read %d", 2000 nrcr_read)); 2001 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2002 "==> nxge_rx_pkts: loop: rcr channel %d " 2003 "multi %d " 2004 "nrcr_read %d " 2005 "npk read %d " 2006 "head_pp $%p index %d ", 2007 channel, 2008 multi, 2009 nrcr_read, npkt_read, rcr_desc_rd_head_pp, 2010 comp_rd_index)); 2011 2012 } 2013 2014 rcr_p->rcr_desc_rd_head_pp = rcr_desc_rd_head_pp; 2015 rcr_p->comp_rd_index = comp_rd_index; 2016 rcr_p->rcr_desc_rd_head_p = rcr_desc_rd_head_p; 2017 2018 if ((nxgep->intr_timeout != rcr_p->intr_timeout) || 2019 (nxgep->intr_threshold != rcr_p->intr_threshold)) { 2020 rcr_p->intr_timeout = nxgep->intr_timeout; 2021 rcr_p->intr_threshold = nxgep->intr_threshold; 2022 rcr_cfg_b.value = 0x0ULL; 2023 if (rcr_p->intr_timeout) 2024 rcr_cfg_b.bits.ldw.entout = 1; 2025 rcr_cfg_b.bits.ldw.timeout = rcr_p->intr_timeout; 2026 rcr_cfg_b.bits.ldw.pthres = rcr_p->intr_threshold; 2027 RXDMA_REG_WRITE64(handle, RCRCFIG_B_REG, 2028 channel, rcr_cfg_b.value); 2029 } 2030 2031 cs.bits.ldw.pktread = npkt_read; 2032 cs.bits.ldw.ptrread = nrcr_read; 2033 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, 2034 channel, cs.value); 2035 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2036 "==> nxge_rx_pkts: EXIT: rcr channel %d " 2037 "head_pp $%p index %016llx ", 2038 channel, 2039 rcr_p->rcr_desc_rd_head_pp, 2040 rcr_p->comp_rd_index)); 2041 /* 2042 * Update RCR buffer pointer read and number of packets 2043 * read. 2044 */ 2045 2046 *rcrp = rcr_p; 2047 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_pkts")); 2048 return (head_mp); 2049 } 2050 2051 void 2052 nxge_receive_packet(p_nxge_t nxgep, 2053 p_rx_rcr_ring_t rcr_p, p_rcr_entry_t rcr_desc_rd_head_p, 2054 boolean_t *multi_p, mblk_t **mp, mblk_t **mp_cont) 2055 { 2056 p_mblk_t nmp = NULL; 2057 uint64_t multi; 2058 uint64_t dcf_err; 2059 uint8_t channel; 2060 2061 boolean_t first_entry = B_TRUE; 2062 boolean_t is_tcp_udp = B_FALSE; 2063 boolean_t buffer_free = B_FALSE; 2064 boolean_t error_send_up = B_FALSE; 2065 uint8_t error_type; 2066 uint16_t l2_len; 2067 uint16_t skip_len; 2068 uint8_t pktbufsz_type; 2069 uint16_t pktbufsz; 2070 uint64_t rcr_entry; 2071 uint64_t *pkt_buf_addr_pp; 2072 uint64_t *pkt_buf_addr_p; 2073 uint32_t buf_offset; 2074 uint32_t bsize; 2075 uint32_t error_disp_cnt; 2076 uint32_t msg_index; 2077 p_rx_rbr_ring_t rx_rbr_p; 2078 p_rx_msg_t *rx_msg_ring_p; 2079 p_rx_msg_t rx_msg_p; 2080 uint16_t sw_offset_bytes = 0, hdr_size = 0; 2081 nxge_status_t status = NXGE_OK; 2082 boolean_t is_valid = B_FALSE; 2083 p_nxge_rx_ring_stats_t rdc_stats; 2084 uint32_t bytes_read; 2085 uint64_t pkt_type; 2086 uint64_t frag; 2087 #ifdef NXGE_DEBUG 2088 int dump_len; 2089 #endif 2090 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_receive_packet")); 2091 first_entry = (*mp == NULL) ? B_TRUE : B_FALSE; 2092 2093 rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); 2094 2095 multi = (rcr_entry & RCR_MULTI_MASK); 2096 dcf_err = (rcr_entry & RCR_DCF_ERROR_MASK); 2097 pkt_type = (rcr_entry & RCR_PKT_TYPE_MASK); 2098 2099 error_type = ((rcr_entry & RCR_ERROR_MASK) >> RCR_ERROR_SHIFT); 2100 frag = (rcr_entry & RCR_FRAG_MASK); 2101 2102 l2_len = ((rcr_entry & RCR_L2_LEN_MASK) >> RCR_L2_LEN_SHIFT); 2103 2104 pktbufsz_type = ((rcr_entry & RCR_PKTBUFSZ_MASK) >> 2105 RCR_PKTBUFSZ_SHIFT); 2106 2107 pkt_buf_addr_pp = (uint64_t *)((rcr_entry & RCR_PKT_BUF_ADDR_MASK) << 2108 RCR_PKT_BUF_ADDR_SHIFT); 2109 2110 channel = rcr_p->rdc; 2111 2112 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2113 "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 2114 "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 2115 "error_type 0x%x pkt_type 0x%x " 2116 "pktbufsz_type %d ", 2117 rcr_desc_rd_head_p, 2118 rcr_entry, pkt_buf_addr_pp, l2_len, 2119 multi, 2120 error_type, 2121 pkt_type, 2122 pktbufsz_type)); 2123 2124 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2125 "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 2126 "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 2127 "error_type 0x%x pkt_type 0x%x ", rcr_desc_rd_head_p, 2128 rcr_entry, pkt_buf_addr_pp, l2_len, 2129 multi, 2130 error_type, 2131 pkt_type)); 2132 2133 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2134 "==> (rbr) nxge_receive_packet: entry 0x%0llx " 2135 "full pkt_buf_addr_pp $%p l2_len %d", 2136 rcr_entry, pkt_buf_addr_pp, l2_len)); 2137 2138 /* get the stats ptr */ 2139 rdc_stats = rcr_p->rdc_stats; 2140 2141 if (!l2_len) { 2142 2143 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2144 "<== nxge_receive_packet: failed: l2 length is 0.")); 2145 return; 2146 } 2147 2148 /* Hardware sends us 4 bytes of CRC as no stripping is done. */ 2149 l2_len -= ETHERFCSL; 2150 2151 /* shift 6 bits to get the full io address */ 2152 pkt_buf_addr_pp = (uint64_t *)((uint64_t)pkt_buf_addr_pp << 2153 RCR_PKT_BUF_ADDR_SHIFT_FULL); 2154 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2155 "==> (rbr) nxge_receive_packet: entry 0x%0llx " 2156 "full pkt_buf_addr_pp $%p l2_len %d", 2157 rcr_entry, pkt_buf_addr_pp, l2_len)); 2158 2159 rx_rbr_p = rcr_p->rx_rbr_p; 2160 rx_msg_ring_p = rx_rbr_p->rx_msg_ring; 2161 2162 if (first_entry) { 2163 hdr_size = (rcr_p->full_hdr_flag ? RXDMA_HDR_SIZE_FULL : 2164 RXDMA_HDR_SIZE_DEFAULT); 2165 2166 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2167 "==> nxge_receive_packet: first entry 0x%016llx " 2168 "pkt_buf_addr_pp $%p l2_len %d hdr %d", 2169 rcr_entry, pkt_buf_addr_pp, l2_len, 2170 hdr_size)); 2171 } 2172 2173 MUTEX_ENTER(&rcr_p->lock); 2174 MUTEX_ENTER(&rx_rbr_p->lock); 2175 2176 bytes_read = rcr_p->rcvd_pkt_bytes; 2177 2178 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2179 "==> (rbr 1) nxge_receive_packet: entry 0x%0llx " 2180 "full pkt_buf_addr_pp $%p l2_len %d", 2181 rcr_entry, pkt_buf_addr_pp, l2_len)); 2182 2183 /* 2184 * Packet buffer address in the completion entry points 2185 * to the starting buffer address (offset 0). 2186 * Use the starting buffer address to locate the corresponding 2187 * kernel address. 2188 */ 2189 status = nxge_rxbuf_pp_to_vp(nxgep, rx_rbr_p, 2190 pktbufsz_type, pkt_buf_addr_pp, &pkt_buf_addr_p, 2191 &buf_offset, 2192 &msg_index); 2193 2194 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2195 "==> (rbr 2) nxge_receive_packet: entry 0x%0llx " 2196 "full pkt_buf_addr_pp $%p l2_len %d", 2197 rcr_entry, pkt_buf_addr_pp, l2_len)); 2198 2199 if (status != NXGE_OK) { 2200 MUTEX_EXIT(&rx_rbr_p->lock); 2201 MUTEX_EXIT(&rcr_p->lock); 2202 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2203 "<== nxge_receive_packet: found vaddr failed %d", 2204 status)); 2205 return; 2206 } 2207 2208 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2209 "==> (rbr 3) nxge_receive_packet: entry 0x%0llx " 2210 "full pkt_buf_addr_pp $%p l2_len %d", 2211 rcr_entry, pkt_buf_addr_pp, l2_len)); 2212 2213 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2214 "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 2215 "full pkt_buf_addr_pp $%p l2_len %d", 2216 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 2217 2218 rx_msg_p = rx_msg_ring_p[msg_index]; 2219 2220 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2221 "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 2222 "full pkt_buf_addr_pp $%p l2_len %d", 2223 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 2224 2225 switch (pktbufsz_type) { 2226 case RCR_PKTBUFSZ_0: 2227 bsize = rx_rbr_p->pkt_buf_size0_bytes; 2228 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2229 "==> nxge_receive_packet: 0 buf %d", bsize)); 2230 break; 2231 case RCR_PKTBUFSZ_1: 2232 bsize = rx_rbr_p->pkt_buf_size1_bytes; 2233 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2234 "==> nxge_receive_packet: 1 buf %d", bsize)); 2235 break; 2236 case RCR_PKTBUFSZ_2: 2237 bsize = rx_rbr_p->pkt_buf_size2_bytes; 2238 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2239 "==> nxge_receive_packet: 2 buf %d", bsize)); 2240 break; 2241 case RCR_SINGLE_BLOCK: 2242 bsize = rx_msg_p->block_size; 2243 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2244 "==> nxge_receive_packet: single %d", bsize)); 2245 2246 break; 2247 default: 2248 MUTEX_EXIT(&rx_rbr_p->lock); 2249 MUTEX_EXIT(&rcr_p->lock); 2250 return; 2251 } 2252 2253 DMA_COMMON_SYNC_OFFSET(rx_msg_p->buf_dma, 2254 (buf_offset + sw_offset_bytes), 2255 (hdr_size + l2_len), 2256 DDI_DMA_SYNC_FORCPU); 2257 2258 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2259 "==> nxge_receive_packet: after first dump:usage count")); 2260 2261 if (rx_msg_p->cur_usage_cnt == 0) { 2262 if (rx_rbr_p->rbr_use_bcopy) { 2263 atomic_inc_32(&rx_rbr_p->rbr_consumed); 2264 if (rx_rbr_p->rbr_consumed < 2265 rx_rbr_p->rbr_threshold_hi) { 2266 if (rx_rbr_p->rbr_threshold_lo == 0 || 2267 ((rx_rbr_p->rbr_consumed >= 2268 rx_rbr_p->rbr_threshold_lo) && 2269 (rx_rbr_p->rbr_bufsize_type >= 2270 pktbufsz_type))) { 2271 rx_msg_p->rx_use_bcopy = B_TRUE; 2272 } 2273 } else { 2274 rx_msg_p->rx_use_bcopy = B_TRUE; 2275 } 2276 } 2277 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2278 "==> nxge_receive_packet: buf %d (new block) ", 2279 bsize)); 2280 2281 rx_msg_p->pkt_buf_size_code = pktbufsz_type; 2282 rx_msg_p->pkt_buf_size = bsize; 2283 rx_msg_p->cur_usage_cnt = 1; 2284 if (pktbufsz_type == RCR_SINGLE_BLOCK) { 2285 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2286 "==> nxge_receive_packet: buf %d " 2287 "(single block) ", 2288 bsize)); 2289 /* 2290 * Buffer can be reused once the free function 2291 * is called. 2292 */ 2293 rx_msg_p->max_usage_cnt = 1; 2294 buffer_free = B_TRUE; 2295 } else { 2296 rx_msg_p->max_usage_cnt = rx_msg_p->block_size/bsize; 2297 if (rx_msg_p->max_usage_cnt == 1) { 2298 buffer_free = B_TRUE; 2299 } 2300 } 2301 } else { 2302 rx_msg_p->cur_usage_cnt++; 2303 if (rx_msg_p->cur_usage_cnt == rx_msg_p->max_usage_cnt) { 2304 buffer_free = B_TRUE; 2305 } 2306 } 2307 2308 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2309 "msgbuf index = %d l2len %d bytes usage %d max_usage %d ", 2310 msg_index, l2_len, 2311 rx_msg_p->cur_usage_cnt, rx_msg_p->max_usage_cnt)); 2312 2313 if ((error_type) || (dcf_err)) { 2314 rdc_stats->ierrors++; 2315 if (dcf_err) { 2316 rdc_stats->dcf_err++; 2317 #ifdef NXGE_DEBUG 2318 if (!rdc_stats->dcf_err) { 2319 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2320 "nxge_receive_packet: channel %d dcf_err rcr" 2321 " 0x%llx", channel, rcr_entry)); 2322 } 2323 #endif 2324 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 2325 NXGE_FM_EREPORT_RDMC_DCF_ERR); 2326 } else { 2327 /* Update error stats */ 2328 error_disp_cnt = NXGE_ERROR_SHOW_MAX; 2329 rdc_stats->errlog.compl_err_type = error_type; 2330 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 2331 NXGE_FM_EREPORT_RDMC_COMPLETION_ERR); 2332 2333 switch (error_type) { 2334 case RCR_L2_ERROR: 2335 rdc_stats->l2_err++; 2336 if (rdc_stats->l2_err < 2337 error_disp_cnt) 2338 NXGE_ERROR_MSG((nxgep, 2339 NXGE_ERR_CTL, 2340 " nxge_receive_packet:" 2341 " channel %d RCR L2_ERROR", 2342 channel)); 2343 break; 2344 case RCR_L4_CSUM_ERROR: 2345 error_send_up = B_TRUE; 2346 rdc_stats->l4_cksum_err++; 2347 if (rdc_stats->l4_cksum_err < 2348 error_disp_cnt) 2349 NXGE_ERROR_MSG((nxgep, 2350 NXGE_ERR_CTL, 2351 " nxge_receive_packet:" 2352 " channel %d" 2353 " RCR L4_CSUM_ERROR", 2354 channel)); 2355 break; 2356 case RCR_FFLP_SOFT_ERROR: 2357 error_send_up = B_TRUE; 2358 rdc_stats->fflp_soft_err++; 2359 if (rdc_stats->fflp_soft_err < 2360 error_disp_cnt) 2361 NXGE_ERROR_MSG((nxgep, 2362 NXGE_ERR_CTL, 2363 " nxge_receive_packet:" 2364 " channel %d" 2365 " RCR FFLP_SOFT_ERROR", 2366 channel)); 2367 break; 2368 case RCR_ZCP_SOFT_ERROR: 2369 error_send_up = B_TRUE; 2370 rdc_stats->fflp_soft_err++; 2371 if (rdc_stats->zcp_soft_err < 2372 error_disp_cnt) 2373 NXGE_ERROR_MSG((nxgep, 2374 NXGE_ERR_CTL, 2375 " nxge_receive_packet:" 2376 " Channel %d" 2377 " RCR ZCP_SOFT_ERROR", 2378 channel)); 2379 break; 2380 default: 2381 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2382 " nxge_receive_packet:" 2383 " Channel %d" 2384 " RCR entry 0x%llx" 2385 " error 0x%x", 2386 rcr_entry, channel, 2387 error_type)); 2388 break; 2389 } 2390 } 2391 2392 /* 2393 * Update and repost buffer block if max usage 2394 * count is reached. 2395 */ 2396 if (error_send_up == B_FALSE) { 2397 atomic_inc_32(&rx_msg_p->ref_cnt); 2398 atomic_inc_32(&nxge_mblks_pending); 2399 if (buffer_free == B_TRUE) { 2400 rx_msg_p->free = B_TRUE; 2401 } 2402 2403 MUTEX_EXIT(&rx_rbr_p->lock); 2404 MUTEX_EXIT(&rcr_p->lock); 2405 nxge_freeb(rx_msg_p); 2406 return; 2407 } 2408 } 2409 2410 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2411 "==> nxge_receive_packet: DMA sync second ")); 2412 2413 skip_len = sw_offset_bytes + hdr_size; 2414 if (!rx_msg_p->rx_use_bcopy) { 2415 /* 2416 * For loaned up buffers, the driver reference count 2417 * will be incremented first and then the free state. 2418 */ 2419 nmp = nxge_dupb(rx_msg_p, buf_offset, bsize); 2420 } else { 2421 nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset + skip_len, l2_len); 2422 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2423 "==> nxge_receive_packet: use bcopy " 2424 "rbr consumed %d " 2425 "pktbufsz_type %d " 2426 "offset %d " 2427 "hdr_size %d l2_len %d " 2428 "nmp->b_rptr $%p", 2429 rx_rbr_p->rbr_consumed, 2430 pktbufsz_type, 2431 buf_offset, hdr_size, l2_len, 2432 nmp->b_rptr)); 2433 } 2434 if (nmp != NULL) { 2435 pktbufsz = nxge_get_pktbuf_size(nxgep, pktbufsz_type, 2436 rx_rbr_p->rbr_cfgb); 2437 if (!rx_msg_p->rx_use_bcopy) { 2438 if (first_entry) { 2439 bytes_read = 0; 2440 nmp->b_rptr = &nmp->b_rptr[skip_len]; 2441 if (l2_len > pktbufsz - skip_len) 2442 nmp->b_wptr = &nmp->b_rptr[pktbufsz 2443 - skip_len]; 2444 else 2445 nmp->b_wptr = &nmp->b_rptr[l2_len]; 2446 } else { 2447 if (l2_len - bytes_read > pktbufsz) 2448 nmp->b_wptr = &nmp->b_rptr[pktbufsz]; 2449 else 2450 nmp->b_wptr = 2451 &nmp->b_rptr[l2_len - bytes_read]; 2452 } 2453 bytes_read += nmp->b_wptr - nmp->b_rptr; 2454 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2455 "==> nxge_receive_packet after dupb: " 2456 "rbr consumed %d " 2457 "pktbufsz_type %d " 2458 "nmp $%p rptr $%p wptr $%p " 2459 "buf_offset %d bzise %d l2_len %d skip_len %d", 2460 rx_rbr_p->rbr_consumed, 2461 pktbufsz_type, 2462 nmp, nmp->b_rptr, nmp->b_wptr, 2463 buf_offset, bsize, l2_len, skip_len)); 2464 } 2465 } else { 2466 cmn_err(CE_WARN, "!nxge_receive_packet: " 2467 "update stats (error)"); 2468 } 2469 if (buffer_free == B_TRUE) { 2470 rx_msg_p->free = B_TRUE; 2471 } 2472 2473 /* 2474 * ERROR, FRAG and PKT_TYPE are only reported 2475 * in the first entry. 2476 * If a packet is not fragmented and no error bit is set, then 2477 * L4 checksum is OK. 2478 */ 2479 is_valid = (nmp != NULL); 2480 rdc_stats->ibytes += l2_len; 2481 rdc_stats->ipackets++; 2482 MUTEX_EXIT(&rx_rbr_p->lock); 2483 MUTEX_EXIT(&rcr_p->lock); 2484 2485 if (rx_msg_p->free && rx_msg_p->rx_use_bcopy) { 2486 atomic_inc_32(&rx_msg_p->ref_cnt); 2487 atomic_inc_32(&nxge_mblks_pending); 2488 nxge_freeb(rx_msg_p); 2489 } 2490 2491 if (is_valid) { 2492 nmp->b_cont = NULL; 2493 if (first_entry) { 2494 *mp = nmp; 2495 *mp_cont = NULL; 2496 } else 2497 *mp_cont = nmp; 2498 } 2499 2500 /* 2501 * Update stats and hardware checksuming. 2502 */ 2503 if (is_valid && !multi) { 2504 2505 is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP || 2506 pkt_type == RCR_PKT_IS_UDP) ? 2507 B_TRUE: B_FALSE); 2508 2509 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_receive_packet: " 2510 "is_valid 0x%x multi 0x%llx pkt %d frag %d error %d", 2511 is_valid, multi, is_tcp_udp, frag, error_type)); 2512 2513 if (is_tcp_udp && !frag && !error_type) { 2514 (void) hcksum_assoc(nmp, NULL, NULL, 0, 0, 0, 0, 2515 HCK_FULLCKSUM_OK | HCK_FULLCKSUM, 0); 2516 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2517 "==> nxge_receive_packet: Full tcp/udp cksum " 2518 "is_valid 0x%x multi 0x%llx pkt %d frag %d " 2519 "error %d", 2520 is_valid, multi, is_tcp_udp, frag, error_type)); 2521 } 2522 } 2523 2524 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2525 "==> nxge_receive_packet: *mp 0x%016llx", *mp)); 2526 2527 *multi_p = (multi == RCR_MULTI_MASK); 2528 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_receive_packet: " 2529 "multi %d nmp 0x%016llx *mp 0x%016llx *mp_cont 0x%016llx", 2530 *multi_p, nmp, *mp, *mp_cont)); 2531 } 2532 2533 /*ARGSUSED*/ 2534 static nxge_status_t 2535 nxge_rx_err_evnts(p_nxge_t nxgep, uint_t index, p_nxge_ldv_t ldvp, 2536 rx_dma_ctl_stat_t cs) 2537 { 2538 p_nxge_rx_ring_stats_t rdc_stats; 2539 npi_handle_t handle; 2540 npi_status_t rs; 2541 boolean_t rxchan_fatal = B_FALSE; 2542 boolean_t rxport_fatal = B_FALSE; 2543 uint8_t channel; 2544 uint8_t portn; 2545 nxge_status_t status = NXGE_OK; 2546 uint32_t error_disp_cnt = NXGE_ERROR_SHOW_MAX; 2547 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_err_evnts")); 2548 2549 handle = NXGE_DEV_NPI_HANDLE(nxgep); 2550 channel = ldvp->channel; 2551 portn = nxgep->mac.portnum; 2552 rdc_stats = &nxgep->statsp->rdc_stats[ldvp->vdma_index]; 2553 2554 if (cs.bits.hdw.rbr_tmout) { 2555 rdc_stats->rx_rbr_tmout++; 2556 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2557 NXGE_FM_EREPORT_RDMC_RBR_TMOUT); 2558 rxchan_fatal = B_TRUE; 2559 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2560 "==> nxge_rx_err_evnts: rx_rbr_timeout")); 2561 } 2562 if (cs.bits.hdw.rsp_cnt_err) { 2563 rdc_stats->rsp_cnt_err++; 2564 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2565 NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR); 2566 rxchan_fatal = B_TRUE; 2567 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2568 "==> nxge_rx_err_evnts(channel %d): " 2569 "rsp_cnt_err", channel)); 2570 } 2571 if (cs.bits.hdw.byte_en_bus) { 2572 rdc_stats->byte_en_bus++; 2573 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2574 NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS); 2575 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2576 "==> nxge_rx_err_evnts(channel %d): " 2577 "fatal error: byte_en_bus", channel)); 2578 rxchan_fatal = B_TRUE; 2579 } 2580 if (cs.bits.hdw.rsp_dat_err) { 2581 rdc_stats->rsp_dat_err++; 2582 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2583 NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR); 2584 rxchan_fatal = B_TRUE; 2585 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2586 "==> nxge_rx_err_evnts(channel %d): " 2587 "fatal error: rsp_dat_err", channel)); 2588 } 2589 if (cs.bits.hdw.rcr_ack_err) { 2590 rdc_stats->rcr_ack_err++; 2591 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2592 NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR); 2593 rxchan_fatal = B_TRUE; 2594 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2595 "==> nxge_rx_err_evnts(channel %d): " 2596 "fatal error: rcr_ack_err", channel)); 2597 } 2598 if (cs.bits.hdw.dc_fifo_err) { 2599 rdc_stats->dc_fifo_err++; 2600 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2601 NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR); 2602 /* This is not a fatal error! */ 2603 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2604 "==> nxge_rx_err_evnts(channel %d): " 2605 "dc_fifo_err", channel)); 2606 rxport_fatal = B_TRUE; 2607 } 2608 if ((cs.bits.hdw.rcr_sha_par) || (cs.bits.hdw.rbr_pre_par)) { 2609 if ((rs = npi_rxdma_ring_perr_stat_get(handle, 2610 &rdc_stats->errlog.pre_par, 2611 &rdc_stats->errlog.sha_par)) 2612 != NPI_SUCCESS) { 2613 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2614 "==> nxge_rx_err_evnts(channel %d): " 2615 "rcr_sha_par: get perr", channel)); 2616 return (NXGE_ERROR | rs); 2617 } 2618 if (cs.bits.hdw.rcr_sha_par) { 2619 rdc_stats->rcr_sha_par++; 2620 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2621 NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR); 2622 rxchan_fatal = B_TRUE; 2623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2624 "==> nxge_rx_err_evnts(channel %d): " 2625 "fatal error: rcr_sha_par", channel)); 2626 } 2627 if (cs.bits.hdw.rbr_pre_par) { 2628 rdc_stats->rbr_pre_par++; 2629 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2630 NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR); 2631 rxchan_fatal = B_TRUE; 2632 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2633 "==> nxge_rx_err_evnts(channel %d): " 2634 "fatal error: rbr_pre_par", channel)); 2635 } 2636 } 2637 if (cs.bits.hdw.port_drop_pkt) { 2638 rdc_stats->port_drop_pkt++; 2639 if (rdc_stats->port_drop_pkt < error_disp_cnt) 2640 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2641 "==> nxge_rx_err_evnts (channel %d): " 2642 "port_drop_pkt", channel)); 2643 } 2644 if (cs.bits.hdw.wred_drop) { 2645 rdc_stats->wred_drop++; 2646 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2647 "==> nxge_rx_err_evnts(channel %d): " 2648 "wred_drop", channel)); 2649 } 2650 if (cs.bits.hdw.rbr_pre_empty) { 2651 rdc_stats->rbr_pre_empty++; 2652 if (rdc_stats->rbr_pre_empty < error_disp_cnt) 2653 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2654 "==> nxge_rx_err_evnts(channel %d): " 2655 "rbr_pre_empty", channel)); 2656 } 2657 if (cs.bits.hdw.rcr_shadow_full) { 2658 rdc_stats->rcr_shadow_full++; 2659 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2660 "==> nxge_rx_err_evnts(channel %d): " 2661 "rcr_shadow_full", channel)); 2662 } 2663 if (cs.bits.hdw.config_err) { 2664 rdc_stats->config_err++; 2665 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2666 NXGE_FM_EREPORT_RDMC_CONFIG_ERR); 2667 rxchan_fatal = B_TRUE; 2668 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2669 "==> nxge_rx_err_evnts(channel %d): " 2670 "config error", channel)); 2671 } 2672 if (cs.bits.hdw.rcrincon) { 2673 rdc_stats->rcrincon++; 2674 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2675 NXGE_FM_EREPORT_RDMC_RCRINCON); 2676 rxchan_fatal = B_TRUE; 2677 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2678 "==> nxge_rx_err_evnts(channel %d): " 2679 "fatal error: rcrincon error", channel)); 2680 } 2681 if (cs.bits.hdw.rcrfull) { 2682 rdc_stats->rcrfull++; 2683 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2684 NXGE_FM_EREPORT_RDMC_RCRFULL); 2685 rxchan_fatal = B_TRUE; 2686 if (rdc_stats->rcrfull < error_disp_cnt) 2687 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2688 "==> nxge_rx_err_evnts(channel %d): " 2689 "fatal error: rcrfull error", channel)); 2690 } 2691 if (cs.bits.hdw.rbr_empty) { 2692 rdc_stats->rbr_empty++; 2693 if (rdc_stats->rbr_empty < error_disp_cnt) 2694 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2695 "==> nxge_rx_err_evnts(channel %d): " 2696 "rbr empty error", channel)); 2697 } 2698 if (cs.bits.hdw.rbrfull) { 2699 rdc_stats->rbrfull++; 2700 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2701 NXGE_FM_EREPORT_RDMC_RBRFULL); 2702 rxchan_fatal = B_TRUE; 2703 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2704 "==> nxge_rx_err_evnts(channel %d): " 2705 "fatal error: rbr_full error", channel)); 2706 } 2707 if (cs.bits.hdw.rbrlogpage) { 2708 rdc_stats->rbrlogpage++; 2709 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2710 NXGE_FM_EREPORT_RDMC_RBRLOGPAGE); 2711 rxchan_fatal = B_TRUE; 2712 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2713 "==> nxge_rx_err_evnts(channel %d): " 2714 "fatal error: rbr logical page error", channel)); 2715 } 2716 if (cs.bits.hdw.cfiglogpage) { 2717 rdc_stats->cfiglogpage++; 2718 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2719 NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE); 2720 rxchan_fatal = B_TRUE; 2721 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2722 "==> nxge_rx_err_evnts(channel %d): " 2723 "fatal error: cfig logical page error", channel)); 2724 } 2725 2726 if (rxport_fatal) { 2727 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2728 " nxge_rx_err_evnts: " 2729 " fatal error on Port #%d\n", 2730 portn)); 2731 status = nxge_ipp_fatal_err_recover(nxgep); 2732 if (status == NXGE_OK) { 2733 FM_SERVICE_RESTORED(nxgep); 2734 } 2735 } 2736 2737 if (rxchan_fatal) { 2738 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2739 " nxge_rx_err_evnts: " 2740 " fatal error on Channel #%d\n", 2741 channel)); 2742 status = nxge_rxdma_fatal_err_recover(nxgep, channel); 2743 if (status == NXGE_OK) { 2744 FM_SERVICE_RESTORED(nxgep); 2745 } 2746 } 2747 2748 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rx_err_evnts")); 2749 2750 return (status); 2751 } 2752 2753 static nxge_status_t 2754 nxge_map_rxdma(p_nxge_t nxgep) 2755 { 2756 int i, ndmas; 2757 uint16_t channel; 2758 p_rx_rbr_rings_t rx_rbr_rings; 2759 p_rx_rbr_ring_t *rbr_rings; 2760 p_rx_rcr_rings_t rx_rcr_rings; 2761 p_rx_rcr_ring_t *rcr_rings; 2762 p_rx_mbox_areas_t rx_mbox_areas_p; 2763 p_rx_mbox_t *rx_mbox_p; 2764 p_nxge_dma_pool_t dma_buf_poolp; 2765 p_nxge_dma_pool_t dma_cntl_poolp; 2766 p_nxge_dma_common_t *dma_buf_p; 2767 p_nxge_dma_common_t *dma_cntl_p; 2768 uint32_t *num_chunks; 2769 nxge_status_t status = NXGE_OK; 2770 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2771 p_nxge_dma_common_t t_dma_buf_p; 2772 p_nxge_dma_common_t t_dma_cntl_p; 2773 #endif 2774 2775 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma")); 2776 2777 dma_buf_poolp = nxgep->rx_buf_pool_p; 2778 dma_cntl_poolp = nxgep->rx_cntl_pool_p; 2779 2780 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 2781 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2782 "<== nxge_map_rxdma: buf not allocated")); 2783 return (NXGE_ERROR); 2784 } 2785 2786 ndmas = dma_buf_poolp->ndmas; 2787 if (!ndmas) { 2788 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2789 "<== nxge_map_rxdma: no dma allocated")); 2790 return (NXGE_ERROR); 2791 } 2792 2793 num_chunks = dma_buf_poolp->num_chunks; 2794 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2795 dma_cntl_p = dma_cntl_poolp->dma_buf_pool_p; 2796 2797 rx_rbr_rings = (p_rx_rbr_rings_t) 2798 KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2799 rbr_rings = (p_rx_rbr_ring_t *) 2800 KMEM_ZALLOC(sizeof (p_rx_rbr_ring_t) * ndmas, KM_SLEEP); 2801 rx_rcr_rings = (p_rx_rcr_rings_t) 2802 KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2803 rcr_rings = (p_rx_rcr_ring_t *) 2804 KMEM_ZALLOC(sizeof (p_rx_rcr_ring_t) * ndmas, KM_SLEEP); 2805 rx_mbox_areas_p = (p_rx_mbox_areas_t) 2806 KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2807 rx_mbox_p = (p_rx_mbox_t *) 2808 KMEM_ZALLOC(sizeof (p_rx_mbox_t) * ndmas, KM_SLEEP); 2809 2810 /* 2811 * Timeout should be set based on the system clock divider. 2812 * The following timeout value of 1 assumes that the 2813 * granularity (1000) is 3 microseconds running at 300MHz. 2814 */ 2815 2816 nxgep->intr_threshold = RXDMA_RCR_PTHRES_DEFAULT; 2817 nxgep->intr_timeout = RXDMA_RCR_TO_DEFAULT; 2818 2819 /* 2820 * Map descriptors from the buffer polls for each dam channel. 2821 */ 2822 for (i = 0; i < ndmas; i++) { 2823 /* 2824 * Set up and prepare buffer blocks, descriptors 2825 * and mailbox. 2826 */ 2827 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 2828 status = nxge_map_rxdma_channel(nxgep, channel, 2829 (p_nxge_dma_common_t *)&dma_buf_p[i], 2830 (p_rx_rbr_ring_t *)&rbr_rings[i], 2831 num_chunks[i], 2832 (p_nxge_dma_common_t *)&dma_cntl_p[i], 2833 (p_rx_rcr_ring_t *)&rcr_rings[i], 2834 (p_rx_mbox_t *)&rx_mbox_p[i]); 2835 if (status != NXGE_OK) { 2836 goto nxge_map_rxdma_fail1; 2837 } 2838 rbr_rings[i]->index = (uint16_t)i; 2839 rcr_rings[i]->index = (uint16_t)i; 2840 rcr_rings[i]->rdc_stats = &nxgep->statsp->rdc_stats[i]; 2841 2842 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2843 if (nxgep->niu_type == N2_NIU && NXGE_DMA_BLOCK == 1) { 2844 rbr_rings[i]->hv_set = B_FALSE; 2845 t_dma_buf_p = (p_nxge_dma_common_t)dma_buf_p[i]; 2846 t_dma_cntl_p = 2847 (p_nxge_dma_common_t)dma_cntl_p[i]; 2848 2849 rbr_rings[i]->hv_rx_buf_base_ioaddr_pp = 2850 (uint64_t)t_dma_buf_p->orig_ioaddr_pp; 2851 rbr_rings[i]->hv_rx_buf_ioaddr_size = 2852 (uint64_t)t_dma_buf_p->orig_alength; 2853 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2854 "==> nxge_map_rxdma_channel: " 2855 "channel %d " 2856 "data buf base io $%p ($%p) " 2857 "size 0x%llx (%d 0x%x)", 2858 channel, 2859 rbr_rings[i]->hv_rx_buf_base_ioaddr_pp, 2860 t_dma_cntl_p->ioaddr_pp, 2861 rbr_rings[i]->hv_rx_buf_ioaddr_size, 2862 t_dma_buf_p->orig_alength, 2863 t_dma_buf_p->orig_alength)); 2864 2865 rbr_rings[i]->hv_rx_cntl_base_ioaddr_pp = 2866 (uint64_t)t_dma_cntl_p->orig_ioaddr_pp; 2867 rbr_rings[i]->hv_rx_cntl_ioaddr_size = 2868 (uint64_t)t_dma_cntl_p->orig_alength; 2869 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2870 "==> nxge_map_rxdma_channel: " 2871 "channel %d " 2872 "cntl base io $%p ($%p) " 2873 "size 0x%llx (%d 0x%x)", 2874 channel, 2875 rbr_rings[i]->hv_rx_cntl_base_ioaddr_pp, 2876 t_dma_cntl_p->ioaddr_pp, 2877 rbr_rings[i]->hv_rx_cntl_ioaddr_size, 2878 t_dma_cntl_p->orig_alength, 2879 t_dma_cntl_p->orig_alength)); 2880 } 2881 2882 #endif /* sun4v and NIU_LP_WORKAROUND */ 2883 } 2884 2885 rx_rbr_rings->ndmas = rx_rcr_rings->ndmas = ndmas; 2886 rx_rbr_rings->rbr_rings = rbr_rings; 2887 nxgep->rx_rbr_rings = rx_rbr_rings; 2888 rx_rcr_rings->rcr_rings = rcr_rings; 2889 nxgep->rx_rcr_rings = rx_rcr_rings; 2890 2891 rx_mbox_areas_p->rxmbox_areas = rx_mbox_p; 2892 nxgep->rx_mbox_areas_p = rx_mbox_areas_p; 2893 2894 goto nxge_map_rxdma_exit; 2895 2896 nxge_map_rxdma_fail1: 2897 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2898 "==> nxge_map_rxdma: unmap rbr,rcr " 2899 "(status 0x%x channel %d i %d)", 2900 status, channel, i)); 2901 i--; 2902 for (; i >= 0; i--) { 2903 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 2904 nxge_unmap_rxdma_channel(nxgep, channel, 2905 rbr_rings[i], 2906 rcr_rings[i], 2907 rx_mbox_p[i]); 2908 } 2909 2910 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2911 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2912 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2913 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2914 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2915 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2916 2917 nxge_map_rxdma_exit: 2918 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2919 "<== nxge_map_rxdma: " 2920 "(status 0x%x channel %d)", 2921 status, channel)); 2922 2923 return (status); 2924 } 2925 2926 static void 2927 nxge_unmap_rxdma(p_nxge_t nxgep) 2928 { 2929 int i, ndmas; 2930 uint16_t channel; 2931 p_rx_rbr_rings_t rx_rbr_rings; 2932 p_rx_rbr_ring_t *rbr_rings; 2933 p_rx_rcr_rings_t rx_rcr_rings; 2934 p_rx_rcr_ring_t *rcr_rings; 2935 p_rx_mbox_areas_t rx_mbox_areas_p; 2936 p_rx_mbox_t *rx_mbox_p; 2937 p_nxge_dma_pool_t dma_buf_poolp; 2938 p_nxge_dma_pool_t dma_cntl_poolp; 2939 p_nxge_dma_common_t *dma_buf_p; 2940 2941 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_unmap_rxdma")); 2942 2943 dma_buf_poolp = nxgep->rx_buf_pool_p; 2944 dma_cntl_poolp = nxgep->rx_cntl_pool_p; 2945 2946 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 2947 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2948 "<== nxge_unmap_rxdma: NULL buf pointers")); 2949 return; 2950 } 2951 2952 rx_rbr_rings = nxgep->rx_rbr_rings; 2953 rx_rcr_rings = nxgep->rx_rcr_rings; 2954 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 2955 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2956 "<== nxge_unmap_rxdma: NULL ring pointers")); 2957 return; 2958 } 2959 ndmas = rx_rbr_rings->ndmas; 2960 if (!ndmas) { 2961 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2962 "<== nxge_unmap_rxdma: no channel")); 2963 return; 2964 } 2965 2966 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2967 "==> nxge_unmap_rxdma (ndmas %d)", ndmas)); 2968 rbr_rings = rx_rbr_rings->rbr_rings; 2969 rcr_rings = rx_rcr_rings->rcr_rings; 2970 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 2971 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 2972 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2973 2974 for (i = 0; i < ndmas; i++) { 2975 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 2976 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2977 "==> nxge_unmap_rxdma (ndmas %d) channel %d", 2978 ndmas, channel)); 2979 (void) nxge_unmap_rxdma_channel(nxgep, channel, 2980 (p_rx_rbr_ring_t)rbr_rings[i], 2981 (p_rx_rcr_ring_t)rcr_rings[i], 2982 (p_rx_mbox_t)rx_mbox_p[i]); 2983 } 2984 2985 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2986 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2987 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2988 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2989 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2990 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2991 2992 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2993 "<== nxge_unmap_rxdma")); 2994 } 2995 2996 nxge_status_t 2997 nxge_map_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 2998 p_nxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 2999 uint32_t num_chunks, 3000 p_nxge_dma_common_t *dma_cntl_p, p_rx_rcr_ring_t *rcr_p, 3001 p_rx_mbox_t *rx_mbox_p) 3002 { 3003 int status = NXGE_OK; 3004 3005 /* 3006 * Set up and prepare buffer blocks, descriptors 3007 * and mailbox. 3008 */ 3009 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3010 "==> nxge_map_rxdma_channel (channel %d)", channel)); 3011 /* 3012 * Receive buffer blocks 3013 */ 3014 status = nxge_map_rxdma_channel_buf_ring(nxgep, channel, 3015 dma_buf_p, rbr_p, num_chunks); 3016 if (status != NXGE_OK) { 3017 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3018 "==> nxge_map_rxdma_channel (channel %d): " 3019 "map buffer failed 0x%x", channel, status)); 3020 goto nxge_map_rxdma_channel_exit; 3021 } 3022 3023 /* 3024 * Receive block ring, completion ring and mailbox. 3025 */ 3026 status = nxge_map_rxdma_channel_cfg_ring(nxgep, channel, 3027 dma_cntl_p, rbr_p, rcr_p, rx_mbox_p); 3028 if (status != NXGE_OK) { 3029 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3030 "==> nxge_map_rxdma_channel (channel %d): " 3031 "map config failed 0x%x", channel, status)); 3032 goto nxge_map_rxdma_channel_fail2; 3033 } 3034 3035 goto nxge_map_rxdma_channel_exit; 3036 3037 nxge_map_rxdma_channel_fail3: 3038 /* Free rbr, rcr */ 3039 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3040 "==> nxge_map_rxdma_channel: free rbr/rcr " 3041 "(status 0x%x channel %d)", 3042 status, channel)); 3043 nxge_unmap_rxdma_channel_cfg_ring(nxgep, 3044 *rcr_p, *rx_mbox_p); 3045 3046 nxge_map_rxdma_channel_fail2: 3047 /* Free buffer blocks */ 3048 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3049 "==> nxge_map_rxdma_channel: free rx buffers" 3050 "(nxgep 0x%x status 0x%x channel %d)", 3051 nxgep, status, channel)); 3052 nxge_unmap_rxdma_channel_buf_ring(nxgep, *rbr_p); 3053 3054 status = NXGE_ERROR; 3055 3056 nxge_map_rxdma_channel_exit: 3057 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3058 "<== nxge_map_rxdma_channel: " 3059 "(nxgep 0x%x status 0x%x channel %d)", 3060 nxgep, status, channel)); 3061 3062 return (status); 3063 } 3064 3065 /*ARGSUSED*/ 3066 static void 3067 nxge_unmap_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 3068 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 3069 { 3070 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3071 "==> nxge_unmap_rxdma_channel (channel %d)", channel)); 3072 3073 /* 3074 * unmap receive block ring, completion ring and mailbox. 3075 */ 3076 (void) nxge_unmap_rxdma_channel_cfg_ring(nxgep, 3077 rcr_p, rx_mbox_p); 3078 3079 /* unmap buffer blocks */ 3080 (void) nxge_unmap_rxdma_channel_buf_ring(nxgep, rbr_p); 3081 3082 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma_channel")); 3083 } 3084 3085 /*ARGSUSED*/ 3086 static nxge_status_t 3087 nxge_map_rxdma_channel_cfg_ring(p_nxge_t nxgep, uint16_t dma_channel, 3088 p_nxge_dma_common_t *dma_cntl_p, p_rx_rbr_ring_t *rbr_p, 3089 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 3090 { 3091 p_rx_rbr_ring_t rbrp; 3092 p_rx_rcr_ring_t rcrp; 3093 p_rx_mbox_t mboxp; 3094 p_nxge_dma_common_t cntl_dmap; 3095 p_nxge_dma_common_t dmap; 3096 p_rx_msg_t *rx_msg_ring; 3097 p_rx_msg_t rx_msg_p; 3098 p_rbr_cfig_a_t rcfga_p; 3099 p_rbr_cfig_b_t rcfgb_p; 3100 p_rcrcfig_a_t cfga_p; 3101 p_rcrcfig_b_t cfgb_p; 3102 p_rxdma_cfig1_t cfig1_p; 3103 p_rxdma_cfig2_t cfig2_p; 3104 p_rbr_kick_t kick_p; 3105 uint32_t dmaaddrp; 3106 uint32_t *rbr_vaddrp; 3107 uint32_t bkaddr; 3108 nxge_status_t status = NXGE_OK; 3109 int i; 3110 uint32_t nxge_port_rcr_size; 3111 3112 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3113 "==> nxge_map_rxdma_channel_cfg_ring")); 3114 3115 cntl_dmap = *dma_cntl_p; 3116 3117 /* Map in the receive block ring */ 3118 rbrp = *rbr_p; 3119 dmap = (p_nxge_dma_common_t)&rbrp->rbr_desc; 3120 nxge_setup_dma_common(dmap, cntl_dmap, rbrp->rbb_max, 4); 3121 /* 3122 * Zero out buffer block ring descriptors. 3123 */ 3124 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3125 3126 rcfga_p = &(rbrp->rbr_cfga); 3127 rcfgb_p = &(rbrp->rbr_cfgb); 3128 kick_p = &(rbrp->rbr_kick); 3129 rcfga_p->value = 0; 3130 rcfgb_p->value = 0; 3131 kick_p->value = 0; 3132 rbrp->rbr_addr = dmap->dma_cookie.dmac_laddress; 3133 rcfga_p->value = (rbrp->rbr_addr & 3134 (RBR_CFIG_A_STDADDR_MASK | 3135 RBR_CFIG_A_STDADDR_BASE_MASK)); 3136 rcfga_p->value |= ((uint64_t)rbrp->rbb_max << RBR_CFIG_A_LEN_SHIFT); 3137 3138 rcfgb_p->bits.ldw.bufsz0 = rbrp->pkt_buf_size0; 3139 rcfgb_p->bits.ldw.vld0 = 1; 3140 rcfgb_p->bits.ldw.bufsz1 = rbrp->pkt_buf_size1; 3141 rcfgb_p->bits.ldw.vld1 = 1; 3142 rcfgb_p->bits.ldw.bufsz2 = rbrp->pkt_buf_size2; 3143 rcfgb_p->bits.ldw.vld2 = 1; 3144 rcfgb_p->bits.ldw.bksize = nxgep->rx_bksize_code; 3145 3146 /* 3147 * For each buffer block, enter receive block address to the ring. 3148 */ 3149 rbr_vaddrp = (uint32_t *)dmap->kaddrp; 3150 rbrp->rbr_desc_vp = (uint32_t *)dmap->kaddrp; 3151 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3152 "==> nxge_map_rxdma_channel_cfg_ring: channel %d " 3153 "rbr_vaddrp $%p", dma_channel, rbr_vaddrp)); 3154 3155 rx_msg_ring = rbrp->rx_msg_ring; 3156 for (i = 0; i < rbrp->tnblocks; i++) { 3157 rx_msg_p = rx_msg_ring[i]; 3158 rx_msg_p->nxgep = nxgep; 3159 rx_msg_p->rx_rbr_p = rbrp; 3160 bkaddr = (uint32_t) 3161 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress 3162 >> RBR_BKADDR_SHIFT)); 3163 rx_msg_p->free = B_FALSE; 3164 rx_msg_p->max_usage_cnt = 0xbaddcafe; 3165 3166 *rbr_vaddrp++ = bkaddr; 3167 } 3168 3169 kick_p->bits.ldw.bkadd = rbrp->rbb_max; 3170 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 3171 3172 rbrp->rbr_rd_index = 0; 3173 3174 rbrp->rbr_consumed = 0; 3175 rbrp->rbr_use_bcopy = B_TRUE; 3176 rbrp->rbr_bufsize_type = RCR_PKTBUFSZ_0; 3177 /* 3178 * Do bcopy on packets greater than bcopy size once 3179 * the lo threshold is reached. 3180 * This lo threshold should be less than the hi threshold. 3181 * 3182 * Do bcopy on every packet once the hi threshold is reached. 3183 */ 3184 if (nxge_rx_threshold_lo >= nxge_rx_threshold_hi) { 3185 /* default it to use hi */ 3186 nxge_rx_threshold_lo = nxge_rx_threshold_hi; 3187 } 3188 3189 if (nxge_rx_buf_size_type > NXGE_RBR_TYPE2) { 3190 nxge_rx_buf_size_type = NXGE_RBR_TYPE2; 3191 } 3192 rbrp->rbr_bufsize_type = nxge_rx_buf_size_type; 3193 3194 switch (nxge_rx_threshold_hi) { 3195 default: 3196 case NXGE_RX_COPY_NONE: 3197 /* Do not do bcopy at all */ 3198 rbrp->rbr_use_bcopy = B_FALSE; 3199 rbrp->rbr_threshold_hi = rbrp->rbb_max; 3200 break; 3201 3202 case NXGE_RX_COPY_1: 3203 case NXGE_RX_COPY_2: 3204 case NXGE_RX_COPY_3: 3205 case NXGE_RX_COPY_4: 3206 case NXGE_RX_COPY_5: 3207 case NXGE_RX_COPY_6: 3208 case NXGE_RX_COPY_7: 3209 rbrp->rbr_threshold_hi = 3210 rbrp->rbb_max * 3211 (nxge_rx_threshold_hi)/NXGE_RX_BCOPY_SCALE; 3212 break; 3213 3214 case NXGE_RX_COPY_ALL: 3215 rbrp->rbr_threshold_hi = 0; 3216 break; 3217 } 3218 3219 switch (nxge_rx_threshold_lo) { 3220 default: 3221 case NXGE_RX_COPY_NONE: 3222 /* Do not do bcopy at all */ 3223 if (rbrp->rbr_use_bcopy) { 3224 rbrp->rbr_use_bcopy = B_FALSE; 3225 } 3226 rbrp->rbr_threshold_lo = rbrp->rbb_max; 3227 break; 3228 3229 case NXGE_RX_COPY_1: 3230 case NXGE_RX_COPY_2: 3231 case NXGE_RX_COPY_3: 3232 case NXGE_RX_COPY_4: 3233 case NXGE_RX_COPY_5: 3234 case NXGE_RX_COPY_6: 3235 case NXGE_RX_COPY_7: 3236 rbrp->rbr_threshold_lo = 3237 rbrp->rbb_max * 3238 (nxge_rx_threshold_lo)/NXGE_RX_BCOPY_SCALE; 3239 break; 3240 3241 case NXGE_RX_COPY_ALL: 3242 rbrp->rbr_threshold_lo = 0; 3243 break; 3244 } 3245 3246 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3247 "nxge_map_rxdma_channel_cfg_ring: channel %d " 3248 "rbb_max %d " 3249 "rbrp->rbr_bufsize_type %d " 3250 "rbb_threshold_hi %d " 3251 "rbb_threshold_lo %d", 3252 dma_channel, 3253 rbrp->rbb_max, 3254 rbrp->rbr_bufsize_type, 3255 rbrp->rbr_threshold_hi, 3256 rbrp->rbr_threshold_lo)); 3257 3258 rbrp->page_valid.value = 0; 3259 rbrp->page_mask_1.value = rbrp->page_mask_2.value = 0; 3260 rbrp->page_value_1.value = rbrp->page_value_2.value = 0; 3261 rbrp->page_reloc_1.value = rbrp->page_reloc_2.value = 0; 3262 rbrp->page_hdl.value = 0; 3263 3264 rbrp->page_valid.bits.ldw.page0 = 1; 3265 rbrp->page_valid.bits.ldw.page1 = 1; 3266 3267 /* Map in the receive completion ring */ 3268 rcrp = (p_rx_rcr_ring_t) 3269 KMEM_ZALLOC(sizeof (rx_rcr_ring_t), KM_SLEEP); 3270 rcrp->rdc = dma_channel; 3271 3272 nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 3273 rcrp->comp_size = nxge_port_rcr_size; 3274 rcrp->comp_wrap_mask = nxge_port_rcr_size - 1; 3275 3276 rcrp->max_receive_pkts = nxge_max_rx_pkts; 3277 3278 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 3279 nxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size, 3280 sizeof (rcr_entry_t)); 3281 rcrp->comp_rd_index = 0; 3282 rcrp->comp_wt_index = 0; 3283 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 3284 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 3285 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3286 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3287 3288 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 3289 (nxge_port_rcr_size - 1); 3290 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 3291 (nxge_port_rcr_size - 1); 3292 3293 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3294 "==> nxge_map_rxdma_channel_cfg_ring: " 3295 "channel %d " 3296 "rbr_vaddrp $%p " 3297 "rcr_desc_rd_head_p $%p " 3298 "rcr_desc_rd_head_pp $%p " 3299 "rcr_desc_rd_last_p $%p " 3300 "rcr_desc_rd_last_pp $%p ", 3301 dma_channel, 3302 rbr_vaddrp, 3303 rcrp->rcr_desc_rd_head_p, 3304 rcrp->rcr_desc_rd_head_pp, 3305 rcrp->rcr_desc_last_p, 3306 rcrp->rcr_desc_last_pp)); 3307 3308 /* 3309 * Zero out buffer block ring descriptors. 3310 */ 3311 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3312 rcrp->intr_timeout = nxgep->intr_timeout; 3313 rcrp->intr_threshold = nxgep->intr_threshold; 3314 rcrp->full_hdr_flag = B_FALSE; 3315 rcrp->sw_priv_hdr_len = 0; 3316 3317 cfga_p = &(rcrp->rcr_cfga); 3318 cfgb_p = &(rcrp->rcr_cfgb); 3319 cfga_p->value = 0; 3320 cfgb_p->value = 0; 3321 rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress; 3322 cfga_p->value = (rcrp->rcr_addr & 3323 (RCRCFIG_A_STADDR_MASK | 3324 RCRCFIG_A_STADDR_BASE_MASK)); 3325 3326 rcfga_p->value |= ((uint64_t)rcrp->comp_size << 3327 RCRCFIG_A_LEN_SHIF); 3328 3329 /* 3330 * Timeout should be set based on the system clock divider. 3331 * The following timeout value of 1 assumes that the 3332 * granularity (1000) is 3 microseconds running at 300MHz. 3333 */ 3334 cfgb_p->bits.ldw.pthres = rcrp->intr_threshold; 3335 cfgb_p->bits.ldw.timeout = rcrp->intr_timeout; 3336 cfgb_p->bits.ldw.entout = 1; 3337 3338 /* Map in the mailbox */ 3339 mboxp = (p_rx_mbox_t) 3340 KMEM_ZALLOC(sizeof (rx_mbox_t), KM_SLEEP); 3341 dmap = (p_nxge_dma_common_t)&mboxp->rx_mbox; 3342 nxge_setup_dma_common(dmap, cntl_dmap, 1, sizeof (rxdma_mailbox_t)); 3343 cfig1_p = (p_rxdma_cfig1_t)&mboxp->rx_cfg1; 3344 cfig2_p = (p_rxdma_cfig2_t)&mboxp->rx_cfg2; 3345 cfig1_p->value = cfig2_p->value = 0; 3346 3347 mboxp->mbox_addr = dmap->dma_cookie.dmac_laddress; 3348 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3349 "==> nxge_map_rxdma_channel_cfg_ring: " 3350 "channel %d cfg1 0x%016llx cfig2 0x%016llx cookie 0x%016llx", 3351 dma_channel, cfig1_p->value, cfig2_p->value, 3352 mboxp->mbox_addr)); 3353 3354 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress >> 32 3355 & 0xfff); 3356 cfig1_p->bits.ldw.mbaddr_h = dmaaddrp; 3357 3358 3359 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 0xffffffff); 3360 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 3361 RXDMA_CFIG2_MBADDR_L_MASK); 3362 3363 cfig2_p->bits.ldw.mbaddr = (dmaaddrp >> RXDMA_CFIG2_MBADDR_L_SHIFT); 3364 3365 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3366 "==> nxge_map_rxdma_channel_cfg_ring: " 3367 "channel %d damaddrp $%p " 3368 "cfg1 0x%016llx cfig2 0x%016llx", 3369 dma_channel, dmaaddrp, 3370 cfig1_p->value, cfig2_p->value)); 3371 3372 cfig2_p->bits.ldw.full_hdr = rcrp->full_hdr_flag; 3373 cfig2_p->bits.ldw.offset = rcrp->sw_priv_hdr_len; 3374 3375 rbrp->rx_rcr_p = rcrp; 3376 rcrp->rx_rbr_p = rbrp; 3377 *rcr_p = rcrp; 3378 *rx_mbox_p = mboxp; 3379 3380 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3381 "<== nxge_map_rxdma_channel_cfg_ring status 0x%08x", status)); 3382 3383 return (status); 3384 } 3385 3386 /*ARGSUSED*/ 3387 static void 3388 nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t nxgep, 3389 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 3390 { 3391 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3392 "==> nxge_unmap_rxdma_channel_cfg_ring: channel %d", 3393 rcr_p->rdc)); 3394 3395 KMEM_FREE(rcr_p, sizeof (rx_rcr_ring_t)); 3396 KMEM_FREE(rx_mbox_p, sizeof (rx_mbox_t)); 3397 3398 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3399 "<== nxge_unmap_rxdma_channel_cfg_ring")); 3400 } 3401 3402 static nxge_status_t 3403 nxge_map_rxdma_channel_buf_ring(p_nxge_t nxgep, uint16_t channel, 3404 p_nxge_dma_common_t *dma_buf_p, 3405 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks) 3406 { 3407 p_rx_rbr_ring_t rbrp; 3408 p_nxge_dma_common_t dma_bufp, tmp_bufp; 3409 p_rx_msg_t *rx_msg_ring; 3410 p_rx_msg_t rx_msg_p; 3411 p_mblk_t mblk_p; 3412 3413 rxring_info_t *ring_info; 3414 nxge_status_t status = NXGE_OK; 3415 int i, j, index; 3416 uint32_t size, bsize, nblocks, nmsgs; 3417 3418 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3419 "==> nxge_map_rxdma_channel_buf_ring: channel %d", 3420 channel)); 3421 3422 dma_bufp = tmp_bufp = *dma_buf_p; 3423 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3424 " nxge_map_rxdma_channel_buf_ring: channel %d to map %d " 3425 "chunks bufp 0x%016llx", 3426 channel, num_chunks, dma_bufp)); 3427 3428 nmsgs = 0; 3429 for (i = 0; i < num_chunks; i++, tmp_bufp++) { 3430 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3431 "==> nxge_map_rxdma_channel_buf_ring: channel %d " 3432 "bufp 0x%016llx nblocks %d nmsgs %d", 3433 channel, tmp_bufp, tmp_bufp->nblocks, nmsgs)); 3434 nmsgs += tmp_bufp->nblocks; 3435 } 3436 if (!nmsgs) { 3437 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3438 "<== nxge_map_rxdma_channel_buf_ring: channel %d " 3439 "no msg blocks", 3440 channel)); 3441 status = NXGE_ERROR; 3442 goto nxge_map_rxdma_channel_buf_ring_exit; 3443 } 3444 3445 rbrp = (p_rx_rbr_ring_t) 3446 KMEM_ZALLOC(sizeof (rx_rbr_ring_t), KM_SLEEP); 3447 3448 size = nmsgs * sizeof (p_rx_msg_t); 3449 rx_msg_ring = KMEM_ZALLOC(size, KM_SLEEP); 3450 ring_info = (rxring_info_t *)KMEM_ZALLOC(sizeof (rxring_info_t), 3451 KM_SLEEP); 3452 3453 MUTEX_INIT(&rbrp->lock, NULL, MUTEX_DRIVER, 3454 (void *)nxgep->interrupt_cookie); 3455 MUTEX_INIT(&rbrp->post_lock, NULL, MUTEX_DRIVER, 3456 (void *)nxgep->interrupt_cookie); 3457 rbrp->rdc = channel; 3458 rbrp->num_blocks = num_chunks; 3459 rbrp->tnblocks = nmsgs; 3460 rbrp->rbb_max = nmsgs; 3461 rbrp->rbr_max_size = nmsgs; 3462 rbrp->rbr_wrap_mask = (rbrp->rbb_max - 1); 3463 3464 /* 3465 * Buffer sizes suggested by NIU architect. 3466 * 256, 512 and 2K. 3467 */ 3468 3469 rbrp->pkt_buf_size0 = RBR_BUFSZ0_256B; 3470 rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_256_BYTES; 3471 rbrp->npi_pkt_buf_size0 = SIZE_256B; 3472 3473 rbrp->pkt_buf_size1 = RBR_BUFSZ1_1K; 3474 rbrp->pkt_buf_size1_bytes = RBR_BUFSZ1_1K_BYTES; 3475 rbrp->npi_pkt_buf_size1 = SIZE_1KB; 3476 3477 rbrp->block_size = nxgep->rx_default_block_size; 3478 3479 if (!nxge_jumbo_enable && !nxgep->param_arr[param_accept_jumbo].value) { 3480 rbrp->pkt_buf_size2 = RBR_BUFSZ2_2K; 3481 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_2K_BYTES; 3482 rbrp->npi_pkt_buf_size2 = SIZE_2KB; 3483 } else { 3484 if (rbrp->block_size >= 0x2000) { 3485 rbrp->pkt_buf_size2 = RBR_BUFSZ2_8K; 3486 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_8K_BYTES; 3487 rbrp->npi_pkt_buf_size2 = SIZE_8KB; 3488 } else { 3489 rbrp->pkt_buf_size2 = RBR_BUFSZ2_4K; 3490 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_4K_BYTES; 3491 rbrp->npi_pkt_buf_size2 = SIZE_4KB; 3492 } 3493 } 3494 3495 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3496 "==> nxge_map_rxdma_channel_buf_ring: channel %d " 3497 "actual rbr max %d rbb_max %d nmsgs %d " 3498 "rbrp->block_size %d default_block_size %d " 3499 "(config nxge_rbr_size %d nxge_rbr_spare_size %d)", 3500 channel, rbrp->rbr_max_size, rbrp->rbb_max, nmsgs, 3501 rbrp->block_size, nxgep->rx_default_block_size, 3502 nxge_rbr_size, nxge_rbr_spare_size)); 3503 3504 /* Map in buffers from the buffer pool. */ 3505 index = 0; 3506 for (i = 0; i < rbrp->num_blocks; i++, dma_bufp++) { 3507 bsize = dma_bufp->block_size; 3508 nblocks = dma_bufp->nblocks; 3509 ring_info->buffer[i].dvma_addr = (uint64_t)dma_bufp->ioaddr_pp; 3510 ring_info->buffer[i].buf_index = i; 3511 ring_info->buffer[i].buf_size = dma_bufp->alength; 3512 ring_info->buffer[i].start_index = index; 3513 ring_info->buffer[i].kaddr = (uint64_t)dma_bufp->kaddrp; 3514 3515 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3516 " nxge_map_rxdma_channel_buf_ring: map channel %d " 3517 "chunk %d" 3518 " nblocks %d chunk_size %x block_size 0x%x " 3519 "dma_bufp $%p", channel, i, 3520 dma_bufp->nblocks, ring_info->buffer[i].buf_size, bsize, 3521 dma_bufp)); 3522 3523 for (j = 0; j < nblocks; j++) { 3524 if ((rx_msg_p = nxge_allocb(bsize, BPRI_LO, 3525 dma_bufp)) == NULL) { 3526 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3527 "allocb failed (index %d i %d j %d)", 3528 index, i, j)); 3529 goto nxge_map_rxdma_channel_buf_ring_fail1; 3530 } 3531 rx_msg_ring[index] = rx_msg_p; 3532 rx_msg_p->block_index = index; 3533 rx_msg_p->shifted_addr = (uint32_t) 3534 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 3535 RBR_BKADDR_SHIFT)); 3536 3537 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3538 "index %d j %d rx_msg_p $%p mblk %p", 3539 index, j, rx_msg_p, rx_msg_p->rx_mblk_p)); 3540 3541 mblk_p = rx_msg_p->rx_mblk_p; 3542 mblk_p->b_wptr = mblk_p->b_rptr + bsize; 3543 index++; 3544 rx_msg_p->buf_dma.dma_channel = channel; 3545 } 3546 } 3547 if (i < rbrp->num_blocks) { 3548 goto nxge_map_rxdma_channel_buf_ring_fail1; 3549 } 3550 3551 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3552 "nxge_map_rxdma_channel_buf_ring: done buf init " 3553 "channel %d msg block entries %d", 3554 channel, index)); 3555 ring_info->block_size_mask = bsize - 1; 3556 rbrp->rx_msg_ring = rx_msg_ring; 3557 rbrp->dma_bufp = dma_buf_p; 3558 rbrp->ring_info = ring_info; 3559 3560 status = nxge_rxbuf_index_info_init(nxgep, rbrp); 3561 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3562 " nxge_map_rxdma_channel_buf_ring: " 3563 "channel %d done buf info init", channel)); 3564 3565 *rbr_p = rbrp; 3566 goto nxge_map_rxdma_channel_buf_ring_exit; 3567 3568 nxge_map_rxdma_channel_buf_ring_fail1: 3569 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3570 " nxge_map_rxdma_channel_buf_ring: failed channel (0x%x)", 3571 channel, status)); 3572 3573 index--; 3574 for (; index >= 0; index--) { 3575 rx_msg_p = rx_msg_ring[index]; 3576 if (rx_msg_p != NULL) { 3577 freeb(rx_msg_p->rx_mblk_p); 3578 rx_msg_ring[index] = NULL; 3579 } 3580 } 3581 nxge_map_rxdma_channel_buf_ring_fail: 3582 MUTEX_DESTROY(&rbrp->post_lock); 3583 MUTEX_DESTROY(&rbrp->lock); 3584 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3585 KMEM_FREE(rx_msg_ring, size); 3586 KMEM_FREE(rbrp, sizeof (rx_rbr_ring_t)); 3587 3588 status = NXGE_ERROR; 3589 3590 nxge_map_rxdma_channel_buf_ring_exit: 3591 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3592 "<== nxge_map_rxdma_channel_buf_ring status 0x%08x", status)); 3593 3594 return (status); 3595 } 3596 3597 /*ARGSUSED*/ 3598 static void 3599 nxge_unmap_rxdma_channel_buf_ring(p_nxge_t nxgep, 3600 p_rx_rbr_ring_t rbr_p) 3601 { 3602 p_rx_msg_t *rx_msg_ring; 3603 p_rx_msg_t rx_msg_p; 3604 rxring_info_t *ring_info; 3605 int i; 3606 uint32_t size; 3607 #ifdef NXGE_DEBUG 3608 int num_chunks; 3609 #endif 3610 3611 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3612 "==> nxge_unmap_rxdma_channel_buf_ring")); 3613 if (rbr_p == NULL) { 3614 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3615 "<== nxge_unmap_rxdma_channel_buf_ring: NULL rbrp")); 3616 return; 3617 } 3618 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3619 "==> nxge_unmap_rxdma_channel_buf_ring: channel %d", 3620 rbr_p->rdc)); 3621 3622 rx_msg_ring = rbr_p->rx_msg_ring; 3623 ring_info = rbr_p->ring_info; 3624 3625 if (rx_msg_ring == NULL || ring_info == NULL) { 3626 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3627 "<== nxge_unmap_rxdma_channel_buf_ring: " 3628 "rx_msg_ring $%p ring_info $%p", 3629 rx_msg_p, ring_info)); 3630 return; 3631 } 3632 3633 #ifdef NXGE_DEBUG 3634 num_chunks = rbr_p->num_blocks; 3635 #endif 3636 size = rbr_p->tnblocks * sizeof (p_rx_msg_t); 3637 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3638 " nxge_unmap_rxdma_channel_buf_ring: channel %d chunks %d " 3639 "tnblocks %d (max %d) size ptrs %d ", 3640 rbr_p->rdc, num_chunks, 3641 rbr_p->tnblocks, rbr_p->rbr_max_size, size)); 3642 3643 for (i = 0; i < rbr_p->tnblocks; i++) { 3644 rx_msg_p = rx_msg_ring[i]; 3645 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3646 " nxge_unmap_rxdma_channel_buf_ring: " 3647 "rx_msg_p $%p", 3648 rx_msg_p)); 3649 if (rx_msg_p != NULL) { 3650 freeb(rx_msg_p->rx_mblk_p); 3651 rx_msg_ring[i] = NULL; 3652 } 3653 } 3654 3655 MUTEX_DESTROY(&rbr_p->post_lock); 3656 MUTEX_DESTROY(&rbr_p->lock); 3657 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3658 KMEM_FREE(rx_msg_ring, size); 3659 KMEM_FREE(rbr_p, sizeof (rx_rbr_ring_t)); 3660 3661 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3662 "<== nxge_unmap_rxdma_channel_buf_ring")); 3663 } 3664 3665 static nxge_status_t 3666 nxge_rxdma_hw_start_common(p_nxge_t nxgep) 3667 { 3668 nxge_status_t status = NXGE_OK; 3669 3670 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 3671 3672 /* 3673 * Load the sharable parameters by writing to the 3674 * function zero control registers. These FZC registers 3675 * should be initialized only once for the entire chip. 3676 */ 3677 (void) nxge_init_fzc_rx_common(nxgep); 3678 3679 /* 3680 * Initialize the RXDMA port specific FZC control configurations. 3681 * These FZC registers are pertaining to each port. 3682 */ 3683 (void) nxge_init_fzc_rxdma_port(nxgep); 3684 3685 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 3686 3687 return (status); 3688 } 3689 3690 /*ARGSUSED*/ 3691 static void 3692 nxge_rxdma_hw_stop_common(p_nxge_t nxgep) 3693 { 3694 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop_common")); 3695 3696 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop_common")); 3697 } 3698 3699 static nxge_status_t 3700 nxge_rxdma_hw_start(p_nxge_t nxgep) 3701 { 3702 int i, ndmas; 3703 uint16_t channel; 3704 p_rx_rbr_rings_t rx_rbr_rings; 3705 p_rx_rbr_ring_t *rbr_rings; 3706 p_rx_rcr_rings_t rx_rcr_rings; 3707 p_rx_rcr_ring_t *rcr_rings; 3708 p_rx_mbox_areas_t rx_mbox_areas_p; 3709 p_rx_mbox_t *rx_mbox_p; 3710 nxge_status_t status = NXGE_OK; 3711 3712 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start")); 3713 3714 rx_rbr_rings = nxgep->rx_rbr_rings; 3715 rx_rcr_rings = nxgep->rx_rcr_rings; 3716 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3717 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3718 "<== nxge_rxdma_hw_start: NULL ring pointers")); 3719 return (NXGE_ERROR); 3720 } 3721 ndmas = rx_rbr_rings->ndmas; 3722 if (ndmas == 0) { 3723 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3724 "<== nxge_rxdma_hw_start: no dma channel allocated")); 3725 return (NXGE_ERROR); 3726 } 3727 3728 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3729 "==> nxge_rxdma_hw_start (ndmas %d)", ndmas)); 3730 3731 rbr_rings = rx_rbr_rings->rbr_rings; 3732 rcr_rings = rx_rcr_rings->rcr_rings; 3733 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 3734 if (rx_mbox_areas_p) { 3735 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 3736 } 3737 3738 for (i = 0; i < ndmas; i++) { 3739 channel = rbr_rings[i]->rdc; 3740 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3741 "==> nxge_rxdma_hw_start (ndmas %d) channel %d", 3742 ndmas, channel)); 3743 status = nxge_rxdma_start_channel(nxgep, channel, 3744 (p_rx_rbr_ring_t)rbr_rings[i], 3745 (p_rx_rcr_ring_t)rcr_rings[i], 3746 (p_rx_mbox_t)rx_mbox_p[i]); 3747 if (status != NXGE_OK) { 3748 goto nxge_rxdma_hw_start_fail1; 3749 } 3750 } 3751 3752 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start: " 3753 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3754 rx_rbr_rings, rx_rcr_rings)); 3755 3756 goto nxge_rxdma_hw_start_exit; 3757 3758 nxge_rxdma_hw_start_fail1: 3759 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3760 "==> nxge_rxdma_hw_start: disable " 3761 "(status 0x%x channel %d i %d)", status, channel, i)); 3762 for (; i >= 0; i--) { 3763 channel = rbr_rings[i]->rdc; 3764 (void) nxge_rxdma_stop_channel(nxgep, channel); 3765 } 3766 3767 nxge_rxdma_hw_start_exit: 3768 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3769 "==> nxge_rxdma_hw_start: (status 0x%x)", status)); 3770 3771 return (status); 3772 } 3773 3774 static void 3775 nxge_rxdma_hw_stop(p_nxge_t nxgep) 3776 { 3777 int i, ndmas; 3778 uint16_t channel; 3779 p_rx_rbr_rings_t rx_rbr_rings; 3780 p_rx_rbr_ring_t *rbr_rings; 3781 p_rx_rcr_rings_t rx_rcr_rings; 3782 3783 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop")); 3784 3785 rx_rbr_rings = nxgep->rx_rbr_rings; 3786 rx_rcr_rings = nxgep->rx_rcr_rings; 3787 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3788 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3789 "<== nxge_rxdma_hw_stop: NULL ring pointers")); 3790 return; 3791 } 3792 ndmas = rx_rbr_rings->ndmas; 3793 if (!ndmas) { 3794 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3795 "<== nxge_rxdma_hw_stop: no dma channel allocated")); 3796 return; 3797 } 3798 3799 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3800 "==> nxge_rxdma_hw_stop (ndmas %d)", ndmas)); 3801 3802 rbr_rings = rx_rbr_rings->rbr_rings; 3803 3804 for (i = 0; i < ndmas; i++) { 3805 channel = rbr_rings[i]->rdc; 3806 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3807 "==> nxge_rxdma_hw_stop (ndmas %d) channel %d", 3808 ndmas, channel)); 3809 (void) nxge_rxdma_stop_channel(nxgep, channel); 3810 } 3811 3812 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop: " 3813 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3814 rx_rbr_rings, rx_rcr_rings)); 3815 3816 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_hw_stop")); 3817 } 3818 3819 3820 static nxge_status_t 3821 nxge_rxdma_start_channel(p_nxge_t nxgep, uint16_t channel, 3822 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 3823 3824 { 3825 npi_handle_t handle; 3826 npi_status_t rs = NPI_SUCCESS; 3827 rx_dma_ctl_stat_t cs; 3828 rx_dma_ent_msk_t ent_mask; 3829 nxge_status_t status = NXGE_OK; 3830 3831 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel")); 3832 3833 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3834 3835 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "nxge_rxdma_start_channel: " 3836 "npi handle addr $%p acc $%p", 3837 nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 3838 3839 /* Reset RXDMA channel */ 3840 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 3841 if (rs != NPI_SUCCESS) { 3842 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3843 "==> nxge_rxdma_start_channel: " 3844 "reset rxdma failed (0x%08x channel %d)", 3845 status, channel)); 3846 return (NXGE_ERROR | rs); 3847 } 3848 3849 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3850 "==> nxge_rxdma_start_channel: reset done: channel %d", 3851 channel)); 3852 3853 /* 3854 * Initialize the RXDMA channel specific FZC control 3855 * configurations. These FZC registers are pertaining 3856 * to each RX channel (logical pages). 3857 */ 3858 status = nxge_init_fzc_rxdma_channel(nxgep, 3859 channel, rbr_p, rcr_p, mbox_p); 3860 if (status != NXGE_OK) { 3861 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3862 "==> nxge_rxdma_start_channel: " 3863 "init fzc rxdma failed (0x%08x channel %d)", 3864 status, channel)); 3865 return (status); 3866 } 3867 3868 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3869 "==> nxge_rxdma_start_channel: fzc done")); 3870 3871 /* 3872 * Zero out the shadow and prefetch ram. 3873 */ 3874 3875 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3876 "ram done")); 3877 3878 /* Set up the interrupt event masks. */ 3879 ent_mask.value = 0; 3880 ent_mask.value |= RX_DMA_ENT_MSK_RBREMPTY_MASK; 3881 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 3882 &ent_mask); 3883 if (rs != NPI_SUCCESS) { 3884 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3885 "==> nxge_rxdma_start_channel: " 3886 "init rxdma event masks failed (0x%08x channel %d)", 3887 status, channel)); 3888 return (NXGE_ERROR | rs); 3889 } 3890 3891 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3892 "event done: channel %d (mask 0x%016llx)", 3893 channel, ent_mask.value)); 3894 3895 /* Initialize the receive DMA control and status register */ 3896 cs.value = 0; 3897 cs.bits.hdw.mex = 1; 3898 cs.bits.hdw.rcrthres = 1; 3899 cs.bits.hdw.rcrto = 1; 3900 cs.bits.hdw.rbr_empty = 1; 3901 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, &cs); 3902 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3903 "channel %d rx_dma_cntl_stat 0x%0016llx", channel, cs.value)); 3904 if (status != NXGE_OK) { 3905 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3906 "==> nxge_rxdma_start_channel: " 3907 "init rxdma control register failed (0x%08x channel %d", 3908 status, channel)); 3909 return (status); 3910 } 3911 3912 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3913 "control done - channel %d cs 0x%016llx", channel, cs.value)); 3914 3915 /* 3916 * Load RXDMA descriptors, buffers, mailbox, 3917 * initialise the receive DMA channels and 3918 * enable each DMA channel. 3919 */ 3920 status = nxge_enable_rxdma_channel(nxgep, 3921 channel, rbr_p, rcr_p, mbox_p); 3922 3923 if (status != NXGE_OK) { 3924 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3925 " nxge_rxdma_start_channel: " 3926 " init enable rxdma failed (0x%08x channel %d)", 3927 status, channel)); 3928 return (status); 3929 } 3930 3931 ent_mask.value = 0; 3932 ent_mask.value |= (RX_DMA_ENT_MSK_WRED_DROP_MASK | 3933 RX_DMA_ENT_MSK_PTDROP_PKT_MASK); 3934 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 3935 &ent_mask); 3936 if (rs != NPI_SUCCESS) { 3937 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3938 "==> nxge_rxdma_start_channel: " 3939 "init rxdma event masks failed (0x%08x channel %d)", 3940 status, channel)); 3941 return (NXGE_ERROR | rs); 3942 } 3943 3944 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3945 "control done - channel %d cs 0x%016llx", channel, cs.value)); 3946 3947 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3948 "==> nxge_rxdma_start_channel: enable done")); 3949 3950 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_start_channel")); 3951 3952 return (NXGE_OK); 3953 } 3954 3955 static nxge_status_t 3956 nxge_rxdma_stop_channel(p_nxge_t nxgep, uint16_t channel) 3957 { 3958 npi_handle_t handle; 3959 npi_status_t rs = NPI_SUCCESS; 3960 rx_dma_ctl_stat_t cs; 3961 rx_dma_ent_msk_t ent_mask; 3962 nxge_status_t status = NXGE_OK; 3963 3964 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel")); 3965 3966 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3967 3968 NXGE_DEBUG_MSG((nxgep, RX_CTL, "nxge_rxdma_stop_channel: " 3969 "npi handle addr $%p acc $%p", 3970 nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 3971 3972 /* Reset RXDMA channel */ 3973 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 3974 if (rs != NPI_SUCCESS) { 3975 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3976 " nxge_rxdma_stop_channel: " 3977 " reset rxdma failed (0x%08x channel %d)", 3978 rs, channel)); 3979 return (NXGE_ERROR | rs); 3980 } 3981 3982 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3983 "==> nxge_rxdma_stop_channel: reset done")); 3984 3985 /* Set up the interrupt event masks. */ 3986 ent_mask.value = RX_DMA_ENT_MSK_ALL; 3987 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 3988 &ent_mask); 3989 if (rs != NPI_SUCCESS) { 3990 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3991 "==> nxge_rxdma_stop_channel: " 3992 "set rxdma event masks failed (0x%08x channel %d)", 3993 rs, channel)); 3994 return (NXGE_ERROR | rs); 3995 } 3996 3997 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3998 "==> nxge_rxdma_stop_channel: event done")); 3999 4000 /* Initialize the receive DMA control and status register */ 4001 cs.value = 0; 4002 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, 4003 &cs); 4004 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel: control " 4005 " to default (all 0s) 0x%08x", cs.value)); 4006 if (status != NXGE_OK) { 4007 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4008 " nxge_rxdma_stop_channel: init rxdma" 4009 " control register failed (0x%08x channel %d", 4010 status, channel)); 4011 return (status); 4012 } 4013 4014 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4015 "==> nxge_rxdma_stop_channel: control done")); 4016 4017 /* disable dma channel */ 4018 status = nxge_disable_rxdma_channel(nxgep, channel); 4019 4020 if (status != NXGE_OK) { 4021 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4022 " nxge_rxdma_stop_channel: " 4023 " init enable rxdma failed (0x%08x channel %d)", 4024 status, channel)); 4025 return (status); 4026 } 4027 4028 NXGE_DEBUG_MSG((nxgep, 4029 RX_CTL, "==> nxge_rxdma_stop_channel: disable done")); 4030 4031 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_channel")); 4032 4033 return (NXGE_OK); 4034 } 4035 4036 nxge_status_t 4037 nxge_rxdma_handle_sys_errors(p_nxge_t nxgep) 4038 { 4039 npi_handle_t handle; 4040 p_nxge_rdc_sys_stats_t statsp; 4041 rx_ctl_dat_fifo_stat_t stat; 4042 uint32_t zcp_err_status; 4043 uint32_t ipp_err_status; 4044 nxge_status_t status = NXGE_OK; 4045 npi_status_t rs = NPI_SUCCESS; 4046 boolean_t my_err = B_FALSE; 4047 4048 handle = nxgep->npi_handle; 4049 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 4050 4051 rs = npi_rxdma_rxctl_fifo_error_intr_get(handle, &stat); 4052 4053 if (rs != NPI_SUCCESS) 4054 return (NXGE_ERROR | rs); 4055 4056 if (stat.bits.ldw.id_mismatch) { 4057 statsp->id_mismatch++; 4058 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 4059 NXGE_FM_EREPORT_RDMC_ID_MISMATCH); 4060 /* Global fatal error encountered */ 4061 } 4062 4063 if ((stat.bits.ldw.zcp_eop_err) || (stat.bits.ldw.ipp_eop_err)) { 4064 switch (nxgep->mac.portnum) { 4065 case 0: 4066 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT0) || 4067 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT0)) { 4068 my_err = B_TRUE; 4069 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4070 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4071 } 4072 break; 4073 case 1: 4074 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT1) || 4075 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT1)) { 4076 my_err = B_TRUE; 4077 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4078 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4079 } 4080 break; 4081 case 2: 4082 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT2) || 4083 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT2)) { 4084 my_err = B_TRUE; 4085 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4086 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4087 } 4088 break; 4089 case 3: 4090 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT3) || 4091 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT3)) { 4092 my_err = B_TRUE; 4093 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4094 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4095 } 4096 break; 4097 default: 4098 return (NXGE_ERROR); 4099 } 4100 } 4101 4102 if (my_err) { 4103 status = nxge_rxdma_handle_port_errors(nxgep, ipp_err_status, 4104 zcp_err_status); 4105 if (status != NXGE_OK) 4106 return (status); 4107 } 4108 4109 return (NXGE_OK); 4110 } 4111 4112 static nxge_status_t 4113 nxge_rxdma_handle_port_errors(p_nxge_t nxgep, uint32_t ipp_status, 4114 uint32_t zcp_status) 4115 { 4116 boolean_t rxport_fatal = B_FALSE; 4117 p_nxge_rdc_sys_stats_t statsp; 4118 nxge_status_t status = NXGE_OK; 4119 uint8_t portn; 4120 4121 portn = nxgep->mac.portnum; 4122 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 4123 4124 if (ipp_status & (0x1 << portn)) { 4125 statsp->ipp_eop_err++; 4126 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 4127 NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR); 4128 rxport_fatal = B_TRUE; 4129 } 4130 4131 if (zcp_status & (0x1 << portn)) { 4132 statsp->zcp_eop_err++; 4133 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 4134 NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR); 4135 rxport_fatal = B_TRUE; 4136 } 4137 4138 if (rxport_fatal) { 4139 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4140 " nxge_rxdma_handle_port_error: " 4141 " fatal error on Port #%d\n", 4142 portn)); 4143 status = nxge_rx_port_fatal_err_recover(nxgep); 4144 if (status == NXGE_OK) { 4145 FM_SERVICE_RESTORED(nxgep); 4146 } 4147 } 4148 4149 return (status); 4150 } 4151 4152 static nxge_status_t 4153 nxge_rxdma_fatal_err_recover(p_nxge_t nxgep, uint16_t channel) 4154 { 4155 npi_handle_t handle; 4156 npi_status_t rs = NPI_SUCCESS; 4157 nxge_status_t status = NXGE_OK; 4158 p_rx_rbr_ring_t rbrp; 4159 p_rx_rcr_ring_t rcrp; 4160 p_rx_mbox_t mboxp; 4161 rx_dma_ent_msk_t ent_mask; 4162 p_nxge_dma_common_t dmap; 4163 int ring_idx; 4164 uint32_t ref_cnt; 4165 p_rx_msg_t rx_msg_p; 4166 int i; 4167 uint32_t nxge_port_rcr_size; 4168 4169 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fatal_err_recover")); 4170 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4171 "Recovering from RxDMAChannel#%d error...", channel)); 4172 4173 /* 4174 * Stop the dma channel waits for the stop done. 4175 * If the stop done bit is not set, then create 4176 * an error. 4177 */ 4178 4179 handle = NXGE_DEV_NPI_HANDLE(nxgep); 4180 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Rx DMA stop...")); 4181 4182 ring_idx = nxge_rxdma_get_ring_index(nxgep, channel); 4183 rbrp = (p_rx_rbr_ring_t)nxgep->rx_rbr_rings->rbr_rings[ring_idx]; 4184 rcrp = (p_rx_rcr_ring_t)nxgep->rx_rcr_rings->rcr_rings[ring_idx]; 4185 4186 MUTEX_ENTER(&rcrp->lock); 4187 MUTEX_ENTER(&rbrp->lock); 4188 MUTEX_ENTER(&rbrp->post_lock); 4189 4190 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA channel...")); 4191 4192 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 4193 if (rs != NPI_SUCCESS) { 4194 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4195 "nxge_disable_rxdma_channel:failed")); 4196 goto fail; 4197 } 4198 4199 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA interrupt...")); 4200 4201 /* Disable interrupt */ 4202 ent_mask.value = RX_DMA_ENT_MSK_ALL; 4203 rs = npi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 4204 if (rs != NPI_SUCCESS) { 4205 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4206 "nxge_rxdma_stop_channel: " 4207 "set rxdma event masks failed (channel %d)", 4208 channel)); 4209 } 4210 4211 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel reset...")); 4212 4213 /* Reset RXDMA channel */ 4214 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 4215 if (rs != NPI_SUCCESS) { 4216 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4217 "nxge_rxdma_fatal_err_recover: " 4218 " reset rxdma failed (channel %d)", channel)); 4219 goto fail; 4220 } 4221 4222 nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 4223 4224 mboxp = 4225 (p_rx_mbox_t)nxgep->rx_mbox_areas_p->rxmbox_areas[ring_idx]; 4226 4227 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 4228 rbrp->rbr_rd_index = 0; 4229 4230 rcrp->comp_rd_index = 0; 4231 rcrp->comp_wt_index = 0; 4232 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 4233 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 4234 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 4235 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 4236 4237 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 4238 (nxge_port_rcr_size - 1); 4239 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 4240 (nxge_port_rcr_size - 1); 4241 4242 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 4243 bzero((caddr_t)dmap->kaddrp, dmap->alength); 4244 4245 cmn_err(CE_NOTE, "!rbr entries = %d\n", rbrp->rbr_max_size); 4246 4247 for (i = 0; i < rbrp->rbr_max_size; i++) { 4248 rx_msg_p = rbrp->rx_msg_ring[i]; 4249 ref_cnt = rx_msg_p->ref_cnt; 4250 if (ref_cnt != 1) { 4251 if (rx_msg_p->cur_usage_cnt != 4252 rx_msg_p->max_usage_cnt) { 4253 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4254 "buf[%d]: cur_usage_cnt = %d " 4255 "max_usage_cnt = %d\n", i, 4256 rx_msg_p->cur_usage_cnt, 4257 rx_msg_p->max_usage_cnt)); 4258 } else { 4259 /* Buffer can be re-posted */ 4260 rx_msg_p->free = B_TRUE; 4261 rx_msg_p->cur_usage_cnt = 0; 4262 rx_msg_p->max_usage_cnt = 0xbaddcafe; 4263 rx_msg_p->pkt_buf_size = 0; 4264 } 4265 } 4266 } 4267 4268 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel re-start...")); 4269 4270 status = nxge_rxdma_start_channel(nxgep, channel, rbrp, rcrp, mboxp); 4271 if (status != NXGE_OK) { 4272 goto fail; 4273 } 4274 4275 MUTEX_EXIT(&rbrp->post_lock); 4276 MUTEX_EXIT(&rbrp->lock); 4277 MUTEX_EXIT(&rcrp->lock); 4278 4279 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4280 "Recovery Successful, RxDMAChannel#%d Restored", 4281 channel)); 4282 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fatal_err_recover")); 4283 4284 return (NXGE_OK); 4285 fail: 4286 MUTEX_EXIT(&rbrp->post_lock); 4287 MUTEX_EXIT(&rbrp->lock); 4288 MUTEX_EXIT(&rcrp->lock); 4289 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 4290 4291 return (NXGE_ERROR | rs); 4292 } 4293 4294 nxge_status_t 4295 nxge_rx_port_fatal_err_recover(p_nxge_t nxgep) 4296 { 4297 nxge_status_t status = NXGE_OK; 4298 p_nxge_dma_common_t *dma_buf_p; 4299 uint16_t channel; 4300 int ndmas; 4301 int i; 4302 4303 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_port_fatal_err_recover")); 4304 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4305 "Recovering from RxPort error...")); 4306 /* Disable RxMAC */ 4307 4308 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxMAC...\n")); 4309 if (nxge_rx_mac_disable(nxgep) != NXGE_OK) 4310 goto fail; 4311 4312 NXGE_DELAY(1000); 4313 4314 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Stop all RxDMA channels...")); 4315 4316 ndmas = nxgep->rx_buf_pool_p->ndmas; 4317 dma_buf_p = nxgep->rx_buf_pool_p->dma_buf_pool_p; 4318 4319 for (i = 0; i < ndmas; i++) { 4320 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 4321 if (nxge_rxdma_fatal_err_recover(nxgep, channel) != NXGE_OK) { 4322 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4323 "Could not recover channel %d", 4324 channel)); 4325 } 4326 } 4327 4328 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Reset IPP...")); 4329 4330 /* Reset IPP */ 4331 if (nxge_ipp_reset(nxgep) != NXGE_OK) { 4332 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4333 "nxge_rx_port_fatal_err_recover: " 4334 "Failed to reset IPP")); 4335 goto fail; 4336 } 4337 4338 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Reset RxMAC...")); 4339 4340 /* Reset RxMAC */ 4341 if (nxge_rx_mac_reset(nxgep) != NXGE_OK) { 4342 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4343 "nxge_rx_port_fatal_err_recover: " 4344 "Failed to reset RxMAC")); 4345 goto fail; 4346 } 4347 4348 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize IPP...")); 4349 4350 /* Re-Initialize IPP */ 4351 if (nxge_ipp_init(nxgep) != NXGE_OK) { 4352 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4353 "nxge_rx_port_fatal_err_recover: " 4354 "Failed to init IPP")); 4355 goto fail; 4356 } 4357 4358 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize RxMAC...")); 4359 4360 /* Re-Initialize RxMAC */ 4361 if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK) { 4362 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4363 "nxge_rx_port_fatal_err_recover: " 4364 "Failed to reset RxMAC")); 4365 goto fail; 4366 } 4367 4368 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-enable RxMAC...")); 4369 4370 /* Re-enable RxMAC */ 4371 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) { 4372 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4373 "nxge_rx_port_fatal_err_recover: " 4374 "Failed to enable RxMAC")); 4375 goto fail; 4376 } 4377 4378 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4379 "Recovery Successful, RxPort Restored")); 4380 4381 return (NXGE_OK); 4382 fail: 4383 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 4384 return (status); 4385 } 4386 4387 void 4388 nxge_rxdma_inject_err(p_nxge_t nxgep, uint32_t err_id, uint8_t chan) 4389 { 4390 rx_dma_ctl_stat_t cs; 4391 rx_ctl_dat_fifo_stat_t cdfs; 4392 4393 switch (err_id) { 4394 case NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR: 4395 case NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR: 4396 case NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR: 4397 case NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR: 4398 case NXGE_FM_EREPORT_RDMC_RBR_TMOUT: 4399 case NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR: 4400 case NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS: 4401 case NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR: 4402 case NXGE_FM_EREPORT_RDMC_RCRINCON: 4403 case NXGE_FM_EREPORT_RDMC_RCRFULL: 4404 case NXGE_FM_EREPORT_RDMC_RBRFULL: 4405 case NXGE_FM_EREPORT_RDMC_RBRLOGPAGE: 4406 case NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE: 4407 case NXGE_FM_EREPORT_RDMC_CONFIG_ERR: 4408 RXDMA_REG_READ64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 4409 chan, &cs.value); 4410 if (err_id == NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR) 4411 cs.bits.hdw.rcr_ack_err = 1; 4412 else if (err_id == NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR) 4413 cs.bits.hdw.dc_fifo_err = 1; 4414 else if (err_id == NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR) 4415 cs.bits.hdw.rcr_sha_par = 1; 4416 else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR) 4417 cs.bits.hdw.rbr_pre_par = 1; 4418 else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_TMOUT) 4419 cs.bits.hdw.rbr_tmout = 1; 4420 else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR) 4421 cs.bits.hdw.rsp_cnt_err = 1; 4422 else if (err_id == NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS) 4423 cs.bits.hdw.byte_en_bus = 1; 4424 else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR) 4425 cs.bits.hdw.rsp_dat_err = 1; 4426 else if (err_id == NXGE_FM_EREPORT_RDMC_CONFIG_ERR) 4427 cs.bits.hdw.config_err = 1; 4428 else if (err_id == NXGE_FM_EREPORT_RDMC_RCRINCON) 4429 cs.bits.hdw.rcrincon = 1; 4430 else if (err_id == NXGE_FM_EREPORT_RDMC_RCRFULL) 4431 cs.bits.hdw.rcrfull = 1; 4432 else if (err_id == NXGE_FM_EREPORT_RDMC_RBRFULL) 4433 cs.bits.hdw.rbrfull = 1; 4434 else if (err_id == NXGE_FM_EREPORT_RDMC_RBRLOGPAGE) 4435 cs.bits.hdw.rbrlogpage = 1; 4436 else if (err_id == NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE) 4437 cs.bits.hdw.cfiglogpage = 1; 4438 cmn_err(CE_NOTE, "!Write 0x%lx to RX_DMA_CTL_STAT_DBG_REG\n", 4439 cs.value); 4440 RXDMA_REG_WRITE64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 4441 chan, cs.value); 4442 break; 4443 case NXGE_FM_EREPORT_RDMC_ID_MISMATCH: 4444 case NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR: 4445 case NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR: 4446 cdfs.value = 0; 4447 if (err_id == NXGE_FM_EREPORT_RDMC_ID_MISMATCH) 4448 cdfs.bits.ldw.id_mismatch = (1 << nxgep->mac.portnum); 4449 else if (err_id == NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR) 4450 cdfs.bits.ldw.zcp_eop_err = (1 << nxgep->mac.portnum); 4451 else if (err_id == NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR) 4452 cdfs.bits.ldw.ipp_eop_err = (1 << nxgep->mac.portnum); 4453 cmn_err(CE_NOTE, 4454 "!Write 0x%lx to RX_CTL_DAT_FIFO_STAT_DBG_REG\n", 4455 cdfs.value); 4456 RXDMA_REG_WRITE64(nxgep->npi_handle, 4457 RX_CTL_DAT_FIFO_STAT_DBG_REG, chan, cdfs.value); 4458 break; 4459 case NXGE_FM_EREPORT_RDMC_DCF_ERR: 4460 break; 4461 case NXGE_FM_EREPORT_RDMC_COMPLETION_ERR: 4462 break; 4463 } 4464 } 4465 4466 4467 static uint16_t 4468 nxge_get_pktbuf_size(p_nxge_t nxgep, int bufsz_type, rbr_cfig_b_t rbr_cfgb) 4469 { 4470 uint16_t sz = RBR_BKSIZE_8K_BYTES; 4471 4472 switch (bufsz_type) { 4473 case RCR_PKTBUFSZ_0: 4474 switch (rbr_cfgb.bits.ldw.bufsz0) { 4475 case RBR_BUFSZ0_256B: 4476 sz = RBR_BUFSZ0_256_BYTES; 4477 break; 4478 case RBR_BUFSZ0_512B: 4479 sz = RBR_BUFSZ0_512B_BYTES; 4480 break; 4481 case RBR_BUFSZ0_1K: 4482 sz = RBR_BUFSZ0_1K_BYTES; 4483 break; 4484 case RBR_BUFSZ0_2K: 4485 sz = RBR_BUFSZ0_2K_BYTES; 4486 break; 4487 default: 4488 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4489 "nxge_get_pktbug_size: bad bufsz0")); 4490 break; 4491 } 4492 break; 4493 case RCR_PKTBUFSZ_1: 4494 switch (rbr_cfgb.bits.ldw.bufsz1) { 4495 case RBR_BUFSZ1_1K: 4496 sz = RBR_BUFSZ1_1K_BYTES; 4497 break; 4498 case RBR_BUFSZ1_2K: 4499 sz = RBR_BUFSZ1_2K_BYTES; 4500 break; 4501 case RBR_BUFSZ1_4K: 4502 sz = RBR_BUFSZ1_4K_BYTES; 4503 break; 4504 case RBR_BUFSZ1_8K: 4505 sz = RBR_BUFSZ1_8K_BYTES; 4506 break; 4507 default: 4508 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4509 "nxge_get_pktbug_size: bad bufsz1")); 4510 break; 4511 } 4512 break; 4513 case RCR_PKTBUFSZ_2: 4514 switch (rbr_cfgb.bits.ldw.bufsz2) { 4515 case RBR_BUFSZ2_2K: 4516 sz = RBR_BUFSZ2_2K_BYTES; 4517 break; 4518 case RBR_BUFSZ2_4K: 4519 sz = RBR_BUFSZ2_4K_BYTES; 4520 break; 4521 case RBR_BUFSZ2_8K: 4522 sz = RBR_BUFSZ2_8K_BYTES; 4523 break; 4524 case RBR_BUFSZ2_16K: 4525 sz = RBR_BUFSZ2_16K_BYTES; 4526 break; 4527 default: 4528 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4529 "nxge_get_pktbug_size: bad bufsz2")); 4530 break; 4531 } 4532 break; 4533 case RCR_SINGLE_BLOCK: 4534 switch (rbr_cfgb.bits.ldw.bksize) { 4535 case BKSIZE_4K: 4536 sz = RBR_BKSIZE_4K_BYTES; 4537 break; 4538 case BKSIZE_8K: 4539 sz = RBR_BKSIZE_8K_BYTES; 4540 break; 4541 case BKSIZE_16K: 4542 sz = RBR_BKSIZE_16K_BYTES; 4543 break; 4544 case BKSIZE_32K: 4545 sz = RBR_BKSIZE_32K_BYTES; 4546 break; 4547 default: 4548 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4549 "nxge_get_pktbug_size: bad bksize")); 4550 break; 4551 } 4552 break; 4553 default: 4554 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4555 "nxge_get_pktbug_size: bad bufsz_type")); 4556 break; 4557 } 4558 return (sz); 4559 } 4560