1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <sys/nxge/nxge_rxdma.h> 30 31 #define NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp) \ 32 (rdcgrp + nxgep->pt_config.hw_config.start_rdc_grpid) 33 #define NXGE_ACTUAL_RDC(nxgep, rdc) \ 34 (rdc + nxgep->pt_config.hw_config.start_rdc) 35 36 /* 37 * Globals: tunable parameters (/etc/system or adb) 38 * 39 */ 40 extern uint32_t nxge_rbr_size; 41 extern uint32_t nxge_rcr_size; 42 extern uint32_t nxge_rbr_spare_size; 43 44 extern uint32_t nxge_mblks_pending; 45 46 /* 47 * Tunable to reduce the amount of time spent in the 48 * ISR doing Rx Processing. 49 */ 50 extern uint32_t nxge_max_rx_pkts; 51 boolean_t nxge_jumbo_enable; 52 53 /* 54 * Tunables to manage the receive buffer blocks. 55 * 56 * nxge_rx_threshold_hi: copy all buffers. 57 * nxge_rx_bcopy_size_type: receive buffer block size type. 58 * nxge_rx_threshold_lo: copy only up to tunable block size type. 59 */ 60 extern nxge_rxbuf_threshold_t nxge_rx_threshold_hi; 61 extern nxge_rxbuf_type_t nxge_rx_buf_size_type; 62 extern nxge_rxbuf_threshold_t nxge_rx_threshold_lo; 63 64 static nxge_status_t nxge_map_rxdma(p_nxge_t); 65 static void nxge_unmap_rxdma(p_nxge_t); 66 67 static nxge_status_t nxge_rxdma_hw_start_common(p_nxge_t); 68 static void nxge_rxdma_hw_stop_common(p_nxge_t); 69 70 static nxge_status_t nxge_rxdma_hw_start(p_nxge_t); 71 static void nxge_rxdma_hw_stop(p_nxge_t); 72 73 static nxge_status_t nxge_map_rxdma_channel(p_nxge_t, uint16_t, 74 p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 75 uint32_t, 76 p_nxge_dma_common_t *, p_rx_rcr_ring_t *, 77 p_rx_mbox_t *); 78 static void nxge_unmap_rxdma_channel(p_nxge_t, uint16_t, 79 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 80 81 static nxge_status_t nxge_map_rxdma_channel_cfg_ring(p_nxge_t, 82 uint16_t, 83 p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 84 p_rx_rcr_ring_t *, p_rx_mbox_t *); 85 static void nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t, 86 p_rx_rcr_ring_t, p_rx_mbox_t); 87 88 static nxge_status_t nxge_map_rxdma_channel_buf_ring(p_nxge_t, 89 uint16_t, 90 p_nxge_dma_common_t *, 91 p_rx_rbr_ring_t *, uint32_t); 92 static void nxge_unmap_rxdma_channel_buf_ring(p_nxge_t, 93 p_rx_rbr_ring_t); 94 95 static nxge_status_t nxge_rxdma_start_channel(p_nxge_t, uint16_t, 96 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 97 static nxge_status_t nxge_rxdma_stop_channel(p_nxge_t, uint16_t); 98 99 mblk_t * 100 nxge_rx_pkts(p_nxge_t, uint_t, p_nxge_ldv_t, 101 p_rx_rcr_ring_t *, rx_dma_ctl_stat_t); 102 103 static void nxge_receive_packet(p_nxge_t, 104 p_rx_rcr_ring_t, 105 p_rcr_entry_t, 106 boolean_t *, 107 mblk_t **, mblk_t **); 108 109 nxge_status_t nxge_disable_rxdma_channel(p_nxge_t, uint16_t); 110 111 static p_rx_msg_t nxge_allocb(size_t, uint32_t, p_nxge_dma_common_t); 112 static void nxge_freeb(p_rx_msg_t); 113 static void nxge_rx_pkts_vring(p_nxge_t, uint_t, 114 p_nxge_ldv_t, rx_dma_ctl_stat_t); 115 static nxge_status_t nxge_rx_err_evnts(p_nxge_t, uint_t, 116 p_nxge_ldv_t, rx_dma_ctl_stat_t); 117 118 static nxge_status_t nxge_rxdma_handle_port_errors(p_nxge_t, 119 uint32_t, uint32_t); 120 121 static nxge_status_t nxge_rxbuf_index_info_init(p_nxge_t, 122 p_rx_rbr_ring_t); 123 124 125 static nxge_status_t 126 nxge_rxdma_fatal_err_recover(p_nxge_t, uint16_t); 127 128 nxge_status_t 129 nxge_rx_port_fatal_err_recover(p_nxge_t); 130 131 nxge_status_t 132 nxge_init_rxdma_channels(p_nxge_t nxgep) 133 { 134 nxge_status_t status = NXGE_OK; 135 136 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_init_rxdma_channels")); 137 138 status = nxge_map_rxdma(nxgep); 139 if (status != NXGE_OK) { 140 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 141 "<== nxge_init_rxdma: status 0x%x", status)); 142 return (status); 143 } 144 145 status = nxge_rxdma_hw_start_common(nxgep); 146 if (status != NXGE_OK) { 147 nxge_unmap_rxdma(nxgep); 148 } 149 150 status = nxge_rxdma_hw_start(nxgep); 151 if (status != NXGE_OK) { 152 nxge_unmap_rxdma(nxgep); 153 } 154 155 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 156 "<== nxge_init_rxdma_channels: status 0x%x", status)); 157 158 return (status); 159 } 160 161 void 162 nxge_uninit_rxdma_channels(p_nxge_t nxgep) 163 { 164 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channels")); 165 166 nxge_rxdma_hw_stop(nxgep); 167 nxge_rxdma_hw_stop_common(nxgep); 168 nxge_unmap_rxdma(nxgep); 169 170 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 171 "<== nxge_uinit_rxdma_channels")); 172 } 173 174 nxge_status_t 175 nxge_reset_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 176 { 177 npi_handle_t handle; 178 npi_status_t rs = NPI_SUCCESS; 179 nxge_status_t status = NXGE_OK; 180 181 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_reset_rxdma_channel")); 182 183 handle = NXGE_DEV_NPI_HANDLE(nxgep); 184 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 185 186 if (rs != NPI_SUCCESS) { 187 status = NXGE_ERROR | rs; 188 } 189 190 return (status); 191 } 192 193 void 194 nxge_rxdma_regs_dump_channels(p_nxge_t nxgep) 195 { 196 int i, ndmas; 197 uint16_t channel; 198 p_rx_rbr_rings_t rx_rbr_rings; 199 p_rx_rbr_ring_t *rbr_rings; 200 npi_handle_t handle; 201 202 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_regs_dump_channels")); 203 204 handle = NXGE_DEV_NPI_HANDLE(nxgep); 205 (void) npi_rxdma_dump_fzc_regs(handle); 206 207 rx_rbr_rings = nxgep->rx_rbr_rings; 208 if (rx_rbr_rings == NULL) { 209 NXGE_DEBUG_MSG((nxgep, RX_CTL, 210 "<== nxge_rxdma_regs_dump_channels: " 211 "NULL ring pointer")); 212 return; 213 } 214 if (rx_rbr_rings->rbr_rings == NULL) { 215 NXGE_DEBUG_MSG((nxgep, RX_CTL, 216 "<== nxge_rxdma_regs_dump_channels: " 217 " NULL rbr rings pointer")); 218 return; 219 } 220 221 ndmas = rx_rbr_rings->ndmas; 222 if (!ndmas) { 223 NXGE_DEBUG_MSG((nxgep, RX_CTL, 224 "<== nxge_rxdma_regs_dump_channels: no channel")); 225 return; 226 } 227 228 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 229 "==> nxge_rxdma_regs_dump_channels (ndmas %d)", ndmas)); 230 231 rbr_rings = rx_rbr_rings->rbr_rings; 232 for (i = 0; i < ndmas; i++) { 233 if (rbr_rings == NULL || rbr_rings[i] == NULL) { 234 continue; 235 } 236 channel = rbr_rings[i]->rdc; 237 (void) nxge_dump_rxdma_channel(nxgep, channel); 238 } 239 240 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_regs_dump")); 241 242 } 243 244 nxge_status_t 245 nxge_dump_rxdma_channel(p_nxge_t nxgep, uint8_t channel) 246 { 247 npi_handle_t handle; 248 npi_status_t rs = NPI_SUCCESS; 249 nxge_status_t status = NXGE_OK; 250 251 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_dump_rxdma_channel")); 252 253 handle = NXGE_DEV_NPI_HANDLE(nxgep); 254 rs = npi_rxdma_dump_rdc_regs(handle, channel); 255 256 if (rs != NPI_SUCCESS) { 257 status = NXGE_ERROR | rs; 258 } 259 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dump_rxdma_channel")); 260 return (status); 261 } 262 263 nxge_status_t 264 nxge_init_rxdma_channel_event_mask(p_nxge_t nxgep, uint16_t channel, 265 p_rx_dma_ent_msk_t mask_p) 266 { 267 npi_handle_t handle; 268 npi_status_t rs = NPI_SUCCESS; 269 nxge_status_t status = NXGE_OK; 270 271 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 272 "<== nxge_init_rxdma_channel_event_mask")); 273 274 handle = NXGE_DEV_NPI_HANDLE(nxgep); 275 rs = npi_rxdma_event_mask(handle, OP_SET, channel, mask_p); 276 if (rs != NPI_SUCCESS) { 277 status = NXGE_ERROR | rs; 278 } 279 280 return (status); 281 } 282 283 nxge_status_t 284 nxge_init_rxdma_channel_cntl_stat(p_nxge_t nxgep, uint16_t channel, 285 p_rx_dma_ctl_stat_t cs_p) 286 { 287 npi_handle_t handle; 288 npi_status_t rs = NPI_SUCCESS; 289 nxge_status_t status = NXGE_OK; 290 291 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 292 "<== nxge_init_rxdma_channel_cntl_stat")); 293 294 handle = NXGE_DEV_NPI_HANDLE(nxgep); 295 rs = npi_rxdma_control_status(handle, OP_SET, channel, cs_p); 296 297 if (rs != NPI_SUCCESS) { 298 status = NXGE_ERROR | rs; 299 } 300 301 return (status); 302 } 303 304 nxge_status_t 305 nxge_rxdma_cfg_rdcgrp_default_rdc(p_nxge_t nxgep, uint8_t rdcgrp, 306 uint8_t rdc) 307 { 308 npi_handle_t handle; 309 npi_status_t rs = NPI_SUCCESS; 310 p_nxge_dma_pt_cfg_t p_dma_cfgp; 311 p_nxge_rdc_grp_t rdc_grp_p; 312 uint8_t actual_rdcgrp, actual_rdc; 313 314 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 315 " ==> nxge_rxdma_cfg_rdcgrp_default_rdc")); 316 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 317 318 handle = NXGE_DEV_NPI_HANDLE(nxgep); 319 320 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdcgrp]; 321 rdc_grp_p->rdc[0] = rdc; 322 323 actual_rdcgrp = NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp); 324 actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc); 325 326 rs = npi_rxdma_cfg_rdc_table_default_rdc(handle, actual_rdcgrp, 327 actual_rdc); 328 329 if (rs != NPI_SUCCESS) { 330 return (NXGE_ERROR | rs); 331 } 332 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 333 " <== nxge_rxdma_cfg_rdcgrp_default_rdc")); 334 return (NXGE_OK); 335 } 336 337 nxge_status_t 338 nxge_rxdma_cfg_port_default_rdc(p_nxge_t nxgep, uint8_t port, uint8_t rdc) 339 { 340 npi_handle_t handle; 341 342 uint8_t actual_rdc; 343 npi_status_t rs = NPI_SUCCESS; 344 345 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 346 " ==> nxge_rxdma_cfg_port_default_rdc")); 347 348 handle = NXGE_DEV_NPI_HANDLE(nxgep); 349 actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc); 350 rs = npi_rxdma_cfg_default_port_rdc(handle, port, actual_rdc); 351 352 353 if (rs != NPI_SUCCESS) { 354 return (NXGE_ERROR | rs); 355 } 356 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 357 " <== nxge_rxdma_cfg_port_default_rdc")); 358 359 return (NXGE_OK); 360 } 361 362 nxge_status_t 363 nxge_rxdma_cfg_rcr_threshold(p_nxge_t nxgep, uint8_t channel, 364 uint16_t pkts) 365 { 366 npi_status_t rs = NPI_SUCCESS; 367 npi_handle_t handle; 368 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 369 " ==> nxge_rxdma_cfg_rcr_threshold")); 370 handle = NXGE_DEV_NPI_HANDLE(nxgep); 371 372 rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, pkts); 373 374 if (rs != NPI_SUCCESS) { 375 return (NXGE_ERROR | rs); 376 } 377 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_threshold")); 378 return (NXGE_OK); 379 } 380 381 nxge_status_t 382 nxge_rxdma_cfg_rcr_timeout(p_nxge_t nxgep, uint8_t channel, 383 uint16_t tout, uint8_t enable) 384 { 385 npi_status_t rs = NPI_SUCCESS; 386 npi_handle_t handle; 387 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " ==> nxge_rxdma_cfg_rcr_timeout")); 388 handle = NXGE_DEV_NPI_HANDLE(nxgep); 389 if (enable == 0) { 390 rs = npi_rxdma_cfg_rdc_rcr_timeout_disable(handle, channel); 391 } else { 392 rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 393 tout); 394 } 395 396 if (rs != NPI_SUCCESS) { 397 return (NXGE_ERROR | rs); 398 } 399 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_timeout")); 400 return (NXGE_OK); 401 } 402 403 nxge_status_t 404 nxge_enable_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 405 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 406 { 407 npi_handle_t handle; 408 rdc_desc_cfg_t rdc_desc; 409 p_rcrcfig_b_t cfgb_p; 410 npi_status_t rs = NPI_SUCCESS; 411 412 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel")); 413 handle = NXGE_DEV_NPI_HANDLE(nxgep); 414 /* 415 * Use configuration data composed at init time. 416 * Write to hardware the receive ring configurations. 417 */ 418 rdc_desc.mbox_enable = 1; 419 rdc_desc.mbox_addr = mbox_p->mbox_addr; 420 NXGE_DEBUG_MSG((nxgep, RX_CTL, 421 "==> nxge_enable_rxdma_channel: mboxp $%p($%p)", 422 mbox_p->mbox_addr, rdc_desc.mbox_addr)); 423 424 rdc_desc.rbr_len = rbr_p->rbb_max; 425 rdc_desc.rbr_addr = rbr_p->rbr_addr; 426 427 switch (nxgep->rx_bksize_code) { 428 case RBR_BKSIZE_4K: 429 rdc_desc.page_size = SIZE_4KB; 430 break; 431 case RBR_BKSIZE_8K: 432 rdc_desc.page_size = SIZE_8KB; 433 break; 434 case RBR_BKSIZE_16K: 435 rdc_desc.page_size = SIZE_16KB; 436 break; 437 case RBR_BKSIZE_32K: 438 rdc_desc.page_size = SIZE_32KB; 439 break; 440 } 441 442 rdc_desc.size0 = rbr_p->npi_pkt_buf_size0; 443 rdc_desc.valid0 = 1; 444 445 rdc_desc.size1 = rbr_p->npi_pkt_buf_size1; 446 rdc_desc.valid1 = 1; 447 448 rdc_desc.size2 = rbr_p->npi_pkt_buf_size2; 449 rdc_desc.valid2 = 1; 450 451 rdc_desc.full_hdr = rcr_p->full_hdr_flag; 452 rdc_desc.offset = rcr_p->sw_priv_hdr_len; 453 454 rdc_desc.rcr_len = rcr_p->comp_size; 455 rdc_desc.rcr_addr = rcr_p->rcr_addr; 456 457 cfgb_p = &(rcr_p->rcr_cfgb); 458 rdc_desc.rcr_threshold = cfgb_p->bits.ldw.pthres; 459 rdc_desc.rcr_timeout = cfgb_p->bits.ldw.timeout; 460 rdc_desc.rcr_timeout_enable = cfgb_p->bits.ldw.entout; 461 462 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 463 "rbr_len qlen %d pagesize code %d rcr_len %d", 464 rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len)); 465 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 466 "size 0 %d size 1 %d size 2 %d", 467 rbr_p->npi_pkt_buf_size0, rbr_p->npi_pkt_buf_size1, 468 rbr_p->npi_pkt_buf_size2)); 469 470 rs = npi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc, &rdc_desc); 471 if (rs != NPI_SUCCESS) { 472 return (NXGE_ERROR | rs); 473 } 474 475 /* 476 * Enable the timeout and threshold. 477 */ 478 rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, 479 rdc_desc.rcr_threshold); 480 if (rs != NPI_SUCCESS) { 481 return (NXGE_ERROR | rs); 482 } 483 484 rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 485 rdc_desc.rcr_timeout); 486 if (rs != NPI_SUCCESS) { 487 return (NXGE_ERROR | rs); 488 } 489 490 /* Enable the DMA */ 491 rs = npi_rxdma_cfg_rdc_enable(handle, channel); 492 if (rs != NPI_SUCCESS) { 493 return (NXGE_ERROR | rs); 494 } 495 496 /* Kick the DMA engine. */ 497 npi_rxdma_rdc_rbr_kick(handle, channel, rbr_p->rbb_max); 498 /* Clear the rbr empty bit */ 499 (void) npi_rxdma_channel_rbr_empty_clear(handle, channel); 500 501 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_enable_rxdma_channel")); 502 503 return (NXGE_OK); 504 } 505 506 nxge_status_t 507 nxge_disable_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 508 { 509 npi_handle_t handle; 510 npi_status_t rs = NPI_SUCCESS; 511 512 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_disable_rxdma_channel")); 513 handle = NXGE_DEV_NPI_HANDLE(nxgep); 514 515 /* disable the DMA */ 516 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 517 if (rs != NPI_SUCCESS) { 518 NXGE_DEBUG_MSG((nxgep, RX_CTL, 519 "<== nxge_disable_rxdma_channel:failed (0x%x)", 520 rs)); 521 return (NXGE_ERROR | rs); 522 } 523 524 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_disable_rxdma_channel")); 525 return (NXGE_OK); 526 } 527 528 nxge_status_t 529 nxge_rxdma_channel_rcrflush(p_nxge_t nxgep, uint8_t channel) 530 { 531 npi_handle_t handle; 532 nxge_status_t status = NXGE_OK; 533 534 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 535 "<== nxge_init_rxdma_channel_rcrflush")); 536 537 handle = NXGE_DEV_NPI_HANDLE(nxgep); 538 npi_rxdma_rdc_rcr_flush(handle, channel); 539 540 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 541 "<== nxge_init_rxdma_channel_rcrflsh")); 542 return (status); 543 544 } 545 546 #define MID_INDEX(l, r) ((r + l + 1) >> 1) 547 548 #define TO_LEFT -1 549 #define TO_RIGHT 1 550 #define BOTH_RIGHT (TO_RIGHT + TO_RIGHT) 551 #define BOTH_LEFT (TO_LEFT + TO_LEFT) 552 #define IN_MIDDLE (TO_RIGHT + TO_LEFT) 553 #define NO_HINT 0xffffffff 554 555 /*ARGSUSED*/ 556 nxge_status_t 557 nxge_rxbuf_pp_to_vp(p_nxge_t nxgep, p_rx_rbr_ring_t rbr_p, 558 uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp, 559 uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index) 560 { 561 int bufsize; 562 uint64_t pktbuf_pp; 563 uint64_t dvma_addr; 564 rxring_info_t *ring_info; 565 int base_side, end_side; 566 int r_index, l_index, anchor_index; 567 int found, search_done; 568 uint32_t offset, chunk_size, block_size, page_size_mask; 569 uint32_t chunk_index, block_index, total_index; 570 int max_iterations, iteration; 571 rxbuf_index_info_t *bufinfo; 572 573 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_rxbuf_pp_to_vp")); 574 575 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 576 "==> nxge_rxbuf_pp_to_vp: buf_pp $%p btype %d", 577 pkt_buf_addr_pp, 578 pktbufsz_type)); 579 #if defined(__i386) 580 pktbuf_pp = (uint64_t)(uint32_t)pkt_buf_addr_pp; 581 #else 582 pktbuf_pp = (uint64_t)pkt_buf_addr_pp; 583 #endif 584 585 switch (pktbufsz_type) { 586 case 0: 587 bufsize = rbr_p->pkt_buf_size0; 588 break; 589 case 1: 590 bufsize = rbr_p->pkt_buf_size1; 591 break; 592 case 2: 593 bufsize = rbr_p->pkt_buf_size2; 594 break; 595 case RCR_SINGLE_BLOCK: 596 bufsize = 0; 597 anchor_index = 0; 598 break; 599 default: 600 return (NXGE_ERROR); 601 } 602 603 if (rbr_p->num_blocks == 1) { 604 anchor_index = 0; 605 ring_info = rbr_p->ring_info; 606 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 607 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 608 "==> nxge_rxbuf_pp_to_vp: (found, 1 block) " 609 "buf_pp $%p btype %d anchor_index %d " 610 "bufinfo $%p", 611 pkt_buf_addr_pp, 612 pktbufsz_type, 613 anchor_index, 614 bufinfo)); 615 616 goto found_index; 617 } 618 619 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 620 "==> nxge_rxbuf_pp_to_vp: " 621 "buf_pp $%p btype %d anchor_index %d", 622 pkt_buf_addr_pp, 623 pktbufsz_type, 624 anchor_index)); 625 626 ring_info = rbr_p->ring_info; 627 found = B_FALSE; 628 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 629 iteration = 0; 630 max_iterations = ring_info->max_iterations; 631 /* 632 * First check if this block has been seen 633 * recently. This is indicated by a hint which 634 * is initialized when the first buffer of the block 635 * is seen. The hint is reset when the last buffer of 636 * the block has been processed. 637 * As three block sizes are supported, three hints 638 * are kept. The idea behind the hints is that once 639 * the hardware uses a block for a buffer of that 640 * size, it will use it exclusively for that size 641 * and will use it until it is exhausted. It is assumed 642 * that there would a single block being used for the same 643 * buffer sizes at any given time. 644 */ 645 if (ring_info->hint[pktbufsz_type] != NO_HINT) { 646 anchor_index = ring_info->hint[pktbufsz_type]; 647 dvma_addr = bufinfo[anchor_index].dvma_addr; 648 chunk_size = bufinfo[anchor_index].buf_size; 649 if ((pktbuf_pp >= dvma_addr) && 650 (pktbuf_pp < (dvma_addr + chunk_size))) { 651 found = B_TRUE; 652 /* 653 * check if this is the last buffer in the block 654 * If so, then reset the hint for the size; 655 */ 656 657 if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size)) 658 ring_info->hint[pktbufsz_type] = NO_HINT; 659 } 660 } 661 662 if (found == B_FALSE) { 663 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 664 "==> nxge_rxbuf_pp_to_vp: (!found)" 665 "buf_pp $%p btype %d anchor_index %d", 666 pkt_buf_addr_pp, 667 pktbufsz_type, 668 anchor_index)); 669 670 /* 671 * This is the first buffer of the block of this 672 * size. Need to search the whole information 673 * array. 674 * the search algorithm uses a binary tree search 675 * algorithm. It assumes that the information is 676 * already sorted with increasing order 677 * info[0] < info[1] < info[2] .... < info[n-1] 678 * where n is the size of the information array 679 */ 680 r_index = rbr_p->num_blocks - 1; 681 l_index = 0; 682 search_done = B_FALSE; 683 anchor_index = MID_INDEX(r_index, l_index); 684 while (search_done == B_FALSE) { 685 if ((r_index == l_index) || 686 (iteration >= max_iterations)) 687 search_done = B_TRUE; 688 end_side = TO_RIGHT; /* to the right */ 689 base_side = TO_LEFT; /* to the left */ 690 /* read the DVMA address information and sort it */ 691 dvma_addr = bufinfo[anchor_index].dvma_addr; 692 chunk_size = bufinfo[anchor_index].buf_size; 693 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 694 "==> nxge_rxbuf_pp_to_vp: (searching)" 695 "buf_pp $%p btype %d " 696 "anchor_index %d chunk_size %d dvmaaddr $%p", 697 pkt_buf_addr_pp, 698 pktbufsz_type, 699 anchor_index, 700 chunk_size, 701 dvma_addr)); 702 703 if (pktbuf_pp >= dvma_addr) 704 base_side = TO_RIGHT; /* to the right */ 705 if (pktbuf_pp < (dvma_addr + chunk_size)) 706 end_side = TO_LEFT; /* to the left */ 707 708 switch (base_side + end_side) { 709 case IN_MIDDLE: 710 /* found */ 711 found = B_TRUE; 712 search_done = B_TRUE; 713 if ((pktbuf_pp + bufsize) < 714 (dvma_addr + chunk_size)) 715 ring_info->hint[pktbufsz_type] = 716 bufinfo[anchor_index].buf_index; 717 break; 718 case BOTH_RIGHT: 719 /* not found: go to the right */ 720 l_index = anchor_index + 1; 721 anchor_index = 722 MID_INDEX(r_index, l_index); 723 break; 724 725 case BOTH_LEFT: 726 /* not found: go to the left */ 727 r_index = anchor_index - 1; 728 anchor_index = MID_INDEX(r_index, 729 l_index); 730 break; 731 default: /* should not come here */ 732 return (NXGE_ERROR); 733 } 734 iteration++; 735 } 736 737 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 738 "==> nxge_rxbuf_pp_to_vp: (search done)" 739 "buf_pp $%p btype %d anchor_index %d", 740 pkt_buf_addr_pp, 741 pktbufsz_type, 742 anchor_index)); 743 } 744 745 if (found == B_FALSE) { 746 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 747 "==> nxge_rxbuf_pp_to_vp: (search failed)" 748 "buf_pp $%p btype %d anchor_index %d", 749 pkt_buf_addr_pp, 750 pktbufsz_type, 751 anchor_index)); 752 return (NXGE_ERROR); 753 } 754 755 found_index: 756 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 757 "==> nxge_rxbuf_pp_to_vp: (FOUND1)" 758 "buf_pp $%p btype %d bufsize %d anchor_index %d", 759 pkt_buf_addr_pp, 760 pktbufsz_type, 761 bufsize, 762 anchor_index)); 763 764 /* index of the first block in this chunk */ 765 chunk_index = bufinfo[anchor_index].start_index; 766 dvma_addr = bufinfo[anchor_index].dvma_addr; 767 page_size_mask = ring_info->block_size_mask; 768 769 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 770 "==> nxge_rxbuf_pp_to_vp: (FOUND3), get chunk)" 771 "buf_pp $%p btype %d bufsize %d " 772 "anchor_index %d chunk_index %d dvma $%p", 773 pkt_buf_addr_pp, 774 pktbufsz_type, 775 bufsize, 776 anchor_index, 777 chunk_index, 778 dvma_addr)); 779 780 offset = pktbuf_pp - dvma_addr; /* offset within the chunk */ 781 block_size = rbr_p->block_size; /* System block(page) size */ 782 783 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 784 "==> nxge_rxbuf_pp_to_vp: (FOUND4), get chunk)" 785 "buf_pp $%p btype %d bufsize %d " 786 "anchor_index %d chunk_index %d dvma $%p " 787 "offset %d block_size %d", 788 pkt_buf_addr_pp, 789 pktbufsz_type, 790 bufsize, 791 anchor_index, 792 chunk_index, 793 dvma_addr, 794 offset, 795 block_size)); 796 797 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> getting total index")); 798 799 block_index = (offset / block_size); /* index within chunk */ 800 total_index = chunk_index + block_index; 801 802 803 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 804 "==> nxge_rxbuf_pp_to_vp: " 805 "total_index %d dvma_addr $%p " 806 "offset %d block_size %d " 807 "block_index %d ", 808 total_index, dvma_addr, 809 offset, block_size, 810 block_index)); 811 #if defined(__i386) 812 *pkt_buf_addr_p = (uint64_t *)((uint32_t)bufinfo[anchor_index].kaddr + 813 (uint32_t)offset); 814 #else 815 *pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr + 816 (uint64_t)offset); 817 #endif 818 819 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 820 "==> nxge_rxbuf_pp_to_vp: " 821 "total_index %d dvma_addr $%p " 822 "offset %d block_size %d " 823 "block_index %d " 824 "*pkt_buf_addr_p $%p", 825 total_index, dvma_addr, 826 offset, block_size, 827 block_index, 828 *pkt_buf_addr_p)); 829 830 831 *msg_index = total_index; 832 *bufoffset = (offset & page_size_mask); 833 834 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 835 "==> nxge_rxbuf_pp_to_vp: get msg index: " 836 "msg_index %d bufoffset_index %d", 837 *msg_index, 838 *bufoffset)); 839 840 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rxbuf_pp_to_vp")); 841 842 return (NXGE_OK); 843 } 844 845 /* 846 * used by quick sort (qsort) function 847 * to perform comparison 848 */ 849 static int 850 nxge_sort_compare(const void *p1, const void *p2) 851 { 852 853 rxbuf_index_info_t *a, *b; 854 855 a = (rxbuf_index_info_t *)p1; 856 b = (rxbuf_index_info_t *)p2; 857 858 if (a->dvma_addr > b->dvma_addr) 859 return (1); 860 if (a->dvma_addr < b->dvma_addr) 861 return (-1); 862 return (0); 863 } 864 865 866 867 /* 868 * grabbed this sort implementation from common/syscall/avl.c 869 * 870 */ 871 /* 872 * Generic shellsort, from K&R (1st ed, p 58.), somewhat modified. 873 * v = Ptr to array/vector of objs 874 * n = # objs in the array 875 * s = size of each obj (must be multiples of a word size) 876 * f = ptr to function to compare two objs 877 * returns (-1 = less than, 0 = equal, 1 = greater than 878 */ 879 void 880 nxge_ksort(caddr_t v, int n, int s, int (*f)()) 881 { 882 int g, i, j, ii; 883 unsigned int *p1, *p2; 884 unsigned int tmp; 885 886 /* No work to do */ 887 if (v == NULL || n <= 1) 888 return; 889 /* Sanity check on arguments */ 890 ASSERT(((uintptr_t)v & 0x3) == 0 && (s & 0x3) == 0); 891 ASSERT(s > 0); 892 893 for (g = n / 2; g > 0; g /= 2) { 894 for (i = g; i < n; i++) { 895 for (j = i - g; j >= 0 && 896 (*f)(v + j * s, v + (j + g) * s) == 1; 897 j -= g) { 898 p1 = (unsigned *)(v + j * s); 899 p2 = (unsigned *)(v + (j + g) * s); 900 for (ii = 0; ii < s / 4; ii++) { 901 tmp = *p1; 902 *p1++ = *p2; 903 *p2++ = tmp; 904 } 905 } 906 } 907 } 908 } 909 910 /* 911 * Initialize data structures required for rxdma 912 * buffer dvma->vmem address lookup 913 */ 914 /*ARGSUSED*/ 915 static nxge_status_t 916 nxge_rxbuf_index_info_init(p_nxge_t nxgep, p_rx_rbr_ring_t rbrp) 917 { 918 919 int index; 920 rxring_info_t *ring_info; 921 int max_iteration = 0, max_index = 0; 922 923 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_rxbuf_index_info_init")); 924 925 ring_info = rbrp->ring_info; 926 ring_info->hint[0] = NO_HINT; 927 ring_info->hint[1] = NO_HINT; 928 ring_info->hint[2] = NO_HINT; 929 max_index = rbrp->num_blocks; 930 931 /* read the DVMA address information and sort it */ 932 /* do init of the information array */ 933 934 935 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 936 " nxge_rxbuf_index_info_init Sort ptrs")); 937 938 /* sort the array */ 939 nxge_ksort((void *)ring_info->buffer, max_index, 940 sizeof (rxbuf_index_info_t), nxge_sort_compare); 941 942 943 944 for (index = 0; index < max_index; index++) { 945 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 946 " nxge_rxbuf_index_info_init: sorted chunk %d " 947 " ioaddr $%p kaddr $%p size %x", 948 index, ring_info->buffer[index].dvma_addr, 949 ring_info->buffer[index].kaddr, 950 ring_info->buffer[index].buf_size)); 951 } 952 953 max_iteration = 0; 954 while (max_index >= (1ULL << max_iteration)) 955 max_iteration++; 956 ring_info->max_iterations = max_iteration + 1; 957 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 958 " nxge_rxbuf_index_info_init Find max iter %d", 959 ring_info->max_iterations)); 960 961 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxbuf_index_info_init")); 962 return (NXGE_OK); 963 } 964 965 /* ARGSUSED */ 966 void 967 nxge_dump_rcr_entry(p_nxge_t nxgep, p_rcr_entry_t entry_p) 968 { 969 #ifdef NXGE_DEBUG 970 971 uint32_t bptr; 972 uint64_t pp; 973 974 bptr = entry_p->bits.hdw.pkt_buf_addr; 975 976 NXGE_DEBUG_MSG((nxgep, RX_CTL, 977 "\trcr entry $%p " 978 "\trcr entry 0x%0llx " 979 "\trcr entry 0x%08x " 980 "\trcr entry 0x%08x " 981 "\tvalue 0x%0llx\n" 982 "\tmulti = %d\n" 983 "\tpkt_type = 0x%x\n" 984 "\tzero_copy = %d\n" 985 "\tnoport = %d\n" 986 "\tpromis = %d\n" 987 "\terror = 0x%04x\n" 988 "\tdcf_err = 0x%01x\n" 989 "\tl2_len = %d\n" 990 "\tpktbufsize = %d\n" 991 "\tpkt_buf_addr = $%p\n" 992 "\tpkt_buf_addr (<< 6) = $%p\n", 993 entry_p, 994 *(int64_t *)entry_p, 995 *(int32_t *)entry_p, 996 *(int32_t *)((char *)entry_p + 32), 997 entry_p->value, 998 entry_p->bits.hdw.multi, 999 entry_p->bits.hdw.pkt_type, 1000 entry_p->bits.hdw.zero_copy, 1001 entry_p->bits.hdw.noport, 1002 entry_p->bits.hdw.promis, 1003 entry_p->bits.hdw.error, 1004 entry_p->bits.hdw.dcf_err, 1005 entry_p->bits.hdw.l2_len, 1006 entry_p->bits.hdw.pktbufsz, 1007 bptr, 1008 entry_p->bits.ldw.pkt_buf_addr)); 1009 1010 pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) << 1011 RCR_PKT_BUF_ADDR_SHIFT; 1012 1013 NXGE_DEBUG_MSG((nxgep, RX_CTL, "rcr pp 0x%llx l2 len %d", 1014 pp, (*(int64_t *)entry_p >> 40) & 0x3fff)); 1015 #endif 1016 } 1017 1018 void 1019 nxge_rxdma_regs_dump(p_nxge_t nxgep, int rdc) 1020 { 1021 npi_handle_t handle; 1022 rbr_stat_t rbr_stat; 1023 addr44_t hd_addr; 1024 addr44_t tail_addr; 1025 uint16_t qlen; 1026 1027 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1028 "==> nxge_rxdma_regs_dump: rdc channel %d", rdc)); 1029 1030 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1031 1032 /* RBR head */ 1033 hd_addr.addr = 0; 1034 (void) npi_rxdma_rdc_rbr_head_get(handle, rdc, &hd_addr); 1035 #if defined(__i386) 1036 printf("nxge_rxdma_regs_dump: got hdptr $%p \n", 1037 (void *)(uint32_t)hd_addr.addr); 1038 #else 1039 printf("nxge_rxdma_regs_dump: got hdptr $%p \n", 1040 (void *)hd_addr.addr); 1041 #endif 1042 1043 /* RBR stats */ 1044 (void) npi_rxdma_rdc_rbr_stat_get(handle, rdc, &rbr_stat); 1045 printf("nxge_rxdma_regs_dump: rbr len %d \n", rbr_stat.bits.ldw.qlen); 1046 1047 /* RCR tail */ 1048 tail_addr.addr = 0; 1049 (void) npi_rxdma_rdc_rcr_tail_get(handle, rdc, &tail_addr); 1050 #if defined(__i386) 1051 printf("nxge_rxdma_regs_dump: got tail ptr $%p \n", 1052 (void *)(uint32_t)tail_addr.addr); 1053 #else 1054 printf("nxge_rxdma_regs_dump: got tail ptr $%p \n", 1055 (void *)tail_addr.addr); 1056 #endif 1057 1058 /* RCR qlen */ 1059 (void) npi_rxdma_rdc_rcr_qlen_get(handle, rdc, &qlen); 1060 printf("nxge_rxdma_regs_dump: rcr len %x \n", qlen); 1061 1062 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1063 "<== nxge_rxdma_regs_dump: rdc rdc %d", rdc)); 1064 } 1065 1066 void 1067 nxge_rxdma_stop(p_nxge_t nxgep) 1068 { 1069 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop")); 1070 1071 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 1072 (void) nxge_rx_mac_disable(nxgep); 1073 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 1074 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop")); 1075 } 1076 1077 void 1078 nxge_rxdma_stop_reinit(p_nxge_t nxgep) 1079 { 1080 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_reinit")); 1081 1082 (void) nxge_rxdma_stop(nxgep); 1083 (void) nxge_uninit_rxdma_channels(nxgep); 1084 (void) nxge_init_rxdma_channels(nxgep); 1085 1086 #ifndef AXIS_DEBUG_LB 1087 (void) nxge_xcvr_init(nxgep); 1088 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 1089 #endif 1090 (void) nxge_rx_mac_enable(nxgep); 1091 1092 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_reinit")); 1093 } 1094 1095 nxge_status_t 1096 nxge_rxdma_hw_mode(p_nxge_t nxgep, boolean_t enable) 1097 { 1098 int i, ndmas; 1099 uint16_t channel; 1100 p_rx_rbr_rings_t rx_rbr_rings; 1101 p_rx_rbr_ring_t *rbr_rings; 1102 npi_handle_t handle; 1103 npi_status_t rs = NPI_SUCCESS; 1104 nxge_status_t status = NXGE_OK; 1105 1106 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1107 "==> nxge_rxdma_hw_mode: mode %d", enable)); 1108 1109 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1110 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1111 "<== nxge_rxdma_mode: not initialized")); 1112 return (NXGE_ERROR); 1113 } 1114 1115 rx_rbr_rings = nxgep->rx_rbr_rings; 1116 if (rx_rbr_rings == NULL) { 1117 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1118 "<== nxge_rxdma_mode: NULL ring pointer")); 1119 return (NXGE_ERROR); 1120 } 1121 if (rx_rbr_rings->rbr_rings == NULL) { 1122 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1123 "<== nxge_rxdma_mode: NULL rbr rings pointer")); 1124 return (NXGE_ERROR); 1125 } 1126 1127 ndmas = rx_rbr_rings->ndmas; 1128 if (!ndmas) { 1129 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1130 "<== nxge_rxdma_mode: no channel")); 1131 return (NXGE_ERROR); 1132 } 1133 1134 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1135 "==> nxge_rxdma_mode (ndmas %d)", ndmas)); 1136 1137 rbr_rings = rx_rbr_rings->rbr_rings; 1138 1139 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1140 for (i = 0; i < ndmas; i++) { 1141 if (rbr_rings == NULL || rbr_rings[i] == NULL) { 1142 continue; 1143 } 1144 channel = rbr_rings[i]->rdc; 1145 if (enable) { 1146 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1147 "==> nxge_rxdma_hw_mode: channel %d (enable)", 1148 channel)); 1149 rs = npi_rxdma_cfg_rdc_enable(handle, channel); 1150 } else { 1151 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1152 "==> nxge_rxdma_hw_mode: channel %d (disable)", 1153 channel)); 1154 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 1155 } 1156 } 1157 1158 status = ((rs == NPI_SUCCESS) ? NXGE_OK : NXGE_ERROR | rs); 1159 1160 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1161 "<== nxge_rxdma_hw_mode: status 0x%x", status)); 1162 1163 return (status); 1164 } 1165 1166 void 1167 nxge_rxdma_enable_channel(p_nxge_t nxgep, uint16_t channel) 1168 { 1169 npi_handle_t handle; 1170 1171 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 1172 "==> nxge_rxdma_enable_channel: channel %d", channel)); 1173 1174 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1175 (void) npi_rxdma_cfg_rdc_enable(handle, channel); 1176 1177 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_enable_channel")); 1178 } 1179 1180 void 1181 nxge_rxdma_disable_channel(p_nxge_t nxgep, uint16_t channel) 1182 { 1183 npi_handle_t handle; 1184 1185 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 1186 "==> nxge_rxdma_disable_channel: channel %d", channel)); 1187 1188 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1189 (void) npi_rxdma_cfg_rdc_disable(handle, channel); 1190 1191 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_disable_channel")); 1192 } 1193 1194 void 1195 nxge_hw_start_rx(p_nxge_t nxgep) 1196 { 1197 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_start_rx")); 1198 1199 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 1200 (void) nxge_rx_mac_enable(nxgep); 1201 1202 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_start_rx")); 1203 } 1204 1205 /*ARGSUSED*/ 1206 void 1207 nxge_fixup_rxdma_rings(p_nxge_t nxgep) 1208 { 1209 int i, ndmas; 1210 uint16_t rdc; 1211 p_rx_rbr_rings_t rx_rbr_rings; 1212 p_rx_rbr_ring_t *rbr_rings; 1213 p_rx_rcr_rings_t rx_rcr_rings; 1214 1215 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_fixup_rxdma_rings")); 1216 1217 rx_rbr_rings = nxgep->rx_rbr_rings; 1218 if (rx_rbr_rings == NULL) { 1219 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1220 "<== nxge_fixup_rxdma_rings: NULL ring pointer")); 1221 return; 1222 } 1223 ndmas = rx_rbr_rings->ndmas; 1224 if (!ndmas) { 1225 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1226 "<== nxge_fixup_rxdma_rings: no channel")); 1227 return; 1228 } 1229 1230 rx_rcr_rings = nxgep->rx_rcr_rings; 1231 if (rx_rcr_rings == NULL) { 1232 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1233 "<== nxge_fixup_rxdma_rings: NULL ring pointer")); 1234 return; 1235 } 1236 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1237 "==> nxge_fixup_rxdma_rings (ndmas %d)", ndmas)); 1238 1239 nxge_rxdma_hw_stop(nxgep); 1240 1241 rbr_rings = rx_rbr_rings->rbr_rings; 1242 for (i = 0; i < ndmas; i++) { 1243 rdc = rbr_rings[i]->rdc; 1244 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1245 "==> nxge_fixup_rxdma_rings: channel %d " 1246 "ring $%px", rdc, rbr_rings[i])); 1247 (void) nxge_rxdma_fixup_channel(nxgep, rdc, i); 1248 } 1249 1250 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_fixup_rxdma_rings")); 1251 } 1252 1253 void 1254 nxge_rxdma_fix_channel(p_nxge_t nxgep, uint16_t channel) 1255 { 1256 int i; 1257 1258 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fix_channel")); 1259 i = nxge_rxdma_get_ring_index(nxgep, channel); 1260 if (i < 0) { 1261 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1262 "<== nxge_rxdma_fix_channel: no entry found")); 1263 return; 1264 } 1265 1266 nxge_rxdma_fixup_channel(nxgep, channel, i); 1267 1268 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_txdma_fix_channel")); 1269 } 1270 1271 void 1272 nxge_rxdma_fixup_channel(p_nxge_t nxgep, uint16_t channel, int entry) 1273 { 1274 int ndmas; 1275 p_rx_rbr_rings_t rx_rbr_rings; 1276 p_rx_rbr_ring_t *rbr_rings; 1277 p_rx_rcr_rings_t rx_rcr_rings; 1278 p_rx_rcr_ring_t *rcr_rings; 1279 p_rx_mbox_areas_t rx_mbox_areas_p; 1280 p_rx_mbox_t *rx_mbox_p; 1281 p_nxge_dma_pool_t dma_buf_poolp; 1282 p_nxge_dma_pool_t dma_cntl_poolp; 1283 p_rx_rbr_ring_t rbrp; 1284 p_rx_rcr_ring_t rcrp; 1285 p_rx_mbox_t mboxp; 1286 p_nxge_dma_common_t dmap; 1287 nxge_status_t status = NXGE_OK; 1288 1289 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fixup_channel")); 1290 1291 (void) nxge_rxdma_stop_channel(nxgep, channel); 1292 1293 dma_buf_poolp = nxgep->rx_buf_pool_p; 1294 dma_cntl_poolp = nxgep->rx_cntl_pool_p; 1295 1296 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 1297 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1298 "<== nxge_rxdma_fixup_channel: buf not allocated")); 1299 return; 1300 } 1301 1302 ndmas = dma_buf_poolp->ndmas; 1303 if (!ndmas) { 1304 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1305 "<== nxge_rxdma_fixup_channel: no dma allocated")); 1306 return; 1307 } 1308 1309 rx_rbr_rings = nxgep->rx_rbr_rings; 1310 rx_rcr_rings = nxgep->rx_rcr_rings; 1311 rbr_rings = rx_rbr_rings->rbr_rings; 1312 rcr_rings = rx_rcr_rings->rcr_rings; 1313 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 1314 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 1315 1316 /* Reinitialize the receive block and completion rings */ 1317 rbrp = (p_rx_rbr_ring_t)rbr_rings[entry], 1318 rcrp = (p_rx_rcr_ring_t)rcr_rings[entry], 1319 mboxp = (p_rx_mbox_t)rx_mbox_p[entry]; 1320 1321 1322 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 1323 rbrp->rbr_rd_index = 0; 1324 rcrp->comp_rd_index = 0; 1325 rcrp->comp_wt_index = 0; 1326 1327 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 1328 bzero((caddr_t)dmap->kaddrp, dmap->alength); 1329 1330 status = nxge_rxdma_start_channel(nxgep, channel, 1331 rbrp, rcrp, mboxp); 1332 if (status != NXGE_OK) { 1333 goto nxge_rxdma_fixup_channel_fail; 1334 } 1335 if (status != NXGE_OK) { 1336 goto nxge_rxdma_fixup_channel_fail; 1337 } 1338 1339 nxge_rxdma_fixup_channel_fail: 1340 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1341 "==> nxge_rxdma_fixup_channel: failed (0x%08x)", status)); 1342 1343 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fixup_channel")); 1344 } 1345 1346 int 1347 nxge_rxdma_get_ring_index(p_nxge_t nxgep, uint16_t channel) 1348 { 1349 int i, ndmas; 1350 uint16_t rdc; 1351 p_rx_rbr_rings_t rx_rbr_rings; 1352 p_rx_rbr_ring_t *rbr_rings; 1353 1354 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1355 "==> nxge_rxdma_get_ring_index: channel %d", channel)); 1356 1357 rx_rbr_rings = nxgep->rx_rbr_rings; 1358 if (rx_rbr_rings == NULL) { 1359 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1360 "<== nxge_rxdma_get_ring_index: NULL ring pointer")); 1361 return (-1); 1362 } 1363 ndmas = rx_rbr_rings->ndmas; 1364 if (!ndmas) { 1365 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1366 "<== nxge_rxdma_get_ring_index: no channel")); 1367 return (-1); 1368 } 1369 1370 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1371 "==> nxge_rxdma_get_ring_index (ndmas %d)", ndmas)); 1372 1373 rbr_rings = rx_rbr_rings->rbr_rings; 1374 for (i = 0; i < ndmas; i++) { 1375 rdc = rbr_rings[i]->rdc; 1376 if (channel == rdc) { 1377 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1378 "==> nxge_rxdma_get_rbr_ring: " 1379 "channel %d (index %d) " 1380 "ring %d", channel, i, 1381 rbr_rings[i])); 1382 return (i); 1383 } 1384 } 1385 1386 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1387 "<== nxge_rxdma_get_rbr_ring_index: not found")); 1388 1389 return (-1); 1390 } 1391 1392 p_rx_rbr_ring_t 1393 nxge_rxdma_get_rbr_ring(p_nxge_t nxgep, uint16_t channel) 1394 { 1395 int i, ndmas; 1396 uint16_t rdc; 1397 p_rx_rbr_rings_t rx_rbr_rings; 1398 p_rx_rbr_ring_t *rbr_rings; 1399 1400 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1401 "==> nxge_rxdma_get_rbr_ring: channel %d", channel)); 1402 1403 rx_rbr_rings = nxgep->rx_rbr_rings; 1404 if (rx_rbr_rings == NULL) { 1405 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1406 "<== nxge_rxdma_get_rbr_ring: NULL ring pointer")); 1407 return (NULL); 1408 } 1409 ndmas = rx_rbr_rings->ndmas; 1410 if (!ndmas) { 1411 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1412 "<== nxge_rxdma_get_rbr_ring: no channel")); 1413 return (NULL); 1414 } 1415 1416 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1417 "==> nxge_rxdma_get_ring (ndmas %d)", ndmas)); 1418 1419 rbr_rings = rx_rbr_rings->rbr_rings; 1420 for (i = 0; i < ndmas; i++) { 1421 rdc = rbr_rings[i]->rdc; 1422 if (channel == rdc) { 1423 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1424 "==> nxge_rxdma_get_rbr_ring: channel %d " 1425 "ring $%p", channel, rbr_rings[i])); 1426 return (rbr_rings[i]); 1427 } 1428 } 1429 1430 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1431 "<== nxge_rxdma_get_rbr_ring: not found")); 1432 1433 return (NULL); 1434 } 1435 1436 p_rx_rcr_ring_t 1437 nxge_rxdma_get_rcr_ring(p_nxge_t nxgep, uint16_t channel) 1438 { 1439 int i, ndmas; 1440 uint16_t rdc; 1441 p_rx_rcr_rings_t rx_rcr_rings; 1442 p_rx_rcr_ring_t *rcr_rings; 1443 1444 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1445 "==> nxge_rxdma_get_rcr_ring: channel %d", channel)); 1446 1447 rx_rcr_rings = nxgep->rx_rcr_rings; 1448 if (rx_rcr_rings == NULL) { 1449 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1450 "<== nxge_rxdma_get_rcr_ring: NULL ring pointer")); 1451 return (NULL); 1452 } 1453 ndmas = rx_rcr_rings->ndmas; 1454 if (!ndmas) { 1455 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1456 "<== nxge_rxdma_get_rcr_ring: no channel")); 1457 return (NULL); 1458 } 1459 1460 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1461 "==> nxge_rxdma_get_rcr_ring (ndmas %d)", ndmas)); 1462 1463 rcr_rings = rx_rcr_rings->rcr_rings; 1464 for (i = 0; i < ndmas; i++) { 1465 rdc = rcr_rings[i]->rdc; 1466 if (channel == rdc) { 1467 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1468 "==> nxge_rxdma_get_rcr_ring: channel %d " 1469 "ring $%p", channel, rcr_rings[i])); 1470 return (rcr_rings[i]); 1471 } 1472 } 1473 1474 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1475 "<== nxge_rxdma_get_rcr_ring: not found")); 1476 1477 return (NULL); 1478 } 1479 1480 /* 1481 * Static functions start here. 1482 */ 1483 static p_rx_msg_t 1484 nxge_allocb(size_t size, uint32_t pri, p_nxge_dma_common_t dmabuf_p) 1485 { 1486 p_rx_msg_t nxge_mp = NULL; 1487 p_nxge_dma_common_t dmamsg_p; 1488 uchar_t *buffer; 1489 1490 nxge_mp = KMEM_ZALLOC(sizeof (rx_msg_t), KM_NOSLEEP); 1491 if (nxge_mp == NULL) { 1492 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 1493 "Allocation of a rx msg failed.")); 1494 goto nxge_allocb_exit; 1495 } 1496 1497 nxge_mp->use_buf_pool = B_FALSE; 1498 if (dmabuf_p) { 1499 nxge_mp->use_buf_pool = B_TRUE; 1500 dmamsg_p = (p_nxge_dma_common_t)&nxge_mp->buf_dma; 1501 *dmamsg_p = *dmabuf_p; 1502 dmamsg_p->nblocks = 1; 1503 dmamsg_p->block_size = size; 1504 dmamsg_p->alength = size; 1505 buffer = (uchar_t *)dmabuf_p->kaddrp; 1506 1507 dmabuf_p->kaddrp = (void *) 1508 ((char *)dmabuf_p->kaddrp + size); 1509 dmabuf_p->ioaddr_pp = (void *) 1510 ((char *)dmabuf_p->ioaddr_pp + size); 1511 dmabuf_p->alength -= size; 1512 dmabuf_p->offset += size; 1513 dmabuf_p->dma_cookie.dmac_laddress += size; 1514 dmabuf_p->dma_cookie.dmac_size -= size; 1515 1516 } else { 1517 buffer = KMEM_ALLOC(size, KM_NOSLEEP); 1518 if (buffer == NULL) { 1519 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 1520 "Allocation of a receive page failed.")); 1521 goto nxge_allocb_fail1; 1522 } 1523 } 1524 1525 nxge_mp->rx_mblk_p = desballoc(buffer, size, pri, &nxge_mp->freeb); 1526 if (nxge_mp->rx_mblk_p == NULL) { 1527 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "desballoc failed.")); 1528 goto nxge_allocb_fail2; 1529 } 1530 1531 nxge_mp->buffer = buffer; 1532 nxge_mp->block_size = size; 1533 nxge_mp->freeb.free_func = (void (*)())nxge_freeb; 1534 nxge_mp->freeb.free_arg = (caddr_t)nxge_mp; 1535 nxge_mp->ref_cnt = 1; 1536 nxge_mp->free = B_TRUE; 1537 nxge_mp->rx_use_bcopy = B_FALSE; 1538 1539 atomic_inc_32(&nxge_mblks_pending); 1540 1541 goto nxge_allocb_exit; 1542 1543 nxge_allocb_fail2: 1544 if (!nxge_mp->use_buf_pool) { 1545 KMEM_FREE(buffer, size); 1546 } 1547 1548 nxge_allocb_fail1: 1549 KMEM_FREE(nxge_mp, sizeof (rx_msg_t)); 1550 nxge_mp = NULL; 1551 1552 nxge_allocb_exit: 1553 return (nxge_mp); 1554 } 1555 1556 p_mblk_t 1557 nxge_dupb(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 1558 { 1559 p_mblk_t mp; 1560 1561 NXGE_DEBUG_MSG((NULL, MEM_CTL, "==> nxge_dupb")); 1562 NXGE_DEBUG_MSG((NULL, MEM_CTL, "nxge_mp = $%p " 1563 "offset = 0x%08X " 1564 "size = 0x%08X", 1565 nxge_mp, offset, size)); 1566 1567 mp = desballoc(&nxge_mp->buffer[offset], size, 1568 0, &nxge_mp->freeb); 1569 if (mp == NULL) { 1570 NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 1571 goto nxge_dupb_exit; 1572 } 1573 atomic_inc_32(&nxge_mp->ref_cnt); 1574 atomic_inc_32(&nxge_mblks_pending); 1575 1576 1577 nxge_dupb_exit: 1578 NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 1579 nxge_mp)); 1580 return (mp); 1581 } 1582 1583 p_mblk_t 1584 nxge_dupb_bcopy(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 1585 { 1586 p_mblk_t mp; 1587 uchar_t *dp; 1588 1589 mp = allocb(size + NXGE_RXBUF_EXTRA, 0); 1590 if (mp == NULL) { 1591 NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 1592 goto nxge_dupb_bcopy_exit; 1593 } 1594 dp = mp->b_rptr = mp->b_rptr + NXGE_RXBUF_EXTRA; 1595 bcopy((void *)&nxge_mp->buffer[offset], dp, size); 1596 mp->b_wptr = dp + size; 1597 1598 nxge_dupb_bcopy_exit: 1599 NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 1600 nxge_mp)); 1601 return (mp); 1602 } 1603 1604 void nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, 1605 p_rx_msg_t rx_msg_p); 1606 1607 void 1608 nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p) 1609 { 1610 1611 npi_handle_t handle; 1612 1613 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_post_page")); 1614 1615 /* Reuse this buffer */ 1616 rx_msg_p->free = B_FALSE; 1617 rx_msg_p->cur_usage_cnt = 0; 1618 rx_msg_p->max_usage_cnt = 0; 1619 rx_msg_p->pkt_buf_size = 0; 1620 1621 if (rx_rbr_p->rbr_use_bcopy) { 1622 rx_msg_p->rx_use_bcopy = B_FALSE; 1623 atomic_dec_32(&rx_rbr_p->rbr_consumed); 1624 } 1625 1626 /* 1627 * Get the rbr header pointer and its offset index. 1628 */ 1629 MUTEX_ENTER(&rx_rbr_p->post_lock); 1630 1631 1632 rx_rbr_p->rbr_wr_index = ((rx_rbr_p->rbr_wr_index + 1) & 1633 rx_rbr_p->rbr_wrap_mask); 1634 rx_rbr_p->rbr_desc_vp[rx_rbr_p->rbr_wr_index] = rx_msg_p->shifted_addr; 1635 MUTEX_EXIT(&rx_rbr_p->post_lock); 1636 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1637 npi_rxdma_rdc_rbr_kick(handle, rx_rbr_p->rdc, 1); 1638 1639 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1640 "<== nxge_post_page (channel %d post_next_index %d)", 1641 rx_rbr_p->rdc, rx_rbr_p->rbr_wr_index)); 1642 1643 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_post_page")); 1644 } 1645 1646 void 1647 nxge_freeb(p_rx_msg_t rx_msg_p) 1648 { 1649 size_t size; 1650 uchar_t *buffer = NULL; 1651 int ref_cnt; 1652 boolean_t free_state = B_FALSE; 1653 1654 rx_rbr_ring_t *ring = rx_msg_p->rx_rbr_p; 1655 1656 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "==> nxge_freeb")); 1657 NXGE_DEBUG_MSG((NULL, MEM2_CTL, 1658 "nxge_freeb:rx_msg_p = $%p (block pending %d)", 1659 rx_msg_p, nxge_mblks_pending)); 1660 1661 atomic_dec_32(&nxge_mblks_pending); 1662 /* 1663 * First we need to get the free state, then 1664 * atomic decrement the reference count to prevent 1665 * the race condition with the interrupt thread that 1666 * is processing a loaned up buffer block. 1667 */ 1668 free_state = rx_msg_p->free; 1669 ref_cnt = atomic_add_32_nv(&rx_msg_p->ref_cnt, -1); 1670 if (!ref_cnt) { 1671 buffer = rx_msg_p->buffer; 1672 size = rx_msg_p->block_size; 1673 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "nxge_freeb: " 1674 "will free: rx_msg_p = $%p (block pending %d)", 1675 rx_msg_p, nxge_mblks_pending)); 1676 1677 if (!rx_msg_p->use_buf_pool) { 1678 KMEM_FREE(buffer, size); 1679 } 1680 1681 KMEM_FREE(rx_msg_p, sizeof (rx_msg_t)); 1682 1683 if (ring) { 1684 /* 1685 * Decrement the receive buffer ring's reference 1686 * count, too. 1687 */ 1688 atomic_dec_32(&ring->rbr_ref_cnt); 1689 1690 /* 1691 * Free the receive buffer ring, iff 1692 * 1. all the receive buffers have been freed 1693 * 2. and we are in the proper state (that is, 1694 * we are not UNMAPPING). 1695 */ 1696 if (ring->rbr_ref_cnt == 0 && 1697 ring->rbr_state == RBR_UNMAPPED) { 1698 KMEM_FREE(ring, sizeof (*ring)); 1699 } 1700 } 1701 return; 1702 } 1703 1704 /* 1705 * Repost buffer. 1706 */ 1707 if (free_state && (ref_cnt == 1) && ring) { 1708 NXGE_DEBUG_MSG((NULL, RX_CTL, 1709 "nxge_freeb: post page $%p:", rx_msg_p)); 1710 if (ring->rbr_state == RBR_POSTING) 1711 nxge_post_page(rx_msg_p->nxgep, ring, rx_msg_p); 1712 } 1713 1714 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "<== nxge_freeb")); 1715 } 1716 1717 uint_t 1718 nxge_rx_intr(void *arg1, void *arg2) 1719 { 1720 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 1721 p_nxge_t nxgep = (p_nxge_t)arg2; 1722 p_nxge_ldg_t ldgp; 1723 uint8_t channel; 1724 npi_handle_t handle; 1725 rx_dma_ctl_stat_t cs; 1726 1727 #ifdef NXGE_DEBUG 1728 rxdma_cfig1_t cfg; 1729 #endif 1730 uint_t serviced = DDI_INTR_UNCLAIMED; 1731 1732 if (ldvp == NULL) { 1733 NXGE_DEBUG_MSG((NULL, INT_CTL, 1734 "<== nxge_rx_intr: arg2 $%p arg1 $%p", 1735 nxgep, ldvp)); 1736 1737 return (DDI_INTR_CLAIMED); 1738 } 1739 1740 if (arg2 == NULL || (void *)ldvp->nxgep != arg2) { 1741 nxgep = ldvp->nxgep; 1742 } 1743 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1744 "==> nxge_rx_intr: arg2 $%p arg1 $%p", 1745 nxgep, ldvp)); 1746 1747 /* 1748 * This interrupt handler is for a specific 1749 * receive dma channel. 1750 */ 1751 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1752 /* 1753 * Get the control and status for this channel. 1754 */ 1755 channel = ldvp->channel; 1756 ldgp = ldvp->ldgp; 1757 RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel, &cs.value); 1758 1759 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_intr:channel %d " 1760 "cs 0x%016llx rcrto 0x%x rcrthres %x", 1761 channel, 1762 cs.value, 1763 cs.bits.hdw.rcrto, 1764 cs.bits.hdw.rcrthres)); 1765 1766 nxge_rx_pkts_vring(nxgep, ldvp->vdma_index, ldvp, cs); 1767 serviced = DDI_INTR_CLAIMED; 1768 1769 /* error events. */ 1770 if (cs.value & RX_DMA_CTL_STAT_ERROR) { 1771 (void) nxge_rx_err_evnts(nxgep, ldvp->vdma_index, ldvp, cs); 1772 } 1773 1774 nxge_intr_exit: 1775 1776 1777 /* 1778 * Enable the mailbox update interrupt if we want 1779 * to use mailbox. We probably don't need to use 1780 * mailbox as it only saves us one pio read. 1781 * Also write 1 to rcrthres and rcrto to clear 1782 * these two edge triggered bits. 1783 */ 1784 1785 cs.value &= RX_DMA_CTL_STAT_WR1C; 1786 cs.bits.hdw.mex = 1; 1787 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, 1788 cs.value); 1789 1790 /* 1791 * Rearm this logical group if this is a single device 1792 * group. 1793 */ 1794 if (ldgp->nldvs == 1) { 1795 ldgimgm_t mgm; 1796 mgm.value = 0; 1797 mgm.bits.ldw.arm = 1; 1798 mgm.bits.ldw.timer = ldgp->ldg_timer; 1799 NXGE_REG_WR64(handle, 1800 LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg), 1801 mgm.value); 1802 } 1803 1804 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_intr: serviced %d", 1805 serviced)); 1806 return (serviced); 1807 } 1808 1809 /* 1810 * Process the packets received in the specified logical device 1811 * and pass up a chain of message blocks to the upper layer. 1812 */ 1813 static void 1814 nxge_rx_pkts_vring(p_nxge_t nxgep, uint_t vindex, p_nxge_ldv_t ldvp, 1815 rx_dma_ctl_stat_t cs) 1816 { 1817 p_mblk_t mp; 1818 p_rx_rcr_ring_t rcrp; 1819 1820 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts_vring")); 1821 if ((mp = nxge_rx_pkts(nxgep, vindex, ldvp, &rcrp, cs)) == NULL) { 1822 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1823 "<== nxge_rx_pkts_vring: no mp")); 1824 return; 1825 } 1826 1827 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts_vring: $%p", 1828 mp)); 1829 1830 #ifdef NXGE_DEBUG 1831 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1832 "==> nxge_rx_pkts_vring:calling mac_rx " 1833 "LEN %d mp $%p mp->b_cont $%p mp->b_next $%p rcrp $%p " 1834 "mac_handle $%p", 1835 mp->b_wptr - mp->b_rptr, 1836 mp, mp->b_cont, mp->b_next, 1837 rcrp, rcrp->rcr_mac_handle)); 1838 1839 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1840 "==> nxge_rx_pkts_vring: dump packets " 1841 "(mp $%p b_rptr $%p b_wptr $%p):\n %s", 1842 mp, 1843 mp->b_rptr, 1844 mp->b_wptr, 1845 nxge_dump_packet((char *)mp->b_rptr, 1846 mp->b_wptr - mp->b_rptr))); 1847 if (mp->b_cont) { 1848 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1849 "==> nxge_rx_pkts_vring: dump b_cont packets " 1850 "(mp->b_cont $%p b_rptr $%p b_wptr $%p):\n %s", 1851 mp->b_cont, 1852 mp->b_cont->b_rptr, 1853 mp->b_cont->b_wptr, 1854 nxge_dump_packet((char *)mp->b_cont->b_rptr, 1855 mp->b_cont->b_wptr - mp->b_cont->b_rptr))); 1856 } 1857 if (mp->b_next) { 1858 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1859 "==> nxge_rx_pkts_vring: dump next packets " 1860 "(b_rptr $%p): %s", 1861 mp->b_next->b_rptr, 1862 nxge_dump_packet((char *)mp->b_next->b_rptr, 1863 mp->b_next->b_wptr - mp->b_next->b_rptr))); 1864 } 1865 #endif 1866 1867 mac_rx(nxgep->mach, rcrp->rcr_mac_handle, mp); 1868 } 1869 1870 1871 /* 1872 * This routine is the main packet receive processing function. 1873 * It gets the packet type, error code, and buffer related 1874 * information from the receive completion entry. 1875 * How many completion entries to process is based on the number of packets 1876 * queued by the hardware, a hardware maintained tail pointer 1877 * and a configurable receive packet count. 1878 * 1879 * A chain of message blocks will be created as result of processing 1880 * the completion entries. This chain of message blocks will be returned and 1881 * a hardware control status register will be updated with the number of 1882 * packets were removed from the hardware queue. 1883 * 1884 */ 1885 mblk_t * 1886 nxge_rx_pkts(p_nxge_t nxgep, uint_t vindex, p_nxge_ldv_t ldvp, 1887 p_rx_rcr_ring_t *rcrp, rx_dma_ctl_stat_t cs) 1888 { 1889 npi_handle_t handle; 1890 uint8_t channel; 1891 p_rx_rcr_rings_t rx_rcr_rings; 1892 p_rx_rcr_ring_t rcr_p; 1893 uint32_t comp_rd_index; 1894 p_rcr_entry_t rcr_desc_rd_head_p; 1895 p_rcr_entry_t rcr_desc_rd_head_pp; 1896 p_mblk_t nmp, mp_cont, head_mp, *tail_mp; 1897 uint16_t qlen, nrcr_read, npkt_read; 1898 uint32_t qlen_hw; 1899 boolean_t multi; 1900 rcrcfig_b_t rcr_cfg_b; 1901 #if defined(_BIG_ENDIAN) 1902 npi_status_t rs = NPI_SUCCESS; 1903 #endif 1904 1905 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:vindex %d " 1906 "channel %d", vindex, ldvp->channel)); 1907 1908 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1909 return (NULL); 1910 } 1911 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1912 rx_rcr_rings = nxgep->rx_rcr_rings; 1913 rcr_p = rx_rcr_rings->rcr_rings[vindex]; 1914 channel = rcr_p->rdc; 1915 if (channel != ldvp->channel) { 1916 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:index %d " 1917 "channel %d, and rcr channel %d not matched.", 1918 vindex, ldvp->channel, channel)); 1919 return (NULL); 1920 } 1921 1922 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1923 "==> nxge_rx_pkts: START: rcr channel %d " 1924 "head_p $%p head_pp $%p index %d ", 1925 channel, rcr_p->rcr_desc_rd_head_p, 1926 rcr_p->rcr_desc_rd_head_pp, 1927 rcr_p->comp_rd_index)); 1928 1929 1930 #if !defined(_BIG_ENDIAN) 1931 qlen = RXDMA_REG_READ32(handle, RCRSTAT_A_REG, channel) & 0xffff; 1932 #else 1933 rs = npi_rxdma_rdc_rcr_qlen_get(handle, channel, &qlen); 1934 if (rs != NPI_SUCCESS) { 1935 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:index %d " 1936 "channel %d, get qlen failed 0x%08x", 1937 vindex, ldvp->channel, rs)); 1938 return (NULL); 1939 } 1940 #endif 1941 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:rcr channel %d " 1942 "qlen %d", channel, qlen)); 1943 1944 1945 1946 if (!qlen) { 1947 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1948 "==> nxge_rx_pkts:rcr channel %d " 1949 "qlen %d (no pkts)", channel, qlen)); 1950 1951 return (NULL); 1952 } 1953 1954 comp_rd_index = rcr_p->comp_rd_index; 1955 1956 rcr_desc_rd_head_p = rcr_p->rcr_desc_rd_head_p; 1957 rcr_desc_rd_head_pp = rcr_p->rcr_desc_rd_head_pp; 1958 nrcr_read = npkt_read = 0; 1959 1960 /* 1961 * Number of packets queued 1962 * (The jumbo or multi packet will be counted as only one 1963 * packets and it may take up more than one completion entry). 1964 */ 1965 qlen_hw = (qlen < nxge_max_rx_pkts) ? 1966 qlen : nxge_max_rx_pkts; 1967 head_mp = NULL; 1968 tail_mp = &head_mp; 1969 nmp = mp_cont = NULL; 1970 multi = B_FALSE; 1971 1972 while (qlen_hw) { 1973 1974 #ifdef NXGE_DEBUG 1975 nxge_dump_rcr_entry(nxgep, rcr_desc_rd_head_p); 1976 #endif 1977 /* 1978 * Process one completion ring entry. 1979 */ 1980 nxge_receive_packet(nxgep, 1981 rcr_p, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont); 1982 1983 /* 1984 * message chaining modes 1985 */ 1986 if (nmp) { 1987 nmp->b_next = NULL; 1988 if (!multi && !mp_cont) { /* frame fits a partition */ 1989 *tail_mp = nmp; 1990 tail_mp = &nmp->b_next; 1991 nmp = NULL; 1992 } else if (multi && !mp_cont) { /* first segment */ 1993 *tail_mp = nmp; 1994 tail_mp = &nmp->b_cont; 1995 } else if (multi && mp_cont) { /* mid of multi segs */ 1996 *tail_mp = mp_cont; 1997 tail_mp = &mp_cont->b_cont; 1998 } else if (!multi && mp_cont) { /* last segment */ 1999 *tail_mp = mp_cont; 2000 tail_mp = &nmp->b_next; 2001 nmp = NULL; 2002 } 2003 } 2004 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2005 "==> nxge_rx_pkts: loop: rcr channel %d " 2006 "before updating: multi %d " 2007 "nrcr_read %d " 2008 "npk read %d " 2009 "head_pp $%p index %d ", 2010 channel, 2011 multi, 2012 nrcr_read, npkt_read, rcr_desc_rd_head_pp, 2013 comp_rd_index)); 2014 2015 if (!multi) { 2016 qlen_hw--; 2017 npkt_read++; 2018 } 2019 2020 /* 2021 * Update the next read entry. 2022 */ 2023 comp_rd_index = NEXT_ENTRY(comp_rd_index, 2024 rcr_p->comp_wrap_mask); 2025 2026 rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p, 2027 rcr_p->rcr_desc_first_p, 2028 rcr_p->rcr_desc_last_p); 2029 2030 nrcr_read++; 2031 2032 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2033 "<== nxge_rx_pkts: (SAM, process one packet) " 2034 "nrcr_read %d", 2035 nrcr_read)); 2036 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2037 "==> nxge_rx_pkts: loop: rcr channel %d " 2038 "multi %d " 2039 "nrcr_read %d " 2040 "npk read %d " 2041 "head_pp $%p index %d ", 2042 channel, 2043 multi, 2044 nrcr_read, npkt_read, rcr_desc_rd_head_pp, 2045 comp_rd_index)); 2046 2047 } 2048 2049 rcr_p->rcr_desc_rd_head_pp = rcr_desc_rd_head_pp; 2050 rcr_p->comp_rd_index = comp_rd_index; 2051 rcr_p->rcr_desc_rd_head_p = rcr_desc_rd_head_p; 2052 2053 if ((nxgep->intr_timeout != rcr_p->intr_timeout) || 2054 (nxgep->intr_threshold != rcr_p->intr_threshold)) { 2055 rcr_p->intr_timeout = nxgep->intr_timeout; 2056 rcr_p->intr_threshold = nxgep->intr_threshold; 2057 rcr_cfg_b.value = 0x0ULL; 2058 if (rcr_p->intr_timeout) 2059 rcr_cfg_b.bits.ldw.entout = 1; 2060 rcr_cfg_b.bits.ldw.timeout = rcr_p->intr_timeout; 2061 rcr_cfg_b.bits.ldw.pthres = rcr_p->intr_threshold; 2062 RXDMA_REG_WRITE64(handle, RCRCFIG_B_REG, 2063 channel, rcr_cfg_b.value); 2064 } 2065 2066 cs.bits.ldw.pktread = npkt_read; 2067 cs.bits.ldw.ptrread = nrcr_read; 2068 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, 2069 channel, cs.value); 2070 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2071 "==> nxge_rx_pkts: EXIT: rcr channel %d " 2072 "head_pp $%p index %016llx ", 2073 channel, 2074 rcr_p->rcr_desc_rd_head_pp, 2075 rcr_p->comp_rd_index)); 2076 /* 2077 * Update RCR buffer pointer read and number of packets 2078 * read. 2079 */ 2080 2081 *rcrp = rcr_p; 2082 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_pkts")); 2083 return (head_mp); 2084 } 2085 2086 void 2087 nxge_receive_packet(p_nxge_t nxgep, 2088 p_rx_rcr_ring_t rcr_p, p_rcr_entry_t rcr_desc_rd_head_p, 2089 boolean_t *multi_p, mblk_t **mp, mblk_t **mp_cont) 2090 { 2091 p_mblk_t nmp = NULL; 2092 uint64_t multi; 2093 uint64_t dcf_err; 2094 uint8_t channel; 2095 2096 boolean_t first_entry = B_TRUE; 2097 boolean_t is_tcp_udp = B_FALSE; 2098 boolean_t buffer_free = B_FALSE; 2099 boolean_t error_send_up = B_FALSE; 2100 uint8_t error_type; 2101 uint16_t l2_len; 2102 uint16_t skip_len; 2103 uint8_t pktbufsz_type; 2104 uint64_t rcr_entry; 2105 uint64_t *pkt_buf_addr_pp; 2106 uint64_t *pkt_buf_addr_p; 2107 uint32_t buf_offset; 2108 uint32_t bsize; 2109 uint32_t error_disp_cnt; 2110 uint32_t msg_index; 2111 p_rx_rbr_ring_t rx_rbr_p; 2112 p_rx_msg_t *rx_msg_ring_p; 2113 p_rx_msg_t rx_msg_p; 2114 uint16_t sw_offset_bytes = 0, hdr_size = 0; 2115 nxge_status_t status = NXGE_OK; 2116 boolean_t is_valid = B_FALSE; 2117 p_nxge_rx_ring_stats_t rdc_stats; 2118 uint32_t bytes_read; 2119 uint64_t pkt_type; 2120 uint64_t frag; 2121 #ifdef NXGE_DEBUG 2122 int dump_len; 2123 #endif 2124 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_receive_packet")); 2125 first_entry = (*mp == NULL) ? B_TRUE : B_FALSE; 2126 2127 rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); 2128 2129 multi = (rcr_entry & RCR_MULTI_MASK); 2130 dcf_err = (rcr_entry & RCR_DCF_ERROR_MASK); 2131 pkt_type = (rcr_entry & RCR_PKT_TYPE_MASK); 2132 2133 error_type = ((rcr_entry & RCR_ERROR_MASK) >> RCR_ERROR_SHIFT); 2134 frag = (rcr_entry & RCR_FRAG_MASK); 2135 2136 l2_len = ((rcr_entry & RCR_L2_LEN_MASK) >> RCR_L2_LEN_SHIFT); 2137 2138 pktbufsz_type = ((rcr_entry & RCR_PKTBUFSZ_MASK) >> 2139 RCR_PKTBUFSZ_SHIFT); 2140 #if defined(__i386) 2141 pkt_buf_addr_pp = (uint64_t *)(uint32_t)((rcr_entry & 2142 RCR_PKT_BUF_ADDR_MASK) << RCR_PKT_BUF_ADDR_SHIFT); 2143 #else 2144 pkt_buf_addr_pp = (uint64_t *)((rcr_entry & RCR_PKT_BUF_ADDR_MASK) << 2145 RCR_PKT_BUF_ADDR_SHIFT); 2146 #endif 2147 2148 channel = rcr_p->rdc; 2149 2150 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2151 "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 2152 "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 2153 "error_type 0x%x pkt_type 0x%x " 2154 "pktbufsz_type %d ", 2155 rcr_desc_rd_head_p, 2156 rcr_entry, pkt_buf_addr_pp, l2_len, 2157 multi, 2158 error_type, 2159 pkt_type, 2160 pktbufsz_type)); 2161 2162 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2163 "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 2164 "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 2165 "error_type 0x%x pkt_type 0x%x ", rcr_desc_rd_head_p, 2166 rcr_entry, pkt_buf_addr_pp, l2_len, 2167 multi, 2168 error_type, 2169 pkt_type)); 2170 2171 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2172 "==> (rbr) nxge_receive_packet: entry 0x%0llx " 2173 "full pkt_buf_addr_pp $%p l2_len %d", 2174 rcr_entry, pkt_buf_addr_pp, l2_len)); 2175 2176 /* get the stats ptr */ 2177 rdc_stats = rcr_p->rdc_stats; 2178 2179 if (!l2_len) { 2180 2181 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2182 "<== nxge_receive_packet: failed: l2 length is 0.")); 2183 return; 2184 } 2185 2186 /* Hardware sends us 4 bytes of CRC as no stripping is done. */ 2187 l2_len -= ETHERFCSL; 2188 2189 /* shift 6 bits to get the full io address */ 2190 #if defined(__i386) 2191 pkt_buf_addr_pp = (uint64_t *)((uint32_t)pkt_buf_addr_pp << 2192 RCR_PKT_BUF_ADDR_SHIFT_FULL); 2193 #else 2194 pkt_buf_addr_pp = (uint64_t *)((uint64_t)pkt_buf_addr_pp << 2195 RCR_PKT_BUF_ADDR_SHIFT_FULL); 2196 #endif 2197 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2198 "==> (rbr) nxge_receive_packet: entry 0x%0llx " 2199 "full pkt_buf_addr_pp $%p l2_len %d", 2200 rcr_entry, pkt_buf_addr_pp, l2_len)); 2201 2202 rx_rbr_p = rcr_p->rx_rbr_p; 2203 rx_msg_ring_p = rx_rbr_p->rx_msg_ring; 2204 2205 if (first_entry) { 2206 hdr_size = (rcr_p->full_hdr_flag ? RXDMA_HDR_SIZE_FULL : 2207 RXDMA_HDR_SIZE_DEFAULT); 2208 2209 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2210 "==> nxge_receive_packet: first entry 0x%016llx " 2211 "pkt_buf_addr_pp $%p l2_len %d hdr %d", 2212 rcr_entry, pkt_buf_addr_pp, l2_len, 2213 hdr_size)); 2214 } 2215 2216 MUTEX_ENTER(&rcr_p->lock); 2217 MUTEX_ENTER(&rx_rbr_p->lock); 2218 2219 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2220 "==> (rbr 1) nxge_receive_packet: entry 0x%0llx " 2221 "full pkt_buf_addr_pp $%p l2_len %d", 2222 rcr_entry, pkt_buf_addr_pp, l2_len)); 2223 2224 /* 2225 * Packet buffer address in the completion entry points 2226 * to the starting buffer address (offset 0). 2227 * Use the starting buffer address to locate the corresponding 2228 * kernel address. 2229 */ 2230 status = nxge_rxbuf_pp_to_vp(nxgep, rx_rbr_p, 2231 pktbufsz_type, pkt_buf_addr_pp, &pkt_buf_addr_p, 2232 &buf_offset, 2233 &msg_index); 2234 2235 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2236 "==> (rbr 2) nxge_receive_packet: entry 0x%0llx " 2237 "full pkt_buf_addr_pp $%p l2_len %d", 2238 rcr_entry, pkt_buf_addr_pp, l2_len)); 2239 2240 if (status != NXGE_OK) { 2241 MUTEX_EXIT(&rx_rbr_p->lock); 2242 MUTEX_EXIT(&rcr_p->lock); 2243 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2244 "<== nxge_receive_packet: found vaddr failed %d", 2245 status)); 2246 return; 2247 } 2248 2249 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2250 "==> (rbr 3) nxge_receive_packet: entry 0x%0llx " 2251 "full pkt_buf_addr_pp $%p l2_len %d", 2252 rcr_entry, pkt_buf_addr_pp, l2_len)); 2253 2254 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2255 "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 2256 "full pkt_buf_addr_pp $%p l2_len %d", 2257 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 2258 2259 rx_msg_p = rx_msg_ring_p[msg_index]; 2260 2261 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2262 "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 2263 "full pkt_buf_addr_pp $%p l2_len %d", 2264 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 2265 2266 switch (pktbufsz_type) { 2267 case RCR_PKTBUFSZ_0: 2268 bsize = rx_rbr_p->pkt_buf_size0_bytes; 2269 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2270 "==> nxge_receive_packet: 0 buf %d", bsize)); 2271 break; 2272 case RCR_PKTBUFSZ_1: 2273 bsize = rx_rbr_p->pkt_buf_size1_bytes; 2274 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2275 "==> nxge_receive_packet: 1 buf %d", bsize)); 2276 break; 2277 case RCR_PKTBUFSZ_2: 2278 bsize = rx_rbr_p->pkt_buf_size2_bytes; 2279 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2280 "==> nxge_receive_packet: 2 buf %d", bsize)); 2281 break; 2282 case RCR_SINGLE_BLOCK: 2283 bsize = rx_msg_p->block_size; 2284 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2285 "==> nxge_receive_packet: single %d", bsize)); 2286 2287 break; 2288 default: 2289 MUTEX_EXIT(&rx_rbr_p->lock); 2290 MUTEX_EXIT(&rcr_p->lock); 2291 return; 2292 } 2293 2294 DMA_COMMON_SYNC_OFFSET(rx_msg_p->buf_dma, 2295 (buf_offset + sw_offset_bytes), 2296 (hdr_size + l2_len), 2297 DDI_DMA_SYNC_FORCPU); 2298 2299 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2300 "==> nxge_receive_packet: after first dump:usage count")); 2301 2302 if (rx_msg_p->cur_usage_cnt == 0) { 2303 if (rx_rbr_p->rbr_use_bcopy) { 2304 atomic_inc_32(&rx_rbr_p->rbr_consumed); 2305 if (rx_rbr_p->rbr_consumed < 2306 rx_rbr_p->rbr_threshold_hi) { 2307 if (rx_rbr_p->rbr_threshold_lo == 0 || 2308 ((rx_rbr_p->rbr_consumed >= 2309 rx_rbr_p->rbr_threshold_lo) && 2310 (rx_rbr_p->rbr_bufsize_type >= 2311 pktbufsz_type))) { 2312 rx_msg_p->rx_use_bcopy = B_TRUE; 2313 } 2314 } else { 2315 rx_msg_p->rx_use_bcopy = B_TRUE; 2316 } 2317 } 2318 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2319 "==> nxge_receive_packet: buf %d (new block) ", 2320 bsize)); 2321 2322 rx_msg_p->pkt_buf_size_code = pktbufsz_type; 2323 rx_msg_p->pkt_buf_size = bsize; 2324 rx_msg_p->cur_usage_cnt = 1; 2325 if (pktbufsz_type == RCR_SINGLE_BLOCK) { 2326 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2327 "==> nxge_receive_packet: buf %d " 2328 "(single block) ", 2329 bsize)); 2330 /* 2331 * Buffer can be reused once the free function 2332 * is called. 2333 */ 2334 rx_msg_p->max_usage_cnt = 1; 2335 buffer_free = B_TRUE; 2336 } else { 2337 rx_msg_p->max_usage_cnt = rx_msg_p->block_size/bsize; 2338 if (rx_msg_p->max_usage_cnt == 1) { 2339 buffer_free = B_TRUE; 2340 } 2341 } 2342 } else { 2343 rx_msg_p->cur_usage_cnt++; 2344 if (rx_msg_p->cur_usage_cnt == rx_msg_p->max_usage_cnt) { 2345 buffer_free = B_TRUE; 2346 } 2347 } 2348 2349 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2350 "msgbuf index = %d l2len %d bytes usage %d max_usage %d ", 2351 msg_index, l2_len, 2352 rx_msg_p->cur_usage_cnt, rx_msg_p->max_usage_cnt)); 2353 2354 if ((error_type) || (dcf_err)) { 2355 rdc_stats->ierrors++; 2356 if (dcf_err) { 2357 rdc_stats->dcf_err++; 2358 #ifdef NXGE_DEBUG 2359 if (!rdc_stats->dcf_err) { 2360 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2361 "nxge_receive_packet: channel %d dcf_err rcr" 2362 " 0x%llx", channel, rcr_entry)); 2363 } 2364 #endif 2365 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 2366 NXGE_FM_EREPORT_RDMC_DCF_ERR); 2367 } else { 2368 /* Update error stats */ 2369 error_disp_cnt = NXGE_ERROR_SHOW_MAX; 2370 rdc_stats->errlog.compl_err_type = error_type; 2371 2372 switch (error_type) { 2373 /* 2374 * Do not send FMA ereport for RCR_L2_ERROR and 2375 * RCR_L4_CSUM_ERROR because most likely they indicate 2376 * back pressure rather than HW failures. 2377 */ 2378 case RCR_L2_ERROR: 2379 rdc_stats->l2_err++; 2380 if (rdc_stats->l2_err < 2381 error_disp_cnt) { 2382 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2383 " nxge_receive_packet:" 2384 " channel %d RCR L2_ERROR", 2385 channel)); 2386 } 2387 break; 2388 case RCR_L4_CSUM_ERROR: 2389 error_send_up = B_TRUE; 2390 rdc_stats->l4_cksum_err++; 2391 if (rdc_stats->l4_cksum_err < 2392 error_disp_cnt) { 2393 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2394 " nxge_receive_packet:" 2395 " channel %d" 2396 " RCR L4_CSUM_ERROR", channel)); 2397 } 2398 break; 2399 /* 2400 * Do not send FMA ereport for RCR_FFLP_SOFT_ERROR and 2401 * RCR_ZCP_SOFT_ERROR because they reflect the same 2402 * FFLP and ZCP errors that have been reported by 2403 * nxge_fflp.c and nxge_zcp.c. 2404 */ 2405 case RCR_FFLP_SOFT_ERROR: 2406 error_send_up = B_TRUE; 2407 rdc_stats->fflp_soft_err++; 2408 if (rdc_stats->fflp_soft_err < 2409 error_disp_cnt) { 2410 NXGE_ERROR_MSG((nxgep, 2411 NXGE_ERR_CTL, 2412 " nxge_receive_packet:" 2413 " channel %d" 2414 " RCR FFLP_SOFT_ERROR", channel)); 2415 } 2416 break; 2417 case RCR_ZCP_SOFT_ERROR: 2418 error_send_up = B_TRUE; 2419 rdc_stats->fflp_soft_err++; 2420 if (rdc_stats->zcp_soft_err < 2421 error_disp_cnt) 2422 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2423 " nxge_receive_packet: Channel %d" 2424 " RCR ZCP_SOFT_ERROR", channel)); 2425 break; 2426 default: 2427 rdc_stats->rcr_unknown_err++; 2428 if (rdc_stats->rcr_unknown_err 2429 < error_disp_cnt) { 2430 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2431 " nxge_receive_packet: Channel %d" 2432 " RCR entry 0x%llx error 0x%x", 2433 rcr_entry, channel, error_type)); 2434 } 2435 break; 2436 } 2437 } 2438 2439 /* 2440 * Update and repost buffer block if max usage 2441 * count is reached. 2442 */ 2443 if (error_send_up == B_FALSE) { 2444 atomic_inc_32(&rx_msg_p->ref_cnt); 2445 atomic_inc_32(&nxge_mblks_pending); 2446 if (buffer_free == B_TRUE) { 2447 rx_msg_p->free = B_TRUE; 2448 } 2449 2450 MUTEX_EXIT(&rx_rbr_p->lock); 2451 MUTEX_EXIT(&rcr_p->lock); 2452 nxge_freeb(rx_msg_p); 2453 return; 2454 } 2455 } 2456 2457 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2458 "==> nxge_receive_packet: DMA sync second ")); 2459 2460 bytes_read = rcr_p->rcvd_pkt_bytes; 2461 skip_len = sw_offset_bytes + hdr_size; 2462 if (!rx_msg_p->rx_use_bcopy) { 2463 /* 2464 * For loaned up buffers, the driver reference count 2465 * will be incremented first and then the free state. 2466 */ 2467 if ((nmp = nxge_dupb(rx_msg_p, buf_offset, bsize)) != NULL) { 2468 if (first_entry) { 2469 nmp->b_rptr = &nmp->b_rptr[skip_len]; 2470 if (l2_len < bsize - skip_len) { 2471 nmp->b_wptr = &nmp->b_rptr[l2_len]; 2472 } else { 2473 nmp->b_wptr = &nmp->b_rptr[bsize 2474 - skip_len]; 2475 } 2476 } else { 2477 if (l2_len - bytes_read < bsize) { 2478 nmp->b_wptr = 2479 &nmp->b_rptr[l2_len - bytes_read]; 2480 } else { 2481 nmp->b_wptr = &nmp->b_rptr[bsize]; 2482 } 2483 } 2484 } 2485 } else { 2486 if (first_entry) { 2487 nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset + skip_len, 2488 l2_len < bsize - skip_len ? 2489 l2_len : bsize - skip_len); 2490 } else { 2491 nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset, 2492 l2_len - bytes_read < bsize ? 2493 l2_len - bytes_read : bsize); 2494 } 2495 } 2496 if (nmp != NULL) { 2497 if (first_entry) 2498 bytes_read = nmp->b_wptr - nmp->b_rptr; 2499 else 2500 bytes_read += nmp->b_wptr - nmp->b_rptr; 2501 2502 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2503 "==> nxge_receive_packet after dupb: " 2504 "rbr consumed %d " 2505 "pktbufsz_type %d " 2506 "nmp $%p rptr $%p wptr $%p " 2507 "buf_offset %d bzise %d l2_len %d skip_len %d", 2508 rx_rbr_p->rbr_consumed, 2509 pktbufsz_type, 2510 nmp, nmp->b_rptr, nmp->b_wptr, 2511 buf_offset, bsize, l2_len, skip_len)); 2512 } else { 2513 cmn_err(CE_WARN, "!nxge_receive_packet: " 2514 "update stats (error)"); 2515 atomic_inc_32(&rx_msg_p->ref_cnt); 2516 atomic_inc_32(&nxge_mblks_pending); 2517 if (buffer_free == B_TRUE) { 2518 rx_msg_p->free = B_TRUE; 2519 } 2520 MUTEX_EXIT(&rx_rbr_p->lock); 2521 MUTEX_EXIT(&rcr_p->lock); 2522 nxge_freeb(rx_msg_p); 2523 return; 2524 } 2525 2526 if (buffer_free == B_TRUE) { 2527 rx_msg_p->free = B_TRUE; 2528 } 2529 /* 2530 * ERROR, FRAG and PKT_TYPE are only reported 2531 * in the first entry. 2532 * If a packet is not fragmented and no error bit is set, then 2533 * L4 checksum is OK. 2534 */ 2535 is_valid = (nmp != NULL); 2536 if (first_entry) { 2537 rdc_stats->ipackets++; /* count only 1st seg for jumbo */ 2538 rdc_stats->ibytes += skip_len + l2_len < bsize ? 2539 l2_len : bsize; 2540 } else { 2541 rdc_stats->ibytes += l2_len - bytes_read < bsize ? 2542 l2_len - bytes_read : bsize; 2543 } 2544 2545 rcr_p->rcvd_pkt_bytes = bytes_read; 2546 2547 MUTEX_EXIT(&rx_rbr_p->lock); 2548 MUTEX_EXIT(&rcr_p->lock); 2549 2550 if (rx_msg_p->free && rx_msg_p->rx_use_bcopy) { 2551 atomic_inc_32(&rx_msg_p->ref_cnt); 2552 atomic_inc_32(&nxge_mblks_pending); 2553 nxge_freeb(rx_msg_p); 2554 } 2555 2556 if (is_valid) { 2557 nmp->b_cont = NULL; 2558 if (first_entry) { 2559 *mp = nmp; 2560 *mp_cont = NULL; 2561 } else { 2562 *mp_cont = nmp; 2563 } 2564 } 2565 2566 /* 2567 * Update stats and hardware checksuming. 2568 */ 2569 if (is_valid && !multi) { 2570 2571 is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP || 2572 pkt_type == RCR_PKT_IS_UDP) ? 2573 B_TRUE: B_FALSE); 2574 2575 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_receive_packet: " 2576 "is_valid 0x%x multi 0x%llx pkt %d frag %d error %d", 2577 is_valid, multi, is_tcp_udp, frag, error_type)); 2578 2579 if (is_tcp_udp && !frag && !error_type) { 2580 (void) hcksum_assoc(nmp, NULL, NULL, 0, 0, 0, 0, 2581 HCK_FULLCKSUM_OK | HCK_FULLCKSUM, 0); 2582 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2583 "==> nxge_receive_packet: Full tcp/udp cksum " 2584 "is_valid 0x%x multi 0x%llx pkt %d frag %d " 2585 "error %d", 2586 is_valid, multi, is_tcp_udp, frag, error_type)); 2587 } 2588 } 2589 2590 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2591 "==> nxge_receive_packet: *mp 0x%016llx", *mp)); 2592 2593 *multi_p = (multi == RCR_MULTI_MASK); 2594 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_receive_packet: " 2595 "multi %d nmp 0x%016llx *mp 0x%016llx *mp_cont 0x%016llx", 2596 *multi_p, nmp, *mp, *mp_cont)); 2597 } 2598 2599 /*ARGSUSED*/ 2600 static nxge_status_t 2601 nxge_rx_err_evnts(p_nxge_t nxgep, uint_t index, p_nxge_ldv_t ldvp, 2602 rx_dma_ctl_stat_t cs) 2603 { 2604 p_nxge_rx_ring_stats_t rdc_stats; 2605 npi_handle_t handle; 2606 npi_status_t rs; 2607 boolean_t rxchan_fatal = B_FALSE; 2608 boolean_t rxport_fatal = B_FALSE; 2609 uint8_t channel; 2610 uint8_t portn; 2611 nxge_status_t status = NXGE_OK; 2612 uint32_t error_disp_cnt = NXGE_ERROR_SHOW_MAX; 2613 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_err_evnts")); 2614 2615 handle = NXGE_DEV_NPI_HANDLE(nxgep); 2616 channel = ldvp->channel; 2617 portn = nxgep->mac.portnum; 2618 rdc_stats = &nxgep->statsp->rdc_stats[ldvp->vdma_index]; 2619 2620 if (cs.bits.hdw.rbr_tmout) { 2621 rdc_stats->rx_rbr_tmout++; 2622 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2623 NXGE_FM_EREPORT_RDMC_RBR_TMOUT); 2624 rxchan_fatal = B_TRUE; 2625 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2626 "==> nxge_rx_err_evnts: rx_rbr_timeout")); 2627 } 2628 if (cs.bits.hdw.rsp_cnt_err) { 2629 rdc_stats->rsp_cnt_err++; 2630 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2631 NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR); 2632 rxchan_fatal = B_TRUE; 2633 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2634 "==> nxge_rx_err_evnts(channel %d): " 2635 "rsp_cnt_err", channel)); 2636 } 2637 if (cs.bits.hdw.byte_en_bus) { 2638 rdc_stats->byte_en_bus++; 2639 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2640 NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS); 2641 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2642 "==> nxge_rx_err_evnts(channel %d): " 2643 "fatal error: byte_en_bus", channel)); 2644 rxchan_fatal = B_TRUE; 2645 } 2646 if (cs.bits.hdw.rsp_dat_err) { 2647 rdc_stats->rsp_dat_err++; 2648 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2649 NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR); 2650 rxchan_fatal = B_TRUE; 2651 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2652 "==> nxge_rx_err_evnts(channel %d): " 2653 "fatal error: rsp_dat_err", channel)); 2654 } 2655 if (cs.bits.hdw.rcr_ack_err) { 2656 rdc_stats->rcr_ack_err++; 2657 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2658 NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR); 2659 rxchan_fatal = B_TRUE; 2660 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2661 "==> nxge_rx_err_evnts(channel %d): " 2662 "fatal error: rcr_ack_err", channel)); 2663 } 2664 if (cs.bits.hdw.dc_fifo_err) { 2665 rdc_stats->dc_fifo_err++; 2666 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2667 NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR); 2668 /* This is not a fatal error! */ 2669 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2670 "==> nxge_rx_err_evnts(channel %d): " 2671 "dc_fifo_err", channel)); 2672 rxport_fatal = B_TRUE; 2673 } 2674 if ((cs.bits.hdw.rcr_sha_par) || (cs.bits.hdw.rbr_pre_par)) { 2675 if ((rs = npi_rxdma_ring_perr_stat_get(handle, 2676 &rdc_stats->errlog.pre_par, 2677 &rdc_stats->errlog.sha_par)) 2678 != NPI_SUCCESS) { 2679 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2680 "==> nxge_rx_err_evnts(channel %d): " 2681 "rcr_sha_par: get perr", channel)); 2682 return (NXGE_ERROR | rs); 2683 } 2684 if (cs.bits.hdw.rcr_sha_par) { 2685 rdc_stats->rcr_sha_par++; 2686 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2687 NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR); 2688 rxchan_fatal = B_TRUE; 2689 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2690 "==> nxge_rx_err_evnts(channel %d): " 2691 "fatal error: rcr_sha_par", channel)); 2692 } 2693 if (cs.bits.hdw.rbr_pre_par) { 2694 rdc_stats->rbr_pre_par++; 2695 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2696 NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR); 2697 rxchan_fatal = B_TRUE; 2698 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2699 "==> nxge_rx_err_evnts(channel %d): " 2700 "fatal error: rbr_pre_par", channel)); 2701 } 2702 } 2703 if (cs.bits.hdw.port_drop_pkt) { 2704 rdc_stats->port_drop_pkt++; 2705 if (rdc_stats->port_drop_pkt < error_disp_cnt) 2706 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2707 "==> nxge_rx_err_evnts (channel %d): " 2708 "port_drop_pkt", channel)); 2709 } 2710 if (cs.bits.hdw.wred_drop) { 2711 rdc_stats->wred_drop++; 2712 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2713 "==> nxge_rx_err_evnts(channel %d): " 2714 "wred_drop", channel)); 2715 } 2716 if (cs.bits.hdw.rbr_pre_empty) { 2717 rdc_stats->rbr_pre_empty++; 2718 if (rdc_stats->rbr_pre_empty < error_disp_cnt) 2719 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2720 "==> nxge_rx_err_evnts(channel %d): " 2721 "rbr_pre_empty", channel)); 2722 } 2723 if (cs.bits.hdw.rcr_shadow_full) { 2724 rdc_stats->rcr_shadow_full++; 2725 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2726 "==> nxge_rx_err_evnts(channel %d): " 2727 "rcr_shadow_full", channel)); 2728 } 2729 if (cs.bits.hdw.config_err) { 2730 rdc_stats->config_err++; 2731 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2732 NXGE_FM_EREPORT_RDMC_CONFIG_ERR); 2733 rxchan_fatal = B_TRUE; 2734 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2735 "==> nxge_rx_err_evnts(channel %d): " 2736 "config error", channel)); 2737 } 2738 if (cs.bits.hdw.rcrincon) { 2739 rdc_stats->rcrincon++; 2740 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2741 NXGE_FM_EREPORT_RDMC_RCRINCON); 2742 rxchan_fatal = B_TRUE; 2743 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2744 "==> nxge_rx_err_evnts(channel %d): " 2745 "fatal error: rcrincon error", channel)); 2746 } 2747 if (cs.bits.hdw.rcrfull) { 2748 rdc_stats->rcrfull++; 2749 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2750 NXGE_FM_EREPORT_RDMC_RCRFULL); 2751 rxchan_fatal = B_TRUE; 2752 if (rdc_stats->rcrfull < error_disp_cnt) 2753 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2754 "==> nxge_rx_err_evnts(channel %d): " 2755 "fatal error: rcrfull error", channel)); 2756 } 2757 if (cs.bits.hdw.rbr_empty) { 2758 rdc_stats->rbr_empty++; 2759 if (rdc_stats->rbr_empty < error_disp_cnt) 2760 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2761 "==> nxge_rx_err_evnts(channel %d): " 2762 "rbr empty error", channel)); 2763 } 2764 if (cs.bits.hdw.rbrfull) { 2765 rdc_stats->rbrfull++; 2766 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2767 NXGE_FM_EREPORT_RDMC_RBRFULL); 2768 rxchan_fatal = B_TRUE; 2769 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2770 "==> nxge_rx_err_evnts(channel %d): " 2771 "fatal error: rbr_full error", channel)); 2772 } 2773 if (cs.bits.hdw.rbrlogpage) { 2774 rdc_stats->rbrlogpage++; 2775 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2776 NXGE_FM_EREPORT_RDMC_RBRLOGPAGE); 2777 rxchan_fatal = B_TRUE; 2778 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2779 "==> nxge_rx_err_evnts(channel %d): " 2780 "fatal error: rbr logical page error", channel)); 2781 } 2782 if (cs.bits.hdw.cfiglogpage) { 2783 rdc_stats->cfiglogpage++; 2784 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2785 NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE); 2786 rxchan_fatal = B_TRUE; 2787 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2788 "==> nxge_rx_err_evnts(channel %d): " 2789 "fatal error: cfig logical page error", channel)); 2790 } 2791 2792 if (rxport_fatal) { 2793 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2794 " nxge_rx_err_evnts: " 2795 " fatal error on Port #%d\n", 2796 portn)); 2797 status = nxge_ipp_fatal_err_recover(nxgep); 2798 if (status == NXGE_OK) { 2799 FM_SERVICE_RESTORED(nxgep); 2800 } 2801 } 2802 2803 if (rxchan_fatal) { 2804 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2805 " nxge_rx_err_evnts: " 2806 " fatal error on Channel #%d\n", 2807 channel)); 2808 status = nxge_rxdma_fatal_err_recover(nxgep, channel); 2809 if (status == NXGE_OK) { 2810 FM_SERVICE_RESTORED(nxgep); 2811 } 2812 } 2813 2814 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rx_err_evnts")); 2815 2816 return (status); 2817 } 2818 2819 static nxge_status_t 2820 nxge_map_rxdma(p_nxge_t nxgep) 2821 { 2822 int i, ndmas; 2823 uint16_t channel; 2824 p_rx_rbr_rings_t rx_rbr_rings; 2825 p_rx_rbr_ring_t *rbr_rings; 2826 p_rx_rcr_rings_t rx_rcr_rings; 2827 p_rx_rcr_ring_t *rcr_rings; 2828 p_rx_mbox_areas_t rx_mbox_areas_p; 2829 p_rx_mbox_t *rx_mbox_p; 2830 p_nxge_dma_pool_t dma_buf_poolp; 2831 p_nxge_dma_pool_t dma_cntl_poolp; 2832 p_nxge_dma_common_t *dma_buf_p; 2833 p_nxge_dma_common_t *dma_cntl_p; 2834 uint32_t *num_chunks; 2835 nxge_status_t status = NXGE_OK; 2836 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2837 p_nxge_dma_common_t t_dma_buf_p; 2838 p_nxge_dma_common_t t_dma_cntl_p; 2839 #endif 2840 2841 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma")); 2842 2843 dma_buf_poolp = nxgep->rx_buf_pool_p; 2844 dma_cntl_poolp = nxgep->rx_cntl_pool_p; 2845 2846 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 2847 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2848 "<== nxge_map_rxdma: buf not allocated")); 2849 return (NXGE_ERROR); 2850 } 2851 2852 ndmas = dma_buf_poolp->ndmas; 2853 if (!ndmas) { 2854 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2855 "<== nxge_map_rxdma: no dma allocated")); 2856 return (NXGE_ERROR); 2857 } 2858 2859 num_chunks = dma_buf_poolp->num_chunks; 2860 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2861 dma_cntl_p = dma_cntl_poolp->dma_buf_pool_p; 2862 2863 rx_rbr_rings = (p_rx_rbr_rings_t) 2864 KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2865 rbr_rings = (p_rx_rbr_ring_t *) 2866 KMEM_ZALLOC(sizeof (p_rx_rbr_ring_t) * ndmas, KM_SLEEP); 2867 rx_rcr_rings = (p_rx_rcr_rings_t) 2868 KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2869 rcr_rings = (p_rx_rcr_ring_t *) 2870 KMEM_ZALLOC(sizeof (p_rx_rcr_ring_t) * ndmas, KM_SLEEP); 2871 rx_mbox_areas_p = (p_rx_mbox_areas_t) 2872 KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2873 rx_mbox_p = (p_rx_mbox_t *) 2874 KMEM_ZALLOC(sizeof (p_rx_mbox_t) * ndmas, KM_SLEEP); 2875 2876 /* 2877 * Timeout should be set based on the system clock divider. 2878 * The following timeout value of 1 assumes that the 2879 * granularity (1000) is 3 microseconds running at 300MHz. 2880 */ 2881 2882 nxgep->intr_threshold = RXDMA_RCR_PTHRES_DEFAULT; 2883 nxgep->intr_timeout = RXDMA_RCR_TO_DEFAULT; 2884 2885 /* 2886 * Map descriptors from the buffer polls for each dam channel. 2887 */ 2888 for (i = 0; i < ndmas; i++) { 2889 /* 2890 * Set up and prepare buffer blocks, descriptors 2891 * and mailbox. 2892 */ 2893 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 2894 status = nxge_map_rxdma_channel(nxgep, channel, 2895 (p_nxge_dma_common_t *)&dma_buf_p[i], 2896 (p_rx_rbr_ring_t *)&rbr_rings[i], 2897 num_chunks[i], 2898 (p_nxge_dma_common_t *)&dma_cntl_p[i], 2899 (p_rx_rcr_ring_t *)&rcr_rings[i], 2900 (p_rx_mbox_t *)&rx_mbox_p[i]); 2901 if (status != NXGE_OK) { 2902 goto nxge_map_rxdma_fail1; 2903 } 2904 rbr_rings[i]->index = (uint16_t)i; 2905 rcr_rings[i]->index = (uint16_t)i; 2906 rcr_rings[i]->rdc_stats = &nxgep->statsp->rdc_stats[i]; 2907 2908 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2909 if (nxgep->niu_type == N2_NIU && NXGE_DMA_BLOCK == 1) { 2910 rbr_rings[i]->hv_set = B_FALSE; 2911 t_dma_buf_p = (p_nxge_dma_common_t)dma_buf_p[i]; 2912 t_dma_cntl_p = 2913 (p_nxge_dma_common_t)dma_cntl_p[i]; 2914 2915 rbr_rings[i]->hv_rx_buf_base_ioaddr_pp = 2916 (uint64_t)t_dma_buf_p->orig_ioaddr_pp; 2917 rbr_rings[i]->hv_rx_buf_ioaddr_size = 2918 (uint64_t)t_dma_buf_p->orig_alength; 2919 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2920 "==> nxge_map_rxdma_channel: " 2921 "channel %d " 2922 "data buf base io $%p ($%p) " 2923 "size 0x%llx (%d 0x%x)", 2924 channel, 2925 rbr_rings[i]->hv_rx_buf_base_ioaddr_pp, 2926 t_dma_cntl_p->ioaddr_pp, 2927 rbr_rings[i]->hv_rx_buf_ioaddr_size, 2928 t_dma_buf_p->orig_alength, 2929 t_dma_buf_p->orig_alength)); 2930 2931 rbr_rings[i]->hv_rx_cntl_base_ioaddr_pp = 2932 (uint64_t)t_dma_cntl_p->orig_ioaddr_pp; 2933 rbr_rings[i]->hv_rx_cntl_ioaddr_size = 2934 (uint64_t)t_dma_cntl_p->orig_alength; 2935 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2936 "==> nxge_map_rxdma_channel: " 2937 "channel %d " 2938 "cntl base io $%p ($%p) " 2939 "size 0x%llx (%d 0x%x)", 2940 channel, 2941 rbr_rings[i]->hv_rx_cntl_base_ioaddr_pp, 2942 t_dma_cntl_p->ioaddr_pp, 2943 rbr_rings[i]->hv_rx_cntl_ioaddr_size, 2944 t_dma_cntl_p->orig_alength, 2945 t_dma_cntl_p->orig_alength)); 2946 } 2947 2948 #endif /* sun4v and NIU_LP_WORKAROUND */ 2949 } 2950 2951 rx_rbr_rings->ndmas = rx_rcr_rings->ndmas = ndmas; 2952 rx_rbr_rings->rbr_rings = rbr_rings; 2953 nxgep->rx_rbr_rings = rx_rbr_rings; 2954 rx_rcr_rings->rcr_rings = rcr_rings; 2955 nxgep->rx_rcr_rings = rx_rcr_rings; 2956 2957 rx_mbox_areas_p->rxmbox_areas = rx_mbox_p; 2958 nxgep->rx_mbox_areas_p = rx_mbox_areas_p; 2959 2960 goto nxge_map_rxdma_exit; 2961 2962 nxge_map_rxdma_fail1: 2963 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2964 "==> nxge_map_rxdma: unmap rbr,rcr " 2965 "(status 0x%x channel %d i %d)", 2966 status, channel, i)); 2967 i--; 2968 for (; i >= 0; i--) { 2969 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 2970 nxge_unmap_rxdma_channel(nxgep, channel, 2971 rbr_rings[i], 2972 rcr_rings[i], 2973 rx_mbox_p[i]); 2974 } 2975 2976 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2977 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2978 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2979 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2980 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2981 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2982 2983 nxge_map_rxdma_exit: 2984 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2985 "<== nxge_map_rxdma: " 2986 "(status 0x%x channel %d)", 2987 status, channel)); 2988 2989 return (status); 2990 } 2991 2992 static void 2993 nxge_unmap_rxdma(p_nxge_t nxgep) 2994 { 2995 int i, ndmas; 2996 uint16_t channel; 2997 p_rx_rbr_rings_t rx_rbr_rings; 2998 p_rx_rbr_ring_t *rbr_rings; 2999 p_rx_rcr_rings_t rx_rcr_rings; 3000 p_rx_rcr_ring_t *rcr_rings; 3001 p_rx_mbox_areas_t rx_mbox_areas_p; 3002 p_rx_mbox_t *rx_mbox_p; 3003 p_nxge_dma_pool_t dma_buf_poolp; 3004 p_nxge_dma_pool_t dma_cntl_poolp; 3005 p_nxge_dma_common_t *dma_buf_p; 3006 3007 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_unmap_rxdma")); 3008 3009 dma_buf_poolp = nxgep->rx_buf_pool_p; 3010 dma_cntl_poolp = nxgep->rx_cntl_pool_p; 3011 3012 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 3013 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3014 "<== nxge_unmap_rxdma: NULL buf pointers")); 3015 return; 3016 } 3017 3018 rx_rbr_rings = nxgep->rx_rbr_rings; 3019 rx_rcr_rings = nxgep->rx_rcr_rings; 3020 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3021 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3022 "<== nxge_unmap_rxdma: NULL ring pointers")); 3023 return; 3024 } 3025 ndmas = rx_rbr_rings->ndmas; 3026 if (!ndmas) { 3027 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3028 "<== nxge_unmap_rxdma: no channel")); 3029 return; 3030 } 3031 3032 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3033 "==> nxge_unmap_rxdma (ndmas %d)", ndmas)); 3034 rbr_rings = rx_rbr_rings->rbr_rings; 3035 rcr_rings = rx_rcr_rings->rcr_rings; 3036 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 3037 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 3038 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 3039 3040 for (i = 0; i < ndmas; i++) { 3041 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 3042 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3043 "==> nxge_unmap_rxdma (ndmas %d) channel %d", 3044 ndmas, channel)); 3045 (void) nxge_unmap_rxdma_channel(nxgep, channel, 3046 (p_rx_rbr_ring_t)rbr_rings[i], 3047 (p_rx_rcr_ring_t)rcr_rings[i], 3048 (p_rx_mbox_t)rx_mbox_p[i]); 3049 } 3050 3051 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 3052 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 3053 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 3054 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 3055 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 3056 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 3057 3058 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3059 "<== nxge_unmap_rxdma")); 3060 } 3061 3062 nxge_status_t 3063 nxge_map_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 3064 p_nxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 3065 uint32_t num_chunks, 3066 p_nxge_dma_common_t *dma_cntl_p, p_rx_rcr_ring_t *rcr_p, 3067 p_rx_mbox_t *rx_mbox_p) 3068 { 3069 int status = NXGE_OK; 3070 3071 /* 3072 * Set up and prepare buffer blocks, descriptors 3073 * and mailbox. 3074 */ 3075 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3076 "==> nxge_map_rxdma_channel (channel %d)", channel)); 3077 /* 3078 * Receive buffer blocks 3079 */ 3080 status = nxge_map_rxdma_channel_buf_ring(nxgep, channel, 3081 dma_buf_p, rbr_p, num_chunks); 3082 if (status != NXGE_OK) { 3083 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3084 "==> nxge_map_rxdma_channel (channel %d): " 3085 "map buffer failed 0x%x", channel, status)); 3086 goto nxge_map_rxdma_channel_exit; 3087 } 3088 3089 /* 3090 * Receive block ring, completion ring and mailbox. 3091 */ 3092 status = nxge_map_rxdma_channel_cfg_ring(nxgep, channel, 3093 dma_cntl_p, rbr_p, rcr_p, rx_mbox_p); 3094 if (status != NXGE_OK) { 3095 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3096 "==> nxge_map_rxdma_channel (channel %d): " 3097 "map config failed 0x%x", channel, status)); 3098 goto nxge_map_rxdma_channel_fail2; 3099 } 3100 3101 goto nxge_map_rxdma_channel_exit; 3102 3103 nxge_map_rxdma_channel_fail3: 3104 /* Free rbr, rcr */ 3105 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3106 "==> nxge_map_rxdma_channel: free rbr/rcr " 3107 "(status 0x%x channel %d)", 3108 status, channel)); 3109 nxge_unmap_rxdma_channel_cfg_ring(nxgep, 3110 *rcr_p, *rx_mbox_p); 3111 3112 nxge_map_rxdma_channel_fail2: 3113 /* Free buffer blocks */ 3114 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3115 "==> nxge_map_rxdma_channel: free rx buffers" 3116 "(nxgep 0x%x status 0x%x channel %d)", 3117 nxgep, status, channel)); 3118 nxge_unmap_rxdma_channel_buf_ring(nxgep, *rbr_p); 3119 3120 status = NXGE_ERROR; 3121 3122 nxge_map_rxdma_channel_exit: 3123 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3124 "<== nxge_map_rxdma_channel: " 3125 "(nxgep 0x%x status 0x%x channel %d)", 3126 nxgep, status, channel)); 3127 3128 return (status); 3129 } 3130 3131 /*ARGSUSED*/ 3132 static void 3133 nxge_unmap_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 3134 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 3135 { 3136 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3137 "==> nxge_unmap_rxdma_channel (channel %d)", channel)); 3138 3139 /* 3140 * unmap receive block ring, completion ring and mailbox. 3141 */ 3142 (void) nxge_unmap_rxdma_channel_cfg_ring(nxgep, 3143 rcr_p, rx_mbox_p); 3144 3145 /* unmap buffer blocks */ 3146 (void) nxge_unmap_rxdma_channel_buf_ring(nxgep, rbr_p); 3147 3148 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma_channel")); 3149 } 3150 3151 /*ARGSUSED*/ 3152 static nxge_status_t 3153 nxge_map_rxdma_channel_cfg_ring(p_nxge_t nxgep, uint16_t dma_channel, 3154 p_nxge_dma_common_t *dma_cntl_p, p_rx_rbr_ring_t *rbr_p, 3155 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 3156 { 3157 p_rx_rbr_ring_t rbrp; 3158 p_rx_rcr_ring_t rcrp; 3159 p_rx_mbox_t mboxp; 3160 p_nxge_dma_common_t cntl_dmap; 3161 p_nxge_dma_common_t dmap; 3162 p_rx_msg_t *rx_msg_ring; 3163 p_rx_msg_t rx_msg_p; 3164 p_rbr_cfig_a_t rcfga_p; 3165 p_rbr_cfig_b_t rcfgb_p; 3166 p_rcrcfig_a_t cfga_p; 3167 p_rcrcfig_b_t cfgb_p; 3168 p_rxdma_cfig1_t cfig1_p; 3169 p_rxdma_cfig2_t cfig2_p; 3170 p_rbr_kick_t kick_p; 3171 uint32_t dmaaddrp; 3172 uint32_t *rbr_vaddrp; 3173 uint32_t bkaddr; 3174 nxge_status_t status = NXGE_OK; 3175 int i; 3176 uint32_t nxge_port_rcr_size; 3177 3178 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3179 "==> nxge_map_rxdma_channel_cfg_ring")); 3180 3181 cntl_dmap = *dma_cntl_p; 3182 3183 /* Map in the receive block ring */ 3184 rbrp = *rbr_p; 3185 dmap = (p_nxge_dma_common_t)&rbrp->rbr_desc; 3186 nxge_setup_dma_common(dmap, cntl_dmap, rbrp->rbb_max, 4); 3187 /* 3188 * Zero out buffer block ring descriptors. 3189 */ 3190 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3191 3192 rcfga_p = &(rbrp->rbr_cfga); 3193 rcfgb_p = &(rbrp->rbr_cfgb); 3194 kick_p = &(rbrp->rbr_kick); 3195 rcfga_p->value = 0; 3196 rcfgb_p->value = 0; 3197 kick_p->value = 0; 3198 rbrp->rbr_addr = dmap->dma_cookie.dmac_laddress; 3199 rcfga_p->value = (rbrp->rbr_addr & 3200 (RBR_CFIG_A_STDADDR_MASK | 3201 RBR_CFIG_A_STDADDR_BASE_MASK)); 3202 rcfga_p->value |= ((uint64_t)rbrp->rbb_max << RBR_CFIG_A_LEN_SHIFT); 3203 3204 rcfgb_p->bits.ldw.bufsz0 = rbrp->pkt_buf_size0; 3205 rcfgb_p->bits.ldw.vld0 = 1; 3206 rcfgb_p->bits.ldw.bufsz1 = rbrp->pkt_buf_size1; 3207 rcfgb_p->bits.ldw.vld1 = 1; 3208 rcfgb_p->bits.ldw.bufsz2 = rbrp->pkt_buf_size2; 3209 rcfgb_p->bits.ldw.vld2 = 1; 3210 rcfgb_p->bits.ldw.bksize = nxgep->rx_bksize_code; 3211 3212 /* 3213 * For each buffer block, enter receive block address to the ring. 3214 */ 3215 rbr_vaddrp = (uint32_t *)dmap->kaddrp; 3216 rbrp->rbr_desc_vp = (uint32_t *)dmap->kaddrp; 3217 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3218 "==> nxge_map_rxdma_channel_cfg_ring: channel %d " 3219 "rbr_vaddrp $%p", dma_channel, rbr_vaddrp)); 3220 3221 rx_msg_ring = rbrp->rx_msg_ring; 3222 for (i = 0; i < rbrp->tnblocks; i++) { 3223 rx_msg_p = rx_msg_ring[i]; 3224 rx_msg_p->nxgep = nxgep; 3225 rx_msg_p->rx_rbr_p = rbrp; 3226 bkaddr = (uint32_t) 3227 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress 3228 >> RBR_BKADDR_SHIFT)); 3229 rx_msg_p->free = B_FALSE; 3230 rx_msg_p->max_usage_cnt = 0xbaddcafe; 3231 3232 *rbr_vaddrp++ = bkaddr; 3233 } 3234 3235 kick_p->bits.ldw.bkadd = rbrp->rbb_max; 3236 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 3237 3238 rbrp->rbr_rd_index = 0; 3239 3240 rbrp->rbr_consumed = 0; 3241 rbrp->rbr_use_bcopy = B_TRUE; 3242 rbrp->rbr_bufsize_type = RCR_PKTBUFSZ_0; 3243 /* 3244 * Do bcopy on packets greater than bcopy size once 3245 * the lo threshold is reached. 3246 * This lo threshold should be less than the hi threshold. 3247 * 3248 * Do bcopy on every packet once the hi threshold is reached. 3249 */ 3250 if (nxge_rx_threshold_lo >= nxge_rx_threshold_hi) { 3251 /* default it to use hi */ 3252 nxge_rx_threshold_lo = nxge_rx_threshold_hi; 3253 } 3254 3255 if (nxge_rx_buf_size_type > NXGE_RBR_TYPE2) { 3256 nxge_rx_buf_size_type = NXGE_RBR_TYPE2; 3257 } 3258 rbrp->rbr_bufsize_type = nxge_rx_buf_size_type; 3259 3260 switch (nxge_rx_threshold_hi) { 3261 default: 3262 case NXGE_RX_COPY_NONE: 3263 /* Do not do bcopy at all */ 3264 rbrp->rbr_use_bcopy = B_FALSE; 3265 rbrp->rbr_threshold_hi = rbrp->rbb_max; 3266 break; 3267 3268 case NXGE_RX_COPY_1: 3269 case NXGE_RX_COPY_2: 3270 case NXGE_RX_COPY_3: 3271 case NXGE_RX_COPY_4: 3272 case NXGE_RX_COPY_5: 3273 case NXGE_RX_COPY_6: 3274 case NXGE_RX_COPY_7: 3275 rbrp->rbr_threshold_hi = 3276 rbrp->rbb_max * 3277 (nxge_rx_threshold_hi)/NXGE_RX_BCOPY_SCALE; 3278 break; 3279 3280 case NXGE_RX_COPY_ALL: 3281 rbrp->rbr_threshold_hi = 0; 3282 break; 3283 } 3284 3285 switch (nxge_rx_threshold_lo) { 3286 default: 3287 case NXGE_RX_COPY_NONE: 3288 /* Do not do bcopy at all */ 3289 if (rbrp->rbr_use_bcopy) { 3290 rbrp->rbr_use_bcopy = B_FALSE; 3291 } 3292 rbrp->rbr_threshold_lo = rbrp->rbb_max; 3293 break; 3294 3295 case NXGE_RX_COPY_1: 3296 case NXGE_RX_COPY_2: 3297 case NXGE_RX_COPY_3: 3298 case NXGE_RX_COPY_4: 3299 case NXGE_RX_COPY_5: 3300 case NXGE_RX_COPY_6: 3301 case NXGE_RX_COPY_7: 3302 rbrp->rbr_threshold_lo = 3303 rbrp->rbb_max * 3304 (nxge_rx_threshold_lo)/NXGE_RX_BCOPY_SCALE; 3305 break; 3306 3307 case NXGE_RX_COPY_ALL: 3308 rbrp->rbr_threshold_lo = 0; 3309 break; 3310 } 3311 3312 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3313 "nxge_map_rxdma_channel_cfg_ring: channel %d " 3314 "rbb_max %d " 3315 "rbrp->rbr_bufsize_type %d " 3316 "rbb_threshold_hi %d " 3317 "rbb_threshold_lo %d", 3318 dma_channel, 3319 rbrp->rbb_max, 3320 rbrp->rbr_bufsize_type, 3321 rbrp->rbr_threshold_hi, 3322 rbrp->rbr_threshold_lo)); 3323 3324 rbrp->page_valid.value = 0; 3325 rbrp->page_mask_1.value = rbrp->page_mask_2.value = 0; 3326 rbrp->page_value_1.value = rbrp->page_value_2.value = 0; 3327 rbrp->page_reloc_1.value = rbrp->page_reloc_2.value = 0; 3328 rbrp->page_hdl.value = 0; 3329 3330 rbrp->page_valid.bits.ldw.page0 = 1; 3331 rbrp->page_valid.bits.ldw.page1 = 1; 3332 3333 /* Map in the receive completion ring */ 3334 rcrp = (p_rx_rcr_ring_t) 3335 KMEM_ZALLOC(sizeof (rx_rcr_ring_t), KM_SLEEP); 3336 rcrp->rdc = dma_channel; 3337 3338 nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 3339 rcrp->comp_size = nxge_port_rcr_size; 3340 rcrp->comp_wrap_mask = nxge_port_rcr_size - 1; 3341 3342 rcrp->max_receive_pkts = nxge_max_rx_pkts; 3343 3344 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 3345 nxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size, 3346 sizeof (rcr_entry_t)); 3347 rcrp->comp_rd_index = 0; 3348 rcrp->comp_wt_index = 0; 3349 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 3350 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 3351 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3352 #if defined(__i386) 3353 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3354 #else 3355 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3356 #endif 3357 3358 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 3359 (nxge_port_rcr_size - 1); 3360 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 3361 (nxge_port_rcr_size - 1); 3362 3363 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3364 "==> nxge_map_rxdma_channel_cfg_ring: " 3365 "channel %d " 3366 "rbr_vaddrp $%p " 3367 "rcr_desc_rd_head_p $%p " 3368 "rcr_desc_rd_head_pp $%p " 3369 "rcr_desc_rd_last_p $%p " 3370 "rcr_desc_rd_last_pp $%p ", 3371 dma_channel, 3372 rbr_vaddrp, 3373 rcrp->rcr_desc_rd_head_p, 3374 rcrp->rcr_desc_rd_head_pp, 3375 rcrp->rcr_desc_last_p, 3376 rcrp->rcr_desc_last_pp)); 3377 3378 /* 3379 * Zero out buffer block ring descriptors. 3380 */ 3381 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3382 rcrp->intr_timeout = nxgep->intr_timeout; 3383 rcrp->intr_threshold = nxgep->intr_threshold; 3384 rcrp->full_hdr_flag = B_FALSE; 3385 rcrp->sw_priv_hdr_len = 0; 3386 3387 cfga_p = &(rcrp->rcr_cfga); 3388 cfgb_p = &(rcrp->rcr_cfgb); 3389 cfga_p->value = 0; 3390 cfgb_p->value = 0; 3391 rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress; 3392 cfga_p->value = (rcrp->rcr_addr & 3393 (RCRCFIG_A_STADDR_MASK | 3394 RCRCFIG_A_STADDR_BASE_MASK)); 3395 3396 rcfga_p->value |= ((uint64_t)rcrp->comp_size << 3397 RCRCFIG_A_LEN_SHIF); 3398 3399 /* 3400 * Timeout should be set based on the system clock divider. 3401 * The following timeout value of 1 assumes that the 3402 * granularity (1000) is 3 microseconds running at 300MHz. 3403 */ 3404 cfgb_p->bits.ldw.pthres = rcrp->intr_threshold; 3405 cfgb_p->bits.ldw.timeout = rcrp->intr_timeout; 3406 cfgb_p->bits.ldw.entout = 1; 3407 3408 /* Map in the mailbox */ 3409 mboxp = (p_rx_mbox_t) 3410 KMEM_ZALLOC(sizeof (rx_mbox_t), KM_SLEEP); 3411 dmap = (p_nxge_dma_common_t)&mboxp->rx_mbox; 3412 nxge_setup_dma_common(dmap, cntl_dmap, 1, sizeof (rxdma_mailbox_t)); 3413 cfig1_p = (p_rxdma_cfig1_t)&mboxp->rx_cfg1; 3414 cfig2_p = (p_rxdma_cfig2_t)&mboxp->rx_cfg2; 3415 cfig1_p->value = cfig2_p->value = 0; 3416 3417 mboxp->mbox_addr = dmap->dma_cookie.dmac_laddress; 3418 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3419 "==> nxge_map_rxdma_channel_cfg_ring: " 3420 "channel %d cfg1 0x%016llx cfig2 0x%016llx cookie 0x%016llx", 3421 dma_channel, cfig1_p->value, cfig2_p->value, 3422 mboxp->mbox_addr)); 3423 3424 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress >> 32 3425 & 0xfff); 3426 cfig1_p->bits.ldw.mbaddr_h = dmaaddrp; 3427 3428 3429 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 0xffffffff); 3430 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 3431 RXDMA_CFIG2_MBADDR_L_MASK); 3432 3433 cfig2_p->bits.ldw.mbaddr = (dmaaddrp >> RXDMA_CFIG2_MBADDR_L_SHIFT); 3434 3435 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3436 "==> nxge_map_rxdma_channel_cfg_ring: " 3437 "channel %d damaddrp $%p " 3438 "cfg1 0x%016llx cfig2 0x%016llx", 3439 dma_channel, dmaaddrp, 3440 cfig1_p->value, cfig2_p->value)); 3441 3442 cfig2_p->bits.ldw.full_hdr = rcrp->full_hdr_flag; 3443 cfig2_p->bits.ldw.offset = rcrp->sw_priv_hdr_len; 3444 3445 rbrp->rx_rcr_p = rcrp; 3446 rcrp->rx_rbr_p = rbrp; 3447 *rcr_p = rcrp; 3448 *rx_mbox_p = mboxp; 3449 3450 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3451 "<== nxge_map_rxdma_channel_cfg_ring status 0x%08x", status)); 3452 3453 return (status); 3454 } 3455 3456 /*ARGSUSED*/ 3457 static void 3458 nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t nxgep, 3459 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 3460 { 3461 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3462 "==> nxge_unmap_rxdma_channel_cfg_ring: channel %d", 3463 rcr_p->rdc)); 3464 3465 KMEM_FREE(rcr_p, sizeof (rx_rcr_ring_t)); 3466 KMEM_FREE(rx_mbox_p, sizeof (rx_mbox_t)); 3467 3468 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3469 "<== nxge_unmap_rxdma_channel_cfg_ring")); 3470 } 3471 3472 static nxge_status_t 3473 nxge_map_rxdma_channel_buf_ring(p_nxge_t nxgep, uint16_t channel, 3474 p_nxge_dma_common_t *dma_buf_p, 3475 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks) 3476 { 3477 p_rx_rbr_ring_t rbrp; 3478 p_nxge_dma_common_t dma_bufp, tmp_bufp; 3479 p_rx_msg_t *rx_msg_ring; 3480 p_rx_msg_t rx_msg_p; 3481 p_mblk_t mblk_p; 3482 3483 rxring_info_t *ring_info; 3484 nxge_status_t status = NXGE_OK; 3485 int i, j, index; 3486 uint32_t size, bsize, nblocks, nmsgs; 3487 3488 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3489 "==> nxge_map_rxdma_channel_buf_ring: channel %d", 3490 channel)); 3491 3492 dma_bufp = tmp_bufp = *dma_buf_p; 3493 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3494 " nxge_map_rxdma_channel_buf_ring: channel %d to map %d " 3495 "chunks bufp 0x%016llx", 3496 channel, num_chunks, dma_bufp)); 3497 3498 nmsgs = 0; 3499 for (i = 0; i < num_chunks; i++, tmp_bufp++) { 3500 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3501 "==> nxge_map_rxdma_channel_buf_ring: channel %d " 3502 "bufp 0x%016llx nblocks %d nmsgs %d", 3503 channel, tmp_bufp, tmp_bufp->nblocks, nmsgs)); 3504 nmsgs += tmp_bufp->nblocks; 3505 } 3506 if (!nmsgs) { 3507 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3508 "<== nxge_map_rxdma_channel_buf_ring: channel %d " 3509 "no msg blocks", 3510 channel)); 3511 status = NXGE_ERROR; 3512 goto nxge_map_rxdma_channel_buf_ring_exit; 3513 } 3514 3515 rbrp = (p_rx_rbr_ring_t)KMEM_ZALLOC(sizeof (*rbrp), KM_SLEEP); 3516 3517 size = nmsgs * sizeof (p_rx_msg_t); 3518 rx_msg_ring = KMEM_ZALLOC(size, KM_SLEEP); 3519 ring_info = (rxring_info_t *)KMEM_ZALLOC(sizeof (rxring_info_t), 3520 KM_SLEEP); 3521 3522 MUTEX_INIT(&rbrp->lock, NULL, MUTEX_DRIVER, 3523 (void *)nxgep->interrupt_cookie); 3524 MUTEX_INIT(&rbrp->post_lock, NULL, MUTEX_DRIVER, 3525 (void *)nxgep->interrupt_cookie); 3526 rbrp->rdc = channel; 3527 rbrp->num_blocks = num_chunks; 3528 rbrp->tnblocks = nmsgs; 3529 rbrp->rbb_max = nmsgs; 3530 rbrp->rbr_max_size = nmsgs; 3531 rbrp->rbr_wrap_mask = (rbrp->rbb_max - 1); 3532 3533 /* 3534 * Buffer sizes suggested by NIU architect. 3535 * 256, 512 and 2K. 3536 */ 3537 3538 rbrp->pkt_buf_size0 = RBR_BUFSZ0_256B; 3539 rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_256_BYTES; 3540 rbrp->npi_pkt_buf_size0 = SIZE_256B; 3541 3542 rbrp->pkt_buf_size1 = RBR_BUFSZ1_1K; 3543 rbrp->pkt_buf_size1_bytes = RBR_BUFSZ1_1K_BYTES; 3544 rbrp->npi_pkt_buf_size1 = SIZE_1KB; 3545 3546 rbrp->block_size = nxgep->rx_default_block_size; 3547 3548 if (!nxge_jumbo_enable && !nxgep->param_arr[param_accept_jumbo].value) { 3549 rbrp->pkt_buf_size2 = RBR_BUFSZ2_2K; 3550 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_2K_BYTES; 3551 rbrp->npi_pkt_buf_size2 = SIZE_2KB; 3552 } else { 3553 if (rbrp->block_size >= 0x2000) { 3554 rbrp->pkt_buf_size2 = RBR_BUFSZ2_8K; 3555 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_8K_BYTES; 3556 rbrp->npi_pkt_buf_size2 = SIZE_8KB; 3557 } else { 3558 rbrp->pkt_buf_size2 = RBR_BUFSZ2_4K; 3559 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_4K_BYTES; 3560 rbrp->npi_pkt_buf_size2 = SIZE_4KB; 3561 } 3562 } 3563 3564 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3565 "==> nxge_map_rxdma_channel_buf_ring: channel %d " 3566 "actual rbr max %d rbb_max %d nmsgs %d " 3567 "rbrp->block_size %d default_block_size %d " 3568 "(config nxge_rbr_size %d nxge_rbr_spare_size %d)", 3569 channel, rbrp->rbr_max_size, rbrp->rbb_max, nmsgs, 3570 rbrp->block_size, nxgep->rx_default_block_size, 3571 nxge_rbr_size, nxge_rbr_spare_size)); 3572 3573 /* Map in buffers from the buffer pool. */ 3574 index = 0; 3575 for (i = 0; i < rbrp->num_blocks; i++, dma_bufp++) { 3576 bsize = dma_bufp->block_size; 3577 nblocks = dma_bufp->nblocks; 3578 #if defined(__i386) 3579 ring_info->buffer[i].dvma_addr = (uint32_t)dma_bufp->ioaddr_pp; 3580 #else 3581 ring_info->buffer[i].dvma_addr = (uint64_t)dma_bufp->ioaddr_pp; 3582 #endif 3583 ring_info->buffer[i].buf_index = i; 3584 ring_info->buffer[i].buf_size = dma_bufp->alength; 3585 ring_info->buffer[i].start_index = index; 3586 #if defined(__i386) 3587 ring_info->buffer[i].kaddr = (uint32_t)dma_bufp->kaddrp; 3588 #else 3589 ring_info->buffer[i].kaddr = (uint64_t)dma_bufp->kaddrp; 3590 #endif 3591 3592 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3593 " nxge_map_rxdma_channel_buf_ring: map channel %d " 3594 "chunk %d" 3595 " nblocks %d chunk_size %x block_size 0x%x " 3596 "dma_bufp $%p", channel, i, 3597 dma_bufp->nblocks, ring_info->buffer[i].buf_size, bsize, 3598 dma_bufp)); 3599 3600 for (j = 0; j < nblocks; j++) { 3601 if ((rx_msg_p = nxge_allocb(bsize, BPRI_LO, 3602 dma_bufp)) == NULL) { 3603 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3604 "allocb failed (index %d i %d j %d)", 3605 index, i, j)); 3606 goto nxge_map_rxdma_channel_buf_ring_fail1; 3607 } 3608 rx_msg_ring[index] = rx_msg_p; 3609 rx_msg_p->block_index = index; 3610 rx_msg_p->shifted_addr = (uint32_t) 3611 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 3612 RBR_BKADDR_SHIFT)); 3613 3614 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3615 "index %d j %d rx_msg_p $%p mblk %p", 3616 index, j, rx_msg_p, rx_msg_p->rx_mblk_p)); 3617 3618 mblk_p = rx_msg_p->rx_mblk_p; 3619 mblk_p->b_wptr = mblk_p->b_rptr + bsize; 3620 3621 rbrp->rbr_ref_cnt++; 3622 index++; 3623 rx_msg_p->buf_dma.dma_channel = channel; 3624 } 3625 } 3626 if (i < rbrp->num_blocks) { 3627 goto nxge_map_rxdma_channel_buf_ring_fail1; 3628 } 3629 3630 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3631 "nxge_map_rxdma_channel_buf_ring: done buf init " 3632 "channel %d msg block entries %d", 3633 channel, index)); 3634 ring_info->block_size_mask = bsize - 1; 3635 rbrp->rx_msg_ring = rx_msg_ring; 3636 rbrp->dma_bufp = dma_buf_p; 3637 rbrp->ring_info = ring_info; 3638 3639 status = nxge_rxbuf_index_info_init(nxgep, rbrp); 3640 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3641 " nxge_map_rxdma_channel_buf_ring: " 3642 "channel %d done buf info init", channel)); 3643 3644 /* 3645 * Finally, permit nxge_freeb() to call nxge_post_page(). 3646 */ 3647 rbrp->rbr_state = RBR_POSTING; 3648 3649 *rbr_p = rbrp; 3650 goto nxge_map_rxdma_channel_buf_ring_exit; 3651 3652 nxge_map_rxdma_channel_buf_ring_fail1: 3653 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3654 " nxge_map_rxdma_channel_buf_ring: failed channel (0x%x)", 3655 channel, status)); 3656 3657 index--; 3658 for (; index >= 0; index--) { 3659 rx_msg_p = rx_msg_ring[index]; 3660 if (rx_msg_p != NULL) { 3661 freeb(rx_msg_p->rx_mblk_p); 3662 rx_msg_ring[index] = NULL; 3663 } 3664 } 3665 nxge_map_rxdma_channel_buf_ring_fail: 3666 MUTEX_DESTROY(&rbrp->post_lock); 3667 MUTEX_DESTROY(&rbrp->lock); 3668 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3669 KMEM_FREE(rx_msg_ring, size); 3670 KMEM_FREE(rbrp, sizeof (rx_rbr_ring_t)); 3671 3672 status = NXGE_ERROR; 3673 3674 nxge_map_rxdma_channel_buf_ring_exit: 3675 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3676 "<== nxge_map_rxdma_channel_buf_ring status 0x%08x", status)); 3677 3678 return (status); 3679 } 3680 3681 /*ARGSUSED*/ 3682 static void 3683 nxge_unmap_rxdma_channel_buf_ring(p_nxge_t nxgep, 3684 p_rx_rbr_ring_t rbr_p) 3685 { 3686 p_rx_msg_t *rx_msg_ring; 3687 p_rx_msg_t rx_msg_p; 3688 rxring_info_t *ring_info; 3689 int i; 3690 uint32_t size; 3691 #ifdef NXGE_DEBUG 3692 int num_chunks; 3693 #endif 3694 3695 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3696 "==> nxge_unmap_rxdma_channel_buf_ring")); 3697 if (rbr_p == NULL) { 3698 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3699 "<== nxge_unmap_rxdma_channel_buf_ring: NULL rbrp")); 3700 return; 3701 } 3702 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3703 "==> nxge_unmap_rxdma_channel_buf_ring: channel %d", 3704 rbr_p->rdc)); 3705 3706 rx_msg_ring = rbr_p->rx_msg_ring; 3707 ring_info = rbr_p->ring_info; 3708 3709 if (rx_msg_ring == NULL || ring_info == NULL) { 3710 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3711 "<== nxge_unmap_rxdma_channel_buf_ring: " 3712 "rx_msg_ring $%p ring_info $%p", 3713 rx_msg_p, ring_info)); 3714 return; 3715 } 3716 3717 #ifdef NXGE_DEBUG 3718 num_chunks = rbr_p->num_blocks; 3719 #endif 3720 size = rbr_p->tnblocks * sizeof (p_rx_msg_t); 3721 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3722 " nxge_unmap_rxdma_channel_buf_ring: channel %d chunks %d " 3723 "tnblocks %d (max %d) size ptrs %d ", 3724 rbr_p->rdc, num_chunks, 3725 rbr_p->tnblocks, rbr_p->rbr_max_size, size)); 3726 3727 for (i = 0; i < rbr_p->tnblocks; i++) { 3728 rx_msg_p = rx_msg_ring[i]; 3729 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3730 " nxge_unmap_rxdma_channel_buf_ring: " 3731 "rx_msg_p $%p", 3732 rx_msg_p)); 3733 if (rx_msg_p != NULL) { 3734 freeb(rx_msg_p->rx_mblk_p); 3735 rx_msg_ring[i] = NULL; 3736 } 3737 } 3738 3739 /* 3740 * We no longer may use the mutex <post_lock>. By setting 3741 * <rbr_state> to anything but POSTING, we prevent 3742 * nxge_post_page() from accessing a dead mutex. 3743 */ 3744 rbr_p->rbr_state = RBR_UNMAPPING; 3745 MUTEX_DESTROY(&rbr_p->post_lock); 3746 3747 MUTEX_DESTROY(&rbr_p->lock); 3748 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3749 KMEM_FREE(rx_msg_ring, size); 3750 3751 if (rbr_p->rbr_ref_cnt == 0) { 3752 /* This is the normal state of affairs. */ 3753 KMEM_FREE(rbr_p, sizeof (*rbr_p)); 3754 } else { 3755 /* 3756 * Some of our buffers are still being used. 3757 * Therefore, tell nxge_freeb() this ring is 3758 * unmapped, so it may free <rbr_p> for us. 3759 */ 3760 rbr_p->rbr_state = RBR_UNMAPPED; 3761 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3762 "unmap_rxdma_buf_ring: %d %s outstanding.", 3763 rbr_p->rbr_ref_cnt, 3764 rbr_p->rbr_ref_cnt == 1 ? "msg" : "msgs")); 3765 } 3766 3767 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3768 "<== nxge_unmap_rxdma_channel_buf_ring")); 3769 } 3770 3771 static nxge_status_t 3772 nxge_rxdma_hw_start_common(p_nxge_t nxgep) 3773 { 3774 nxge_status_t status = NXGE_OK; 3775 3776 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 3777 3778 /* 3779 * Load the sharable parameters by writing to the 3780 * function zero control registers. These FZC registers 3781 * should be initialized only once for the entire chip. 3782 */ 3783 (void) nxge_init_fzc_rx_common(nxgep); 3784 3785 /* 3786 * Initialize the RXDMA port specific FZC control configurations. 3787 * These FZC registers are pertaining to each port. 3788 */ 3789 (void) nxge_init_fzc_rxdma_port(nxgep); 3790 3791 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 3792 3793 return (status); 3794 } 3795 3796 /*ARGSUSED*/ 3797 static void 3798 nxge_rxdma_hw_stop_common(p_nxge_t nxgep) 3799 { 3800 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop_common")); 3801 3802 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop_common")); 3803 } 3804 3805 static nxge_status_t 3806 nxge_rxdma_hw_start(p_nxge_t nxgep) 3807 { 3808 int i, ndmas; 3809 uint16_t channel; 3810 p_rx_rbr_rings_t rx_rbr_rings; 3811 p_rx_rbr_ring_t *rbr_rings; 3812 p_rx_rcr_rings_t rx_rcr_rings; 3813 p_rx_rcr_ring_t *rcr_rings; 3814 p_rx_mbox_areas_t rx_mbox_areas_p; 3815 p_rx_mbox_t *rx_mbox_p; 3816 nxge_status_t status = NXGE_OK; 3817 3818 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start")); 3819 3820 rx_rbr_rings = nxgep->rx_rbr_rings; 3821 rx_rcr_rings = nxgep->rx_rcr_rings; 3822 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3823 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3824 "<== nxge_rxdma_hw_start: NULL ring pointers")); 3825 return (NXGE_ERROR); 3826 } 3827 ndmas = rx_rbr_rings->ndmas; 3828 if (ndmas == 0) { 3829 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3830 "<== nxge_rxdma_hw_start: no dma channel allocated")); 3831 return (NXGE_ERROR); 3832 } 3833 3834 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3835 "==> nxge_rxdma_hw_start (ndmas %d)", ndmas)); 3836 3837 rbr_rings = rx_rbr_rings->rbr_rings; 3838 rcr_rings = rx_rcr_rings->rcr_rings; 3839 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 3840 if (rx_mbox_areas_p) { 3841 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 3842 } 3843 3844 for (i = 0; i < ndmas; i++) { 3845 channel = rbr_rings[i]->rdc; 3846 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3847 "==> nxge_rxdma_hw_start (ndmas %d) channel %d", 3848 ndmas, channel)); 3849 status = nxge_rxdma_start_channel(nxgep, channel, 3850 (p_rx_rbr_ring_t)rbr_rings[i], 3851 (p_rx_rcr_ring_t)rcr_rings[i], 3852 (p_rx_mbox_t)rx_mbox_p[i]); 3853 if (status != NXGE_OK) { 3854 goto nxge_rxdma_hw_start_fail1; 3855 } 3856 } 3857 3858 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start: " 3859 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3860 rx_rbr_rings, rx_rcr_rings)); 3861 3862 goto nxge_rxdma_hw_start_exit; 3863 3864 nxge_rxdma_hw_start_fail1: 3865 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3866 "==> nxge_rxdma_hw_start: disable " 3867 "(status 0x%x channel %d i %d)", status, channel, i)); 3868 for (; i >= 0; i--) { 3869 channel = rbr_rings[i]->rdc; 3870 (void) nxge_rxdma_stop_channel(nxgep, channel); 3871 } 3872 3873 nxge_rxdma_hw_start_exit: 3874 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3875 "==> nxge_rxdma_hw_start: (status 0x%x)", status)); 3876 3877 return (status); 3878 } 3879 3880 static void 3881 nxge_rxdma_hw_stop(p_nxge_t nxgep) 3882 { 3883 int i, ndmas; 3884 uint16_t channel; 3885 p_rx_rbr_rings_t rx_rbr_rings; 3886 p_rx_rbr_ring_t *rbr_rings; 3887 p_rx_rcr_rings_t rx_rcr_rings; 3888 3889 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop")); 3890 3891 rx_rbr_rings = nxgep->rx_rbr_rings; 3892 rx_rcr_rings = nxgep->rx_rcr_rings; 3893 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3894 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3895 "<== nxge_rxdma_hw_stop: NULL ring pointers")); 3896 return; 3897 } 3898 ndmas = rx_rbr_rings->ndmas; 3899 if (!ndmas) { 3900 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3901 "<== nxge_rxdma_hw_stop: no dma channel allocated")); 3902 return; 3903 } 3904 3905 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3906 "==> nxge_rxdma_hw_stop (ndmas %d)", ndmas)); 3907 3908 rbr_rings = rx_rbr_rings->rbr_rings; 3909 3910 for (i = 0; i < ndmas; i++) { 3911 channel = rbr_rings[i]->rdc; 3912 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3913 "==> nxge_rxdma_hw_stop (ndmas %d) channel %d", 3914 ndmas, channel)); 3915 (void) nxge_rxdma_stop_channel(nxgep, channel); 3916 } 3917 3918 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop: " 3919 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3920 rx_rbr_rings, rx_rcr_rings)); 3921 3922 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_hw_stop")); 3923 } 3924 3925 3926 static nxge_status_t 3927 nxge_rxdma_start_channel(p_nxge_t nxgep, uint16_t channel, 3928 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 3929 3930 { 3931 npi_handle_t handle; 3932 npi_status_t rs = NPI_SUCCESS; 3933 rx_dma_ctl_stat_t cs; 3934 rx_dma_ent_msk_t ent_mask; 3935 nxge_status_t status = NXGE_OK; 3936 3937 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel")); 3938 3939 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3940 3941 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "nxge_rxdma_start_channel: " 3942 "npi handle addr $%p acc $%p", 3943 nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 3944 3945 /* Reset RXDMA channel */ 3946 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 3947 if (rs != NPI_SUCCESS) { 3948 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3949 "==> nxge_rxdma_start_channel: " 3950 "reset rxdma failed (0x%08x channel %d)", 3951 status, channel)); 3952 return (NXGE_ERROR | rs); 3953 } 3954 3955 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3956 "==> nxge_rxdma_start_channel: reset done: channel %d", 3957 channel)); 3958 3959 /* 3960 * Initialize the RXDMA channel specific FZC control 3961 * configurations. These FZC registers are pertaining 3962 * to each RX channel (logical pages). 3963 */ 3964 status = nxge_init_fzc_rxdma_channel(nxgep, 3965 channel, rbr_p, rcr_p, mbox_p); 3966 if (status != NXGE_OK) { 3967 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3968 "==> nxge_rxdma_start_channel: " 3969 "init fzc rxdma failed (0x%08x channel %d)", 3970 status, channel)); 3971 return (status); 3972 } 3973 3974 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3975 "==> nxge_rxdma_start_channel: fzc done")); 3976 3977 /* 3978 * Zero out the shadow and prefetch ram. 3979 */ 3980 3981 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3982 "ram done")); 3983 3984 /* Set up the interrupt event masks. */ 3985 ent_mask.value = 0; 3986 ent_mask.value |= RX_DMA_ENT_MSK_RBREMPTY_MASK; 3987 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 3988 &ent_mask); 3989 if (rs != NPI_SUCCESS) { 3990 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3991 "==> nxge_rxdma_start_channel: " 3992 "init rxdma event masks failed (0x%08x channel %d)", 3993 status, channel)); 3994 return (NXGE_ERROR | rs); 3995 } 3996 3997 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3998 "event done: channel %d (mask 0x%016llx)", 3999 channel, ent_mask.value)); 4000 4001 /* Initialize the receive DMA control and status register */ 4002 cs.value = 0; 4003 cs.bits.hdw.mex = 1; 4004 cs.bits.hdw.rcrthres = 1; 4005 cs.bits.hdw.rcrto = 1; 4006 cs.bits.hdw.rbr_empty = 1; 4007 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, &cs); 4008 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 4009 "channel %d rx_dma_cntl_stat 0x%0016llx", channel, cs.value)); 4010 if (status != NXGE_OK) { 4011 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4012 "==> nxge_rxdma_start_channel: " 4013 "init rxdma control register failed (0x%08x channel %d", 4014 status, channel)); 4015 return (status); 4016 } 4017 4018 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 4019 "control done - channel %d cs 0x%016llx", channel, cs.value)); 4020 4021 /* 4022 * Load RXDMA descriptors, buffers, mailbox, 4023 * initialise the receive DMA channels and 4024 * enable each DMA channel. 4025 */ 4026 status = nxge_enable_rxdma_channel(nxgep, 4027 channel, rbr_p, rcr_p, mbox_p); 4028 4029 if (status != NXGE_OK) { 4030 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4031 " nxge_rxdma_start_channel: " 4032 " init enable rxdma failed (0x%08x channel %d)", 4033 status, channel)); 4034 return (status); 4035 } 4036 4037 ent_mask.value = 0; 4038 ent_mask.value |= (RX_DMA_ENT_MSK_WRED_DROP_MASK | 4039 RX_DMA_ENT_MSK_PTDROP_PKT_MASK); 4040 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 4041 &ent_mask); 4042 if (rs != NPI_SUCCESS) { 4043 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4044 "==> nxge_rxdma_start_channel: " 4045 "init rxdma event masks failed (0x%08x channel %d)", 4046 status, channel)); 4047 return (NXGE_ERROR | rs); 4048 } 4049 4050 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 4051 "control done - channel %d cs 0x%016llx", channel, cs.value)); 4052 4053 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 4054 "==> nxge_rxdma_start_channel: enable done")); 4055 4056 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_start_channel")); 4057 4058 return (NXGE_OK); 4059 } 4060 4061 static nxge_status_t 4062 nxge_rxdma_stop_channel(p_nxge_t nxgep, uint16_t channel) 4063 { 4064 npi_handle_t handle; 4065 npi_status_t rs = NPI_SUCCESS; 4066 rx_dma_ctl_stat_t cs; 4067 rx_dma_ent_msk_t ent_mask; 4068 nxge_status_t status = NXGE_OK; 4069 4070 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel")); 4071 4072 handle = NXGE_DEV_NPI_HANDLE(nxgep); 4073 4074 NXGE_DEBUG_MSG((nxgep, RX_CTL, "nxge_rxdma_stop_channel: " 4075 "npi handle addr $%p acc $%p", 4076 nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 4077 4078 /* Reset RXDMA channel */ 4079 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 4080 if (rs != NPI_SUCCESS) { 4081 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4082 " nxge_rxdma_stop_channel: " 4083 " reset rxdma failed (0x%08x channel %d)", 4084 rs, channel)); 4085 return (NXGE_ERROR | rs); 4086 } 4087 4088 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4089 "==> nxge_rxdma_stop_channel: reset done")); 4090 4091 /* Set up the interrupt event masks. */ 4092 ent_mask.value = RX_DMA_ENT_MSK_ALL; 4093 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 4094 &ent_mask); 4095 if (rs != NPI_SUCCESS) { 4096 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4097 "==> nxge_rxdma_stop_channel: " 4098 "set rxdma event masks failed (0x%08x channel %d)", 4099 rs, channel)); 4100 return (NXGE_ERROR | rs); 4101 } 4102 4103 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4104 "==> nxge_rxdma_stop_channel: event done")); 4105 4106 /* Initialize the receive DMA control and status register */ 4107 cs.value = 0; 4108 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, 4109 &cs); 4110 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel: control " 4111 " to default (all 0s) 0x%08x", cs.value)); 4112 if (status != NXGE_OK) { 4113 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4114 " nxge_rxdma_stop_channel: init rxdma" 4115 " control register failed (0x%08x channel %d", 4116 status, channel)); 4117 return (status); 4118 } 4119 4120 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4121 "==> nxge_rxdma_stop_channel: control done")); 4122 4123 /* disable dma channel */ 4124 status = nxge_disable_rxdma_channel(nxgep, channel); 4125 4126 if (status != NXGE_OK) { 4127 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4128 " nxge_rxdma_stop_channel: " 4129 " init enable rxdma failed (0x%08x channel %d)", 4130 status, channel)); 4131 return (status); 4132 } 4133 4134 NXGE_DEBUG_MSG((nxgep, 4135 RX_CTL, "==> nxge_rxdma_stop_channel: disable done")); 4136 4137 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_channel")); 4138 4139 return (NXGE_OK); 4140 } 4141 4142 nxge_status_t 4143 nxge_rxdma_handle_sys_errors(p_nxge_t nxgep) 4144 { 4145 npi_handle_t handle; 4146 p_nxge_rdc_sys_stats_t statsp; 4147 rx_ctl_dat_fifo_stat_t stat; 4148 uint32_t zcp_err_status; 4149 uint32_t ipp_err_status; 4150 nxge_status_t status = NXGE_OK; 4151 npi_status_t rs = NPI_SUCCESS; 4152 boolean_t my_err = B_FALSE; 4153 4154 handle = nxgep->npi_handle; 4155 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 4156 4157 rs = npi_rxdma_rxctl_fifo_error_intr_get(handle, &stat); 4158 4159 if (rs != NPI_SUCCESS) 4160 return (NXGE_ERROR | rs); 4161 4162 if (stat.bits.ldw.id_mismatch) { 4163 statsp->id_mismatch++; 4164 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 4165 NXGE_FM_EREPORT_RDMC_ID_MISMATCH); 4166 /* Global fatal error encountered */ 4167 } 4168 4169 if ((stat.bits.ldw.zcp_eop_err) || (stat.bits.ldw.ipp_eop_err)) { 4170 switch (nxgep->mac.portnum) { 4171 case 0: 4172 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT0) || 4173 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT0)) { 4174 my_err = B_TRUE; 4175 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4176 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4177 } 4178 break; 4179 case 1: 4180 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT1) || 4181 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT1)) { 4182 my_err = B_TRUE; 4183 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4184 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4185 } 4186 break; 4187 case 2: 4188 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT2) || 4189 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT2)) { 4190 my_err = B_TRUE; 4191 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4192 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4193 } 4194 break; 4195 case 3: 4196 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT3) || 4197 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT3)) { 4198 my_err = B_TRUE; 4199 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4200 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4201 } 4202 break; 4203 default: 4204 return (NXGE_ERROR); 4205 } 4206 } 4207 4208 if (my_err) { 4209 status = nxge_rxdma_handle_port_errors(nxgep, ipp_err_status, 4210 zcp_err_status); 4211 if (status != NXGE_OK) 4212 return (status); 4213 } 4214 4215 return (NXGE_OK); 4216 } 4217 4218 static nxge_status_t 4219 nxge_rxdma_handle_port_errors(p_nxge_t nxgep, uint32_t ipp_status, 4220 uint32_t zcp_status) 4221 { 4222 boolean_t rxport_fatal = B_FALSE; 4223 p_nxge_rdc_sys_stats_t statsp; 4224 nxge_status_t status = NXGE_OK; 4225 uint8_t portn; 4226 4227 portn = nxgep->mac.portnum; 4228 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 4229 4230 if (ipp_status & (0x1 << portn)) { 4231 statsp->ipp_eop_err++; 4232 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 4233 NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR); 4234 rxport_fatal = B_TRUE; 4235 } 4236 4237 if (zcp_status & (0x1 << portn)) { 4238 statsp->zcp_eop_err++; 4239 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 4240 NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR); 4241 rxport_fatal = B_TRUE; 4242 } 4243 4244 if (rxport_fatal) { 4245 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4246 " nxge_rxdma_handle_port_error: " 4247 " fatal error on Port #%d\n", 4248 portn)); 4249 status = nxge_rx_port_fatal_err_recover(nxgep); 4250 if (status == NXGE_OK) { 4251 FM_SERVICE_RESTORED(nxgep); 4252 } 4253 } 4254 4255 return (status); 4256 } 4257 4258 static nxge_status_t 4259 nxge_rxdma_fatal_err_recover(p_nxge_t nxgep, uint16_t channel) 4260 { 4261 npi_handle_t handle; 4262 npi_status_t rs = NPI_SUCCESS; 4263 nxge_status_t status = NXGE_OK; 4264 p_rx_rbr_ring_t rbrp; 4265 p_rx_rcr_ring_t rcrp; 4266 p_rx_mbox_t mboxp; 4267 rx_dma_ent_msk_t ent_mask; 4268 p_nxge_dma_common_t dmap; 4269 int ring_idx; 4270 uint32_t ref_cnt; 4271 p_rx_msg_t rx_msg_p; 4272 int i; 4273 uint32_t nxge_port_rcr_size; 4274 4275 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fatal_err_recover")); 4276 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4277 "Recovering from RxDMAChannel#%d error...", channel)); 4278 4279 /* 4280 * Stop the dma channel waits for the stop done. 4281 * If the stop done bit is not set, then create 4282 * an error. 4283 */ 4284 4285 handle = NXGE_DEV_NPI_HANDLE(nxgep); 4286 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Rx DMA stop...")); 4287 4288 ring_idx = nxge_rxdma_get_ring_index(nxgep, channel); 4289 rbrp = (p_rx_rbr_ring_t)nxgep->rx_rbr_rings->rbr_rings[ring_idx]; 4290 rcrp = (p_rx_rcr_ring_t)nxgep->rx_rcr_rings->rcr_rings[ring_idx]; 4291 4292 MUTEX_ENTER(&rcrp->lock); 4293 MUTEX_ENTER(&rbrp->lock); 4294 MUTEX_ENTER(&rbrp->post_lock); 4295 4296 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA channel...")); 4297 4298 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 4299 if (rs != NPI_SUCCESS) { 4300 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4301 "nxge_disable_rxdma_channel:failed")); 4302 goto fail; 4303 } 4304 4305 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA interrupt...")); 4306 4307 /* Disable interrupt */ 4308 ent_mask.value = RX_DMA_ENT_MSK_ALL; 4309 rs = npi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 4310 if (rs != NPI_SUCCESS) { 4311 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4312 "nxge_rxdma_stop_channel: " 4313 "set rxdma event masks failed (channel %d)", 4314 channel)); 4315 } 4316 4317 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel reset...")); 4318 4319 /* Reset RXDMA channel */ 4320 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 4321 if (rs != NPI_SUCCESS) { 4322 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4323 "nxge_rxdma_fatal_err_recover: " 4324 " reset rxdma failed (channel %d)", channel)); 4325 goto fail; 4326 } 4327 4328 nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 4329 4330 mboxp = 4331 (p_rx_mbox_t)nxgep->rx_mbox_areas_p->rxmbox_areas[ring_idx]; 4332 4333 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 4334 rbrp->rbr_rd_index = 0; 4335 4336 rcrp->comp_rd_index = 0; 4337 rcrp->comp_wt_index = 0; 4338 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 4339 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 4340 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 4341 #if defined(__i386) 4342 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 4343 #else 4344 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 4345 #endif 4346 4347 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 4348 (nxge_port_rcr_size - 1); 4349 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 4350 (nxge_port_rcr_size - 1); 4351 4352 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 4353 bzero((caddr_t)dmap->kaddrp, dmap->alength); 4354 4355 cmn_err(CE_NOTE, "!rbr entries = %d\n", rbrp->rbr_max_size); 4356 4357 for (i = 0; i < rbrp->rbr_max_size; i++) { 4358 rx_msg_p = rbrp->rx_msg_ring[i]; 4359 ref_cnt = rx_msg_p->ref_cnt; 4360 if (ref_cnt != 1) { 4361 if (rx_msg_p->cur_usage_cnt != 4362 rx_msg_p->max_usage_cnt) { 4363 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4364 "buf[%d]: cur_usage_cnt = %d " 4365 "max_usage_cnt = %d\n", i, 4366 rx_msg_p->cur_usage_cnt, 4367 rx_msg_p->max_usage_cnt)); 4368 } else { 4369 /* Buffer can be re-posted */ 4370 rx_msg_p->free = B_TRUE; 4371 rx_msg_p->cur_usage_cnt = 0; 4372 rx_msg_p->max_usage_cnt = 0xbaddcafe; 4373 rx_msg_p->pkt_buf_size = 0; 4374 } 4375 } 4376 } 4377 4378 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel re-start...")); 4379 4380 status = nxge_rxdma_start_channel(nxgep, channel, rbrp, rcrp, mboxp); 4381 if (status != NXGE_OK) { 4382 goto fail; 4383 } 4384 4385 MUTEX_EXIT(&rbrp->post_lock); 4386 MUTEX_EXIT(&rbrp->lock); 4387 MUTEX_EXIT(&rcrp->lock); 4388 4389 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4390 "Recovery Successful, RxDMAChannel#%d Restored", 4391 channel)); 4392 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fatal_err_recover")); 4393 4394 return (NXGE_OK); 4395 fail: 4396 MUTEX_EXIT(&rbrp->post_lock); 4397 MUTEX_EXIT(&rbrp->lock); 4398 MUTEX_EXIT(&rcrp->lock); 4399 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 4400 4401 return (NXGE_ERROR | rs); 4402 } 4403 4404 nxge_status_t 4405 nxge_rx_port_fatal_err_recover(p_nxge_t nxgep) 4406 { 4407 nxge_status_t status = NXGE_OK; 4408 p_nxge_dma_common_t *dma_buf_p; 4409 uint16_t channel; 4410 int ndmas; 4411 int i; 4412 4413 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_port_fatal_err_recover")); 4414 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4415 "Recovering from RxPort error...")); 4416 /* Disable RxMAC */ 4417 4418 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxMAC...\n")); 4419 if (nxge_rx_mac_disable(nxgep) != NXGE_OK) 4420 goto fail; 4421 4422 NXGE_DELAY(1000); 4423 4424 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Stop all RxDMA channels...")); 4425 4426 ndmas = nxgep->rx_buf_pool_p->ndmas; 4427 dma_buf_p = nxgep->rx_buf_pool_p->dma_buf_pool_p; 4428 4429 for (i = 0; i < ndmas; i++) { 4430 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 4431 if (nxge_rxdma_fatal_err_recover(nxgep, channel) != NXGE_OK) { 4432 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4433 "Could not recover channel %d", 4434 channel)); 4435 } 4436 } 4437 4438 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Reset IPP...")); 4439 4440 /* Reset IPP */ 4441 if (nxge_ipp_reset(nxgep) != NXGE_OK) { 4442 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4443 "nxge_rx_port_fatal_err_recover: " 4444 "Failed to reset IPP")); 4445 goto fail; 4446 } 4447 4448 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Reset RxMAC...")); 4449 4450 /* Reset RxMAC */ 4451 if (nxge_rx_mac_reset(nxgep) != NXGE_OK) { 4452 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4453 "nxge_rx_port_fatal_err_recover: " 4454 "Failed to reset RxMAC")); 4455 goto fail; 4456 } 4457 4458 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize IPP...")); 4459 4460 /* Re-Initialize IPP */ 4461 if (nxge_ipp_init(nxgep) != NXGE_OK) { 4462 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4463 "nxge_rx_port_fatal_err_recover: " 4464 "Failed to init IPP")); 4465 goto fail; 4466 } 4467 4468 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize RxMAC...")); 4469 4470 /* Re-Initialize RxMAC */ 4471 if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK) { 4472 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4473 "nxge_rx_port_fatal_err_recover: " 4474 "Failed to reset RxMAC")); 4475 goto fail; 4476 } 4477 4478 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-enable RxMAC...")); 4479 4480 /* Re-enable RxMAC */ 4481 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) { 4482 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4483 "nxge_rx_port_fatal_err_recover: " 4484 "Failed to enable RxMAC")); 4485 goto fail; 4486 } 4487 4488 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4489 "Recovery Successful, RxPort Restored")); 4490 4491 return (NXGE_OK); 4492 fail: 4493 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 4494 return (status); 4495 } 4496 4497 void 4498 nxge_rxdma_inject_err(p_nxge_t nxgep, uint32_t err_id, uint8_t chan) 4499 { 4500 rx_dma_ctl_stat_t cs; 4501 rx_ctl_dat_fifo_stat_t cdfs; 4502 4503 switch (err_id) { 4504 case NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR: 4505 case NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR: 4506 case NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR: 4507 case NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR: 4508 case NXGE_FM_EREPORT_RDMC_RBR_TMOUT: 4509 case NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR: 4510 case NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS: 4511 case NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR: 4512 case NXGE_FM_EREPORT_RDMC_RCRINCON: 4513 case NXGE_FM_EREPORT_RDMC_RCRFULL: 4514 case NXGE_FM_EREPORT_RDMC_RBRFULL: 4515 case NXGE_FM_EREPORT_RDMC_RBRLOGPAGE: 4516 case NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE: 4517 case NXGE_FM_EREPORT_RDMC_CONFIG_ERR: 4518 RXDMA_REG_READ64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 4519 chan, &cs.value); 4520 if (err_id == NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR) 4521 cs.bits.hdw.rcr_ack_err = 1; 4522 else if (err_id == NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR) 4523 cs.bits.hdw.dc_fifo_err = 1; 4524 else if (err_id == NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR) 4525 cs.bits.hdw.rcr_sha_par = 1; 4526 else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR) 4527 cs.bits.hdw.rbr_pre_par = 1; 4528 else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_TMOUT) 4529 cs.bits.hdw.rbr_tmout = 1; 4530 else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR) 4531 cs.bits.hdw.rsp_cnt_err = 1; 4532 else if (err_id == NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS) 4533 cs.bits.hdw.byte_en_bus = 1; 4534 else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR) 4535 cs.bits.hdw.rsp_dat_err = 1; 4536 else if (err_id == NXGE_FM_EREPORT_RDMC_CONFIG_ERR) 4537 cs.bits.hdw.config_err = 1; 4538 else if (err_id == NXGE_FM_EREPORT_RDMC_RCRINCON) 4539 cs.bits.hdw.rcrincon = 1; 4540 else if (err_id == NXGE_FM_EREPORT_RDMC_RCRFULL) 4541 cs.bits.hdw.rcrfull = 1; 4542 else if (err_id == NXGE_FM_EREPORT_RDMC_RBRFULL) 4543 cs.bits.hdw.rbrfull = 1; 4544 else if (err_id == NXGE_FM_EREPORT_RDMC_RBRLOGPAGE) 4545 cs.bits.hdw.rbrlogpage = 1; 4546 else if (err_id == NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE) 4547 cs.bits.hdw.cfiglogpage = 1; 4548 #if defined(__i386) 4549 cmn_err(CE_NOTE, "!Write 0x%llx to RX_DMA_CTL_STAT_DBG_REG\n", 4550 cs.value); 4551 #else 4552 cmn_err(CE_NOTE, "!Write 0x%lx to RX_DMA_CTL_STAT_DBG_REG\n", 4553 cs.value); 4554 #endif 4555 RXDMA_REG_WRITE64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 4556 chan, cs.value); 4557 break; 4558 case NXGE_FM_EREPORT_RDMC_ID_MISMATCH: 4559 case NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR: 4560 case NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR: 4561 cdfs.value = 0; 4562 if (err_id == NXGE_FM_EREPORT_RDMC_ID_MISMATCH) 4563 cdfs.bits.ldw.id_mismatch = (1 << nxgep->mac.portnum); 4564 else if (err_id == NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR) 4565 cdfs.bits.ldw.zcp_eop_err = (1 << nxgep->mac.portnum); 4566 else if (err_id == NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR) 4567 cdfs.bits.ldw.ipp_eop_err = (1 << nxgep->mac.portnum); 4568 #if defined(__i386) 4569 cmn_err(CE_NOTE, 4570 "!Write 0x%llx to RX_CTL_DAT_FIFO_STAT_DBG_REG\n", 4571 cdfs.value); 4572 #else 4573 cmn_err(CE_NOTE, 4574 "!Write 0x%lx to RX_CTL_DAT_FIFO_STAT_DBG_REG\n", 4575 cdfs.value); 4576 #endif 4577 RXDMA_REG_WRITE64(nxgep->npi_handle, 4578 RX_CTL_DAT_FIFO_STAT_DBG_REG, chan, cdfs.value); 4579 break; 4580 case NXGE_FM_EREPORT_RDMC_DCF_ERR: 4581 break; 4582 case NXGE_FM_EREPORT_RDMC_RCR_ERR: 4583 break; 4584 } 4585 } 4586