1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <inet/common.h> 30 #include <inet/mi.h> 31 #include <inet/nd.h> 32 33 extern uint64_t npi_debug_level; 34 35 #define NXGE_PARAM_MAC_RW \ 36 NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 37 NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 38 39 #define NXGE_PARAM_MAC_DONT_SHOW \ 40 NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 41 42 #define NXGE_PARAM_RXDMA_RW \ 43 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 44 NXGE_PARAM_READ_PROP 45 46 #define NXGE_PARAM_RXDMA_RWC \ 47 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 48 NXGE_PARAM_READ_PROP 49 50 #define NXGE_PARAM_L2CLASS_CFG \ 51 NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 52 NXGE_PARAM_NDD_WR_OK 53 54 #define NXGE_PARAM_CLASS_RWS \ 55 NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 56 57 #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 58 59 #define SET_RX_INTR_TIME_DISABLE 0 60 #define SET_RX_INTR_TIME_ENABLE 1 61 #define SET_RX_INTR_PKTS 2 62 63 #define BASE_ANY 0 64 #define BASE_BINARY 2 65 #define BASE_HEX 16 66 #define BASE_DECIMAL 10 67 #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 68 #define ALL_FF_32 0xFFFFFFFFUL 69 70 #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 71 #define NXGE_NDD_INFODUMP_BUFF_8K 8192 72 #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 73 #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 74 75 #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 76 ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 77 78 #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 79 ((mblk_t *)pmp)->b_wptr += plen; \ 80 rlen -= plen; \ 81 } 82 83 static int nxge_param_rx_intr_pkts(p_nxge_t, queue_t *, 84 mblk_t *, char *, caddr_t); 85 static int nxge_param_rx_intr_time(p_nxge_t, queue_t *, 86 mblk_t *, char *, caddr_t); 87 static int nxge_param_set_mac(p_nxge_t, queue_t *, 88 mblk_t *, char *, caddr_t); 89 static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 90 mblk_t *, char *, caddr_t); 91 static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 92 mblk_t *, char *, caddr_t); 93 static int nxge_param_set_ether_usr(p_nxge_t, 94 queue_t *, mblk_t *, char *, caddr_t); 95 static int nxge_param_set_ip_usr(p_nxge_t, 96 queue_t *, mblk_t *, char *, caddr_t); 97 static int nxge_param_set_ip_opt(p_nxge_t, 98 queue_t *, mblk_t *, char *, caddr_t); 99 static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 100 queue_t *, mblk_t *, char *, caddr_t); 101 static int nxge_param_set_mac_rdcgrp(p_nxge_t, 102 queue_t *, mblk_t *, char *, caddr_t); 103 static int nxge_param_fflp_hash_init(p_nxge_t, 104 queue_t *, mblk_t *, char *, caddr_t); 105 static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 106 mblk_t *, char *, caddr_t); 107 static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 108 mblk_t *, char *, caddr_t); 109 static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 110 mblk_t *, char *, caddr_t); 111 static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 112 static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 113 p_mblk_t, caddr_t); 114 static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 115 p_mblk_t, caddr_t); 116 static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 117 p_mblk_t, caddr_t); 118 static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 119 p_mblk_t, caddr_t); 120 static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 121 p_mblk_t, caddr_t); 122 static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 123 static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 124 static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 125 static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 126 char *, caddr_t); 127 static int nxge_param_set_npi_debug_flag(p_nxge_t, 128 queue_t *, mblk_t *, char *, caddr_t); 129 static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 130 static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 131 static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 132 static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 133 static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 134 static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 135 static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 136 static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 137 static boolean_t nxge_param_link_update(p_nxge_t); 138 139 /* 140 * Global array of Neptune changable parameters. 141 * This array is initialized to correspond to the default 142 * Neptune 4 port configuration. This array would be copied 143 * into each port's parameter structure and modifed per 144 * fcode and nxge.conf configuration. Later, the parameters are 145 * exported to ndd to display and run-time configuration (at least 146 * some of them). 147 * 148 */ 149 150 static nxge_param_t nxge_param_arr[] = { 151 /* 152 * min max value old hw-name conf-name 153 */ 154 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 155 0, 999, 1000, 0, "instance", "instance"}, 156 157 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 158 0, 999, 1000, 0, "main-instance", "main_instance"}, 159 160 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 161 0, 3, 0, 0, "function-number", "function_number"}, 162 163 /* Partition Id */ 164 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 165 0, 8, 0, 0, "partition-id", "partition_id"}, 166 167 /* Read Write Permission Mode */ 168 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 169 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 170 171 { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ, 172 0, 32, 0, 0, "version", "fw_version"}, 173 174 /* hw cfg types */ 175 /* control the DMA config of Neptune/NIU */ 176 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 177 CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 178 "niu-cfg-type", "niu_cfg_type"}, 179 180 /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 181 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 182 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 183 "tx-qcfg-type", "tx_qcfg_type"}, 184 185 /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 186 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 187 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 188 "rx-qcfg-type", "rx_qcfg_type"}, 189 190 { nxge_param_get_mac, nxge_param_set_mac, 191 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 192 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 193 194 { nxge_param_get_mac, nxge_param_set_mac, 195 NXGE_PARAM_DONT_SHOW, 196 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 197 198 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 199 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 200 201 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 202 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 203 204 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 205 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 206 207 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 208 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 209 210 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 211 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 212 213 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 214 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 215 216 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 217 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 218 219 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 220 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 221 222 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 223 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 224 225 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 226 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 227 228 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 229 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 230 231 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 232 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 233 234 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 235 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 236 237 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 238 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 239 240 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 241 0, 255, 8, 8, "ipg0", "ipg0"}, 242 243 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 244 0, 255, 8, 8, "ipg1", "ipg1"}, 245 246 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 247 0, 255, 4, 4, "ipg2", "ipg2"}, 248 249 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 250 0, 1, 0, 0, "accept-jumbo", "accept_jumbo"}, 251 252 /* Transmit DMA channels */ 253 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 254 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 255 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 256 257 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 258 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 259 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 260 261 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 262 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 263 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 264 { nxge_param_get_txdma_info, NULL, 265 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 266 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 267 268 /* Receive DMA channels */ 269 { nxge_param_get_generic, NULL, 270 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 271 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 272 273 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 274 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 275 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 276 277 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 278 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 279 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 280 "rx-drr-weight", "rx_drr_weight"}, 281 282 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 283 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 284 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 285 286 { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ | 287 NXGE_PARAM_DONT_SHOW, 288 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 289 290 { nxge_param_get_rxdma_info, NULL, 291 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 292 NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 293 "rx-rbr-size", "rx_rbr_size"}, 294 295 { nxge_param_get_rxdma_info, NULL, 296 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 297 NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 298 "rx-rcr-size", "rx_rcr_size"}, 299 300 { nxge_param_get_generic, nxge_param_set_port_rdc, 301 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 302 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 303 304 { nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW, 305 NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 306 RXDMA_RCR_TO_DEFAULT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 307 308 { nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW, 309 NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 310 RXDMA_RCR_PTHRES_DEFAULT, 0, 311 "rxdma-intr-pkts", "rxdma_intr_pkts"}, 312 313 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 314 NXGE_PARAM_DONT_SHOW, 315 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 316 317 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 318 NXGE_PARAM_DONT_SHOW, 319 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 320 321 { nxge_param_get_generic, nxge_param_set_grp_rdc, 322 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 323 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 324 325 { nxge_param_get_generic, nxge_param_set_grp_rdc, 326 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 327 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 328 329 { nxge_param_get_generic, nxge_param_set_grp_rdc, 330 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 331 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 332 333 { nxge_param_get_generic, nxge_param_set_grp_rdc, 334 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 335 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 336 337 { nxge_param_get_generic, nxge_param_set_grp_rdc, 338 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 339 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 340 341 { nxge_param_get_generic, nxge_param_set_grp_rdc, 342 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 343 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 344 345 { nxge_param_get_generic, nxge_param_set_grp_rdc, 346 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 347 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 348 349 { nxge_param_get_generic, nxge_param_set_grp_rdc, 350 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 351 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 352 353 { nxge_param_get_rxdma_rdcgrp_info, NULL, 354 NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW, 355 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 356 357 /* Logical device groups */ 358 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 359 0, 63, 0, 0, "start-ldg", "start_ldg"}, 360 361 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 362 0, 64, 0, 0, "max-ldg", "max_ldg" }, 363 364 /* MAC table information */ 365 { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 366 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 367 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 368 369 /* VLAN table information */ 370 { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 371 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 372 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 373 374 { nxge_param_get_generic, NULL, 375 NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | 376 NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW, 377 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 378 379 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 380 NXGE_PARAM_DONT_SHOW, 381 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 382 383 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 384 NXGE_PARAM_DONT_SHOW, 385 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 386 387 { nxge_param_get_generic, nxge_param_tcam_enable, 388 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 389 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 390 391 { nxge_param_get_generic, nxge_param_hash_lookup_enable, 392 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 393 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 394 395 { nxge_param_get_generic, nxge_param_llc_snap_enable, 396 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 397 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 398 399 { nxge_param_get_generic, nxge_param_fflp_hash_init, 400 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 401 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 402 403 { nxge_param_get_generic, nxge_param_fflp_hash_init, 404 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 405 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 406 407 { nxge_param_get_generic, nxge_param_set_ether_usr, 408 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 409 0, ALL_FF_32, 0x0, 0, 410 "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 411 412 { nxge_param_get_generic, nxge_param_set_ether_usr, 413 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 414 0, ALL_FF_32, 0x0, 0, 415 "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 416 417 { nxge_param_get_generic, nxge_param_set_ip_usr, 418 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 419 0, ALL_FF_32, 0x0, 0, 420 "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 421 422 { nxge_param_get_generic, nxge_param_set_ip_usr, 423 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 424 0, ALL_FF_32, 0x0, 0, 425 "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 426 427 { nxge_param_get_generic, nxge_param_set_ip_usr, 428 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 429 0, ALL_FF_32, 0x0, 0, 430 "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 431 432 { nxge_param_get_generic, nxge_param_set_ip_usr, 433 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 434 0, ALL_FF_32, 0x0, 0, 435 "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 436 437 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 438 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 439 0, ALL_FF_32, 0x0, 0, 440 "class-opt-ip-usr4", "class_opt_ip_usr4"}, 441 442 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 443 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 444 0, ALL_FF_32, 0x0, 0, 445 "class-opt-ip-usr5", "class_opt_ip_usr5"}, 446 447 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 448 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 449 0, ALL_FF_32, 0x0, 0, 450 "class-opt-ip-usr6", "class_opt_ip_usr6"}, 451 452 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 453 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 454 0, ALL_FF_32, 0x0, 0, 455 "class-opt-ip-usr7", "class_opt_ip_usr7"}, 456 457 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 458 NXGE_PARAM_CLASS_RWS, 459 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 460 "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 461 462 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 463 NXGE_PARAM_CLASS_RWS, 464 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 465 "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 466 467 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 468 NXGE_PARAM_CLASS_RWS, 469 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 470 "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 471 472 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 473 NXGE_PARAM_CLASS_RWS, 474 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 475 "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 476 477 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 478 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 479 "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 480 481 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 482 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 483 "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 484 485 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 486 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 487 "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 488 489 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 490 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 491 "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 492 493 { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 494 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 495 0ULL, ALL_FF_64, 0ULL, 0ULL, 496 "nxge-debug-flag", "nxge_debug_flag"}, 497 498 { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 499 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 500 0ULL, ALL_FF_64, 0ULL, 0ULL, 501 "npi-debug-flag", "npi_debug_flag"}, 502 503 { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 504 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 505 506 { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 507 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 508 509 { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ | 510 NXGE_PARAM_DONT_SHOW, 511 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 512 513 { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ | 514 NXGE_PARAM_DONT_SHOW, 515 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 516 517 { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ | 518 NXGE_PARAM_DONT_SHOW, 519 0, 0x0fffffff, 0x0fffffff, 0, 520 "dump-fflp-regs", "dump_fflp_regs"}, 521 522 { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ | 523 NXGE_PARAM_DONT_SHOW, 524 0, 0x0fffffff, 0x0fffffff, 0, 525 "dump-vlan-table", "dump_vlan_table"}, 526 527 { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ | 528 NXGE_PARAM_DONT_SHOW, 529 0, 0x0fffffff, 0x0fffffff, 0, 530 "dump-rdc-table", "dump_rdc_table"}, 531 532 { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ | 533 NXGE_PARAM_DONT_SHOW, 534 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 535 536 { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 537 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 538 }; 539 540 extern void *nxge_list; 541 542 void 543 nxge_get_param_soft_properties(p_nxge_t nxgep) 544 { 545 546 p_nxge_param_t param_arr; 547 uint_t prop_len; 548 int i, j; 549 uint32_t param_count; 550 uint32_t *int_prop_val; 551 552 NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 553 554 param_arr = nxgep->param_arr; 555 param_count = nxgep->param_count; 556 for (i = 0; i < param_count; i++) { 557 if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 558 continue; 559 if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 560 continue; 561 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 562 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 563 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 564 nxgep->dip, 0, param_arr[i].fcode_name, 565 (int **)&int_prop_val, 566 (uint_t *)&prop_len) 567 == DDI_PROP_SUCCESS) { 568 uint32_t *cfg_value; 569 uint64_t prop_count; 570 571 if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 572 prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 573 cfg_value = (uint32_t *)param_arr[i].value; 574 for (j = 0; j < prop_len; j++) { 575 cfg_value[j] = int_prop_val[j]; 576 } 577 prop_count = prop_len; 578 param_arr[i].type |= 579 (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 580 ddi_prop_free(int_prop_val); 581 } 582 continue; 583 } 584 585 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 586 param_arr[i].fcode_name, 587 (int **)&int_prop_val, 588 &prop_len) == DDI_PROP_SUCCESS) { 589 if ((*int_prop_val >= param_arr[i].minimum) && 590 (*int_prop_val <= param_arr[i].maximum)) 591 param_arr[i].value = *int_prop_val; 592 #ifdef NXGE_DEBUG_ERROR 593 else { 594 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 595 "nxge%d: 'prom' file parameter error\n", 596 nxgep->instance)); 597 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 598 "Parameter keyword '%s'" 599 " is outside valid range\n", 600 param_arr[i].name)); 601 } 602 #endif 603 ddi_prop_free(int_prop_val); 604 } 605 606 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 607 param_arr[i].name, 608 (int **)&int_prop_val, 609 &prop_len) == DDI_PROP_SUCCESS) { 610 if ((*int_prop_val >= param_arr[i].minimum) && 611 (*int_prop_val <= param_arr[i].maximum)) 612 param_arr[i].value = *int_prop_val; 613 #ifdef NXGE_DEBUG_ERROR 614 else { 615 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 616 "nxge%d: 'conf' file parameter error\n", 617 nxgep->instance)); 618 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 619 "Parameter keyword '%s'" 620 "is outside valid range\n", 621 param_arr[i].name)); 622 } 623 #endif 624 ddi_prop_free(int_prop_val); 625 } 626 } 627 } 628 629 static int 630 nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 631 { 632 int status = B_TRUE; 633 int channel; 634 uint8_t grp; 635 char *prop_name; 636 char *end; 637 uint32_t name_chars; 638 639 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 640 "nxge_private_param_register %s", param_arr->name)); 641 642 if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 643 return (B_TRUE); 644 645 prop_name = param_arr->name; 646 if (param_arr->type & NXGE_PARAM_RXDMA) { 647 if (strncmp("rxdma_intr", prop_name, 10) == 0) 648 return (B_TRUE); 649 name_chars = strlen("default_grp"); 650 if (strncmp("default_grp", prop_name, name_chars) == 0) { 651 prop_name += name_chars; 652 grp = mi_strtol(prop_name, &end, 10); 653 /* now check if this rdcgrp is in config */ 654 return (nxge_check_rdcgrp_port_member(nxgep, grp)); 655 } 656 name_chars = strlen(prop_name); 657 if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 658 return (B_TRUE); 659 } 660 return (B_FALSE); 661 } 662 663 if (param_arr->type & NXGE_PARAM_TXDMA) { 664 name_chars = strlen("txdma"); 665 if (strncmp("txdma", prop_name, name_chars) == 0) { 666 prop_name += name_chars; 667 channel = mi_strtol(prop_name, &end, 10); 668 /* now check if this rdc is in config */ 669 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 670 " nxge_private_param_register: %d", 671 channel)); 672 return (nxge_check_txdma_port_member(nxgep, channel)); 673 } 674 return (B_FALSE); 675 } 676 677 status = B_FALSE; 678 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 679 680 return (status); 681 } 682 683 void 684 nxge_setup_param(p_nxge_t nxgep) 685 { 686 p_nxge_param_t param_arr; 687 int i; 688 pfi_t set_pfi; 689 690 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 691 692 /* 693 * Make sure the param_instance is set to a valid device instance. 694 */ 695 if (nxge_param_arr[param_instance].value == 1000) 696 nxge_param_arr[param_instance].value = nxgep->instance; 697 698 param_arr = nxgep->param_arr; 699 param_arr[param_instance].value = nxgep->instance; 700 param_arr[param_function_number].value = nxgep->function_num; 701 702 for (i = 0; i < nxgep->param_count; i++) { 703 if ((param_arr[i].type & NXGE_PARAM_PRIV) && 704 (nxge_private_param_register(nxgep, 705 ¶m_arr[i]) == B_FALSE)) { 706 param_arr[i].setf = NULL; 707 param_arr[i].getf = NULL; 708 } 709 710 if (param_arr[i].type & NXGE_PARAM_CMPLX) 711 param_arr[i].setf = NULL; 712 713 if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 714 param_arr[i].setf = NULL; 715 param_arr[i].getf = NULL; 716 } 717 718 set_pfi = (pfi_t)param_arr[i].setf; 719 720 if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 721 set_pfi = NULL; 722 } 723 724 if (!nxge_nd_load(&nxgep->param_list, param_arr[i].name, 725 (pfi_t)param_arr[i].getf, set_pfi, 726 (caddr_t)¶m_arr[i])) { 727 (void) nxge_nd_free(&nxgep->param_list); 728 break; 729 } 730 } 731 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 732 } 733 734 void 735 nxge_init_param(p_nxge_t nxgep) 736 { 737 p_nxge_param_t param_arr; 738 int i, alloc_size; 739 uint64_t alloc_count; 740 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 741 /* 742 * Make sure the param_instance is set to a valid device instance. 743 */ 744 if (nxge_param_arr[param_instance].value == 1000) 745 nxge_param_arr[param_instance].value = nxgep->instance; 746 747 param_arr = nxgep->param_arr; 748 if (param_arr == NULL) { 749 param_arr = (p_nxge_param_t) 750 KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 751 } 752 753 for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 754 param_arr[i] = nxge_param_arr[i]; 755 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 756 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 757 alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 758 alloc_size = alloc_count * sizeof (uint64_t); 759 param_arr[i].value = 760 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 761 param_arr[i].old_value = 762 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 763 param_arr[i].type |= 764 (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 765 } 766 } 767 768 nxgep->param_arr = param_arr; 769 nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 770 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 771 nxgep->param_count)); 772 } 773 774 void 775 nxge_destroy_param(p_nxge_t nxgep) 776 { 777 int i; 778 uint64_t free_size, free_count; 779 780 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 781 782 if (nxgep->param_arr == NULL) 783 return; 784 /* 785 * Make sure the param_instance is set to a valid device instance. 786 */ 787 if (nxge_param_arr[param_instance].value == nxgep->instance) { 788 for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 789 if ((ddi_get_soft_state(nxge_list, i) != NULL) && 790 (i != nxgep->instance)) 791 break; 792 } 793 nxge_param_arr[param_instance].value = i; 794 } 795 796 if (nxgep->param_list) 797 nxge_nd_free(&nxgep->param_list); 798 for (i = 0; i < nxgep->param_count; i++) 799 if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 800 (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 801 free_count = ((nxgep->param_arr[i].type & 802 NXGE_PARAM_ARRAY_ALLOC_MASK) >> 803 NXGE_PARAM_ARRAY_ALLOC_SHIFT); 804 free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 805 free_size = sizeof (uint64_t) * free_count; 806 KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 807 KMEM_FREE((void *)nxgep->param_arr[i].old_value, 808 free_size); 809 } 810 811 KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 812 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 813 } 814 815 /* 816 * Extracts the value from the 'nxge' parameter array and prints the 817 * parameter value. cp points to the required parameter. 818 */ 819 820 /* ARGSUSED */ 821 int 822 nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 823 { 824 p_nxge_param_t pa = (p_nxge_param_t)cp; 825 826 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 827 "==> nxge_param_get_generic name %s ", pa->name)); 828 829 if (pa->value > 0xffffffff) 830 (void) mi_mpprintf(mp, "%x%x", 831 (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 832 else 833 (void) mi_mpprintf(mp, "%x", (int)pa->value); 834 835 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 836 return (0); 837 } 838 839 /* ARGSUSED */ 840 static int 841 nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 842 { 843 p_nxge_param_t pa = (p_nxge_param_t)cp; 844 845 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 846 847 (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 848 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 849 return (0); 850 } 851 852 /* ARGSUSED */ 853 static int 854 nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 855 { 856 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver")); 857 858 (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n", 859 nxgep->instance, nxgep->vpd_info.ver); 860 861 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver")); 862 return (0); 863 } 864 865 /* ARGSUSED */ 866 int 867 nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 868 { 869 870 uint_t print_len, buf_len; 871 p_mblk_t np; 872 int tdc; 873 874 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 875 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 876 877 (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 878 nxgep->function_num); 879 880 881 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 882 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 883 return (0); 884 } 885 886 buf_len = buff_alloc_size; 887 mp->b_cont = np; 888 889 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 890 "Total TDCs\t %d\n", nxgep->ntdc); 891 892 ((mblk_t *)np)->b_wptr += print_len; 893 buf_len -= print_len; 894 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 895 "TDC\t HW TDC\t\n"); 896 ((mblk_t *)np)->b_wptr += print_len; 897 898 buf_len -= print_len; 899 for (tdc = 0; tdc < nxgep->ntdc; tdc++) { 900 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 901 buf_len, "%d\t %d\n", 902 tdc, nxgep->tdc[tdc]); 903 ((mblk_t *)np)->b_wptr += print_len; 904 buf_len -= print_len; 905 } 906 907 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 908 return (0); 909 } 910 911 /* ARGSUSED */ 912 int 913 nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 914 { 915 uint_t print_len, buf_len; 916 p_mblk_t np; 917 int rdc; 918 p_nxge_dma_pt_cfg_t p_dma_cfgp; 919 p_nxge_hw_pt_cfg_t p_cfgp; 920 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 921 p_rx_rcr_rings_t rx_rcr_rings; 922 p_rx_rcr_ring_t *rcr_rings; 923 p_rx_rbr_rings_t rx_rbr_rings; 924 p_rx_rbr_ring_t *rbr_rings; 925 926 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 927 928 (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 929 nxgep->function_num); 930 931 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 932 /* The following may work even if we cannot get a large buf. */ 933 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 934 return (0); 935 } 936 937 buf_len = buff_alloc_size; 938 mp->b_cont = np; 939 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 940 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 941 942 rx_rcr_rings = nxgep->rx_rcr_rings; 943 rcr_rings = rx_rcr_rings->rcr_rings; 944 rx_rbr_rings = nxgep->rx_rbr_rings; 945 rbr_rings = rx_rbr_rings->rbr_rings; 946 947 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 948 "Total RDCs\t %d\n", p_cfgp->max_rdcs); 949 950 ((mblk_t *)np)->b_wptr += print_len; 951 buf_len -= print_len; 952 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 953 "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 954 "chunks\t RCR ptr\n"); 955 956 ((mblk_t *)np)->b_wptr += print_len; 957 buf_len -= print_len; 958 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 959 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 960 " %d\t %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 961 rdc, nxgep->rdc[rdc], 962 p_dma_cfgp->rcr_timeout[rdc], 963 p_dma_cfgp->rcr_threshold[rdc], 964 rbr_rings[rdc], 965 rbr_rings[rdc]->num_blocks, rcr_rings[rdc]); 966 ((mblk_t *)np)->b_wptr += print_len; 967 buf_len -= print_len; 968 } 969 970 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 971 return (0); 972 } 973 974 /* ARGSUSED */ 975 int 976 nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 977 p_mblk_t mp, caddr_t cp) 978 { 979 uint_t print_len, buf_len; 980 p_mblk_t np; 981 int offset, rdc, i, rdc_grp; 982 p_nxge_rdc_grp_t rdc_grp_p; 983 p_nxge_dma_pt_cfg_t p_dma_cfgp; 984 p_nxge_hw_pt_cfg_t p_cfgp; 985 986 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 987 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 988 "==> nxge_param_get_rxdma_rdcgrp_info")); 989 990 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 991 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 992 993 (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 994 nxgep->function_num); 995 996 rdc_grp = p_cfgp->start_rdc_grpid; 997 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 998 /* The following may work even if we cannot get a large buf. */ 999 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1000 return (0); 1001 } 1002 1003 buf_len = buff_alloc_size; 1004 mp->b_cont = np; 1005 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1006 "Total RDC Groups\t %d \n" 1007 "start RDC group\t %d\n", 1008 p_cfgp->max_rdc_grpids, 1009 p_cfgp->start_rdc_grpid); 1010 1011 ((mblk_t *)np)->b_wptr += print_len; 1012 buf_len -= print_len; 1013 1014 for (i = 0, rdc_grp = p_cfgp->start_rdc_grpid; 1015 rdc_grp < (p_cfgp->max_rdc_grpids + p_cfgp->start_rdc_grpid); 1016 rdc_grp++, i++) { 1017 rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 1018 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1019 "\nRDC Group Info for Group [%d] %d\n" 1020 "RDC Count %d\tstart RDC %d\n" 1021 "RDC Group Population Information" 1022 " (offsets 0 - 15)\n", 1023 i, rdc_grp, rdc_grp_p->max_rdcs, 1024 rdc_grp_p->start_rdc); 1025 1026 ((mblk_t *)np)->b_wptr += print_len; 1027 buf_len -= print_len; 1028 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1029 buf_len, "\n"); 1030 ((mblk_t *)np)->b_wptr += print_len; 1031 buf_len -= print_len; 1032 1033 for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 1034 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1035 buf_len, "[%d]=%d ", rdc, 1036 rdc_grp_p->start_rdc + rdc); 1037 ((mblk_t *)np)->b_wptr += print_len; 1038 buf_len -= print_len; 1039 } 1040 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1041 buf_len, "\n"); 1042 ((mblk_t *)np)->b_wptr += print_len; 1043 buf_len -= print_len; 1044 1045 for (offset = 0; offset < 16; offset++) { 1046 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1047 buf_len, " %2d ", 1048 rdc_grp_p->rdc[offset]); 1049 ((mblk_t *)np)->b_wptr += print_len; 1050 buf_len -= print_len; 1051 } 1052 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1053 buf_len, "\n"); 1054 ((mblk_t *)np)->b_wptr += print_len; 1055 buf_len -= print_len; 1056 } 1057 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1058 "<== nxge_param_get_rxdma_rdcgrp_info")); 1059 return (0); 1060 } 1061 1062 int 1063 nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 1064 { 1065 p_mblk_t tmp; 1066 1067 tmp = mp; 1068 while (tmp->b_cont) 1069 tmp = tmp->b_cont; 1070 if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 1071 tmp->b_cont = allocb(1024, BPRI_HI); 1072 tmp = tmp->b_cont; 1073 if (!tmp) 1074 return (ENOMEM); 1075 } 1076 1077 *nmp = tmp; 1078 return (0); 1079 } 1080 1081 /* 1082 * Sets the ge parameter to the value in the nxge_param_register using 1083 * nxge_nd_load(). 1084 */ 1085 1086 /* ARGSUSED */ 1087 int 1088 nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1089 char *value, caddr_t cp) 1090 { 1091 char *end; 1092 uint32_t new_value; 1093 p_nxge_param_t pa = (p_nxge_param_t)cp; 1094 1095 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 1096 new_value = (uint32_t)mi_strtol(value, &end, 10); 1097 if (end == value || new_value < pa->minimum || 1098 new_value > pa->maximum) { 1099 return (EINVAL); 1100 } 1101 pa->value = new_value; 1102 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 1103 return (0); 1104 } 1105 1106 /* 1107 * Sets the ge parameter to the value in the nxge_param_register using 1108 * nxge_nd_load(). 1109 */ 1110 1111 /* ARGSUSED */ 1112 int 1113 nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1114 char *value, caddr_t cp) 1115 { 1116 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 1117 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 1118 return (0); 1119 } 1120 1121 /* 1122 * Sets the ge parameter to the value in the nxge_param_register using 1123 * nxge_nd_load(). 1124 */ 1125 1126 /* ARGSUSED */ 1127 int 1128 nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1129 char *value, caddr_t cp) 1130 { 1131 char *end; 1132 uint32_t new_value; 1133 int status = 0; 1134 p_nxge_param_t pa = (p_nxge_param_t)cp; 1135 1136 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 1137 new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 1138 if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 1139 return (EINVAL); 1140 } 1141 1142 if (pa->value != new_value) { 1143 pa->old_value = pa->value; 1144 pa->value = new_value; 1145 } 1146 1147 if (!nxge_param_link_update(nxgep)) { 1148 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1149 " false ret from nxge_param_link_update")); 1150 status = EINVAL; 1151 } 1152 1153 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 1154 return (status); 1155 } 1156 1157 /* ARGSUSED */ 1158 static int 1159 nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1160 char *value, caddr_t cp) 1161 { 1162 char *end; 1163 uint32_t cfg_value; 1164 p_nxge_param_t pa = (p_nxge_param_t)cp; 1165 1166 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 1167 1168 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1169 1170 if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 1171 (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 1172 return (EINVAL); 1173 } 1174 1175 if ((pa->value != cfg_value)) { 1176 pa->old_value = pa->value; 1177 pa->value = cfg_value; 1178 nxgep->intr_threshold = pa->value; 1179 } 1180 1181 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 1182 return (0); 1183 } 1184 1185 /* ARGSUSED */ 1186 static int 1187 nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1188 char *value, caddr_t cp) 1189 { 1190 char *end; 1191 uint32_t cfg_value; 1192 p_nxge_param_t pa = (p_nxge_param_t)cp; 1193 1194 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 1195 1196 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1197 1198 if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 1199 (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 1200 return (EINVAL); 1201 } 1202 1203 if ((pa->value != cfg_value)) { 1204 pa->old_value = pa->value; 1205 pa->value = cfg_value; 1206 nxgep->intr_timeout = pa->value; 1207 } 1208 1209 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 1210 return (0); 1211 } 1212 1213 /* ARGSUSED */ 1214 static int 1215 nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1216 mblk_t *mp, char *value, caddr_t cp) 1217 { 1218 char *end; 1219 uint32_t status = 0, cfg_value; 1220 p_nxge_param_t pa = (p_nxge_param_t)cp; 1221 uint32_t cfg_it = B_FALSE; 1222 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1223 p_nxge_hw_pt_cfg_t p_cfgp; 1224 uint32_t *val_ptr, *old_val_ptr; 1225 nxge_param_map_t *mac_map; 1226 p_nxge_class_pt_cfg_t p_class_cfgp; 1227 nxge_mv_cfg_t *mac_host_info; 1228 1229 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 1230 1231 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1232 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1233 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1234 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1235 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1236 1237 /* 1238 * now do decoding 1239 */ 1240 mac_map = (nxge_param_map_t *)&cfg_value; 1241 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 1242 cfg_value, mac_map->param_id, mac_map->map_to)); 1243 1244 if ((mac_map->param_id < p_cfgp->max_macs) && 1245 (mac_map->map_to < (p_cfgp->max_rdc_grpids + 1246 p_cfgp->start_rdc_grpid)) && (mac_map->map_to >= 1247 p_cfgp->start_rdc_grpid)) { 1248 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1249 " nxge_param_set_mac_rdcgrp mapping" 1250 " id %d grp %d", mac_map->param_id, mac_map->map_to)); 1251 val_ptr = (uint32_t *)pa->value; 1252 old_val_ptr = (uint32_t *)pa->old_value; 1253 if (val_ptr[mac_map->param_id] != cfg_value) { 1254 old_val_ptr[mac_map->param_id] = 1255 val_ptr[mac_map->param_id]; 1256 val_ptr[mac_map->param_id] = cfg_value; 1257 mac_host_info[mac_map->param_id].mpr_npr = 1258 mac_map->pref; 1259 mac_host_info[mac_map->param_id].flag = 1; 1260 mac_host_info[mac_map->param_id].rdctbl = 1261 mac_map->map_to; 1262 cfg_it = B_TRUE; 1263 } 1264 } else { 1265 return (EINVAL); 1266 } 1267 1268 if (cfg_it == B_TRUE) { 1269 status = nxge_logical_mac_assign_rdc_table(nxgep, 1270 (uint8_t)mac_map->param_id); 1271 if (status != NXGE_OK) 1272 return (EINVAL); 1273 } 1274 1275 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 1276 return (0); 1277 } 1278 1279 /* ARGSUSED */ 1280 static int 1281 nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1282 mblk_t *mp, char *value, caddr_t cp) 1283 { 1284 char *end; 1285 uint32_t status = 0, cfg_value; 1286 p_nxge_param_t pa = (p_nxge_param_t)cp; 1287 uint32_t cfg_it = B_FALSE; 1288 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1289 p_nxge_hw_pt_cfg_t p_cfgp; 1290 uint32_t *val_ptr, *old_val_ptr; 1291 nxge_param_map_t *vmap, *old_map; 1292 p_nxge_class_pt_cfg_t p_class_cfgp; 1293 uint64_t cfgd_vlans; 1294 int i, inc = 0, cfg_position; 1295 nxge_mv_cfg_t *vlan_tbl; 1296 1297 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1298 1299 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1300 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1301 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1302 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1303 1304 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1305 1306 /* now do decoding */ 1307 cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1308 NXGE_PARAM_ARRAY_CNT_SHIFT); 1309 1310 if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 1311 /* 1312 * for now, we process only upto max 1313 * NXGE_PARAM_ARRAY_INIT_SIZE parameters 1314 * In the future, we may want to expand 1315 * the storage array and continue 1316 */ 1317 return (EINVAL); 1318 } 1319 1320 vmap = (nxge_param_map_t *)&cfg_value; 1321 if ((vmap->param_id) && 1322 (vmap->param_id < NXGE_MAX_VLANS) && 1323 (vmap->map_to < p_cfgp->max_rdc_grpids)) { 1324 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1325 "nxge_param_set_vlan_rdcgrp mapping" 1326 " id %d grp %d", 1327 vmap->param_id, vmap->map_to)); 1328 val_ptr = (uint32_t *)pa->value; 1329 old_val_ptr = (uint32_t *)pa->old_value; 1330 1331 /* search to see if this vlan id is already configured */ 1332 for (i = 0; i < cfgd_vlans; i++) { 1333 old_map = (nxge_param_map_t *)&val_ptr[i]; 1334 if ((old_map->param_id == 0) || 1335 (vmap->param_id == old_map->param_id) || 1336 (vlan_tbl[vmap->param_id].flag)) { 1337 cfg_position = i; 1338 break; 1339 } 1340 } 1341 1342 if (cfgd_vlans == 0) { 1343 cfg_position = 0; 1344 inc++; 1345 } 1346 1347 if (i == cfgd_vlans) { 1348 cfg_position = i; 1349 inc++; 1350 } 1351 1352 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1353 "set_vlan_rdcgrp mapping" 1354 " i %d cfgd_vlans %llx position %d ", 1355 i, cfgd_vlans, cfg_position)); 1356 if (val_ptr[cfg_position] != cfg_value) { 1357 old_val_ptr[cfg_position] = val_ptr[cfg_position]; 1358 val_ptr[cfg_position] = cfg_value; 1359 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 1360 vlan_tbl[vmap->param_id].flag = 1; 1361 vlan_tbl[vmap->param_id].rdctbl = 1362 vmap->map_to + p_cfgp->start_rdc_grpid; 1363 cfg_it = B_TRUE; 1364 if (inc) { 1365 cfgd_vlans++; 1366 pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 1367 pa->type |= (cfgd_vlans << 1368 NXGE_PARAM_ARRAY_CNT_SHIFT); 1369 1370 } 1371 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1372 "after: param_set_vlan_rdcgrp " 1373 " cfg_vlans %llx position %d \n", 1374 cfgd_vlans, cfg_position)); 1375 } 1376 } else { 1377 return (EINVAL); 1378 } 1379 1380 if (cfg_it == B_TRUE) { 1381 status = nxge_fflp_config_vlan_table(nxgep, 1382 (uint16_t)vmap->param_id); 1383 if (status != NXGE_OK) 1384 return (EINVAL); 1385 } 1386 1387 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 1388 return (0); 1389 } 1390 1391 /* ARGSUSED */ 1392 static int 1393 nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1394 mblk_t *mp, caddr_t cp) 1395 { 1396 1397 uint_t print_len, buf_len; 1398 p_mblk_t np; 1399 int i; 1400 uint32_t *val_ptr; 1401 nxge_param_map_t *vmap; 1402 p_nxge_param_t pa = (p_nxge_param_t)cp; 1403 p_nxge_class_pt_cfg_t p_class_cfgp; 1404 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1405 p_nxge_hw_pt_cfg_t p_cfgp; 1406 uint64_t cfgd_vlans = 0; 1407 nxge_mv_cfg_t *vlan_tbl; 1408 int buff_alloc_size = 1409 NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1410 1411 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1412 (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 1413 nxgep->function_num); 1414 1415 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1416 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1417 return (0); 1418 } 1419 1420 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1421 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1422 1423 buf_len = buff_alloc_size; 1424 mp->b_cont = np; 1425 cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1426 NXGE_PARAM_ARRAY_CNT_SHIFT; 1427 1428 i = (int)cfgd_vlans; 1429 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1430 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1431 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1432 "Configured VLANs %d\n" 1433 "VLAN ID\t RDC GRP (Actual/Port)\t" 1434 " Prefernce\n", i); 1435 ((mblk_t *)np)->b_wptr += print_len; 1436 buf_len -= print_len; 1437 1438 val_ptr = (uint32_t *)pa->value; 1439 1440 for (i = 0; i < cfgd_vlans; i++) { 1441 vmap = (nxge_param_map_t *)&val_ptr[i]; 1442 if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 1443 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1444 buf_len, 1445 " %d\t\t %d/%d\t\t %d\n", 1446 vmap->param_id, 1447 vlan_tbl[vmap->param_id].rdctbl, 1448 vlan_tbl[vmap->param_id].rdctbl - 1449 p_cfgp->start_rdc_grpid, 1450 vlan_tbl[vmap->param_id].mpr_npr); 1451 ((mblk_t *)np)->b_wptr += print_len; 1452 buf_len -= print_len; 1453 } 1454 } 1455 1456 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 1457 return (0); 1458 } 1459 1460 /* ARGSUSED */ 1461 static int 1462 nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1463 mblk_t *mp, caddr_t cp) 1464 { 1465 uint_t print_len, buf_len; 1466 p_mblk_t np; 1467 int i; 1468 p_nxge_class_pt_cfg_t p_class_cfgp; 1469 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1470 p_nxge_hw_pt_cfg_t p_cfgp; 1471 nxge_mv_cfg_t *mac_host_info; 1472 1473 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1474 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 1475 (void) mi_mpprintf(mp, 1476 "MAC ADDR RDC Mapping Information for Port\t %d\n", 1477 nxgep->function_num); 1478 1479 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1480 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1481 return (0); 1482 } 1483 1484 buf_len = buff_alloc_size; 1485 mp->b_cont = np; 1486 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1487 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1488 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1489 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1490 print_len = snprintf((char *)np->b_wptr, buf_len, 1491 "MAC ID\t RDC GRP (Actual/Port)\t" 1492 " Prefernce\n"); 1493 ((mblk_t *)np)->b_wptr += print_len; 1494 buf_len -= print_len; 1495 for (i = 0; i < p_cfgp->max_macs; i++) { 1496 if (mac_host_info[i].flag) { 1497 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1498 buf_len, 1499 " %d\t %d/%d\t\t %d\n", 1500 i, mac_host_info[i].rdctbl, 1501 mac_host_info[i].rdctbl - 1502 p_cfgp->start_rdc_grpid, 1503 mac_host_info[i].mpr_npr); 1504 ((mblk_t *)np)->b_wptr += print_len; 1505 buf_len -= print_len; 1506 } 1507 } 1508 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1509 "Done Info Dumping \n"); 1510 ((mblk_t *)np)->b_wptr += print_len; 1511 buf_len -= print_len; 1512 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 1513 return (0); 1514 } 1515 1516 /* ARGSUSED */ 1517 static int 1518 nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1519 mblk_t *mp, char *value, caddr_t cp) 1520 { 1521 uint32_t status = 0, cfg_value; 1522 p_nxge_param_t pa = (p_nxge_param_t)cp; 1523 uint32_t cfg_it = B_FALSE; 1524 char *end; 1525 1526 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 1527 1528 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1529 if (pa->value != cfg_value) { 1530 pa->old_value = pa->value; 1531 pa->value = cfg_value; 1532 cfg_it = B_TRUE; 1533 } 1534 1535 if (cfg_it == B_TRUE) { 1536 if (pa->value) 1537 status = nxge_fflp_config_tcam_enable(nxgep); 1538 else 1539 status = nxge_fflp_config_tcam_disable(nxgep); 1540 if (status != NXGE_OK) 1541 return (EINVAL); 1542 } 1543 1544 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 1545 return (0); 1546 } 1547 1548 /* ARGSUSED */ 1549 static int 1550 nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1551 mblk_t *mp, char *value, caddr_t cp) 1552 { 1553 uint32_t status = 0, cfg_value; 1554 p_nxge_param_t pa = (p_nxge_param_t)cp; 1555 uint32_t cfg_it = B_FALSE; 1556 char *end; 1557 1558 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 1559 1560 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1561 if (pa->value != cfg_value) { 1562 pa->old_value = pa->value; 1563 pa->value = cfg_value; 1564 cfg_it = B_TRUE; 1565 } 1566 1567 if (cfg_it == B_TRUE) { 1568 if (pa->value) 1569 status = nxge_fflp_config_hash_lookup_enable(nxgep); 1570 else 1571 status = nxge_fflp_config_hash_lookup_disable(nxgep); 1572 if (status != NXGE_OK) 1573 return (EINVAL); 1574 } 1575 1576 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 1577 return (0); 1578 } 1579 1580 /* ARGSUSED */ 1581 static int 1582 nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1583 mblk_t *mp, char *value, caddr_t cp) 1584 { 1585 char *end; 1586 uint32_t status = 0, cfg_value; 1587 p_nxge_param_t pa = (p_nxge_param_t)cp; 1588 uint32_t cfg_it = B_FALSE; 1589 1590 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 1591 1592 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1593 if (pa->value != cfg_value) { 1594 pa->old_value = pa->value; 1595 pa->value = cfg_value; 1596 cfg_it = B_TRUE; 1597 } 1598 1599 if (cfg_it == B_TRUE) { 1600 if (pa->value) 1601 status = nxge_fflp_config_tcam_enable(nxgep); 1602 else 1603 status = nxge_fflp_config_tcam_disable(nxgep); 1604 if (status != NXGE_OK) 1605 return (EINVAL); 1606 } 1607 1608 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 1609 return (0); 1610 } 1611 1612 /* ARGSUSED */ 1613 static int 1614 nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1615 mblk_t *mp, char *value, caddr_t cp) 1616 { 1617 char *end; 1618 uint8_t ether_class; 1619 uint32_t status = 0, cfg_value; 1620 p_nxge_param_t pa = (p_nxge_param_t)cp; 1621 uint8_t cfg_it = B_FALSE; 1622 1623 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 1624 1625 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1626 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1627 return (EINVAL); 1628 } 1629 1630 if (pa->value != cfg_value) { 1631 pa->old_value = pa->value; 1632 pa->value = cfg_value; 1633 cfg_it = B_TRUE; 1634 } 1635 1636 /* do the actual hw setup */ 1637 if (cfg_it == B_TRUE) { 1638 ether_class = mi_strtol(pa->name, &end, 10); 1639 #ifdef lint 1640 ether_class = ether_class; 1641 #endif 1642 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 1643 } 1644 1645 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 1646 return (status); 1647 } 1648 1649 /* ARGSUSED */ 1650 static int 1651 nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1652 mblk_t *mp, char *value, caddr_t cp) 1653 { 1654 char *end; 1655 tcam_class_t class; 1656 uint32_t status, cfg_value; 1657 p_nxge_param_t pa = (p_nxge_param_t)cp; 1658 uint32_t cfg_it = B_FALSE; 1659 1660 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 1661 1662 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1663 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1664 return (EINVAL); 1665 } 1666 1667 if (pa->value != cfg_value) { 1668 pa->old_value = pa->value; 1669 pa->value = cfg_value; 1670 cfg_it = B_TRUE; 1671 } 1672 1673 /* do the actual hw setup with cfg_value. */ 1674 if (cfg_it == B_TRUE) { 1675 class = mi_strtol(pa->name, &end, 10); 1676 status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 1677 } 1678 1679 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 1680 return (status); 1681 } 1682 1683 /* ARGSUSED */ 1684 static int 1685 nxge_class_name_2value(p_nxge_t nxgep, char *name) 1686 { 1687 int i; 1688 int class_instance = param_class_opt_ip_usr4; 1689 p_nxge_param_t param_arr; 1690 1691 param_arr = nxgep->param_arr; 1692 for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 1693 if (strcmp(param_arr[class_instance].name, name) == 0) 1694 return (i); 1695 class_instance++; 1696 } 1697 return (-1); 1698 } 1699 1700 /* ARGSUSED */ 1701 static int 1702 nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1703 mblk_t *mp, char *value, caddr_t cp) 1704 { 1705 char *end; 1706 uint32_t status, cfg_value; 1707 p_nxge_param_t pa = (p_nxge_param_t)cp; 1708 tcam_class_t class; 1709 uint32_t cfg_it = B_FALSE; 1710 1711 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 1712 1713 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1714 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1715 return (EINVAL); 1716 } 1717 1718 if (pa->value != cfg_value) { 1719 pa->old_value = pa->value; 1720 pa->value = cfg_value; 1721 cfg_it = B_TRUE; 1722 } 1723 1724 if (cfg_it == B_TRUE) { 1725 /* do the actual hw setup */ 1726 class = nxge_class_name_2value(nxgep, pa->name); 1727 if (class == -1) 1728 return (EINVAL); 1729 1730 status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 1731 if (status != NXGE_OK) 1732 return (EINVAL); 1733 } 1734 1735 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 1736 return (0); 1737 } 1738 1739 /* ARGSUSED */ 1740 static int 1741 nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1742 mblk_t *mp, caddr_t cp) 1743 { 1744 uint32_t status, cfg_value; 1745 p_nxge_param_t pa = (p_nxge_param_t)cp; 1746 tcam_class_t class; 1747 1748 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 1749 1750 /* do the actual hw setup */ 1751 class = nxge_class_name_2value(nxgep, pa->name); 1752 if (class == -1) 1753 return (EINVAL); 1754 1755 cfg_value = 0; 1756 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 1757 if (status != NXGE_OK) 1758 return (EINVAL); 1759 1760 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1761 "nxge_param_get_ip_opt_get %x ", cfg_value)); 1762 1763 pa->value = cfg_value; 1764 (void) mi_mpprintf(mp, "%x", cfg_value); 1765 1766 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 1767 return (0); 1768 } 1769 1770 /* ARGSUSED */ 1771 static int 1772 nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1773 mblk_t *mp, char *value, caddr_t cp) 1774 { 1775 char *end; 1776 uint32_t status, cfg_value; 1777 p_nxge_param_t pa = (p_nxge_param_t)cp; 1778 tcam_class_t class; 1779 uint32_t cfg_it = B_FALSE; 1780 1781 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 1782 1783 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1784 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1785 return (EINVAL); 1786 } 1787 1788 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1789 "nxge_param_fflp_hash_init value %x", cfg_value)); 1790 1791 if (pa->value != cfg_value) { 1792 pa->old_value = pa->value; 1793 pa->value = cfg_value; 1794 cfg_it = B_TRUE; 1795 } 1796 1797 if (cfg_it == B_TRUE) { 1798 char *h_name; 1799 1800 /* do the actual hw setup */ 1801 h_name = pa->name; 1802 h_name++; 1803 class = mi_strtol(h_name, &end, 10); 1804 switch (class) { 1805 case 1: 1806 status = nxge_fflp_set_hash1(nxgep, 1807 (uint32_t)pa->value); 1808 break; 1809 case 2: 1810 status = nxge_fflp_set_hash2(nxgep, 1811 (uint16_t)pa->value); 1812 break; 1813 1814 default: 1815 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1816 " nxge_param_fflp_hash_init" 1817 " %s Wrong hash var %d", 1818 pa->name, class)); 1819 return (EINVAL); 1820 } 1821 if (status != NXGE_OK) 1822 return (EINVAL); 1823 } 1824 1825 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 1826 return (0); 1827 } 1828 1829 /* ARGSUSED */ 1830 static int 1831 nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1832 mblk_t *mp, char *value, caddr_t cp) 1833 { 1834 char *end; 1835 uint32_t status = 0, cfg_value; 1836 p_nxge_param_t pa = (p_nxge_param_t)cp; 1837 uint32_t cfg_it = B_FALSE; 1838 int rdc_grp; 1839 uint8_t real_rdc; 1840 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1841 p_nxge_hw_pt_cfg_t p_cfgp; 1842 p_nxge_rdc_grp_t rdc_grp_p; 1843 1844 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1845 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1846 1847 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 1848 1849 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1850 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1851 return (EINVAL); 1852 } 1853 1854 if (cfg_value >= p_cfgp->max_rdcs) { 1855 return (EINVAL); 1856 } 1857 1858 if (pa->value != cfg_value) { 1859 pa->old_value = pa->value; 1860 pa->value = cfg_value; 1861 cfg_it = B_TRUE; 1862 } 1863 1864 if (cfg_it == B_TRUE) { 1865 char *grp_name; 1866 grp_name = pa->name; 1867 grp_name += strlen("default-grp"); 1868 rdc_grp = mi_strtol(grp_name, &end, 10); 1869 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 1870 real_rdc = rdc_grp_p->start_rdc + cfg_value; 1871 if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 1872 cfg_value) == B_FALSE) { 1873 pa->value = pa->old_value; 1874 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1875 " nxge_param_set_grp_rdc" 1876 " %d read %d actual %d outof range", 1877 rdc_grp, cfg_value, real_rdc)); 1878 return (EINVAL); 1879 } 1880 status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 1881 real_rdc); 1882 if (status != NXGE_OK) 1883 return (EINVAL); 1884 } 1885 1886 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 1887 return (0); 1888 } 1889 1890 /* ARGSUSED */ 1891 static int 1892 nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 1893 mblk_t *mp, char *value, caddr_t cp) 1894 { 1895 char *end; 1896 uint32_t status = B_TRUE, cfg_value; 1897 p_nxge_param_t pa = (p_nxge_param_t)cp; 1898 uint32_t cfg_it = B_FALSE; 1899 1900 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1901 p_nxge_hw_pt_cfg_t p_cfgp; 1902 1903 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 1904 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1905 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1906 1907 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1908 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1909 return (EINVAL); 1910 } 1911 1912 if (pa->value != cfg_value) { 1913 if (cfg_value >= p_cfgp->max_rdcs) 1914 return (EINVAL); 1915 pa->old_value = pa->value; 1916 pa->value = cfg_value; 1917 cfg_it = B_TRUE; 1918 } 1919 1920 if (cfg_it == B_TRUE) { 1921 status = nxge_rxdma_cfg_port_default_rdc(nxgep, 1922 nxgep->function_num, 1923 nxgep->rdc[cfg_value]); 1924 if (status != NXGE_OK) 1925 return (EINVAL); 1926 } 1927 1928 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 1929 return (0); 1930 } 1931 1932 /* ARGSUSED */ 1933 static int 1934 nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 1935 mblk_t *mp, char *value, caddr_t cp) 1936 { 1937 char *end; 1938 uint32_t status = 0; 1939 uint64_t cfg_value = 0; 1940 p_nxge_param_t pa = (p_nxge_param_t)cp; 1941 uint32_t cfg_it = B_FALSE; 1942 1943 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 1944 cfg_value = mi_strtol(value, &end, BASE_HEX); 1945 1946 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1947 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1948 " nxge_param_set_nxge_debug_flag" 1949 " outof range %llx", cfg_value)); 1950 return (EINVAL); 1951 } 1952 if (pa->value != cfg_value) { 1953 pa->old_value = pa->value; 1954 pa->value = cfg_value; 1955 cfg_it = B_TRUE; 1956 } 1957 1958 if (cfg_it == B_TRUE) { 1959 nxgep->nxge_debug_level = pa->value; 1960 } 1961 1962 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 1963 return (status); 1964 } 1965 1966 /* ARGSUSED */ 1967 static int 1968 nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 1969 { 1970 int status = 0; 1971 p_nxge_param_t pa = (p_nxge_param_t)cp; 1972 1973 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 1974 1975 if (pa->value > 0xffffffff) 1976 (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 1977 (int)(pa->value & 0xffffffff)); 1978 else 1979 (void) mi_mpprintf(mp, "%x", (int)pa->value); 1980 1981 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 1982 return (status); 1983 } 1984 1985 /* ARGSUSED */ 1986 static int 1987 nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 1988 mblk_t *mp, char *value, caddr_t cp) 1989 { 1990 char *end; 1991 uint32_t status = 0; 1992 uint64_t cfg_value = 0; 1993 p_nxge_param_t pa; 1994 uint32_t cfg_it = B_FALSE; 1995 1996 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 1997 cfg_value = mi_strtol(value, &end, BASE_HEX); 1998 pa = (p_nxge_param_t)cp; 1999 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2000 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 2001 " outof range %llx", cfg_value)); 2002 return (EINVAL); 2003 } 2004 if (pa->value != cfg_value) { 2005 pa->old_value = pa->value; 2006 pa->value = cfg_value; 2007 cfg_it = B_TRUE; 2008 } 2009 2010 if (cfg_it == B_TRUE) { 2011 npi_debug_level = pa->value; 2012 } 2013 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 2014 return (status); 2015 } 2016 2017 /* ARGSUSED */ 2018 static int 2019 nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2020 { 2021 uint_t rdc; 2022 2023 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 2024 2025 (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2026 for (rdc = 0; rdc < nxgep->nrdc; rdc++) 2027 (void) nxge_dump_rxdma_channel(nxgep, nxgep->rdc[rdc]); 2028 2029 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 2030 return (0); 2031 } 2032 2033 /* ARGSUSED */ 2034 static int 2035 nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2036 { 2037 uint_t tdc; 2038 2039 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 2040 2041 for (tdc = 0; tdc < nxgep->ntdc; tdc++) 2042 (void) nxge_txdma_regs_dump(nxgep, nxgep->tdc[tdc]); 2043 2044 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 2045 return (0); 2046 } 2047 2048 /* ARGSUSED */ 2049 static int 2050 nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2051 { 2052 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 2053 2054 (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2055 2056 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 2057 return (0); 2058 } 2059 2060 /* ARGSUSED */ 2061 static int 2062 nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2063 { 2064 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 2065 2066 (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2067 nxgep->function_num); 2068 2069 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 2070 return (0); 2071 } 2072 2073 /* ARGSUSED */ 2074 static int 2075 nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2076 { 2077 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 2078 2079 (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2080 nxgep->function_num); 2081 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 2082 return (0); 2083 } 2084 2085 /* ARGSUSED */ 2086 static int 2087 nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2088 { 2089 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 2090 2091 (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 2092 2093 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 2094 return (0); 2095 } 2096 2097 /* ARGSUSED */ 2098 static int 2099 nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2100 { 2101 uint8_t table; 2102 2103 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 2104 for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 2105 (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 2106 table); 2107 } 2108 2109 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 2110 return (0); 2111 } 2112 2113 typedef struct block_info { 2114 char *name; 2115 uint32_t offset; 2116 } block_info_t; 2117 2118 block_info_t reg_block[] = { 2119 {"PIO", PIO}, 2120 {"FZC_PIO", FZC_PIO}, 2121 {"FZC_XMAC", FZC_MAC}, 2122 {"FZC_IPP", FZC_IPP}, 2123 {"FFLP", FFLP}, 2124 {"FZC_FFLP", FZC_FFLP}, 2125 {"PIO_VADDR", PIO_VADDR}, 2126 {"ZCP", ZCP}, 2127 {"FZC_ZCP", FZC_ZCP}, 2128 {"DMC", DMC}, 2129 {"FZC_DMC", FZC_DMC}, 2130 {"TXC", TXC}, 2131 {"FZC_TXC", FZC_TXC}, 2132 {"PIO_LDSV", PIO_LDSV}, 2133 {"PIO_LDGIM", PIO_LDGIM}, 2134 {"PIO_IMASK0", PIO_IMASK0}, 2135 {"PIO_IMASK1", PIO_IMASK1}, 2136 {"FZC_PROM", FZC_PROM}, 2137 {"END", ALL_FF_32}, 2138 }; 2139 2140 /* ARGSUSED */ 2141 static int 2142 nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2143 { 2144 uint_t print_len, buf_len; 2145 p_mblk_t np; 2146 int rdc, tdc, block; 2147 uint64_t base; 2148 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2149 p_nxge_hw_pt_cfg_t p_cfgp; 2150 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 2151 p_tx_ring_t *tx_rings; 2152 p_rx_rcr_rings_t rx_rcr_rings; 2153 p_rx_rcr_ring_t *rcr_rings; 2154 p_rx_rbr_rings_t rx_rbr_rings; 2155 p_rx_rbr_ring_t *rbr_rings; 2156 2157 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2158 "==> nxge_param_dump_ptrs")); 2159 2160 (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 2161 nxgep->function_num); 2162 2163 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 2164 /* The following may work even if we cannot get a large buf. */ 2165 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 2166 return (0); 2167 } 2168 2169 buf_len = buff_alloc_size; 2170 mp->b_cont = np; 2171 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2172 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2173 2174 rx_rcr_rings = nxgep->rx_rcr_rings; 2175 rcr_rings = rx_rcr_rings->rcr_rings; 2176 rx_rbr_rings = nxgep->rx_rbr_rings; 2177 rbr_rings = rx_rbr_rings->rbr_rings; 2178 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2179 "nxgep (nxge_t) $%p\n" 2180 "dev_regs (dev_regs_t) $%p\n", 2181 nxgep, nxgep->dev_regs); 2182 2183 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2184 2185 /* do register pointers */ 2186 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2187 "reg base (npi_reg_ptr_t) $%p\t " 2188 "pci reg (npi_reg_ptr_t) $%p\n", 2189 nxgep->dev_regs->nxge_regp, 2190 nxgep->dev_regs->nxge_pciregp); 2191 2192 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2193 2194 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2195 "\nBlock \t Offset \n"); 2196 2197 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2198 block = 0; 2199 base = (uint64_t)nxgep->dev_regs->nxge_regp; 2200 while (reg_block[block].offset != ALL_FF_32) { 2201 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2202 "%9s\t 0x%llx\n", 2203 reg_block[block].name, 2204 (unsigned long long)(reg_block[block].offset + base)); 2205 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2206 block++; 2207 } 2208 2209 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2210 "\nRDC\t rcrp (rx_rcr_ring_t)\t " 2211 "rbrp (rx_rbr_ring_t)\n"); 2212 2213 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2214 2215 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 2216 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2217 " %d\t $%p\t\t $%p\n", 2218 rdc, rcr_rings[rdc], 2219 rbr_rings[rdc]); 2220 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2221 } 2222 2223 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2224 "\nTDC\t tdcp (tx_ring_t)\n"); 2225 2226 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2227 tx_rings = nxgep->tx_rings->rings; 2228 for (tdc = 0; tdc < p_cfgp->max_tdcs; tdc++) { 2229 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2230 " %d\t $%p\n", tdc, tx_rings[tdc]); 2231 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2232 } 2233 2234 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 2235 2236 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2237 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 2238 return (0); 2239 } 2240 2241 /* 2242 * Load 'name' into the named dispatch table pointed to by 'ndp'. 2243 * 'ndp' should be the address of a char pointer cell. If the table 2244 * does not exist (*ndp == 0), a new table is allocated and 'ndp' 2245 * is stuffed. If there is not enough space in the table for a new 2246 * entry, more space is allocated. 2247 */ 2248 /* ARGSUSED */ 2249 boolean_t 2250 nxge_nd_load(caddr_t *pparam, char *name, 2251 pfi_t get_pfi, pfi_t set_pfi, caddr_t data) 2252 { 2253 ND *nd; 2254 NDE *nde; 2255 2256 NXGE_DEBUG_MSG((NULL, NDD2_CTL, " ==> nxge_nd_load")); 2257 if (!pparam) 2258 return (B_FALSE); 2259 2260 if ((nd = (ND *)*pparam) == NULL) { 2261 if ((nd = (ND *)KMEM_ZALLOC(sizeof (ND), KM_NOSLEEP)) == NULL) 2262 return (B_FALSE); 2263 *pparam = (caddr_t)nd; 2264 } 2265 2266 if (nd->nd_tbl) { 2267 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2268 if (strcmp(name, nde->nde_name) == 0) 2269 goto fill_it; 2270 } 2271 } 2272 2273 if (nd->nd_free_count <= 1) { 2274 if ((nde = (NDE *)KMEM_ZALLOC(nd->nd_size + 2275 NDE_ALLOC_SIZE, KM_NOSLEEP)) == NULL) 2276 return (B_FALSE); 2277 nd->nd_free_count += NDE_ALLOC_COUNT; 2278 if (nd->nd_tbl) { 2279 bcopy((char *)nd->nd_tbl, (char *)nde, nd->nd_size); 2280 KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 2281 } else { 2282 nd->nd_free_count--; 2283 nde->nde_name = "?"; 2284 nde->nde_get_pfi = nxge_nd_get_names; 2285 nde->nde_set_pfi = nxge_set_default; 2286 } 2287 nde->nde_data = (caddr_t)nd; 2288 nd->nd_tbl = nde; 2289 nd->nd_size += NDE_ALLOC_SIZE; 2290 } 2291 for (nde = nd->nd_tbl; nde->nde_name; nde++) 2292 noop; 2293 nd->nd_free_count--; 2294 fill_it: 2295 nde->nde_name = name; 2296 nde->nde_get_pfi = get_pfi; 2297 nde->nde_set_pfi = set_pfi; 2298 nde->nde_data = data; 2299 NXGE_DEBUG_MSG((NULL, NDD2_CTL, " <== nxge_nd_load")); 2300 2301 return (B_TRUE); 2302 } 2303 2304 /* 2305 * Free the table pointed to by 'pparam' 2306 */ 2307 void 2308 nxge_nd_free(caddr_t *pparam) 2309 { 2310 ND *nd; 2311 2312 if ((nd = (ND *)*pparam) != NULL) { 2313 if (nd->nd_tbl) 2314 KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 2315 KMEM_FREE((char *)nd, sizeof (ND)); 2316 *pparam = nil(caddr_t); 2317 } 2318 } 2319 2320 int 2321 nxge_nd_getset(p_nxge_t nxgep, queue_t *q, caddr_t param, p_mblk_t mp) 2322 { 2323 int err; 2324 IOCP iocp; 2325 p_mblk_t mp1, mp2; 2326 ND *nd; 2327 NDE *nde; 2328 char *valp; 2329 size_t avail; 2330 2331 if (!param) { 2332 return (B_FALSE); 2333 } 2334 2335 nd = (ND *)param; 2336 iocp = (IOCP)mp->b_rptr; 2337 if ((iocp->ioc_count == 0) || !(mp1 = mp->b_cont)) { 2338 mp->b_datap->db_type = M_IOCACK; 2339 iocp->ioc_count = 0; 2340 iocp->ioc_error = EINVAL; 2341 return (B_FALSE); 2342 } 2343 2344 /* 2345 * NOTE - logic throughout nd_xxx assumes single data block for ioctl. 2346 * However, existing code sends in some big buffers. 2347 */ 2348 avail = iocp->ioc_count; 2349 if (mp1->b_cont) { 2350 freemsg(mp1->b_cont); 2351 mp1->b_cont = NULL; 2352 } 2353 2354 mp1->b_datap->db_lim[-1] = '\0'; /* Force null termination */ 2355 for (valp = (char *)mp1->b_rptr; *valp != '\0'; valp++) { 2356 if (*valp == '-') 2357 *valp = '_'; 2358 } 2359 2360 valp = (char *)mp1->b_rptr; 2361 2362 for (nde = nd->nd_tbl; /* */; nde++) { 2363 if (!nde->nde_name) 2364 return (B_FALSE); 2365 if (strcmp(nde->nde_name, valp) == 0) 2366 break; 2367 } 2368 err = EINVAL; 2369 while (*valp++) 2370 noop; 2371 if (!*valp || valp >= (char *)mp1->b_wptr) 2372 valp = nilp(char); 2373 switch (iocp->ioc_cmd) { 2374 case ND_GET: 2375 /* 2376 * (temporary) hack: "*valp" is size of user buffer for 2377 * copyout. If result of action routine is too big, free 2378 * excess and return ioc_rval as buffer size needed. 2379 * Return as many mblocks as will fit, free the rest. For 2380 * backward compatibility, assume size of original ioctl 2381 * buffer if "*valp" bad or not given. 2382 */ 2383 if (valp) 2384 avail = mi_strtol(valp, (char **)0, 10); 2385 /* 2386 * We overwrite the name/value with the reply data 2387 */ 2388 mp2 = mp1; 2389 while (mp2) { 2390 mp2->b_wptr = mp2->b_rptr; 2391 mp2 = mp2->b_cont; 2392 } 2393 2394 if (nde->nde_get_pfi) { 2395 err = (*nde->nde_get_pfi)(nxgep, q, mp1, nde->nde_data); 2396 } 2397 2398 if (!err) { 2399 size_t size_out = 0; 2400 ssize_t excess; 2401 2402 iocp->ioc_rval = 0; 2403 2404 /* Tack on the null */ 2405 err = nxge_mk_mblk_tail_space(mp1, &mp2, 1); 2406 if (!err) { 2407 *mp2->b_wptr++ = '\0'; 2408 size_out = msgdsize(mp1); 2409 excess = size_out - avail; 2410 if (excess > 0) { 2411 iocp->ioc_rval = (int)size_out; 2412 size_out -= excess; 2413 (void) adjmsg(mp1, -(excess + 1)); 2414 err = nxge_mk_mblk_tail_space( 2415 mp1, &mp2, 1); 2416 if (!err) 2417 *mp2->b_wptr++ = '\0'; 2418 else 2419 size_out = 0; 2420 } 2421 } else 2422 size_out = 0; 2423 iocp->ioc_count = size_out; 2424 } 2425 break; 2426 2427 case ND_SET: 2428 if (valp) { 2429 if (nde->nde_set_pfi) { 2430 err = (*nde->nde_set_pfi)(nxgep, q, mp1, valp, 2431 nde->nde_data); 2432 iocp->ioc_count = 0; 2433 freemsg(mp1); 2434 mp->b_cont = NULL; 2435 } 2436 } 2437 break; 2438 2439 default: 2440 break; 2441 } 2442 iocp->ioc_error = err; 2443 mp->b_datap->db_type = M_IOCACK; 2444 return (B_TRUE); 2445 } 2446 2447 /* ARGSUSED */ 2448 int 2449 nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 2450 { 2451 ND *nd; 2452 NDE *nde; 2453 char *rwtag; 2454 boolean_t get_ok, set_ok; 2455 size_t param_len; 2456 int status = 0; 2457 2458 nd = (ND *)param; 2459 if (!nd) 2460 return (ENOENT); 2461 2462 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2463 get_ok = (nde->nde_get_pfi != nxge_get_default) && 2464 (nde->nde_get_pfi != NULL); 2465 set_ok = (nde->nde_set_pfi != nxge_set_default) && 2466 (nde->nde_set_pfi != NULL); 2467 if (get_ok) { 2468 if (set_ok) 2469 rwtag = "read and write"; 2470 else 2471 rwtag = "read only"; 2472 } else if (set_ok) 2473 rwtag = "write only"; 2474 else { 2475 continue; 2476 } 2477 param_len = strlen(rwtag); 2478 param_len += strlen(nde->nde_name); 2479 param_len += 4; 2480 2481 (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 2482 } 2483 return (status); 2484 } 2485 2486 /* ARGSUSED */ 2487 int 2488 nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 2489 { 2490 return (EACCES); 2491 } 2492 2493 /* ARGSUSED */ 2494 int 2495 nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2496 caddr_t data) 2497 { 2498 return (EACCES); 2499 } 2500 2501 void 2502 nxge_param_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 2503 { 2504 int cmd; 2505 int status = B_FALSE; 2506 2507 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_ioctl")); 2508 cmd = iocp->ioc_cmd; 2509 2510 switch (cmd) { 2511 default: 2512 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2513 "nxge_param_ioctl: bad cmd 0x%0x", cmd)); 2514 break; 2515 2516 case ND_GET: 2517 case ND_SET: 2518 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2519 "nxge_param_ioctl: cmd 0x%0x", cmd)); 2520 if (!nxge_nd_getset(nxgep, wq, nxgep->param_list, mp)) { 2521 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2522 "false ret from nxge_nd_getset")); 2523 break; 2524 } 2525 status = B_TRUE; 2526 break; 2527 } 2528 2529 if (status) { 2530 qreply(wq, mp); 2531 } else { 2532 miocnak(wq, mp, 0, EINVAL); 2533 } 2534 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_ioctl")); 2535 } 2536 2537 /* ARGSUSED */ 2538 static boolean_t 2539 nxge_param_link_update(p_nxge_t nxgep) 2540 { 2541 p_nxge_param_t param_arr; 2542 nxge_param_index_t i; 2543 boolean_t update_xcvr; 2544 boolean_t update_dev; 2545 int instance; 2546 boolean_t status = B_TRUE; 2547 2548 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_link_update")); 2549 2550 param_arr = nxgep->param_arr; 2551 instance = nxgep->instance; 2552 update_xcvr = B_FALSE; 2553 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 2554 update_xcvr |= param_arr[i].value; 2555 } 2556 2557 if (update_xcvr) { 2558 update_xcvr = B_FALSE; 2559 for (i = param_autoneg; i < param_enable_ipg0; i++) { 2560 update_xcvr |= 2561 (param_arr[i].value != param_arr[i].old_value); 2562 param_arr[i].old_value = param_arr[i].value; 2563 } 2564 if (update_xcvr) { 2565 RW_ENTER_WRITER(&nxgep->filter_lock); 2566 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 2567 (void) nxge_link_init(nxgep); 2568 (void) nxge_mac_init(nxgep); 2569 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 2570 RW_EXIT(&nxgep->filter_lock); 2571 } 2572 } else { 2573 cmn_err(CE_WARN, " Last setting will leave nxge%d with " 2574 " no link capabilities.", instance); 2575 cmn_err(CE_WARN, " Restoring previous setting."); 2576 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 2577 param_arr[i].value = param_arr[i].old_value; 2578 } 2579 2580 update_dev = B_FALSE; 2581 2582 if (update_dev) { 2583 RW_ENTER_WRITER(&nxgep->filter_lock); 2584 (void) nxge_rx_mac_disable(nxgep); 2585 (void) nxge_tx_mac_disable(nxgep); 2586 (void) nxge_tx_mac_enable(nxgep); 2587 (void) nxge_rx_mac_enable(nxgep); 2588 RW_EXIT(&nxgep->filter_lock); 2589 } 2590 2591 nxge_param_hw_update_exit: 2592 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2593 "<== nxge_param_link_update status = 0x%08x", status)); 2594 return (status); 2595 } 2596