1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/nxge/nxge_impl.h> 27 #include <sys/nxge/nxge_hio.h> 28 29 #include <inet/common.h> 30 #include <inet/mi.h> 31 #include <inet/nd.h> 32 33 extern uint64_t npi_debug_level; 34 35 #define NXGE_PARAM_MAC_RW \ 36 NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 37 NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 38 39 #define NXGE_PARAM_MAC_DONT_SHOW \ 40 NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 41 42 #define NXGE_PARAM_RXDMA_RW \ 43 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 44 NXGE_PARAM_READ_PROP 45 46 #define NXGE_PARAM_RXDMA_RWC \ 47 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 48 NXGE_PARAM_READ_PROP 49 50 #define NXGE_PARAM_L2CLASS_CFG \ 51 NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 52 NXGE_PARAM_NDD_WR_OK 53 54 #define NXGE_PARAM_CLASS_RWS \ 55 NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 56 57 #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 58 59 #define SET_RX_INTR_TIME_DISABLE 0 60 #define SET_RX_INTR_TIME_ENABLE 1 61 #define SET_RX_INTR_PKTS 2 62 63 #define BASE_ANY 0 64 #define BASE_BINARY 2 65 #define BASE_HEX 16 66 #define BASE_DECIMAL 10 67 #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 68 #define ALL_FF_32 0xFFFFFFFFUL 69 70 #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 71 #define NXGE_NDD_INFODUMP_BUFF_8K 8192 72 #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 73 #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 74 75 #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 76 ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 77 78 #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 79 ((mblk_t *)pmp)->b_wptr += plen; \ 80 rlen -= plen; \ 81 } 82 83 int nxge_param_set_mac(p_nxge_t, queue_t *, 84 mblk_t *, char *, caddr_t); 85 static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 86 mblk_t *, char *, caddr_t); 87 static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 88 mblk_t *, char *, caddr_t); 89 static int nxge_param_set_ether_usr(p_nxge_t, 90 queue_t *, mblk_t *, char *, caddr_t); 91 static int nxge_param_set_ip_usr(p_nxge_t, 92 queue_t *, mblk_t *, char *, caddr_t); 93 static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 94 queue_t *, mblk_t *, char *, caddr_t); 95 static int nxge_param_set_mac_rdcgrp(p_nxge_t, 96 queue_t *, mblk_t *, char *, caddr_t); 97 static int nxge_param_fflp_hash_init(p_nxge_t, 98 queue_t *, mblk_t *, char *, caddr_t); 99 static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 100 mblk_t *, char *, caddr_t); 101 static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 102 mblk_t *, char *, caddr_t); 103 static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 104 mblk_t *, char *, caddr_t); 105 static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 106 static int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 107 static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 108 p_mblk_t, caddr_t); 109 static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 110 p_mblk_t, caddr_t); 111 static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 112 p_mblk_t, caddr_t); 113 static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 114 p_mblk_t, caddr_t); 115 static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 116 p_mblk_t, caddr_t); 117 static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 118 static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 119 static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 120 static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 121 char *, caddr_t); 122 static int nxge_param_set_npi_debug_flag(p_nxge_t, 123 queue_t *, mblk_t *, char *, caddr_t); 124 static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 125 static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 126 static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 127 static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 128 static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 129 static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 130 static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 131 static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 132 static void nxge_param_sync(p_nxge_t); 133 134 /* 135 * Global array of Neptune changable parameters. 136 * This array is initialized to correspond to the default 137 * Neptune 4 port configuration. This array would be copied 138 * into each port's parameter structure and modifed per 139 * fcode and nxge.conf configuration. Later, the parameters are 140 * exported to ndd to display and run-time configuration (at least 141 * some of them). 142 * 143 * Parameters with DONT_SHOW are not shown by ndd. 144 * 145 */ 146 147 static nxge_param_t nxge_param_arr[] = { 148 /* 149 * min max value old hw-name conf-name 150 */ 151 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 152 0, 999, 1000, 0, "instance", "instance"}, 153 154 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 155 0, 999, 1000, 0, "main-instance", "main_instance"}, 156 157 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 158 0, 3, 0, 0, "function-number", "function_number"}, 159 160 /* Partition Id */ 161 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 162 0, 8, 0, 0, "partition-id", "partition_id"}, 163 164 /* Read Write Permission Mode */ 165 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 166 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 167 168 { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ, 169 0, 32, 0, 0, "version", "fw_version"}, 170 171 { nxge_param_get_port_mode, NULL, NXGE_PARAM_READ, 172 0, 32, 0, 0, "port-mode", "port_mode"}, 173 174 /* hw cfg types */ 175 /* control the DMA config of Neptune/NIU */ 176 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 177 CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 178 "niu-cfg-type", "niu_cfg_type"}, 179 180 /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 181 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 182 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 183 "tx-qcfg-type", "tx_qcfg_type"}, 184 185 /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 186 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 187 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 188 "rx-qcfg-type", "rx_qcfg_type"}, 189 190 { nxge_param_get_mac, nxge_param_set_mac, 191 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 192 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 193 194 { nxge_param_get_mac, nxge_param_set_mac, 195 NXGE_PARAM_DONT_SHOW, 196 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 197 198 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 199 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 200 201 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 202 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 203 204 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 205 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 206 207 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 208 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 209 210 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 211 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 212 213 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 214 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 215 216 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 217 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 218 219 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 220 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 221 222 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 223 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 224 225 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 226 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 227 228 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 229 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 230 231 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 232 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 233 234 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 235 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 236 237 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 238 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 239 240 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 241 0, 255, 8, 8, "ipg0", "ipg0"}, 242 243 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 244 0, 255, 8, 8, "ipg1", "ipg1"}, 245 246 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 247 0, 255, 4, 4, "ipg2", "ipg2"}, 248 249 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 250 0, 1, 0, 0, "accept-jumbo", "accept_jumbo"}, 251 252 /* Transmit DMA channels */ 253 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 254 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 255 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 256 257 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 258 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 259 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 260 261 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 262 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 263 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 264 { nxge_param_get_txdma_info, NULL, 265 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 266 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 267 268 /* Receive DMA channels */ 269 { nxge_param_get_generic, NULL, 270 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 271 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 272 273 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 274 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 275 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 276 277 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 278 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 279 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 280 "rx-drr-weight", "rx_drr_weight"}, 281 282 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 283 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 284 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 285 286 { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ | 287 NXGE_PARAM_DONT_SHOW, 288 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 289 290 { nxge_param_get_rxdma_info, NULL, 291 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 292 NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 293 "rx-rbr-size", "rx_rbr_size"}, 294 295 { nxge_param_get_rxdma_info, NULL, 296 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 297 NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 298 "rx-rcr-size", "rx_rcr_size"}, 299 300 { nxge_param_get_generic, nxge_param_set_port_rdc, 301 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 302 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 303 304 { nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW, 305 NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 306 NXGE_RDC_RCR_TIMEOUT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 307 308 { nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW, 309 NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 310 NXGE_RDC_RCR_THRESHOLD, 0, 311 "rxdma-intr-pkts", "rxdma_intr_pkts"}, 312 313 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 314 NXGE_PARAM_DONT_SHOW, 315 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 316 317 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 318 NXGE_PARAM_DONT_SHOW, 319 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 320 321 { nxge_param_get_generic, nxge_param_set_grp_rdc, 322 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 323 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 324 325 { nxge_param_get_generic, nxge_param_set_grp_rdc, 326 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 327 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 328 329 { nxge_param_get_generic, nxge_param_set_grp_rdc, 330 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 331 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 332 333 { nxge_param_get_generic, nxge_param_set_grp_rdc, 334 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 335 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 336 337 { nxge_param_get_generic, nxge_param_set_grp_rdc, 338 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 339 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 340 341 { nxge_param_get_generic, nxge_param_set_grp_rdc, 342 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 343 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 344 345 { nxge_param_get_generic, nxge_param_set_grp_rdc, 346 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 347 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 348 349 { nxge_param_get_generic, nxge_param_set_grp_rdc, 350 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 351 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 352 353 { nxge_param_get_rxdma_rdcgrp_info, NULL, 354 NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW, 355 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 356 357 /* Logical device groups */ 358 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 359 0, 63, 0, 0, "start-ldg", "start_ldg"}, 360 361 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 362 0, 64, 0, 0, "max-ldg", "max_ldg" }, 363 364 /* MAC table information */ 365 { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 366 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 367 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 368 369 /* VLAN table information */ 370 { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 371 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 372 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 373 374 { nxge_param_get_generic, NULL, 375 NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | 376 NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW, 377 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 378 379 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 380 NXGE_PARAM_DONT_SHOW, 381 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 382 383 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 384 NXGE_PARAM_DONT_SHOW, 385 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 386 387 { nxge_param_get_generic, nxge_param_tcam_enable, 388 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 389 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 390 391 { nxge_param_get_generic, nxge_param_hash_lookup_enable, 392 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 393 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 394 395 { nxge_param_get_generic, nxge_param_llc_snap_enable, 396 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 397 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 398 399 { nxge_param_get_generic, nxge_param_fflp_hash_init, 400 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 401 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 402 403 { nxge_param_get_generic, nxge_param_fflp_hash_init, 404 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 405 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 406 407 { nxge_param_get_generic, nxge_param_set_ether_usr, 408 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 409 0, ALL_FF_32, 0x0, 0, 410 "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 411 412 { nxge_param_get_generic, nxge_param_set_ether_usr, 413 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 414 0, ALL_FF_32, 0x0, 0, 415 "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 416 417 { nxge_param_get_generic, nxge_param_set_ip_usr, 418 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 419 0, ALL_FF_32, 0x0, 0, 420 "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 421 422 { nxge_param_get_generic, nxge_param_set_ip_usr, 423 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 424 0, ALL_FF_32, 0x0, 0, 425 "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 426 427 { nxge_param_get_generic, nxge_param_set_ip_usr, 428 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 429 0, ALL_FF_32, 0x0, 0, 430 "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 431 432 { nxge_param_get_generic, nxge_param_set_ip_usr, 433 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 434 0, ALL_FF_32, 0x0, 0, 435 "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 436 437 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 438 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 439 0, ALL_FF_32, 0x0, 0, 440 "class-opt-ip-usr4", "class_opt_ip_usr4"}, 441 442 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 443 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 444 0, ALL_FF_32, 0x0, 0, 445 "class-opt-ip-usr5", "class_opt_ip_usr5"}, 446 447 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 448 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 449 0, ALL_FF_32, 0x0, 0, 450 "class-opt-ip-usr6", "class_opt_ip_usr6"}, 451 452 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 453 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 454 0, ALL_FF_32, 0x0, 0, 455 "class-opt-ip-usr7", "class_opt_ip_usr7"}, 456 457 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 458 NXGE_PARAM_CLASS_RWS, 459 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 460 "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 461 462 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 463 NXGE_PARAM_CLASS_RWS, 464 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 465 "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 466 467 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 468 NXGE_PARAM_CLASS_RWS, 469 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 470 "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 471 472 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 473 NXGE_PARAM_CLASS_RWS, 474 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 475 "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 476 477 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 478 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 479 "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 480 481 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 482 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 483 "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 484 485 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 486 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 487 "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 488 489 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 490 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 491 "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 492 493 { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 494 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 495 0ULL, ALL_FF_64, 0ULL, 0ULL, 496 "nxge-debug-flag", "nxge_debug_flag"}, 497 498 { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 499 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 500 0ULL, ALL_FF_64, 0ULL, 0ULL, 501 "npi-debug-flag", "npi_debug_flag"}, 502 503 { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 504 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 505 506 { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 507 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 508 509 { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ | 510 NXGE_PARAM_DONT_SHOW, 511 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 512 513 { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ | 514 NXGE_PARAM_DONT_SHOW, 515 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 516 517 { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ | 518 NXGE_PARAM_DONT_SHOW, 519 0, 0x0fffffff, 0x0fffffff, 0, 520 "dump-fflp-regs", "dump_fflp_regs"}, 521 522 { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ | 523 NXGE_PARAM_DONT_SHOW, 524 0, 0x0fffffff, 0x0fffffff, 0, 525 "dump-vlan-table", "dump_vlan_table"}, 526 527 { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ | 528 NXGE_PARAM_DONT_SHOW, 529 0, 0x0fffffff, 0x0fffffff, 0, 530 "dump-rdc-table", "dump_rdc_table"}, 531 532 { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ | 533 NXGE_PARAM_DONT_SHOW, 534 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 535 536 { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 537 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 538 }; 539 540 extern void *nxge_list; 541 542 void 543 nxge_get_param_soft_properties(p_nxge_t nxgep) 544 { 545 546 p_nxge_param_t param_arr; 547 uint_t prop_len; 548 int i, j; 549 uint32_t param_count; 550 uint32_t *int_prop_val; 551 552 NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 553 554 param_arr = nxgep->param_arr; 555 param_count = nxgep->param_count; 556 for (i = 0; i < param_count; i++) { 557 if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 558 continue; 559 if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 560 continue; 561 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 562 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 563 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 564 nxgep->dip, 0, param_arr[i].fcode_name, 565 (int **)&int_prop_val, 566 (uint_t *)&prop_len) 567 == DDI_PROP_SUCCESS) { 568 uint32_t *cfg_value; 569 uint64_t prop_count; 570 571 if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 572 prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 573 #if defined(__i386) 574 cfg_value = 575 (uint32_t *)(int32_t)param_arr[i].value; 576 #else 577 cfg_value = (uint32_t *)param_arr[i].value; 578 #endif 579 for (j = 0; j < prop_len; j++) { 580 cfg_value[j] = int_prop_val[j]; 581 } 582 prop_count = prop_len; 583 param_arr[i].type |= 584 (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 585 ddi_prop_free(int_prop_val); 586 } 587 continue; 588 } 589 590 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 591 param_arr[i].fcode_name, 592 (int **)&int_prop_val, 593 &prop_len) == DDI_PROP_SUCCESS) { 594 if ((*int_prop_val >= param_arr[i].minimum) && 595 (*int_prop_val <= param_arr[i].maximum)) 596 param_arr[i].value = *int_prop_val; 597 #ifdef NXGE_DEBUG_ERROR 598 else { 599 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 600 "nxge%d: 'prom' file parameter error\n", 601 nxgep->instance)); 602 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 603 "Parameter keyword '%s'" 604 " is outside valid range\n", 605 param_arr[i].name)); 606 } 607 #endif 608 ddi_prop_free(int_prop_val); 609 } 610 611 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 612 param_arr[i].name, 613 (int **)&int_prop_val, 614 &prop_len) == DDI_PROP_SUCCESS) { 615 if ((*int_prop_val >= param_arr[i].minimum) && 616 (*int_prop_val <= param_arr[i].maximum)) 617 param_arr[i].value = *int_prop_val; 618 #ifdef NXGE_DEBUG_ERROR 619 else { 620 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 621 "nxge%d: 'conf' file parameter error\n", 622 nxgep->instance)); 623 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 624 "Parameter keyword '%s'" 625 "is outside valid range\n", 626 param_arr[i].name)); 627 } 628 #endif 629 ddi_prop_free(int_prop_val); 630 } 631 } 632 } 633 634 static int 635 nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 636 { 637 int status = B_TRUE; 638 int channel; 639 uint8_t grp; 640 char *prop_name; 641 char *end; 642 uint32_t name_chars; 643 644 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 645 "nxge_private_param_register %s", param_arr->name)); 646 647 if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 648 return (B_TRUE); 649 650 prop_name = param_arr->name; 651 if (param_arr->type & NXGE_PARAM_RXDMA) { 652 if (strncmp("rxdma_intr", prop_name, 10) == 0) 653 return (B_TRUE); 654 name_chars = strlen("default_grp"); 655 if (strncmp("default_grp", prop_name, name_chars) == 0) { 656 prop_name += name_chars; 657 grp = mi_strtol(prop_name, &end, 10); 658 /* now check if this rdcgrp is in config */ 659 return (nxge_check_rdcgrp_port_member(nxgep, grp)); 660 } 661 name_chars = strlen(prop_name); 662 if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 663 return (B_TRUE); 664 } 665 return (B_FALSE); 666 } 667 668 if (param_arr->type & NXGE_PARAM_TXDMA) { 669 name_chars = strlen("txdma"); 670 if (strncmp("txdma", prop_name, name_chars) == 0) { 671 prop_name += name_chars; 672 channel = mi_strtol(prop_name, &end, 10); 673 /* now check if this rdc is in config */ 674 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 675 " nxge_private_param_register: %d", 676 channel)); 677 return (nxge_check_txdma_port_member(nxgep, channel)); 678 } 679 return (B_FALSE); 680 } 681 682 status = B_FALSE; 683 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 684 685 return (status); 686 } 687 688 void 689 nxge_setup_param(p_nxge_t nxgep) 690 { 691 p_nxge_param_t param_arr; 692 int i; 693 pfi_t set_pfi; 694 695 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 696 697 /* 698 * Make sure the param_instance is set to a valid device instance. 699 */ 700 if (nxge_param_arr[param_instance].value == 1000) 701 nxge_param_arr[param_instance].value = nxgep->instance; 702 703 param_arr = nxgep->param_arr; 704 param_arr[param_instance].value = nxgep->instance; 705 param_arr[param_function_number].value = nxgep->function_num; 706 707 for (i = 0; i < nxgep->param_count; i++) { 708 if ((param_arr[i].type & NXGE_PARAM_PRIV) && 709 (nxge_private_param_register(nxgep, 710 ¶m_arr[i]) == B_FALSE)) { 711 param_arr[i].setf = NULL; 712 param_arr[i].getf = NULL; 713 } 714 715 if (param_arr[i].type & NXGE_PARAM_CMPLX) 716 param_arr[i].setf = NULL; 717 718 if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 719 param_arr[i].setf = NULL; 720 param_arr[i].getf = NULL; 721 } 722 723 set_pfi = (pfi_t)param_arr[i].setf; 724 725 if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 726 set_pfi = NULL; 727 } 728 729 } 730 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 731 } 732 733 void 734 nxge_init_param(p_nxge_t nxgep) 735 { 736 p_nxge_param_t param_arr; 737 int i, alloc_size; 738 uint64_t alloc_count; 739 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 740 /* 741 * Make sure the param_instance is set to a valid device instance. 742 */ 743 if (nxge_param_arr[param_instance].value == 1000) 744 nxge_param_arr[param_instance].value = nxgep->instance; 745 746 param_arr = nxgep->param_arr; 747 if (param_arr == NULL) { 748 param_arr = (p_nxge_param_t) 749 KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 750 } 751 752 for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 753 param_arr[i] = nxge_param_arr[i]; 754 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 755 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 756 alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 757 alloc_size = alloc_count * sizeof (uint64_t); 758 param_arr[i].value = 759 #if defined(__i386) 760 (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 761 KM_SLEEP); 762 #else 763 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 764 #endif 765 param_arr[i].old_value = 766 #if defined(__i386) 767 (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 768 KM_SLEEP); 769 #else 770 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 771 #endif 772 param_arr[i].type |= 773 (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 774 } 775 } 776 777 nxgep->param_arr = param_arr; 778 nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 779 780 nxge_param_sync(nxgep); 781 782 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 783 nxgep->param_count)); 784 } 785 786 void 787 nxge_destroy_param(p_nxge_t nxgep) 788 { 789 int i; 790 uint64_t free_size, free_count; 791 792 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 793 794 if (nxgep->param_arr == NULL) 795 return; 796 /* 797 * Make sure the param_instance is set to a valid device instance. 798 */ 799 if (nxge_param_arr[param_instance].value == nxgep->instance) { 800 for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 801 if ((ddi_get_soft_state(nxge_list, i) != NULL) && 802 (i != nxgep->instance)) 803 break; 804 } 805 nxge_param_arr[param_instance].value = i; 806 } 807 808 for (i = 0; i < nxgep->param_count; i++) 809 if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 810 (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 811 free_count = ((nxgep->param_arr[i].type & 812 NXGE_PARAM_ARRAY_ALLOC_MASK) >> 813 NXGE_PARAM_ARRAY_ALLOC_SHIFT); 814 free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 815 free_size = sizeof (uint64_t) * free_count; 816 #if defined(__i386) 817 KMEM_FREE((void *)(uint32_t)nxgep->param_arr[i].value, 818 free_size); 819 #else 820 KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 821 #endif 822 #if defined(__i386) 823 KMEM_FREE((void *)(uint32_t) 824 nxgep->param_arr[i].old_value, free_size); 825 #else 826 KMEM_FREE((void *)nxgep->param_arr[i].old_value, 827 free_size); 828 #endif 829 } 830 831 KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 832 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 833 } 834 835 /* 836 * Extracts the value from the 'nxge' parameter array and prints the 837 * parameter value. cp points to the required parameter. 838 */ 839 840 /* ARGSUSED */ 841 int 842 nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 843 { 844 p_nxge_param_t pa = (p_nxge_param_t)cp; 845 846 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 847 "==> nxge_param_get_generic name %s ", pa->name)); 848 849 if (pa->value > 0xffffffff) 850 (void) mi_mpprintf(mp, "%x%x", 851 (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 852 else 853 (void) mi_mpprintf(mp, "%x", (int)pa->value); 854 855 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 856 return (0); 857 } 858 859 /* ARGSUSED */ 860 static int 861 nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 862 { 863 p_nxge_param_t pa = (p_nxge_param_t)cp; 864 865 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 866 867 (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 868 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 869 return (0); 870 } 871 872 /* ARGSUSED */ 873 static int 874 nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 875 { 876 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver")); 877 878 (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n", 879 nxgep->instance, nxgep->vpd_info.ver); 880 881 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver")); 882 return (0); 883 } 884 885 /* ARGSUSED */ 886 static int 887 nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 888 { 889 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode")); 890 891 switch (nxgep->mac.portmode) { 892 case PORT_1G_COPPER: 893 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Copper %s\n", 894 nxgep->instance, 895 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 896 break; 897 case PORT_1G_FIBER: 898 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Fiber %s\n", 899 nxgep->instance, 900 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 901 break; 902 case PORT_10G_COPPER: 903 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Copper " 904 "%s\n", nxgep->instance, 905 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 906 break; 907 case PORT_10G_FIBER: 908 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Fiber %s\n", 909 nxgep->instance, 910 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 911 break; 912 case PORT_10G_SERDES: 913 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Serdes " 914 "%s\n", nxgep->instance, 915 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 916 break; 917 case PORT_1G_SERDES: 918 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Serdes %s\n", 919 nxgep->instance, 920 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 921 break; 922 case PORT_1G_RGMII_FIBER: 923 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G RGMII " 924 "Fiber %s\n", nxgep->instance, 925 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 926 break; 927 case PORT_HSP_MODE: 928 (void) mi_mpprintf(mp, "Port mode for nxge%d: Hot Swappable " 929 "PHY, Currently NOT present\n", nxgep->instance); 930 break; 931 case PORT_10G_TN1010: 932 (void) mi_mpprintf(mp, "Port mode for nxge%d:" 933 " 10G Copper with TN1010 %s\n", nxgep->instance, 934 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 935 break; 936 case PORT_1G_TN1010: 937 (void) mi_mpprintf(mp, "Port mode for nxge%d:" 938 " 1G Copper with TN1010 %s\n", nxgep->instance, 939 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 940 break; 941 default: 942 (void) mi_mpprintf(mp, "Port mode for nxge%d: Unknown %s\n", 943 nxgep->instance, 944 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 945 break; 946 } 947 948 (void) mi_mpprintf(mp, "Software LSO for nxge%d: %s\n", 949 nxgep->instance, 950 nxgep->soft_lso_enable ? "enable" : "disable"); 951 952 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode")); 953 return (0); 954 } 955 956 /* ARGSUSED */ 957 int 958 nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 959 { 960 961 uint_t print_len, buf_len; 962 p_mblk_t np; 963 964 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 965 int tdc; 966 967 nxge_grp_set_t *set; 968 969 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 970 971 (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 972 nxgep->function_num); 973 974 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 975 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 976 return (0); 977 } 978 979 buf_len = buff_alloc_size; 980 mp->b_cont = np; 981 print_len = 0; 982 983 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 984 "TDC\t HW TDC\t\n"); 985 ((mblk_t *)np)->b_wptr += print_len; 986 buf_len -= print_len; 987 988 set = &nxgep->tx_set; 989 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { 990 if ((1 << tdc) & set->owned.map) { 991 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 992 buf_len, "%d\n", tdc); 993 ((mblk_t *)np)->b_wptr += print_len; 994 buf_len -= print_len; 995 } 996 } 997 998 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 999 return (0); 1000 } 1001 1002 /* ARGSUSED */ 1003 int 1004 nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 1005 { 1006 uint_t print_len, buf_len; 1007 p_mblk_t np; 1008 int rdc; 1009 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1010 p_nxge_hw_pt_cfg_t p_cfgp; 1011 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 1012 p_rx_rcr_rings_t rx_rcr_rings; 1013 p_rx_rcr_ring_t *rcr_rings; 1014 p_rx_rbr_rings_t rx_rbr_rings; 1015 p_rx_rbr_ring_t *rbr_rings; 1016 nxge_grp_set_t *set; 1017 1018 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 1019 1020 (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 1021 nxgep->function_num); 1022 1023 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1024 /* The following may work even if we cannot get a large buf. */ 1025 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1026 return (0); 1027 } 1028 1029 buf_len = buff_alloc_size; 1030 mp->b_cont = np; 1031 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1032 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1033 1034 rx_rcr_rings = nxgep->rx_rcr_rings; 1035 rcr_rings = rx_rcr_rings->rcr_rings; 1036 rx_rbr_rings = nxgep->rx_rbr_rings; 1037 rbr_rings = rx_rbr_rings->rbr_rings; 1038 1039 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1040 "Total RDCs\t %d\n", p_cfgp->max_rdcs); 1041 1042 ((mblk_t *)np)->b_wptr += print_len; 1043 buf_len -= print_len; 1044 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1045 "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 1046 "chunks\t RCR ptr\n"); 1047 1048 ((mblk_t *)np)->b_wptr += print_len; 1049 buf_len -= print_len; 1050 1051 set = &nxgep->rx_set; 1052 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1053 if ((1 << rdc) & set->owned.map) { 1054 print_len = snprintf((char *) 1055 ((mblk_t *)np)->b_wptr, buf_len, 1056 " %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 1057 rdc, 1058 p_dma_cfgp->rcr_timeout[rdc], 1059 p_dma_cfgp->rcr_threshold[rdc], 1060 (void *)rbr_rings[rdc], 1061 rbr_rings[rdc]->num_blocks, (void *)rcr_rings[rdc]); 1062 ((mblk_t *)np)->b_wptr += print_len; 1063 buf_len -= print_len; 1064 } 1065 } 1066 1067 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 1068 return (0); 1069 } 1070 1071 /* ARGSUSED */ 1072 int 1073 nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 1074 p_mblk_t mp, caddr_t cp) 1075 { 1076 uint_t print_len, buf_len; 1077 p_mblk_t np; 1078 int offset, rdc, i, rdc_grp; 1079 p_nxge_rdc_grp_t rdc_grp_p; 1080 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1081 p_nxge_hw_pt_cfg_t p_cfgp; 1082 1083 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 1084 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1085 "==> nxge_param_get_rxdma_rdcgrp_info")); 1086 1087 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1088 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1089 1090 (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 1091 nxgep->function_num); 1092 1093 rdc_grp = p_cfgp->def_mac_rxdma_grpid; 1094 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1095 /* The following may work even if we cannot get a large buf. */ 1096 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1097 return (0); 1098 } 1099 1100 buf_len = buff_alloc_size; 1101 mp->b_cont = np; 1102 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1103 "Total RDC Groups\t %d \n" 1104 "default RDC group\t %d\n", 1105 p_cfgp->max_rdc_grpids, 1106 p_cfgp->def_mac_rxdma_grpid); 1107 1108 ((mblk_t *)np)->b_wptr += print_len; 1109 buf_len -= print_len; 1110 1111 for (i = 0; i < NXGE_MAX_RDC_GROUPS; i++) { 1112 if (p_cfgp->grpids[i]) { 1113 rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 1114 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1115 buf_len, 1116 "\nRDC Group Info for Group [%d] %d\n" 1117 "RDC Count %d\tstart RDC %d\n" 1118 "RDC Group Population Information" 1119 " (offsets 0 - 15)\n", 1120 i, rdc_grp, rdc_grp_p->max_rdcs, 1121 rdc_grp_p->start_rdc); 1122 1123 ((mblk_t *)np)->b_wptr += print_len; 1124 buf_len -= print_len; 1125 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1126 buf_len, "\n"); 1127 ((mblk_t *)np)->b_wptr += print_len; 1128 buf_len -= print_len; 1129 1130 for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 1131 print_len = snprintf( 1132 (char *)((mblk_t *)np)->b_wptr, 1133 buf_len, "[%d]=%d ", rdc, 1134 rdc_grp_p->start_rdc + rdc); 1135 ((mblk_t *)np)->b_wptr += print_len; 1136 buf_len -= print_len; 1137 } 1138 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1139 buf_len, "\n"); 1140 ((mblk_t *)np)->b_wptr += print_len; 1141 buf_len -= print_len; 1142 1143 for (offset = 0; offset < 16; offset++) { 1144 print_len = snprintf( 1145 (char *)((mblk_t *)np)->b_wptr, 1146 buf_len, " %c", 1147 rdc_grp_p->map & (1 << offset) ? 1148 '1' : '0'); 1149 ((mblk_t *)np)->b_wptr += print_len; 1150 buf_len -= print_len; 1151 } 1152 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1153 buf_len, "\n"); 1154 ((mblk_t *)np)->b_wptr += print_len; 1155 buf_len -= print_len; 1156 } 1157 } 1158 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1159 "<== nxge_param_get_rxdma_rdcgrp_info")); 1160 return (0); 1161 } 1162 1163 int 1164 nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 1165 { 1166 p_mblk_t tmp; 1167 1168 tmp = mp; 1169 while (tmp->b_cont) 1170 tmp = tmp->b_cont; 1171 if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 1172 tmp->b_cont = allocb(1024, BPRI_HI); 1173 tmp = tmp->b_cont; 1174 if (!tmp) 1175 return (ENOMEM); 1176 } 1177 1178 *nmp = tmp; 1179 return (0); 1180 } 1181 1182 1183 /* ARGSUSED */ 1184 int 1185 nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1186 char *value, caddr_t cp) 1187 { 1188 char *end; 1189 uint32_t new_value; 1190 p_nxge_param_t pa = (p_nxge_param_t)cp; 1191 1192 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 1193 new_value = (uint32_t)mi_strtol(value, &end, 10); 1194 if (end == value || new_value < pa->minimum || 1195 new_value > pa->maximum) { 1196 return (EINVAL); 1197 } 1198 pa->value = new_value; 1199 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 1200 return (0); 1201 } 1202 1203 1204 /* ARGSUSED */ 1205 int 1206 nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1207 char *value, caddr_t cp) 1208 { 1209 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 1210 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 1211 return (0); 1212 } 1213 1214 1215 /* ARGSUSED */ 1216 int 1217 nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1218 char *value, caddr_t cp) 1219 { 1220 char *end; 1221 uint32_t new_value; 1222 int status = 0; 1223 p_nxge_param_t pa = (p_nxge_param_t)cp; 1224 1225 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 1226 new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 1227 if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 1228 return (EINVAL); 1229 } 1230 1231 if (pa->value != new_value) { 1232 pa->old_value = pa->value; 1233 pa->value = new_value; 1234 } 1235 1236 if (!nxge_param_link_update(nxgep)) { 1237 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1238 " false ret from nxge_param_link_update")); 1239 status = EINVAL; 1240 } 1241 1242 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 1243 return (status); 1244 } 1245 1246 /* ARGSUSED */ 1247 int 1248 nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1249 char *value, caddr_t cp) 1250 { 1251 char *end; 1252 uint32_t cfg_value; 1253 p_nxge_param_t pa = (p_nxge_param_t)cp; 1254 1255 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 1256 1257 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1258 1259 if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 1260 (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 1261 return (EINVAL); 1262 } 1263 1264 if ((pa->value != cfg_value)) { 1265 pa->old_value = pa->value; 1266 pa->value = cfg_value; 1267 nxgep->intr_threshold = pa->value; 1268 } 1269 1270 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 1271 return (0); 1272 } 1273 1274 /* ARGSUSED */ 1275 int 1276 nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1277 char *value, caddr_t cp) 1278 { 1279 char *end; 1280 uint32_t cfg_value; 1281 p_nxge_param_t pa = (p_nxge_param_t)cp; 1282 1283 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 1284 1285 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1286 1287 if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 1288 (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 1289 return (EINVAL); 1290 } 1291 1292 if ((pa->value != cfg_value)) { 1293 pa->old_value = pa->value; 1294 pa->value = cfg_value; 1295 nxgep->intr_timeout = pa->value; 1296 } 1297 1298 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 1299 return (0); 1300 } 1301 1302 /* ARGSUSED */ 1303 static int 1304 nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1305 mblk_t *mp, char *value, caddr_t cp) 1306 { 1307 char *end; 1308 uint32_t status = 0, cfg_value; 1309 p_nxge_param_t pa = (p_nxge_param_t)cp; 1310 uint32_t cfg_it = B_FALSE; 1311 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1312 p_nxge_hw_pt_cfg_t p_cfgp; 1313 uint32_t *val_ptr, *old_val_ptr; 1314 nxge_param_map_t *mac_map; 1315 p_nxge_class_pt_cfg_t p_class_cfgp; 1316 nxge_mv_cfg_t *mac_host_info; 1317 1318 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 1319 1320 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1321 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1322 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1323 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1324 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1325 1326 /* 1327 * now do decoding 1328 */ 1329 mac_map = (nxge_param_map_t *)&cfg_value; 1330 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 1331 cfg_value, mac_map->param_id, mac_map->map_to)); 1332 1333 if ((mac_map->param_id < p_cfgp->max_macs) && 1334 p_cfgp->grpids[mac_map->map_to]) { 1335 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1336 " nxge_param_set_mac_rdcgrp mapping" 1337 " id %d grp %d", mac_map->param_id, mac_map->map_to)); 1338 #if defined(__i386) 1339 val_ptr = (uint32_t *)(uint32_t)pa->value; 1340 #else 1341 val_ptr = (uint32_t *)pa->value; 1342 #endif 1343 #if defined(__i386) 1344 old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1345 #else 1346 old_val_ptr = (uint32_t *)pa->old_value; 1347 #endif 1348 if (val_ptr[mac_map->param_id] != cfg_value) { 1349 old_val_ptr[mac_map->param_id] = 1350 val_ptr[mac_map->param_id]; 1351 val_ptr[mac_map->param_id] = cfg_value; 1352 mac_host_info[mac_map->param_id].mpr_npr = 1353 mac_map->pref; 1354 mac_host_info[mac_map->param_id].flag = 1; 1355 mac_host_info[mac_map->param_id].rdctbl = 1356 mac_map->map_to; 1357 cfg_it = B_TRUE; 1358 } 1359 } else { 1360 return (EINVAL); 1361 } 1362 1363 if (cfg_it == B_TRUE) { 1364 status = nxge_logical_mac_assign_rdc_table(nxgep, 1365 (uint8_t)mac_map->param_id); 1366 if (status != NXGE_OK) 1367 return (EINVAL); 1368 } 1369 1370 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 1371 return (0); 1372 } 1373 1374 /* ARGSUSED */ 1375 static int 1376 nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1377 mblk_t *mp, char *value, caddr_t cp) 1378 { 1379 char *end; 1380 uint32_t status = 0, cfg_value; 1381 p_nxge_param_t pa = (p_nxge_param_t)cp; 1382 uint32_t cfg_it = B_FALSE; 1383 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1384 p_nxge_hw_pt_cfg_t p_cfgp; 1385 uint32_t *val_ptr, *old_val_ptr; 1386 nxge_param_map_t *vmap, *old_map; 1387 p_nxge_class_pt_cfg_t p_class_cfgp; 1388 uint64_t cfgd_vlans; 1389 int i, inc = 0, cfg_position; 1390 nxge_mv_cfg_t *vlan_tbl; 1391 1392 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1393 1394 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1395 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1396 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1397 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1398 1399 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1400 1401 /* now do decoding */ 1402 cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1403 NXGE_PARAM_ARRAY_CNT_SHIFT); 1404 1405 if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 1406 /* 1407 * for now, we process only upto max 1408 * NXGE_PARAM_ARRAY_INIT_SIZE parameters 1409 * In the future, we may want to expand 1410 * the storage array and continue 1411 */ 1412 return (EINVAL); 1413 } 1414 1415 vmap = (nxge_param_map_t *)&cfg_value; 1416 if ((vmap->param_id) && 1417 (vmap->param_id < NXGE_MAX_VLANS) && 1418 (vmap->map_to < p_cfgp->max_rdc_grpids)) { 1419 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1420 "nxge_param_set_vlan_rdcgrp mapping" 1421 " id %d grp %d", 1422 vmap->param_id, vmap->map_to)); 1423 #if defined(__i386) 1424 val_ptr = (uint32_t *)(uint32_t)pa->value; 1425 #else 1426 val_ptr = (uint32_t *)pa->value; 1427 #endif 1428 #if defined(__i386) 1429 old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1430 #else 1431 old_val_ptr = (uint32_t *)pa->old_value; 1432 #endif 1433 1434 /* search to see if this vlan id is already configured */ 1435 for (i = 0; i < cfgd_vlans; i++) { 1436 old_map = (nxge_param_map_t *)&val_ptr[i]; 1437 if ((old_map->param_id == 0) || 1438 (vmap->param_id == old_map->param_id) || 1439 (vlan_tbl[vmap->param_id].flag)) { 1440 cfg_position = i; 1441 break; 1442 } 1443 } 1444 1445 if (cfgd_vlans == 0) { 1446 cfg_position = 0; 1447 inc++; 1448 } 1449 1450 if (i == cfgd_vlans) { 1451 cfg_position = i; 1452 inc++; 1453 } 1454 1455 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1456 "set_vlan_rdcgrp mapping" 1457 " i %d cfgd_vlans %llx position %d ", 1458 i, cfgd_vlans, cfg_position)); 1459 if (val_ptr[cfg_position] != cfg_value) { 1460 old_val_ptr[cfg_position] = val_ptr[cfg_position]; 1461 val_ptr[cfg_position] = cfg_value; 1462 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 1463 vlan_tbl[vmap->param_id].flag = 1; 1464 vlan_tbl[vmap->param_id].rdctbl = 1465 vmap->map_to + p_cfgp->def_mac_rxdma_grpid; 1466 cfg_it = B_TRUE; 1467 if (inc) { 1468 cfgd_vlans++; 1469 pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 1470 pa->type |= (cfgd_vlans << 1471 NXGE_PARAM_ARRAY_CNT_SHIFT); 1472 1473 } 1474 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1475 "after: param_set_vlan_rdcgrp " 1476 " cfg_vlans %llx position %d \n", 1477 cfgd_vlans, cfg_position)); 1478 } 1479 } else { 1480 return (EINVAL); 1481 } 1482 1483 if (cfg_it == B_TRUE) { 1484 status = nxge_fflp_config_vlan_table(nxgep, 1485 (uint16_t)vmap->param_id); 1486 if (status != NXGE_OK) 1487 return (EINVAL); 1488 } 1489 1490 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 1491 return (0); 1492 } 1493 1494 /* ARGSUSED */ 1495 static int 1496 nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1497 mblk_t *mp, caddr_t cp) 1498 { 1499 1500 uint_t print_len, buf_len; 1501 p_mblk_t np; 1502 int i; 1503 uint32_t *val_ptr; 1504 nxge_param_map_t *vmap; 1505 p_nxge_param_t pa = (p_nxge_param_t)cp; 1506 p_nxge_class_pt_cfg_t p_class_cfgp; 1507 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1508 p_nxge_hw_pt_cfg_t p_cfgp; 1509 uint64_t cfgd_vlans = 0; 1510 nxge_mv_cfg_t *vlan_tbl; 1511 int buff_alloc_size = 1512 NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1513 1514 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1515 (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 1516 nxgep->function_num); 1517 1518 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1519 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1520 return (0); 1521 } 1522 1523 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1524 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1525 1526 buf_len = buff_alloc_size; 1527 mp->b_cont = np; 1528 cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1529 NXGE_PARAM_ARRAY_CNT_SHIFT; 1530 1531 i = (int)cfgd_vlans; 1532 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1533 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1534 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1535 "Configured VLANs %d\n" 1536 "VLAN ID\t RDC GRP (Actual/Port)\t" 1537 " Prefernce\n", i); 1538 ((mblk_t *)np)->b_wptr += print_len; 1539 buf_len -= print_len; 1540 #if defined(__i386) 1541 val_ptr = (uint32_t *)(uint32_t)pa->value; 1542 #else 1543 val_ptr = (uint32_t *)pa->value; 1544 #endif 1545 1546 for (i = 0; i < cfgd_vlans; i++) { 1547 vmap = (nxge_param_map_t *)&val_ptr[i]; 1548 if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 1549 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1550 buf_len, 1551 " %d\t\t %d/%d\t\t %d\n", 1552 vmap->param_id, 1553 vlan_tbl[vmap->param_id].rdctbl, 1554 vlan_tbl[vmap->param_id].rdctbl - 1555 p_cfgp->def_mac_rxdma_grpid, 1556 vlan_tbl[vmap->param_id].mpr_npr); 1557 ((mblk_t *)np)->b_wptr += print_len; 1558 buf_len -= print_len; 1559 } 1560 } 1561 1562 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 1563 return (0); 1564 } 1565 1566 /* ARGSUSED */ 1567 static int 1568 nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1569 mblk_t *mp, caddr_t cp) 1570 { 1571 uint_t print_len, buf_len; 1572 p_mblk_t np; 1573 int i; 1574 p_nxge_class_pt_cfg_t p_class_cfgp; 1575 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1576 p_nxge_hw_pt_cfg_t p_cfgp; 1577 nxge_mv_cfg_t *mac_host_info; 1578 1579 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1580 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 1581 (void) mi_mpprintf(mp, 1582 "MAC ADDR RDC Mapping Information for Port\t %d\n", 1583 nxgep->function_num); 1584 1585 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1586 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1587 return (0); 1588 } 1589 1590 buf_len = buff_alloc_size; 1591 mp->b_cont = np; 1592 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1593 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1594 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1595 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1596 print_len = snprintf((char *)np->b_wptr, buf_len, 1597 "MAC ID\t RDC GRP (Actual/Port)\t" 1598 " Prefernce\n"); 1599 ((mblk_t *)np)->b_wptr += print_len; 1600 buf_len -= print_len; 1601 for (i = 0; i < p_cfgp->max_macs; i++) { 1602 if (mac_host_info[i].flag) { 1603 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1604 buf_len, 1605 " %d\t %d/%d\t\t %d\n", 1606 i, mac_host_info[i].rdctbl, 1607 mac_host_info[i].rdctbl - 1608 p_cfgp->def_mac_rxdma_grpid, 1609 mac_host_info[i].mpr_npr); 1610 ((mblk_t *)np)->b_wptr += print_len; 1611 buf_len -= print_len; 1612 } 1613 } 1614 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1615 "Done Info Dumping \n"); 1616 ((mblk_t *)np)->b_wptr += print_len; 1617 buf_len -= print_len; 1618 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 1619 return (0); 1620 } 1621 1622 /* ARGSUSED */ 1623 static int 1624 nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1625 mblk_t *mp, char *value, caddr_t cp) 1626 { 1627 uint32_t status = 0, cfg_value; 1628 p_nxge_param_t pa = (p_nxge_param_t)cp; 1629 uint32_t cfg_it = B_FALSE; 1630 char *end; 1631 1632 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 1633 1634 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1635 if (pa->value != cfg_value) { 1636 pa->old_value = pa->value; 1637 pa->value = cfg_value; 1638 cfg_it = B_TRUE; 1639 } 1640 1641 if (cfg_it == B_TRUE) { 1642 if (pa->value) 1643 status = nxge_fflp_config_tcam_enable(nxgep); 1644 else 1645 status = nxge_fflp_config_tcam_disable(nxgep); 1646 if (status != NXGE_OK) 1647 return (EINVAL); 1648 } 1649 1650 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 1651 return (0); 1652 } 1653 1654 /* ARGSUSED */ 1655 static int 1656 nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1657 mblk_t *mp, char *value, caddr_t cp) 1658 { 1659 uint32_t status = 0, cfg_value; 1660 p_nxge_param_t pa = (p_nxge_param_t)cp; 1661 uint32_t cfg_it = B_FALSE; 1662 char *end; 1663 1664 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 1665 1666 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1667 if (pa->value != cfg_value) { 1668 pa->old_value = pa->value; 1669 pa->value = cfg_value; 1670 cfg_it = B_TRUE; 1671 } 1672 1673 if (cfg_it == B_TRUE) { 1674 if (pa->value) 1675 status = nxge_fflp_config_hash_lookup_enable(nxgep); 1676 else 1677 status = nxge_fflp_config_hash_lookup_disable(nxgep); 1678 if (status != NXGE_OK) 1679 return (EINVAL); 1680 } 1681 1682 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 1683 return (0); 1684 } 1685 1686 /* ARGSUSED */ 1687 static int 1688 nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1689 mblk_t *mp, char *value, caddr_t cp) 1690 { 1691 char *end; 1692 uint32_t status = 0, cfg_value; 1693 p_nxge_param_t pa = (p_nxge_param_t)cp; 1694 uint32_t cfg_it = B_FALSE; 1695 1696 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 1697 1698 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1699 if (pa->value != cfg_value) { 1700 pa->old_value = pa->value; 1701 pa->value = cfg_value; 1702 cfg_it = B_TRUE; 1703 } 1704 1705 if (cfg_it == B_TRUE) { 1706 if (pa->value) 1707 status = nxge_fflp_config_tcam_enable(nxgep); 1708 else 1709 status = nxge_fflp_config_tcam_disable(nxgep); 1710 if (status != NXGE_OK) 1711 return (EINVAL); 1712 } 1713 1714 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 1715 return (0); 1716 } 1717 1718 /* ARGSUSED */ 1719 static int 1720 nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1721 mblk_t *mp, char *value, caddr_t cp) 1722 { 1723 char *end; 1724 uint8_t ether_class; 1725 uint32_t status = 0, cfg_value; 1726 p_nxge_param_t pa = (p_nxge_param_t)cp; 1727 uint8_t cfg_it = B_FALSE; 1728 1729 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 1730 1731 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1732 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1733 return (EINVAL); 1734 } 1735 1736 if (pa->value != cfg_value) { 1737 pa->old_value = pa->value; 1738 pa->value = cfg_value; 1739 cfg_it = B_TRUE; 1740 } 1741 1742 /* do the actual hw setup */ 1743 if (cfg_it == B_TRUE) { 1744 ether_class = mi_strtol(pa->name, &end, 10); 1745 #ifdef lint 1746 ether_class = ether_class; 1747 #endif 1748 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 1749 } 1750 1751 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 1752 return (status); 1753 } 1754 1755 /* ARGSUSED */ 1756 static int 1757 nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1758 mblk_t *mp, char *value, caddr_t cp) 1759 { 1760 char *end; 1761 tcam_class_t class; 1762 uint32_t status, cfg_value; 1763 p_nxge_param_t pa = (p_nxge_param_t)cp; 1764 uint32_t cfg_it = B_FALSE; 1765 1766 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 1767 1768 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1769 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1770 return (EINVAL); 1771 } 1772 1773 if (pa->value != cfg_value) { 1774 pa->old_value = pa->value; 1775 pa->value = cfg_value; 1776 cfg_it = B_TRUE; 1777 } 1778 1779 /* do the actual hw setup with cfg_value. */ 1780 if (cfg_it == B_TRUE) { 1781 class = mi_strtol(pa->name, &end, 10); 1782 status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 1783 } 1784 1785 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 1786 return (status); 1787 } 1788 1789 /* ARGSUSED */ 1790 static int 1791 nxge_class_name_2value(p_nxge_t nxgep, char *name) 1792 { 1793 int i; 1794 int class_instance = param_class_opt_ip_usr4; 1795 p_nxge_param_t param_arr; 1796 1797 param_arr = nxgep->param_arr; 1798 for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 1799 if (strcmp(param_arr[class_instance].name, name) == 0) 1800 return (i); 1801 class_instance++; 1802 } 1803 return (-1); 1804 } 1805 1806 /* ARGSUSED */ 1807 int 1808 nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1809 mblk_t *mp, char *value, caddr_t cp) 1810 { 1811 char *end; 1812 uint32_t status, cfg_value; 1813 p_nxge_param_t pa = (p_nxge_param_t)cp; 1814 tcam_class_t class; 1815 uint32_t cfg_it = B_FALSE; 1816 1817 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 1818 1819 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1820 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1821 return (EINVAL); 1822 } 1823 1824 if (pa->value != cfg_value) { 1825 pa->old_value = pa->value; 1826 pa->value = cfg_value; 1827 cfg_it = B_TRUE; 1828 } 1829 1830 if (cfg_it == B_TRUE) { 1831 /* do the actual hw setup */ 1832 class = nxge_class_name_2value(nxgep, pa->name); 1833 if (class == -1) 1834 return (EINVAL); 1835 1836 status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 1837 if (status != NXGE_OK) 1838 return (EINVAL); 1839 } 1840 1841 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 1842 return (0); 1843 } 1844 1845 /* ARGSUSED */ 1846 static int 1847 nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1848 mblk_t *mp, caddr_t cp) 1849 { 1850 uint32_t status, cfg_value; 1851 p_nxge_param_t pa = (p_nxge_param_t)cp; 1852 tcam_class_t class; 1853 1854 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 1855 1856 /* do the actual hw setup */ 1857 class = nxge_class_name_2value(nxgep, pa->name); 1858 if (class == -1) 1859 return (EINVAL); 1860 1861 cfg_value = 0; 1862 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 1863 if (status != NXGE_OK) 1864 return (EINVAL); 1865 1866 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1867 "nxge_param_get_ip_opt_get %x ", cfg_value)); 1868 1869 pa->value = cfg_value; 1870 (void) mi_mpprintf(mp, "%x", cfg_value); 1871 1872 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 1873 return (0); 1874 } 1875 1876 /* ARGSUSED */ 1877 static int 1878 nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1879 mblk_t *mp, char *value, caddr_t cp) 1880 { 1881 char *end; 1882 uint32_t status, cfg_value; 1883 p_nxge_param_t pa = (p_nxge_param_t)cp; 1884 tcam_class_t class; 1885 uint32_t cfg_it = B_FALSE; 1886 1887 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 1888 1889 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1890 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1891 return (EINVAL); 1892 } 1893 1894 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1895 "nxge_param_fflp_hash_init value %x", cfg_value)); 1896 1897 if (pa->value != cfg_value) { 1898 pa->old_value = pa->value; 1899 pa->value = cfg_value; 1900 cfg_it = B_TRUE; 1901 } 1902 1903 if (cfg_it == B_TRUE) { 1904 char *h_name; 1905 1906 /* do the actual hw setup */ 1907 h_name = pa->name; 1908 h_name++; 1909 class = mi_strtol(h_name, &end, 10); 1910 switch (class) { 1911 case 1: 1912 status = nxge_fflp_set_hash1(nxgep, 1913 (uint32_t)pa->value); 1914 break; 1915 case 2: 1916 status = nxge_fflp_set_hash2(nxgep, 1917 (uint16_t)pa->value); 1918 break; 1919 1920 default: 1921 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1922 " nxge_param_fflp_hash_init" 1923 " %s Wrong hash var %d", 1924 pa->name, class)); 1925 return (EINVAL); 1926 } 1927 if (status != NXGE_OK) 1928 return (EINVAL); 1929 } 1930 1931 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 1932 return (0); 1933 } 1934 1935 /* ARGSUSED */ 1936 static int 1937 nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1938 mblk_t *mp, char *value, caddr_t cp) 1939 { 1940 char *end; 1941 uint32_t status = 0, cfg_value; 1942 p_nxge_param_t pa = (p_nxge_param_t)cp; 1943 uint32_t cfg_it = B_FALSE; 1944 int rdc_grp; 1945 uint8_t real_rdc; 1946 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1947 p_nxge_hw_pt_cfg_t p_cfgp; 1948 p_nxge_rdc_grp_t rdc_grp_p; 1949 1950 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1951 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1952 1953 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 1954 1955 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1956 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1957 return (EINVAL); 1958 } 1959 1960 if (cfg_value >= p_cfgp->max_rdcs) { 1961 return (EINVAL); 1962 } 1963 1964 if (pa->value != cfg_value) { 1965 pa->old_value = pa->value; 1966 pa->value = cfg_value; 1967 cfg_it = B_TRUE; 1968 } 1969 1970 if (cfg_it == B_TRUE) { 1971 char *grp_name; 1972 grp_name = pa->name; 1973 grp_name += strlen("default-grp"); 1974 rdc_grp = mi_strtol(grp_name, &end, 10); 1975 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 1976 real_rdc = rdc_grp_p->start_rdc + cfg_value; 1977 if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 1978 cfg_value) == B_FALSE) { 1979 pa->value = pa->old_value; 1980 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1981 " nxge_param_set_grp_rdc" 1982 " %d read %d actual %d outof range", 1983 rdc_grp, cfg_value, real_rdc)); 1984 return (EINVAL); 1985 } 1986 status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 1987 real_rdc); 1988 if (status != NXGE_OK) 1989 return (EINVAL); 1990 } 1991 1992 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 1993 return (0); 1994 } 1995 1996 /* ARGSUSED */ 1997 static int 1998 nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 1999 mblk_t *mp, char *value, caddr_t cp) 2000 { 2001 char *end; 2002 uint32_t status = B_TRUE, cfg_value; 2003 p_nxge_param_t pa = (p_nxge_param_t)cp; 2004 uint32_t cfg_it = B_FALSE; 2005 2006 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2007 p_nxge_hw_pt_cfg_t p_cfgp; 2008 2009 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 2010 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2011 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2012 2013 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 2014 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2015 return (EINVAL); 2016 } 2017 2018 if (pa->value != cfg_value) { 2019 if (cfg_value >= p_cfgp->max_rdcs) 2020 return (EINVAL); 2021 pa->old_value = pa->value; 2022 pa->value = cfg_value; 2023 cfg_it = B_TRUE; 2024 } 2025 2026 if (cfg_it == B_TRUE) { 2027 int rdc; 2028 if ((rdc = nxge_dci_map(nxgep, VP_BOUND_RX, cfg_value)) < 0) 2029 return (EINVAL); 2030 status = nxge_rxdma_cfg_port_default_rdc(nxgep, 2031 nxgep->function_num, rdc); 2032 if (status != NXGE_OK) 2033 return (EINVAL); 2034 } 2035 2036 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 2037 return (0); 2038 } 2039 2040 /* ARGSUSED */ 2041 static int 2042 nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 2043 mblk_t *mp, char *value, caddr_t cp) 2044 { 2045 char *end; 2046 uint32_t status = 0; 2047 uint64_t cfg_value = 0; 2048 p_nxge_param_t pa = (p_nxge_param_t)cp; 2049 uint32_t cfg_it = B_FALSE; 2050 2051 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 2052 cfg_value = mi_strtol(value, &end, BASE_HEX); 2053 2054 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2055 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2056 " nxge_param_set_nxge_debug_flag" 2057 " outof range %llx", cfg_value)); 2058 return (EINVAL); 2059 } 2060 if (pa->value != cfg_value) { 2061 pa->old_value = pa->value; 2062 pa->value = cfg_value; 2063 cfg_it = B_TRUE; 2064 } 2065 2066 if (cfg_it == B_TRUE) { 2067 nxgep->nxge_debug_level = pa->value; 2068 } 2069 2070 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 2071 return (status); 2072 } 2073 2074 /* ARGSUSED */ 2075 static int 2076 nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2077 { 2078 int status = 0; 2079 p_nxge_param_t pa = (p_nxge_param_t)cp; 2080 2081 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 2082 2083 if (pa->value > 0xffffffff) 2084 (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 2085 (int)(pa->value & 0xffffffff)); 2086 else 2087 (void) mi_mpprintf(mp, "%x", (int)pa->value); 2088 2089 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 2090 return (status); 2091 } 2092 2093 /* ARGSUSED */ 2094 static int 2095 nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 2096 mblk_t *mp, char *value, caddr_t cp) 2097 { 2098 char *end; 2099 uint32_t status = 0; 2100 uint64_t cfg_value = 0; 2101 p_nxge_param_t pa; 2102 uint32_t cfg_it = B_FALSE; 2103 2104 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 2105 cfg_value = mi_strtol(value, &end, BASE_HEX); 2106 pa = (p_nxge_param_t)cp; 2107 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2108 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 2109 " outof range %llx", cfg_value)); 2110 return (EINVAL); 2111 } 2112 if (pa->value != cfg_value) { 2113 pa->old_value = pa->value; 2114 pa->value = cfg_value; 2115 cfg_it = B_TRUE; 2116 } 2117 2118 if (cfg_it == B_TRUE) { 2119 npi_debug_level = pa->value; 2120 } 2121 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 2122 return (status); 2123 } 2124 2125 /* ARGSUSED */ 2126 static int 2127 nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2128 { 2129 nxge_grp_set_t *set = &nxgep->rx_set; 2130 int rdc; 2131 2132 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 2133 2134 if (!isLDOMguest(nxgep)) 2135 (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2136 2137 for (rdc = 0; rdc < NXGE_MAX_TDCS; rdc++) { 2138 if ((1 << rdc) & set->owned.map) { 2139 (void) nxge_dump_rxdma_channel(nxgep, rdc); 2140 } 2141 } 2142 2143 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 2144 return (0); 2145 } 2146 2147 /* ARGSUSED */ 2148 static int 2149 nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2150 { 2151 nxge_grp_set_t *set = &nxgep->tx_set; 2152 int tdc; 2153 2154 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 2155 2156 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { 2157 if ((1 << tdc) & set->owned.map) { 2158 (void) nxge_txdma_regs_dump(nxgep, tdc); 2159 } 2160 } 2161 2162 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 2163 return (0); 2164 } 2165 2166 /* ARGSUSED */ 2167 static int 2168 nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2169 { 2170 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 2171 2172 (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2173 2174 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 2175 return (0); 2176 } 2177 2178 /* ARGSUSED */ 2179 static int 2180 nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2181 { 2182 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 2183 2184 (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2185 nxgep->function_num); 2186 2187 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 2188 return (0); 2189 } 2190 2191 /* ARGSUSED */ 2192 static int 2193 nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2194 { 2195 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 2196 2197 (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2198 nxgep->function_num); 2199 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 2200 return (0); 2201 } 2202 2203 /* ARGSUSED */ 2204 static int 2205 nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2206 { 2207 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 2208 2209 (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 2210 2211 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 2212 return (0); 2213 } 2214 2215 /* ARGSUSED */ 2216 static int 2217 nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2218 { 2219 uint8_t table; 2220 2221 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 2222 for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 2223 (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 2224 table); 2225 } 2226 2227 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 2228 return (0); 2229 } 2230 2231 typedef struct block_info { 2232 char *name; 2233 uint32_t offset; 2234 } block_info_t; 2235 2236 block_info_t reg_block[] = { 2237 {"PIO", PIO}, 2238 {"FZC_PIO", FZC_PIO}, 2239 {"FZC_XMAC", FZC_MAC}, 2240 {"FZC_IPP", FZC_IPP}, 2241 {"FFLP", FFLP}, 2242 {"FZC_FFLP", FZC_FFLP}, 2243 {"PIO_VADDR", PIO_VADDR}, 2244 {"ZCP", ZCP}, 2245 {"FZC_ZCP", FZC_ZCP}, 2246 {"DMC", DMC}, 2247 {"FZC_DMC", FZC_DMC}, 2248 {"TXC", TXC}, 2249 {"FZC_TXC", FZC_TXC}, 2250 {"PIO_LDSV", PIO_LDSV}, 2251 {"PIO_LDGIM", PIO_LDGIM}, 2252 {"PIO_IMASK0", PIO_IMASK0}, 2253 {"PIO_IMASK1", PIO_IMASK1}, 2254 {"FZC_PROM", FZC_PROM}, 2255 {"END", ALL_FF_32}, 2256 }; 2257 2258 /* ARGSUSED */ 2259 static int 2260 nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2261 { 2262 uint_t print_len, buf_len; 2263 p_mblk_t np; 2264 int rdc, tdc, block; 2265 uint64_t base; 2266 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2267 p_nxge_hw_pt_cfg_t p_cfgp; 2268 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 2269 p_tx_ring_t *tx_rings; 2270 p_rx_rcr_rings_t rx_rcr_rings; 2271 p_rx_rcr_ring_t *rcr_rings; 2272 p_rx_rbr_rings_t rx_rbr_rings; 2273 p_rx_rbr_ring_t *rbr_rings; 2274 2275 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2276 "==> nxge_param_dump_ptrs")); 2277 2278 (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 2279 nxgep->function_num); 2280 2281 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 2282 /* The following may work even if we cannot get a large buf. */ 2283 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 2284 return (0); 2285 } 2286 2287 buf_len = buff_alloc_size; 2288 mp->b_cont = np; 2289 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2290 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2291 2292 rx_rcr_rings = nxgep->rx_rcr_rings; 2293 rcr_rings = rx_rcr_rings->rcr_rings; 2294 rx_rbr_rings = nxgep->rx_rbr_rings; 2295 rbr_rings = rx_rbr_rings->rbr_rings; 2296 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2297 "nxgep (nxge_t) $%p\n" 2298 "dev_regs (dev_regs_t) $%p\n", 2299 (void *)nxgep, (void *)nxgep->dev_regs); 2300 2301 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2302 2303 /* do register pointers */ 2304 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2305 "reg base (npi_reg_ptr_t) $%p\t " 2306 "pci reg (npi_reg_ptr_t) $%p\n", 2307 (void *)nxgep->dev_regs->nxge_regp, 2308 (void *)nxgep->dev_regs->nxge_pciregp); 2309 2310 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2311 2312 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2313 "\nBlock \t Offset \n"); 2314 2315 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2316 block = 0; 2317 #if defined(__i386) 2318 base = (uint64_t)(uint32_t)nxgep->dev_regs->nxge_regp; 2319 #else 2320 base = (uint64_t)nxgep->dev_regs->nxge_regp; 2321 #endif 2322 while (reg_block[block].offset != ALL_FF_32) { 2323 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2324 "%9s\t 0x%llx\n", 2325 reg_block[block].name, 2326 (unsigned long long)(reg_block[block].offset + base)); 2327 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2328 block++; 2329 } 2330 2331 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2332 "\nRDC\t rcrp (rx_rcr_ring_t)\t " 2333 "rbrp (rx_rbr_ring_t)\n"); 2334 2335 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2336 2337 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 2338 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2339 " %d\t $%p\t\t $%p\n", 2340 rdc, (void *)rcr_rings[rdc], 2341 (void *)rbr_rings[rdc]); 2342 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2343 } 2344 2345 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2346 "\nTDC\t tdcp (tx_ring_t)\n"); 2347 2348 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2349 tx_rings = nxgep->tx_rings->rings; 2350 for (tdc = 0; tdc < p_cfgp->tdc.count; tdc++) { 2351 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2352 " %d\t $%p\n", tdc, (void *)tx_rings[tdc]); 2353 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2354 } 2355 2356 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 2357 2358 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2359 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 2360 return (0); 2361 } 2362 2363 2364 /* ARGSUSED */ 2365 int 2366 nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 2367 { 2368 ND *nd; 2369 NDE *nde; 2370 char *rwtag; 2371 boolean_t get_ok, set_ok; 2372 size_t param_len; 2373 int status = 0; 2374 2375 nd = (ND *)param; 2376 if (!nd) 2377 return (ENOENT); 2378 2379 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2380 get_ok = (nde->nde_get_pfi != nxge_get_default) && 2381 (nde->nde_get_pfi != NULL); 2382 set_ok = (nde->nde_set_pfi != nxge_set_default) && 2383 (nde->nde_set_pfi != NULL); 2384 if (get_ok) { 2385 if (set_ok) 2386 rwtag = "read and write"; 2387 else 2388 rwtag = "read only"; 2389 } else if (set_ok) 2390 rwtag = "write only"; 2391 else { 2392 continue; 2393 } 2394 param_len = strlen(rwtag); 2395 param_len += strlen(nde->nde_name); 2396 param_len += 4; 2397 2398 (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 2399 } 2400 return (status); 2401 } 2402 2403 /* ARGSUSED */ 2404 int 2405 nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 2406 { 2407 return (EACCES); 2408 } 2409 2410 /* ARGSUSED */ 2411 int 2412 nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2413 caddr_t data) 2414 { 2415 return (EACCES); 2416 } 2417 2418 boolean_t 2419 nxge_param_link_update(p_nxge_t nxgep) 2420 { 2421 p_nxge_param_t param_arr; 2422 nxge_param_index_t i; 2423 boolean_t update_xcvr; 2424 boolean_t update_dev; 2425 int instance; 2426 boolean_t status = B_TRUE; 2427 2428 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_link_update")); 2429 2430 param_arr = nxgep->param_arr; 2431 instance = nxgep->instance; 2432 update_xcvr = B_FALSE; 2433 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 2434 update_xcvr |= param_arr[i].value; 2435 } 2436 2437 if (update_xcvr) { 2438 update_xcvr = B_FALSE; 2439 for (i = param_autoneg; i < param_enable_ipg0; i++) { 2440 update_xcvr |= 2441 (param_arr[i].value != param_arr[i].old_value); 2442 param_arr[i].old_value = param_arr[i].value; 2443 } 2444 if (update_xcvr) { 2445 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2446 "==> nxge_param_link_update: update xcvr")); 2447 RW_ENTER_WRITER(&nxgep->filter_lock); 2448 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 2449 (void) nxge_link_init(nxgep); 2450 (void) nxge_mac_init(nxgep); 2451 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 2452 RW_EXIT(&nxgep->filter_lock); 2453 } 2454 } else { 2455 cmn_err(CE_WARN, " Last setting will leave nxge%d with " 2456 " no link capabilities.", instance); 2457 cmn_err(CE_WARN, " Restoring previous setting."); 2458 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 2459 param_arr[i].value = param_arr[i].old_value; 2460 } 2461 2462 update_dev = B_FALSE; 2463 2464 if (update_dev) { 2465 RW_ENTER_WRITER(&nxgep->filter_lock); 2466 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2467 "==> nxge_param_link_update: update dev")); 2468 (void) nxge_rx_mac_disable(nxgep); 2469 (void) nxge_tx_mac_disable(nxgep); 2470 (void) nxge_tx_mac_enable(nxgep); 2471 (void) nxge_rx_mac_enable(nxgep); 2472 RW_EXIT(&nxgep->filter_lock); 2473 } 2474 2475 nxge_param_hw_update_exit: 2476 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2477 "<== nxge_param_link_update status = 0x%08x", status)); 2478 return (status); 2479 } 2480 2481 /* 2482 * synchronize the adv* and en* parameters. 2483 * 2484 * See comments in <sys/dld.h> for details of the *_en_* 2485 * parameters. The usage of ndd for setting adv parameters will 2486 * synchronize all the en parameters with the nxge parameters, 2487 * implicitly disabling any settings made via dladm. 2488 */ 2489 static void 2490 nxge_param_sync(p_nxge_t nxgep) 2491 { 2492 p_nxge_param_t param_arr; 2493 param_arr = nxgep->param_arr; 2494 2495 nxgep->param_en_pause = param_arr[param_anar_pause].value; 2496 nxgep->param_en_1000fdx = param_arr[param_anar_1000fdx].value; 2497 nxgep->param_en_100fdx = param_arr[param_anar_100fdx].value; 2498 nxgep->param_en_10fdx = param_arr[param_anar_10fdx].value; 2499 } 2500 2501 /* ARGSUSED */ 2502 int 2503 nxge_dld_get_ip_opt(p_nxge_t nxgep, caddr_t cp) 2504 { 2505 uint32_t status, cfg_value; 2506 p_nxge_param_t pa = (p_nxge_param_t)cp; 2507 tcam_class_t class; 2508 2509 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_dld_get_ip_opt")); 2510 2511 /* do the actual hw setup */ 2512 class = nxge_class_name_2value(nxgep, pa->name); 2513 if (class == -1) 2514 return (EINVAL); 2515 2516 cfg_value = 0; 2517 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 2518 if (status != NXGE_OK) 2519 return (EINVAL); 2520 2521 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2522 "nxge_param_get_ip_opt_get %x ", cfg_value)); 2523 2524 pa->value = cfg_value; 2525 2526 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 2527 return (0); 2528 } 2529