1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/nxge/nxge_impl.h> 27 #include <sys/nxge/nxge_mac.h> 28 #include <sys/nxge/nxge_hio.h> 29 30 #define LINK_MONITOR_PERIOD (1000 * 1000) 31 #define LM_WAIT_MULTIPLIER 8 32 33 #define SERDES_RDY_WT_INTERVAL 50 34 #define MAX_SERDES_RDY_RETRIES 10 35 36 #define TN1010_SPEED_1G 1 37 #define TN1010_SPEED_10G 0 38 #define TN1010_AN_IN_PROG 0 /* Auto negotiation in progress */ 39 #define TN1010_AN_COMPLETE 1 40 #define TN1010_AN_RSVD 2 41 #define TN1010_AN_FAILED 3 42 43 extern uint32_t nxge_no_link_notify; 44 extern boolean_t nxge_no_msg; 45 extern uint32_t nxge_lb_dbg; 46 extern boolean_t nxge_jumbo_enable; 47 extern uint32_t nxge_jumbo_mtu; 48 49 /* The following functions may be found in nxge_main.c */ 50 extern void nxge_mmac_kstat_update(p_nxge_t nxgep, mac_addr_slot_t slot, 51 boolean_t factory); 52 extern int nxge_m_mmac_add(void *arg, mac_multi_addr_t *maddr); 53 extern int nxge_m_mmac_remove(void *arg, mac_addr_slot_t slot); 54 extern int nxge_altmac_set(p_nxge_t nxgep, uint8_t *mac_addr, 55 mac_addr_slot_t slot, uint8_t rdctbl); 56 57 typedef enum { 58 CHECK_LINK_RESCHEDULE, 59 CHECK_LINK_STOP 60 } check_link_state_t; 61 62 static check_link_state_t nxge_check_link_stop(nxge_t *); 63 64 /* 65 * Ethernet broadcast address definition. 66 */ 67 static ether_addr_st etherbroadcastaddr = 68 {{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; 69 /* 70 * Ethernet zero address definition. 71 */ 72 static ether_addr_st etherzeroaddr = 73 {{0x0, 0x0, 0x0, 0x0, 0x0, 0x0}}; 74 /* 75 * Supported chip types 76 */ 77 static uint32_t nxge_supported_cl45_ids[] = { 78 BCM8704_DEV_ID, 79 MARVELL_88X_201X_DEV_ID, 80 BCM8706_DEV_ID, 81 TN1010_DEV_ID 82 }; 83 84 static uint32_t nxge_supported_cl22_ids[] = { 85 BCM5464R_PHY_ID, 86 BCM5482_PHY_ID 87 }; 88 89 #define NUM_CLAUSE_45_IDS (sizeof (nxge_supported_cl45_ids) / \ 90 sizeof (uint32_t)) 91 #define NUM_CLAUSE_22_IDS (sizeof (nxge_supported_cl22_ids) / \ 92 sizeof (uint32_t)) 93 /* 94 * static functions 95 */ 96 static uint32_t nxge_get_cl45_pma_pmd_id(p_nxge_t, int); 97 static uint32_t nxge_get_cl45_pcs_id(p_nxge_t, int); 98 static uint32_t nxge_get_cl22_phy_id(p_nxge_t, int); 99 static boolean_t nxge_is_supported_phy(uint32_t, uint8_t); 100 static boolean_t nxge_is_phy_present(p_nxge_t, int, uint32_t, uint32_t); 101 static nxge_status_t nxge_n2_serdes_init(p_nxge_t); 102 static nxge_status_t nxge_neptune_10G_serdes_init(p_nxge_t); 103 static nxge_status_t nxge_1G_serdes_init(p_nxge_t); 104 static nxge_status_t nxge_10G_link_intr_stop(p_nxge_t); 105 static nxge_status_t nxge_10G_link_intr_start(p_nxge_t); 106 static nxge_status_t nxge_1G_copper_link_intr_stop(p_nxge_t); 107 static nxge_status_t nxge_1G_copper_link_intr_start(p_nxge_t); 108 static nxge_status_t nxge_1G_fiber_link_intr_stop(p_nxge_t); 109 static nxge_status_t nxge_1G_fiber_link_intr_start(p_nxge_t); 110 static nxge_status_t nxge_check_mii_link(p_nxge_t); 111 static nxge_status_t nxge_check_10g_link(p_nxge_t); 112 static nxge_status_t nxge_10G_xcvr_init(p_nxge_t); 113 static nxge_status_t nxge_BCM8704_xcvr_init(p_nxge_t); 114 static nxge_status_t nxge_BCM8706_xcvr_init(p_nxge_t); 115 static nxge_status_t nxge_1G_xcvr_init(p_nxge_t); 116 static void nxge_bcm5464_link_led_off(p_nxge_t); 117 static nxge_status_t nxge_check_mrvl88x2011_link(p_nxge_t, boolean_t *); 118 static nxge_status_t nxge_mrvl88x2011_xcvr_init(p_nxge_t); 119 static nxge_status_t nxge_get_num_of_xaui(uint32_t *port_pma_pmd_dev_id, 120 uint32_t *port_pcs_dev_id, uint32_t *port_phy_id, uint8_t *num_xaui); 121 static nxge_status_t nxge_get_tn1010_speed(p_nxge_t nxgep, uint16_t *speed); 122 static nxge_status_t nxge_set_tn1010_param(p_nxge_t nxgep); 123 static nxge_status_t nxge_tn1010_check(p_nxge_t nxgep, 124 nxge_link_state_t *link_up); 125 static boolean_t nxge_is_tn1010_phy(p_nxge_t nxgep); 126 static nxge_status_t nxge_tn1010_xcvr_init(p_nxge_t nxgep); 127 128 nxge_status_t nxge_mac_init(p_nxge_t); 129 static nxge_status_t nxge_mii_get_link_mode(p_nxge_t); 130 131 #ifdef NXGE_DEBUG 132 static void nxge_mii_dump(p_nxge_t); 133 static nxge_status_t nxge_tn1010_reset(p_nxge_t nxgep); 134 static void nxge_dump_tn1010_status_regs(p_nxge_t nxgep); 135 #endif 136 137 /* 138 * xcvr tables for supported transceivers 139 */ 140 141 /* 142 * nxge_n2_10G_table is for 10G fiber or serdes on N2-NIU systems. 143 * The Teranetics TN1010 based copper XAUI card can also be used 144 * on N2-NIU systems in 10G mode, but it uses its own table 145 * nxge_n2_10G_tn1010_table below. 146 */ 147 static nxge_xcvr_table_t nxge_n2_10G_table = { 148 nxge_n2_serdes_init, 149 nxge_10G_xcvr_init, 150 nxge_10G_link_intr_stop, 151 nxge_10G_link_intr_start, 152 nxge_check_10g_link, 153 PCS_XCVR 154 }; 155 156 /* 157 * For the Teranetics TN1010 based copper XAUI card 158 */ 159 static nxge_xcvr_table_t nxge_n2_10G_tn1010_table = { 160 nxge_n2_serdes_init, /* Handle both 1G and 10G */ 161 nxge_tn1010_xcvr_init, /* Handle both 1G and 10G */ 162 nxge_10G_link_intr_stop, 163 nxge_10G_link_intr_start, 164 nxge_check_tn1010_link, /* Will figure out speed */ 165 XPCS_XCVR 166 }; 167 168 static nxge_xcvr_table_t nxge_n2_1G_table = { 169 nxge_n2_serdes_init, 170 nxge_1G_xcvr_init, 171 nxge_1G_fiber_link_intr_stop, 172 nxge_1G_fiber_link_intr_start, 173 nxge_check_mii_link, 174 PCS_XCVR 175 }; 176 177 static nxge_xcvr_table_t nxge_n2_1G_tn1010_table = { 178 nxge_n2_serdes_init, 179 nxge_tn1010_xcvr_init, 180 nxge_1G_fiber_link_intr_stop, /* TN1010 is a Cu PHY, but it uses */ 181 nxge_1G_fiber_link_intr_start, /* PCS for 1G, so call fiber func */ 182 nxge_check_tn1010_link, 183 PCS_XCVR 184 }; 185 186 static nxge_xcvr_table_t nxge_10G_tn1010_table = { 187 nxge_neptune_10G_serdes_init, 188 nxge_tn1010_xcvr_init, 189 nxge_10G_link_intr_stop, 190 nxge_10G_link_intr_start, 191 nxge_check_tn1010_link, 192 XPCS_XCVR 193 }; 194 195 static nxge_xcvr_table_t nxge_1G_tn1010_table = { 196 nxge_1G_serdes_init, 197 nxge_tn1010_xcvr_init, 198 nxge_1G_fiber_link_intr_stop, 199 nxge_1G_fiber_link_intr_start, 200 nxge_check_tn1010_link, 201 PCS_XCVR 202 }; 203 204 static nxge_xcvr_table_t nxge_10G_fiber_table = { 205 nxge_neptune_10G_serdes_init, 206 nxge_10G_xcvr_init, 207 nxge_10G_link_intr_stop, 208 nxge_10G_link_intr_start, 209 nxge_check_10g_link, 210 PCS_XCVR 211 }; 212 213 static nxge_xcvr_table_t nxge_1G_copper_table = { 214 NULL, 215 nxge_1G_xcvr_init, 216 nxge_1G_copper_link_intr_stop, 217 nxge_1G_copper_link_intr_start, 218 nxge_check_mii_link, 219 INT_MII_XCVR 220 }; 221 222 /* This table is for Neptune portmode == PORT_1G_SERDES cases */ 223 static nxge_xcvr_table_t nxge_1G_fiber_table = { 224 nxge_1G_serdes_init, 225 nxge_1G_xcvr_init, 226 nxge_1G_fiber_link_intr_stop, 227 nxge_1G_fiber_link_intr_start, 228 nxge_check_mii_link, 229 PCS_XCVR 230 }; 231 232 static nxge_xcvr_table_t nxge_10G_copper_table = { 233 nxge_neptune_10G_serdes_init, 234 NULL, 235 NULL, 236 NULL, 237 NULL, 238 PCS_XCVR 239 }; 240 241 /* 242 * NXGE_PORT_TN1010 is defined as, 243 * NXGE_PORT_SPD_NONE | (NXGE_PHY_TN1010 << NXGE_PHY_SHIFT) 244 * = 0 | 5 << 16 = 0x50000 245 * 246 * So NEPTUNE_2_TN1010 = 247 * (NXGE_PORT_TN1010 | 248 * (NXGE_PORT_TN1010 << 4) | 249 * (NXGE_PORT_NONE << 8) | 250 * (NXGE_PORT_NONE << 12)), 251 * = 0x50000 | (0x50000 << 4) 252 * = 0x550000 253 * 254 * This function partitions nxgep->nxge_hw_p->niu_type (which may have 255 * value NEPTUNE_2_TN1010) and checks if a port has type = NXGE_PORT_TN1010 256 * = 0x50000 257 */ 258 static boolean_t nxge_is_tn1010_phy(p_nxge_t nxgep) 259 { 260 uint8_t portn = NXGE_GET_PORT_NUM(nxgep->function_num); 261 262 if (((nxgep->nxge_hw_p->niu_type >> (NXGE_PORT_TYPE_SHIFT * portn)) 263 & NXGE_PHY_MASK) == NXGE_PORT_TN1010) { 264 return (B_TRUE); 265 } else { 266 return (B_FALSE); 267 } 268 } 269 270 271 /* 272 * Figure out nxgep->mac.portmode from nxge.conf, OBP's device properties, 273 * serial EEPROM or VPD if possible. Note that not all systems could get 274 * the portmode information by calling this function. For example, the 275 * Maramba system figures out the portmode information by calling function 276 * nxge_setup_xcvr_table. 277 */ 278 nxge_status_t 279 nxge_get_xcvr_type(p_nxge_t nxgep) 280 { 281 nxge_status_t status = NXGE_OK; 282 char *phy_type; 283 char *prop_val; 284 uint8_t portn = NXGE_GET_PORT_NUM(nxgep->function_num); 285 286 nxgep->mac.portmode = 0; 287 nxgep->xcvr_addr = 0; 288 289 /* 290 * First check for hot swappable phy property. 291 */ 292 if (nxgep->hot_swappable_phy == B_TRUE) { 293 nxgep->statsp->mac_stats.xcvr_inuse = HSP_XCVR; 294 nxgep->mac.portmode = PORT_HSP_MODE; 295 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "Other: Hot Swappable")); 296 } else if (ddi_prop_exists(DDI_DEV_T_ANY, nxgep->dip, 297 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 298 "hot-swappable-phy") == 1) { 299 nxgep->statsp->mac_stats.xcvr_inuse = HSP_XCVR; 300 nxgep->mac.portmode = PORT_HSP_MODE; 301 NXGE_DEBUG_MSG((nxgep, MAC_CTL, ".conf: Hot Swappable")); 302 } else if (nxgep->niu_type == N2_NIU && 303 ddi_prop_exists(DDI_DEV_T_ANY, nxgep->dip, 0, 304 "hot-swappable-phy") == 1) { 305 nxgep->statsp->mac_stats.xcvr_inuse = HSP_XCVR; 306 nxgep->mac.portmode = PORT_HSP_MODE; 307 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "OBP: Hot Swappable")); 308 } 309 310 /* 311 * MDIO polling support for Monza RTM card, Goa NEM card 312 */ 313 if (nxgep->mac.portmode == PORT_HSP_MODE) { 314 nxgep->hot_swappable_phy = B_TRUE; 315 /* 316 * If this is the 2nd NIU port, then check 2 addresses 317 * to take care of the Goa NEM card. Port 1 can have addr 17 318 * (in the eval board) or 20 (in the P0 board). 319 */ 320 if (portn == 1) { 321 if (nxge_is_phy_present(nxgep, 322 ALT_GOA_CLAUSE45_PORT1_ADDR, BCM8706_DEV_ID, 323 BCM_PHY_ID_MASK)) { 324 nxgep->xcvr_addr = 325 ALT_GOA_CLAUSE45_PORT1_ADDR; 326 goto found_phy; 327 } 328 } 329 if (nxge_is_phy_present(nxgep, 330 GOA_CLAUSE45_PORT_ADDR_BASE + portn, 331 BCM8706_DEV_ID, BCM_PHY_ID_MASK)) { 332 nxgep->xcvr_addr = GOA_CLAUSE45_PORT_ADDR_BASE + 333 portn; 334 goto found_phy; 335 } 336 337 nxgep->phy_absent = B_TRUE; 338 goto check_phy_done; 339 found_phy: 340 nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR; 341 nxgep->mac.portmode = PORT_10G_FIBER; 342 nxgep->phy_absent = B_FALSE; 343 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "10G Fiber Xcvr " 344 "found for hot swappable phy")); 345 check_phy_done: 346 return (status); 347 } 348 349 /* Get phy-type property (May have been set by nxge.conf) */ 350 if ((ddi_prop_lookup_string(DDI_DEV_T_ANY, nxgep->dip, 351 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 352 "phy-type", &prop_val)) == DDI_PROP_SUCCESS) { 353 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 354 "found conf file: phy-type %s", prop_val)); 355 if (strcmp("xgsd", prop_val) == 0) { 356 nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR; 357 nxgep->mac.portmode = PORT_10G_SERDES; 358 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 359 "found: 10G Serdes")); 360 } else if (strcmp("gsd", prop_val) == 0) { 361 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 362 nxgep->mac.portmode = PORT_1G_SERDES; 363 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "1G Serdes")); 364 } else if (strcmp("mif", prop_val) == 0) { 365 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 366 nxgep->mac.portmode = PORT_1G_COPPER; 367 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "1G Copper Xcvr")); 368 } else if (strcmp("pcs", prop_val) == 0) { 369 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 370 nxgep->mac.portmode = PORT_1G_FIBER; 371 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "1G FIBER Xcvr")); 372 } else if (strcmp("xgf", prop_val) == 0) { 373 /* 374 * Before OBP supports new phy-type property 375 * value "xgc", the 10G copper XAUI may carry 376 * "xgf" instead of "xgc". If the OBP is 377 * upgraded to a newer version which supports 378 * "xgc", then the TN1010 related code in this 379 * "xgf" case will not be used anymore. 380 */ 381 if (nxge_is_tn1010_phy(nxgep)) { 382 if ((status = nxge_set_tn1010_param(nxgep)) 383 != NXGE_OK) { 384 return (status); 385 } 386 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "TN1010 Xcvr")); 387 } else { /* For Fiber XAUI */ 388 nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR; 389 nxgep->mac.portmode = PORT_10G_FIBER; 390 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 391 "10G Fiber Xcvr")); 392 } 393 } else if (strcmp("xgc", prop_val) == 0) { 394 if ((status = nxge_set_tn1010_param(nxgep)) != NXGE_OK) 395 return (status); 396 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "TN1010 Xcvr")); 397 } 398 399 (void) ddi_prop_update_string(DDI_DEV_T_NONE, nxgep->dip, 400 "phy-type", prop_val); 401 ddi_prop_free(prop_val); 402 403 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_get_xcvr_type: " 404 "Got phy type [0x%x] from conf file", 405 nxgep->mac.portmode)); 406 407 return (NXGE_OK); 408 } 409 410 /* Get phy-type property from OBP */ 411 if (nxgep->niu_type == N2_NIU) { 412 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, nxgep->dip, 0, 413 "phy-type", &prop_val) == DDI_PROP_SUCCESS) { 414 if (strcmp("xgf", prop_val) == 0) { 415 /* 416 * Before OBP supports new phy-type property 417 * value "xgc", the 10G copper XAUI may carry 418 * "xgf" instead of "xgc". If the OBP is 419 * upgraded to a newer version which supports 420 * "xgc", then the TN1010 related code in this 421 * "xgf" case will not be used anymore. 422 */ 423 if (nxge_is_tn1010_phy(nxgep)) { 424 if ((status = 425 nxge_set_tn1010_param(nxgep)) 426 != NXGE_OK) { 427 return (status); 428 } 429 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 430 "TN1010 Xcvr")); 431 } else { /* For Fiber XAUI */ 432 nxgep->statsp->mac_stats.xcvr_inuse 433 = XPCS_XCVR; 434 nxgep->mac.portmode = PORT_10G_FIBER; 435 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 436 "10G Fiber Xcvr")); 437 } 438 } else if (strcmp("mif", prop_val) == 0) { 439 nxgep->statsp->mac_stats.xcvr_inuse = 440 INT_MII_XCVR; 441 nxgep->mac.portmode = PORT_1G_COPPER; 442 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 443 "1G Copper Xcvr")); 444 } else if (strcmp("pcs", prop_val) == 0) { 445 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 446 nxgep->mac.portmode = PORT_1G_FIBER; 447 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 448 "1G Fiber Xcvr")); 449 } else if (strcmp("xgc", prop_val) == 0) { 450 status = nxge_set_tn1010_param(nxgep); 451 if (status != NXGE_OK) 452 return (status); 453 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "TN1010 Xcvr")); 454 } else if (strcmp("xgsd", prop_val) == 0) { 455 nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR; 456 nxgep->mac.portmode = PORT_10G_SERDES; 457 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 458 "OBP: 10G Serdes")); 459 } else if (strcmp("gsd", prop_val) == 0) { 460 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 461 nxgep->mac.portmode = PORT_1G_SERDES; 462 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 463 "OBP: 1G Serdes")); 464 } else { 465 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 466 "Unknown phy-type: %s", prop_val)); 467 ddi_prop_free(prop_val); 468 return (NXGE_ERROR); 469 } 470 status = NXGE_OK; 471 (void) ddi_prop_update_string(DDI_DEV_T_NONE, 472 nxgep->dip, "phy-type", prop_val); 473 ddi_prop_free(prop_val); 474 475 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_get_xcvr_type: " 476 "Got phy type [0x%x] from OBP", 477 nxgep->mac.portmode)); 478 479 return (status); 480 } else { 481 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 482 "Exiting...phy-type property not found")); 483 return (NXGE_ERROR); 484 } 485 } 486 487 488 if (!nxgep->vpd_info.present) { 489 return (NXGE_OK); 490 } 491 492 if (!nxgep->vpd_info.ver_valid) { 493 goto read_seeprom; 494 } 495 496 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 497 "Reading phy type from expansion ROM")); 498 /* 499 * Try to read the phy type from the vpd data read off the 500 * expansion ROM. 501 */ 502 phy_type = nxgep->vpd_info.phy_type; 503 504 if (strncmp(phy_type, "mif", 3) == 0) { 505 nxgep->mac.portmode = PORT_1G_COPPER; 506 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 507 } else if (strncmp(phy_type, "xgf", 3) == 0) { 508 nxgep->mac.portmode = PORT_10G_FIBER; 509 nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR; 510 } else if (strncmp(phy_type, "pcs", 3) == 0) { 511 nxgep->mac.portmode = PORT_1G_FIBER; 512 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 513 } else if (strncmp(phy_type, "xgc", 3) == 0) { 514 status = nxge_set_tn1010_param(nxgep); 515 if (status != NXGE_OK) { 516 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 517 "nxge_get_xcvr_type: Failed to set TN1010 param")); 518 goto read_seeprom; 519 } 520 } else if (strncmp(phy_type, "xgsd", 4) == 0) { 521 nxgep->mac.portmode = PORT_10G_SERDES; 522 nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR; 523 } else if (strncmp(phy_type, "gsd", 3) == 0) { 524 nxgep->mac.portmode = PORT_1G_SERDES; 525 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 526 } else { 527 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 528 "nxge_get_xcvr_type: Unknown phy type [%c%c%c] in EEPROM", 529 phy_type[0], phy_type[1], phy_type[2])); 530 goto read_seeprom; 531 } 532 533 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_get_xcvr_type: " 534 "Got phy type [0x%x] from VPD", nxgep->mac.portmode)); 535 536 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_get_xcvr_type")); 537 return (status); 538 539 read_seeprom: 540 /* 541 * read the phy type from the SEEPROM - NCR registers 542 */ 543 status = nxge_espc_phy_type_get(nxgep); 544 if (status != NXGE_OK) { 545 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 546 "Failed to get phy type")); 547 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version " 548 "[%s] invalid...please update", nxgep->vpd_info.ver)); 549 } 550 551 return (status); 552 553 } 554 555 /* Set up the PHY specific values. */ 556 557 nxge_status_t 558 nxge_setup_xcvr_table(p_nxge_t nxgep) 559 { 560 nxge_status_t status = NXGE_OK; 561 uint32_t port_type; 562 uint8_t portn = NXGE_GET_PORT_NUM(nxgep->function_num); 563 uint32_t pcs_id = 0; 564 uint32_t pma_pmd_id = 0; 565 uint32_t phy_id = 0; 566 uint16_t chip_id = 0; 567 568 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_setup_xcvr_table: port<%d>", 569 portn)); 570 571 switch (nxgep->niu_type) { 572 case N2_NIU: 573 switch (nxgep->mac.portmode) { 574 case PORT_1G_FIBER: 575 case PORT_1G_SERDES: 576 nxgep->xcvr = nxge_n2_1G_table; 577 nxgep->xcvr_addr = portn; 578 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "NIU 1G %s Xcvr", 579 (nxgep->mac.portmode == PORT_1G_FIBER) ? "Fiber" : 580 "Serdes")); 581 break; 582 case PORT_10G_FIBER: 583 case PORT_10G_SERDES: 584 nxgep->xcvr = nxge_n2_10G_table; 585 if (nxgep->nxge_hw_p->xcvr_addr[portn]) { 586 nxgep->xcvr_addr = 587 nxgep->nxge_hw_p->xcvr_addr[portn]; 588 } 589 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "NIU 10G %s Xcvr", 590 (nxgep->mac.portmode == PORT_10G_FIBER) ? "Fiber" : 591 "Serdes")); 592 break; 593 case PORT_1G_TN1010: 594 nxgep->xcvr = nxge_n2_1G_tn1010_table; 595 nxgep->xcvr_addr = nxgep->nxge_hw_p->xcvr_addr[portn]; 596 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 597 "TN1010 Copper Xcvr in 1G")); 598 break; 599 case PORT_10G_TN1010: 600 nxgep->xcvr = nxge_n2_10G_tn1010_table; 601 nxgep->xcvr_addr = nxgep->nxge_hw_p->xcvr_addr[portn]; 602 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 603 "TN1010 Copper Xcvr in 10G")); 604 break; 605 case PORT_HSP_MODE: 606 nxgep->xcvr = nxge_n2_10G_table; 607 nxgep->xcvr.xcvr_inuse = HSP_XCVR; 608 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "NIU 10G Hot " 609 "Swappable Xcvr (not present)")); 610 break; 611 default: 612 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 613 "<== nxge_setup_xcvr_table: " 614 "Unable to determine NIU portmode")); 615 return (NXGE_ERROR); 616 } 617 break; 618 default: 619 if (nxgep->mac.portmode == 0) { 620 /* 621 * Would be the case for platforms like Maramba 622 * in which the phy type could not be got from conf 623 * file, OBP, VPD or Serial PROM. 624 */ 625 if (!NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 626 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 627 "<== nxge_setup_xcvr_table:" 628 " Invalid Neptune type [0x%x]", 629 nxgep->niu_type)); 630 return (NXGE_ERROR); 631 } 632 633 port_type = nxgep->niu_type >> 634 (NXGE_PORT_TYPE_SHIFT * portn); 635 port_type = port_type & (NXGE_PORT_TYPE_MASK); 636 637 switch (port_type) { 638 639 case NXGE_PORT_1G_COPPER: 640 nxgep->mac.portmode = PORT_1G_COPPER; 641 break; 642 case NXGE_PORT_10G_COPPER: 643 nxgep->mac.portmode = PORT_10G_COPPER; 644 break; 645 case NXGE_PORT_1G_FIBRE: 646 nxgep->mac.portmode = PORT_1G_FIBER; 647 break; 648 case NXGE_PORT_10G_FIBRE: 649 nxgep->mac.portmode = PORT_10G_FIBER; 650 break; 651 case NXGE_PORT_1G_SERDES: 652 nxgep->mac.portmode = PORT_1G_SERDES; 653 break; 654 case NXGE_PORT_10G_SERDES: 655 nxgep->mac.portmode = PORT_10G_SERDES; 656 break; 657 /* Ports 2 and 3 of Alonso or ARTM */ 658 case NXGE_PORT_1G_RGMII_FIBER: 659 nxgep->mac.portmode = PORT_1G_RGMII_FIBER; 660 break; 661 case NXGE_PORT_TN1010: 662 /* 663 * If this port uses the TN1010 copper 664 * PHY, then its speed is not known yet 665 * because nxge_scan_ports_phy could only 666 * figure out the vendor of the PHY but 667 * not its speed. nxge_set_tn1010_param 668 * will read the PHY speed and set 669 * portmode accordingly. 670 */ 671 if ((status = nxge_set_tn1010_param(nxgep)) 672 != NXGE_OK) { 673 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 674 "nxge_set_tn1010_param failed")); 675 return (status); 676 } 677 break; 678 default: 679 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 680 "<== nxge_setup_xcvr_table: " 681 "Unknown port-type: 0x%x", port_type)); 682 return (NXGE_ERROR); 683 } 684 } 685 686 /* 687 * Above switch has figured out nxge->mac.portmode, now set 688 * nxgep->xcvr (the table) and nxgep->xcvr_addr according 689 * to portmode. 690 */ 691 switch (nxgep->mac.portmode) { 692 case PORT_1G_COPPER: 693 case PORT_1G_RGMII_FIBER: 694 nxgep->xcvr = nxge_1G_copper_table; 695 nxgep->xcvr_addr = nxgep->nxge_hw_p->xcvr_addr[portn]; 696 /* 697 * For Altas 4-1G copper, Xcvr port numbers are 698 * swapped with ethernet port number. This is 699 * designed for better signal integrity in 700 * routing. This is also the case for the 701 * on-board Neptune copper ports on the Maramba 702 * platform. 703 */ 704 switch (nxgep->platform_type) { 705 case P_NEPTUNE_ATLAS_4PORT: 706 case P_NEPTUNE_MARAMBA_P0: 707 case P_NEPTUNE_MARAMBA_P1: 708 switch (portn) { 709 case 0: 710 nxgep->xcvr_addr += 3; 711 break; 712 case 1: 713 nxgep->xcvr_addr += 1; 714 break; 715 case 2: 716 nxgep->xcvr_addr -= 1; 717 break; 718 case 3: 719 nxgep->xcvr_addr -= 3; 720 break; 721 default: 722 return (NXGE_ERROR); 723 } 724 break; 725 default: 726 break; 727 } 728 729 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "1G %s Xcvr", 730 (nxgep->mac.portmode == PORT_1G_COPPER) ? 731 "Copper" : "RGMII Fiber")); 732 break; 733 734 case PORT_10G_COPPER: 735 nxgep->xcvr = nxge_10G_copper_table; 736 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "10G Copper Xcvr")); 737 break; 738 739 case PORT_1G_TN1010: 740 nxgep->xcvr = nxge_1G_tn1010_table; 741 nxgep->xcvr_addr = nxgep->nxge_hw_p->xcvr_addr[portn]; 742 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 743 "1G TN1010 copper Xcvr")); 744 break; 745 746 case PORT_10G_TN1010: 747 nxgep->xcvr = nxge_10G_tn1010_table; 748 nxgep->xcvr_addr = nxgep->nxge_hw_p->xcvr_addr[portn]; 749 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 750 "10G TN1010 copper Xcvr")); 751 break; 752 753 case PORT_1G_FIBER: 754 case PORT_1G_SERDES: 755 nxgep->xcvr = nxge_1G_fiber_table; 756 nxgep->xcvr_addr = portn; 757 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "1G %s Xcvr", 758 (nxgep->mac.portmode == PORT_1G_FIBER) ? 759 "Fiber" : "Serdes")); 760 break; 761 case PORT_10G_FIBER: 762 case PORT_10G_SERDES: 763 nxgep->xcvr = nxge_10G_fiber_table; 764 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "10G xcvr " 765 "nxgep->nxge_hw_p->xcvr_addr[portn] = [%d] " 766 "nxgep->xcvr_addr = [%d]", 767 nxgep->nxge_hw_p->xcvr_addr[portn], 768 nxgep->xcvr_addr)); 769 if (nxgep->nxge_hw_p->xcvr_addr[portn]) { 770 nxgep->xcvr_addr = 771 nxgep->nxge_hw_p->xcvr_addr[portn]; 772 } 773 switch (nxgep->platform_type) { 774 case P_NEPTUNE_MARAMBA_P0: 775 case P_NEPTUNE_MARAMBA_P1: 776 /* 777 * Switch off LED for corresponding copper 778 * port 779 */ 780 nxge_bcm5464_link_led_off(nxgep); 781 break; 782 default: 783 break; 784 } 785 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "10G %s Xcvr", 786 (nxgep->mac.portmode == PORT_10G_FIBER) ? 787 "Fiber" : "Serdes")); 788 break; 789 790 case PORT_HSP_MODE: 791 nxgep->xcvr = nxge_10G_fiber_table; 792 nxgep->xcvr.xcvr_inuse = HSP_XCVR; 793 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "Neptune 10G Hot " 794 "Swappable Xcvr (not present)")); 795 break; 796 default: 797 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 798 "Unknown port-type: 0x%x", port_type)); 799 return (NXGE_ERROR); 800 } 801 } 802 803 if (nxgep->mac.portmode == PORT_10G_FIBER) { 804 uint32_t pma_pmd_id; 805 pma_pmd_id = nxge_get_cl45_pma_pmd_id(nxgep, 806 nxgep->xcvr_addr); 807 if ((pma_pmd_id & BCM_PHY_ID_MASK) == MARVELL_88X201X_PHY_ID) { 808 chip_id = MRVL88X201X_CHIP_ID; 809 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 810 "nxge_setup_xcvr_table: " 811 "Chip ID MARVELL [0x%x] for 10G xcvr", chip_id)); 812 } else if ((status = nxge_mdio_read(nxgep, nxgep->xcvr_addr, 813 BCM8704_PCS_DEV_ADDR, BCM8704_CHIP_ID_REG, 814 &chip_id)) == NXGE_OK) { 815 816 switch (chip_id) { 817 case BCM8704_CHIP_ID: 818 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 819 "nxge_setup_xcvr_table: " 820 "Chip ID 8704 [0x%x] for 10G xcvr", 821 chip_id)); 822 break; 823 case BCM8706_CHIP_ID: 824 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 825 "nxge_setup_xcvr_table: " 826 "Chip ID 8706 [0x%x] for 10G xcvr", 827 chip_id)); 828 break; 829 default: 830 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 831 "nxge_setup_xcvr_table: " 832 "Unknown Chip ID [0x%x] for 10G xcvr", 833 chip_id)); 834 break; 835 } 836 } 837 } 838 839 nxgep->statsp->mac_stats.xcvr_inuse = nxgep->xcvr.xcvr_inuse; 840 nxgep->statsp->mac_stats.xcvr_portn = nxgep->xcvr_addr; 841 nxgep->chip_id = chip_id; 842 843 /* 844 * Get the actual device ID value returned by MDIO read. 845 */ 846 nxgep->statsp->mac_stats.xcvr_id = 0; 847 848 pma_pmd_id = nxge_get_cl45_pma_pmd_id(nxgep, nxgep->xcvr_addr); 849 if (nxge_is_supported_phy(pma_pmd_id, CLAUSE_45_TYPE)) { 850 nxgep->statsp->mac_stats.xcvr_id = pma_pmd_id; 851 } else { 852 pcs_id = nxge_get_cl45_pcs_id(nxgep, nxgep->xcvr_addr); 853 if (nxge_is_supported_phy(pcs_id, CLAUSE_45_TYPE)) { 854 nxgep->statsp->mac_stats.xcvr_id = pcs_id; 855 } else { 856 phy_id = nxge_get_cl22_phy_id(nxgep, 857 nxgep->xcvr_addr); 858 if (nxge_is_supported_phy(phy_id, CLAUSE_22_TYPE)) { 859 nxgep->statsp->mac_stats.xcvr_id = phy_id; 860 } 861 } 862 } 863 864 nxgep->mac.linkchkmode = LINKCHK_TIMER; 865 866 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_setup_xcvr_table: niu_type" 867 "[0x%x] platform type[0x%x] xcvr_addr[%d]", nxgep->niu_type, 868 nxgep->platform_type, nxgep->xcvr_addr)); 869 870 return (status); 871 } 872 873 /* Initialize the entire MAC and physical layer */ 874 875 nxge_status_t 876 nxge_mac_init(p_nxge_t nxgep) 877 { 878 uint8_t portn; 879 nxge_status_t status = NXGE_OK; 880 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 881 882 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_mac_init: port<%d>", portn)); 883 884 nxgep->mac.portnum = portn; 885 nxgep->mac.porttype = PORT_TYPE_XMAC; 886 887 if ((portn == BMAC_PORT_0) || (portn == BMAC_PORT_1)) 888 nxgep->mac.porttype = PORT_TYPE_BMAC; 889 890 891 /* Initialize XIF to configure a network mode */ 892 if ((status = nxge_xif_init(nxgep)) != NXGE_OK) { 893 goto fail; 894 } 895 896 if ((status = nxge_pcs_init(nxgep)) != NXGE_OK) { 897 goto fail; 898 } 899 900 /* Initialize TX and RX MACs */ 901 /* 902 * Always perform XIF init first, before TX and RX MAC init 903 */ 904 if ((status = nxge_tx_mac_reset(nxgep)) != NXGE_OK) 905 goto fail; 906 907 if ((status = nxge_tx_mac_init(nxgep)) != NXGE_OK) 908 goto fail; 909 910 if ((status = nxge_rx_mac_reset(nxgep)) != NXGE_OK) 911 goto fail; 912 913 if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK) 914 goto fail; 915 916 if ((status = nxge_tx_mac_enable(nxgep)) != NXGE_OK) 917 goto fail; 918 919 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) 920 goto fail; 921 922 /* Initialize MAC control configuration */ 923 if ((status = nxge_mac_ctrl_init(nxgep)) != NXGE_OK) { 924 goto fail; 925 } 926 927 nxgep->statsp->mac_stats.mac_mtu = nxgep->mac.maxframesize; 928 929 /* The Neptune Serdes needs to be reinitialized again */ 930 if ((NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) && 931 ((nxgep->mac.portmode == PORT_1G_SERDES) || 932 (nxgep->mac.portmode == PORT_1G_TN1010) || 933 (nxgep->mac.portmode == PORT_1G_FIBER)) && 934 ((portn == 0) || (portn == 1))) { 935 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 936 "nxge_mac_init: reinit Neptune 1G Serdes ")); 937 if ((status = nxge_1G_serdes_init(nxgep)) != NXGE_OK) { 938 goto fail; 939 } 940 } 941 942 943 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_mac_init: port<%d>", portn)); 944 945 return (NXGE_OK); 946 fail: 947 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 948 "nxge_mac_init: failed to initialize MAC port<%d>", portn)); 949 return (status); 950 } 951 952 /* Initialize the Ethernet Link */ 953 954 nxge_status_t 955 nxge_link_init(p_nxge_t nxgep) 956 { 957 nxge_status_t status = NXGE_OK; 958 nxge_port_mode_t portmode; 959 #ifdef NXGE_DEBUG 960 uint8_t portn; 961 962 portn = nxgep->mac.portnum; 963 964 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_link_init: port<%d>", portn)); 965 #endif 966 if (nxgep->hot_swappable_phy && nxgep->phy_absent) { 967 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_link_init: " 968 "Phy not present, cannot initialize link")); 969 return (status); 970 } 971 972 portmode = nxgep->mac.portmode; 973 974 /* 975 * Workaround to get link up in both NIU ports. Some portmodes require 976 * that the xcvr be initialized twice, the first time before calling 977 * nxge_serdes_init. 978 */ 979 if (nxgep->niu_type == N2_NIU && (portmode != PORT_10G_SERDES) && 980 (portmode != PORT_10G_TN1010) && 981 (portmode != PORT_1G_TN1010) && 982 (portmode != PORT_1G_SERDES)) { 983 if ((status = nxge_xcvr_init(nxgep)) != NXGE_OK) { 984 goto fail; 985 } 986 } 987 988 NXGE_DELAY(200000); 989 /* Initialize internal serdes */ 990 if ((status = nxge_serdes_init(nxgep)) != NXGE_OK) 991 goto fail; 992 NXGE_DELAY(200000); 993 if ((status = nxge_xcvr_init(nxgep)) != NXGE_OK) 994 goto fail; 995 996 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_link_init: port<%d>", portn)); 997 998 return (NXGE_OK); 999 1000 fail: 1001 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_link_init: ", 1002 "failed to initialize Ethernet link on port<%d>", portn)); 1003 1004 return (status); 1005 } 1006 1007 1008 /* Initialize the XIF sub-block within the MAC */ 1009 1010 nxge_status_t 1011 nxge_xif_init(p_nxge_t nxgep) 1012 { 1013 uint32_t xif_cfg = 0; 1014 npi_attr_t ap; 1015 uint8_t portn; 1016 nxge_port_t portt; 1017 nxge_port_mode_t portmode; 1018 p_nxge_stats_t statsp; 1019 npi_status_t rs = NPI_SUCCESS; 1020 npi_handle_t handle; 1021 1022 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 1023 1024 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_xif_init: port<%d>", portn)); 1025 1026 handle = nxgep->npi_handle; 1027 portmode = nxgep->mac.portmode; 1028 portt = nxgep->mac.porttype; 1029 statsp = nxgep->statsp; 1030 1031 if ((NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) && 1032 ((nxgep->mac.portmode == PORT_1G_SERDES) || 1033 (nxgep->mac.portmode == PORT_1G_TN1010) || 1034 (nxgep->mac.portmode == PORT_1G_FIBER)) && 1035 ((portn == 0) || (portn == 1))) { 1036 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1037 "nxge_xcvr_init: set ATCA mode")); 1038 npi_mac_mif_set_atca_mode(nxgep->npi_handle, B_TRUE); 1039 } 1040 1041 if (portt == PORT_TYPE_XMAC) { 1042 1043 /* Setup XIF Configuration for XMAC */ 1044 1045 if ((portmode == PORT_10G_FIBER) || 1046 (portmode == PORT_10G_COPPER) || 1047 (portmode == PORT_10G_TN1010) || 1048 (portmode == PORT_10G_SERDES)) 1049 xif_cfg |= CFG_XMAC_XIF_LFS; 1050 1051 /* Bypass PCS so that RGMII will be used */ 1052 if (portmode == PORT_1G_COPPER) { 1053 xif_cfg |= CFG_XMAC_XIF_1G_PCS_BYPASS; 1054 } 1055 1056 /* Set MAC Internal Loopback if necessary */ 1057 if (statsp->port_stats.lb_mode == nxge_lb_mac1000) 1058 xif_cfg |= CFG_XMAC_XIF_LOOPBACK; 1059 1060 if (statsp->mac_stats.link_speed == 100) 1061 xif_cfg |= CFG_XMAC_XIF_SEL_CLK_25MHZ; 1062 1063 xif_cfg |= CFG_XMAC_XIF_TX_OUTPUT; 1064 1065 if ((portmode == PORT_10G_FIBER) || 1066 (portmode == PORT_10G_TN1010) || 1067 (portmode == PORT_1G_TN1010) || 1068 (portmode == PORT_10G_SERDES)) { 1069 /* Assume LED same for 1G and 10G */ 1070 if (statsp->mac_stats.link_up) { 1071 xif_cfg |= CFG_XMAC_XIF_LED_POLARITY; 1072 } else { 1073 xif_cfg |= CFG_XMAC_XIF_LED_FORCE; 1074 } 1075 } 1076 1077 rs = npi_xmac_xif_config(handle, INIT, portn, xif_cfg); 1078 if (rs != NPI_SUCCESS) 1079 goto fail; 1080 1081 nxgep->mac.xif_config = xif_cfg; 1082 1083 /* Set Port Mode */ 1084 if ((portmode == PORT_10G_FIBER) || 1085 (portmode == PORT_10G_COPPER) || 1086 (portmode == PORT_10G_TN1010) || 1087 (portmode == PORT_10G_SERDES)) { 1088 SET_MAC_ATTR1(handle, ap, portn, MAC_PORT_MODE, 1089 MAC_XGMII_MODE, rs); 1090 if (rs != NPI_SUCCESS) 1091 goto fail; 1092 if (statsp->mac_stats.link_up) { 1093 if (nxge_10g_link_led_on(nxgep) != NXGE_OK) 1094 goto fail; 1095 } else { 1096 if (nxge_10g_link_led_off(nxgep) != NXGE_OK) 1097 goto fail; 1098 } 1099 } else if ((portmode == PORT_1G_FIBER) || 1100 (portmode == PORT_1G_COPPER) || 1101 (portmode == PORT_1G_SERDES) || 1102 (portmode == PORT_1G_TN1010) || 1103 (portmode == PORT_1G_RGMII_FIBER)) { 1104 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1105 "nxge_xif_init: Port[%d] Mode[%d] Speed[%d]", 1106 portn, portmode, statsp->mac_stats.link_speed)); 1107 if (statsp->mac_stats.link_speed == 1000) { 1108 SET_MAC_ATTR1(handle, ap, portn, MAC_PORT_MODE, 1109 MAC_GMII_MODE, rs); 1110 } else { 1111 SET_MAC_ATTR1(handle, ap, portn, MAC_PORT_MODE, 1112 MAC_MII_MODE, rs); 1113 } 1114 if (rs != NPI_SUCCESS) 1115 goto fail; 1116 } else { 1117 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1118 "nxge_xif_init: Unknown port mode (%d)" 1119 " for port<%d>", portmode, portn)); 1120 goto fail; 1121 } 1122 1123 /* Enable ATCA mode */ 1124 1125 } else if (portt == PORT_TYPE_BMAC) { 1126 1127 /* Setup XIF Configuration for BMAC */ 1128 1129 if ((portmode == PORT_1G_COPPER) || 1130 (portmode == PORT_1G_RGMII_FIBER)) { 1131 if (statsp->mac_stats.link_speed == 100) 1132 xif_cfg |= CFG_BMAC_XIF_SEL_CLK_25MHZ; 1133 } 1134 1135 if (statsp->port_stats.lb_mode == nxge_lb_mac1000) 1136 xif_cfg |= CFG_BMAC_XIF_LOOPBACK; 1137 1138 if (statsp->mac_stats.link_speed == 1000) 1139 xif_cfg |= CFG_BMAC_XIF_GMII_MODE; 1140 1141 xif_cfg |= CFG_BMAC_XIF_TX_OUTPUT; 1142 1143 rs = npi_bmac_xif_config(handle, INIT, portn, xif_cfg); 1144 if (rs != NPI_SUCCESS) 1145 goto fail; 1146 nxgep->mac.xif_config = xif_cfg; 1147 } 1148 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_xif_init: port<%d>", portn)); 1149 return (NXGE_OK); 1150 fail: 1151 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1152 "nxge_xif_init: Failed to initialize XIF port<%d>", portn)); 1153 return (NXGE_ERROR | rs); 1154 } 1155 1156 1157 /* 1158 * Initialize the PCS sub-block in the MAC. Note that PCS does not 1159 * support loopback like XPCS. 1160 */ 1161 nxge_status_t 1162 nxge_pcs_init(p_nxge_t nxgep) 1163 { 1164 pcs_cfg_t pcs_cfg; 1165 uint32_t val; 1166 uint8_t portn; 1167 nxge_port_mode_t portmode; 1168 npi_handle_t handle; 1169 p_nxge_stats_t statsp; 1170 pcs_ctrl_t pcs_ctrl; 1171 npi_status_t rs = NPI_SUCCESS; 1172 uint8_t i; 1173 1174 handle = nxgep->npi_handle; 1175 portmode = nxgep->mac.portmode; 1176 portn = nxgep->mac.portnum; 1177 statsp = nxgep->statsp; 1178 1179 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_pcs_init: port<%d>", portn)); 1180 1181 if (portmode == PORT_1G_FIBER || 1182 portmode == PORT_1G_TN1010 || 1183 portmode == PORT_1G_SERDES) { 1184 if (portmode == PORT_1G_TN1010) { 1185 /* Reset PCS multiple time in PORT_1G_TN1010 mode */ 1186 for (i = 0; i < 6; i ++) { 1187 if ((rs = npi_mac_pcs_reset(handle, portn)) 1188 != NPI_SUCCESS) { 1189 goto fail; 1190 } 1191 } 1192 } else { 1193 if ((rs = npi_mac_pcs_reset(handle, portn)) 1194 != NPI_SUCCESS) 1195 goto fail; 1196 } 1197 1198 /* Initialize port's PCS */ 1199 pcs_cfg.value = 0; 1200 pcs_cfg.bits.w0.enable = 1; 1201 pcs_cfg.bits.w0.mask = 1; 1202 PCS_REG_WR(handle, portn, PCS_CONFIG_REG, pcs_cfg.value); 1203 PCS_REG_WR(handle, portn, PCS_DATAPATH_MODE_REG, 0); 1204 1205 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1206 "==> nxge_pcs_init: (1G) port<%d> write config 0x%llx", 1207 portn, pcs_cfg.value)); 1208 1209 if (portmode == PORT_1G_TN1010) { 1210 /* 1211 * Must disable PCS auto-negotiation when the the driver 1212 * is driving the TN1010 based XAUI card Otherwise the 1213 * autonegotiation between the PCS and the TN1010 PCS 1214 * will never complete and the Neptune/NIU will not work 1215 */ 1216 pcs_ctrl.value = 0; 1217 PCS_REG_WR(handle, portn, PCS_MII_CTRL_REG, 1218 pcs_ctrl.value); 1219 } 1220 } else if (portmode == PORT_10G_FIBER || 1221 portmode == PORT_10G_COPPER || 1222 portmode == PORT_10G_TN1010 || 1223 portmode == PORT_10G_SERDES) { 1224 /* Use internal XPCS, bypass 1G PCS */ 1225 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1226 val &= ~XMAC_XIF_XPCS_BYPASS; 1227 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1228 1229 if ((rs = npi_xmac_xpcs_reset(handle, portn)) != NPI_SUCCESS) 1230 goto fail; 1231 1232 /* Set XPCS Internal Loopback if necessary */ 1233 if ((rs = npi_xmac_xpcs_read(handle, portn, 1234 XPCS_REG_CONTROL1, &val)) != NPI_SUCCESS) 1235 goto fail; 1236 1237 if ((statsp->port_stats.lb_mode == nxge_lb_mac10g) || 1238 (statsp->port_stats.lb_mode == nxge_lb_mac1000)) 1239 val |= XPCS_CTRL1_LOOPBK; 1240 else 1241 val &= ~XPCS_CTRL1_LOOPBK; 1242 if ((rs = npi_xmac_xpcs_write(handle, portn, 1243 XPCS_REG_CONTROL1, val)) != NPI_SUCCESS) 1244 goto fail; 1245 1246 /* Clear descw errors */ 1247 if ((rs = npi_xmac_xpcs_write(handle, portn, 1248 XPCS_REG_DESCWERR_COUNTER, 0)) != NPI_SUCCESS) 1249 goto fail; 1250 /* Clear symbol errors */ 1251 if ((rs = npi_xmac_xpcs_read(handle, portn, 1252 XPCS_REG_SYMBOL_ERR_L0_1_COUNTER, &val)) != NPI_SUCCESS) 1253 goto fail; 1254 if ((rs = npi_xmac_xpcs_read(handle, portn, 1255 XPCS_REG_SYMBOL_ERR_L2_3_COUNTER, &val)) != NPI_SUCCESS) 1256 goto fail; 1257 1258 } else if ((portmode == PORT_1G_COPPER) || 1259 (portmode == PORT_1G_RGMII_FIBER)) { 1260 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1261 "==> nxge_pcs_init: (1G) copper port<%d>", portn)); 1262 if (portn < 4) { 1263 PCS_REG_WR(handle, portn, PCS_DATAPATH_MODE_REG, 1264 PCS_DATAPATH_MODE_MII); 1265 } 1266 if ((rs = npi_mac_pcs_reset(handle, portn)) != NPI_SUCCESS) 1267 goto fail; 1268 1269 } else { 1270 goto fail; 1271 } 1272 pass: 1273 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_pcs_init: port<%d>", portn)); 1274 return (NXGE_OK); 1275 fail: 1276 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1277 "nxge_pcs_init: Failed to initialize PCS port<%d>", portn)); 1278 return (NXGE_ERROR | rs); 1279 } 1280 1281 /* 1282 * Initialize the MAC CTRL sub-block within the MAC 1283 * Only the receive-pause-cap is supported. 1284 */ 1285 nxge_status_t 1286 nxge_mac_ctrl_init(p_nxge_t nxgep) 1287 { 1288 uint8_t portn; 1289 nxge_port_t portt; 1290 p_nxge_stats_t statsp; 1291 npi_handle_t handle; 1292 uint32_t val; 1293 1294 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 1295 1296 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_mac_ctrl_init: port<%d>", 1297 portn)); 1298 1299 handle = nxgep->npi_handle; 1300 portt = nxgep->mac.porttype; 1301 statsp = nxgep->statsp; 1302 1303 if (portt == PORT_TYPE_XMAC) { 1304 /* Reading the current XMAC Config Register for XMAC */ 1305 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1306 1307 /* 1308 * Setup XMAC Configuration for XMAC 1309 * XMAC only supports receive-pause 1310 */ 1311 if (statsp->mac_stats.adv_cap_asmpause) { 1312 if (!statsp->mac_stats.adv_cap_pause) { 1313 /* 1314 * If adv_cap_asmpause is 1 and adv_cap_pause 1315 * is 0, enable receive pause. 1316 */ 1317 val |= XMAC_RX_CFG_RX_PAUSE_EN; 1318 } else { 1319 /* 1320 * If adv_cap_asmpause is 1 and adv_cap_pause 1321 * is 1, disable receive pause. Send pause is 1322 * not supported. 1323 */ 1324 val &= ~XMAC_RX_CFG_RX_PAUSE_EN; 1325 } 1326 } else { 1327 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1328 "==> nxge_mac_ctrl_init: port<%d>: pause", 1329 portn)); 1330 if (statsp->mac_stats.adv_cap_pause) { 1331 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1332 "==> nxge_mac_ctrl_init: port<%d>: " 1333 "enable pause", portn)); 1334 /* 1335 * If adv_cap_asmpause is 0 and adv_cap_pause 1336 * is 1, enable receive pause. 1337 */ 1338 val |= XMAC_RX_CFG_RX_PAUSE_EN; 1339 } else { 1340 /* 1341 * If adv_cap_asmpause is 0 and adv_cap_pause 1342 * is 0, disable receive pause. Send pause is 1343 * not supported 1344 */ 1345 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1346 "==> nxge_mac_ctrl_init: port<%d>: " 1347 "disable pause", portn)); 1348 val &= ~XMAC_RX_CFG_RX_PAUSE_EN; 1349 } 1350 } 1351 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1352 } else if (portt == PORT_TYPE_BMAC) { 1353 /* Reading the current MAC CTRL Config Register for BMAC */ 1354 BMAC_REG_RD(handle, portn, MAC_CTRL_CONFIG_REG, &val); 1355 1356 /* Setup MAC CTRL Configuration for BMAC */ 1357 if (statsp->mac_stats.adv_cap_asmpause) { 1358 if (statsp->mac_stats.adv_cap_pause) { 1359 /* 1360 * If adv_cap_asmpause is 1 and adv_cap_pause 1361 * is 1, disable receive pause. Send pause 1362 * is not supported 1363 */ 1364 val &= ~MAC_CTRL_CFG_RECV_PAUSE_EN; 1365 } else { 1366 /* 1367 * If adv_cap_asmpause is 1 and adv_cap_pause 1368 * is 0, enable receive pause and disable 1369 * send pause. 1370 */ 1371 val |= MAC_CTRL_CFG_RECV_PAUSE_EN; 1372 val &= ~MAC_CTRL_CFG_SEND_PAUSE_EN; 1373 } 1374 } else { 1375 if (statsp->mac_stats.adv_cap_pause) { 1376 /* 1377 * If adv_cap_asmpause is 0 and adv_cap_pause 1378 * is 1, enable receive pause. Send pause is 1379 * not supported. 1380 */ 1381 val |= MAC_CTRL_CFG_RECV_PAUSE_EN; 1382 } else { 1383 /* 1384 * If adv_cap_asmpause is 0 and adv_cap_pause 1385 * is 0, pause capability is not available in 1386 * either direction. 1387 */ 1388 val &= (~MAC_CTRL_CFG_SEND_PAUSE_EN & 1389 ~MAC_CTRL_CFG_RECV_PAUSE_EN); 1390 } 1391 } 1392 BMAC_REG_WR(handle, portn, MAC_CTRL_CONFIG_REG, val); 1393 } 1394 1395 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_mac_ctrl_init: port<%d>", 1396 portn)); 1397 1398 return (NXGE_OK); 1399 } 1400 1401 /* Initialize the Internal Serdes */ 1402 1403 nxge_status_t 1404 nxge_serdes_init(p_nxge_t nxgep) 1405 { 1406 p_nxge_stats_t statsp; 1407 #ifdef NXGE_DEBUG 1408 uint8_t portn; 1409 #endif 1410 nxge_status_t status = NXGE_OK; 1411 1412 #ifdef NXGE_DEBUG 1413 portn = nxgep->mac.portnum; 1414 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1415 "==> nxge_serdes_init port<%d>", portn)); 1416 #endif 1417 1418 if (nxgep->xcvr.serdes_init) { 1419 statsp = nxgep->statsp; 1420 status = nxgep->xcvr.serdes_init(nxgep); 1421 if (status != NXGE_OK) 1422 goto fail; 1423 statsp->mac_stats.serdes_inits++; 1424 } 1425 1426 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_serdes_init port<%d>", 1427 portn)); 1428 1429 return (NXGE_OK); 1430 1431 fail: 1432 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1433 "nxge_serdes_init: Failed to initialize serdes for port<%d>", 1434 portn)); 1435 1436 return (status); 1437 } 1438 1439 /* Initialize the TI Hedwig Internal Serdes (N2-NIU only) */ 1440 1441 static nxge_status_t 1442 nxge_n2_serdes_init(p_nxge_t nxgep) 1443 { 1444 uint8_t portn; 1445 int chan; 1446 esr_ti_cfgpll_l_t pll_cfg_l; 1447 esr_ti_cfgpll_l_t pll_sts_l; 1448 esr_ti_cfgrx_l_t rx_cfg_l; 1449 esr_ti_cfgrx_h_t rx_cfg_h; 1450 esr_ti_cfgtx_l_t tx_cfg_l; 1451 esr_ti_cfgtx_h_t tx_cfg_h; 1452 #ifdef NXGE_DEBUG 1453 esr_ti_testcfg_t cfg; 1454 #endif 1455 esr_ti_testcfg_t test_cfg; 1456 nxge_status_t status = NXGE_OK; 1457 1458 portn = nxgep->mac.portnum; 1459 1460 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_n2_serdes_init port<%d>", 1461 portn)); 1462 1463 tx_cfg_l.value = 0; 1464 tx_cfg_h.value = 0; 1465 rx_cfg_l.value = 0; 1466 rx_cfg_h.value = 0; 1467 pll_cfg_l.value = 0; 1468 pll_sts_l.value = 0; 1469 test_cfg.value = 0; 1470 1471 /* 1472 * If the nxge driver has been plumbed without a link, then it will 1473 * detect a link up when a cable connecting to an anto-negotiation 1474 * partner is plugged into the port. Because the TN1010 PHY supports 1475 * both 1G and 10G speeds, the driver must re-configure the 1476 * Neptune/NIU according to the negotiated speed. nxge_n2_serdes_init 1477 * is called at the post-link-up reconfiguration time. Here it calls 1478 * nxge_set_tn1010_param to set portmode before re-initializing 1479 * the serdes. 1480 */ 1481 if (nxgep->mac.portmode == PORT_1G_TN1010 || 1482 nxgep->mac.portmode == PORT_10G_TN1010) { 1483 if (nxge_set_tn1010_param(nxgep) != NXGE_OK) { 1484 goto fail; 1485 } 1486 } 1487 1488 if (nxgep->mac.portmode == PORT_10G_FIBER || 1489 nxgep->mac.portmode == PORT_10G_TN1010 || 1490 nxgep->mac.portmode == PORT_10G_SERDES) { 1491 /* 0x0E01 */ 1492 tx_cfg_l.bits.entx = 1; 1493 tx_cfg_l.bits.swing = CFGTX_SWING_1375MV; 1494 1495 /* 0x9101 */ 1496 rx_cfg_l.bits.enrx = 1; 1497 rx_cfg_l.bits.term = CFGRX_TERM_0P8VDDT; 1498 rx_cfg_l.bits.align = CFGRX_ALIGN_EN; 1499 rx_cfg_l.bits.los = CFGRX_LOS_LOTHRES; 1500 1501 /* 0x0008 */ 1502 rx_cfg_h.bits.eq = CFGRX_EQ_ADAPTIVE_LP_ADAPTIVE_ZF; 1503 1504 /* Set loopback mode if necessary */ 1505 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g) { 1506 tx_cfg_l.bits.entest = 1; 1507 rx_cfg_l.bits.entest = 1; 1508 test_cfg.bits.loopback = TESTCFG_INNER_CML_DIS_LOOPBACK; 1509 if ((status = nxge_mdio_write(nxgep, portn, 1510 ESR_N2_DEV_ADDR, 1511 ESR_N2_TEST_CFG_REG, test_cfg.value)) != NXGE_OK) 1512 goto fail; 1513 } 1514 1515 /* Initialize PLL for 10G */ 1516 pll_cfg_l.bits.mpy = CFGPLL_MPY_10X; 1517 pll_cfg_l.bits.enpll = 1; 1518 pll_sts_l.bits.enpll = 1; 1519 if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR, 1520 ESR_N2_PLL_CFG_L_REG, pll_cfg_l.value)) != NXGE_OK) 1521 goto fail; 1522 1523 if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR, 1524 ESR_N2_PLL_STS_L_REG, pll_sts_l.value)) != NXGE_OK) 1525 goto fail; 1526 1527 #ifdef NXGE_DEBUG 1528 nxge_mdio_read(nxgep, portn, ESR_N2_DEV_ADDR, 1529 ESR_N2_PLL_CFG_L_REG, &cfg.value); 1530 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1531 "==> nxge_n2_serdes_init port<%d>: PLL cfg.l 0x%x (0x%x)", 1532 portn, pll_cfg_l.value, cfg.value)); 1533 1534 nxge_mdio_read(nxgep, portn, ESR_N2_DEV_ADDR, 1535 ESR_N2_PLL_STS_L_REG, &cfg.value); 1536 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1537 "==> nxge_n2_serdes_init port<%d>: PLL sts.l 0x%x (0x%x)", 1538 portn, pll_sts_l.value, cfg.value)); 1539 #endif 1540 } else if (nxgep->mac.portmode == PORT_1G_FIBER || 1541 nxgep->mac.portmode == PORT_1G_TN1010 || 1542 nxgep->mac.portmode == PORT_1G_SERDES) { 1543 /* 0x0E21 */ 1544 tx_cfg_l.bits.entx = 1; 1545 tx_cfg_l.bits.rate = CFGTX_RATE_HALF; 1546 tx_cfg_l.bits.swing = CFGTX_SWING_1375MV; 1547 1548 /* 0x9121 */ 1549 rx_cfg_l.bits.enrx = 1; 1550 rx_cfg_l.bits.rate = CFGRX_RATE_HALF; 1551 rx_cfg_l.bits.term = CFGRX_TERM_0P8VDDT; 1552 rx_cfg_l.bits.align = CFGRX_ALIGN_EN; 1553 rx_cfg_l.bits.los = CFGRX_LOS_LOTHRES; 1554 1555 if (portn == 0) { 1556 /* 0x8 */ 1557 rx_cfg_h.bits.eq = CFGRX_EQ_ADAPTIVE_LP_ADAPTIVE_ZF; 1558 } 1559 1560 /* Initialize PLL for 1G */ 1561 pll_cfg_l.bits.mpy = CFGPLL_MPY_8X; 1562 pll_cfg_l.bits.enpll = 1; 1563 pll_sts_l.bits.enpll = 1; 1564 if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR, 1565 ESR_N2_PLL_CFG_L_REG, pll_cfg_l.value)) != NXGE_OK) 1566 goto fail; 1567 1568 if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR, 1569 ESR_N2_PLL_STS_L_REG, pll_sts_l.value)) != NXGE_OK) 1570 goto fail; 1571 1572 #ifdef NXGE_DEBUG 1573 nxge_mdio_read(nxgep, portn, ESR_N2_DEV_ADDR, 1574 ESR_N2_PLL_CFG_L_REG, &cfg.value); 1575 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1576 "==> nxge_n2_serdes_init port<%d>: PLL cfg.l 0x%x (0x%x)", 1577 portn, pll_cfg_l.value, cfg.value)); 1578 1579 nxge_mdio_read(nxgep, portn, ESR_N2_DEV_ADDR, 1580 ESR_N2_PLL_STS_L_REG, &cfg.value); 1581 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1582 "==> nxge_n2_serdes_init port<%d>: PLL sts.l 0x%x (0x%x)", 1583 portn, pll_sts_l.value, cfg.value)); 1584 #endif 1585 1586 /* Set loopback mode if necessary */ 1587 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000) { 1588 tx_cfg_l.bits.entest = 1; 1589 rx_cfg_l.bits.entest = 1; 1590 test_cfg.bits.loopback = TESTCFG_INNER_CML_DIS_LOOPBACK; 1591 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1592 "==> nxge_n2_serdes_init port<%d>: loopback 0x%x", 1593 portn, test_cfg.value)); 1594 if ((status = nxge_mdio_write(nxgep, portn, 1595 ESR_N2_DEV_ADDR, 1596 ESR_N2_TEST_CFG_REG, test_cfg.value)) != NXGE_OK) { 1597 goto fail; 1598 } 1599 } 1600 } else { 1601 goto fail; 1602 } 1603 1604 /* MIF_REG_WR(handle, MIF_MASK_REG, ~mask); */ 1605 1606 NXGE_DELAY(20); 1607 1608 /* init TX channels */ 1609 for (chan = 0; chan < 4; chan++) { 1610 if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR, 1611 ESR_N2_TX_CFG_L_REG_ADDR(chan), tx_cfg_l.value)) != NXGE_OK) 1612 goto fail; 1613 1614 if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR, 1615 ESR_N2_TX_CFG_H_REG_ADDR(chan), tx_cfg_h.value)) != NXGE_OK) 1616 goto fail; 1617 1618 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1619 "==> nxge_n2_serdes_init port<%d>: chan %d tx_cfg_l 0x%x", 1620 portn, chan, tx_cfg_l.value)); 1621 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1622 "==> nxge_n2_serdes_init port<%d>: chan %d tx_cfg_h 0x%x", 1623 portn, chan, tx_cfg_h.value)); 1624 } 1625 1626 /* init RX channels */ 1627 for (chan = 0; chan < 4; chan++) { 1628 if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR, 1629 ESR_N2_RX_CFG_L_REG_ADDR(chan), rx_cfg_l.value)) != NXGE_OK) 1630 goto fail; 1631 1632 if ((status = nxge_mdio_write(nxgep, portn, ESR_N2_DEV_ADDR, 1633 ESR_N2_RX_CFG_H_REG_ADDR(chan), rx_cfg_h.value)) != NXGE_OK) 1634 goto fail; 1635 1636 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1637 "==> nxge_n2_serdes_init port<%d>: chan %d rx_cfg_l 0x%x", 1638 portn, chan, rx_cfg_l.value)); 1639 1640 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1641 "==> nxge_n2_serdes_init port<%d>: chan %d rx_cfg_h 0x%x", 1642 portn, chan, rx_cfg_h.value)); 1643 } 1644 1645 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_n2_serdes_init port<%d>", 1646 portn)); 1647 1648 return (NXGE_OK); 1649 fail: 1650 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1651 "nxge_n2_serdes_init: Failed to initialize N2 serdes for port<%d>", 1652 portn)); 1653 1654 return (status); 1655 } 1656 1657 /* Initialize the Neptune Internal Serdes for 10G (Neptune only) */ 1658 1659 static nxge_status_t 1660 nxge_neptune_10G_serdes_init(p_nxge_t nxgep) 1661 { 1662 npi_handle_t handle; 1663 uint8_t portn; 1664 int chan, i; 1665 sr_rx_tx_ctrl_l_t rx_tx_ctrl_l; 1666 sr_rx_tx_ctrl_h_t rx_tx_ctrl_h; 1667 sr_glue_ctrl0_l_t glue_ctrl0_l; 1668 sr_glue_ctrl0_h_t glue_ctrl0_h; 1669 uint64_t val; 1670 uint16_t val16l; 1671 uint16_t val16h; 1672 nxge_status_t status = NXGE_OK; 1673 1674 portn = nxgep->mac.portnum; 1675 1676 if ((portn != 0) && (portn != 1)) 1677 return (NXGE_OK); 1678 1679 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1680 "==> nxge_neptune_10G_serdes_init port<%d>", portn)); 1681 handle = nxgep->npi_handle; 1682 switch (portn) { 1683 case 0: 1684 /* Reset Serdes */ 1685 ESR_REG_WR(handle, ESR_RESET_REG, ESR_RESET_0); 1686 NXGE_DELAY(20); 1687 ESR_REG_WR(handle, ESR_RESET_REG, 0x0); 1688 NXGE_DELAY(2000); 1689 1690 /* Configure Serdes to 10G mode */ 1691 ESR_REG_WR(handle, ESR_0_PLL_CONFIG_REG, 1692 ESR_PLL_CFG_10G_SERDES); 1693 1694 ESR_REG_WR(handle, ESR_0_CONTROL_REG, 1695 ESR_CTL_EN_SYNCDET_0 | ESR_CTL_EN_SYNCDET_1 | 1696 ESR_CTL_EN_SYNCDET_2 | ESR_CTL_EN_SYNCDET_3 | 1697 (0x5 << ESR_CTL_OUT_EMPH_0_SHIFT) | 1698 (0x5 << ESR_CTL_OUT_EMPH_1_SHIFT) | 1699 (0x5 << ESR_CTL_OUT_EMPH_2_SHIFT) | 1700 (0x5 << ESR_CTL_OUT_EMPH_3_SHIFT) | 1701 (0x5 << ESR_CTL_OUT_EMPH_3_SHIFT) | 1702 (0x1 << ESR_CTL_LOSADJ_0_SHIFT) | 1703 (0x1 << ESR_CTL_LOSADJ_1_SHIFT) | 1704 (0x1 << ESR_CTL_LOSADJ_2_SHIFT) | 1705 (0x1 << ESR_CTL_LOSADJ_3_SHIFT)); 1706 1707 /* Set Serdes0 Internal Loopback if necessary */ 1708 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g) { 1709 ESR_REG_WR(handle, 1710 ESR_0_TEST_CONFIG_REG, 1711 ESR_PAD_LOOPBACK_CH3 | 1712 ESR_PAD_LOOPBACK_CH2 | 1713 ESR_PAD_LOOPBACK_CH1 | 1714 ESR_PAD_LOOPBACK_CH0); 1715 } else { 1716 ESR_REG_WR(handle, ESR_0_TEST_CONFIG_REG, 0); 1717 } 1718 break; 1719 case 1: 1720 /* Reset Serdes */ 1721 ESR_REG_WR(handle, ESR_RESET_REG, ESR_RESET_1); 1722 NXGE_DELAY(20); 1723 ESR_REG_WR(handle, ESR_RESET_REG, 0x0); 1724 NXGE_DELAY(2000); 1725 1726 /* Configure Serdes to 10G mode */ 1727 ESR_REG_WR(handle, ESR_1_PLL_CONFIG_REG, 1728 ESR_PLL_CFG_10G_SERDES); 1729 1730 ESR_REG_WR(handle, ESR_1_CONTROL_REG, 1731 ESR_CTL_EN_SYNCDET_0 | ESR_CTL_EN_SYNCDET_1 | 1732 ESR_CTL_EN_SYNCDET_2 | ESR_CTL_EN_SYNCDET_3 | 1733 (0x5 << ESR_CTL_OUT_EMPH_0_SHIFT) | 1734 (0x5 << ESR_CTL_OUT_EMPH_1_SHIFT) | 1735 (0x5 << ESR_CTL_OUT_EMPH_2_SHIFT) | 1736 (0x5 << ESR_CTL_OUT_EMPH_3_SHIFT) | 1737 (0x5 << ESR_CTL_OUT_EMPH_3_SHIFT) | 1738 (0x1 << ESR_CTL_LOSADJ_0_SHIFT) | 1739 (0x1 << ESR_CTL_LOSADJ_1_SHIFT) | 1740 (0x1 << ESR_CTL_LOSADJ_2_SHIFT) | 1741 (0x1 << ESR_CTL_LOSADJ_3_SHIFT)); 1742 1743 /* Set Serdes1 Internal Loopback if necessary */ 1744 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g) { 1745 ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG, 1746 ESR_PAD_LOOPBACK_CH3 | ESR_PAD_LOOPBACK_CH2 | 1747 ESR_PAD_LOOPBACK_CH1 | ESR_PAD_LOOPBACK_CH0); 1748 } else { 1749 ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG, 0); 1750 } 1751 break; 1752 default: 1753 /* Nothing to do here */ 1754 goto done; 1755 } 1756 1757 /* init TX RX channels */ 1758 for (chan = 0; chan < 4; chan++) { 1759 if ((status = nxge_mdio_read(nxgep, portn, 1760 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_L_ADDR(chan), 1761 &rx_tx_ctrl_l.value)) != NXGE_OK) 1762 goto fail; 1763 if ((status = nxge_mdio_read(nxgep, portn, 1764 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_H_ADDR(chan), 1765 &rx_tx_ctrl_h.value)) != NXGE_OK) 1766 goto fail; 1767 if ((status = nxge_mdio_read(nxgep, portn, 1768 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_L_ADDR(chan), 1769 &glue_ctrl0_l.value)) != NXGE_OK) 1770 goto fail; 1771 if ((status = nxge_mdio_read(nxgep, portn, 1772 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_H_ADDR(chan), 1773 &glue_ctrl0_h.value)) != NXGE_OK) 1774 goto fail; 1775 rx_tx_ctrl_l.bits.enstretch = 1; 1776 rx_tx_ctrl_h.bits.vmuxlo = 2; 1777 rx_tx_ctrl_h.bits.vpulselo = 2; 1778 glue_ctrl0_l.bits.rxlosenable = 1; 1779 glue_ctrl0_l.bits.samplerate = 0xF; 1780 glue_ctrl0_l.bits.thresholdcount = 0xFF; 1781 glue_ctrl0_h.bits.bitlocktime = BITLOCKTIME_300_CYCLES; 1782 if ((status = nxge_mdio_write(nxgep, portn, 1783 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_L_ADDR(chan), 1784 rx_tx_ctrl_l.value)) != NXGE_OK) 1785 goto fail; 1786 if ((status = nxge_mdio_write(nxgep, portn, 1787 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_H_ADDR(chan), 1788 rx_tx_ctrl_h.value)) != NXGE_OK) 1789 goto fail; 1790 if ((status = nxge_mdio_write(nxgep, portn, 1791 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_L_ADDR(chan), 1792 glue_ctrl0_l.value)) != NXGE_OK) 1793 goto fail; 1794 if ((status = nxge_mdio_write(nxgep, portn, 1795 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_H_ADDR(chan), 1796 glue_ctrl0_h.value)) != NXGE_OK) 1797 goto fail; 1798 } 1799 1800 /* Apply Tx core reset */ 1801 if ((status = nxge_mdio_write(nxgep, portn, 1802 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR(), 1803 (uint16_t)0)) != NXGE_OK) 1804 goto fail; 1805 1806 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 1807 ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR(), (uint16_t)0xffff)) != 1808 NXGE_OK) 1809 goto fail; 1810 1811 NXGE_DELAY(200); 1812 1813 /* Apply Rx core reset */ 1814 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 1815 ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR(), (uint16_t)0xffff)) != 1816 NXGE_OK) 1817 goto fail; 1818 1819 NXGE_DELAY(200); 1820 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 1821 ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR(), (uint16_t)0)) != NXGE_OK) 1822 goto fail; 1823 1824 NXGE_DELAY(200); 1825 if ((status = nxge_mdio_read(nxgep, portn, 1826 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR(), 1827 &val16l)) != NXGE_OK) 1828 goto fail; 1829 if ((status = nxge_mdio_read(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 1830 ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR(), &val16h)) != NXGE_OK) 1831 goto fail; 1832 if ((val16l != 0) || (val16h != 0)) { 1833 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1834 "Failed to reset port<%d> XAUI Serdes " 1835 "(val16l 0x%x val16h 0x%x)", 1836 portn, val16l, val16h)); 1837 } 1838 1839 if (portn == 0) { 1840 /* Wait for serdes to be ready */ 1841 for (i = 0; i < MAX_SERDES_RDY_RETRIES; i++) { 1842 ESR_REG_RD(handle, ESR_INTERNAL_SIGNALS_REG, &val); 1843 if ((val & ESR_SIG_P0_BITS_MASK) != 1844 (ESR_SIG_SERDES_RDY0_P0 | ESR_SIG_DETECT0_P0 | 1845 ESR_SIG_XSERDES_RDY_P0 | 1846 ESR_SIG_XDETECT_P0_CH3 | 1847 ESR_SIG_XDETECT_P0_CH2 | 1848 ESR_SIG_XDETECT_P0_CH1 | 1849 ESR_SIG_XDETECT_P0_CH0)) 1850 1851 NXGE_DELAY(SERDES_RDY_WT_INTERVAL); 1852 else 1853 break; 1854 } 1855 1856 if (i == MAX_SERDES_RDY_RETRIES) { 1857 /* 1858 * RDY signal stays low may due to the absent of the 1859 * external PHY, it is not an error condition. But still 1860 * print the message for the debugging purpose when link 1861 * stays down 1862 */ 1863 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1864 "nxge_neptune_10G_serdes_init: " 1865 "Serdes/signal for port<%d> not ready", portn)); 1866 goto done; 1867 } 1868 } else if (portn == 1) { 1869 /* Wait for serdes to be ready */ 1870 for (i = 0; i < MAX_SERDES_RDY_RETRIES; i++) { 1871 ESR_REG_RD(handle, ESR_INTERNAL_SIGNALS_REG, &val); 1872 if ((val & ESR_SIG_P1_BITS_MASK) != 1873 (ESR_SIG_SERDES_RDY0_P1 | ESR_SIG_DETECT0_P1 | 1874 ESR_SIG_XSERDES_RDY_P1 | 1875 ESR_SIG_XDETECT_P1_CH3 | 1876 ESR_SIG_XDETECT_P1_CH2 | 1877 ESR_SIG_XDETECT_P1_CH1 | 1878 ESR_SIG_XDETECT_P1_CH0)) 1879 1880 NXGE_DELAY(SERDES_RDY_WT_INTERVAL); 1881 else 1882 break; 1883 } 1884 1885 if (i == MAX_SERDES_RDY_RETRIES) { 1886 /* 1887 * RDY signal stays low may due to the absent of the 1888 * external PHY, it is not an error condition. But still 1889 * print the message for the debugging purpose when link 1890 * stays down 1891 */ 1892 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1893 "nxge_neptune_10G_serdes_init: " 1894 "Serdes/signal for port<%d> not ready", portn)); 1895 goto done; 1896 } 1897 } 1898 1899 done: 1900 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1901 "<== nxge_neptune_10G_serdes_init port<%d>", portn)); 1902 1903 return (NXGE_OK); 1904 fail: 1905 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1906 "nxge_neptune_10G_serdes_init: " 1907 "Failed to initialize Neptune serdes for port<%d>", portn)); 1908 1909 return (status); 1910 } 1911 1912 /* Initialize Neptune Internal Serdes for 1G (Neptune only) */ 1913 1914 static nxge_status_t 1915 nxge_1G_serdes_init(p_nxge_t nxgep) 1916 { 1917 npi_handle_t handle; 1918 uint8_t portn; 1919 int chan; 1920 sr_rx_tx_ctrl_l_t rx_tx_ctrl_l; 1921 sr_rx_tx_ctrl_h_t rx_tx_ctrl_h; 1922 sr_glue_ctrl0_l_t glue_ctrl0_l; 1923 sr_glue_ctrl0_h_t glue_ctrl0_h; 1924 uint64_t val; 1925 uint16_t val16l; 1926 uint16_t val16h; 1927 nxge_status_t status = NXGE_OK; 1928 1929 portn = nxgep->mac.portnum; 1930 1931 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 1932 "==> nxge_1G_serdes_init port<%d>", portn)); 1933 1934 handle = nxgep->npi_handle; 1935 1936 switch (portn) { 1937 case 0: 1938 /* Assert the reset register */ 1939 ESR_REG_RD(handle, ESR_RESET_REG, &val); 1940 val |= ESR_RESET_0; 1941 ESR_REG_WR(handle, ESR_RESET_REG, val); 1942 1943 /* Set the PLL register to 0x79 */ 1944 ESR_REG_WR(handle, ESR_0_PLL_CONFIG_REG, 1945 ESR_PLL_CFG_1G_SERDES); 1946 1947 /* Set the control register to 0x249249f */ 1948 ESR_REG_WR(handle, ESR_0_CONTROL_REG, ESR_CTL_1G_SERDES); 1949 1950 /* Set Serdes0 Internal Loopback if necessary */ 1951 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000) { 1952 /* Set pad loopback modes 0xaa */ 1953 ESR_REG_WR(handle, ESR_0_TEST_CONFIG_REG, 1954 ESR_TSTCFG_LBTEST_PAD); 1955 } else { 1956 ESR_REG_WR(handle, ESR_0_TEST_CONFIG_REG, 0); 1957 } 1958 1959 /* Deassert the reset register */ 1960 ESR_REG_RD(handle, ESR_RESET_REG, &val); 1961 val &= ~ESR_RESET_0; 1962 ESR_REG_WR(handle, ESR_RESET_REG, val); 1963 break; 1964 1965 case 1: 1966 /* Assert the reset register */ 1967 ESR_REG_RD(handle, ESR_RESET_REG, &val); 1968 val |= ESR_RESET_1; 1969 ESR_REG_WR(handle, ESR_RESET_REG, val); 1970 1971 /* Set PLL register to 0x79 */ 1972 ESR_REG_WR(handle, ESR_1_PLL_CONFIG_REG, 1973 ESR_PLL_CFG_1G_SERDES); 1974 1975 /* Set the control register to 0x249249f */ 1976 ESR_REG_WR(handle, ESR_1_CONTROL_REG, ESR_CTL_1G_SERDES); 1977 1978 /* Set Serdes1 Internal Loopback if necessary */ 1979 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000) { 1980 /* Set pad loopback mode 0xaa */ 1981 ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG, 1982 ESR_TSTCFG_LBTEST_PAD); 1983 } else { 1984 ESR_REG_WR(handle, ESR_1_TEST_CONFIG_REG, 0); 1985 } 1986 1987 /* Deassert the reset register */ 1988 ESR_REG_RD(handle, ESR_RESET_REG, &val); 1989 val &= ~ESR_RESET_1; 1990 ESR_REG_WR(handle, ESR_RESET_REG, val); 1991 break; 1992 1993 default: 1994 /* Nothing to do here */ 1995 goto done; 1996 } 1997 1998 /* init TX RX channels */ 1999 for (chan = 0; chan < 4; chan++) { 2000 if ((status = nxge_mdio_read(nxgep, portn, 2001 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_L_ADDR(chan), 2002 &rx_tx_ctrl_l.value)) != NXGE_OK) { 2003 goto fail; 2004 } 2005 if ((status = nxge_mdio_read(nxgep, portn, 2006 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_H_ADDR(chan), 2007 &rx_tx_ctrl_h.value)) != NXGE_OK) { 2008 goto fail; 2009 } 2010 if ((status = nxge_mdio_read(nxgep, portn, 2011 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_L_ADDR(chan), 2012 &glue_ctrl0_l.value)) != NXGE_OK) { 2013 goto fail; 2014 } 2015 if ((status = nxge_mdio_read(nxgep, portn, 2016 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_H_ADDR(chan), 2017 &glue_ctrl0_h.value)) != NXGE_OK) { 2018 goto fail; 2019 } 2020 2021 rx_tx_ctrl_l.bits.enstretch = 1; 2022 rx_tx_ctrl_h.bits.vmuxlo = 2; 2023 rx_tx_ctrl_h.bits.vpulselo = 2; 2024 glue_ctrl0_l.bits.rxlosenable = 1; 2025 glue_ctrl0_l.bits.samplerate = 0xF; 2026 glue_ctrl0_l.bits.thresholdcount = 0xFF; 2027 glue_ctrl0_h.bits.bitlocktime = BITLOCKTIME_300_CYCLES; 2028 if ((status = nxge_mdio_write(nxgep, portn, 2029 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_L_ADDR(chan), 2030 rx_tx_ctrl_l.value)) != NXGE_OK) { 2031 goto fail; 2032 } 2033 if ((status = nxge_mdio_write(nxgep, portn, 2034 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_RX_TX_CONTROL_H_ADDR(chan), 2035 rx_tx_ctrl_h.value)) != NXGE_OK) { 2036 goto fail; 2037 } 2038 if ((status = nxge_mdio_write(nxgep, portn, 2039 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_L_ADDR(chan), 2040 glue_ctrl0_l.value)) != NXGE_OK) { 2041 goto fail; 2042 } 2043 if ((status = nxge_mdio_write(nxgep, portn, 2044 ESR_NEPTUNE_DEV_ADDR, ESR_NEP_GLUE_CONTROL0_H_ADDR(chan), 2045 glue_ctrl0_h.value)) != NXGE_OK) { 2046 goto fail; 2047 } 2048 } 2049 2050 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2051 ESR_NEP_RX_POWER_CONTROL_L_ADDR(), 0xfff)) != NXGE_OK) { 2052 goto fail; 2053 } 2054 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2055 ESR_NEP_RX_POWER_CONTROL_H_ADDR(), 0xfff)) != NXGE_OK) { 2056 goto fail; 2057 } 2058 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2059 ESR_NEP_TX_POWER_CONTROL_L_ADDR(), 0x70)) != NXGE_OK) { 2060 goto fail; 2061 } 2062 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2063 ESR_NEP_TX_POWER_CONTROL_H_ADDR(), 0xfff)) != NXGE_OK) { 2064 goto fail; 2065 } 2066 2067 /* Apply Tx core reset */ 2068 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2069 ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR(), (uint16_t)0)) != NXGE_OK) { 2070 goto fail; 2071 } 2072 2073 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2074 ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR(), (uint16_t)0xffff)) != 2075 NXGE_OK) { 2076 goto fail; 2077 } 2078 2079 NXGE_DELAY(200); 2080 2081 /* Apply Rx core reset */ 2082 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2083 ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR(), (uint16_t)0xffff)) != 2084 NXGE_OK) { 2085 goto fail; 2086 } 2087 2088 NXGE_DELAY(200); 2089 if ((status = nxge_mdio_write(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2090 ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR(), (uint16_t)0)) != NXGE_OK) { 2091 goto fail; 2092 } 2093 2094 NXGE_DELAY(200); 2095 if ((status = nxge_mdio_read(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2096 ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR(), &val16l)) != NXGE_OK) { 2097 goto fail; 2098 } 2099 if ((status = nxge_mdio_read(nxgep, portn, ESR_NEPTUNE_DEV_ADDR, 2100 ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR(), &val16h)) != NXGE_OK) { 2101 goto fail; 2102 } 2103 if ((val16l != 0) || (val16h != 0)) { 2104 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2105 "Failed to reset port<%d> XAUI Serdes " 2106 "(val16l 0x%x val16h 0x%x)", portn, val16l, val16h)); 2107 status = NXGE_ERROR; 2108 goto fail; 2109 } 2110 2111 NXGE_DELAY(200); 2112 ESR_REG_RD(handle, ESR_INTERNAL_SIGNALS_REG, &val); 2113 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2114 "nxge_neptune_serdes_init: read internal signal reg port<%d> " 2115 "val 0x%x", portn, val)); 2116 if (portn == 0) { 2117 if ((val & ESR_SIG_P0_BITS_MASK_1G) != 2118 (ESR_SIG_SERDES_RDY0_P0 | ESR_SIG_DETECT0_P0)) { 2119 /* 2120 * RDY signal stays low may due to the absent of the 2121 * external PHY, it is not an error condition. But still 2122 * print the message for the debugging purpose when link 2123 * stays down 2124 */ 2125 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2126 "nxge_neptune_1G_serdes_init: " 2127 "Serdes/signal for port<%d> not ready", portn)); 2128 goto done; 2129 } 2130 } else if (portn == 1) { 2131 if ((val & ESR_SIG_P1_BITS_MASK_1G) != 2132 (ESR_SIG_SERDES_RDY0_P1 | ESR_SIG_DETECT0_P1)) { 2133 /* 2134 * RDY signal stays low may due to the absent of the 2135 * external PHY, it is not an error condition. But still 2136 * print the message for the debugging purpose when link 2137 * stays down 2138 */ 2139 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2140 "nxge_neptune_1G_serdes_init: " 2141 "Serdes/signal for port<%d> not ready", portn)); 2142 goto done; 2143 2144 } 2145 } 2146 done: 2147 2148 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2149 "<== nxge_1G_serdes_init port<%d>", portn)); 2150 return (NXGE_OK); 2151 fail: 2152 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2153 "nxge_1G_serdes_init: " 2154 "Failed to initialize Neptune serdes for port<%d>", 2155 portn)); 2156 2157 return (status); 2158 } 2159 2160 /* Initialize the BCM 8704 xcvr */ 2161 2162 static nxge_status_t 2163 nxge_BCM8704_xcvr_init(p_nxge_t nxgep) 2164 { 2165 uint16_t val; 2166 #ifdef NXGE_DEBUG 2167 uint8_t portn; 2168 uint16_t val1; 2169 #endif 2170 uint8_t phy_port_addr; 2171 pmd_tx_control_t tx_ctl; 2172 control_t ctl; 2173 phyxs_control_t phyxs_ctl; 2174 pcs_control_t pcs_ctl; 2175 uint32_t delay = 0; 2176 optics_dcntr_t op_ctr; 2177 nxge_status_t status = NXGE_OK; 2178 #ifdef NXGE_DEBUG 2179 portn = nxgep->mac.portnum; 2180 #endif 2181 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_BCM8704_xcvr_init: port<%d>", 2182 portn)); 2183 2184 phy_port_addr = nxgep->statsp->mac_stats.xcvr_portn; 2185 2186 /* Reset the transceiver */ 2187 if ((status = nxge_mdio_read(nxgep, phy_port_addr, BCM8704_PHYXS_ADDR, 2188 BCM8704_PHYXS_CONTROL_REG, &phyxs_ctl.value)) != NXGE_OK) 2189 goto fail; 2190 2191 phyxs_ctl.bits.reset = 1; 2192 if ((status = nxge_mdio_write(nxgep, phy_port_addr, BCM8704_PHYXS_ADDR, 2193 BCM8704_PHYXS_CONTROL_REG, phyxs_ctl.value)) != NXGE_OK) 2194 goto fail; 2195 2196 do { 2197 drv_usecwait(500); 2198 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2199 BCM8704_PHYXS_ADDR, BCM8704_PHYXS_CONTROL_REG, 2200 &phyxs_ctl.value)) != NXGE_OK) 2201 goto fail; 2202 delay++; 2203 } while ((phyxs_ctl.bits.reset) && (delay < 100)); 2204 if (delay == 100) { 2205 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_xcvr_init: " 2206 "failed to reset Transceiver on port<%d>", portn)); 2207 status = NXGE_ERROR; 2208 goto fail; 2209 } 2210 2211 /* Set to 0x7FBF */ 2212 ctl.value = 0; 2213 ctl.bits.res1 = 0x3F; 2214 ctl.bits.optxon_lvl = 1; 2215 ctl.bits.oprxflt_lvl = 1; 2216 ctl.bits.optrxlos_lvl = 1; 2217 ctl.bits.optxflt_lvl = 1; 2218 ctl.bits.opprflt_lvl = 1; 2219 ctl.bits.obtmpflt_lvl = 1; 2220 ctl.bits.opbiasflt_lvl = 1; 2221 ctl.bits.optxrst_lvl = 1; 2222 if ((status = nxge_mdio_write(nxgep, phy_port_addr, 2223 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL_REG, ctl.value)) 2224 != NXGE_OK) 2225 goto fail; 2226 2227 /* Set to 0x164 */ 2228 tx_ctl.value = 0; 2229 tx_ctl.bits.tsck_lpwren = 1; 2230 tx_ctl.bits.tx_dac_txck = 0x2; 2231 tx_ctl.bits.tx_dac_txd = 0x1; 2232 tx_ctl.bits.xfp_clken = 1; 2233 if ((status = nxge_mdio_write(nxgep, phy_port_addr, 2234 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL_REG, 2235 tx_ctl.value)) != NXGE_OK) 2236 goto fail; 2237 /* 2238 * According to Broadcom's instruction, SW needs to read 2239 * back these registers twice after written. 2240 */ 2241 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2242 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL_REG, &val)) 2243 != NXGE_OK) 2244 goto fail; 2245 2246 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2247 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL_REG, &val)) 2248 != NXGE_OK) 2249 goto fail; 2250 2251 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2252 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL_REG, &val)) 2253 != NXGE_OK) 2254 goto fail; 2255 2256 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2257 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL_REG, &val)) 2258 != NXGE_OK) 2259 goto fail; 2260 2261 /* Enable Tx and Rx LEDs to be driven by traffic */ 2262 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2263 BCM8704_USER_DEV3_ADDR, BCM8704_USER_OPTICS_DIGITAL_CTRL_REG, 2264 &op_ctr.value)) != NXGE_OK) 2265 goto fail; 2266 if (NXGE_IS_XAUI_PLATFORM(nxgep)) { 2267 op_ctr.bits.gpio_sel = 0x1; 2268 } else { 2269 op_ctr.bits.gpio_sel = 0x3; 2270 } 2271 if ((status = nxge_mdio_write(nxgep, phy_port_addr, 2272 BCM8704_USER_DEV3_ADDR, BCM8704_USER_OPTICS_DIGITAL_CTRL_REG, 2273 op_ctr.value)) != NXGE_OK) 2274 goto fail; 2275 2276 NXGE_DELAY(1000000); 2277 2278 /* Set BCM8704 Internal Loopback mode if necessary */ 2279 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2280 BCM8704_PCS_DEV_ADDR, BCM8704_PCS_CONTROL_REG, &pcs_ctl.value)) 2281 != NXGE_OK) 2282 goto fail; 2283 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) 2284 pcs_ctl.bits.loopback = 1; 2285 else 2286 pcs_ctl.bits.loopback = 0; 2287 if ((status = nxge_mdio_write(nxgep, phy_port_addr, 2288 BCM8704_PCS_DEV_ADDR, BCM8704_PCS_CONTROL_REG, pcs_ctl.value)) 2289 != NXGE_OK) 2290 goto fail; 2291 2292 status = nxge_mdio_read(nxgep, phy_port_addr, 0x1, 0xA, &val); 2293 if (status != NXGE_OK) 2294 goto fail; 2295 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2296 "BCM8704 port<%d> Dev 1 Reg 0xA = 0x%x\n", portn, val)); 2297 status = nxge_mdio_read(nxgep, phy_port_addr, 0x3, 0x20, &val); 2298 if (status != NXGE_OK) 2299 goto fail; 2300 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2301 "BCM8704 port<%d> Dev 3 Reg 0x20 = 0x%x\n", portn, val)); 2302 status = nxge_mdio_read(nxgep, phy_port_addr, 0x4, 0x18, &val); 2303 if (status != NXGE_OK) 2304 goto fail; 2305 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2306 "BCM8704 port<%d> Dev 4 Reg 0x18 = 0x%x\n", portn, val)); 2307 2308 #ifdef NXGE_DEBUG 2309 /* Diagnose link issue if link is not up */ 2310 status = nxge_mdio_read(nxgep, phy_port_addr, BCM8704_USER_DEV3_ADDR, 2311 BCM8704_USER_ANALOG_STATUS0_REG, 2312 &val); 2313 if (status != NXGE_OK) 2314 goto fail; 2315 2316 status = nxge_mdio_read(nxgep, phy_port_addr, 2317 BCM8704_USER_DEV3_ADDR, BCM8704_USER_ANALOG_STATUS0_REG, &val); 2318 if (status != NXGE_OK) 2319 goto fail; 2320 2321 status = nxge_mdio_read(nxgep, phy_port_addr, 2322 BCM8704_USER_DEV3_ADDR, BCM8704_USER_TX_ALARM_STATUS_REG, &val1); 2323 if (status != NXGE_OK) 2324 goto fail; 2325 2326 status = nxge_mdio_read(nxgep, phy_port_addr, 2327 BCM8704_USER_DEV3_ADDR, BCM8704_USER_TX_ALARM_STATUS_REG, &val1); 2328 if (status != NXGE_OK) 2329 goto fail; 2330 2331 if (val != 0x3FC) { 2332 if ((val == 0x43BC) && (val1 != 0)) { 2333 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2334 "Cable not connected to peer or bad" 2335 " cable on port<%d>\n", portn)); 2336 } else if (val == 0x639C) { 2337 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2338 "Optical module (XFP) is bad or absent" 2339 " on port<%d>\n", portn)); 2340 } 2341 } 2342 #endif 2343 2344 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_BCM8704_xcvr_init: port<%d>", 2345 portn)); 2346 return (NXGE_OK); 2347 2348 fail: 2349 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2350 "nxge_BCM8704_xcvr_init: failed to initialize transceiver for " 2351 "port<%d>", nxgep->mac.portnum)); 2352 return (NXGE_ERROR); 2353 } 2354 2355 /* Initialize the BCM 8706 Transceiver */ 2356 2357 static nxge_status_t 2358 nxge_BCM8706_xcvr_init(p_nxge_t nxgep) 2359 { 2360 uint8_t phy_port_addr; 2361 phyxs_control_t phyxs_ctl; 2362 pcs_control_t pcs_ctl; 2363 uint32_t delay = 0; 2364 optics_dcntr_t op_ctr; 2365 nxge_status_t status = NXGE_OK; 2366 #ifdef NXGE_DEBUG 2367 uint8_t portn = nxgep->mac.portnum; 2368 #endif 2369 2370 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_BCM8706_xcvr_init: port<%d>", 2371 portn)); 2372 2373 phy_port_addr = nxgep->statsp->mac_stats.xcvr_portn; 2374 2375 /* Reset the transceiver */ 2376 if ((status = nxge_mdio_read(nxgep, phy_port_addr, BCM8704_PHYXS_ADDR, 2377 BCM8704_PHYXS_CONTROL_REG, &phyxs_ctl.value)) != NXGE_OK) 2378 goto fail; 2379 2380 phyxs_ctl.bits.reset = 1; 2381 if ((status = nxge_mdio_write(nxgep, phy_port_addr, BCM8704_PHYXS_ADDR, 2382 BCM8704_PHYXS_CONTROL_REG, phyxs_ctl.value)) != NXGE_OK) 2383 goto fail; 2384 do { 2385 drv_usecwait(500); 2386 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2387 BCM8704_PHYXS_ADDR, BCM8704_PHYXS_CONTROL_REG, 2388 &phyxs_ctl.value)) != NXGE_OK) 2389 goto fail; 2390 delay++; 2391 } while ((phyxs_ctl.bits.reset) && (delay < 100)); 2392 2393 if (delay == 100) { 2394 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_xcvr_init: " 2395 "failed to reset Transceiver on port<%d>", portn)); 2396 status = NXGE_ERROR; 2397 goto fail; 2398 } 2399 2400 NXGE_DELAY(1000000); 2401 2402 /* Set BCM8706 Internal Loopback mode if necessary */ 2403 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2404 BCM8704_PCS_DEV_ADDR, BCM8704_PCS_CONTROL_REG, &pcs_ctl.value)) 2405 != NXGE_OK) 2406 goto fail; 2407 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) 2408 pcs_ctl.bits.loopback = 1; 2409 else 2410 pcs_ctl.bits.loopback = 0; 2411 if ((status = nxge_mdio_write(nxgep, phy_port_addr, 2412 BCM8704_PCS_DEV_ADDR, BCM8704_PCS_CONTROL_REG, pcs_ctl.value)) 2413 != NXGE_OK) 2414 goto fail; 2415 2416 /* Enable Tx and Rx LEDs to be driven by traffic */ 2417 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2418 BCM8704_USER_DEV3_ADDR, BCM8704_USER_OPTICS_DIGITAL_CTRL_REG, 2419 &op_ctr.value)) != NXGE_OK) 2420 goto fail; 2421 op_ctr.bits.gpio_sel = 0x3; 2422 op_ctr.bits.res2 = 0x1; 2423 2424 if ((status = nxge_mdio_write(nxgep, phy_port_addr, 2425 BCM8704_USER_DEV3_ADDR, BCM8704_USER_OPTICS_DIGITAL_CTRL_REG, 2426 op_ctr.value)) != NXGE_OK) 2427 goto fail; 2428 2429 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_BCM8706_xcvr_init: port<%d>", 2430 portn)); 2431 return (NXGE_OK); 2432 2433 fail: 2434 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2435 "nxge_BCM8706_xcvr_init: failed to initialize transceiver for " 2436 "port<%d>", nxgep->mac.portnum)); 2437 return (status); 2438 } 2439 2440 #define CHK_STAT(x) status = (x); if (status != NXGE_OK) goto fail 2441 2442 #define MRVL88X2011_RD(nxgep, port, d, r, p) \ 2443 CHK_STAT(nxge_mdio_read(nxgep, port, d, r, p)) 2444 2445 #define MRVL88X2011_WR(nxgep, port, d, r, p) \ 2446 CHK_STAT(nxge_mdio_write(nxgep, port, d, r, p)) 2447 2448 2449 static void 2450 nxge_mrvl88x2011_led_blink_rate(p_nxge_t nxgep, uint16_t rate) 2451 { 2452 uint16_t value; 2453 uint8_t phy = nxgep->statsp->mac_stats.xcvr_portn; 2454 2455 if (nxge_mdio_read(nxgep, phy, MRVL_88X2011_USER_DEV2_ADDR, 2456 MRVL_88X2011_LED_BLINK_CTL, &value) == NXGE_OK) { 2457 value &= ~MRVL_88X2011_LED_BLK_MASK; 2458 value |= (rate << MRVL_88X2011_LED_BLK_SHIFT); 2459 (void) nxge_mdio_write(nxgep, phy, 2460 MRVL_88X2011_USER_DEV2_ADDR, MRVL_88X2011_LED_BLINK_CTL, 2461 value); 2462 } 2463 } 2464 2465 static nxge_status_t 2466 nxge_mrvl88x2011_setup_lb(p_nxge_t nxgep) 2467 { 2468 nxge_status_t status; 2469 pcs_control_t pcs_ctl; 2470 uint8_t phy = nxgep->statsp->mac_stats.xcvr_portn; 2471 2472 MRVL88X2011_RD(nxgep, phy, MRVL_88X2011_USER_DEV3_ADDR, 2473 MRVL_88X2011_PMA_PMD_CTL_1, &pcs_ctl.value); 2474 2475 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) 2476 pcs_ctl.bits.loopback = 1; 2477 else 2478 pcs_ctl.bits.loopback = 0; 2479 2480 MRVL88X2011_WR(nxgep, phy, MRVL_88X2011_USER_DEV3_ADDR, 2481 MRVL_88X2011_PMA_PMD_CTL_1, pcs_ctl.value); 2482 2483 fail: 2484 return (status); 2485 } 2486 2487 2488 static void 2489 nxge_mrvl88x2011_led(p_nxge_t nxgep, uint16_t val) 2490 { 2491 uint16_t val2; 2492 uint8_t phy = nxgep->statsp->mac_stats.xcvr_portn; 2493 2494 val2 = MRVL_88X2011_LED(MRVL_88X2011_LED_ACT, val); 2495 val2 &= ~MRVL_88X2011_LED(MRVL_88X2011_LED_ACT, 2496 MRVL_88X2011_LED_CTL_MASK); 2497 val2 |= MRVL_88X2011_LED(MRVL_88X2011_LED_ACT, val); 2498 2499 if (nxge_mdio_write(nxgep, phy, MRVL_88X2011_USER_DEV2_ADDR, 2500 MRVL_88X2011_LED_8_TO_11_CTL, val2) != NXGE_OK) { 2501 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2502 "nxge_mrvl88x2011_led: nxge_mdio_write failed!!")); 2503 } 2504 } 2505 2506 2507 static nxge_status_t 2508 nxge_mrvl88x2011_xcvr_init(p_nxge_t nxgep) 2509 { 2510 uint8_t phy; 2511 nxge_status_t status; 2512 uint16_t clk; 2513 2514 phy = nxgep->statsp->mac_stats.xcvr_portn; 2515 2516 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2517 "==> nxge_mrvl88x2011_xcvr_init: port<%d> addr<0x%x>", 2518 nxgep->mac.portnum, phy)); 2519 2520 /* Set LED functions */ 2521 nxge_mrvl88x2011_led_blink_rate(nxgep, MRVL_88X2011_LED_BLK134MS); 2522 /* PCS activity */ 2523 nxge_mrvl88x2011_led(nxgep, MRVL_88X2011_LED_ACT); 2524 2525 MRVL88X2011_RD(nxgep, phy, MRVL_88X2011_USER_DEV3_ADDR, 2526 MRVL_88X2011_GEN_CTL, &clk); 2527 clk |= MRVL_88X2011_ENA_XFPREFCLK; 2528 MRVL88X2011_WR(nxgep, phy, MRVL_88X2011_USER_DEV3_ADDR, 2529 MRVL_88X2011_GEN_CTL, clk); 2530 2531 /* Set internal loopback mode if necessary */ 2532 2533 CHK_STAT(nxge_mrvl88x2011_setup_lb(nxgep)); 2534 2535 /* Enable PMD */ 2536 MRVL88X2011_WR(nxgep, phy, MRVL_88X2011_USER_DEV1_ADDR, 2537 MRVL_88X2011_10G_PMD_TX_DIS, MRVL_88X2011_ENA_PMDTX); 2538 2539 NXGE_DEBUG_MSG((nxgep, MAC_CTL, " nxge_mrvl88x2011_reset: OK")); 2540 2541 fail: 2542 return (status); 2543 } 2544 2545 2546 2547 /* Initialize the 10G Transceiver */ 2548 2549 static nxge_status_t 2550 nxge_10G_xcvr_init(p_nxge_t nxgep) 2551 { 2552 p_nxge_stats_t statsp; 2553 p_nxge_param_t param_arr = nxgep->param_arr; 2554 nxge_status_t status = NXGE_OK; 2555 #ifdef NXGE_DEBUG 2556 uint8_t portn = nxgep->mac.portnum; 2557 #endif 2558 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_10G_xcvr_init: port<%d>", 2559 portn)); 2560 2561 statsp = nxgep->statsp; 2562 2563 if (nxgep->mac.portmode == PORT_10G_SERDES) { 2564 goto done; 2565 } 2566 2567 /* Disable Link LEDs */ 2568 if (nxge_10g_link_led_off(nxgep) != NXGE_OK) 2569 goto fail; 2570 2571 /* Set Clause 45 */ 2572 npi_mac_mif_set_indirect_mode(nxgep->npi_handle, B_TRUE); 2573 2574 switch (nxgep->chip_id) { 2575 case BCM8704_CHIP_ID: 2576 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_10G_xcvr_init: " 2577 "Chip ID 8704 [0x%x] for 10G xcvr", nxgep->chip_id)); 2578 status = nxge_BCM8704_xcvr_init(nxgep); 2579 break; 2580 case BCM8706_CHIP_ID: 2581 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_10G_xcvr_init: " 2582 "Chip ID 8706 [0x%x] for 10G xcvr", nxgep->chip_id)); 2583 status = nxge_BCM8706_xcvr_init(nxgep); 2584 break; 2585 case MRVL88X201X_CHIP_ID: 2586 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "nxge_10G_xcvr_init: " 2587 "Chip ID 8706 [0x%x] for 10G xcvr", nxgep->chip_id)); 2588 status = nxge_mrvl88x2011_xcvr_init(nxgep); 2589 break; 2590 default: 2591 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_xcvr_init: " 2592 "Unknown chip ID 0x%x for 10G xcvr addr[%d]", 2593 nxgep->chip_id, nxgep->statsp->mac_stats.xcvr_portn)); 2594 goto fail; 2595 } 2596 2597 if (status != NXGE_OK) { 2598 goto fail; 2599 } 2600 done: 2601 statsp->mac_stats.cap_10gfdx = 1; 2602 statsp->mac_stats.lp_cap_10gfdx = 1; 2603 statsp->mac_stats.adv_cap_asmpause = 2604 param_arr[param_anar_asmpause].value; 2605 statsp->mac_stats.adv_cap_pause = param_arr[param_anar_pause].value; 2606 2607 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_10G_xcvr_init: port<%d>", 2608 portn)); 2609 return (NXGE_OK); 2610 2611 fail: 2612 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2613 "nxge_10G_xcvr_init: failed to initialize transceiver for " 2614 "port<%d>", nxgep->mac.portnum)); 2615 return (NXGE_ERROR); 2616 } 2617 2618 /* Initialize the 1G copper (BCM 5464) Transceiver */ 2619 2620 static nxge_status_t 2621 nxge_1G_xcvr_init(p_nxge_t nxgep) 2622 { 2623 p_nxge_param_t param_arr = nxgep->param_arr; 2624 p_nxge_stats_t statsp = nxgep->statsp; 2625 nxge_status_t status = NXGE_OK; 2626 2627 if (nxgep->mac.portmode == PORT_1G_SERDES) { 2628 statsp->mac_stats.cap_1000fdx = 2629 param_arr[param_anar_1000fdx].value; 2630 goto done; 2631 } 2632 2633 /* Set Clause 22 */ 2634 npi_mac_mif_set_indirect_mode(nxgep->npi_handle, B_FALSE); 2635 2636 /* Set capability flags */ 2637 statsp->mac_stats.cap_1000fdx = param_arr[param_anar_1000fdx].value; 2638 if ((nxgep->mac.portmode == PORT_1G_COPPER) || 2639 (nxgep->mac.portmode == PORT_1G_FIBER)) { 2640 statsp->mac_stats.cap_100fdx = 2641 param_arr[param_anar_100fdx].value; 2642 statsp->mac_stats.cap_10fdx = 2643 param_arr[param_anar_10fdx].value; 2644 } 2645 2646 status = nxge_mii_xcvr_init(nxgep); 2647 done: 2648 return (status); 2649 } 2650 2651 /* 2652 * Although the Teranetics copper transceiver (TN1010) does not need 2653 * to be initialized by the driver for passing packets, this funtion 2654 * initializes the members of nxgep->statsp->mac_stats struct for 2655 * kstat based on the value of nxgep->statsp->ports_stats.lb_mode. 2656 * It also configures the TN1010 for PHY loopback to support SunVTS. 2657 * 2658 * TN1010 only has the option to disable advertisement for the 10G 2659 * mode. So we can set it to either Dual Mode or 1G Only mode but 2660 * can't set it to 10G Only mode. 2661 * 2662 * ndd -set command can set the following 6 speed/duplex related parameters. 2663 * 2664 * ---------------------------------------------------------------- 2665 * ndd -set /dev/nxgeX param n kstat nxge:X | grep param 2666 * ---------------------------------------------------------------- 2667 * adv_autoneg_cap kstat nxge:1 | grep adv_cap_autoneg 2668 * adv_10gfdx_cap 2669 * adv_1000fdx_cap kstat nxge:1 | grep adv_cap_1000fdx 2670 * adv_100fdx_cap kstat nxge:1 | grep adv_cap_100fdx 2671 * adv_10fdx_cap kstat nxge:1 | grep adv_cap_10fdx 2672 * adv_pause_cap kstat nxge:1 | grep adv_cap_pause 2673 * ---------------------------------------------------------------- 2674 */ 2675 static nxge_status_t 2676 nxge_tn1010_xcvr_init(p_nxge_t nxgep) 2677 { 2678 p_nxge_param_t param_arr; 2679 p_nxge_stats_t statsp; 2680 tn1010_pcs_ctrl_t tn1010_pcs_ctrl; 2681 uint16_t speed; 2682 uint8_t phy_port_addr; 2683 uint8_t portn = NXGE_GET_PORT_NUM(nxgep->function_num); 2684 int status = NXGE_OK; 2685 2686 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_1G_tn1010_xcvr_init")); 2687 2688 param_arr = nxgep->param_arr; 2689 statsp = nxgep->statsp; 2690 2691 /* 2692 * Initialize the xcvr statistics which are NOT controlled by ndd 2693 */ 2694 statsp->mac_stats.cap_autoneg = 1; /* TN1010 autoneg is always on */ 2695 statsp->mac_stats.cap_100T4 = 0; 2696 2697 /* 2698 * Read the TN1010 link speed and initialize capabilities kstat. Note 2699 * that function nxge_check_tn1010_link repeatedly invoked by the 2700 * timer will update link_speed real time. 2701 */ 2702 if (nxge_get_tn1010_speed(nxgep, &speed) != NXGE_OK) { 2703 goto fail; 2704 } 2705 if (speed == TN1010_SPEED_1G) { 2706 statsp->mac_stats.cap_10gfdx = 0; 2707 } else { 2708 statsp->mac_stats.cap_10gfdx = 1; 2709 } 2710 2711 /* Whether we are in 1G or 10G mode, we always have the 1G capability */ 2712 statsp->mac_stats.cap_1000fdx = 1; 2713 2714 /* TN1010 is not able to operate in the following states */ 2715 statsp->mac_stats.cap_1000hdx = 0; 2716 statsp->mac_stats.cap_100fdx = 0; 2717 statsp->mac_stats.cap_100hdx = 0; 2718 statsp->mac_stats.cap_10fdx = 0; 2719 statsp->mac_stats.cap_10hdx = 0; 2720 2721 /* param_anar_pause can be modified by ndd -set */ 2722 statsp->mac_stats.cap_pause = param_arr[param_anar_pause].value; 2723 2724 /* 2725 * The following 4 lines actually overwrites what ever the ndd command 2726 * has set. For example, by command 2727 * ndd -set /dev/nxge1 adv_autoneg_cap n (n = 0 or 1) 2728 * we could set param_arr[param_autoneg].value to n. However, because 2729 * here we assign constants to these parameters, whatever we set with 2730 * the "ndd -set" command will be replaced. So command 2731 * kstat nxge:X | grep param 2732 * will always show those constant values. In other words, the 2733 * "ndd -set" command can NOT change the values of these 4 parameters 2734 * even though the command appears to be successful. 2735 * 2736 * Note: TN1010 auto negotiation is always enabled. 2737 */ 2738 statsp->mac_stats.adv_cap_autoneg 2739 = param_arr[param_autoneg].value = 1; 2740 statsp->mac_stats.adv_cap_1000fdx 2741 = param_arr[param_anar_1000fdx].value = 1; 2742 statsp->mac_stats.adv_cap_100fdx 2743 = param_arr[param_anar_100fdx].value = 0; 2744 statsp->mac_stats.adv_cap_10fdx 2745 = param_arr[param_anar_10fdx].value = 0; 2746 2747 /* 2748 * The following 4 ndd params have type NXGE_PARAM_MAC_DONT_SHOW as 2749 * defined in nxge_param_arr[], therefore they are not seen by the 2750 * "ndd -get" command and can not be changed by ndd. We just set 2751 * them (both ndd param and kstat values) to constant 0 because TN1010 2752 * does not support those speeds. 2753 */ 2754 statsp->mac_stats.adv_cap_100T4 2755 = param_arr[param_anar_100T4].value = 0; 2756 statsp->mac_stats.adv_cap_1000hdx 2757 = param_arr[param_anar_1000hdx].value = 0; 2758 statsp->mac_stats.adv_cap_100hdx 2759 = param_arr[param_anar_100hdx].value = 0; 2760 statsp->mac_stats.adv_cap_10hdx 2761 = param_arr[param_anar_10hdx].value = 0; 2762 2763 /* 2764 * adv_cap_pause has type NXGE_PARAM_MAC_RW, so it can be modified 2765 * by ndd 2766 */ 2767 statsp->mac_stats.adv_cap_pause = param_arr[param_anar_pause].value; 2768 2769 /* 2770 * nxge_param_arr[] defines the adv_cap_asmpause with type 2771 * NXGE_PARAM_DONT_SHOW, therefore they are NOT seen by the 2772 * "ndd -get" command and can not be changed by ndd. Here we do not 2773 * assign a constant to it so the default value defined in 2774 * nxge_param_arr[] will be used to set the parameter and 2775 * will be shown by the kstat. 2776 */ 2777 statsp->mac_stats.adv_cap_asmpause 2778 = param_arr[param_anar_asmpause].value; 2779 2780 /* 2781 * Initialize the link statistics. 2782 */ 2783 statsp->mac_stats.link_T4 = 0; 2784 statsp->mac_stats.link_asmpause = 0; 2785 statsp->mac_stats.link_pause = 0; 2786 if (speed == TN1010_SPEED_1G) { 2787 statsp->mac_stats.link_speed = 1000; 2788 statsp->mac_stats.link_duplex = 2; /* Full duplex */ 2789 statsp->mac_stats.link_up = 1; 2790 } else { 2791 statsp->mac_stats.link_speed = 10000; 2792 statsp->mac_stats.link_duplex = 2; 2793 statsp->mac_stats.link_up = 1; 2794 } 2795 2796 /* 2797 * Because TN1010 does not have a link partner register, to 2798 * figure out the link partner's capabilities is tricky. Here we 2799 * just set the kstat based on our knowledge about the partner 2800 * (The partner must support auto-neg because auto-negotiation 2801 * has completed, it must support 1G or 10G because that is the 2802 * negotiated speed we are using.) 2803 * 2804 * Note: Current kstat does not show lp_cap_10gfdx and 2805 * lp_cap_10ghdx. 2806 */ 2807 if (speed == TN1010_SPEED_1G) { 2808 statsp->mac_stats.lp_cap_1000fdx = 1; 2809 statsp->mac_stats.lp_cap_10gfdx = 0; 2810 } else { 2811 statsp->mac_stats.lp_cap_1000fdx = 0; 2812 statsp->mac_stats.lp_cap_10gfdx = 1; 2813 } 2814 statsp->mac_stats.lp_cap_10ghdx = 0; 2815 statsp->mac_stats.lp_cap_1000hdx = 0; 2816 statsp->mac_stats.lp_cap_100fdx = 0; 2817 statsp->mac_stats.lp_cap_100hdx = 0; 2818 statsp->mac_stats.lp_cap_10fdx = 0; 2819 statsp->mac_stats.lp_cap_10hdx = 0; 2820 statsp->mac_stats.lp_cap_10gfdx = 0; 2821 statsp->mac_stats.lp_cap_10ghdx = 0; 2822 statsp->mac_stats.lp_cap_100T4 = 0; 2823 statsp->mac_stats.lp_cap_autoneg = 1; 2824 statsp->mac_stats.lp_cap_asmpause = 0; 2825 statsp->mac_stats.lp_cap_pause = 0; 2826 2827 /* Handle PHY loopback for SunVTS loopback test */ 2828 npi_mac_mif_set_indirect_mode(nxgep->npi_handle, B_TRUE); 2829 phy_port_addr = nxgep->nxge_hw_p->xcvr_addr[portn]; 2830 2831 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 2832 TN1010_PCS_DEV_ADDR, TN1010_PCS_CONTROL_REG, 2833 &tn1010_pcs_ctrl.value)) != NXGE_OK) { 2834 goto fail; 2835 } 2836 if ((statsp->port_stats.lb_mode == nxge_lb_phy1000) || 2837 (statsp->port_stats.lb_mode == nxge_lb_phy10g)) { 2838 tn1010_pcs_ctrl.bits.loopback = 1; 2839 } else { 2840 tn1010_pcs_ctrl.bits.loopback = 0; 2841 } 2842 if ((status = nxge_mdio_write(nxgep, phy_port_addr, 2843 TN1010_PCS_DEV_ADDR, TN1010_PCS_CONTROL_REG, 2844 tn1010_pcs_ctrl.value)) != NXGE_OK) { 2845 goto fail; 2846 } 2847 2848 statsp->mac_stats.xcvr_inits++; 2849 2850 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2851 "<== nxge_1G_tn1010_xcvr_init status 0x%x", status)); 2852 return (status); 2853 fail: 2854 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2855 "<== nxge_1G_tn1010_xcvr_init status 0x%x", status)); 2856 return (status); 2857 } 2858 2859 /* Initialize transceiver */ 2860 2861 nxge_status_t 2862 nxge_xcvr_init(p_nxge_t nxgep) 2863 { 2864 p_nxge_stats_t statsp; 2865 #ifdef NXGE_DEBUG 2866 uint8_t portn; 2867 #endif 2868 2869 nxge_status_t status = NXGE_OK; 2870 #ifdef NXGE_DEBUG 2871 portn = nxgep->mac.portnum; 2872 #endif 2873 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_xcvr_init: port<%d>", portn)); 2874 statsp = nxgep->statsp; 2875 2876 /* 2877 * Initialize the xcvr statistics. nxgep->xcvr.xcvr_init will 2878 * modify mac_stats. 2879 */ 2880 statsp->mac_stats.cap_autoneg = 0; 2881 statsp->mac_stats.cap_100T4 = 0; 2882 statsp->mac_stats.cap_100fdx = 0; 2883 statsp->mac_stats.cap_100hdx = 0; 2884 statsp->mac_stats.cap_10fdx = 0; 2885 statsp->mac_stats.cap_10hdx = 0; 2886 statsp->mac_stats.cap_asmpause = 0; 2887 statsp->mac_stats.cap_pause = 0; 2888 statsp->mac_stats.cap_1000fdx = 0; 2889 statsp->mac_stats.cap_1000hdx = 0; 2890 statsp->mac_stats.cap_10gfdx = 0; 2891 statsp->mac_stats.cap_10ghdx = 0; 2892 2893 /* 2894 * Initialize the link statistics. 2895 */ 2896 statsp->mac_stats.link_T4 = 0; 2897 statsp->mac_stats.link_asmpause = 0; 2898 statsp->mac_stats.link_pause = 0; 2899 2900 if (nxgep->xcvr.xcvr_init) { 2901 status = nxgep->xcvr.xcvr_init(nxgep); 2902 if (status != NXGE_OK) 2903 goto fail; 2904 statsp->mac_stats.xcvr_inits++; 2905 } 2906 2907 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_xcvr_init: port<%d>", 2908 portn)); 2909 return (NXGE_OK); 2910 2911 fail: 2912 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2913 "nxge_xcvr_init: failed to initialize transceiver for port<%d>", 2914 portn)); 2915 return (status); 2916 } 2917 2918 /* Look for transceiver type */ 2919 2920 nxge_status_t 2921 nxge_xcvr_find(p_nxge_t nxgep) 2922 { 2923 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_xcvr_find: port<%d>", 2924 nxgep->mac.portnum)); 2925 2926 if (nxge_get_xcvr_type(nxgep) != NXGE_OK) 2927 return (NXGE_ERROR); 2928 2929 if (nxge_setup_xcvr_table(nxgep) != NXGE_OK) 2930 return (NXGE_ERROR); 2931 2932 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_xcvr_find: xcvr_inuse = %d", 2933 nxgep->statsp->mac_stats.xcvr_inuse)); 2934 return (NXGE_OK); 2935 } 2936 2937 /* Initialize the TxMAC sub-block */ 2938 2939 nxge_status_t 2940 nxge_tx_mac_init(p_nxge_t nxgep) 2941 { 2942 npi_attr_t ap; 2943 uint8_t portn; 2944 nxge_port_mode_t portmode; 2945 nxge_port_t portt; 2946 npi_handle_t handle; 2947 npi_status_t rs = NPI_SUCCESS; 2948 2949 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 2950 portt = nxgep->mac.porttype; 2951 handle = nxgep->npi_handle; 2952 portmode = nxgep->mac.portmode; 2953 2954 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_tx_mac_init: port<%d>", 2955 portn)); 2956 /* Set Max and Min Frame Size */ 2957 /* 2958 * Use maxframesize to configure the hardware maxframe size 2959 * and minframesize to configure the hardware minframe size. 2960 */ 2961 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 2962 "==> nxge_tx_mac_init: port<%d> " 2963 "min framesize %d max framesize %d ", 2964 nxgep->mac.minframesize, 2965 nxgep->mac.maxframesize, 2966 portn)); 2967 2968 SET_MAC_ATTR2(handle, ap, portn, 2969 MAC_PORT_FRAME_SIZE, 2970 nxgep->mac.minframesize, 2971 nxgep->mac.maxframesize, 2972 rs); 2973 if (rs != NPI_SUCCESS) 2974 goto fail; 2975 2976 if (portt == PORT_TYPE_XMAC) { 2977 if ((rs = npi_xmac_tx_iconfig(handle, INIT, portn, 2978 0)) != NPI_SUCCESS) 2979 goto fail; 2980 nxgep->mac.tx_iconfig = NXGE_XMAC_TX_INTRS; 2981 if ((portmode == PORT_10G_FIBER) || 2982 (portmode == PORT_10G_COPPER) || 2983 (portmode == PORT_10G_TN1010) || 2984 (portmode == PORT_10G_SERDES)) { 2985 SET_MAC_ATTR1(handle, ap, portn, XMAC_10G_PORT_IPG, 2986 XGMII_IPG_12_15, rs); 2987 if (rs != NPI_SUCCESS) 2988 goto fail; 2989 nxgep->mac.ipg[0] = XGMII_IPG_12_15; 2990 } else { 2991 SET_MAC_ATTR1(handle, ap, portn, XMAC_PORT_IPG, 2992 MII_GMII_IPG_12, rs); 2993 if (rs != NPI_SUCCESS) 2994 goto fail; 2995 nxgep->mac.ipg[0] = MII_GMII_IPG_12; 2996 } 2997 if ((rs = npi_xmac_tx_config(handle, INIT, portn, 2998 CFG_XMAC_TX_CRC | CFG_XMAC_TX)) != NPI_SUCCESS) 2999 goto fail; 3000 nxgep->mac.tx_config = CFG_XMAC_TX_CRC | CFG_XMAC_TX; 3001 nxgep->mac.maxburstsize = 0; /* not programmable */ 3002 nxgep->mac.ctrltype = 0; /* not programmable */ 3003 nxgep->mac.pa_size = 0; /* not programmable */ 3004 3005 if ((rs = npi_xmac_zap_tx_counters(handle, portn)) 3006 != NPI_SUCCESS) 3007 goto fail; 3008 3009 } else { 3010 if ((rs = npi_bmac_tx_iconfig(handle, INIT, portn, 3011 0)) != NPI_SUCCESS) 3012 goto fail; 3013 nxgep->mac.tx_iconfig = NXGE_BMAC_TX_INTRS; 3014 3015 SET_MAC_ATTR1(handle, ap, portn, BMAC_PORT_CTRL_TYPE, 0x8808, 3016 rs); 3017 if (rs != NPI_SUCCESS) 3018 goto fail; 3019 nxgep->mac.ctrltype = 0x8808; 3020 3021 SET_MAC_ATTR1(handle, ap, portn, BMAC_PORT_PA_SIZE, 0x7, rs); 3022 if (rs != NPI_SUCCESS) 3023 goto fail; 3024 nxgep->mac.pa_size = 0x7; 3025 3026 if ((rs = npi_bmac_tx_config(handle, INIT, portn, 3027 CFG_BMAC_TX_CRC | CFG_BMAC_TX)) != NPI_SUCCESS) 3028 goto fail; 3029 nxgep->mac.tx_config = CFG_BMAC_TX_CRC | CFG_BMAC_TX; 3030 } 3031 3032 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_tx_mac_init: port<%d>", 3033 portn)); 3034 3035 return (NXGE_OK); 3036 fail: 3037 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3038 "nxge_tx_mac_init: failed to initialize port<%d> TXMAC", portn)); 3039 3040 return (NXGE_ERROR | rs); 3041 } 3042 3043 int 3044 nxge_hio_hostinfo_get_rdc_table(p_nxge_t nxgep) 3045 { 3046 int rdc_tbl; 3047 3048 /* 3049 * Get an RDC table (version 0). 3050 */ 3051 if ((rdc_tbl = nxge_fzc_rdc_tbl_bind(nxgep, -1, B_FALSE)) < 0) { 3052 NXGE_ERROR_MSG((nxgep, OBP_CTL, 3053 "nxge_hio_hostinfo_get_rdc_table: " 3054 "there are no free RDC tables!")); 3055 return (EBUSY); 3056 } 3057 3058 return (rdc_tbl); 3059 } 3060 3061 /* 3062 * nxge_hio_hostinfo_init 3063 * 3064 * Initialize an alternate MAC address, and bind a macrdctbln to it. 3065 * 3066 * Arguments: 3067 * nxge 3068 * vr The Virtualization Region 3069 * macaddr The alternate MAC address 3070 * 3071 * Notes: 3072 * 1. Find & bind an RDC table to <nxge>. 3073 * 2. Program an alternate MAC address (<macaddr>). 3074 * 3. Bind the RDC table to <macaddr>. 3075 * 3076 * Context: 3077 * Service domain 3078 * 3079 * Side Effects: 3080 * nxge->class_config.mac_host_info[slot].rdctbl 3081 * vr->slot & vr->altmac 3082 * 3083 */ 3084 int 3085 nxge_hio_hostinfo_init(nxge_t *nxge, nxge_hio_vr_t *vr, ether_addr_t *macaddr) 3086 { 3087 int slot, error; 3088 uint8_t rdc_tbl; 3089 nxge_mmac_t *mmac_info; 3090 nxge_rdc_grp_t *group; 3091 uint8_t *addr = (uint8_t *)macaddr; 3092 3093 mutex_enter(nxge->genlock); 3094 3095 rdc_tbl = (uint8_t)vr->rdc_tbl; 3096 3097 /* Initialize the NXGE RDC table data structure. */ 3098 group = &nxge->pt_config.rdc_grps[rdc_tbl]; 3099 group->port = NXGE_GET_PORT_NUM(nxge->function_num); 3100 group->config_method = RDC_TABLE_ENTRY_METHOD_REP; 3101 group->flag = 1; /* This group has been configured. */ 3102 3103 mmac_info = &nxge->nxge_mmac_info; 3104 3105 /* 3106 * Are there free slots. 3107 */ 3108 if (mmac_info->naddrfree == 0) { 3109 mutex_exit(nxge->genlock); 3110 return (ENOSPC); 3111 } 3112 3113 /* 3114 * Find a slot for the VR to use for Hybrid I/O. 3115 */ 3116 if (mmac_info->num_factory_mmac < mmac_info->num_mmac) { 3117 for (slot = mmac_info->num_factory_mmac + 1; 3118 slot <= mmac_info->num_mmac; slot++) { 3119 if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 3120 break; 3121 } 3122 if (slot > mmac_info->num_mmac) { 3123 for (slot = 1; slot <= mmac_info->num_factory_mmac; 3124 slot++) { 3125 if (!(mmac_info->mac_pool[slot].flags 3126 & MMAC_SLOT_USED)) 3127 break; 3128 } 3129 } 3130 } else { 3131 for (slot = 1; slot <= mmac_info->num_mmac; slot++) { 3132 if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 3133 break; 3134 } 3135 } 3136 ASSERT(slot <= mmac_info->num_mmac); 3137 vr->slot = slot; 3138 3139 error = nxge_altmac_set(nxge, addr, slot, rdc_tbl); 3140 if (error != 0) { 3141 mutex_exit(nxge->genlock); 3142 return (EIO); 3143 } 3144 3145 bcopy(macaddr, vr->altmac, sizeof (vr->altmac)); 3146 3147 /* 3148 * Update mmac 3149 */ 3150 bcopy(addr, mmac_info->mac_pool[vr->slot].addr, ETHERADDRL); 3151 mmac_info->mac_pool[vr->slot].flags |= MMAC_SLOT_USED; 3152 mmac_info->mac_pool[vr->slot].flags &= ~MMAC_VENDOR_ADDR; 3153 mmac_info->naddrfree--; 3154 nxge_mmac_kstat_update(nxge, vr->slot, B_FALSE); 3155 3156 mutex_exit(nxge->genlock); 3157 return (0); 3158 } 3159 3160 /* 3161 * nxge_hio_hostinfo_uninit 3162 * 3163 * Uninitialize an alternate MAC address. 3164 * 3165 * Arguments: 3166 * nxge 3167 * vr The Virtualization Region 3168 * 3169 * Notes: 3170 * 1. Remove the VR's alternate MAC address. 3171 * 1. Free (unbind) the RDC table allocated to this VR. 3172 * 3173 * Context: 3174 * Service domain 3175 * 3176 * Side Effects: 3177 * nxge->class_config.mac_host_info[slot].rdctbl 3178 * 3179 */ 3180 void 3181 nxge_hio_hostinfo_uninit(nxge_t *nxge, nxge_hio_vr_t *vr) 3182 { 3183 nxge_class_pt_cfg_t *class; 3184 uint8_t addrn; 3185 3186 addrn = vr->slot - 1; 3187 (void) npi_mac_altaddr_disable(nxge->npi_handle, 3188 nxge->mac.portnum, addrn); 3189 3190 /* Set this variable to its default. */ 3191 class = (p_nxge_class_pt_cfg_t)&nxge->class_config; 3192 class->mac_host_info[addrn].rdctbl = 3193 nxge->pt_config.hw_config.def_mac_rxdma_grpid; 3194 3195 (void) nxge_m_mmac_remove(nxge, vr->slot); 3196 vr->slot = -1; 3197 3198 (void) nxge_fzc_rdc_tbl_unbind(nxge, vr->rdc_tbl); 3199 vr->rdc_tbl = (uint8_t)-1; 3200 } 3201 3202 /* Initialize the RxMAC sub-block */ 3203 3204 nxge_status_t 3205 nxge_rx_mac_init(p_nxge_t nxgep) 3206 { 3207 npi_attr_t ap; 3208 uint32_t i; 3209 uint16_t hashtab_e; 3210 p_hash_filter_t hash_filter; 3211 nxge_port_t portt; 3212 uint8_t portn; 3213 npi_handle_t handle; 3214 npi_status_t rs = NPI_SUCCESS; 3215 uint16_t *addr16p; 3216 uint16_t addr0, addr1, addr2; 3217 xmac_rx_config_t xconfig; 3218 bmac_rx_config_t bconfig; 3219 3220 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 3221 3222 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_rx_mac_init: port<%d>\n", 3223 portn)); 3224 handle = nxgep->npi_handle; 3225 portt = nxgep->mac.porttype; 3226 3227 addr16p = (uint16_t *)nxgep->ouraddr.ether_addr_octet; 3228 addr0 = ntohs(addr16p[2]); 3229 addr1 = ntohs(addr16p[1]); 3230 addr2 = ntohs(addr16p[0]); 3231 SET_MAC_ATTR3(handle, ap, portn, MAC_PORT_ADDR, addr0, addr1, addr2, 3232 rs); 3233 3234 if (rs != NPI_SUCCESS) 3235 goto fail; 3236 SET_MAC_ATTR3(handle, ap, portn, MAC_PORT_ADDR_FILTER, 0, 0, 0, rs); 3237 if (rs != NPI_SUCCESS) 3238 goto fail; 3239 SET_MAC_ATTR2(handle, ap, portn, MAC_PORT_ADDR_FILTER_MASK, 0, 0, rs); 3240 if (rs != NPI_SUCCESS) 3241 goto fail; 3242 3243 /* 3244 * Load the multicast hash filter bits. 3245 */ 3246 hash_filter = nxgep->hash_filter; 3247 for (i = 0; i < MAC_MAX_HASH_ENTRY; i++) { 3248 if (hash_filter != NULL) { 3249 hashtab_e = (uint16_t)hash_filter->hash_filter_regs[ 3250 (NMCFILTER_REGS - 1) - i]; 3251 } else { 3252 hashtab_e = 0; 3253 } 3254 3255 if ((rs = npi_mac_hashtab_entry(handle, OP_SET, portn, i, 3256 (uint16_t *)&hashtab_e)) != NPI_SUCCESS) 3257 goto fail; 3258 } 3259 3260 if (portt == PORT_TYPE_XMAC) { 3261 if ((rs = npi_xmac_rx_iconfig(handle, INIT, portn, 3262 0)) != NPI_SUCCESS) 3263 goto fail; 3264 nxgep->mac.rx_iconfig = NXGE_XMAC_RX_INTRS; 3265 3266 (void) nxge_fflp_init_hostinfo(nxgep); 3267 3268 xconfig = CFG_XMAC_RX_ERRCHK | CFG_XMAC_RX_CRC_CHK | 3269 CFG_XMAC_RX | CFG_XMAC_RX_CODE_VIO_CHK & 3270 ~CFG_XMAC_RX_STRIP_CRC; 3271 3272 if (nxgep->filter.all_phys_cnt != 0) 3273 xconfig |= CFG_XMAC_RX_PROMISCUOUS; 3274 3275 if (nxgep->filter.all_multicast_cnt != 0) 3276 xconfig |= CFG_XMAC_RX_PROMISCUOUSGROUP; 3277 3278 xconfig |= CFG_XMAC_RX_HASH_FILTER; 3279 3280 if ((rs = npi_xmac_rx_config(handle, INIT, portn, 3281 xconfig)) != NPI_SUCCESS) 3282 goto fail; 3283 nxgep->mac.rx_config = xconfig; 3284 3285 /* Comparison of mac unique address is always enabled on XMAC */ 3286 3287 if ((rs = npi_xmac_zap_rx_counters(handle, portn)) 3288 != NPI_SUCCESS) 3289 goto fail; 3290 } else { 3291 (void) nxge_fflp_init_hostinfo(nxgep); 3292 3293 if (npi_bmac_rx_iconfig(nxgep->npi_handle, INIT, portn, 3294 0) != NPI_SUCCESS) 3295 goto fail; 3296 nxgep->mac.rx_iconfig = NXGE_BMAC_RX_INTRS; 3297 3298 bconfig = CFG_BMAC_RX_DISCARD_ON_ERR | CFG_BMAC_RX & 3299 ~CFG_BMAC_RX_STRIP_CRC; 3300 3301 if (nxgep->filter.all_phys_cnt != 0) 3302 bconfig |= CFG_BMAC_RX_PROMISCUOUS; 3303 3304 if (nxgep->filter.all_multicast_cnt != 0) 3305 bconfig |= CFG_BMAC_RX_PROMISCUOUSGROUP; 3306 3307 bconfig |= CFG_BMAC_RX_HASH_FILTER; 3308 if ((rs = npi_bmac_rx_config(handle, INIT, portn, 3309 bconfig)) != NPI_SUCCESS) 3310 goto fail; 3311 nxgep->mac.rx_config = bconfig; 3312 3313 /* Always enable comparison of mac unique address */ 3314 if ((rs = npi_mac_altaddr_enable(handle, portn, 0)) 3315 != NPI_SUCCESS) 3316 goto fail; 3317 } 3318 3319 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_rx_mac_init: port<%d>\n", 3320 portn)); 3321 3322 return (NXGE_OK); 3323 3324 fail: 3325 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3326 "nxge_rx_mac_init: Failed to Initialize port<%d> RxMAC", portn)); 3327 3328 return (NXGE_ERROR | rs); 3329 } 3330 3331 /* Enable TXMAC */ 3332 3333 nxge_status_t 3334 nxge_tx_mac_enable(p_nxge_t nxgep) 3335 { 3336 npi_handle_t handle; 3337 npi_status_t rs = NPI_SUCCESS; 3338 nxge_status_t status = NXGE_OK; 3339 3340 handle = nxgep->npi_handle; 3341 3342 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_tx_mac_enable: port<%d>", 3343 nxgep->mac.portnum)); 3344 3345 if ((status = nxge_tx_mac_init(nxgep)) != NXGE_OK) 3346 goto fail; 3347 3348 /* based on speed */ 3349 nxgep->msg_min = ETHERMIN; 3350 3351 if (nxgep->mac.porttype == PORT_TYPE_XMAC) { 3352 if ((rs = npi_xmac_tx_config(handle, ENABLE, nxgep->mac.portnum, 3353 CFG_XMAC_TX)) != NPI_SUCCESS) 3354 goto fail; 3355 } else { 3356 if ((rs = npi_bmac_tx_config(handle, ENABLE, nxgep->mac.portnum, 3357 CFG_BMAC_TX)) != NPI_SUCCESS) 3358 goto fail; 3359 } 3360 3361 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_tx_mac_enable: port<%d>", 3362 nxgep->mac.portnum)); 3363 3364 return (NXGE_OK); 3365 fail: 3366 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3367 "nxgep_tx_mac_enable: Failed to enable port<%d> TxMAC", 3368 nxgep->mac.portnum)); 3369 if (rs != NPI_SUCCESS) 3370 return (NXGE_ERROR | rs); 3371 else 3372 return (status); 3373 } 3374 3375 /* Disable TXMAC */ 3376 3377 nxge_status_t 3378 nxge_tx_mac_disable(p_nxge_t nxgep) 3379 { 3380 npi_handle_t handle; 3381 npi_status_t rs = NPI_SUCCESS; 3382 3383 if (isLDOMguest(nxgep)) 3384 return (NXGE_OK); 3385 3386 handle = nxgep->npi_handle; 3387 3388 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_tx_mac_disable: port<%d>", 3389 nxgep->mac.portnum)); 3390 3391 if (nxgep->mac.porttype == PORT_TYPE_XMAC) { 3392 if ((rs = npi_xmac_tx_config(handle, DISABLE, 3393 nxgep->mac.portnum, CFG_XMAC_TX)) != NPI_SUCCESS) 3394 goto fail; 3395 } else { 3396 if ((rs = npi_bmac_tx_config(handle, DISABLE, 3397 nxgep->mac.portnum, CFG_BMAC_TX)) != NPI_SUCCESS) 3398 goto fail; 3399 } 3400 3401 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_tx_mac_disable: port<%d>", 3402 nxgep->mac.portnum)); 3403 return (NXGE_OK); 3404 fail: 3405 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3406 "nxge_tx_mac_disable: Failed to disable port<%d> TxMAC", 3407 nxgep->mac.portnum)); 3408 return (NXGE_ERROR | rs); 3409 } 3410 3411 /* Enable RXMAC */ 3412 3413 nxge_status_t 3414 nxge_rx_mac_enable(p_nxge_t nxgep) 3415 { 3416 npi_handle_t handle; 3417 uint8_t portn; 3418 npi_status_t rs = NPI_SUCCESS; 3419 nxge_status_t status = NXGE_OK; 3420 3421 /* This is a service-domain-only activity. */ 3422 if (isLDOMguest(nxgep)) 3423 return (status); 3424 3425 handle = nxgep->npi_handle; 3426 portn = nxgep->mac.portnum; 3427 3428 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_rx_mac_enable: port<%d>", 3429 portn)); 3430 3431 if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK) 3432 goto fail; 3433 3434 if (nxgep->mac.porttype == PORT_TYPE_XMAC) { 3435 if ((rs = npi_xmac_rx_config(handle, ENABLE, portn, 3436 CFG_XMAC_RX)) != NPI_SUCCESS) 3437 goto fail; 3438 } else { 3439 if ((rs = npi_bmac_rx_config(handle, ENABLE, portn, 3440 CFG_BMAC_RX)) != NPI_SUCCESS) 3441 goto fail; 3442 } 3443 3444 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3445 "<== nxge_rx_mac_enable: port<%d>", portn)); 3446 3447 return (NXGE_OK); 3448 fail: 3449 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3450 "nxgep_rx_mac_enable: Failed to enable port<%d> RxMAC", portn)); 3451 3452 if (rs != NPI_SUCCESS) 3453 return (NXGE_ERROR | rs); 3454 else 3455 return (status); 3456 } 3457 3458 /* Disable RXMAC */ 3459 3460 nxge_status_t 3461 nxge_rx_mac_disable(p_nxge_t nxgep) 3462 { 3463 npi_handle_t handle; 3464 uint8_t portn; 3465 npi_status_t rs = NPI_SUCCESS; 3466 3467 /* If we are a guest domain driver, don't bother. */ 3468 if (isLDOMguest(nxgep)) 3469 return (NXGE_OK); 3470 3471 handle = nxgep->npi_handle; 3472 portn = nxgep->mac.portnum; 3473 3474 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_rx_mac_disable: port<%d>", 3475 portn)); 3476 3477 if (nxgep->mac.porttype == PORT_TYPE_XMAC) { 3478 if ((rs = npi_xmac_rx_config(handle, DISABLE, portn, 3479 CFG_XMAC_RX)) != NPI_SUCCESS) 3480 goto fail; 3481 } else { 3482 if ((rs = npi_bmac_rx_config(handle, DISABLE, portn, 3483 CFG_BMAC_RX)) != NPI_SUCCESS) 3484 goto fail; 3485 } 3486 3487 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_rx_mac_disable: port<%d>", 3488 portn)); 3489 return (NXGE_OK); 3490 fail: 3491 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3492 "nxgep_rx_mac_disable: Failed to disable port<%d> RxMAC", portn)); 3493 3494 return (NXGE_ERROR | rs); 3495 } 3496 3497 /* Reset TXMAC */ 3498 3499 nxge_status_t 3500 nxge_tx_mac_reset(p_nxge_t nxgep) 3501 { 3502 npi_handle_t handle; 3503 uint8_t portn; 3504 npi_status_t rs = NPI_SUCCESS; 3505 3506 handle = nxgep->npi_handle; 3507 portn = nxgep->mac.portnum; 3508 3509 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_tx_mac_reset: port<%d>", 3510 portn)); 3511 3512 if (nxgep->mac.porttype == PORT_TYPE_XMAC) { 3513 if ((rs = npi_xmac_reset(handle, portn, XTX_MAC_RESET_ALL)) 3514 != NPI_SUCCESS) 3515 goto fail; 3516 } else { 3517 if ((rs = npi_bmac_reset(handle, portn, TX_MAC_RESET)) 3518 != NPI_SUCCESS) 3519 goto fail; 3520 } 3521 3522 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_tx_mac_reset: port<%d>", 3523 portn)); 3524 3525 return (NXGE_OK); 3526 fail: 3527 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3528 "nxge_tx_mac_reset: Failed to Reset TxMAC port<%d>", portn)); 3529 3530 return (NXGE_ERROR | rs); 3531 } 3532 3533 /* Reset RXMAC */ 3534 3535 nxge_status_t 3536 nxge_rx_mac_reset(p_nxge_t nxgep) 3537 { 3538 npi_handle_t handle; 3539 uint8_t portn; 3540 npi_status_t rs = NPI_SUCCESS; 3541 3542 handle = nxgep->npi_handle; 3543 portn = nxgep->mac.portnum; 3544 3545 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_rx_mac_reset: port<%d>", 3546 portn)); 3547 3548 if (nxgep->mac.porttype == PORT_TYPE_XMAC) { 3549 if ((rs = npi_xmac_reset(handle, portn, XRX_MAC_RESET_ALL)) 3550 != NPI_SUCCESS) 3551 goto fail; 3552 } else { 3553 if ((rs = npi_bmac_reset(handle, portn, RX_MAC_RESET)) 3554 != NPI_SUCCESS) 3555 goto fail; 3556 } 3557 3558 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_rx_mac_reset: port<%d>", 3559 portn)); 3560 3561 return (NXGE_OK); 3562 fail: 3563 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3564 "nxge_rx_mac_reset: Failed to Reset RxMAC port<%d>", portn)); 3565 return (NXGE_ERROR | rs); 3566 } 3567 3568 /* 10G fiber link interrupt start routine */ 3569 3570 static nxge_status_t 3571 nxge_10G_link_intr_start(p_nxge_t nxgep) 3572 { 3573 npi_status_t rs = NPI_SUCCESS; 3574 uint8_t portn = nxgep->mac.portnum; 3575 3576 rs = npi_xmac_xpcs_link_intr_enable(nxgep->npi_handle, portn); 3577 3578 if (rs != NPI_SUCCESS) 3579 return (NXGE_ERROR | rs); 3580 else 3581 return (NXGE_OK); 3582 } 3583 3584 /* 10G fiber link interrupt stop routine */ 3585 3586 static nxge_status_t 3587 nxge_10G_link_intr_stop(p_nxge_t nxgep) 3588 { 3589 npi_status_t rs = NPI_SUCCESS; 3590 uint8_t portn = nxgep->mac.portnum; 3591 3592 rs = npi_xmac_xpcs_link_intr_disable(nxgep->npi_handle, portn); 3593 3594 if (rs != NPI_SUCCESS) 3595 return (NXGE_ERROR | rs); 3596 else 3597 return (NXGE_OK); 3598 } 3599 3600 /* 1G fiber link interrupt start routine */ 3601 3602 static nxge_status_t 3603 nxge_1G_fiber_link_intr_start(p_nxge_t nxgep) 3604 { 3605 npi_status_t rs = NPI_SUCCESS; 3606 uint8_t portn = nxgep->mac.portnum; 3607 3608 rs = npi_mac_pcs_link_intr_enable(nxgep->npi_handle, portn); 3609 if (rs != NPI_SUCCESS) 3610 return (NXGE_ERROR | rs); 3611 else 3612 return (NXGE_OK); 3613 } 3614 3615 /* 1G fiber link interrupt stop routine */ 3616 3617 static nxge_status_t 3618 nxge_1G_fiber_link_intr_stop(p_nxge_t nxgep) 3619 { 3620 npi_status_t rs = NPI_SUCCESS; 3621 uint8_t portn = nxgep->mac.portnum; 3622 3623 rs = npi_mac_pcs_link_intr_disable(nxgep->npi_handle, portn); 3624 3625 if (rs != NPI_SUCCESS) 3626 return (NXGE_ERROR | rs); 3627 else 3628 return (NXGE_OK); 3629 } 3630 3631 /* 1G copper link interrupt start routine */ 3632 3633 static nxge_status_t 3634 nxge_1G_copper_link_intr_start(p_nxge_t nxgep) 3635 { 3636 npi_status_t rs = NPI_SUCCESS; 3637 uint8_t portn = nxgep->mac.portnum; 3638 3639 rs = npi_mac_mif_link_intr_enable(nxgep->npi_handle, portn, 3640 MII_STATUS, MII_STATUS_LINKUP); 3641 3642 if (rs != NPI_SUCCESS) 3643 return (NXGE_ERROR | rs); 3644 else 3645 return (NXGE_OK); 3646 } 3647 3648 /* 1G copper link interrupt stop routine */ 3649 3650 static nxge_status_t 3651 nxge_1G_copper_link_intr_stop(p_nxge_t nxgep) 3652 { 3653 npi_status_t rs = NPI_SUCCESS; 3654 uint8_t portn = nxgep->mac.portnum; 3655 3656 rs = npi_mac_mif_link_intr_disable(nxgep->npi_handle, portn); 3657 3658 if (rs != NPI_SUCCESS) 3659 return (NXGE_ERROR | rs); 3660 else 3661 return (NXGE_OK); 3662 } 3663 3664 /* Enable/Disable Link Status change interrupt */ 3665 3666 nxge_status_t 3667 nxge_link_intr(p_nxge_t nxgep, link_intr_enable_t enable) 3668 { 3669 uint8_t portn; 3670 nxge_status_t status = NXGE_OK; 3671 3672 portn = nxgep->mac.portnum; 3673 3674 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_link_intr: port<%d>", portn)); 3675 if (!nxgep->xcvr.link_intr_stop || !nxgep->xcvr.link_intr_start) 3676 return (NXGE_OK); 3677 3678 if (enable == LINK_INTR_START) 3679 status = nxgep->xcvr.link_intr_start(nxgep); 3680 else if (enable == LINK_INTR_STOP) 3681 status = nxgep->xcvr.link_intr_stop(nxgep); 3682 if (status != NXGE_OK) 3683 goto fail; 3684 3685 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_link_intr: port<%d>", portn)); 3686 3687 return (NXGE_OK); 3688 fail: 3689 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3690 "nxge_link_intr: Failed to set port<%d> mif intr mode", portn)); 3691 3692 return (status); 3693 } 3694 3695 /* Initialize 1G Fiber / Copper transceiver using Clause 22 */ 3696 3697 nxge_status_t 3698 nxge_mii_xcvr_init(p_nxge_t nxgep) 3699 { 3700 p_nxge_param_t param_arr; 3701 p_nxge_stats_t statsp; 3702 uint8_t xcvr_portn; 3703 p_mii_regs_t mii_regs; 3704 mii_bmcr_t bmcr; 3705 mii_bmsr_t bmsr; 3706 mii_anar_t anar; 3707 mii_gcr_t gcr; 3708 mii_esr_t esr; 3709 mii_aux_ctl_t bcm5464r_aux; 3710 int status = NXGE_OK; 3711 3712 uint_t delay; 3713 3714 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_mii_xcvr_init")); 3715 3716 param_arr = nxgep->param_arr; 3717 statsp = nxgep->statsp; 3718 xcvr_portn = statsp->mac_stats.xcvr_portn; 3719 3720 mii_regs = NULL; 3721 3722 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3723 "nxge_param_autoneg = 0x%02x", param_arr[param_autoneg].value)); 3724 3725 /* 3726 * The mif phy mode may be connected to either a copper link 3727 * or fiber link. Read the mode control register to get the fiber 3728 * configuration if it is hard-wired to fiber link. 3729 */ 3730 (void) nxge_mii_get_link_mode(nxgep); 3731 if (nxgep->mac.portmode == PORT_1G_RGMII_FIBER) { 3732 return (nxge_mii_xcvr_fiber_init(nxgep)); 3733 } 3734 3735 /* 3736 * Reset the transceiver. 3737 */ 3738 delay = 0; 3739 bmcr.value = 0; 3740 bmcr.bits.reset = 1; 3741 if ((status = nxge_mii_write(nxgep, xcvr_portn, 3742 #if defined(__i386) 3743 (uint8_t)(uint32_t)&mii_regs->bmcr, 3744 #else 3745 (uint8_t)(uint64_t)&mii_regs->bmcr, 3746 #endif 3747 bmcr.value)) != NXGE_OK) 3748 goto fail; 3749 do { 3750 drv_usecwait(500); 3751 if ((status = nxge_mii_read(nxgep, xcvr_portn, 3752 #if defined(__i386) 3753 (uint8_t)(uint32_t)&mii_regs->bmcr, 3754 #else 3755 (uint8_t)(uint64_t)&mii_regs->bmcr, 3756 #endif 3757 &bmcr.value)) != NXGE_OK) 3758 goto fail; 3759 delay++; 3760 } while ((bmcr.bits.reset) && (delay < 1000)); 3761 if (delay == 1000) { 3762 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "Xcvr reset failed.")); 3763 goto fail; 3764 } 3765 3766 if ((status = nxge_mii_read(nxgep, xcvr_portn, 3767 #if defined(__i386) 3768 (uint8_t)(uint32_t)(&mii_regs->bmsr), 3769 #else 3770 (uint8_t)(uint64_t)(&mii_regs->bmsr), 3771 #endif 3772 &bmsr.value)) != NXGE_OK) 3773 goto fail; 3774 3775 param_arr[param_autoneg].value &= bmsr.bits.auto_neg_able; 3776 param_arr[param_anar_100T4].value &= bmsr.bits.link_100T4; 3777 param_arr[param_anar_100fdx].value &= bmsr.bits.link_100fdx; 3778 param_arr[param_anar_100hdx].value = 0; 3779 param_arr[param_anar_10fdx].value &= bmsr.bits.link_10fdx; 3780 param_arr[param_anar_10hdx].value = 0; 3781 3782 /* 3783 * Initialize the xcvr statistics. 3784 */ 3785 statsp->mac_stats.cap_autoneg = bmsr.bits.auto_neg_able; 3786 statsp->mac_stats.cap_100T4 = bmsr.bits.link_100T4; 3787 statsp->mac_stats.cap_100fdx = bmsr.bits.link_100fdx; 3788 statsp->mac_stats.cap_100hdx = 0; 3789 statsp->mac_stats.cap_10fdx = bmsr.bits.link_10fdx; 3790 statsp->mac_stats.cap_10hdx = 0; 3791 statsp->mac_stats.cap_asmpause = param_arr[param_anar_asmpause].value; 3792 statsp->mac_stats.cap_pause = param_arr[param_anar_pause].value; 3793 3794 /* 3795 * Initialize the xcvr advertised capability statistics. 3796 */ 3797 statsp->mac_stats.adv_cap_autoneg = param_arr[param_autoneg].value; 3798 statsp->mac_stats.adv_cap_1000fdx = param_arr[param_anar_1000fdx].value; 3799 statsp->mac_stats.adv_cap_1000hdx = param_arr[param_anar_1000hdx].value; 3800 statsp->mac_stats.adv_cap_100T4 = param_arr[param_anar_100T4].value; 3801 statsp->mac_stats.adv_cap_100fdx = param_arr[param_anar_100fdx].value; 3802 statsp->mac_stats.adv_cap_100hdx = param_arr[param_anar_100hdx].value; 3803 statsp->mac_stats.adv_cap_10fdx = param_arr[param_anar_10fdx].value; 3804 statsp->mac_stats.adv_cap_10hdx = param_arr[param_anar_10hdx].value; 3805 statsp->mac_stats.adv_cap_asmpause = 3806 param_arr[param_anar_asmpause].value; 3807 statsp->mac_stats.adv_cap_pause = param_arr[param_anar_pause].value; 3808 3809 3810 /* 3811 * Check for extended status just in case we're 3812 * running a Gigibit phy. 3813 */ 3814 if (bmsr.bits.extend_status) { 3815 if ((status = nxge_mii_read(nxgep, xcvr_portn, 3816 #if defined(__i386) 3817 (uint8_t)(uint32_t)(&mii_regs->esr), 3818 #else 3819 (uint8_t)(uint64_t)(&mii_regs->esr), 3820 #endif 3821 &esr.value)) != NXGE_OK) 3822 goto fail; 3823 param_arr[param_anar_1000fdx].value &= esr.bits.link_1000fdx; 3824 param_arr[param_anar_1000hdx].value = 0; 3825 3826 statsp->mac_stats.cap_1000fdx = 3827 (esr.bits.link_1000Xfdx || esr.bits.link_1000fdx); 3828 statsp->mac_stats.cap_1000hdx = 0; 3829 } else { 3830 param_arr[param_anar_1000fdx].value = 0; 3831 param_arr[param_anar_1000hdx].value = 0; 3832 } 3833 3834 /* 3835 * Initialize 1G Statistics once the capability is established. 3836 */ 3837 statsp->mac_stats.adv_cap_1000fdx = param_arr[param_anar_1000fdx].value; 3838 statsp->mac_stats.adv_cap_1000hdx = param_arr[param_anar_1000hdx].value; 3839 3840 /* 3841 * Initialize the link statistics. 3842 */ 3843 statsp->mac_stats.link_T4 = 0; 3844 statsp->mac_stats.link_asmpause = 0; 3845 statsp->mac_stats.link_pause = 0; 3846 statsp->mac_stats.link_speed = 0; 3847 statsp->mac_stats.link_duplex = 0; 3848 statsp->mac_stats.link_up = 0; 3849 3850 /* 3851 * Switch off Auto-negotiation, 100M and full duplex. 3852 */ 3853 bmcr.value = 0; 3854 if ((status = nxge_mii_write(nxgep, xcvr_portn, 3855 #if defined(__i386) 3856 (uint8_t)(uint32_t)(&mii_regs->bmcr), 3857 #else 3858 (uint8_t)(uint64_t)(&mii_regs->bmcr), 3859 #endif 3860 bmcr.value)) != NXGE_OK) 3861 goto fail; 3862 3863 if ((statsp->port_stats.lb_mode == nxge_lb_phy) || 3864 (statsp->port_stats.lb_mode == nxge_lb_phy1000)) { 3865 bmcr.bits.loopback = 1; 3866 bmcr.bits.enable_autoneg = 0; 3867 if (statsp->port_stats.lb_mode == nxge_lb_phy1000) 3868 bmcr.bits.speed_1000_sel = 1; 3869 bmcr.bits.duplex_mode = 1; 3870 param_arr[param_autoneg].value = 0; 3871 } else { 3872 bmcr.bits.loopback = 0; 3873 } 3874 3875 if ((statsp->port_stats.lb_mode == nxge_lb_ext1000) || 3876 (statsp->port_stats.lb_mode == nxge_lb_ext100) || 3877 (statsp->port_stats.lb_mode == nxge_lb_ext10)) { 3878 param_arr[param_autoneg].value = 0; 3879 bcm5464r_aux.value = 0; 3880 bcm5464r_aux.bits.ext_lb = 1; 3881 bcm5464r_aux.bits.write_1 = 1; 3882 if ((status = nxge_mii_write(nxgep, xcvr_portn, 3883 BCM5464R_AUX_CTL, bcm5464r_aux.value)) != NXGE_OK) 3884 goto fail; 3885 } 3886 3887 /* If auto-negotiation is desired */ 3888 if (param_arr[param_autoneg].value) { 3889 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3890 "Restarting Auto-negotiation.")); 3891 /* 3892 * Setup our Auto-negotiation advertisement register. 3893 */ 3894 anar.value = 0; 3895 anar.bits.selector = 1; 3896 anar.bits.cap_100T4 = param_arr[param_anar_100T4].value; 3897 anar.bits.cap_100fdx = param_arr[param_anar_100fdx].value; 3898 anar.bits.cap_100hdx = param_arr[param_anar_100hdx].value; 3899 anar.bits.cap_10fdx = param_arr[param_anar_10fdx].value; 3900 anar.bits.cap_10hdx = param_arr[param_anar_10hdx].value; 3901 anar.bits.cap_asmpause = 0; 3902 anar.bits.cap_pause = 0; 3903 if (param_arr[param_anar_1000fdx].value || 3904 param_arr[param_anar_100fdx].value || 3905 param_arr[param_anar_10fdx].value) { 3906 anar.bits.cap_asmpause = statsp->mac_stats.cap_asmpause; 3907 anar.bits.cap_pause = statsp->mac_stats.cap_pause; 3908 } 3909 3910 /* Write to the auto-negotiation advertisement register */ 3911 if ((status = nxge_mii_write(nxgep, xcvr_portn, 3912 #if defined(__i386) 3913 (uint8_t)(uint32_t)(&mii_regs->anar), 3914 #else 3915 (uint8_t)(uint64_t)(&mii_regs->anar), 3916 #endif 3917 anar.value)) != NXGE_OK) 3918 goto fail; 3919 if (bmsr.bits.extend_status) { 3920 gcr.value = 0; 3921 gcr.bits.ms_mode_en = 3922 param_arr[param_master_cfg_enable].value; 3923 gcr.bits.master = 3924 param_arr[param_master_cfg_value].value; 3925 gcr.bits.link_1000fdx = 3926 param_arr[param_anar_1000fdx].value; 3927 gcr.bits.link_1000hdx = 3928 param_arr[param_anar_1000hdx].value; 3929 if ((status = nxge_mii_write(nxgep, xcvr_portn, 3930 #if defined(__i386) 3931 (uint8_t)(uint32_t)(&mii_regs->gcr), 3932 #else 3933 (uint8_t)(uint64_t)(&mii_regs->gcr), 3934 #endif 3935 gcr.value)) != NXGE_OK) 3936 goto fail; 3937 } 3938 3939 bmcr.bits.enable_autoneg = 1; 3940 bmcr.bits.restart_autoneg = 1; 3941 3942 } else { 3943 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "Going into forced mode.")); 3944 bmcr.bits.speed_1000_sel = 3945 param_arr[param_anar_1000fdx].value | 3946 param_arr[param_anar_1000hdx].value; 3947 bmcr.bits.speed_sel = (~bmcr.bits.speed_1000_sel) & 3948 (param_arr[param_anar_100fdx].value | 3949 param_arr[param_anar_100hdx].value); 3950 3951 /* Force to 1G */ 3952 if (bmcr.bits.speed_1000_sel) { 3953 statsp->mac_stats.link_speed = 1000; 3954 gcr.value = 0; 3955 gcr.bits.ms_mode_en = 3956 param_arr[param_master_cfg_enable].value; 3957 gcr.bits.master = 3958 param_arr[param_master_cfg_value].value; 3959 if ((status = nxge_mii_write(nxgep, xcvr_portn, 3960 #if defined(__i386) 3961 (uint8_t)(uint32_t)(&mii_regs->gcr), 3962 #else 3963 (uint8_t)(uint64_t)(&mii_regs->gcr), 3964 #endif 3965 gcr.value)) != NXGE_OK) 3966 goto fail; 3967 if (param_arr[param_anar_1000fdx].value) { 3968 bmcr.bits.duplex_mode = 1; 3969 statsp->mac_stats.link_duplex = 2; 3970 } else 3971 statsp->mac_stats.link_duplex = 1; 3972 3973 /* Force to 100M */ 3974 } else if (bmcr.bits.speed_sel) { 3975 statsp->mac_stats.link_speed = 100; 3976 if (param_arr[param_anar_100fdx].value) { 3977 bmcr.bits.duplex_mode = 1; 3978 statsp->mac_stats.link_duplex = 2; 3979 } else 3980 statsp->mac_stats.link_duplex = 1; 3981 3982 /* Force to 10M */ 3983 } else { 3984 statsp->mac_stats.link_speed = 10; 3985 if (param_arr[param_anar_10fdx].value) { 3986 bmcr.bits.duplex_mode = 1; 3987 statsp->mac_stats.link_duplex = 2; 3988 } else 3989 statsp->mac_stats.link_duplex = 1; 3990 } 3991 if (statsp->mac_stats.link_duplex != 1) { 3992 statsp->mac_stats.link_asmpause = 3993 statsp->mac_stats.cap_asmpause; 3994 statsp->mac_stats.link_pause = 3995 statsp->mac_stats.cap_pause; 3996 } 3997 3998 if ((statsp->port_stats.lb_mode == nxge_lb_ext1000) || 3999 (statsp->port_stats.lb_mode == nxge_lb_ext100) || 4000 (statsp->port_stats.lb_mode == nxge_lb_ext10)) { 4001 if (statsp->port_stats.lb_mode == nxge_lb_ext1000) { 4002 /* BCM5464R 1000mbps external loopback mode */ 4003 gcr.value = 0; 4004 gcr.bits.ms_mode_en = 1; 4005 gcr.bits.master = 1; 4006 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4007 #if defined(__i386) 4008 (uint8_t)(uint32_t)(&mii_regs->gcr), 4009 #else 4010 (uint8_t)(uint64_t)(&mii_regs->gcr), 4011 #endif 4012 gcr.value)) != NXGE_OK) 4013 goto fail; 4014 bmcr.value = 0; 4015 bmcr.bits.speed_1000_sel = 1; 4016 statsp->mac_stats.link_speed = 1000; 4017 } else if (statsp->port_stats.lb_mode 4018 == nxge_lb_ext100) { 4019 /* BCM5464R 100mbps external loopback mode */ 4020 bmcr.value = 0; 4021 bmcr.bits.speed_sel = 1; 4022 bmcr.bits.duplex_mode = 1; 4023 statsp->mac_stats.link_speed = 100; 4024 } else if (statsp->port_stats.lb_mode 4025 == nxge_lb_ext10) { 4026 /* BCM5464R 10mbps external loopback mode */ 4027 bmcr.value = 0; 4028 bmcr.bits.duplex_mode = 1; 4029 statsp->mac_stats.link_speed = 10; 4030 } 4031 } 4032 } 4033 4034 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4035 #if defined(__i386) 4036 (uint8_t)(uint32_t)(&mii_regs->bmcr), 4037 #else 4038 (uint8_t)(uint64_t)(&mii_regs->bmcr), 4039 #endif 4040 bmcr.value)) != NXGE_OK) 4041 goto fail; 4042 4043 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4044 #if defined(__i386) 4045 (uint8_t)(uint32_t)(&mii_regs->bmcr), 4046 #else 4047 (uint8_t)(uint64_t)(&mii_regs->bmcr), 4048 #endif 4049 &bmcr.value)) != NXGE_OK) 4050 goto fail; 4051 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "bmcr = 0x%04X", bmcr.value)); 4052 4053 /* 4054 * Initialize the xcvr status kept in the context structure. 4055 */ 4056 nxgep->soft_bmsr.value = 0; 4057 4058 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4059 #if defined(__i386) 4060 (uint8_t)(uint32_t)(&mii_regs->bmsr), 4061 #else 4062 (uint8_t)(uint64_t)(&mii_regs->bmsr), 4063 #endif 4064 &nxgep->bmsr.value)) != NXGE_OK) 4065 goto fail; 4066 4067 statsp->mac_stats.xcvr_inits++; 4068 nxgep->bmsr.value = 0; 4069 4070 fail: 4071 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4072 "<== nxge_mii_xcvr_init status 0x%x", status)); 4073 return (status); 4074 } 4075 4076 nxge_status_t 4077 nxge_mii_xcvr_fiber_init(p_nxge_t nxgep) 4078 { 4079 p_nxge_param_t param_arr; 4080 p_nxge_stats_t statsp; 4081 uint8_t xcvr_portn; 4082 p_mii_regs_t mii_regs; 4083 mii_bmcr_t bmcr; 4084 mii_bmsr_t bmsr; 4085 mii_gcr_t gcr; 4086 mii_esr_t esr; 4087 mii_aux_ctl_t bcm5464r_aux; 4088 int status = NXGE_OK; 4089 4090 uint_t delay; 4091 4092 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_mii_xcvr_fiber_init")); 4093 4094 param_arr = nxgep->param_arr; 4095 statsp = nxgep->statsp; 4096 xcvr_portn = statsp->mac_stats.xcvr_portn; 4097 4098 mii_regs = NULL; 4099 4100 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4101 "nxge_mii_xcvr_fiber_init: " 4102 "nxge_param_autoneg = 0x%02x", param_arr[param_autoneg].value)); 4103 4104 /* 4105 * Reset the transceiver. 4106 */ 4107 delay = 0; 4108 bmcr.value = 0; 4109 bmcr.bits.reset = 1; 4110 4111 #if defined(__i386) 4112 4113 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4114 (uint8_t)(uint32_t)(&mii_regs->bmcr), bmcr.value)) != NXGE_OK) 4115 goto fail; 4116 #else 4117 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4118 (uint8_t)(uint64_t)(&mii_regs->bmcr), bmcr.value)) != NXGE_OK) 4119 goto fail; 4120 #endif 4121 do { 4122 drv_usecwait(500); 4123 #if defined(__i386) 4124 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4125 (uint8_t)(uint32_t)(&mii_regs->bmcr), &bmcr.value)) 4126 != NXGE_OK) 4127 goto fail; 4128 #else 4129 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4130 (uint8_t)(uint64_t)(&mii_regs->bmcr), &bmcr.value)) 4131 != NXGE_OK) 4132 goto fail; 4133 #endif 4134 delay++; 4135 } while ((bmcr.bits.reset) && (delay < 1000)); 4136 if (delay == 1000) { 4137 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "Xcvr reset failed.")); 4138 goto fail; 4139 } 4140 4141 #if defined(__i386) 4142 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4143 (uint8_t)(uint32_t)(&mii_regs->bmsr), &bmsr.value)) != NXGE_OK) 4144 goto fail; 4145 #else 4146 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4147 (uint8_t)(uint64_t)(&mii_regs->bmsr), &bmsr.value)) != NXGE_OK) 4148 goto fail; 4149 #endif 4150 4151 param_arr[param_autoneg].value &= bmsr.bits.auto_neg_able; 4152 param_arr[param_anar_100T4].value = 0; 4153 param_arr[param_anar_100fdx].value = 0; 4154 param_arr[param_anar_100hdx].value = 0; 4155 param_arr[param_anar_10fdx].value = 0; 4156 param_arr[param_anar_10hdx].value = 0; 4157 4158 /* 4159 * Initialize the xcvr statistics. 4160 */ 4161 statsp->mac_stats.cap_autoneg = bmsr.bits.auto_neg_able; 4162 statsp->mac_stats.cap_100T4 = 0; 4163 statsp->mac_stats.cap_100fdx = 0; 4164 statsp->mac_stats.cap_100hdx = 0; 4165 statsp->mac_stats.cap_10fdx = 0; 4166 statsp->mac_stats.cap_10hdx = 0; 4167 statsp->mac_stats.cap_asmpause = param_arr[param_anar_asmpause].value; 4168 statsp->mac_stats.cap_pause = param_arr[param_anar_pause].value; 4169 4170 /* 4171 * Initialize the xcvr advertised capability statistics. 4172 */ 4173 statsp->mac_stats.adv_cap_autoneg = param_arr[param_autoneg].value; 4174 statsp->mac_stats.adv_cap_1000fdx = param_arr[param_anar_1000fdx].value; 4175 statsp->mac_stats.adv_cap_1000hdx = param_arr[param_anar_1000hdx].value; 4176 statsp->mac_stats.adv_cap_100T4 = param_arr[param_anar_100T4].value; 4177 statsp->mac_stats.adv_cap_100fdx = param_arr[param_anar_100fdx].value; 4178 statsp->mac_stats.adv_cap_100hdx = param_arr[param_anar_100hdx].value; 4179 statsp->mac_stats.adv_cap_10fdx = param_arr[param_anar_10fdx].value; 4180 statsp->mac_stats.adv_cap_10hdx = param_arr[param_anar_10hdx].value; 4181 statsp->mac_stats.adv_cap_asmpause = 4182 param_arr[param_anar_asmpause].value; 4183 statsp->mac_stats.adv_cap_pause = param_arr[param_anar_pause].value; 4184 4185 /* 4186 * Check for extended status just in case we're 4187 * running a Gigibit phy. 4188 */ 4189 if (bmsr.bits.extend_status) { 4190 #if defined(__i386) 4191 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4192 (uint8_t)(uint32_t)(&mii_regs->esr), &esr.value)) != 4193 NXGE_OK) 4194 goto fail; 4195 #else 4196 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4197 (uint8_t)(uint64_t)(&mii_regs->esr), &esr.value)) != 4198 NXGE_OK) 4199 goto fail; 4200 #endif 4201 param_arr[param_anar_1000fdx].value &= 4202 esr.bits.link_1000fdx; 4203 param_arr[param_anar_1000hdx].value = 0; 4204 4205 statsp->mac_stats.cap_1000fdx = 4206 (esr.bits.link_1000Xfdx || esr.bits.link_1000fdx); 4207 statsp->mac_stats.cap_1000hdx = 0; 4208 } else { 4209 param_arr[param_anar_1000fdx].value = 0; 4210 param_arr[param_anar_1000hdx].value = 0; 4211 } 4212 4213 /* 4214 * Initialize 1G Statistics once the capability is established. 4215 */ 4216 statsp->mac_stats.adv_cap_1000fdx = param_arr[param_anar_1000fdx].value; 4217 statsp->mac_stats.adv_cap_1000hdx = param_arr[param_anar_1000hdx].value; 4218 4219 /* 4220 * Initialize the link statistics. 4221 */ 4222 statsp->mac_stats.link_T4 = 0; 4223 statsp->mac_stats.link_asmpause = 0; 4224 statsp->mac_stats.link_pause = 0; 4225 statsp->mac_stats.link_speed = 0; 4226 statsp->mac_stats.link_duplex = 0; 4227 statsp->mac_stats.link_up = 0; 4228 4229 /* 4230 * Switch off Auto-negotiation, 100M and full duplex. 4231 */ 4232 bmcr.value = 0; 4233 #if defined(__i386) 4234 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4235 (uint8_t)(uint32_t)(&mii_regs->bmcr), bmcr.value)) != NXGE_OK) 4236 goto fail; 4237 #else 4238 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4239 (uint8_t)(uint64_t)(&mii_regs->bmcr), bmcr.value)) != NXGE_OK) 4240 goto fail; 4241 #endif 4242 4243 if ((statsp->port_stats.lb_mode == nxge_lb_phy) || 4244 (statsp->port_stats.lb_mode == nxge_lb_phy1000)) { 4245 bmcr.bits.loopback = 1; 4246 bmcr.bits.enable_autoneg = 0; 4247 if (statsp->port_stats.lb_mode == nxge_lb_phy1000) 4248 bmcr.bits.speed_1000_sel = 1; 4249 bmcr.bits.duplex_mode = 1; 4250 param_arr[param_autoneg].value = 0; 4251 } else { 4252 bmcr.bits.loopback = 0; 4253 } 4254 4255 if (statsp->port_stats.lb_mode == nxge_lb_ext1000) { 4256 param_arr[param_autoneg].value = 0; 4257 bcm5464r_aux.value = 0; 4258 bcm5464r_aux.bits.ext_lb = 1; 4259 bcm5464r_aux.bits.write_1 = 1; 4260 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4261 BCM5464R_AUX_CTL, bcm5464r_aux.value)) != NXGE_OK) 4262 goto fail; 4263 } 4264 4265 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "Going into forced mode.")); 4266 bmcr.bits.speed_1000_sel = 1; 4267 bmcr.bits.speed_sel = 0; 4268 bmcr.bits.duplex_mode = 1; 4269 statsp->mac_stats.link_speed = 1000; 4270 statsp->mac_stats.link_duplex = 2; 4271 4272 if ((statsp->port_stats.lb_mode == nxge_lb_ext1000)) { 4273 /* BCM5464R 1000mbps external loopback mode */ 4274 gcr.value = 0; 4275 gcr.bits.ms_mode_en = 1; 4276 gcr.bits.master = 1; 4277 #if defined(__i386) 4278 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4279 (uint8_t)(uint32_t)(&mii_regs->gcr), 4280 gcr.value)) != NXGE_OK) 4281 goto fail; 4282 #else 4283 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4284 (uint8_t)(uint64_t)(&mii_regs->gcr), 4285 gcr.value)) != NXGE_OK) 4286 goto fail; 4287 #endif 4288 bmcr.value = 0; 4289 bmcr.bits.speed_1000_sel = 1; 4290 statsp->mac_stats.link_speed = 1000; 4291 } 4292 4293 #if defined(__i386) 4294 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4295 (uint8_t)(uint32_t)(&mii_regs->bmcr), 4296 bmcr.value)) != NXGE_OK) 4297 goto fail; 4298 #else 4299 if ((status = nxge_mii_write(nxgep, xcvr_portn, 4300 (uint8_t)(uint64_t)(&mii_regs->bmcr), 4301 bmcr.value)) != NXGE_OK) 4302 goto fail; 4303 #endif 4304 4305 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4306 "nxge_mii_xcvr_fiber_init: value wrote bmcr = 0x%x", 4307 bmcr.value)); 4308 4309 #if defined(__i386) 4310 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4311 (uint8_t)(uint32_t)(&mii_regs->bmcr), &bmcr.value)) != NXGE_OK) 4312 goto fail; 4313 #else 4314 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4315 (uint8_t)(uint64_t)(&mii_regs->bmcr), &bmcr.value)) != NXGE_OK) 4316 goto fail; 4317 #endif 4318 4319 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4320 "nxge_mii_xcvr_fiber_init: read bmcr = 0x%04X", bmcr.value)); 4321 4322 /* 4323 * Initialize the xcvr status kept in the context structure. 4324 */ 4325 nxgep->soft_bmsr.value = 0; 4326 #if defined(__i386) 4327 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4328 (uint8_t)(uint32_t)(&mii_regs->bmsr), 4329 &nxgep->bmsr.value)) != NXGE_OK) 4330 goto fail; 4331 #else 4332 if ((status = nxge_mii_read(nxgep, xcvr_portn, 4333 (uint8_t)(uint64_t)(&mii_regs->bmsr), 4334 &nxgep->bmsr.value)) != NXGE_OK) 4335 goto fail; 4336 #endif 4337 4338 statsp->mac_stats.xcvr_inits++; 4339 nxgep->bmsr.value = 0; 4340 4341 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4342 "<== nxge_mii_xcvr_fiber_init status 0x%x", status)); 4343 return (status); 4344 4345 fail: 4346 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4347 "<== nxge_mii_xcvr_fiber_init status 0x%x", status)); 4348 return (status); 4349 } 4350 4351 /* Read from a MII compliant register */ 4352 4353 nxge_status_t 4354 nxge_mii_read(p_nxge_t nxgep, uint8_t xcvr_portn, uint8_t xcvr_reg, 4355 uint16_t *value) 4356 { 4357 npi_status_t rs = NPI_SUCCESS; 4358 4359 NXGE_DEBUG_MSG((nxgep, MIF_CTL, "==> nxge_mii_read: xcvr_port<%d>" 4360 "xcvr_reg<%d>", xcvr_portn, xcvr_reg)); 4361 4362 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_mdio_lock); 4363 4364 if ((nxgep->mac.portmode == PORT_1G_COPPER) || 4365 (nxgep->mac.portmode == PORT_1G_RGMII_FIBER)) { 4366 if ((rs = npi_mac_mif_mii_read(nxgep->npi_handle, 4367 xcvr_portn, xcvr_reg, value)) != NPI_SUCCESS) 4368 goto fail; 4369 } else if ((nxgep->mac.portmode == PORT_1G_FIBER) || 4370 (nxgep->mac.portmode == PORT_1G_SERDES)) { 4371 if ((rs = npi_mac_pcs_mii_read(nxgep->npi_handle, 4372 xcvr_portn, xcvr_reg, value)) != NPI_SUCCESS) 4373 goto fail; 4374 } else 4375 goto fail; 4376 4377 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 4378 4379 NXGE_DEBUG_MSG((nxgep, MIF_CTL, "<== nxge_mii_read: xcvr_port<%d>" 4380 "xcvr_reg<%d> value=0x%x", xcvr_portn, xcvr_reg, *value)); 4381 return (NXGE_OK); 4382 fail: 4383 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 4384 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4385 "nxge_mii_read: Failed to read mii on xcvr %d", xcvr_portn)); 4386 4387 return (NXGE_ERROR | rs); 4388 } 4389 4390 /* Write to a MII compliant Register */ 4391 4392 nxge_status_t 4393 nxge_mii_write(p_nxge_t nxgep, uint8_t xcvr_portn, uint8_t xcvr_reg, 4394 uint16_t value) 4395 { 4396 npi_status_t rs = NPI_SUCCESS; 4397 4398 NXGE_DEBUG_MSG((nxgep, MIF_CTL, "==> nxge_mii_write: xcvr_port<%d>" 4399 "xcvr_reg<%d> value=0x%x", xcvr_portn, xcvr_reg, value)); 4400 4401 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_mdio_lock); 4402 4403 if ((nxgep->mac.portmode == PORT_1G_COPPER) || 4404 (nxgep->mac.portmode == PORT_1G_RGMII_FIBER)) { 4405 if ((rs = npi_mac_mif_mii_write(nxgep->npi_handle, 4406 xcvr_portn, xcvr_reg, value)) != NPI_SUCCESS) 4407 goto fail; 4408 } else if ((nxgep->mac.portmode == PORT_1G_FIBER) || 4409 (nxgep->mac.portmode == PORT_1G_SERDES)) { 4410 if ((rs = npi_mac_pcs_mii_write(nxgep->npi_handle, 4411 xcvr_portn, xcvr_reg, value)) != NPI_SUCCESS) 4412 goto fail; 4413 } else 4414 goto fail; 4415 4416 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 4417 4418 NXGE_DEBUG_MSG((nxgep, MIF_CTL, "<== nxge_mii_write: xcvr_port<%d>" 4419 "xcvr_reg<%d>", xcvr_portn, xcvr_reg)); 4420 return (NXGE_OK); 4421 fail: 4422 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 4423 4424 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4425 "nxge_mii_write: Failed to write mii on xcvr %d", xcvr_portn)); 4426 4427 return (NXGE_ERROR | rs); 4428 } 4429 4430 /* 4431 * Perform write to Clause45 serdes / transceiver device 4432 * Arguments: 4433 * xcvr_portn: The IEEE 802.3 Clause45 PHYAD, it is the same as port 4434 * number if nxge_mdio_write is used for accessing the 4435 * internal LSIL serdes. Otherwise PHYAD is different 4436 * for different platforms. 4437 * device: With each PHYAD, the driver can use MDIO to control 4438 * multiple devices inside the PHY, here "device" is an 4439 * MMD (MDIO managable device). 4440 * xcvr_reg: Each device has multiple registers. xcvr_reg specifies 4441 * the register which the driver will write value to. 4442 * value: The register value will be filled in. 4443 */ 4444 nxge_status_t 4445 nxge_mdio_read(p_nxge_t nxgep, uint8_t xcvr_portn, uint8_t device, 4446 uint16_t xcvr_reg, uint16_t *value) 4447 { 4448 npi_status_t rs = NPI_SUCCESS; 4449 4450 NXGE_DEBUG_MSG((nxgep, MIF_CTL, "==> nxge_mdio_read: xcvr_port<%d>", 4451 xcvr_portn)); 4452 4453 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_mdio_lock); 4454 4455 if ((rs = npi_mac_mif_mdio_read(nxgep->npi_handle, 4456 xcvr_portn, device, xcvr_reg, value)) != NPI_SUCCESS) 4457 goto fail; 4458 4459 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 4460 4461 NXGE_DEBUG_MSG((nxgep, MIF_CTL, "<== nxge_mdio_read: xcvr_port<%d>", 4462 xcvr_portn)); 4463 return (NXGE_OK); 4464 fail: 4465 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 4466 4467 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4468 "nxge_mdio_read: Failed to read mdio on xcvr %d", xcvr_portn)); 4469 4470 return (NXGE_ERROR | rs); 4471 } 4472 4473 /* Perform write to Clause45 serdes / transceiver device */ 4474 4475 nxge_status_t 4476 nxge_mdio_write(p_nxge_t nxgep, uint8_t xcvr_portn, uint8_t device, 4477 uint16_t xcvr_reg, uint16_t value) 4478 { 4479 npi_status_t rs = NPI_SUCCESS; 4480 4481 NXGE_DEBUG_MSG((nxgep, MIF_CTL, "==> nxge_mdio_write: xcvr_port<%d>", 4482 xcvr_portn)); 4483 4484 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_mdio_lock); 4485 4486 if ((rs = npi_mac_mif_mdio_write(nxgep->npi_handle, 4487 xcvr_portn, device, xcvr_reg, value)) != NPI_SUCCESS) 4488 goto fail; 4489 4490 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 4491 4492 NXGE_DEBUG_MSG((nxgep, MIF_CTL, "<== nxge_mdio_write: xcvr_port<%d>", 4493 xcvr_portn)); 4494 return (NXGE_OK); 4495 fail: 4496 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 4497 4498 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4499 "nxge_mdio_write: Failed to write mdio on xcvr %d", xcvr_portn)); 4500 4501 return (NXGE_ERROR | rs); 4502 } 4503 4504 4505 /* Check MII to see if there is any link status change */ 4506 4507 nxge_status_t 4508 nxge_mii_check(p_nxge_t nxgep, mii_bmsr_t bmsr, mii_bmsr_t bmsr_ints, 4509 nxge_link_state_t *link_up) 4510 { 4511 p_nxge_param_t param_arr; 4512 p_nxge_stats_t statsp; 4513 p_mii_regs_t mii_regs; 4514 p_mii_bmsr_t soft_bmsr; 4515 mii_anar_t anar; 4516 mii_anlpar_t anlpar; 4517 mii_anar_t an_common; 4518 mii_aner_t aner; 4519 mii_gsr_t gsr; 4520 nxge_status_t status = NXGE_OK; 4521 4522 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_mii_check")); 4523 4524 mii_regs = NULL; 4525 param_arr = nxgep->param_arr; 4526 statsp = nxgep->statsp; 4527 soft_bmsr = &nxgep->soft_bmsr; 4528 *link_up = LINK_NO_CHANGE; 4529 4530 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4531 "==> nxge_mii_check bmsr 0x%x bmsr_int 0x%x", 4532 bmsr.value, bmsr_ints.value)); 4533 4534 if (bmsr_ints.bits.link_status) { 4535 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4536 "==> nxge_mii_check (link up) bmsr 0x%x bmsr_int 0x%x", 4537 bmsr.value, bmsr_ints.value)); 4538 if (bmsr.bits.link_status) { 4539 soft_bmsr->bits.link_status = 1; 4540 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4541 "==> nxge_mii_check (link up) soft bmsr 0x%x bmsr_int " 4542 "0x%x", bmsr.value, bmsr_ints.value)); 4543 } else { 4544 statsp->mac_stats.link_up = 0; 4545 soft_bmsr->bits.link_status = 0; 4546 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4547 "Link down cable problem")); 4548 *link_up = LINK_IS_DOWN; 4549 } 4550 } 4551 4552 if (nxgep->mac.portmode == PORT_1G_COPPER && 4553 param_arr[param_autoneg].value) { 4554 if (bmsr_ints.bits.auto_neg_complete) { 4555 if (bmsr.bits.auto_neg_complete) 4556 soft_bmsr->bits.auto_neg_complete = 1; 4557 else 4558 soft_bmsr->bits.auto_neg_complete = 0; 4559 } 4560 if (soft_bmsr->bits.link_status == 0) { 4561 statsp->mac_stats.link_T4 = 0; 4562 statsp->mac_stats.link_speed = 0; 4563 statsp->mac_stats.link_duplex = 0; 4564 statsp->mac_stats.link_asmpause = 0; 4565 statsp->mac_stats.link_pause = 0; 4566 statsp->mac_stats.lp_cap_autoneg = 0; 4567 statsp->mac_stats.lp_cap_100T4 = 0; 4568 statsp->mac_stats.lp_cap_1000fdx = 0; 4569 statsp->mac_stats.lp_cap_1000hdx = 0; 4570 statsp->mac_stats.lp_cap_100fdx = 0; 4571 statsp->mac_stats.lp_cap_100hdx = 0; 4572 statsp->mac_stats.lp_cap_10fdx = 0; 4573 statsp->mac_stats.lp_cap_10hdx = 0; 4574 statsp->mac_stats.lp_cap_10gfdx = 0; 4575 statsp->mac_stats.lp_cap_10ghdx = 0; 4576 statsp->mac_stats.lp_cap_asmpause = 0; 4577 statsp->mac_stats.lp_cap_pause = 0; 4578 } 4579 } else 4580 soft_bmsr->bits.auto_neg_complete = 1; 4581 4582 if ((bmsr_ints.bits.link_status || 4583 bmsr_ints.bits.auto_neg_complete) && 4584 soft_bmsr->bits.link_status && 4585 soft_bmsr->bits.auto_neg_complete) { 4586 statsp->mac_stats.link_up = 1; 4587 4588 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4589 "==> nxge_mii_check " 4590 "(auto negotiation complete or link up) " 4591 "soft bmsr 0x%x bmsr_int 0x%x", 4592 bmsr.value, bmsr_ints.value)); 4593 4594 if (nxgep->mac.portmode == PORT_1G_COPPER && 4595 param_arr[param_autoneg].value) { 4596 if ((status = nxge_mii_read(nxgep, 4597 statsp->mac_stats.xcvr_portn, 4598 #if defined(__i386) 4599 (uint8_t)(uint32_t)(&mii_regs->anar), 4600 #else 4601 (uint8_t)(uint64_t)(&mii_regs->anar), 4602 #endif 4603 &anar.value)) != NXGE_OK) 4604 goto fail; 4605 if ((status = nxge_mii_read(nxgep, 4606 statsp->mac_stats.xcvr_portn, 4607 #if defined(__i386) 4608 (uint8_t)(uint32_t)(&mii_regs->anlpar), 4609 #else 4610 (uint8_t)(uint64_t)(&mii_regs->anlpar), 4611 #endif 4612 &anlpar.value)) != NXGE_OK) 4613 goto fail; 4614 if ((status = nxge_mii_read(nxgep, 4615 statsp->mac_stats.xcvr_portn, 4616 #if defined(__i386) 4617 (uint8_t)(uint32_t)(&mii_regs->aner), 4618 #else 4619 (uint8_t)(uint64_t)(&mii_regs->aner), 4620 #endif 4621 &aner.value)) != NXGE_OK) 4622 goto fail; 4623 statsp->mac_stats.lp_cap_autoneg = aner.bits.lp_an_able; 4624 statsp->mac_stats.lp_cap_100T4 = anlpar.bits.cap_100T4; 4625 statsp->mac_stats.lp_cap_100fdx = 4626 anlpar.bits.cap_100fdx; 4627 statsp->mac_stats.lp_cap_100hdx = 4628 anlpar.bits.cap_100hdx; 4629 statsp->mac_stats.lp_cap_10fdx = anlpar.bits.cap_10fdx; 4630 statsp->mac_stats.lp_cap_10hdx = anlpar.bits.cap_10hdx; 4631 statsp->mac_stats.lp_cap_asmpause = 4632 anlpar.bits.cap_asmpause; 4633 statsp->mac_stats.lp_cap_pause = anlpar.bits.cap_pause; 4634 an_common.value = anar.value & anlpar.value; 4635 if (param_arr[param_anar_1000fdx].value || 4636 param_arr[param_anar_1000hdx].value) { 4637 if ((status = nxge_mii_read(nxgep, 4638 statsp->mac_stats.xcvr_portn, 4639 #if defined(__i386) 4640 (uint8_t)(uint32_t)(&mii_regs->gsr), 4641 #else 4642 (uint8_t)(uint64_t)(&mii_regs->gsr), 4643 #endif 4644 &gsr.value)) != NXGE_OK) 4645 goto fail; 4646 statsp->mac_stats.lp_cap_1000fdx = 4647 gsr.bits.link_1000fdx; 4648 statsp->mac_stats.lp_cap_1000hdx = 4649 gsr.bits.link_1000hdx; 4650 if (param_arr[param_anar_1000fdx].value && 4651 gsr.bits.link_1000fdx) { 4652 statsp->mac_stats.link_speed = 1000; 4653 statsp->mac_stats.link_duplex = 2; 4654 } else if ( 4655 param_arr[param_anar_1000hdx].value && 4656 gsr.bits.link_1000hdx) { 4657 statsp->mac_stats.link_speed = 1000; 4658 statsp->mac_stats.link_duplex = 1; 4659 } 4660 } 4661 if ((an_common.value != 0) && 4662 !(statsp->mac_stats.link_speed)) { 4663 if (an_common.bits.cap_100T4) { 4664 statsp->mac_stats.link_T4 = 1; 4665 statsp->mac_stats.link_speed = 100; 4666 statsp->mac_stats.link_duplex = 1; 4667 } else if (an_common.bits.cap_100fdx) { 4668 statsp->mac_stats.link_speed = 100; 4669 statsp->mac_stats.link_duplex = 2; 4670 } else if (an_common.bits.cap_100hdx) { 4671 statsp->mac_stats.link_speed = 100; 4672 statsp->mac_stats.link_duplex = 1; 4673 } else if (an_common.bits.cap_10fdx) { 4674 statsp->mac_stats.link_speed = 10; 4675 statsp->mac_stats.link_duplex = 2; 4676 } else if (an_common.bits.cap_10hdx) { 4677 statsp->mac_stats.link_speed = 10; 4678 statsp->mac_stats.link_duplex = 1; 4679 } else { 4680 goto fail; 4681 } 4682 } 4683 if (statsp->mac_stats.link_duplex != 1) { 4684 int link_pause; 4685 int cp, lcp; 4686 4687 statsp->mac_stats.link_asmpause = 4688 an_common.bits.cap_asmpause; 4689 cp = statsp->mac_stats.cap_pause; 4690 lcp = statsp->mac_stats.lp_cap_pause; 4691 if (statsp->mac_stats.link_asmpause) { 4692 if ((cp == 0) && (lcp == 1)) { 4693 link_pause = 0; 4694 } else { 4695 link_pause = 1; 4696 } 4697 } else { 4698 link_pause = an_common.bits.cap_pause; 4699 } 4700 statsp->mac_stats.link_pause = link_pause; 4701 } 4702 } else if (nxgep->mac.portmode == PORT_1G_RGMII_FIBER) { 4703 statsp->mac_stats.link_speed = 1000; 4704 statsp->mac_stats.link_duplex = 2; 4705 } 4706 *link_up = LINK_IS_UP; 4707 } 4708 4709 if (nxgep->link_notify) { 4710 *link_up = ((statsp->mac_stats.link_up) ? LINK_IS_UP : 4711 LINK_IS_DOWN); 4712 nxgep->link_notify = B_FALSE; 4713 } 4714 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_mii_check")); 4715 return (NXGE_OK); 4716 fail: 4717 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4718 "nxge_mii_check: Unable to check MII")); 4719 return (status); 4720 } 4721 4722 /* 4723 * Check PCS to see if there is any link status change. 4724 * This function is called by PORT_1G_SERDES only. 4725 */ 4726 void 4727 nxge_pcs_check(p_nxge_t nxgep, uint8_t portn, nxge_link_state_t *link_up) 4728 { 4729 p_nxge_stats_t statsp; 4730 boolean_t linkup; 4731 4732 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_pcs_check")); 4733 4734 statsp = nxgep->statsp; 4735 *link_up = LINK_NO_CHANGE; 4736 4737 (void) npi_mac_get_link_status(nxgep->npi_handle, portn, &linkup); 4738 if (linkup) { 4739 if (nxgep->link_notify || 4740 nxgep->statsp->mac_stats.link_up == 0) { 4741 statsp->mac_stats.link_up = 1; 4742 statsp->mac_stats.link_speed = 1000; 4743 statsp->mac_stats.link_duplex = 2; 4744 *link_up = LINK_IS_UP; 4745 nxgep->link_notify = B_FALSE; 4746 } 4747 } else { 4748 if (nxgep->link_notify || 4749 nxgep->statsp->mac_stats.link_up == 1) { 4750 statsp->mac_stats.link_up = 0; 4751 statsp->mac_stats.link_speed = 0; 4752 statsp->mac_stats.link_duplex = 0; 4753 *link_up = LINK_IS_DOWN; 4754 nxgep->link_notify = B_FALSE; 4755 } 4756 } 4757 4758 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_pcs_check")); 4759 } 4760 4761 /* Add a multicast address entry into the HW hash table */ 4762 4763 nxge_status_t 4764 nxge_add_mcast_addr(p_nxge_t nxgep, struct ether_addr *addrp) 4765 { 4766 uint32_t mchash; 4767 p_hash_filter_t hash_filter; 4768 uint16_t hash_bit; 4769 boolean_t rx_init = B_FALSE; 4770 uint_t j; 4771 nxge_status_t status = NXGE_OK; 4772 4773 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_add_mcast_addr")); 4774 4775 RW_ENTER_WRITER(&nxgep->filter_lock); 4776 mchash = crc32_mchash(addrp); 4777 if (nxgep->hash_filter == NULL) { 4778 NXGE_DEBUG_MSG((NULL, STR_CTL, 4779 "Allocating hash filter storage.")); 4780 nxgep->hash_filter = KMEM_ZALLOC(sizeof (hash_filter_t), 4781 KM_SLEEP); 4782 } 4783 hash_filter = nxgep->hash_filter; 4784 j = mchash / HASH_REG_WIDTH; 4785 hash_bit = (1 << (mchash % HASH_REG_WIDTH)); 4786 hash_filter->hash_filter_regs[j] |= hash_bit; 4787 hash_filter->hash_bit_ref_cnt[mchash]++; 4788 if (hash_filter->hash_bit_ref_cnt[mchash] == 1) { 4789 hash_filter->hash_ref_cnt++; 4790 rx_init = B_TRUE; 4791 } 4792 if (rx_init) { 4793 if ((status = nxge_rx_mac_disable(nxgep)) != NXGE_OK) 4794 goto fail; 4795 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) 4796 goto fail; 4797 } 4798 4799 RW_EXIT(&nxgep->filter_lock); 4800 4801 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_add_mcast_addr")); 4802 4803 return (NXGE_OK); 4804 fail: 4805 RW_EXIT(&nxgep->filter_lock); 4806 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_add_mcast_addr: " 4807 "Unable to add multicast address")); 4808 return (status); 4809 } 4810 4811 /* Remove a multicast address entry from the HW hash table */ 4812 4813 nxge_status_t 4814 nxge_del_mcast_addr(p_nxge_t nxgep, struct ether_addr *addrp) 4815 { 4816 uint32_t mchash; 4817 p_hash_filter_t hash_filter; 4818 uint16_t hash_bit; 4819 boolean_t rx_init = B_FALSE; 4820 uint_t j; 4821 nxge_status_t status = NXGE_OK; 4822 4823 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_del_mcast_addr")); 4824 RW_ENTER_WRITER(&nxgep->filter_lock); 4825 mchash = crc32_mchash(addrp); 4826 if (nxgep->hash_filter == NULL) { 4827 NXGE_DEBUG_MSG((NULL, STR_CTL, 4828 "Hash filter already de_allocated.")); 4829 RW_EXIT(&nxgep->filter_lock); 4830 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_del_mcast_addr")); 4831 return (NXGE_OK); 4832 } 4833 hash_filter = nxgep->hash_filter; 4834 hash_filter->hash_bit_ref_cnt[mchash]--; 4835 if (hash_filter->hash_bit_ref_cnt[mchash] == 0) { 4836 j = mchash / HASH_REG_WIDTH; 4837 hash_bit = (1 << (mchash % HASH_REG_WIDTH)); 4838 hash_filter->hash_filter_regs[j] &= ~hash_bit; 4839 hash_filter->hash_ref_cnt--; 4840 rx_init = B_TRUE; 4841 } 4842 if (hash_filter->hash_ref_cnt == 0) { 4843 NXGE_DEBUG_MSG((NULL, STR_CTL, 4844 "De-allocating hash filter storage.")); 4845 KMEM_FREE(hash_filter, sizeof (hash_filter_t)); 4846 nxgep->hash_filter = NULL; 4847 } 4848 4849 if (rx_init) { 4850 if ((status = nxge_rx_mac_disable(nxgep)) != NXGE_OK) 4851 goto fail; 4852 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) 4853 goto fail; 4854 } 4855 RW_EXIT(&nxgep->filter_lock); 4856 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_del_mcast_addr")); 4857 4858 return (NXGE_OK); 4859 fail: 4860 RW_EXIT(&nxgep->filter_lock); 4861 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_del_mcast_addr: " 4862 "Unable to remove multicast address")); 4863 4864 return (status); 4865 } 4866 4867 /* Set MAC address into MAC address HW registers */ 4868 4869 nxge_status_t 4870 nxge_set_mac_addr(p_nxge_t nxgep, struct ether_addr *addrp) 4871 { 4872 nxge_status_t status = NXGE_OK; 4873 4874 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_set_mac_addr")); 4875 4876 MUTEX_ENTER(&nxgep->ouraddr_lock); 4877 /* 4878 * Exit if the address is same as ouraddr or multicast or broadcast 4879 */ 4880 if (((addrp->ether_addr_octet[0] & 01) == 1) || 4881 (ether_cmp(addrp, ðerbroadcastaddr) == 0) || 4882 (ether_cmp(addrp, &nxgep->ouraddr) == 0)) { 4883 goto nxge_set_mac_addr_exit; 4884 } 4885 nxgep->ouraddr = *addrp; 4886 /* 4887 * Set new interface local address and re-init device. 4888 * This is destructive to any other streams attached 4889 * to this device. 4890 */ 4891 RW_ENTER_WRITER(&nxgep->filter_lock); 4892 if ((status = nxge_rx_mac_disable(nxgep)) != NXGE_OK) 4893 goto fail; 4894 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) 4895 goto fail; 4896 4897 RW_EXIT(&nxgep->filter_lock); 4898 MUTEX_EXIT(&nxgep->ouraddr_lock); 4899 goto nxge_set_mac_addr_end; 4900 nxge_set_mac_addr_exit: 4901 MUTEX_EXIT(&nxgep->ouraddr_lock); 4902 nxge_set_mac_addr_end: 4903 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_set_mac_addr")); 4904 4905 return (NXGE_OK); 4906 fail: 4907 MUTEX_EXIT(&nxgep->ouraddr_lock); 4908 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_set_mac_addr: " 4909 "Unable to set mac address")); 4910 return (status); 4911 } 4912 4913 static 4914 check_link_state_t 4915 nxge_check_link_stop(nxge_t *nxge) 4916 { 4917 /* If the poll has been cancelled, return STOP. */ 4918 MUTEX_ENTER(&nxge->poll_lock); 4919 if (nxge->suspended || nxge->poll_state == LINK_MONITOR_STOPPING) { 4920 nxge->poll_state = LINK_MONITOR_STOP; 4921 nxge->nxge_link_poll_timerid = 0; 4922 cv_broadcast(&nxge->poll_cv); 4923 MUTEX_EXIT(&nxge->poll_lock); 4924 4925 NXGE_DEBUG_MSG((nxge, MAC_CTL, 4926 "nxge_check_%s_link(port<%d>) stopped.", 4927 nxge->mac.portmode == PORT_10G_FIBER ? "10g" : "mii", 4928 nxge->mac.portnum)); 4929 return (CHECK_LINK_STOP); 4930 } 4931 MUTEX_EXIT(&nxge->poll_lock); 4932 4933 return (CHECK_LINK_RESCHEDULE); 4934 } 4935 4936 /* 4937 * Check status of MII (MIF or PCS) link. 4938 * This function is called once per second, that is because this function 4939 * calls nxge_link_monitor with LINK_MONITOR_START, which starts a timer to 4940 * call this function recursively. 4941 */ 4942 static nxge_status_t 4943 nxge_check_mii_link(p_nxge_t nxgep) 4944 { 4945 mii_bmsr_t bmsr_ints, bmsr_data; 4946 mii_anlpar_t anlpar; 4947 mii_gsr_t gsr; 4948 p_mii_regs_t mii_regs; 4949 nxge_status_t status = NXGE_OK; 4950 uint8_t portn; 4951 nxge_link_state_t link_up; 4952 4953 if (nxgep->nxge_magic != NXGE_MAGIC) 4954 return (NXGE_ERROR); 4955 4956 if (nxge_check_link_stop(nxgep) == CHECK_LINK_STOP) 4957 return (NXGE_OK); 4958 4959 portn = nxgep->mac.portnum; 4960 4961 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_check_mii_link port<%d>", 4962 portn)); 4963 4964 mii_regs = NULL; 4965 4966 RW_ENTER_WRITER(&nxgep->filter_lock); 4967 4968 if (nxgep->statsp->port_stats.lb_mode > nxge_lb_ext10) 4969 goto nxge_check_mii_link_exit; 4970 4971 switch (nxgep->mac.portmode) { 4972 default: 4973 bmsr_data.value = 0; 4974 if ((status = nxge_mii_read(nxgep, 4975 nxgep->statsp->mac_stats.xcvr_portn, 4976 #if defined(__i386) 4977 (uint8_t)(uint32_t)(&mii_regs->bmsr), 4978 #else 4979 (uint8_t)(uint64_t)(&mii_regs->bmsr), 4980 #endif 4981 &bmsr_data.value)) != NXGE_OK) { 4982 goto fail; 4983 } 4984 4985 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 4986 "==> nxge_check_mii_link port<0x%x> " 4987 "RIGHT AFTER READ bmsr_data 0x%x (nxgep->bmsr 0x%x ", 4988 portn, bmsr_data.value, nxgep->bmsr.value)); 4989 4990 if (nxgep->param_arr[param_autoneg].value) { 4991 if ((status = nxge_mii_read(nxgep, 4992 nxgep->statsp->mac_stats.xcvr_portn, 4993 #if defined(__i386) 4994 (uint8_t)(uint32_t)(&mii_regs->gsr), 4995 #else 4996 (uint8_t)(uint64_t)(&mii_regs->gsr), 4997 #endif 4998 &gsr.value)) != NXGE_OK) 4999 goto fail; 5000 if ((status = nxge_mii_read(nxgep, 5001 nxgep->statsp->mac_stats.xcvr_portn, 5002 #if defined(__i386) 5003 (uint8_t)(uint32_t)(&mii_regs->anlpar), 5004 #else 5005 (uint8_t)(uint64_t)(&mii_regs->anlpar), 5006 #endif 5007 &anlpar.value)) != NXGE_OK) 5008 goto fail; 5009 if (nxgep->mac.portmode != PORT_1G_RGMII_FIBER) { 5010 5011 if (nxgep->statsp->mac_stats.link_up && 5012 ((nxgep->statsp->mac_stats.lp_cap_1000fdx ^ 5013 gsr.bits.link_1000fdx) || 5014 (nxgep->statsp->mac_stats.lp_cap_1000hdx ^ 5015 gsr.bits.link_1000hdx) || 5016 (nxgep->statsp->mac_stats.lp_cap_100T4 ^ 5017 anlpar.bits.cap_100T4) || 5018 (nxgep->statsp->mac_stats.lp_cap_100fdx ^ 5019 anlpar.bits.cap_100fdx) || 5020 (nxgep->statsp->mac_stats.lp_cap_100hdx ^ 5021 anlpar.bits.cap_100hdx) || 5022 (nxgep->statsp->mac_stats.lp_cap_10fdx ^ 5023 anlpar.bits.cap_10fdx) || 5024 (nxgep->statsp->mac_stats.lp_cap_10hdx ^ 5025 anlpar.bits.cap_10hdx))) { 5026 bmsr_data.bits.link_status = 0; 5027 } 5028 } 5029 } 5030 5031 /* Workaround for link down issue */ 5032 if (bmsr_data.value == 0) { 5033 cmn_err(CE_NOTE, "!LINK DEBUG: Read zero bmsr\n"); 5034 goto nxge_check_mii_link_exit; 5035 } 5036 5037 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5038 "==> nxge_check_mii_link port<0x%x> :" 5039 "BEFORE BMSR ^ nxgep->bmsr 0x%x bmsr_data 0x%x", 5040 portn, nxgep->bmsr.value, bmsr_data.value)); 5041 5042 bmsr_ints.value = nxgep->bmsr.value ^ bmsr_data.value; 5043 nxgep->bmsr.value = bmsr_data.value; 5044 5045 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5046 "==> nxge_check_mii_link port<0x%x> CALLING " 5047 "bmsr_data 0x%x bmsr_ints.value 0x%x", 5048 portn, bmsr_data.value, bmsr_ints.value)); 5049 5050 if ((status = nxge_mii_check(nxgep, bmsr_data, bmsr_ints, 5051 &link_up)) != NXGE_OK) { 5052 goto fail; 5053 } 5054 break; 5055 5056 case PORT_1G_SERDES: 5057 /* 5058 * Above default is for all cases except PORT_1G_SERDES. 5059 * The default case gets information from the PHY, but a 5060 * nxge whose portmode equals PORT_1G_SERDES does not 5061 * have a PHY. 5062 */ 5063 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5064 "==> nxge_check_mii_link port<%d> (SERDES)", portn)); 5065 nxge_pcs_check(nxgep, portn, &link_up); 5066 break; 5067 } 5068 5069 nxge_check_mii_link_exit: 5070 RW_EXIT(&nxgep->filter_lock); 5071 if (link_up == LINK_IS_UP) { 5072 nxge_link_is_up(nxgep); 5073 } else if (link_up == LINK_IS_DOWN) { 5074 nxge_link_is_down(nxgep); 5075 } 5076 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 5077 5078 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_check_mii_link port<%d>", 5079 portn)); 5080 return (NXGE_OK); 5081 5082 fail: 5083 RW_EXIT(&nxgep->filter_lock); 5084 5085 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 5086 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5087 "nxge_check_mii_link: Failed to check link port<%d>", portn)); 5088 return (status); 5089 } 5090 5091 /*ARGSUSED*/ 5092 static nxge_status_t 5093 nxge_check_10g_link(p_nxge_t nxgep) 5094 { 5095 uint8_t portn; 5096 nxge_status_t status = NXGE_OK; 5097 boolean_t link_up; 5098 uint32_t val; 5099 npi_status_t rs; 5100 5101 if (nxgep->nxge_magic != NXGE_MAGIC) 5102 return (NXGE_ERROR); 5103 5104 if (nxge_check_link_stop(nxgep) == CHECK_LINK_STOP) 5105 return (NXGE_OK); 5106 5107 portn = nxgep->mac.portnum; 5108 val = 0; 5109 rs = NPI_SUCCESS; 5110 5111 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_check_10g_link port<%d>", 5112 portn)); 5113 5114 switch (nxgep->mac.portmode) { 5115 default: 5116 /* 5117 * Check if the phy is present in case of hot swappable phy 5118 */ 5119 if (nxgep->hot_swappable_phy) { 5120 boolean_t phy_present_now = B_FALSE; 5121 5122 /* 5123 * If this is the 2nd Goa port, then check 2 addresses 5124 * to take care of the Goa NEM card requirements. 5125 */ 5126 if (portn == 1) { 5127 if (nxge_is_phy_present(nxgep, 5128 ALT_GOA_CLAUSE45_PORT1_ADDR, 5129 BCM8706_DEV_ID, BCM_PHY_ID_MASK)) { 5130 phy_present_now = B_TRUE; 5131 nxgep->xcvr_addr = 5132 ALT_GOA_CLAUSE45_PORT1_ADDR; 5133 goto phy_check_done; 5134 } 5135 } 5136 if (nxge_is_phy_present(nxgep, 5137 (GOA_CLAUSE45_PORT_ADDR_BASE) + portn, 5138 BCM8706_DEV_ID, BCM_PHY_ID_MASK)) { 5139 nxgep->xcvr_addr = 5140 (GOA_CLAUSE45_PORT_ADDR_BASE) + portn; 5141 phy_present_now = B_TRUE; 5142 } 5143 5144 phy_check_done: 5145 if (nxgep->phy_absent) { 5146 if (phy_present_now) { 5147 /* 5148 * Detect, Initialize phy and do link up 5149 * set xcvr vals, link_init, nxge_init 5150 */ 5151 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5152 "Hot swappable phy DETECTED!!")); 5153 nxgep->phy_absent = B_FALSE; 5154 (void) nxge_xcvr_find(nxgep); 5155 (void) nxge_link_init(nxgep); 5156 if (!(nxgep->drv_state & 5157 STATE_HW_INITIALIZED)) { 5158 status = nxge_init(nxgep); 5159 if (status != NXGE_OK) { 5160 NXGE_ERROR_MSG((nxgep, 5161 NXGE_ERR_CTL, 5162 "Hot swappable " 5163 "phy present, but" 5164 " driver init" 5165 " failed...")); 5166 goto fail; 5167 } 5168 } 5169 } 5170 5171 goto start_link_check; 5172 5173 } else if (!phy_present_now) { 5174 /* 5175 * Phy gone, bring link down reset xcvr vals 5176 */ 5177 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5178 "Hot swappable phy REMOVED!!")); 5179 nxgep->phy_absent = B_TRUE; 5180 nxgep->statsp->mac_stats.link_up = 0; 5181 nxgep->statsp->mac_stats.link_speed = 0; 5182 nxgep->statsp->mac_stats.link_duplex = 0; 5183 nxge_link_is_down(nxgep); 5184 nxgep->link_notify = B_FALSE; 5185 5186 (void) nxge_xcvr_find(nxgep); 5187 5188 goto start_link_check; 5189 5190 } 5191 } 5192 if (nxgep->chip_id == MRVL88X201X_CHIP_ID) { 5193 status = nxge_check_mrvl88x2011_link(nxgep, &link_up); 5194 } else { 5195 status = nxge_check_bcm8704_link(nxgep, &link_up); 5196 } 5197 if (status != NXGE_OK) 5198 goto fail; 5199 break; 5200 case PORT_10G_SERDES: 5201 rs = npi_xmac_xpcs_read(nxgep->npi_handle, nxgep->mac.portnum, 5202 XPCS_REG_STATUS, &val); 5203 if (rs != 0) 5204 goto fail; 5205 5206 link_up = B_FALSE; 5207 if (val & XPCS_STATUS_LANE_ALIGN) { 5208 link_up = B_TRUE; 5209 } 5210 5211 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5212 "==> nxge_check_10g_link port<%d> " 5213 "XPCS_REG_STATUS2 0x%x link_up %d", 5214 portn, val, link_up)); 5215 5216 break; 5217 } 5218 5219 if (link_up) { 5220 if (nxgep->link_notify || 5221 nxgep->statsp->mac_stats.link_up == 0) { 5222 if (nxge_10g_link_led_on(nxgep) != NXGE_OK) 5223 goto fail; 5224 nxgep->statsp->mac_stats.link_up = 1; 5225 nxgep->statsp->mac_stats.link_speed = 10000; 5226 nxgep->statsp->mac_stats.link_duplex = 2; 5227 5228 nxge_link_is_up(nxgep); 5229 nxgep->link_notify = B_FALSE; 5230 } 5231 } else { 5232 if (nxgep->link_notify || 5233 nxgep->statsp->mac_stats.link_up == 1) { 5234 if (nxge_10g_link_led_off(nxgep) != NXGE_OK) 5235 goto fail; 5236 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5237 "Link down cable problem")); 5238 nxgep->statsp->mac_stats.link_up = 0; 5239 nxgep->statsp->mac_stats.link_speed = 0; 5240 nxgep->statsp->mac_stats.link_duplex = 0; 5241 5242 nxge_link_is_down(nxgep); 5243 nxgep->link_notify = B_FALSE; 5244 } 5245 } 5246 5247 start_link_check: 5248 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 5249 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_check_10g_link port<%d>", 5250 portn)); 5251 return (NXGE_OK); 5252 5253 fail: 5254 (void) nxge_check_link_stop(nxgep); 5255 5256 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5257 "nxge_check_10g_link: Failed to check link port<%d>", 5258 portn)); 5259 return (status); 5260 } 5261 5262 5263 /* Declare link down */ 5264 5265 void 5266 nxge_link_is_down(p_nxge_t nxgep) 5267 { 5268 p_nxge_stats_t statsp; 5269 char link_stat_msg[64]; 5270 5271 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_link_is_down")); 5272 5273 statsp = nxgep->statsp; 5274 (void) sprintf(link_stat_msg, "xcvr addr:0x%02x - link is down", 5275 statsp->mac_stats.xcvr_portn); 5276 5277 if (nxge_no_msg == B_FALSE) { 5278 NXGE_ERROR_MSG((nxgep, NXGE_NOTE, "%s", link_stat_msg)); 5279 } 5280 5281 mac_link_update(nxgep->mach, LINK_STATE_DOWN); 5282 5283 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_link_is_down")); 5284 } 5285 5286 /* Declare link up */ 5287 5288 void 5289 nxge_link_is_up(p_nxge_t nxgep) 5290 { 5291 p_nxge_stats_t statsp; 5292 char link_stat_msg[64]; 5293 uint32_t val; 5294 5295 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_link_is_up")); 5296 5297 statsp = nxgep->statsp; 5298 (void) sprintf(link_stat_msg, "xcvr addr:0x%02x - link is up %d Mbps ", 5299 statsp->mac_stats.xcvr_portn, 5300 statsp->mac_stats.link_speed); 5301 5302 if (statsp->mac_stats.link_T4) 5303 (void) strcat(link_stat_msg, "T4"); 5304 else if (statsp->mac_stats.link_duplex == 2) 5305 (void) strcat(link_stat_msg, "full duplex"); 5306 else 5307 (void) strcat(link_stat_msg, "half duplex"); 5308 5309 5310 /* Clean up symbol errors incurred during link transition */ 5311 if ((nxgep->mac.portmode == PORT_10G_FIBER) || 5312 (nxgep->mac.portmode == PORT_10G_SERDES)) { 5313 (void) npi_xmac_xpcs_read(nxgep->npi_handle, nxgep->mac.portnum, 5314 XPCS_REG_SYMBOL_ERR_L0_1_COUNTER, &val); 5315 (void) npi_xmac_xpcs_read(nxgep->npi_handle, nxgep->mac.portnum, 5316 XPCS_REG_SYMBOL_ERR_L2_3_COUNTER, &val); 5317 } 5318 5319 /* 5320 * If the driver was plumbed without a link (therefore auto-negotiation 5321 * could not complete), the driver will detect a link up when a cable 5322 * conneting to a link partner is plugged into the port. By the time 5323 * link-up is detected, auto-negotiation should have completed (The 5324 * TN1010 tries to contact a link partner every 8~24ms). Here we re- 5325 * configure the Neptune/NIU according to the newly negotiated speed. 5326 * This is necessary only for the TN1010 basad device because only the 5327 * TN1010 supports dual speeds. 5328 */ 5329 if (nxgep->mac.portmode == PORT_1G_TN1010 || 5330 nxgep->mac.portmode == PORT_10G_TN1010) { 5331 5332 (void) nxge_set_tn1010_param(nxgep); 5333 5334 /* 5335 * nxge_xcvr_find calls nxge_get_xcvr_type (which sets 5336 * nxgep->portmode) and nxge_setup_xcvr_table (which sets 5337 * the nxgep->xcvr to the proper nxge_xcvr_table_t struct). 5338 */ 5339 if (nxge_xcvr_find(nxgep) != NXGE_OK) { 5340 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5341 "nxge_link_is_up: nxge_xcvr_find failed")); 5342 } 5343 5344 /* nxge_link_init calls nxge_xcvr_init and nxge_serdes_init */ 5345 if (nxge_link_init(nxgep) != NXGE_OK) { 5346 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5347 "nxge_link_is_up: nxge_link_init failed")); 5348 } 5349 5350 /* 5351 * nxge_mac_init calls many subroutines including 5352 * nxge_xif_init which sets XGMII or GMII mode 5353 */ 5354 if (nxge_mac_init(nxgep) != NXGE_OK) { 5355 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5356 "nxge_link_is_up: nxge_mac_init failed")); 5357 } 5358 } else { 5359 (void) nxge_xif_init(nxgep); 5360 } 5361 5362 if (nxge_no_msg == B_FALSE) { 5363 NXGE_ERROR_MSG((nxgep, NXGE_NOTE, "%s", link_stat_msg)); 5364 } 5365 5366 mac_link_update(nxgep->mach, LINK_STATE_UP); 5367 5368 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_link_is_up")); 5369 } 5370 5371 #ifdef NXGE_DEBUG 5372 /* Dump all TN1010 Status registers */ 5373 static void 5374 nxge_dump_tn1010_status_regs(p_nxge_t nxgep) 5375 { 5376 uint16_t val; 5377 5378 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5379 TN1010_PMA_PMD_DEV_ADDR, 1, &val); 5380 cmn_err(CE_NOTE, "PMA status1 = 0x%x", val); 5381 5382 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5383 TN1010_PMA_PMD_DEV_ADDR, 8, &val); 5384 cmn_err(CE_NOTE, "PMA status2 = 0x%x", val); 5385 5386 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5387 TN1010_PMA_PMD_DEV_ADDR, 129, &val); 5388 cmn_err(CE_NOTE, "10BASET-T status = 0x%x", val); 5389 5390 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5391 TN1010_PCS_DEV_ADDR, 1, &val); 5392 cmn_err(CE_NOTE, "PCS status1 = 0x%x", val); 5393 5394 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5395 TN1010_PCS_DEV_ADDR, 8, &val); 5396 cmn_err(CE_NOTE, "PCS status2 = 0x%x", val); 5397 5398 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5399 TN1010_PCS_DEV_ADDR, 32, &val); 5400 cmn_err(CE_NOTE, "10GBASE-R status1 = 0x%x", val); 5401 5402 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5403 TN1010_PCS_DEV_ADDR, 33, &val); 5404 cmn_err(CE_NOTE, "10GBASE-R Status2 = 0x%x", val); 5405 5406 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5407 TN1010_PHYXS_DEV_ADDR, 1, &val); 5408 cmn_err(CE_NOTE, "PHYXS status1 = 0x%x", val); 5409 5410 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5411 TN1010_PHYXS_DEV_ADDR, 8, &val); 5412 cmn_err(CE_NOTE, "PHYXS status2 = 0x%x", val); 5413 5414 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5415 TN1010_PHYXS_DEV_ADDR, 24, &val); 5416 cmn_err(CE_NOTE, "XGXS Lane status = 0x%x", val); 5417 5418 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5419 TN1010_AUTONEG_DEV_ADDR, 1, &val); 5420 cmn_err(CE_NOTE, "Autoneg status = 0x%x", val); 5421 5422 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5423 TN1010_AUTONEG_DEV_ADDR, 33, &val); 5424 cmn_err(CE_NOTE, "10Gbase-T An status = 0x%x", val); 5425 5426 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5427 TN1010_VENDOR_MMD1_DEV_ADDR, 1, &val); 5428 cmn_err(CE_NOTE, "TN1010 status = 0x%x", val); 5429 5430 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5431 TN1010_VENDOR_MMD1_DEV_ADDR, 8, &val); 5432 cmn_err(CE_NOTE, "Device status = 0x%x", val); 5433 5434 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5435 TN1010_VENDOR_MMD1_DEV_ADDR, 16, &val); 5436 cmn_err(CE_NOTE, "DDR status = 0x%x", val); 5437 5438 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5439 TN1010_VENDOR_MMD1_DEV_ADDR, 17, &val); 5440 cmn_err(CE_NOTE, "DDR fault status = 0x%x", val); 5441 5442 nxge_mdio_read(nxgep, nxgep->xcvr_addr, 5443 TN1010_VENDOR_MMD1_DEV_ADDR, 11, &val); 5444 cmn_err(CE_NOTE, "Firmware Revision = 0x%x Major = 0x%x Minor = 0x%x", 5445 val, (val & 0xFF00) >> 8, val & 0x00FF); 5446 } 5447 #endif 5448 5449 /* 5450 * Calculate the bit in the multicast address filter 5451 * that selects the given * address. 5452 * Note: For GEM, the last 8-bits are used. 5453 */ 5454 uint32_t 5455 crc32_mchash(p_ether_addr_t addr) 5456 { 5457 uint8_t *cp; 5458 uint32_t crc; 5459 uint32_t c; 5460 int byte; 5461 int bit; 5462 5463 cp = (uint8_t *)addr; 5464 crc = (uint32_t)0xffffffff; 5465 for (byte = 0; byte < 6; byte++) { 5466 c = (uint32_t)cp[byte]; 5467 for (bit = 0; bit < 8; bit++) { 5468 if ((c & 0x1) ^ (crc & 0x1)) 5469 crc = (crc >> 1)^0xedb88320; 5470 else 5471 crc = (crc >> 1); 5472 c >>= 1; 5473 } 5474 } 5475 return ((~crc) >> (32 - HASH_BITS)); 5476 } 5477 5478 /* Reset serdes */ 5479 5480 nxge_status_t 5481 nxge_serdes_reset(p_nxge_t nxgep) 5482 { 5483 npi_handle_t handle; 5484 5485 handle = nxgep->npi_handle; 5486 5487 ESR_REG_WR(handle, ESR_RESET_REG, ESR_RESET_0 | ESR_RESET_1); 5488 drv_usecwait(500); 5489 ESR_REG_WR(handle, ESR_CONFIG_REG, 0); 5490 5491 return (NXGE_OK); 5492 } 5493 5494 /* 5495 * This function monitors link status using interrupt or polling. 5496 * It calls nxgep->xcvr.check_link, a member function of 5497 * nxge_xcvr_table_t. But nxgep->xcvr.check_link calls this 5498 * function back, that is why the check_link routine is 5499 * executed periodically. 5500 */ 5501 nxge_status_t 5502 nxge_link_monitor(p_nxge_t nxgep, link_mon_enable_t enable) 5503 { 5504 nxge_status_t status = NXGE_OK; 5505 5506 /* If we are a guest domain driver, don't bother. */ 5507 if (isLDOMguest(nxgep)) 5508 return (status); 5509 5510 /* 5511 * Return immediately if this is an imaginary XMAC port. 5512 * (At least, we don't have 4-port XMAC cards yet.) 5513 */ 5514 if ((nxgep->mac.portmode == PORT_10G_FIBER || 5515 nxgep->mac.portmode == PORT_10G_SERDES) && 5516 (nxgep->mac.portnum > 1)) 5517 return (NXGE_OK); 5518 5519 if (nxgep->statsp == NULL) { 5520 /* stats has not been allocated. */ 5521 return (NXGE_OK); 5522 } 5523 /* Don't check link if we're in internal loopback mode */ 5524 if (nxgep->statsp->port_stats.lb_mode >= nxge_lb_serdes10g) 5525 return (NXGE_OK); 5526 5527 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5528 "==> nxge_link_monitor port<%d> enable=%d", 5529 nxgep->mac.portnum, enable)); 5530 if (enable == LINK_MONITOR_START) { 5531 if (nxgep->mac.linkchkmode == LINKCHK_INTR) { 5532 if ((status = nxge_link_intr(nxgep, LINK_INTR_START)) 5533 != NXGE_OK) 5534 goto fail; 5535 } else { 5536 timeout_id_t timerid; 5537 /* 5538 * check_link_stop means "Stop the link check", so 5539 * we return without starting the timer. 5540 */ 5541 if (nxge_check_link_stop(nxgep) == CHECK_LINK_STOP) 5542 return (NXGE_OK); 5543 5544 /* 5545 * Otherwise fire the timer for the nxge to check 5546 * the link using the check_link function 5547 * of the nxge_xcvr_table and pass "nxgep" as the 5548 * argument to the check_link function. 5549 */ 5550 if (nxgep->xcvr.check_link) { 5551 timerid = timeout( 5552 (fptrv_t)(nxgep->xcvr.check_link), 5553 nxgep, 5554 drv_usectohz(LINK_MONITOR_PERIOD)); 5555 MUTEX_ENTER(&nxgep->poll_lock); 5556 nxgep->nxge_link_poll_timerid = timerid; 5557 MUTEX_EXIT(&nxgep->poll_lock); 5558 } else { 5559 return (NXGE_ERROR); 5560 } 5561 } 5562 } else { 5563 if (nxgep->mac.linkchkmode == LINKCHK_INTR) { 5564 if ((status = nxge_link_intr(nxgep, LINK_INTR_STOP)) 5565 != NXGE_OK) 5566 goto fail; 5567 } else { 5568 clock_t rv; 5569 5570 MUTEX_ENTER(&nxgep->poll_lock); 5571 5572 /* If <timerid> == 0, the link monitor has */ 5573 /* never been started, or just now stopped. */ 5574 if (nxgep->nxge_link_poll_timerid == 0) { 5575 MUTEX_EXIT(&nxgep->poll_lock); 5576 return (NXGE_OK); 5577 } 5578 5579 nxgep->poll_state = LINK_MONITOR_STOPPING; 5580 rv = cv_timedwait(&nxgep->poll_cv, 5581 &nxgep->poll_lock, 5582 ddi_get_lbolt() + 5583 drv_usectohz(LM_WAIT_MULTIPLIER * 5584 LINK_MONITOR_PERIOD)); 5585 if (rv == -1) { 5586 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5587 "==> stopping port %d: " 5588 "cv_timedwait(%d) timed out", 5589 nxgep->mac.portnum, nxgep->poll_state)); 5590 nxgep->poll_state = LINK_MONITOR_STOP; 5591 nxgep->nxge_link_poll_timerid = 0; 5592 } 5593 5594 MUTEX_EXIT(&nxgep->poll_lock); 5595 } 5596 } 5597 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 5598 "<== nxge_link_monitor port<%d> enable=%d", 5599 nxgep->mac.portnum, enable)); 5600 5601 return (NXGE_OK); 5602 fail: 5603 return (status); 5604 5605 } 5606 5607 nxge_status_t 5608 nxge_check_tn1010_link(p_nxge_t nxgep) 5609 { 5610 nxge_status_t status = NXGE_OK; 5611 nxge_link_state_t link_up; 5612 5613 if (nxgep->nxge_magic != NXGE_MAGIC) { 5614 /* magic is 0 if driver is not attached */ 5615 return (NXGE_ERROR); 5616 } 5617 5618 /* Link has been stopped, no need to continue */ 5619 if (nxge_check_link_stop(nxgep) == CHECK_LINK_STOP) { 5620 return (NXGE_OK); 5621 } 5622 5623 if (nxgep->statsp->port_stats.lb_mode > nxge_lb_ext10) 5624 goto nxge_check_tn1010_link_exit; 5625 5626 if ((status = nxge_tn1010_check(nxgep, &link_up)) != NXGE_OK) 5627 goto fail; 5628 5629 nxge_check_tn1010_link_exit: 5630 if (link_up == LINK_IS_UP) 5631 nxge_link_is_up(nxgep); 5632 else if (link_up == LINK_IS_DOWN) 5633 nxge_link_is_down(nxgep); 5634 5635 /* 5636 * nxge_link_monitor will call (nxgep->xcvr.check_link) 5637 * which could be THIS function. 5638 */ 5639 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 5640 5641 return (NXGE_OK); 5642 5643 fail: 5644 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 5645 5646 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5647 "nxge_check_tn1010_link: Failed to check link")); 5648 return (status); 5649 } 5650 5651 5652 /* 5653 * Fill variable "link_up" with either LINK_IS_UP or LINK_IS_DOWN. 5654 */ 5655 static nxge_status_t 5656 nxge_tn1010_check(p_nxge_t nxgep, nxge_link_state_t *link_up) 5657 { 5658 nxge_status_t status = NXGE_OK; 5659 p_nxge_stats_t statsp; 5660 uint8_t phy_port_addr, portn; 5661 uint16_t val; 5662 5663 *link_up = LINK_NO_CHANGE; 5664 5665 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 5666 phy_port_addr = nxgep->nxge_hw_p->xcvr_addr[portn]; 5667 statsp = nxgep->statsp; 5668 5669 /* Check if link is up */ 5670 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 5671 TN1010_AUTONEG_DEV_ADDR, TN1010_AUTONEG_STATUS_REG, &val)) 5672 != NXGE_OK) { 5673 goto fail; 5674 } 5675 /* 5676 * nxge_link_is_up has called nxge_set_tn1010_param and set 5677 * portmode and link_speed 5678 */ 5679 if (val & TN1010_AN_LINK_STAT_BIT) { 5680 if (nxgep->link_notify || 5681 nxgep->statsp->mac_stats.link_up == 0) { 5682 statsp->mac_stats.link_up = 1; 5683 statsp->mac_stats.link_duplex = 2; 5684 *link_up = LINK_IS_UP; 5685 nxgep->link_notify = B_FALSE; 5686 } 5687 } else { 5688 if (nxgep->link_notify || 5689 nxgep->statsp->mac_stats.link_up == 1) { 5690 statsp->mac_stats.link_up = 0; 5691 statsp->mac_stats.link_speed = 0; 5692 statsp->mac_stats.link_duplex = 0; 5693 *link_up = LINK_IS_DOWN; 5694 nxgep->link_notify = B_FALSE; 5695 } 5696 } 5697 return (NXGE_OK); 5698 5699 fail: 5700 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5701 "nxge_tn1010_check: Unable to check TN1010")); 5702 return (status); 5703 } 5704 5705 5706 /* Set promiscous mode */ 5707 5708 nxge_status_t 5709 nxge_set_promisc(p_nxge_t nxgep, boolean_t on) 5710 { 5711 nxge_status_t status = NXGE_OK; 5712 5713 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_set_promisc: on %d", on)); 5714 5715 nxgep->filter.all_phys_cnt = ((on) ? 1 : 0); 5716 5717 RW_ENTER_WRITER(&nxgep->filter_lock); 5718 5719 if ((status = nxge_rx_mac_disable(nxgep)) != NXGE_OK) { 5720 goto fail; 5721 } 5722 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) { 5723 goto fail; 5724 } 5725 5726 RW_EXIT(&nxgep->filter_lock); 5727 5728 if (on) 5729 nxgep->statsp->mac_stats.promisc = B_TRUE; 5730 else 5731 nxgep->statsp->mac_stats.promisc = B_FALSE; 5732 5733 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_set_promisc")); 5734 5735 return (NXGE_OK); 5736 fail: 5737 RW_EXIT(&nxgep->filter_lock); 5738 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_set_promisc: " 5739 "Unable to set promisc (%d)", on)); 5740 5741 return (status); 5742 } 5743 5744 /*ARGSUSED*/ 5745 uint_t 5746 nxge_mif_intr(void *arg1, void *arg2) 5747 { 5748 #ifdef NXGE_DEBUG 5749 p_nxge_t nxgep = (p_nxge_t)arg2; 5750 #endif 5751 #if NXGE_MIF 5752 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 5753 uint32_t status; 5754 npi_handle_t handle; 5755 uint8_t portn; 5756 p_nxge_stats_t statsp; 5757 #endif 5758 5759 #ifdef NXGE_MIF 5760 if (arg2 == NULL || (void *)ldvp->nxgep != arg2) { 5761 nxgep = ldvp->nxgep; 5762 } 5763 nxgep = ldvp->nxgep; 5764 #endif 5765 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_mif_intr")); 5766 5767 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_mif_intr")); 5768 return (DDI_INTR_CLAIMED); 5769 5770 mif_intr_fail: 5771 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_mif_intr")); 5772 return (DDI_INTR_UNCLAIMED); 5773 } 5774 5775 /*ARGSUSED*/ 5776 uint_t 5777 nxge_mac_intr(void *arg1, void *arg2) 5778 { 5779 p_nxge_t nxgep = (p_nxge_t)arg2; 5780 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 5781 p_nxge_ldg_t ldgp; 5782 uint32_t status; 5783 npi_handle_t handle; 5784 uint8_t portn; 5785 p_nxge_stats_t statsp; 5786 npi_status_t rs = NPI_SUCCESS; 5787 5788 if (arg2 == NULL || (void *)ldvp->nxgep != arg2) { 5789 nxgep = ldvp->nxgep; 5790 } 5791 5792 ldgp = ldvp->ldgp; 5793 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_mac_intr: " 5794 "group %d", ldgp->ldg)); 5795 5796 handle = NXGE_DEV_NPI_HANDLE(nxgep); 5797 /* 5798 * This interrupt handler is for a specific 5799 * mac port. 5800 */ 5801 statsp = (p_nxge_stats_t)nxgep->statsp; 5802 portn = nxgep->mac.portnum; 5803 5804 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5805 "==> nxge_mac_intr: reading mac stats: port<%d>", portn)); 5806 5807 if (nxgep->mac.porttype == PORT_TYPE_XMAC) { 5808 rs = npi_xmac_tx_get_istatus(handle, portn, 5809 (xmac_tx_iconfig_t *)&status); 5810 if (rs != NPI_SUCCESS) 5811 goto npi_fail; 5812 if (status & ICFG_XMAC_TX_ALL) { 5813 if (status & ICFG_XMAC_TX_UNDERRUN) { 5814 statsp->xmac_stats.tx_underflow_err++; 5815 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 5816 NXGE_FM_EREPORT_TXMAC_UNDERFLOW); 5817 } 5818 if (status & ICFG_XMAC_TX_MAX_PACKET_ERR) { 5819 statsp->xmac_stats.tx_maxpktsize_err++; 5820 /* 5821 * Do not send FMA ereport because this 5822 * error does not indicate HW failure. 5823 */ 5824 } 5825 if (status & ICFG_XMAC_TX_OVERFLOW) { 5826 statsp->xmac_stats.tx_overflow_err++; 5827 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 5828 NXGE_FM_EREPORT_TXMAC_OVERFLOW); 5829 } 5830 if (status & ICFG_XMAC_TX_FIFO_XFR_ERR) { 5831 statsp->xmac_stats.tx_fifo_xfr_err++; 5832 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 5833 NXGE_FM_EREPORT_TXMAC_TXFIFO_XFR_ERR); 5834 } 5835 if (status & ICFG_XMAC_TX_BYTE_CNT_EXP) { 5836 statsp->xmac_stats.tx_byte_cnt += 5837 XTXMAC_BYTE_CNT_MASK; 5838 } 5839 if (status & ICFG_XMAC_TX_FRAME_CNT_EXP) { 5840 statsp->xmac_stats.tx_frame_cnt += 5841 XTXMAC_FRM_CNT_MASK; 5842 } 5843 } 5844 5845 rs = npi_xmac_rx_get_istatus(handle, portn, 5846 (xmac_rx_iconfig_t *)&status); 5847 if (rs != NPI_SUCCESS) 5848 goto npi_fail; 5849 if (status & ICFG_XMAC_RX_ALL) { 5850 if (status & ICFG_XMAC_RX_OVERFLOW) 5851 statsp->xmac_stats.rx_overflow_err++; 5852 if (status & ICFG_XMAC_RX_UNDERFLOW) { 5853 statsp->xmac_stats.rx_underflow_err++; 5854 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 5855 NXGE_FM_EREPORT_RXMAC_UNDERFLOW); 5856 } 5857 /* 5858 * Do not send FMA ereport for the following 3 errors 5859 * because they do not indicate HW failures. 5860 */ 5861 if (status & ICFG_XMAC_RX_CRC_ERR_CNT_EXP) { 5862 statsp->xmac_stats.rx_crc_err_cnt += 5863 XRXMAC_CRC_ER_CNT_MASK; 5864 } 5865 if (status & ICFG_XMAC_RX_LEN_ERR_CNT_EXP) { 5866 statsp->xmac_stats.rx_len_err_cnt += 5867 MAC_LEN_ER_CNT_MASK; 5868 } 5869 if (status & ICFG_XMAC_RX_VIOL_ERR_CNT_EXP) { 5870 statsp->xmac_stats.rx_viol_err_cnt += 5871 XRXMAC_CD_VIO_CNT_MASK; 5872 } 5873 if (status & ICFG_XMAC_RX_OCT_CNT_EXP) { 5874 statsp->xmac_stats.rx_byte_cnt += 5875 XRXMAC_BT_CNT_MASK; 5876 } 5877 if (status & ICFG_XMAC_RX_HST_CNT1_EXP) { 5878 statsp->xmac_stats.rx_hist1_cnt += 5879 XRXMAC_HIST_CNT1_MASK; 5880 } 5881 if (status & ICFG_XMAC_RX_HST_CNT2_EXP) { 5882 statsp->xmac_stats.rx_hist2_cnt += 5883 XRXMAC_HIST_CNT2_MASK; 5884 } 5885 if (status & ICFG_XMAC_RX_HST_CNT3_EXP) { 5886 statsp->xmac_stats.rx_hist3_cnt += 5887 XRXMAC_HIST_CNT3_MASK; 5888 } 5889 if (status & ICFG_XMAC_RX_HST_CNT4_EXP) { 5890 statsp->xmac_stats.rx_hist4_cnt += 5891 XRXMAC_HIST_CNT4_MASK; 5892 } 5893 if (status & ICFG_XMAC_RX_HST_CNT5_EXP) { 5894 statsp->xmac_stats.rx_hist5_cnt += 5895 XRXMAC_HIST_CNT5_MASK; 5896 } 5897 if (status & ICFG_XMAC_RX_HST_CNT6_EXP) { 5898 statsp->xmac_stats.rx_hist6_cnt += 5899 XRXMAC_HIST_CNT6_MASK; 5900 } 5901 if (status & ICFG_XMAC_RX_BCAST_CNT_EXP) { 5902 statsp->xmac_stats.rx_broadcast_cnt += 5903 XRXMAC_BC_FRM_CNT_MASK; 5904 } 5905 if (status & ICFG_XMAC_RX_MCAST_CNT_EXP) { 5906 statsp->xmac_stats.rx_mult_cnt += 5907 XRXMAC_MC_FRM_CNT_MASK; 5908 } 5909 /* 5910 * Do not send FMA ereport for the following 3 errors 5911 * because they do not indicate HW failures. 5912 */ 5913 if (status & ICFG_XMAC_RX_FRAG_CNT_EXP) { 5914 statsp->xmac_stats.rx_frag_cnt += 5915 XRXMAC_FRAG_CNT_MASK; 5916 } 5917 if (status & ICFG_XMAC_RX_ALIGNERR_CNT_EXP) { 5918 statsp->xmac_stats.rx_frame_align_err_cnt += 5919 XRXMAC_AL_ER_CNT_MASK; 5920 } 5921 if (status & ICFG_XMAC_RX_LINK_FLT_CNT_EXP) { 5922 statsp->xmac_stats.rx_linkfault_err_cnt += 5923 XMAC_LINK_FLT_CNT_MASK; 5924 } 5925 if (status & ICFG_XMAC_RX_REMOTE_FLT_DET) { 5926 statsp->xmac_stats.rx_remotefault_err++; 5927 } 5928 if (status & ICFG_XMAC_RX_LOCAL_FLT_DET) { 5929 statsp->xmac_stats.rx_localfault_err++; 5930 } 5931 } 5932 5933 rs = npi_xmac_ctl_get_istatus(handle, portn, 5934 (xmac_ctl_iconfig_t *)&status); 5935 if (rs != NPI_SUCCESS) 5936 goto npi_fail; 5937 if (status & ICFG_XMAC_CTRL_ALL) { 5938 if (status & ICFG_XMAC_CTRL_PAUSE_RCVD) 5939 statsp->xmac_stats.rx_pause_cnt++; 5940 if (status & ICFG_XMAC_CTRL_PAUSE_STATE) 5941 statsp->xmac_stats.tx_pause_state++; 5942 if (status & ICFG_XMAC_CTRL_NOPAUSE_STATE) 5943 statsp->xmac_stats.tx_nopause_state++; 5944 } 5945 } else if (nxgep->mac.porttype == PORT_TYPE_BMAC) { 5946 rs = npi_bmac_tx_get_istatus(handle, portn, 5947 (bmac_tx_iconfig_t *)&status); 5948 if (rs != NPI_SUCCESS) 5949 goto npi_fail; 5950 if (status & ICFG_BMAC_TX_ALL) { 5951 if (status & ICFG_BMAC_TX_UNDERFLOW) { 5952 statsp->bmac_stats.tx_underrun_err++; 5953 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 5954 NXGE_FM_EREPORT_TXMAC_UNDERFLOW); 5955 } 5956 if (status & ICFG_BMAC_TX_MAXPKTSZ_ERR) { 5957 statsp->bmac_stats.tx_max_pkt_err++; 5958 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 5959 NXGE_FM_EREPORT_TXMAC_MAX_PKT_ERR); 5960 } 5961 if (status & ICFG_BMAC_TX_BYTE_CNT_EXP) { 5962 statsp->bmac_stats.tx_byte_cnt += 5963 BTXMAC_BYTE_CNT_MASK; 5964 } 5965 if (status & ICFG_BMAC_TX_FRAME_CNT_EXP) { 5966 statsp->bmac_stats.tx_frame_cnt += 5967 BTXMAC_FRM_CNT_MASK; 5968 } 5969 } 5970 5971 rs = npi_bmac_rx_get_istatus(handle, portn, 5972 (bmac_rx_iconfig_t *)&status); 5973 if (rs != NPI_SUCCESS) 5974 goto npi_fail; 5975 if (status & ICFG_BMAC_RX_ALL) { 5976 if (status & ICFG_BMAC_RX_OVERFLOW) { 5977 statsp->bmac_stats.rx_overflow_err++; 5978 } 5979 if (status & ICFG_BMAC_RX_FRAME_CNT_EXP) { 5980 statsp->bmac_stats.rx_frame_cnt += 5981 RXMAC_FRM_CNT_MASK; 5982 } 5983 if (status & ICFG_BMAC_RX_CRC_ERR_CNT_EXP) { 5984 statsp->bmac_stats.rx_crc_err_cnt += 5985 BMAC_CRC_ER_CNT_MASK; 5986 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 5987 NXGE_FM_EREPORT_RXMAC_CRC_ERRCNT_EXP); 5988 } 5989 if (status & ICFG_BMAC_RX_LEN_ERR_CNT_EXP) { 5990 statsp->bmac_stats.rx_len_err_cnt += 5991 MAC_LEN_ER_CNT_MASK; 5992 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 5993 NXGE_FM_EREPORT_RXMAC_LENGTH_ERRCNT_EXP); 5994 } 5995 if (status & ICFG_BMAC_RX_VIOL_ERR_CNT_EXP) 5996 statsp->bmac_stats.rx_viol_err_cnt += 5997 BMAC_CD_VIO_CNT_MASK; 5998 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 5999 NXGE_FM_EREPORT_RXMAC_VIOL_ERRCNT_EXP); 6000 } 6001 if (status & ICFG_BMAC_RX_BYTE_CNT_EXP) { 6002 statsp->bmac_stats.rx_byte_cnt += 6003 BRXMAC_BYTE_CNT_MASK; 6004 } 6005 if (status & ICFG_BMAC_RX_ALIGNERR_CNT_EXP) { 6006 statsp->bmac_stats.rx_align_err_cnt += 6007 BMAC_AL_ER_CNT_MASK; 6008 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 6009 NXGE_FM_EREPORT_RXMAC_ALIGN_ECNT_EXP); 6010 } 6011 6012 rs = npi_bmac_ctl_get_istatus(handle, portn, 6013 (bmac_ctl_iconfig_t *)&status); 6014 if (rs != NPI_SUCCESS) 6015 goto npi_fail; 6016 6017 if (status & ICFG_BMAC_CTL_ALL) { 6018 if (status & ICFG_BMAC_CTL_RCVPAUSE) 6019 statsp->bmac_stats.rx_pause_cnt++; 6020 if (status & ICFG_BMAC_CTL_INPAUSE_ST) 6021 statsp->bmac_stats.tx_pause_state++; 6022 if (status & ICFG_BMAC_CTL_INNOTPAUSE_ST) 6023 statsp->bmac_stats.tx_nopause_state++; 6024 } 6025 } 6026 6027 if (ldgp->nldvs == 1) { 6028 (void) npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 6029 B_TRUE, ldgp->ldg_timer); 6030 } 6031 6032 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_mac_intr")); 6033 return (DDI_INTR_CLAIMED); 6034 6035 npi_fail: 6036 NXGE_ERROR_MSG((nxgep, INT_CTL, "<== nxge_mac_intr")); 6037 return (DDI_INTR_UNCLAIMED); 6038 } 6039 6040 nxge_status_t 6041 nxge_check_bcm8704_link(p_nxge_t nxgep, boolean_t *link_up) 6042 { 6043 uint8_t phy_port_addr; 6044 nxge_status_t status = NXGE_OK; 6045 boolean_t rx_sig_ok; 6046 boolean_t pcs_blk_lock; 6047 boolean_t link_align; 6048 uint16_t val1, val2, val3; 6049 #ifdef NXGE_DEBUG_SYMBOL_ERR 6050 uint16_t val_debug; 6051 uint16_t val; 6052 #endif 6053 6054 phy_port_addr = nxgep->statsp->mac_stats.xcvr_portn; 6055 6056 #ifdef NXGE_DEBUG_SYMBOL_ERR 6057 /* Check Device 3 Register Device 3 0xC809 */ 6058 (void) nxge_mdio_read(nxgep, phy_port_addr, 0x3, 0xC809, &val_debug); 6059 if ((val_debug & ~0x200) != 0) { 6060 cmn_err(CE_NOTE, "!Port%d BCM8704 Dev3 Reg 0xc809 = 0x%x\n", 6061 nxgep->mac.portnum, val_debug); 6062 (void) nxge_mdio_read(nxgep, phy_port_addr, 0x4, 0x18, 6063 &val_debug); 6064 cmn_err(CE_NOTE, "!Port%d BCM8704 Dev4 Reg 0x18 = 0x%x\n", 6065 nxgep->mac.portnum, val_debug); 6066 } 6067 6068 (void) npi_xmac_xpcs_read(nxgep->npi_handle, nxgep->mac.portnum, 6069 XPCS_REG_DESCWERR_COUNTER, &val); 6070 if (val != 0) 6071 cmn_err(CE_NOTE, "!XPCS DESCWERR = 0x%x\n", val); 6072 6073 (void) npi_xmac_xpcs_read(nxgep->npi_handle, nxgep->mac.portnum, 6074 XPCS_REG_SYMBOL_ERR_L0_1_COUNTER, &val); 6075 if (val != 0) 6076 cmn_err(CE_NOTE, "!XPCS SYMBOL_ERR_L0_1 = 0x%x\n", val); 6077 6078 (void) npi_xmac_xpcs_read(nxgep->npi_handle, nxgep->mac.portnum, 6079 XPCS_REG_SYMBOL_ERR_L2_3_COUNTER, &val); 6080 if (val != 0) 6081 cmn_err(CE_NOTE, "!XPCS SYMBOL_ERR_L2_3 = 0x%x\n", val); 6082 #endif 6083 6084 /* Check from BCM8704 if 10G link is up or down */ 6085 6086 /* Check Device 1 Register 0xA bit0 */ 6087 status = nxge_mdio_read(nxgep, phy_port_addr, BCM8704_PMA_PMD_DEV_ADDR, 6088 BCM8704_PMD_RECEIVE_SIG_DETECT, &val1); 6089 if (status != NXGE_OK) 6090 goto fail; 6091 rx_sig_ok = ((val1 & GLOB_PMD_RX_SIG_OK) ? B_TRUE : B_FALSE); 6092 6093 /* Check Device 3 Register 0x20 bit0 */ 6094 if ((status = nxge_mdio_read(nxgep, phy_port_addr, BCM8704_PCS_DEV_ADDR, 6095 BCM8704_10GBASE_R_PCS_STATUS_REG, &val2)) != NPI_SUCCESS) 6096 goto fail; 6097 pcs_blk_lock = ((val2 & PCS_10GBASE_R_PCS_BLK_LOCK) ? B_TRUE : B_FALSE); 6098 6099 /* Check Device 4 Register 0x18 bit12 */ 6100 status = nxge_mdio_read(nxgep, phy_port_addr, BCM8704_PHYXS_ADDR, 6101 BCM8704_PHYXS_XGXS_LANE_STATUS_REG, &val3); 6102 if (status != NXGE_OK) 6103 goto fail; 6104 6105 switch (nxgep->chip_id) { 6106 case BCM8704_CHIP_ID: 6107 link_align = (val3 == (XGXS_LANE_ALIGN_STATUS | 6108 XGXS_LANE3_SYNC | XGXS_LANE2_SYNC | XGXS_LANE1_SYNC | 6109 XGXS_LANE0_SYNC | 0x400)) ? B_TRUE : B_FALSE; 6110 break; 6111 case BCM8706_CHIP_ID: 6112 link_align = ((val3 & XGXS_LANE_ALIGN_STATUS) && 6113 (val3 & XGXS_LANE3_SYNC) && (val3 & XGXS_LANE2_SYNC) && 6114 (val3 & XGXS_LANE1_SYNC) && (val3 & XGXS_LANE0_SYNC)) ? 6115 B_TRUE : B_FALSE; 6116 break; 6117 default: 6118 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_check_bcm8704_link:" 6119 "Unknown chip ID [0x%x]", nxgep->chip_id)); 6120 goto fail; 6121 } 6122 6123 6124 #ifdef NXGE_DEBUG_ALIGN_ERR 6125 /* Temp workaround for link down issue */ 6126 if (pcs_blk_lock == B_FALSE) { 6127 if (val2 != 0x4) { 6128 pcs_blk_lock = B_TRUE; 6129 cmn_err(CE_NOTE, "!LINK DEBUG: port%d PHY Dev3 " 6130 "Reg 0x20 = 0x%x\n", nxgep->mac.portnum, val2); 6131 } 6132 } 6133 6134 if (link_align == B_FALSE) { 6135 if (val3 != 0x140f) { 6136 link_align = B_TRUE; 6137 cmn_err(CE_NOTE, "!LINK DEBUG: port%d PHY Dev4 " 6138 "Reg 0x18 = 0x%x\n", nxgep->mac.portnum, val3); 6139 } 6140 } 6141 6142 if (rx_sig_ok == B_FALSE) { 6143 if ((val2 == 0) || (val3 == 0)) { 6144 rx_sig_ok = B_TRUE; 6145 cmn_err(CE_NOTE, 6146 "!LINK DEBUG: port %d Dev3 or Dev4 read zero\n", 6147 nxgep->mac.portnum); 6148 } 6149 } 6150 #endif 6151 6152 *link_up = ((rx_sig_ok == B_TRUE) && (pcs_blk_lock == B_TRUE) && 6153 (link_align == B_TRUE)) ? B_TRUE : B_FALSE; 6154 6155 return (NXGE_OK); 6156 fail: 6157 return (status); 6158 } 6159 6160 static nxge_status_t 6161 nxge_check_mrvl88x2011_link(p_nxge_t nxgep, boolean_t *link_up) 6162 { 6163 uint8_t phy; 6164 nxge_status_t status = NXGE_OK; 6165 boolean_t pma_status; 6166 boolean_t pcs_status; 6167 boolean_t xgxs_status; 6168 uint16_t val; 6169 6170 phy = nxgep->statsp->mac_stats.xcvr_portn; 6171 6172 MRVL88X2011_RD(nxgep, phy, MRVL_88X2011_USER_DEV1_ADDR, 6173 MRVL_88X2011_10G_PMD_STAT_2, &val); 6174 6175 *link_up = B_FALSE; 6176 6177 /* Check from Marvell 88X2011 if 10G link is up or down */ 6178 6179 /* Check PMA/PMD Register: 1.0001.2 == 1 */ 6180 MRVL88X2011_RD(nxgep, phy, MRVL_88X2011_USER_DEV1_ADDR, 6181 MRVL_88X2011_PMA_PMD_STAT_1, &val); 6182 6183 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6184 "nxge_check_mrvl88x2011_link: pmd=0x%x", val)); 6185 6186 pma_status = ((val & MRVL_88X2011_LNK_STATUS_OK) ? B_TRUE : B_FALSE); 6187 6188 /* Check PMC Register : 3.0001.2 == 1: read twice */ 6189 MRVL88X2011_RD(nxgep, phy, MRVL_88X2011_USER_DEV3_ADDR, 6190 MRVL_88X2011_PMA_PMD_STAT_1, &val); 6191 MRVL88X2011_RD(nxgep, phy, MRVL_88X2011_USER_DEV3_ADDR, 6192 MRVL_88X2011_PMA_PMD_STAT_1, &val); 6193 6194 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6195 "nxge_check_mrvl88x2011_link: pcs=0x%x", val)); 6196 6197 pcs_status = ((val & MRVL_88X2011_LNK_STATUS_OK) ? B_TRUE : B_FALSE); 6198 6199 /* Check XGXS Register : 4.0018.[0-3,12] */ 6200 MRVL88X2011_RD(nxgep, phy, MRVL_88X2011_USER_DEV4_ADDR, 6201 MRVL_88X2011_10G_XGXS_LANE_STAT, &val); 6202 6203 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6204 "nxge_check_mrvl88x2011_link: xgxs=0x%x", val)); 6205 6206 xgxs_status = (val == (XGXS_LANE_ALIGN_STATUS | XGXS_LANE3_SYNC | 6207 XGXS_LANE2_SYNC | XGXS_LANE1_SYNC | 6208 XGXS_LANE0_SYNC | XGXS_PATTERN_TEST_ABILITY | 6209 XGXS_LANE_STAT_MAGIC)) ? B_TRUE : B_FALSE; 6210 6211 *link_up = (pma_status && pcs_status && xgxs_status) ? 6212 B_TRUE : B_FALSE; 6213 6214 fail: 6215 6216 if (*link_up == B_FALSE) { 6217 /* PCS OFF */ 6218 nxge_mrvl88x2011_led(nxgep, MRVL_88X2011_LED_CTL_OFF); 6219 } else { 6220 /* PCS Activity */ 6221 nxge_mrvl88x2011_led(nxgep, MRVL_88X2011_LED_CTL_PCS_ACT); 6222 } 6223 6224 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6225 " <== nxge_check_mrvl88x2011_link: up=%d", *link_up)); 6226 6227 return (status); 6228 } 6229 6230 nxge_status_t 6231 nxge_10g_link_led_on(p_nxge_t nxgep) 6232 { 6233 if (npi_xmac_xif_led(nxgep->npi_handle, nxgep->mac.portnum, B_TRUE) 6234 != NPI_SUCCESS) 6235 return (NXGE_ERROR); 6236 else 6237 return (NXGE_OK); 6238 } 6239 6240 nxge_status_t 6241 nxge_10g_link_led_off(p_nxge_t nxgep) 6242 { 6243 if (npi_xmac_xif_led(nxgep->npi_handle, nxgep->mac.portnum, B_FALSE) 6244 != NPI_SUCCESS) 6245 return (NXGE_ERROR); 6246 else 6247 return (NXGE_OK); 6248 } 6249 6250 static boolean_t 6251 nxge_is_phy_present(p_nxge_t nxgep, int addr, uint32_t id, uint32_t mask) 6252 { 6253 uint32_t pma_pmd_id = 0; 6254 uint32_t pcs_id = 0; 6255 uint32_t phy_id = 0; 6256 6257 pma_pmd_id = nxge_get_cl45_pma_pmd_id(nxgep, addr); 6258 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6259 "nxge_is_phy_present: pma_pmd_id[0x%x]", pma_pmd_id)); 6260 if ((pma_pmd_id & mask) == (id & mask)) 6261 goto found_phy; 6262 pcs_id = nxge_get_cl45_pcs_id(nxgep, addr); 6263 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6264 "nxge_is_phy_present: pcs_id[0x%x]", pcs_id)); 6265 if ((pcs_id & mask) == (id & mask)) 6266 goto found_phy; 6267 phy_id = nxge_get_cl22_phy_id(nxgep, addr); 6268 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6269 "nxge_is_phy_present: phy_id[0x%x]", phy_id)); 6270 if ((phy_id & mask) == (id & mask)) 6271 goto found_phy; 6272 6273 return (B_FALSE); 6274 6275 found_phy: 6276 return (B_TRUE); 6277 } 6278 6279 /* Check if the given id read using the given MDIO Clause is supported */ 6280 6281 static boolean_t 6282 nxge_is_supported_phy(uint32_t id, uint8_t type) 6283 { 6284 int i; 6285 boolean_t found = B_FALSE; 6286 6287 switch (type) { 6288 case CLAUSE_45_TYPE: 6289 for (i = 0; i < NUM_CLAUSE_45_IDS; i++) { 6290 if (((nxge_supported_cl45_ids[i] & BCM_PHY_ID_MASK) == 6291 (id & BCM_PHY_ID_MASK)) || 6292 (TN1010_DEV_ID == (id & TN1010_DEV_ID_MASK))) { 6293 found = B_TRUE; 6294 break; 6295 } 6296 } 6297 break; 6298 case CLAUSE_22_TYPE: 6299 for (i = 0; i < NUM_CLAUSE_22_IDS; i++) { 6300 if ((nxge_supported_cl22_ids[i] & BCM_PHY_ID_MASK) == 6301 (id & BCM_PHY_ID_MASK)) { 6302 found = B_TRUE; 6303 break; 6304 } 6305 } 6306 break; 6307 default: 6308 break; 6309 } 6310 6311 return (found); 6312 } 6313 6314 static uint32_t 6315 nxge_get_cl45_pma_pmd_id(p_nxge_t nxgep, int phy_port) 6316 { 6317 uint16_t val1 = 0; 6318 uint16_t val2 = 0; 6319 uint32_t pma_pmd_dev_id = 0; 6320 npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep); 6321 6322 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_mdio_lock); 6323 (void) npi_mac_mif_mdio_read(handle, phy_port, NXGE_PMA_PMD_DEV_ADDR, 6324 NXGE_DEV_ID_REG_1, &val1); 6325 (void) npi_mac_mif_mdio_read(handle, phy_port, NXGE_PMA_PMD_DEV_ADDR, 6326 NXGE_DEV_ID_REG_2, &val2); 6327 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 6328 6329 /* Concatenate the Device ID stored in two registers. */ 6330 pma_pmd_dev_id = val1; 6331 pma_pmd_dev_id = (pma_pmd_dev_id << 16); 6332 pma_pmd_dev_id |= val2; 6333 6334 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "port[%d] PMA/PMD " 6335 "devid[0x%llx]", phy_port, pma_pmd_dev_id)); 6336 6337 return (pma_pmd_dev_id); 6338 } 6339 6340 static uint32_t 6341 nxge_get_cl45_pcs_id(p_nxge_t nxgep, int phy_port) 6342 { 6343 uint16_t val1 = 0; 6344 uint16_t val2 = 0; 6345 uint32_t pcs_dev_id = 0; 6346 npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep); 6347 6348 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_mdio_lock); 6349 (void) npi_mac_mif_mdio_read(handle, phy_port, NXGE_PCS_DEV_ADDR, 6350 NXGE_DEV_ID_REG_1, &val1); 6351 (void) npi_mac_mif_mdio_read(handle, phy_port, NXGE_PCS_DEV_ADDR, 6352 NXGE_DEV_ID_REG_2, &val2); 6353 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 6354 6355 pcs_dev_id = val1; 6356 pcs_dev_id = (pcs_dev_id << 16); 6357 pcs_dev_id |= val2; 6358 6359 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "port[%d] PCS " 6360 "devid[0x%llx]", phy_port, pcs_dev_id)); 6361 6362 return (pcs_dev_id); 6363 } 6364 6365 static uint32_t 6366 nxge_get_cl22_phy_id(p_nxge_t nxgep, int phy_port) 6367 { 6368 uint16_t val1 = 0; 6369 uint16_t val2 = 0; 6370 uint32_t phy_id = 0; 6371 npi_handle_t handle = NXGE_DEV_NPI_HANDLE(nxgep); 6372 npi_status_t npi_status = NPI_SUCCESS; 6373 6374 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_mdio_lock); 6375 npi_status = npi_mac_mif_mii_read(handle, phy_port, NXGE_PHY_ID_REG_1, 6376 &val1); 6377 if (npi_status != NPI_SUCCESS) { 6378 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "port[%d] " 6379 "clause 22 read to reg 2 failed!!!")); 6380 goto exit; 6381 } 6382 npi_status = npi_mac_mif_mii_read(handle, phy_port, NXGE_PHY_ID_REG_2, 6383 &val2); 6384 if (npi_status != 0) { 6385 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "port[%d] " 6386 "clause 22 read to reg 3 failed!!!")); 6387 goto exit; 6388 } 6389 phy_id = val1; 6390 phy_id = (phy_id << 16); 6391 phy_id |= val2; 6392 6393 exit: 6394 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 6395 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "port[%d] PHY ID [0x%llx]", 6396 phy_port, phy_id)); 6397 6398 return (phy_id); 6399 } 6400 6401 /* 6402 * Scan the PHY ports 0 through 31 to get the PHY ID using Clause 22 MDIO 6403 * read and the PMA/PMD device ID and the PCS device ID using Clause 45 MDIO 6404 * read. Then use the values obtained to determine the phy type of each port 6405 * and the Neptune type. 6406 * 6407 * This function sets hw_p->xcvr_addr[i] for future MDIO access and set 6408 * hw_p->niu_type for each nxge instance to figure out nxgep->mac.portmode 6409 * in case the portmode information is not available via OBP, nxge.conf, 6410 * VPD or SEEPROM. 6411 */ 6412 nxge_status_t 6413 nxge_scan_ports_phy(p_nxge_t nxgep, p_nxge_hw_list_t hw_p) 6414 { 6415 int i, j, l; 6416 uint32_t pma_pmd_dev_id = 0; 6417 uint32_t pcs_dev_id = 0; 6418 uint32_t phy_id = 0; 6419 uint32_t port_pma_pmd_dev_id[NXGE_PORTS_NEPTUNE]; 6420 uint32_t port_pcs_dev_id[NXGE_PORTS_NEPTUNE]; 6421 uint32_t port_phy_id[NXGE_PORTS_NEPTUNE]; 6422 uint8_t pma_pmd_dev_fd[NXGE_MAX_PHY_PORTS]; 6423 uint8_t pcs_dev_fd[NXGE_MAX_PHY_PORTS]; 6424 uint8_t phy_fd_arr[NXGE_MAX_PHY_PORTS]; 6425 uint8_t port_fd_arr[NXGE_MAX_PHY_PORTS]; 6426 uint8_t total_port_fd, total_phy_fd; 6427 uint8_t num_xaui; 6428 nxge_status_t status = NXGE_OK; 6429 6430 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_scan_ports_phy: ")); 6431 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6432 "==> nxge_scan_ports_phy: nxge niu_type[0x%x]", 6433 nxgep->niu_type)); 6434 6435 if (isLDOMguest(nxgep)) { 6436 hw_p->niu_type = NIU_TYPE_NONE; 6437 hw_p->platform_type = P_NEPTUNE_NONE; 6438 return (NXGE_OK); 6439 } 6440 6441 j = l = 0; 6442 total_port_fd = total_phy_fd = 0; 6443 /* 6444 * Clause 45 and Clause 22 port/phy addresses 0 through 5 are reserved 6445 * for on chip serdes usages. "i" in the following for loop starts at 6. 6446 */ 6447 for (i = NXGE_EXT_PHY_PORT_ST; i < NXGE_MAX_PHY_PORTS; i++) { 6448 6449 pma_pmd_dev_id = nxge_get_cl45_pma_pmd_id(nxgep, i); 6450 6451 if (nxge_is_supported_phy(pma_pmd_dev_id, CLAUSE_45_TYPE)) { 6452 pma_pmd_dev_fd[i] = 1; 6453 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "port[%d] " 6454 "PMA/PMD dev %x found", i, pma_pmd_dev_id)); 6455 if (j < NXGE_PORTS_NEPTUNE) { 6456 if ((pma_pmd_dev_id & TN1010_DEV_ID_MASK) 6457 == TN1010_DEV_ID) { 6458 port_pma_pmd_dev_id[j] = TN1010_DEV_ID; 6459 } else { 6460 port_pma_pmd_dev_id[j] = 6461 pma_pmd_dev_id & BCM_PHY_ID_MASK; 6462 } 6463 port_fd_arr[j] = (uint8_t)i; 6464 j++; 6465 } 6466 } else { 6467 pma_pmd_dev_fd[i] = 0; 6468 } 6469 6470 pcs_dev_id = nxge_get_cl45_pcs_id(nxgep, i); 6471 6472 if (nxge_is_supported_phy(pcs_dev_id, CLAUSE_45_TYPE)) { 6473 pcs_dev_fd[i] = 1; 6474 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "port[%d] PCS " 6475 "dev %x found", i, pcs_dev_id)); 6476 if (pma_pmd_dev_fd[i] == 1) { 6477 if ((pcs_dev_id & TN1010_DEV_ID_MASK) 6478 == TN1010_DEV_ID) { 6479 port_pcs_dev_id[j - 1] = 6480 TN1010_DEV_ID; 6481 } else { 6482 port_pcs_dev_id[j - 1] = 6483 pcs_dev_id & 6484 BCM_PHY_ID_MASK; 6485 } 6486 } else { 6487 if (j < NXGE_PORTS_NEPTUNE) { 6488 if ((pcs_dev_id & TN1010_DEV_ID_MASK) 6489 == TN1010_DEV_ID) { 6490 port_pcs_dev_id[j] = 6491 TN1010_DEV_ID; 6492 } else { 6493 port_pcs_dev_id[j] = 6494 pcs_dev_id & 6495 BCM_PHY_ID_MASK; 6496 } 6497 port_fd_arr[j] = (uint8_t)i; 6498 j++; 6499 } 6500 } 6501 } else { 6502 pcs_dev_fd[i] = 0; 6503 } 6504 6505 if (pcs_dev_fd[i] || pma_pmd_dev_fd[i]) { 6506 total_port_fd ++; 6507 } 6508 6509 phy_id = nxge_get_cl22_phy_id(nxgep, i); 6510 if (nxge_is_supported_phy(phy_id, CLAUSE_22_TYPE)) { 6511 total_phy_fd ++; 6512 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "port[%d] PHY ID" 6513 "%x found", i, phy_id)); 6514 if (l < NXGE_PORTS_NEPTUNE) { 6515 if ((phy_id & TN1010_DEV_ID_MASK) 6516 == TN1010_DEV_ID) { 6517 port_phy_id[l] = TN1010_DEV_ID; 6518 } else { 6519 port_phy_id[l] 6520 = phy_id & BCM_PHY_ID_MASK; 6521 } 6522 phy_fd_arr[l] = (uint8_t)i; 6523 l++; 6524 } 6525 } 6526 } 6527 6528 switch (total_port_fd) { 6529 case 2: 6530 switch (total_phy_fd) { 6531 case 2: 6532 /* 2 10G, 2 1G RGMII Fiber / copper */ 6533 if ((((port_pcs_dev_id[0] == PHY_BCM8704_FAMILY) && 6534 (port_pcs_dev_id[1] == PHY_BCM8704_FAMILY)) || 6535 ((port_pma_pmd_dev_id[0] == PHY_BCM8704_FAMILY) && 6536 (port_pma_pmd_dev_id[1] == PHY_BCM8704_FAMILY))) && 6537 ((port_phy_id[0] == PHY_BCM5482_FAMILY) && 6538 (port_phy_id[1] == PHY_BCM5482_FAMILY))) { 6539 6540 switch (hw_p->platform_type) { 6541 case P_NEPTUNE_ROCK: 6542 hw_p->niu_type = NEPTUNE_2_10GF_2_1GC; 6543 /* 6544 * ROCK platform has assigned a lower 6545 * addr to port 1. (port 0 = 0x9 and 6546 * port 1 = 0x8). 6547 */ 6548 hw_p->xcvr_addr[1] = port_fd_arr[0]; 6549 hw_p->xcvr_addr[0] = port_fd_arr[1]; 6550 6551 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6552 "Rock with 2 10G, 2 1GC")); 6553 break; 6554 6555 case P_NEPTUNE_NONE: 6556 default: 6557 hw_p->platform_type = 6558 P_NEPTUNE_GENERIC; 6559 hw_p->niu_type = NEPTUNE_2_10GF_2_1GRF; 6560 6561 hw_p->xcvr_addr[0] = port_fd_arr[0]; 6562 hw_p->xcvr_addr[1] = port_fd_arr[1]; 6563 6564 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6565 "ARTM card with 2 10G, 2 1GF")); 6566 break; 6567 } 6568 6569 hw_p->xcvr_addr[2] = phy_fd_arr[0]; 6570 hw_p->xcvr_addr[3] = phy_fd_arr[1]; 6571 6572 } else { 6573 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6574 "Unsupported neptune type 1")); 6575 goto error_exit; 6576 } 6577 break; 6578 6579 case 1: 6580 /* TODO - 2 10G, 1 1G */ 6581 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6582 "Unsupported neptune type 2 10G, 1 1G")); 6583 goto error_exit; 6584 case 0: 6585 /* 6586 * 2 10G: 2XGF NIC, Marvell, Goa, Huron with 2 XAUI 6587 * cards, etc. 6588 */ 6589 if (((port_pcs_dev_id[0] == PHY_BCM8704_FAMILY) && 6590 (port_pcs_dev_id[1] == PHY_BCM8704_FAMILY)) || 6591 ((port_pma_pmd_dev_id[0] == PHY_BCM8704_FAMILY) && 6592 (port_pma_pmd_dev_id[1] == PHY_BCM8704_FAMILY)) || 6593 ((port_pcs_dev_id[0] == MARVELL_88X201X_PHY_ID) && 6594 (port_pcs_dev_id[1] == MARVELL_88X201X_PHY_ID)) || 6595 ((port_pma_pmd_dev_id[0] == 6596 MARVELL_88X201X_PHY_ID) && 6597 (port_pma_pmd_dev_id[1] == 6598 MARVELL_88X201X_PHY_ID))) { 6599 6600 /* 6601 * Check the first phy port address against 6602 * the known phy start addresses to determine 6603 * the platform type. 6604 */ 6605 6606 switch (port_fd_arr[0]) { 6607 case NEPTUNE_CLAUSE45_PORT_ADDR_BASE: 6608 /* 6609 * The Marvell case also falls into 6610 * this case as 6611 * MRVL88X2011_NEPTUNE_PORT_ADDR_BASE 6612 * == NEPTUNE_CLAUSE45_PORT_ADDR_BASE. 6613 * This is OK for the 2 10G case. 6614 */ 6615 hw_p->niu_type = NEPTUNE_2_10GF; 6616 hw_p->platform_type = 6617 P_NEPTUNE_ATLAS_2PORT; 6618 break; 6619 case GOA_CLAUSE45_PORT_ADDR_BASE: 6620 if (hw_p->platform_type != 6621 P_NEPTUNE_NIU) { 6622 hw_p->platform_type = 6623 P_NEPTUNE_GENERIC; 6624 hw_p->niu_type = 6625 NEPTUNE_2_10GF; 6626 } 6627 break; 6628 default: 6629 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6630 "Unsupported neptune type 2 - 1")); 6631 goto error_exit; 6632 } 6633 6634 for (i = 0; i < 2; i++) { 6635 hw_p->xcvr_addr[i] = port_fd_arr[i]; 6636 } 6637 6638 /* Both XAUI slots have copper XAUI cards */ 6639 } else if ((((port_pcs_dev_id[0] & TN1010_DEV_ID_MASK) 6640 == TN1010_DEV_ID) && 6641 ((port_pcs_dev_id[1] & TN1010_DEV_ID_MASK) 6642 == TN1010_DEV_ID)) || 6643 (((port_pma_pmd_dev_id[0] & TN1010_DEV_ID_MASK) 6644 == TN1010_DEV_ID) && 6645 ((port_pma_pmd_dev_id[1] & TN1010_DEV_ID_MASK) 6646 == TN1010_DEV_ID))) { 6647 hw_p->niu_type = NEPTUNE_2_TN1010; 6648 hw_p->xcvr_addr[0] = port_fd_arr[0]; 6649 hw_p->xcvr_addr[1] = port_fd_arr[1]; 6650 6651 /* Slot0 has fiber XAUI, slot1 has copper XAUI */ 6652 } else if ((port_pcs_dev_id[0] == PHY_BCM8704_FAMILY && 6653 (port_pcs_dev_id[1] & TN1010_DEV_ID_MASK) 6654 == TN1010_DEV_ID) || 6655 (port_pma_pmd_dev_id[0] == PHY_BCM8704_FAMILY && 6656 (port_pma_pmd_dev_id[1] & TN1010_DEV_ID_MASK) == 6657 TN1010_DEV_ID)) { 6658 hw_p->niu_type = NEPTUNE_1_10GF_1_TN1010; 6659 hw_p->xcvr_addr[0] = port_fd_arr[0]; 6660 hw_p->xcvr_addr[1] = port_fd_arr[1]; 6661 6662 /* Slot0 has copper XAUI, slot1 has fiber XAUI */ 6663 } else if ((port_pcs_dev_id[1] == PHY_BCM8704_FAMILY && 6664 (port_pcs_dev_id[0] & TN1010_DEV_ID_MASK) 6665 == TN1010_DEV_ID) || 6666 (port_pma_pmd_dev_id[1] == PHY_BCM8704_FAMILY && 6667 (port_pma_pmd_dev_id[0] & TN1010_DEV_ID_MASK) 6668 == TN1010_DEV_ID)) { 6669 hw_p->niu_type = NEPTUNE_1_TN1010_1_10GF; 6670 hw_p->xcvr_addr[0] = port_fd_arr[0]; 6671 hw_p->xcvr_addr[1] = port_fd_arr[1]; 6672 6673 } else { 6674 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6675 "Unsupported neptune type 2")); 6676 goto error_exit; 6677 } 6678 break; 6679 6680 case 4: 6681 if (nxge_get_num_of_xaui( 6682 port_pma_pmd_dev_id, port_pcs_dev_id, 6683 port_phy_id, &num_xaui) == NXGE_ERROR) { 6684 goto error_exit; 6685 } 6686 if (num_xaui != 2) 6687 goto error_exit; 6688 6689 /* 6690 * Maramba with 2 XAUIs (either fiber or copper) 6691 * 6692 * Check the first phy port address against 6693 * the known phy start addresses to determine 6694 * the platform type. 6695 */ 6696 switch (phy_fd_arr[0]) { 6697 case MARAMBA_P0_CLAUSE22_PORT_ADDR_BASE: 6698 hw_p->platform_type = 6699 P_NEPTUNE_MARAMBA_P0; 6700 break; 6701 case MARAMBA_P1_CLAUSE22_PORT_ADDR_BASE: 6702 hw_p->platform_type = 6703 P_NEPTUNE_MARAMBA_P1; 6704 break; 6705 default: 6706 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6707 "Unknown port %d...Cannot " 6708 "determine platform type", i)); 6709 goto error_exit; 6710 } 6711 6712 hw_p->xcvr_addr[0] = port_fd_arr[0]; 6713 hw_p->xcvr_addr[1] = port_fd_arr[1]; 6714 hw_p->xcvr_addr[2] = phy_fd_arr[2]; 6715 hw_p->xcvr_addr[3] = phy_fd_arr[3]; 6716 6717 /* slot0 has fiber XAUI, slot1 has Cu XAUI */ 6718 if (port_pcs_dev_id[0] == PHY_BCM8704_FAMILY && 6719 (port_pcs_dev_id[1] & TN1010_DEV_ID_MASK) 6720 == TN1010_DEV_ID) { 6721 hw_p->niu_type = NEPTUNE_1_10GF_1_TN1010_2_1GC; 6722 6723 /* slot0 has Cu XAUI, slot1 has fiber XAUI */ 6724 } else if (((port_pcs_dev_id[0] & TN1010_DEV_ID_MASK) 6725 == TN1010_DEV_ID) && 6726 port_pcs_dev_id[1] == PHY_BCM8704_FAMILY) { 6727 hw_p->niu_type = NEPTUNE_1_TN1010_1_10GF_2_1GC; 6728 6729 /* Both slots have fiber XAUI */ 6730 } else if (port_pcs_dev_id[0] == PHY_BCM8704_FAMILY && 6731 port_pcs_dev_id[1] == PHY_BCM8704_FAMILY) { 6732 hw_p->niu_type = NEPTUNE_2_10GF_2_1GC; 6733 6734 /* Both slots have copper XAUI */ 6735 } else if (((port_pcs_dev_id[0] & TN1010_DEV_ID_MASK) 6736 == TN1010_DEV_ID) && 6737 (port_pcs_dev_id[1] & TN1010_DEV_ID_MASK) 6738 == TN1010_DEV_ID) { 6739 hw_p->niu_type = NEPTUNE_2_TN1010_2_1GC; 6740 6741 } else { 6742 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6743 "Unsupported neptune type 3")); 6744 goto error_exit; 6745 } 6746 break; 6747 default: 6748 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6749 "Unsupported neptune type 5")); 6750 goto error_exit; 6751 } 6752 break; 6753 case 1: /* Only one clause45 port */ 6754 switch (total_phy_fd) { /* Number of clause22 ports */ 6755 case 3: 6756 /* 6757 * TODO 3 1G, 1 10G mode. 6758 * Differentiate between 1_1G_1_10G_2_1G and 6759 * 1_10G_3_1G 6760 */ 6761 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6762 "Unsupported neptune type 7")); 6763 goto error_exit; 6764 case 2: 6765 /* 6766 * TODO 2 1G, 1 10G mode. 6767 * Differentiate between 1_1G_1_10G_1_1G and 6768 * 1_10G_2_1G 6769 */ 6770 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6771 "Unsupported neptune type 8")); 6772 goto error_exit; 6773 case 1: 6774 /* 6775 * TODO 1 1G, 1 10G mode. 6776 * Differentiate between 1_1G_1_10G and 6777 * 1_10G_1_1G 6778 */ 6779 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6780 "Unsupported neptune type 9")); 6781 goto error_exit; 6782 case 0: /* N2 with 1 XAUI (fiber or copper) */ 6783 /* Fiber XAUI */ 6784 if (port_pcs_dev_id[0] == PHY_BCM8704_FAMILY || 6785 port_pma_pmd_dev_id[0] == PHY_BCM8704_FAMILY) { 6786 6787 /* 6788 * Check the first phy port address against 6789 * the known phy start addresses to determine 6790 * the platform type. 6791 */ 6792 6793 switch (port_fd_arr[0]) { 6794 case N2_CLAUSE45_PORT_ADDR_BASE: 6795 case (N2_CLAUSE45_PORT_ADDR_BASE + 1): 6796 case ALT_GOA_CLAUSE45_PORT1_ADDR: 6797 /* 6798 * If hw_p->platform_type == 6799 * P_NEPTUNE_NIU, then portmode 6800 * is already known, so there is 6801 * no need to figure out hw_p-> 6802 * platform_type because 6803 * platform_type is only for 6804 * figuring out portmode. 6805 */ 6806 if (hw_p->platform_type != 6807 P_NEPTUNE_NIU) { 6808 hw_p->platform_type = 6809 P_NEPTUNE_GENERIC; 6810 hw_p->niu_type = 6811 NEPTUNE_2_10GF; 6812 } 6813 break; 6814 default: 6815 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6816 "Unsupported neptune type 10")); 6817 goto error_exit; 6818 } 6819 /* 6820 * For GOA, which is a hot swappable PHY, the 6821 * phy address to function number mapping 6822 * should be preserved, i.e., addr 16 is 6823 * assigned to function 0 and 20 to function 1 6824 * But for Huron XAUI, the assignment should 6825 * be by function number, i.e., whichever 6826 * function number attaches should be 6827 * assigned the available PHY (this is required 6828 * primarily to support pre-production Huron 6829 * boards where function 0 is mapped to addr 17 6830 */ 6831 if (port_fd_arr[0] == 6832 ALT_GOA_CLAUSE45_PORT1_ADDR) { 6833 hw_p->xcvr_addr[1] = port_fd_arr[0]; 6834 } else { 6835 hw_p->xcvr_addr[nxgep->function_num] = 6836 port_fd_arr[0]; 6837 } 6838 6839 /* A 10G copper XAUI in either slot0 or slot1 */ 6840 } else if ((port_pcs_dev_id[0] & TN1010_DEV_ID_MASK) 6841 == TN1010_DEV_ID || 6842 (port_pma_pmd_dev_id[0] & TN1010_DEV_ID_MASK) 6843 == TN1010_DEV_ID) { 6844 switch (port_fd_arr[0]) { 6845 /* The XAUI is in slot0 */ 6846 case N2_CLAUSE45_PORT_ADDR_BASE: 6847 hw_p->niu_type = NEPTUNE_1_TN1010; 6848 break; 6849 6850 /* The XAUI is in slot1 */ 6851 case (N2_CLAUSE45_PORT_ADDR_BASE + 1): 6852 hw_p->niu_type 6853 = NEPTUNE_1_NONE_1_TN1010; 6854 break; 6855 default: 6856 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6857 "Unsupported XAUI port address")); 6858 goto error_exit; 6859 } 6860 hw_p->xcvr_addr[nxgep->function_num] 6861 = port_fd_arr[0]; 6862 6863 } else { 6864 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6865 "Unsupported PHY type")); 6866 goto error_exit; 6867 } 6868 break; 6869 case 4: /* Maramba always have 4 clause 45 ports */ 6870 6871 /* Maramba with 1 XAUI */ 6872 if ((port_pcs_dev_id[0] != PHY_BCM8704_FAMILY) && 6873 (port_pma_pmd_dev_id[0] != PHY_BCM8704_FAMILY) && 6874 ((port_pcs_dev_id[0] & TN1010_DEV_ID_MASK) 6875 != TN1010_DEV_ID) && 6876 ((port_pma_pmd_dev_id[0] & TN1010_DEV_ID_MASK) 6877 != TN1010_DEV_ID)) { 6878 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6879 "Unsupported neptune type 12")); 6880 goto error_exit; 6881 } 6882 6883 /* 6884 * Check the first phy port address against 6885 * the known phy start addresses to determine 6886 * the platform type. 6887 */ 6888 switch (phy_fd_arr[0]) { 6889 case MARAMBA_P0_CLAUSE22_PORT_ADDR_BASE: 6890 hw_p->platform_type = 6891 P_NEPTUNE_MARAMBA_P0; 6892 break; 6893 case MARAMBA_P1_CLAUSE22_PORT_ADDR_BASE: 6894 hw_p->platform_type = 6895 P_NEPTUNE_MARAMBA_P1; 6896 break; 6897 default: 6898 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6899 "Unknown port %d...Cannot " 6900 "determine platform type 10 - 2", 6901 i)); 6902 goto error_exit; 6903 } 6904 6905 /* 6906 * Check the clause45 address to determine 6907 * if XAUI is in port 0 or port 1. 6908 */ 6909 switch (port_fd_arr[0]) { 6910 case MARAMBA_CLAUSE45_PORT_ADDR_BASE: 6911 if (port_pcs_dev_id[0] 6912 == PHY_BCM8704_FAMILY || 6913 port_pma_pmd_dev_id[0] 6914 == PHY_BCM8704_FAMILY) { 6915 hw_p->niu_type 6916 = NEPTUNE_1_10GF_3_1GC; 6917 } else { 6918 hw_p->niu_type 6919 = NEPTUNE_1_TN1010_3_1GC; 6920 } 6921 hw_p->xcvr_addr[0] = port_fd_arr[0]; 6922 for (i = 1; i < NXGE_MAX_PORTS; i++) { 6923 hw_p->xcvr_addr[i] = 6924 phy_fd_arr[i]; 6925 } 6926 break; 6927 case (MARAMBA_CLAUSE45_PORT_ADDR_BASE + 1): 6928 if (port_pcs_dev_id[0] 6929 == PHY_BCM8704_FAMILY || 6930 port_pma_pmd_dev_id[0] 6931 == PHY_BCM8704_FAMILY) { 6932 hw_p->niu_type = 6933 NEPTUNE_1_1GC_1_10GF_2_1GC; 6934 } else { 6935 hw_p->niu_type = 6936 NEPTUNE_1_1GC_1_TN1010_2_1GC; 6937 } 6938 hw_p->xcvr_addr[0] = phy_fd_arr[0]; 6939 hw_p->xcvr_addr[1] = port_fd_arr[0]; 6940 hw_p->xcvr_addr[2] = phy_fd_arr[2]; 6941 hw_p->xcvr_addr[3] = phy_fd_arr[3]; 6942 break; 6943 default: 6944 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6945 "Unsupported neptune type 11")); 6946 goto error_exit; 6947 } 6948 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6949 "Maramba with 1 XAUI (fiber or copper)")); 6950 break; 6951 default: 6952 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6953 "Unsupported neptune type 13")); 6954 goto error_exit; 6955 } 6956 break; 6957 case 0: /* 4 ports Neptune based NIC */ 6958 switch (total_phy_fd) { 6959 case 4: 6960 if ((port_phy_id[0] == PHY_BCM5464R_FAMILY) && 6961 (port_phy_id[1] == PHY_BCM5464R_FAMILY) && 6962 (port_phy_id[2] == PHY_BCM5464R_FAMILY) && 6963 (port_phy_id[3] == PHY_BCM5464R_FAMILY)) { 6964 6965 /* 6966 * Check the first phy port address against 6967 * the known phy start addresses to determine 6968 * the platform type. 6969 */ 6970 switch (phy_fd_arr[0]) { 6971 case MARAMBA_P1_CLAUSE22_PORT_ADDR_BASE: 6972 hw_p->platform_type = 6973 P_NEPTUNE_MARAMBA_P1; 6974 break; 6975 case NEPTUNE_CLAUSE22_PORT_ADDR_BASE: 6976 hw_p->platform_type = 6977 P_NEPTUNE_ATLAS_4PORT; 6978 break; 6979 default: 6980 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6981 "Unknown port %d...Cannot " 6982 "determine platform type", i)); 6983 goto error_exit; 6984 } 6985 hw_p->niu_type = NEPTUNE_4_1GC; 6986 for (i = 0; i < NXGE_MAX_PORTS; i++) { 6987 hw_p->xcvr_addr[i] = phy_fd_arr[i]; 6988 } 6989 } else { 6990 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6991 "Unsupported neptune type 14")); 6992 goto error_exit; 6993 } 6994 break; 6995 case 3: 6996 /* TODO 3 1G mode */ 6997 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6998 "Unsupported neptune type 15")); 6999 goto error_exit; 7000 case 2: 7001 /* TODO 2 1G mode */ 7002 if ((port_phy_id[0] == PHY_BCM5482_FAMILY) && 7003 (port_phy_id[1] == PHY_BCM5482_FAMILY)) { 7004 hw_p->platform_type = P_NEPTUNE_GENERIC; 7005 hw_p->niu_type = NEPTUNE_2_1GRF; 7006 hw_p->xcvr_addr[2] = phy_fd_arr[0]; 7007 hw_p->xcvr_addr[3] = phy_fd_arr[1]; 7008 } else { 7009 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7010 "Unsupported neptune type 16")); 7011 goto error_exit; 7012 } 7013 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7014 "2 RGMII Fiber ports - RTM")); 7015 break; 7016 7017 case 1: 7018 /* TODO 1 1G mode */ 7019 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7020 "Unsupported neptune type 17")); 7021 goto error_exit; 7022 default: 7023 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7024 "Unsupported neptune type 18, total phy fd %d", 7025 total_phy_fd)); 7026 goto error_exit; 7027 } 7028 break; 7029 default: 7030 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7031 "Unsupported neptune type 19")); 7032 goto error_exit; 7033 } 7034 7035 scan_exit: 7036 7037 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_scan_ports_phy, " 7038 "niu type [0x%x]\n", hw_p->niu_type)); 7039 return (status); 7040 7041 error_exit: 7042 return (NXGE_ERROR); 7043 } 7044 7045 boolean_t 7046 nxge_is_valid_local_mac(ether_addr_st mac_addr) 7047 { 7048 if ((mac_addr.ether_addr_octet[0] & 0x01) || 7049 (ether_cmp(&mac_addr, ðerbroadcastaddr) == 0) || 7050 (ether_cmp(&mac_addr, ðerzeroaddr) == 0)) 7051 return (B_FALSE); 7052 else 7053 return (B_TRUE); 7054 } 7055 7056 static void 7057 nxge_bcm5464_link_led_off(p_nxge_t nxgep) { 7058 7059 npi_status_t rs = NPI_SUCCESS; 7060 uint8_t xcvr_portn; 7061 uint8_t portn = NXGE_GET_PORT_NUM(nxgep->function_num); 7062 7063 NXGE_DEBUG_MSG((nxgep, MIF_CTL, "==> nxge_bcm5464_link_led_off")); 7064 7065 if (nxgep->nxge_hw_p->platform_type == P_NEPTUNE_MARAMBA_P1) { 7066 xcvr_portn = MARAMBA_P1_CLAUSE22_PORT_ADDR_BASE; 7067 } else if (nxgep->nxge_hw_p->platform_type == P_NEPTUNE_MARAMBA_P0) { 7068 xcvr_portn = MARAMBA_P0_CLAUSE22_PORT_ADDR_BASE; 7069 } 7070 /* 7071 * For Altas 4-1G copper, Xcvr port numbers are 7072 * swapped with ethernet port number. This is 7073 * designed for better signal integrity in routing. 7074 */ 7075 switch (portn) { 7076 case 0: 7077 xcvr_portn += 3; 7078 break; 7079 case 1: 7080 xcvr_portn += 2; 7081 break; 7082 case 2: 7083 xcvr_portn += 1; 7084 break; 7085 case 3: 7086 default: 7087 break; 7088 } 7089 7090 MUTEX_ENTER(&nxgep->nxge_hw_p->nxge_mdio_lock); 7091 rs = npi_mac_mif_mii_write(nxgep->npi_handle, 7092 xcvr_portn, BCM5464R_MISC, 0xb4ee); 7093 if (rs != NPI_SUCCESS) { 7094 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7095 "<== nxge_bcm5464_link_led_off: npi_mac_mif_mii_write " 7096 "returned error 0x[%x]", rs)); 7097 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 7098 return; 7099 } 7100 7101 rs = npi_mac_mif_mii_write(nxgep->npi_handle, 7102 xcvr_portn, BCM5464R_MISC, 0xb8ee); 7103 if (rs != NPI_SUCCESS) { 7104 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7105 "<== nxge_bcm5464_link_led_off: npi_mac_mif_mii_write " 7106 "returned error 0x[%x]", rs)); 7107 } 7108 7109 MUTEX_EXIT(&nxgep->nxge_hw_p->nxge_mdio_lock); 7110 } 7111 7112 static nxge_status_t 7113 nxge_mii_get_link_mode(p_nxge_t nxgep) 7114 { 7115 p_nxge_stats_t statsp; 7116 uint8_t xcvr_portn; 7117 p_mii_regs_t mii_regs; 7118 mii_mode_control_stat_t mode; 7119 int status = NXGE_OK; 7120 7121 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_mii_get_link_mode")); 7122 7123 statsp = nxgep->statsp; 7124 xcvr_portn = statsp->mac_stats.xcvr_portn; 7125 mii_regs = NULL; 7126 mode.value = 0; 7127 mode.bits.shadow = NXGE_MII_MODE_CONTROL_REG; 7128 #if defined(__i386) 7129 if ((status = nxge_mii_write(nxgep, xcvr_portn, 7130 (uint8_t)(uint32_t)(&mii_regs->shadow), 7131 mode.value)) != NXGE_OK) { 7132 goto fail; 7133 #else 7134 if ((status = nxge_mii_write(nxgep, xcvr_portn, 7135 (uint8_t)(uint64_t)(&mii_regs->shadow), 7136 mode.value)) != NXGE_OK) { 7137 goto fail; 7138 #endif 7139 } 7140 #if defined(__i386) 7141 if ((status = nxge_mii_read(nxgep, xcvr_portn, 7142 (uint8_t)(uint32_t)(&mii_regs->shadow), 7143 &mode.value)) != NXGE_OK) { 7144 goto fail; 7145 } 7146 #else 7147 if ((status = nxge_mii_read(nxgep, xcvr_portn, 7148 (uint8_t)(uint64_t)(&mii_regs->shadow), 7149 &mode.value)) != NXGE_OK) { 7150 goto fail; 7151 } 7152 #endif 7153 7154 if (mode.bits.mode == NXGE_MODE_SELECT_FIBER) { 7155 nxgep->mac.portmode = PORT_1G_RGMII_FIBER; 7156 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7157 "nxge_mii_get_link_mode: fiber mode")); 7158 } 7159 7160 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7161 "nxge_mii_get_link_mode: " 7162 "(address 0x%x) port 0x%x mode value 0x%x link mode 0x%x", 7163 NXGE_MII_MODE_CONTROL_REG, xcvr_portn, 7164 mode.value, nxgep->mac.portmode)); 7165 7166 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7167 "<== nxge_mii_get_link_mode")); 7168 return (status); 7169 fail: 7170 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7171 "<== nxge_mii_get_link_mode (failed)")); 7172 return (NXGE_ERROR); 7173 } 7174 7175 nxge_status_t 7176 nxge_mac_set_framesize(p_nxge_t nxgep) 7177 { 7178 npi_attr_t ap; 7179 uint8_t portn; 7180 npi_handle_t handle; 7181 npi_status_t rs = NPI_SUCCESS; 7182 7183 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_mac_set_framesize")); 7184 7185 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 7186 handle = nxgep->npi_handle; 7187 7188 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7189 "==> nxge_mac_sec_framesize: port<%d> " 7190 "min framesize %d max framesize %d ", 7191 portn, 7192 nxgep->mac.minframesize, 7193 nxgep->mac.maxframesize)); 7194 7195 SET_MAC_ATTR2(handle, ap, portn, 7196 MAC_PORT_FRAME_SIZE, 7197 nxgep->mac.minframesize, 7198 nxgep->mac.maxframesize, 7199 rs); 7200 if (rs != NPI_SUCCESS) { 7201 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7202 "<== nxge_mac_set_framesize: failed to configure " 7203 "max/min frame size port %d", portn)); 7204 7205 return (NXGE_ERROR | rs); 7206 } 7207 7208 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7209 "<== nxge_mac_set_framesize: port<%d>", portn)); 7210 7211 return (NXGE_OK); 7212 } 7213 7214 static nxge_status_t 7215 nxge_get_num_of_xaui(uint32_t *port_pma_pmd_dev_id, 7216 uint32_t *port_pcs_dev_id, uint32_t *port_phy_id, uint8_t *num_xaui) 7217 { 7218 uint8_t i; 7219 7220 for (i = 0; i < 4; i++) { 7221 if (port_phy_id[i] != PHY_BCM5464R_FAMILY) 7222 return (NXGE_ERROR); 7223 } 7224 7225 *num_xaui = 0; 7226 if ((port_pma_pmd_dev_id[0] == PHY_BCM8704_FAMILY && 7227 port_pcs_dev_id[0] == PHY_BCM8704_FAMILY) || 7228 (((port_pma_pmd_dev_id[0] & TN1010_DEV_ID_MASK) 7229 == TN1010_DEV_ID) && 7230 ((port_pcs_dev_id[0] & TN1010_DEV_ID_MASK) 7231 == TN1010_DEV_ID))) { 7232 (*num_xaui) ++; 7233 } 7234 if ((port_pma_pmd_dev_id[1] == PHY_BCM8704_FAMILY && 7235 port_pcs_dev_id[1] == PHY_BCM8704_FAMILY) || 7236 (((port_pma_pmd_dev_id[1] & TN1010_DEV_ID_MASK) 7237 == TN1010_DEV_ID) && 7238 ((port_pcs_dev_id[1] & TN1010_DEV_ID_MASK) 7239 == TN1010_DEV_ID))) { 7240 (*num_xaui) ++; 7241 } 7242 return (NXGE_OK); 7243 } 7244 7245 /* 7246 * Instruction from Teranetics: Once you detect link is up, go 7247 * read Reg 30.1.4 for link speed: '1' for 1G and '0' for 10G. You 7248 * may want to qualify it by first checking Register 30.1.7:6 and 7249 * making sure it reads "01" (Auto-Neg Complete). 7250 * 7251 * If this function is called when the link is down or before auto- 7252 * negotiation has completed, then the speed of the PHY is not certain. 7253 * In such cases, this function returns 1G as the default speed with 7254 * NXGE_OK status instead of NXGE_ERROR. It is OK to initialize the 7255 * driver based on a default speed because this function will be called 7256 * again when the link comes up. Returning NXGE_ERROR, which may 7257 * cause brutal chain reaction in caller functions, is not necessary. 7258 */ 7259 static nxge_status_t 7260 nxge_get_tn1010_speed(p_nxge_t nxgep, uint16_t *speed) 7261 { 7262 uint8_t phy_port_addr, autoneg_stat, link_up; 7263 nxge_status_t status = NXGE_OK; 7264 uint16_t val; 7265 uint8_t portn = NXGE_GET_PORT_NUM(nxgep->function_num); 7266 7267 /* Set default speed to 10G */ 7268 *speed = TN1010_SPEED_10G; 7269 7270 /* Set Clause 45 */ 7271 npi_mac_mif_set_indirect_mode(nxgep->npi_handle, B_TRUE); 7272 7273 phy_port_addr = nxgep->nxge_hw_p->xcvr_addr[portn]; 7274 7275 /* Check Device 1 Register 0xA bit0 for link up status */ 7276 status = nxge_mdio_read(nxgep, phy_port_addr, 7277 TN1010_AUTONEG_DEV_ADDR, TN1010_AUTONEG_STATUS_REG, &val); 7278 if (status != NXGE_OK) 7279 goto fail; 7280 7281 link_up = ((val & TN1010_AN_LINK_STAT_BIT) 7282 ? B_TRUE : B_FALSE); 7283 if (link_up == B_FALSE) { 7284 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7285 "nxge_get_tn1010_speed: link is down")); 7286 goto nxge_get_tn1010_speed_exit; 7287 } 7288 7289 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 7290 TN1010_VENDOR_MMD1_DEV_ADDR, TN1010_VENDOR_MMD1_STATUS_REG, 7291 &val)) != NXGE_OK) { 7292 goto fail; 7293 } 7294 autoneg_stat = (val & TN1010_VENDOR_MMD1_AN_STAT_BITS) >> 7295 TN1010_VENDOR_MMD1_AN_STAT_SHIFT; 7296 7297 /* 7298 * Return NXGE_OK even when we can not get a settled speed. In 7299 * such case, the speed reported should not be trusted but that 7300 * is OK, we will call this function periodically and will get 7301 * the correct speed after the link is up. 7302 */ 7303 switch (autoneg_stat) { 7304 case TN1010_AN_IN_PROG: 7305 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7306 "nxge_get_tn1010_speed: Auto-negotiation in progress")); 7307 break; 7308 case TN1010_AN_COMPLETE: 7309 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 7310 TN1010_VENDOR_MMD1_DEV_ADDR, 7311 TN1010_VENDOR_MMD1_STATUS_REG, 7312 &val)) != NXGE_OK) { 7313 goto fail; 7314 } 7315 *speed = (val & TN1010_VENDOR_MMD1_AN_SPEED_BIT) >> 7316 TN1010_VENDOR_MMD1_AN_SPEED_SHIFT; 7317 break; 7318 case TN1010_AN_RSVD: 7319 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7320 "nxge_get_tn1010_speed: Autoneg status undefined")); 7321 break; 7322 case TN1010_AN_FAILED: 7323 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 7324 "nxge_get_tn1010_speed: Auto-negotiation failed")); 7325 break; 7326 default: 7327 break; 7328 } 7329 nxge_get_tn1010_speed_exit: 7330 return (NXGE_OK); 7331 fail: 7332 return (status); 7333 } 7334 7335 7336 /* 7337 * Teranetics TN1010 PHY chip supports both 1G and 10G modes, this function 7338 * figures out the speed of the PHY determined by the autonegotiation 7339 * process and sets the following 3 parameters, 7340 * nxgep->mac.portmode 7341 * nxgep->statsp->mac_stats.link_speed 7342 * nxgep->statsp->mac_stats.xcvr_inuse 7343 */ 7344 static nxge_status_t 7345 nxge_set_tn1010_param(p_nxge_t nxgep) 7346 { 7347 uint16_t speed; 7348 7349 if (nxge_get_tn1010_speed(nxgep, &speed) != NXGE_OK) { 7350 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7351 "nxge_set_tn1010_param: " 7352 "Failed to get TN1010 speed")); 7353 return (NXGE_ERROR); 7354 } 7355 if (speed == TN1010_SPEED_1G) { 7356 nxgep->mac.portmode = PORT_1G_TN1010; 7357 nxgep->statsp->mac_stats.link_speed = 1000; 7358 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 7359 } else { 7360 nxgep->mac.portmode = PORT_10G_TN1010; 7361 nxgep->statsp->mac_stats.link_speed = 10000; 7362 nxgep->statsp->mac_stats.xcvr_inuse = XPCS_XCVR; 7363 } 7364 return (NXGE_OK); 7365 } 7366 7367 #ifdef NXGE_DEBUG 7368 static void 7369 nxge_mii_dump(p_nxge_t nxgep) 7370 { 7371 p_nxge_stats_t statsp; 7372 uint8_t xcvr_portn; 7373 p_mii_regs_t mii_regs; 7374 mii_bmcr_t bmcr; 7375 mii_bmsr_t bmsr; 7376 mii_idr1_t idr1; 7377 mii_idr2_t idr2; 7378 mii_mode_control_stat_t mode; 7379 p_nxge_param_t param_arr; 7380 7381 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_mii_dump")); 7382 7383 statsp = nxgep->statsp; 7384 xcvr_portn = statsp->mac_stats.xcvr_portn; 7385 7386 mii_regs = NULL; 7387 7388 #if defined(__i386) 7389 (void) nxge_mii_read(nxgep, nxgep->statsp->mac_stats.xcvr_portn, 7390 (uint8_t)(uint32_t)(&mii_regs->bmcr), &bmcr.value); 7391 #else 7392 (void) nxge_mii_read(nxgep, nxgep->statsp->mac_stats.xcvr_portn, 7393 (uint8_t)(uint64_t)(&mii_regs->bmcr), &bmcr.value); 7394 #endif 7395 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7396 "nxge_mii_dump: bmcr (0) xcvr 0x%x value 0x%x", 7397 xcvr_portn, bmcr.value)); 7398 7399 #if defined(__i386) 7400 (void) nxge_mii_read(nxgep, 7401 nxgep->statsp->mac_stats.xcvr_portn, 7402 (uint8_t)(uint32_t)(&mii_regs->bmsr), &bmsr.value); 7403 #else 7404 (void) nxge_mii_read(nxgep, 7405 nxgep->statsp->mac_stats.xcvr_portn, 7406 (uint8_t)(uint64_t)(&mii_regs->bmsr), &bmsr.value); 7407 #endif 7408 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7409 "nxge_mii_dump: bmsr (1) xcvr 0x%x value 0x%x", 7410 xcvr_portn, bmsr.value)); 7411 7412 #if defined(__i386) 7413 (void) nxge_mii_read(nxgep, 7414 nxgep->statsp->mac_stats.xcvr_portn, 7415 (uint8_t)(uint32_t)(&mii_regs->idr1), &idr1.value); 7416 #else 7417 (void) nxge_mii_read(nxgep, 7418 nxgep->statsp->mac_stats.xcvr_portn, 7419 (uint8_t)(uint64_t)(&mii_regs->idr1), &idr1.value); 7420 #endif 7421 7422 7423 #if defined(__i386) 7424 (void) nxge_mii_read(nxgep, 7425 nxgep->statsp->mac_stats.xcvr_portn, 7426 (uint8_t)(uint32_t)(&mii_regs->idr2), &idr2.value); 7427 #else 7428 (void) nxge_mii_read(nxgep, 7429 nxgep->statsp->mac_stats.xcvr_portn, 7430 (uint8_t)(uint64_t)(&mii_regs->idr2), &idr2.value); 7431 #endif 7432 7433 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7434 "nxge_mii_dump: idr1 (2) xcvr 0x%x value 0x%x", 7435 xcvr_portn, idr1.value)); 7436 7437 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7438 "nxge_mii_dump: idr2 (3) xcvr 0x%x value 0x%x", 7439 xcvr_portn, idr2.value)); 7440 7441 mode.value = 0; 7442 mode.bits.shadow = NXGE_MII_MODE_CONTROL_REG; 7443 7444 #if defined(__i386) 7445 (void) nxge_mii_write(nxgep, xcvr_portn, 7446 (uint8_t)(uint32_t)(&mii_regs->shadow), mode.value); 7447 7448 (void) nxge_mii_read(nxgep, xcvr_portn, 7449 (uint8_t)(uint32_t)(&mii_regs->shadow), &mode.value); 7450 #else 7451 (void) nxge_mii_write(nxgep, xcvr_portn, 7452 (uint8_t)(uint64_t)(&mii_regs->shadow), mode.value); 7453 7454 (void) nxge_mii_read(nxgep, xcvr_portn, 7455 (uint8_t)(uint64_t)(&mii_regs->shadow), &mode.value); 7456 #endif 7457 7458 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 7459 "nxge_mii_dump: mode control xcvr 0x%x value 0x%x", 7460 xcvr_portn, mode.value)); 7461 } 7462 #endif 7463