xref: /titanic_51/usr/src/uts/common/io/nxge/nxge_fzc.c (revision f500b19684bd0346ac05bec02a50af07f369da1a)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #include	<nxge_impl.h>
27 #include	<npi_mac.h>
28 #include	<npi_rxdma.h>
29 #include	<nxge_hio.h>
30 
31 #if	defined(sun4v) && defined(NIU_LP_WORKAROUND)
32 static int	nxge_herr2kerr(uint64_t);
33 #endif
34 
35 static nxge_status_t nxge_init_fzc_rdc_pages(p_nxge_t,
36     uint16_t, dma_log_page_t *, dma_log_page_t *);
37 
38 static nxge_status_t nxge_init_fzc_tdc_pages(p_nxge_t,
39     uint16_t, dma_log_page_t *, dma_log_page_t *);
40 
41 /*
42  * The following interfaces are controlled by the
43  * function control registers. Some global registers
44  * are to be initialized by only byt one of the 2/4 functions.
45  * Use the test and set register.
46  */
47 /*ARGSUSED*/
48 nxge_status_t
49 nxge_test_and_set(p_nxge_t nxgep, uint8_t tas)
50 {
51 	npi_handle_t		handle;
52 	npi_status_t		rs = NPI_SUCCESS;
53 
54 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
55 	if ((rs = npi_dev_func_sr_sr_get_set_clear(handle, tas))
56 	    != NPI_SUCCESS) {
57 		return (NXGE_ERROR | rs);
58 	}
59 
60 	return (NXGE_OK);
61 }
62 
63 nxge_status_t
64 nxge_set_fzc_multi_part_ctl(p_nxge_t nxgep, boolean_t mpc)
65 {
66 	npi_handle_t		handle;
67 	npi_status_t		rs = NPI_SUCCESS;
68 
69 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_set_fzc_multi_part_ctl"));
70 
71 	/*
72 	 * In multi-partitioning, the partition manager
73 	 * who owns function zero should set this multi-partition
74 	 * control bit.
75 	 */
76 	if (nxgep->use_partition && nxgep->function_num) {
77 		return (NXGE_ERROR);
78 	}
79 
80 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
81 	if ((rs = npi_fzc_mpc_set(handle, mpc)) != NPI_SUCCESS) {
82 		NXGE_DEBUG_MSG((nxgep, DMA_CTL,
83 		    "<== nxge_set_fzc_multi_part_ctl"));
84 		return (NXGE_ERROR | rs);
85 	}
86 
87 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_set_fzc_multi_part_ctl"));
88 
89 	return (NXGE_OK);
90 }
91 
92 nxge_status_t
93 nxge_get_fzc_multi_part_ctl(p_nxge_t nxgep, boolean_t *mpc_p)
94 {
95 	npi_handle_t		handle;
96 	npi_status_t		rs = NPI_SUCCESS;
97 
98 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_get_fzc_multi_part_ctl"));
99 
100 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
101 	if ((rs = npi_fzc_mpc_get(handle, mpc_p)) != NPI_SUCCESS) {
102 		NXGE_DEBUG_MSG((nxgep, DMA_CTL,
103 		    "<== nxge_set_fzc_multi_part_ctl"));
104 		return (NXGE_ERROR | rs);
105 	}
106 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_get_fzc_multi_part_ctl"));
107 
108 	return (NXGE_OK);
109 }
110 
111 /*
112  * System interrupt registers that are under function zero
113  * management.
114  */
115 nxge_status_t
116 nxge_fzc_intr_init(p_nxge_t nxgep)
117 {
118 	nxge_status_t	status = NXGE_OK;
119 
120 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_fzc_intr_init"));
121 
122 	/* Configure the initial timer resolution */
123 	if ((status = nxge_fzc_intr_tmres_set(nxgep)) != NXGE_OK) {
124 		return (status);
125 	}
126 
127 	if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
128 		/*
129 		 * Set up the logical device group's logical devices that
130 		 * the group owns.
131 		 */
132 		if ((status = nxge_fzc_intr_ldg_num_set(nxgep)) != NXGE_OK)
133 			goto fzc_intr_init_exit;
134 
135 		/* Configure the system interrupt data */
136 		if ((status = nxge_fzc_intr_sid_set(nxgep)) != NXGE_OK)
137 			goto fzc_intr_init_exit;
138 	}
139 
140 fzc_intr_init_exit:
141 
142 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_init"));
143 
144 	return (status);
145 }
146 
147 nxge_status_t
148 nxge_fzc_intr_ldg_num_set(p_nxge_t nxgep)
149 {
150 	p_nxge_ldg_t	ldgp;
151 	p_nxge_ldv_t	ldvp;
152 	npi_handle_t	handle;
153 	int		i, j;
154 	npi_status_t	rs = NPI_SUCCESS;
155 
156 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_fzc_intr_ldg_num_set"));
157 
158 	if (nxgep->ldgvp == NULL) {
159 		return (NXGE_ERROR);
160 	}
161 
162 	ldgp = nxgep->ldgvp->ldgp;
163 	ldvp = nxgep->ldgvp->ldvp;
164 	if (ldgp == NULL || ldvp == NULL) {
165 		return (NXGE_ERROR);
166 	}
167 
168 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
169 
170 	for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) {
171 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
172 		    "==> nxge_fzc_intr_ldg_num_set "
173 		    "<== nxge_f(Neptune): # ldv %d "
174 		    "in group %d", ldgp->nldvs, ldgp->ldg));
175 
176 		for (j = 0; j < ldgp->nldvs; j++, ldvp++) {
177 			rs = npi_fzc_ldg_num_set(handle, ldvp->ldv,
178 			    ldvp->ldg_assigned);
179 			if (rs != NPI_SUCCESS) {
180 				NXGE_DEBUG_MSG((nxgep, INT_CTL,
181 				    "<== nxge_fzc_intr_ldg_num_set failed "
182 				    " rs 0x%x ldv %d ldg %d",
183 				    rs, ldvp->ldv, ldvp->ldg_assigned));
184 				return (NXGE_ERROR | rs);
185 			}
186 			NXGE_DEBUG_MSG((nxgep, INT_CTL,
187 			    "<== nxge_fzc_intr_ldg_num_set OK "
188 			    " ldv %d ldg %d",
189 			    ldvp->ldv, ldvp->ldg_assigned));
190 		}
191 	}
192 
193 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_ldg_num_set"));
194 
195 	return (NXGE_OK);
196 }
197 
198 nxge_status_t
199 nxge_fzc_intr_tmres_set(p_nxge_t nxgep)
200 {
201 	npi_handle_t	handle;
202 	npi_status_t	rs = NPI_SUCCESS;
203 
204 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_fzc_intr_tmrese_set"));
205 	if (nxgep->ldgvp == NULL) {
206 		return (NXGE_ERROR);
207 	}
208 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
209 	if ((rs = npi_fzc_ldg_timer_res_set(handle, nxgep->ldgvp->tmres))) {
210 		return (NXGE_ERROR | rs);
211 	}
212 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_tmrese_set"));
213 
214 	return (NXGE_OK);
215 }
216 
217 nxge_status_t
218 nxge_fzc_intr_sid_set(p_nxge_t nxgep)
219 {
220 	npi_handle_t	handle;
221 	p_nxge_ldg_t	ldgp;
222 	fzc_sid_t	sid;
223 	int		i;
224 	npi_status_t	rs = NPI_SUCCESS;
225 
226 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_fzc_intr_sid_set"));
227 	if (nxgep->ldgvp == NULL) {
228 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
229 		    "<== nxge_fzc_intr_sid_set: no ldg"));
230 		return (NXGE_ERROR);
231 	}
232 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
233 	ldgp = nxgep->ldgvp->ldgp;
234 	NXGE_DEBUG_MSG((nxgep, INT_CTL,
235 	    "==> nxge_fzc_intr_sid_set: #int %d", nxgep->ldgvp->ldg_intrs));
236 	for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) {
237 		sid.ldg = ldgp->ldg;
238 		sid.niu = B_FALSE;
239 		sid.func = ldgp->func;
240 		sid.vector = ldgp->vector;
241 		NXGE_DEBUG_MSG((nxgep, INT_CTL,
242 		    "==> nxge_fzc_intr_sid_set(%d): func %d group %d "
243 		    "vector %d",
244 		    i, sid.func, sid.ldg, sid.vector));
245 		rs = npi_fzc_sid_set(handle, sid);
246 		if (rs != NPI_SUCCESS) {
247 			NXGE_DEBUG_MSG((nxgep, INT_CTL,
248 			    "<== nxge_fzc_intr_sid_set:failed 0x%x",
249 			    rs));
250 			return (NXGE_ERROR | rs);
251 		}
252 	}
253 
254 	NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_sid_set"));
255 
256 	return (NXGE_OK);
257 
258 }
259 
260 /*
261  * nxge_init_fzc_rdc
262  *
263  *	Initialize all of a RDC's FZC_DMC registers.
264  *	This is executed by the service domain, on behalf of a
265  *	guest domain, who cannot access these registers.
266  *
267  * Arguments:
268  * 	nxgep
269  * 	channel		The channel to initialize.
270  *
271  * NPI_NXGE function calls:
272  *	nxge_init_fzc_rdc_pages()
273  *
274  * Context:
275  *	Service Domain
276  */
277 /*ARGSUSED*/
278 nxge_status_t
279 nxge_init_fzc_rdc(p_nxge_t nxgep, uint16_t channel)
280 {
281 	nxge_status_t	status = NXGE_OK;
282 
283 	dma_log_page_t	page1, page2;
284 	npi_handle_t	handle;
285 	rdc_red_para_t	red;
286 
287 	/*
288 	 * Initialize the RxDMA channel-specific FZC control
289 	 * registers.
290 	 */
291 
292 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_init_fzc_tdc"));
293 
294 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
295 
296 	/* Reset RXDMA channel */
297 	status = npi_rxdma_cfg_rdc_reset(handle, channel);
298 	if (status != NPI_SUCCESS) {
299 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
300 		    "==> nxge_init_fzc_rdc: npi_rxdma_cfg_rdc_reset(%d) "
301 		    "returned 0x%08x", channel, status));
302 		return (NXGE_ERROR | status);
303 	}
304 
305 	/*
306 	 * These values have been copied from
307 	 * nxge_txdma.c:nxge_map_txdma_channel_cfg_ring().
308 	 */
309 	page1.page_num = 0;
310 	page1.valid = 1;
311 	page1.func_num = nxgep->function_num;
312 	page1.mask = 0;
313 	page1.value = 0;
314 	page1.reloc = 0;
315 
316 	page2.page_num = 1;
317 	page2.valid = 1;
318 	page2.func_num = nxgep->function_num;
319 	page2.mask = 0;
320 	page2.value = 0;
321 	page2.reloc = 0;
322 
323 	if (nxgep->niu_type == N2_NIU) {
324 #if !defined(NIU_HV_WORKAROUND)
325 		status = NXGE_OK;
326 #else
327 		NXGE_DEBUG_MSG((nxgep, RX_CTL,
328 		    "==> nxge_init_fzc_rxdma_channel: N2_NIU - NEED to "
329 		    "set up logical pages"));
330 		/* Initialize the RXDMA logical pages */
331 		status = nxge_init_fzc_rdc_pages(nxgep, channel,
332 		    &page1, &page2);
333 		if (status != NXGE_OK) {
334 			return (status);
335 		}
336 #endif
337 	} else if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
338 		/* Initialize the RXDMA logical pages */
339 		status = nxge_init_fzc_rdc_pages(nxgep, channel,
340 		    &page1, &page2);
341 		if (status != NXGE_OK) {
342 			return (status);
343 		}
344 	} else {
345 		return (NXGE_ERROR);
346 	}
347 
348 	/*
349 	 * Configure RED parameters
350 	 */
351 	red.value = 0;
352 	red.bits.ldw.win = RXDMA_RED_WINDOW_DEFAULT;
353 	red.bits.ldw.thre =
354 	    (nxgep->nxge_port_rcr_size - RXDMA_RED_LESS_ENTRIES);
355 	red.bits.ldw.win_syn = RXDMA_RED_WINDOW_DEFAULT;
356 	red.bits.ldw.thre_sync =
357 	    (nxgep->nxge_port_rcr_size - RXDMA_RED_LESS_ENTRIES);
358 
359 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
360 	    "==> nxge_init_fzc_rxdma_channel_red(thre_sync %d(%x))",
361 	    red.bits.ldw.thre_sync,
362 	    red.bits.ldw.thre_sync));
363 
364 	status |= npi_rxdma_cfg_wred_param(handle, channel, &red);
365 
366 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_init_fzc_rdc"));
367 
368 	return (status);
369 }
370 
371 /*
372  * nxge_init_fzc_rxdma_channel
373  *
374  *	Initialize all per-channel FZC_DMC registers.
375  *
376  * Arguments:
377  * 	nxgep
378  * 	channel		The channel to start
379  *
380  * NPI_NXGE function calls:
381  *	nxge_init_hv_fzc_rxdma_channel_pages()
382  *	nxge_init_fzc_rxdma_channel_pages()
383  *	nxge_init_fzc_rxdma_channel_red()
384  *
385  * Context:
386  *	Service Domain
387  */
388 /*ARGSUSED*/
389 nxge_status_t
390 nxge_init_fzc_rxdma_channel(p_nxge_t nxgep, uint16_t channel)
391 {
392 	rx_rbr_ring_t		*rbr_ring;
393 	rx_rcr_ring_t		*rcr_ring;
394 
395 	nxge_status_t		status = NXGE_OK;
396 
397 	NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_init_fzc_rxdma_channel"));
398 
399 	rbr_ring = nxgep->rx_rbr_rings->rbr_rings[channel];
400 	rcr_ring = nxgep->rx_rcr_rings->rcr_rings[channel];
401 
402 	if (nxgep->niu_type == N2_NIU) {
403 #ifndef	NIU_HV_WORKAROUND
404 #if	defined(sun4v) && defined(NIU_LP_WORKAROUND)
405 		NXGE_DEBUG_MSG((nxgep, RX_CTL,
406 		    "==> nxge_init_fzc_rxdma_channel: N2_NIU - call HV "
407 		    "set up logical pages"));
408 		/* Initialize the RXDMA logical pages */
409 		status = nxge_init_hv_fzc_rxdma_channel_pages(nxgep, channel,
410 		    rbr_ring);
411 		if (status != NXGE_OK) {
412 			return (status);
413 		}
414 #endif
415 		status = NXGE_OK;
416 #else
417 		NXGE_DEBUG_MSG((nxgep, RX_CTL,
418 		    "==> nxge_init_fzc_rxdma_channel: N2_NIU - NEED to "
419 		    "set up logical pages"));
420 		/* Initialize the RXDMA logical pages */
421 		status = nxge_init_fzc_rxdma_channel_pages(nxgep, channel,
422 		    rbr_ring);
423 		if (status != NXGE_OK) {
424 			return (status);
425 		}
426 #endif
427 	} else if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
428 		/* Initialize the RXDMA logical pages */
429 		status = nxge_init_fzc_rxdma_channel_pages(nxgep,
430 		    channel, rbr_ring);
431 		if (status != NXGE_OK) {
432 			return (status);
433 		}
434 	} else {
435 		return (NXGE_ERROR);
436 	}
437 
438 	/* Configure RED parameters */
439 	status = nxge_init_fzc_rxdma_channel_red(nxgep, channel, rcr_ring);
440 
441 	NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_init_fzc_rxdma_channel"));
442 	return (status);
443 }
444 
445 /*
446  * nxge_init_fzc_rdc_pages
447  *
448  *	Configure a TDC's logical pages.
449  *
450  *	This function is executed by the service domain, on behalf of
451  *	a guest domain, to whom this RDC has been loaned.
452  *
453  * Arguments:
454  * 	nxgep
455  * 	channel		The channel to initialize.
456  * 	page0		Logical page 0 definition.
457  * 	page1		Logical page 1 definition.
458  *
459  * Notes:
460  *	I think that this function can be called from any
461  *	domain, but I need to check.
462  *
463  * NPI/NXGE function calls:
464  *	hv_niu_tx_logical_page_conf()
465  *	hv_niu_tx_logical_page_info()
466  *
467  * Context:
468  *	Any domain
469  */
470 nxge_status_t
471 nxge_init_fzc_rdc_pages(
472 	p_nxge_t nxgep,
473 	uint16_t channel,
474 	dma_log_page_t *page0,
475 	dma_log_page_t *page1)
476 {
477 	npi_handle_t handle;
478 	npi_status_t rs;
479 
480 	uint64_t page_handle;
481 
482 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
483 	    "==> nxge_init_fzc_txdma_channel_pages"));
484 
485 #ifndef	NIU_HV_WORKAROUND
486 	if (nxgep->niu_type == N2_NIU) {
487 		NXGE_DEBUG_MSG((nxgep, DMA_CTL,
488 		    "<== nxge_init_fzc_rdc_pages: "
489 		    "N2_NIU: no need to set rxdma logical pages"));
490 		return (NXGE_OK);
491 	}
492 #else
493 	if (nxgep->niu_type == N2_NIU) {
494 		NXGE_DEBUG_MSG((nxgep, DMA_CTL,
495 		    "<== nxge_init_fzc_rdc_pages: "
496 		    "N2_NIU: NEED to set rxdma logical pages"));
497 	}
498 #endif
499 
500 	/*
501 	 * Initialize logical page 1.
502 	 */
503 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
504 	if ((rs = npi_rxdma_cfg_logical_page(handle, channel, page0))
505 	    != NPI_SUCCESS)
506 		return (NXGE_ERROR | rs);
507 
508 	/*
509 	 * Initialize logical page 2.
510 	 */
511 	if ((rs = npi_rxdma_cfg_logical_page(handle, channel, page1))
512 	    != NPI_SUCCESS)
513 		return (NXGE_ERROR | rs);
514 
515 	/*
516 	 * Initialize the page handle.
517 	 * (In the current driver, this is always set to 0.)
518 	 */
519 	page_handle = 0;
520 	rs = npi_rxdma_cfg_logical_page_handle(handle, channel, page_handle);
521 	if (rs == NPI_SUCCESS) {
522 		return (NXGE_OK);
523 	} else {
524 		return (NXGE_ERROR | rs);
525 	}
526 }
527 
528 /*ARGSUSED*/
529 nxge_status_t
530 nxge_init_fzc_rxdma_channel_pages(p_nxge_t nxgep,
531 		uint16_t channel, p_rx_rbr_ring_t rbrp)
532 {
533 	npi_handle_t		handle;
534 	dma_log_page_t		cfg;
535 	npi_status_t		rs = NPI_SUCCESS;
536 
537 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
538 	    "==> nxge_init_fzc_rxdma_channel_pages"));
539 
540 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
541 	/*
542 	 * Initialize logical page 1.
543 	 */
544 	cfg.func_num = nxgep->function_num;
545 	cfg.page_num = 0;
546 	cfg.valid = rbrp->page_valid.bits.ldw.page0;
547 	cfg.value = rbrp->page_value_1.value;
548 	cfg.mask = rbrp->page_mask_1.value;
549 	cfg.reloc = rbrp->page_reloc_1.value;
550 	rs = npi_rxdma_cfg_logical_page(handle, channel,
551 	    (p_dma_log_page_t)&cfg);
552 	if (rs != NPI_SUCCESS) {
553 		return (NXGE_ERROR | rs);
554 	}
555 
556 	/*
557 	 * Initialize logical page 2.
558 	 */
559 	cfg.page_num = 1;
560 	cfg.valid = rbrp->page_valid.bits.ldw.page1;
561 	cfg.value = rbrp->page_value_2.value;
562 	cfg.mask = rbrp->page_mask_2.value;
563 	cfg.reloc = rbrp->page_reloc_2.value;
564 
565 	rs = npi_rxdma_cfg_logical_page(handle, channel, &cfg);
566 	if (rs != NPI_SUCCESS) {
567 		return (NXGE_ERROR | rs);
568 	}
569 
570 	/* Initialize the page handle */
571 	rs = npi_rxdma_cfg_logical_page_handle(handle, channel,
572 	    rbrp->page_hdl.bits.ldw.handle);
573 
574 	if (rs != NPI_SUCCESS) {
575 		return (NXGE_ERROR | rs);
576 	}
577 
578 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
579 	    "<== nxge_init_fzc_rxdma_channel_pages"));
580 
581 	return (NXGE_OK);
582 }
583 
584 /*ARGSUSED*/
585 nxge_status_t
586 nxge_init_fzc_rxdma_channel_red(p_nxge_t nxgep,
587 	uint16_t channel, p_rx_rcr_ring_t rcr_p)
588 {
589 	npi_handle_t		handle;
590 	rdc_red_para_t		red;
591 	npi_status_t		rs = NPI_SUCCESS;
592 
593 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_init_fzc_rxdma_channel_red"));
594 
595 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
596 	red.value = 0;
597 	red.bits.ldw.win = RXDMA_RED_WINDOW_DEFAULT;
598 	red.bits.ldw.thre = (rcr_p->comp_size - RXDMA_RED_LESS_ENTRIES);
599 	red.bits.ldw.win_syn = RXDMA_RED_WINDOW_DEFAULT;
600 	red.bits.ldw.thre_sync = (rcr_p->comp_size - RXDMA_RED_LESS_ENTRIES);
601 
602 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
603 	    "==> nxge_init_fzc_rxdma_channel_red(thre_sync %d(%x))",
604 	    red.bits.ldw.thre_sync,
605 	    red.bits.ldw.thre_sync));
606 
607 	rs = npi_rxdma_cfg_wred_param(handle, channel, &red);
608 	if (rs != NPI_SUCCESS) {
609 		return (NXGE_ERROR | rs);
610 	}
611 
612 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
613 	    "<== nxge_init_fzc_rxdma_channel_red"));
614 
615 	return (NXGE_OK);
616 }
617 
618 /*
619  * nxge_init_fzc_tdc
620  *
621  *	Initialize all of a TDC's FZC_DMC registers.
622  *	This is executed by the service domain, on behalf of a
623  *	guest domain, who cannot access these registers.
624  *
625  * Arguments:
626  * 	nxgep
627  * 	channel		The channel to initialize.
628  *
629  * NPI_NXGE function calls:
630  *	nxge_init_fzc_tdc_pages()
631  *	npi_txc_dma_max_burst_set()
632  *
633  * Registers accessed:
634  *	TXC_DMA_MAX_BURST
635  *
636  * Context:
637  *	Service Domain
638  */
639 /*ARGSUSED*/
640 nxge_status_t
641 nxge_init_fzc_tdc(p_nxge_t nxgep, uint16_t channel)
642 {
643 	nxge_status_t	status = NXGE_OK;
644 
645 	dma_log_page_t	page1, page2;
646 	npi_handle_t	handle;
647 
648 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_init_fzc_tdc"));
649 
650 	/*
651 	 * These values have been copied from
652 	 * nxge_txdma.c:nxge_map_txdma_channel_cfg_ring().
653 	 */
654 	page1.page_num = 0;
655 	page1.valid = 1;
656 	page1.func_num = nxgep->function_num;
657 	page1.mask = 0;
658 	page1.value = 0;
659 	page1.reloc = 0;
660 
661 	page1.page_num = 1;
662 	page1.valid = 1;
663 	page1.func_num = nxgep->function_num;
664 	page1.mask = 0;
665 	page1.value = 0;
666 	page1.reloc = 0;
667 
668 #ifdef	NIU_HV_WORKAROUND
669 	if (nxgep->niu_type == N2_NIU) {
670 		NXGE_DEBUG_MSG((nxgep, DMA_CTL,
671 		    "==> nxge_init_fzc_txdma_channel "
672 		    "N2_NIU: NEED to set up txdma logical pages"));
673 		/* Initialize the TXDMA logical pages */
674 		(void) nxge_init_fzc_tdc_pages(nxgep, channel,
675 		    &page1, &page2);
676 	}
677 #endif
678 	if (nxgep->niu_type != N2_NIU) {
679 		if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
680 			/* Initialize the TXDMA logical pages */
681 			(void) nxge_init_fzc_tdc_pages(nxgep, channel,
682 			    &page1, &page2);
683 		} else
684 			return (NXGE_ERROR);
685 	}
686 
687 	/*
688 	 * Configure the TXC DMA Max Burst value.
689 	 *
690 	 * PRM.13.5
691 	 *
692 	 * TXC DMA Max Burst. TXC_DMA_MAX (FZC_TXC + 0000016)
693 	 * 19:0		dma_max_burst		RW
694 	 * Max burst value associated with DMA. Used by DRR engine
695 	 * for computing when DMA has gone into deficit.
696 	 */
697 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
698 	(void) npi_txc_dma_max_burst_set(
699 	    handle, channel, TXC_DMA_MAX_BURST_DEFAULT);
700 
701 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_init_fzc_tdc"));
702 
703 	return (status);
704 }
705 
706 /*ARGSUSED*/
707 nxge_status_t
708 nxge_init_fzc_txdma_channel(p_nxge_t nxgep, uint16_t channel,
709 	p_tx_ring_t tx_ring_p, p_tx_mbox_t mbox_p)
710 {
711 	nxge_status_t	status = NXGE_OK;
712 
713 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
714 	    "==> nxge_init_fzc_txdma_channel"));
715 
716 	if (nxgep->niu_type == N2_NIU) {
717 #ifndef	NIU_HV_WORKAROUND
718 #if	defined(sun4v) && defined(NIU_LP_WORKAROUND)
719 		NXGE_DEBUG_MSG((nxgep, DMA_CTL,
720 		    "==> nxge_init_fzc_txdma_channel "
721 		    "N2_NIU: call HV to set up txdma logical pages"));
722 		status = nxge_init_hv_fzc_txdma_channel_pages(nxgep, channel,
723 		    tx_ring_p);
724 		if (status != NXGE_OK) {
725 			return (status);
726 		}
727 #endif
728 		status = NXGE_OK;
729 #else
730 		NXGE_DEBUG_MSG((nxgep, DMA_CTL,
731 		    "==> nxge_init_fzc_txdma_channel "
732 		    "N2_NIU: NEED to set up txdma logical pages"));
733 		/* Initialize the TXDMA logical pages */
734 		(void) nxge_init_fzc_txdma_channel_pages(nxgep, channel,
735 		    tx_ring_p);
736 #endif
737 	} else if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
738 		/* Initialize the TXDMA logical pages */
739 		(void) nxge_init_fzc_txdma_channel_pages(nxgep,
740 		    channel, tx_ring_p);
741 	} else {
742 		return (NXGE_ERROR);
743 	}
744 
745 	/*
746 	 * Configure Transmit DRR Weight parameters
747 	 * (It actually programs the TXC max burst register).
748 	 */
749 	(void) nxge_init_fzc_txdma_channel_drr(nxgep, channel, tx_ring_p);
750 
751 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
752 	    "<== nxge_init_fzc_txdma_channel"));
753 	return (status);
754 }
755 
756 
757 nxge_status_t
758 nxge_init_fzc_rx_common(p_nxge_t nxgep)
759 {
760 	npi_handle_t	handle;
761 	npi_status_t	rs = NPI_SUCCESS;
762 	nxge_status_t	status = NXGE_OK;
763 	clock_t		lbolt;
764 	int		table;
765 
766 	nxge_hw_pt_cfg_t *hardware;
767 
768 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_init_fzc_rx_common"));
769 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
770 	if (!handle.regp) {
771 		NXGE_DEBUG_MSG((nxgep, DMA_CTL,
772 		    "==> nxge_init_fzc_rx_common null ptr"));
773 		return (NXGE_ERROR);
774 	}
775 
776 	/*
777 	 * Configure the rxdma clock divider
778 	 * This is the granularity counter based on
779 	 * the hardware system clock (i.e. 300 Mhz) and
780 	 * it is running around 3 nanoseconds.
781 	 * So, set the clock divider counter to 1000 to get
782 	 * microsecond granularity.
783 	 * For example, for a 3 microsecond timeout, the timeout
784 	 * will be set to 1.
785 	 */
786 	rs = npi_rxdma_cfg_clock_div_set(handle, RXDMA_CK_DIV_DEFAULT);
787 	if (rs != NPI_SUCCESS)
788 		return (NXGE_ERROR | rs);
789 
790 #if defined(__i386)
791 	rs = npi_rxdma_cfg_32bitmode_enable(handle);
792 	if (rs != NPI_SUCCESS)
793 		return (NXGE_ERROR | rs);
794 	rs = npi_txdma_mode32_set(handle, B_TRUE);
795 	if (rs != NPI_SUCCESS)
796 		return (NXGE_ERROR | rs);
797 #endif
798 
799 	/*
800 	 * Enable WRED and program an initial value.
801 	 * Use time to set the initial random number.
802 	 */
803 	(void) drv_getparm(LBOLT, &lbolt);
804 	rs = npi_rxdma_cfg_red_rand_init(handle, (uint16_t)lbolt);
805 	if (rs != NPI_SUCCESS)
806 		return (NXGE_ERROR | rs);
807 
808 	hardware = &nxgep->pt_config.hw_config;
809 	for (table = 0; table < NXGE_MAX_RDC_GRPS; table++) {
810 		/* Does this table belong to <nxgep>? */
811 		if (hardware->grpids[table] == (nxgep->function_num + 256))
812 			status = nxge_init_fzc_rdc_tbl(nxgep, table);
813 	}
814 
815 	/* Ethernet Timeout Counter (?) */
816 
817 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
818 	    "<== nxge_init_fzc_rx_common:status 0x%08x", status));
819 
820 	return (status);
821 }
822 
823 nxge_status_t
824 nxge_init_fzc_rdc_tbl(p_nxge_t nxge, int rdc_tbl)
825 {
826 	nxge_hio_data_t *nhd = (nxge_hio_data_t *)nxge->nxge_hw_p->hio;
827 	nx_rdc_tbl_t	*table;
828 	nxge_rdc_grp_t	*group;
829 	npi_handle_t	handle;
830 
831 	npi_status_t	rs = NPI_SUCCESS;
832 	nxge_status_t	status = NXGE_OK;
833 
834 	NXGE_DEBUG_MSG((nxge, DMA_CTL, "==> nxge_init_fzc_rdc_tbl(%d)", table));
835 
836 	group = &nxge->pt_config.rdc_grps[rdc_tbl];
837 
838 	/* This RDC table must have been previously bound to <nxge>. */
839 	MUTEX_ENTER(&nhd->lock);
840 	table = &nhd->rdc_tbl[rdc_tbl];
841 	if (table->nxge != (uintptr_t)nxge) {
842 		MUTEX_EXIT(&nhd->lock);
843 		NXGE_ERROR_MSG((nxge, DMA_CTL,
844 		    "nxge_init_fzc_rdc_tbl(%d): not owner", table));
845 		return (NXGE_ERROR);
846 	} else {
847 		table->map = group->map;
848 	}
849 	MUTEX_EXIT(&nhd->lock);
850 
851 	handle = NXGE_DEV_NPI_HANDLE(nxge);
852 
853 	rs = npi_rxdma_rdc_table_config(handle, rdc_tbl,
854 	    group->map, group->max_rdcs);
855 
856 	if (rs != NPI_SUCCESS) {
857 		status = NXGE_ERROR | rs;
858 	}
859 
860 	NXGE_DEBUG_MSG((nxge, DMA_CTL, "<== nxge_init_fzc_rdc_tbl(%d)", table));
861 	return (status);
862 }
863 
864 static
865 int
866 rdc_tbl_bind(p_nxge_t nxge, int rdc_tbl)
867 {
868 	nxge_hio_data_t *nhd = (nxge_hio_data_t *)nxge->nxge_hw_p->hio;
869 	nx_rdc_tbl_t *table;
870 	int i;
871 
872 	NXGE_DEBUG_MSG((nxge, DMA_CTL, "==> nxge_fzc_rdc_tbl_bind"));
873 
874 	MUTEX_ENTER(&nhd->lock);
875 	/* is the caller asking for a particular table? */
876 	if (rdc_tbl >= 0 && rdc_tbl < NXGE_MAX_RDC_GROUPS) {
877 		table = &nhd->rdc_tbl[rdc_tbl];
878 		if (table->nxge == 0) {
879 			table->nxge = (uintptr_t)nxge; /* It is now bound. */
880 			NXGE_DEBUG_MSG((nxge, DMA_CTL,
881 			    "<== nxge_fzc_rdc_tbl_bind(%d)", rdc_tbl));
882 			MUTEX_EXIT(&nhd->lock);
883 			return (rdc_tbl);
884 		}
885 	} else {	/* The caller will take any old RDC table. */
886 		for (i = 0; i < NXGE_MAX_RDC_GROUPS; i++) {
887 			nx_rdc_tbl_t *table = &nhd->rdc_tbl[i];
888 			if (table->nxge == 0) {
889 				table->nxge = (uintptr_t)nxge;
890 				/* It is now bound. */
891 				MUTEX_EXIT(&nhd->lock);
892 				NXGE_DEBUG_MSG((nxge, DMA_CTL,
893 				    "<== nxge_fzc_rdc_tbl_bind: %d", i));
894 				return (i);
895 			}
896 		}
897 	}
898 	MUTEX_EXIT(&nhd->lock);
899 
900 	NXGE_DEBUG_MSG((nxge, HIO_CTL, "<== nxge_fzc_rdc_tbl_bind"));
901 
902 	return (-EBUSY);	/* RDC tables are bound. */
903 }
904 
905 int
906 nxge_fzc_rdc_tbl_bind(
907 	nxge_t *nxge,
908 	int grp_index,
909 	int acceptNoSubstitutes)
910 {
911 	nxge_hw_pt_cfg_t *hardware;
912 	int index;
913 
914 	hardware = &nxge->pt_config.hw_config;
915 
916 	if ((index = rdc_tbl_bind(nxge, grp_index)) < 0) {
917 		if (acceptNoSubstitutes)
918 			return (index);
919 		index = rdc_tbl_bind(nxge, grp_index);
920 		if (index < 0) {
921 			NXGE_ERROR_MSG((nxge, OBP_CTL,
922 			    "nxge_fzc_rdc_tbl_init: "
923 			    "there are no free RDC tables!"));
924 			return (index);
925 		}
926 	}
927 
928 	hardware->grpids[index] = nxge->function_num + 256;
929 
930 	return (index);
931 }
932 
933 int
934 nxge_fzc_rdc_tbl_unbind(p_nxge_t nxge, int rdc_tbl)
935 {
936 	nxge_hio_data_t *nhd = (nxge_hio_data_t *)nxge->nxge_hw_p->hio;
937 	nx_rdc_tbl_t *table;
938 
939 	NXGE_DEBUG_MSG((nxge, DMA_CTL, "==> nxge_fzc_rdc_tbl_unbind(%d)",
940 	    rdc_tbl));
941 
942 	table = &nhd->rdc_tbl[rdc_tbl];
943 	if (table->nxge != (uintptr_t)nxge) {
944 		NXGE_ERROR_MSG((nxge, DMA_CTL,
945 		    "nxge_fzc_rdc_tbl_unbind(%d): func%d not owner",
946 		    nxge->function_num, rdc_tbl));
947 		return (EINVAL);
948 	} else {
949 		bzero(table, sizeof (*table));
950 	}
951 
952 	NXGE_DEBUG_MSG((nxge, DMA_CTL, "<== nxge_fzc_rdc_tbl_unbind(%d)",
953 	    rdc_tbl));
954 
955 	return (0);
956 }
957 
958 nxge_status_t
959 nxge_init_fzc_rxdma_port(p_nxge_t nxgep)
960 {
961 	npi_handle_t		handle;
962 	p_nxge_dma_pt_cfg_t	p_all_cfgp;
963 	p_nxge_hw_pt_cfg_t	p_cfgp;
964 	hostinfo_t 		hostinfo;
965 	int			i;
966 	npi_status_t		rs = NPI_SUCCESS;
967 	p_nxge_class_pt_cfg_t 	p_class_cfgp;
968 	NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_init_fzc_rxdma_port"));
969 
970 	p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
971 	p_cfgp = (p_nxge_hw_pt_cfg_t)&p_all_cfgp->hw_config;
972 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
973 	/*
974 	 * Initialize the port scheduler DRR weight.
975 	 * npi_rxdma_cfg_port_ddr_weight();
976 	 */
977 
978 	if ((nxgep->mac.portmode == PORT_1G_COPPER) ||
979 	    (nxgep->mac.portmode == PORT_1G_FIBER) ||
980 	    (nxgep->mac.portmode == PORT_1G_TN1010) ||
981 	    (nxgep->mac.portmode == PORT_1G_SERDES)) {
982 		rs = npi_rxdma_cfg_port_ddr_weight(handle,
983 		    nxgep->function_num, NXGE_RX_DRR_WT_1G);
984 		if (rs != NPI_SUCCESS) {
985 			return (NXGE_ERROR | rs);
986 		}
987 	}
988 
989 	/* Program the default RDC of a port */
990 	rs = npi_rxdma_cfg_default_port_rdc(handle, nxgep->function_num,
991 	    p_cfgp->def_rdc);
992 	if (rs != NPI_SUCCESS) {
993 		return (NXGE_ERROR | rs);
994 	}
995 
996 	/*
997 	 * Configure the MAC host info table with RDC tables
998 	 */
999 	hostinfo.value = 0;
1000 	p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
1001 	for (i = 0; i < p_cfgp->max_macs; i++) {
1002 		hostinfo.bits.w0.rdc_tbl_num = p_cfgp->def_mac_rxdma_grpid;
1003 		hostinfo.bits.w0.mac_pref = p_cfgp->mac_pref;
1004 		if (p_class_cfgp->mac_host_info[i].flag) {
1005 			hostinfo.bits.w0.rdc_tbl_num =
1006 			    p_class_cfgp->mac_host_info[i].rdctbl;
1007 			hostinfo.bits.w0.mac_pref =
1008 			    p_class_cfgp->mac_host_info[i].mpr_npr;
1009 		}
1010 
1011 		rs = npi_mac_hostinfo_entry(handle, OP_SET,
1012 		    nxgep->function_num, i, &hostinfo);
1013 		if (rs != NPI_SUCCESS)
1014 			return (NXGE_ERROR | rs);
1015 	}
1016 
1017 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1018 	    "<== nxge_init_fzc_rxdma_port rs 0x%08x", rs));
1019 
1020 	return (NXGE_OK);
1021 
1022 }
1023 
1024 nxge_status_t
1025 nxge_fzc_dmc_def_port_rdc(p_nxge_t nxgep, uint8_t port, uint16_t rdc)
1026 {
1027 	npi_status_t rs = NPI_SUCCESS;
1028 	rs = npi_rxdma_cfg_default_port_rdc(nxgep->npi_reg_handle,
1029 	    port, rdc);
1030 	if (rs & NPI_FAILURE)
1031 		return (NXGE_ERROR | rs);
1032 	return (NXGE_OK);
1033 }
1034 
1035 /*
1036  * nxge_init_fzc_tdc_pages
1037  *
1038  *	Configure a TDC's logical pages.
1039  *
1040  *	This function is executed by the service domain, on behalf of
1041  *	a guest domain, to whom this TDC has been loaned.
1042  *
1043  * Arguments:
1044  * 	nxgep
1045  * 	channel		The channel to initialize.
1046  * 	page0		Logical page 0 definition.
1047  * 	page1		Logical page 1 definition.
1048  *
1049  * Notes:
1050  *	I think that this function can be called from any
1051  *	domain, but I need to check.
1052  *
1053  * NPI/NXGE function calls:
1054  *	hv_niu_tx_logical_page_conf()
1055  *	hv_niu_tx_logical_page_info()
1056  *
1057  * Context:
1058  *	Any domain
1059  */
1060 nxge_status_t
1061 nxge_init_fzc_tdc_pages(
1062 	p_nxge_t nxgep,
1063 	uint16_t channel,
1064 	dma_log_page_t *page0,
1065 	dma_log_page_t *page1)
1066 {
1067 	npi_handle_t handle;
1068 	npi_status_t rs;
1069 
1070 	log_page_hdl_t page_handle;
1071 
1072 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1073 	    "==> nxge_init_fzc_txdma_channel_pages"));
1074 
1075 #ifndef	NIU_HV_WORKAROUND
1076 	if (nxgep->niu_type == N2_NIU) {
1077 		NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1078 		    "<== nxge_init_fzc_tdc_pages: "
1079 		    "N2_NIU: no need to set txdma logical pages"));
1080 		return (NXGE_OK);
1081 	}
1082 #else
1083 	if (nxgep->niu_type == N2_NIU) {
1084 		NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1085 		    "<== nxge_init_fzc_tdc_pages: "
1086 		    "N2_NIU: NEED to set txdma logical pages"));
1087 	}
1088 #endif
1089 
1090 	/*
1091 	 * Initialize logical page 1.
1092 	 */
1093 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
1094 	if ((rs = npi_txdma_log_page_set(handle, channel, page0))
1095 	    != NPI_SUCCESS)
1096 		return (NXGE_ERROR | rs);
1097 
1098 	/*
1099 	 * Initialize logical page 2.
1100 	 */
1101 	if ((rs = npi_txdma_log_page_set(handle, channel, page1))
1102 	    != NPI_SUCCESS)
1103 		return (NXGE_ERROR | rs);
1104 
1105 	/*
1106 	 * Initialize the page handle.
1107 	 * (In the current driver, this is always set to 0.)
1108 	 */
1109 	page_handle.value = 0;
1110 	rs = npi_txdma_log_page_handle_set(handle, channel, &page_handle);
1111 	if (rs == NPI_SUCCESS) {
1112 		return (NXGE_OK);
1113 	} else {
1114 		return (NXGE_ERROR | rs);
1115 	}
1116 }
1117 
1118 nxge_status_t
1119 nxge_init_fzc_txdma_channel_pages(p_nxge_t nxgep, uint16_t channel,
1120 	p_tx_ring_t tx_ring_p)
1121 {
1122 	npi_handle_t		handle;
1123 	dma_log_page_t		cfg;
1124 	npi_status_t		rs = NPI_SUCCESS;
1125 
1126 	NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1127 	    "==> nxge_init_fzc_txdma_channel_pages"));
1128 
1129 #ifndef	NIU_HV_WORKAROUND
1130 	if (nxgep->niu_type == N2_NIU) {
1131 		NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1132 		    "<== nxge_init_fzc_txdma_channel_pages: "
1133 		    "N2_NIU: no need to set txdma logical pages"));
1134 		return (NXGE_OK);
1135 	}
1136 #else
1137 	if (nxgep->niu_type == N2_NIU) {
1138 		NXGE_DEBUG_MSG((nxgep, DMA_CTL,
1139 		    "<== nxge_init_fzc_txdma_channel_pages: "
1140 		    "N2_NIU: NEED to set txdma logical pages"));
1141 	}
1142 #endif
1143 
1144 	/*
1145 	 * Initialize logical page 1.
1146 	 */
1147 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
1148 	cfg.func_num = nxgep->function_num;
1149 	cfg.page_num = 0;
1150 	cfg.valid = tx_ring_p->page_valid.bits.ldw.page0;
1151 	cfg.value = tx_ring_p->page_value_1.value;
1152 	cfg.mask = tx_ring_p->page_mask_1.value;
1153 	cfg.reloc = tx_ring_p->page_reloc_1.value;
1154 
1155 	rs = npi_txdma_log_page_set(handle, channel,
1156 	    (p_dma_log_page_t)&cfg);
1157 	if (rs != NPI_SUCCESS) {
1158 		return (NXGE_ERROR | rs);
1159 	}
1160 
1161 	/*
1162 	 * Initialize logical page 2.
1163 	 */
1164 	cfg.page_num = 1;
1165 	cfg.valid = tx_ring_p->page_valid.bits.ldw.page1;
1166 	cfg.value = tx_ring_p->page_value_2.value;
1167 	cfg.mask = tx_ring_p->page_mask_2.value;
1168 	cfg.reloc = tx_ring_p->page_reloc_2.value;
1169 
1170 	rs = npi_txdma_log_page_set(handle, channel, &cfg);
1171 	if (rs != NPI_SUCCESS) {
1172 		return (NXGE_ERROR | rs);
1173 	}
1174 
1175 	/* Initialize the page handle */
1176 	rs = npi_txdma_log_page_handle_set(handle, channel,
1177 	    &tx_ring_p->page_hdl);
1178 
1179 	if (rs == NPI_SUCCESS) {
1180 		return (NXGE_OK);
1181 	} else {
1182 		return (NXGE_ERROR | rs);
1183 	}
1184 }
1185 
1186 
1187 nxge_status_t
1188 nxge_init_fzc_txdma_channel_drr(p_nxge_t nxgep, uint16_t channel,
1189 	p_tx_ring_t tx_ring_p)
1190 {
1191 	npi_status_t	rs = NPI_SUCCESS;
1192 	npi_handle_t	handle;
1193 
1194 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
1195 	rs = npi_txc_dma_max_burst_set(handle, channel,
1196 	    tx_ring_p->max_burst.value);
1197 	if (rs == NPI_SUCCESS) {
1198 		return (NXGE_OK);
1199 	} else {
1200 		return (NXGE_ERROR | rs);
1201 	}
1202 }
1203 
1204 nxge_status_t
1205 nxge_fzc_sys_err_mask_set(p_nxge_t nxgep, uint64_t mask)
1206 {
1207 	npi_status_t	rs = NPI_SUCCESS;
1208 	npi_handle_t	handle;
1209 
1210 	handle = NXGE_DEV_NPI_HANDLE(nxgep);
1211 	rs = npi_fzc_sys_err_mask_set(handle, mask);
1212 	if (rs == NPI_SUCCESS) {
1213 		return (NXGE_OK);
1214 	} else {
1215 		return (NXGE_ERROR | rs);
1216 	}
1217 }
1218 
1219 /*
1220  * nxge_init_hv_fzc_txdma_channel_pages
1221  *
1222  *	Configure a TDC's logical pages.
1223  *
1224  * Arguments:
1225  * 	nxgep
1226  * 	channel		The channel to initialize.
1227  * 	tx_ring_p	The transmit ring.
1228  *
1229  * Notes:
1230  *	I think that this function can be called from any
1231  *	domain, but I need to check.
1232  *
1233  * NPI/NXGE function calls:
1234  *	hv_niu_tx_logical_page_conf()
1235  *	hv_niu_tx_logical_page_info()
1236  *
1237  * Context:
1238  *	Any domain
1239  */
1240 #if defined(sun4v) && defined(NIU_LP_WORKAROUND)
1241 nxge_status_t
1242 nxge_init_hv_fzc_txdma_channel_pages(p_nxge_t nxgep, uint16_t channel,
1243 	p_tx_ring_t tx_ring_p)
1244 {
1245 	int			err;
1246 	uint64_t		hverr;
1247 #ifdef	DEBUG
1248 	uint64_t		ra, size;
1249 #endif
1250 
1251 	NXGE_DEBUG_MSG((nxgep, TX_CTL,
1252 	    "==> nxge_init_hv_fzc_txdma_channel_pages"));
1253 
1254 	if (tx_ring_p->hv_set) {
1255 		return (NXGE_OK);
1256 	}
1257 
1258 	/*
1259 	 * Initialize logical page 1 for data buffers.
1260 	 */
1261 	hverr = hv_niu_tx_logical_page_conf((uint64_t)channel,
1262 	    (uint64_t)0,
1263 	    tx_ring_p->hv_tx_buf_base_ioaddr_pp,
1264 	    tx_ring_p->hv_tx_buf_ioaddr_size);
1265 
1266 	err = (nxge_status_t)nxge_herr2kerr(hverr);
1267 	if (err != 0) {
1268 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1269 		    "<== nxge_init_hv_fzc_txdma_channel_pages: channel %d "
1270 		    "error status 0x%x "
1271 		    "(page 0 data buf) hverr 0x%llx "
1272 		    "ioaddr_pp $%p "
1273 		    "size 0x%llx ",
1274 		    channel,
1275 		    err,
1276 		    hverr,
1277 		    tx_ring_p->hv_tx_buf_base_ioaddr_pp,
1278 		    tx_ring_p->hv_tx_buf_ioaddr_size));
1279 		return (NXGE_ERROR | err);
1280 	}
1281 
1282 #ifdef	DEBUG
1283 	ra = size = 0;
1284 	hverr = hv_niu_tx_logical_page_info((uint64_t)channel,
1285 	    (uint64_t)0,
1286 	    &ra,
1287 	    &size);
1288 
1289 	NXGE_DEBUG_MSG((nxgep, TX_CTL,
1290 	    "==> nxge_init_hv_fzc_txdma_channel_pages: channel %d "
1291 	    "ok status 0x%x "
1292 	    "(page 0 data buf) hverr 0x%llx "
1293 	    "set ioaddr_pp $%p "
1294 	    "set size 0x%llx "
1295 	    "get ra ioaddr_pp $%p "
1296 	    "get size 0x%llx ",
1297 	    channel,
1298 	    err,
1299 	    hverr,
1300 	    tx_ring_p->hv_tx_buf_base_ioaddr_pp,
1301 	    tx_ring_p->hv_tx_buf_ioaddr_size,
1302 	    ra,
1303 	    size));
1304 #endif
1305 
1306 	NXGE_DEBUG_MSG((nxgep, TX_CTL,
1307 	    "==> nxge_init_hv_fzc_txdma_channel_pages: channel %d "
1308 	    "(page 0 data buf) hverr 0x%llx "
1309 	    "ioaddr_pp $%p "
1310 	    "size 0x%llx ",
1311 	    channel,
1312 	    hverr,
1313 	    tx_ring_p->hv_tx_buf_base_ioaddr_pp,
1314 	    tx_ring_p->hv_tx_buf_ioaddr_size));
1315 
1316 	/*
1317 	 * Initialize logical page 2 for control buffers.
1318 	 */
1319 	hverr = hv_niu_tx_logical_page_conf((uint64_t)channel,
1320 	    (uint64_t)1,
1321 	    tx_ring_p->hv_tx_cntl_base_ioaddr_pp,
1322 	    tx_ring_p->hv_tx_cntl_ioaddr_size);
1323 
1324 	err = (nxge_status_t)nxge_herr2kerr(hverr);
1325 
1326 	NXGE_DEBUG_MSG((nxgep, TX_CTL,
1327 	    "==> nxge_init_hv_fzc_txdma_channel_pages: channel %d"
1328 	    "ok status 0x%x "
1329 	    "(page 1 cntl buf) hverr 0x%llx "
1330 	    "ioaddr_pp $%p "
1331 	    "size 0x%llx ",
1332 	    channel,
1333 	    err,
1334 	    hverr,
1335 	    tx_ring_p->hv_tx_cntl_base_ioaddr_pp,
1336 	    tx_ring_p->hv_tx_cntl_ioaddr_size));
1337 
1338 	if (err != 0) {
1339 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1340 		    "<== nxge_init_hv_fzc_txdma_channel_pages: channel %d"
1341 		    "error status 0x%x "
1342 		    "(page 1 cntl buf) hverr 0x%llx "
1343 		    "ioaddr_pp $%p "
1344 		    "size 0x%llx ",
1345 		    channel,
1346 		    err,
1347 		    hverr,
1348 		    tx_ring_p->hv_tx_cntl_base_ioaddr_pp,
1349 		    tx_ring_p->hv_tx_cntl_ioaddr_size));
1350 		return (NXGE_ERROR | err);
1351 	}
1352 
1353 #ifdef	DEBUG
1354 	ra = size = 0;
1355 	hverr = hv_niu_tx_logical_page_info((uint64_t)channel,
1356 	    (uint64_t)1,
1357 	    &ra,
1358 	    &size);
1359 
1360 	NXGE_DEBUG_MSG((nxgep, TX_CTL,
1361 	    "==> nxge_init_hv_fzc_txdma_channel_pages: channel %d "
1362 	    "(page 1 cntl buf) hverr 0x%llx "
1363 	    "set ioaddr_pp $%p "
1364 	    "set size 0x%llx "
1365 	    "get ra ioaddr_pp $%p "
1366 	    "get size 0x%llx ",
1367 	    channel,
1368 	    hverr,
1369 	    tx_ring_p->hv_tx_cntl_base_ioaddr_pp,
1370 	    tx_ring_p->hv_tx_cntl_ioaddr_size,
1371 	    ra,
1372 	    size));
1373 #endif
1374 
1375 	tx_ring_p->hv_set = B_TRUE;
1376 
1377 	NXGE_DEBUG_MSG((nxgep, TX_CTL,
1378 	    "<== nxge_init_hv_fzc_txdma_channel_pages"));
1379 
1380 	return (NXGE_OK);
1381 }
1382 
1383 /*ARGSUSED*/
1384 nxge_status_t
1385 nxge_init_hv_fzc_rxdma_channel_pages(p_nxge_t nxgep,
1386 		uint16_t channel, p_rx_rbr_ring_t rbrp)
1387 {
1388 	int			err;
1389 	uint64_t		hverr;
1390 #ifdef	DEBUG
1391 	uint64_t		ra, size;
1392 #endif
1393 
1394 	NXGE_DEBUG_MSG((nxgep, RX_CTL,
1395 	    "==> nxge_init_hv_fzc_rxdma_channel_pages"));
1396 
1397 	if (rbrp->hv_set) {
1398 		return (NXGE_OK);
1399 	}
1400 
1401 	/* Initialize data buffers for page 0 */
1402 	hverr = hv_niu_rx_logical_page_conf((uint64_t)channel,
1403 	    (uint64_t)0,
1404 	    rbrp->hv_rx_buf_base_ioaddr_pp,
1405 	    rbrp->hv_rx_buf_ioaddr_size);
1406 	err = (nxge_status_t)nxge_herr2kerr(hverr);
1407 	if (err != 0) {
1408 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1409 		    "<== nxge_init_hv_fzc_rxdma_channel_pages: channel %d"
1410 		    "error status 0x%x "
1411 		    "(page 0 data buf) hverr 0x%llx "
1412 		    "ioaddr_pp $%p "
1413 		    "size 0x%llx ",
1414 		    channel,
1415 		    err,
1416 		    hverr,
1417 		    rbrp->hv_rx_buf_base_ioaddr_pp,
1418 		    rbrp->hv_rx_buf_ioaddr_size));
1419 
1420 		return (NXGE_ERROR | err);
1421 	}
1422 
1423 #ifdef	DEBUG
1424 	ra = size = 0;
1425 	(void) hv_niu_rx_logical_page_info((uint64_t)channel,
1426 	    (uint64_t)0,
1427 	    &ra,
1428 	    &size);
1429 
1430 	NXGE_DEBUG_MSG((nxgep, RX_CTL,
1431 	    "==> nxge_init_hv_fzc_rxdma_channel_pages: channel %d "
1432 	    "ok status 0x%x "
1433 	    "(page 0 data buf) hverr 0x%llx "
1434 	    "set databuf ioaddr_pp $%p "
1435 	    "set databuf size 0x%llx "
1436 	    "get databuf ra ioaddr_pp %p "
1437 	    "get databuf size 0x%llx",
1438 	    channel,
1439 	    err,
1440 	    hverr,
1441 	    rbrp->hv_rx_buf_base_ioaddr_pp,
1442 	    rbrp->hv_rx_buf_ioaddr_size,
1443 	    ra,
1444 	    size));
1445 #endif
1446 
1447 	/* Initialize control buffers for logical page 1.  */
1448 	hverr = hv_niu_rx_logical_page_conf((uint64_t)channel,
1449 	    (uint64_t)1,
1450 	    rbrp->hv_rx_cntl_base_ioaddr_pp,
1451 	    rbrp->hv_rx_cntl_ioaddr_size);
1452 
1453 	err = (nxge_status_t)nxge_herr2kerr(hverr);
1454 	if (err != 0) {
1455 		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1456 		    "<== nxge_init_hv_fzc_rxdma_channel_pages: channel %d"
1457 		    "error status 0x%x "
1458 		    "(page 1 cntl buf) hverr 0x%llx "
1459 		    "ioaddr_pp $%p "
1460 		    "size 0x%llx ",
1461 		    channel,
1462 		    err,
1463 		    hverr,
1464 		    rbrp->hv_rx_buf_base_ioaddr_pp,
1465 		    rbrp->hv_rx_buf_ioaddr_size));
1466 
1467 		return (NXGE_ERROR | err);
1468 	}
1469 
1470 #ifdef	DEBUG
1471 	ra = size = 0;
1472 	(void) hv_niu_rx_logical_page_info((uint64_t)channel,
1473 	    (uint64_t)1,
1474 	    &ra,
1475 	    &size);
1476 
1477 
1478 	NXGE_DEBUG_MSG((nxgep, RX_CTL,
1479 	    "==> nxge_init_hv_fzc_rxdma_channel_pages: channel %d "
1480 	    "error status 0x%x "
1481 	    "(page 1 cntl buf) hverr 0x%llx "
1482 	    "set cntl ioaddr_pp $%p "
1483 	    "set cntl size 0x%llx "
1484 	    "get cntl ioaddr_pp $%p "
1485 	    "get cntl size 0x%llx ",
1486 	    channel,
1487 	    err,
1488 	    hverr,
1489 	    rbrp->hv_rx_cntl_base_ioaddr_pp,
1490 	    rbrp->hv_rx_cntl_ioaddr_size,
1491 	    ra,
1492 	    size));
1493 #endif
1494 
1495 	rbrp->hv_set = B_FALSE;
1496 
1497 	NXGE_DEBUG_MSG((nxgep, RX_CTL,
1498 	    "<== nxge_init_hv_fzc_rxdma_channel_pages"));
1499 
1500 	return (NXGE_OK);
1501 }
1502 
1503 /*
1504  * Map hypervisor error code to errno. Only
1505  * H_ENORADDR, H_EBADALIGN and H_EINVAL are meaningful
1506  * for niu driver. Any other error codes are mapped to EINVAL.
1507  */
1508 static int
1509 nxge_herr2kerr(uint64_t hv_errcode)
1510 {
1511 	int	s_errcode;
1512 
1513 	switch (hv_errcode) {
1514 	case H_ENORADDR:
1515 	case H_EBADALIGN:
1516 		s_errcode = EFAULT;
1517 		break;
1518 	case H_EOK:
1519 		s_errcode = 0;
1520 		break;
1521 	default:
1522 		s_errcode = EINVAL;
1523 		break;
1524 	}
1525 	return (s_errcode);
1526 }
1527 
1528 #endif	/* sun4v and NIU_LP_WORKAROUND */
1529