1*6f45ec7bSml29623 /* 2*6f45ec7bSml29623 * CDDL HEADER START 3*6f45ec7bSml29623 * 4*6f45ec7bSml29623 * The contents of this file are subject to the terms of the 5*6f45ec7bSml29623 * Common Development and Distribution License (the "License"). 6*6f45ec7bSml29623 * You may not use this file except in compliance with the License. 7*6f45ec7bSml29623 * 8*6f45ec7bSml29623 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*6f45ec7bSml29623 * or http://www.opensolaris.org/os/licensing. 10*6f45ec7bSml29623 * See the License for the specific language governing permissions 11*6f45ec7bSml29623 * and limitations under the License. 12*6f45ec7bSml29623 * 13*6f45ec7bSml29623 * When distributing Covered Code, include this CDDL HEADER in each 14*6f45ec7bSml29623 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*6f45ec7bSml29623 * If applicable, add the following below this CDDL HEADER, with the 16*6f45ec7bSml29623 * fields enclosed by brackets "[]" replaced with your own identifying 17*6f45ec7bSml29623 * information: Portions Copyright [yyyy] [name of copyright owner] 18*6f45ec7bSml29623 * 19*6f45ec7bSml29623 * CDDL HEADER END 20*6f45ec7bSml29623 */ 21*6f45ec7bSml29623 /* 22*6f45ec7bSml29623 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23*6f45ec7bSml29623 * Use is subject to license terms. 24*6f45ec7bSml29623 */ 25*6f45ec7bSml29623 26*6f45ec7bSml29623 #pragma ident "%Z%%M% %I% %E% SMI" 27*6f45ec7bSml29623 28*6f45ec7bSml29623 #include <npi_fflp.h> 29*6f45ec7bSml29623 #include <nxge_defs.h> 30*6f45ec7bSml29623 #include <nxge_fflp.h> 31*6f45ec7bSml29623 #include <nxge_flow.h> 32*6f45ec7bSml29623 #include <nxge_impl.h> 33*6f45ec7bSml29623 #include <nxge_common.h> 34*6f45ec7bSml29623 35*6f45ec7bSml29623 /* 36*6f45ec7bSml29623 * Globals: tunable parameters (/etc/system or adb) 37*6f45ec7bSml29623 * 38*6f45ec7bSml29623 */ 39*6f45ec7bSml29623 int nxge_tcam_class_enable = 0; 40*6f45ec7bSml29623 int nxge_tcam_lookup_enable = 0; 41*6f45ec7bSml29623 int nxge_flow_dist_enable = NXGE_CLASS_FLOW_USE_DST_PORT | 42*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST | 43*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO | 44*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_PORTNUM; 45*6f45ec7bSml29623 46*6f45ec7bSml29623 /* 47*6f45ec7bSml29623 * Bit mapped 48*6f45ec7bSml29623 * 0x80000000: Drop 49*6f45ec7bSml29623 * 0x0000: NO TCAM Lookup Needed 50*6f45ec7bSml29623 * 0x0001: TCAM Lookup Needed with Dest Addr (IPv6) 51*6f45ec7bSml29623 * 0x0003: TCAM Lookup Needed with SRC Addr (IPv6) 52*6f45ec7bSml29623 * 0x0010: use MAC Port 53*6f45ec7bSml29623 * 0x0020: use L2DA 54*6f45ec7bSml29623 * 0x0040: use VLAN 55*6f45ec7bSml29623 * 0x0080: use proto 56*6f45ec7bSml29623 * 0x0100: use IP src addr 57*6f45ec7bSml29623 * 0x0200: use IP dest addr 58*6f45ec7bSml29623 * 0x0400: use Src Port 59*6f45ec7bSml29623 * 0x0800: use Dest Port 60*6f45ec7bSml29623 * 0x0fff: enable all options for IPv6 (with src addr) 61*6f45ec7bSml29623 * 0x0ffd: enable all options for IPv6 (with dest addr) 62*6f45ec7bSml29623 * 0x0fff: enable all options for IPv4 63*6f45ec7bSml29623 * 0x0ffd: enable all options for IPv4 64*6f45ec7bSml29623 * 65*6f45ec7bSml29623 */ 66*6f45ec7bSml29623 67*6f45ec7bSml29623 /* 68*6f45ec7bSml29623 * the default is to distribute as function of: 69*6f45ec7bSml29623 * protocol 70*6f45ec7bSml29623 * ip src address 71*6f45ec7bSml29623 * ip dest address 72*6f45ec7bSml29623 * src port 73*6f45ec7bSml29623 * dest port 74*6f45ec7bSml29623 * 75*6f45ec7bSml29623 * 0x0f80 76*6f45ec7bSml29623 * 77*6f45ec7bSml29623 */ 78*6f45ec7bSml29623 79*6f45ec7bSml29623 int nxge_tcp4_class = NXGE_CLASS_FLOW_USE_DST_PORT | 80*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST | 81*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO | 82*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_PORTNUM; 83*6f45ec7bSml29623 84*6f45ec7bSml29623 int nxge_udp4_class = NXGE_CLASS_FLOW_USE_DST_PORT | 85*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST | 86*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO | 87*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_PORTNUM; 88*6f45ec7bSml29623 89*6f45ec7bSml29623 int nxge_ah4_class = NXGE_CLASS_FLOW_USE_DST_PORT | 90*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST | 91*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO | 92*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_PORTNUM; 93*6f45ec7bSml29623 int nxge_sctp4_class = NXGE_CLASS_FLOW_USE_DST_PORT | 94*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST | 95*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO | 96*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_PORTNUM; 97*6f45ec7bSml29623 98*6f45ec7bSml29623 int nxge_tcp6_class = NXGE_CLASS_FLOW_USE_DST_PORT | 99*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST | 100*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO | 101*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_PORTNUM; 102*6f45ec7bSml29623 103*6f45ec7bSml29623 int nxge_udp6_class = NXGE_CLASS_FLOW_USE_DST_PORT | 104*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST | 105*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO | 106*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_PORTNUM; 107*6f45ec7bSml29623 108*6f45ec7bSml29623 int nxge_ah6_class = NXGE_CLASS_FLOW_USE_DST_PORT | 109*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST | 110*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO | 111*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_PORTNUM; 112*6f45ec7bSml29623 113*6f45ec7bSml29623 int nxge_sctp6_class = NXGE_CLASS_FLOW_USE_DST_PORT | 114*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_SRC_PORT | NXGE_CLASS_FLOW_USE_IPDST | 115*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_IPSRC | NXGE_CLASS_FLOW_USE_PROTO | 116*6f45ec7bSml29623 NXGE_CLASS_FLOW_USE_PORTNUM; 117*6f45ec7bSml29623 118*6f45ec7bSml29623 uint32_t nxge_fflp_init_h1 = 0xffffffff; 119*6f45ec7bSml29623 uint32_t nxge_fflp_init_h2 = 0xffff; 120*6f45ec7bSml29623 121*6f45ec7bSml29623 uint64_t class_quick_config_distribute[NXGE_CLASS_CONFIG_PARAMS] = { 122*6f45ec7bSml29623 0xffffffffULL, /* h1_init */ 123*6f45ec7bSml29623 0xffffULL, /* h2_init */ 124*6f45ec7bSml29623 0x0, /* cfg_ether_usr1 */ 125*6f45ec7bSml29623 0x0, /* cfg_ether_usr2 */ 126*6f45ec7bSml29623 0x0, /* cfg_ip_usr4 */ 127*6f45ec7bSml29623 0x0, /* cfg_ip_usr5 */ 128*6f45ec7bSml29623 0x0, /* cfg_ip_usr6 */ 129*6f45ec7bSml29623 0x0, /* cfg_ip_usr7 */ 130*6f45ec7bSml29623 0x0, /* opt_ip_usr4 */ 131*6f45ec7bSml29623 0x0, /* opt_ip_usr5 */ 132*6f45ec7bSml29623 0x0, /* opt_ip_usr6 */ 133*6f45ec7bSml29623 0x0, /* opt_ip_usr7 */ 134*6f45ec7bSml29623 NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv4_tcp */ 135*6f45ec7bSml29623 NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv4_udp */ 136*6f45ec7bSml29623 NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv4_ah */ 137*6f45ec7bSml29623 NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv4_sctp */ 138*6f45ec7bSml29623 NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv6_tcp */ 139*6f45ec7bSml29623 NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv6_udp */ 140*6f45ec7bSml29623 NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv6_ah */ 141*6f45ec7bSml29623 NXGE_CLASS_FLOW_GEN_SERVER /* opt_ipv6_sctp */ 142*6f45ec7bSml29623 }; 143*6f45ec7bSml29623 144*6f45ec7bSml29623 uint64_t class_quick_config_web_server[NXGE_CLASS_CONFIG_PARAMS] = { 145*6f45ec7bSml29623 0xffffffffULL, /* h1_init */ 146*6f45ec7bSml29623 0xffffULL, /* h2_init */ 147*6f45ec7bSml29623 0x0, /* cfg_ether_usr1 */ 148*6f45ec7bSml29623 0x0, /* cfg_ether_usr2 */ 149*6f45ec7bSml29623 0x0, /* cfg_ip_usr4 */ 150*6f45ec7bSml29623 0x0, /* cfg_ip_usr5 */ 151*6f45ec7bSml29623 0x0, /* cfg_ip_usr6 */ 152*6f45ec7bSml29623 0x0, /* cfg_ip_usr7 */ 153*6f45ec7bSml29623 0x0, /* opt_ip_usr4 */ 154*6f45ec7bSml29623 0x0, /* opt_ip_usr5 */ 155*6f45ec7bSml29623 0x0, /* opt_ip_usr6 */ 156*6f45ec7bSml29623 0x0, /* opt_ip_usr7 */ 157*6f45ec7bSml29623 NXGE_CLASS_FLOW_WEB_SERVER, /* opt_ipv4_tcp */ 158*6f45ec7bSml29623 NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv4_udp */ 159*6f45ec7bSml29623 NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv4_ah */ 160*6f45ec7bSml29623 NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv4_sctp */ 161*6f45ec7bSml29623 NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv6_tcp */ 162*6f45ec7bSml29623 NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv6_udp */ 163*6f45ec7bSml29623 NXGE_CLASS_FLOW_GEN_SERVER, /* opt_ipv6_ah */ 164*6f45ec7bSml29623 NXGE_CLASS_FLOW_GEN_SERVER /* opt_ipv6_sctp */ 165*6f45ec7bSml29623 }; 166*6f45ec7bSml29623 167*6f45ec7bSml29623 nxge_status_t 168*6f45ec7bSml29623 nxge_classify_init(p_nxge_t nxgep) 169*6f45ec7bSml29623 { 170*6f45ec7bSml29623 nxge_status_t status = NXGE_OK; 171*6f45ec7bSml29623 172*6f45ec7bSml29623 status = nxge_classify_init_sw(nxgep); 173*6f45ec7bSml29623 if (status != NXGE_OK) 174*6f45ec7bSml29623 return (status); 175*6f45ec7bSml29623 status = nxge_set_hw_classify_config(nxgep); 176*6f45ec7bSml29623 if (status != NXGE_OK) 177*6f45ec7bSml29623 return (status); 178*6f45ec7bSml29623 179*6f45ec7bSml29623 status = nxge_classify_init_hw(nxgep); 180*6f45ec7bSml29623 if (status != NXGE_OK) 181*6f45ec7bSml29623 return (status); 182*6f45ec7bSml29623 183*6f45ec7bSml29623 return (NXGE_OK); 184*6f45ec7bSml29623 } 185*6f45ec7bSml29623 186*6f45ec7bSml29623 nxge_status_t 187*6f45ec7bSml29623 nxge_classify_uninit(p_nxge_t nxgep) 188*6f45ec7bSml29623 { 189*6f45ec7bSml29623 nxge_status_t status = NXGE_OK; 190*6f45ec7bSml29623 191*6f45ec7bSml29623 status = nxge_classify_exit_sw(nxgep); 192*6f45ec7bSml29623 if (status != NXGE_OK) { 193*6f45ec7bSml29623 return (status); 194*6f45ec7bSml29623 } 195*6f45ec7bSml29623 return (NXGE_OK); 196*6f45ec7bSml29623 } 197*6f45ec7bSml29623 198*6f45ec7bSml29623 /* ARGSUSED */ 199*6f45ec7bSml29623 uint64_t 200*6f45ec7bSml29623 nxge_classify_get_cfg_value(p_nxge_t nxgep, uint8_t cfg_type, uint8_t cfg_param) 201*6f45ec7bSml29623 { 202*6f45ec7bSml29623 uint64_t cfg_value; 203*6f45ec7bSml29623 204*6f45ec7bSml29623 if (cfg_param >= NXGE_CLASS_CONFIG_PARAMS) 205*6f45ec7bSml29623 return (-1); 206*6f45ec7bSml29623 switch (cfg_type) { 207*6f45ec7bSml29623 case CFG_L3_WEB: 208*6f45ec7bSml29623 cfg_value = class_quick_config_web_server[cfg_param]; 209*6f45ec7bSml29623 break; 210*6f45ec7bSml29623 case CFG_L3_DISTRIBUTE: 211*6f45ec7bSml29623 default: 212*6f45ec7bSml29623 cfg_value = class_quick_config_distribute[cfg_param]; 213*6f45ec7bSml29623 break; 214*6f45ec7bSml29623 } 215*6f45ec7bSml29623 return (cfg_value); 216*6f45ec7bSml29623 } 217*6f45ec7bSml29623 218*6f45ec7bSml29623 nxge_status_t 219*6f45ec7bSml29623 nxge_set_hw_classify_config(p_nxge_t nxgep) 220*6f45ec7bSml29623 { 221*6f45ec7bSml29623 p_nxge_dma_pt_cfg_t p_all_cfgp; 222*6f45ec7bSml29623 p_nxge_hw_pt_cfg_t p_cfgp; 223*6f45ec7bSml29623 224*6f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_get_hw_classify_config")); 225*6f45ec7bSml29623 226*6f45ec7bSml29623 /* Get mac rdc table info from HW/Prom/.conf etc ...... */ 227*6f45ec7bSml29623 /* for now, get it from dma configs */ 228*6f45ec7bSml29623 p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 229*6f45ec7bSml29623 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_all_cfgp->hw_config; 230*6f45ec7bSml29623 231*6f45ec7bSml29623 /* 232*6f45ec7bSml29623 * classify_init needs to call first. 233*6f45ec7bSml29623 */ 234*6f45ec7bSml29623 nxgep->class_config.mac_rdcgrp = p_cfgp->def_mac_rxdma_grpid; 235*6f45ec7bSml29623 nxgep->class_config.mcast_rdcgrp = p_cfgp->def_mac_rxdma_grpid; 236*6f45ec7bSml29623 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "<== nxge_get_hw_classify_config")); 237*6f45ec7bSml29623 238*6f45ec7bSml29623 return (NXGE_OK); 239*6f45ec7bSml29623 } 240