xref: /titanic_51/usr/src/uts/common/io/nxge/npi/npi.h (revision 15d9d0b528387242011cdcc6190c9e598cfe3a07)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _NPI_H
27 #define	_NPI_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 #include <nxge_common_impl.h>
36 
37 typedef	uint32_t			npi_status_t;
38 
39 /* Common Block ID */
40 
41 #define	MAC_BLK_ID			0x1
42 #define	TXMAC_BLK_ID			0x2
43 #define	RXMAC_BLK_ID			0x3
44 #define	MIF_BLK_ID			0x4
45 #define	IPP_BLK_ID			0x5
46 #define	TXC_BLK_ID			0x6
47 #define	TXDMA_BLK_ID			0x7
48 #define	RXDMA_BLK_ID			0x8
49 #define	ZCP_BLK_ID			0x9
50 #define	ESPC_BLK_ID			0xa
51 #define	FFLP_BLK_ID			0xb
52 #define	PHY_BLK_ID			0xc
53 #define	ETHER_SERDES_BLK_ID		0xd
54 #define	PCIE_SERDES_BLK_ID		0xe
55 #define	VIR_BLK_ID			0xf
56 #define	XAUI_BLK_ID			0x10
57 #define	XFP_BLK_ID			0x11
58 
59 /* Common HW error code */
60 /* HW unable to exit from reset state. */
61 #define	RESET_FAILED			0x81
62 
63 /* Write operation failed on indirect write. */
64 #define	WRITE_FAILED			0x82
65 /* Read operation failed on indirect read.	 */
66 #define	READ_FAILED			0x83
67 
68 /* Error code boundary */
69 
70 #define	COMMON_SW_ERR_START		0x40
71 #define	COMMON_SW_ERR_END		0x4f
72 #define	BLK_SPEC_SW_ERR_START		0x50
73 #define	BLK_SPEC_SW_ERR_END		0x7f
74 #define	COMMON_HW_ERR_START		0x80
75 #define	COMMON_HW_ERR_END		0x8f
76 #define	BLK_SPEC_HW_ERR_START		0x90
77 #define	BLK_SPEC_HW_ERR_END		0xbf
78 
79 #define	IS_PORT				0x00100000
80 #define	IS_CHAN				0x00200000
81 
82 /* Common SW errors code */
83 
84 #define	PORT_INVALID			0x41	/* Invalid port number */
85 #define	CHANNEL_INVALID			0x42	/* Invalid dma channel number */
86 #define	OPCODE_INVALID			0x43	/* Invalid opcode */
87 #define	REGISTER_INVALID		0x44	/* Invalid register number */
88 #define	COUNTER_INVALID			0x45	/* Invalid counter number */
89 #define	CONFIG_INVALID			0x46	/* Invalid config input */
90 #define	LOGICAL_PAGE_INVALID		0x47	/* Invalid logical page # */
91 #define	VLAN_INVALID			0x48	/* Invalid Vlan ID */
92 #define	RDC_TAB_INVALID			0x49	/* Invalid RDC Group Number */
93 #define	LOCATION_INVALID		0x4a	/* Invalid Entry Location */
94 
95 #define	NPI_SUCCESS			0		/* Operation succeed */
96 #define	NPI_FAILURE			0x80000000	/* Operation failed */
97 
98 #define	NPI_CNT_CLR_VAL			0
99 
100 /*
101  * Block identifier starts at bit 8.
102  */
103 #define	NPI_BLOCK_ID_SHIFT		8
104 
105 /*
106  * Port, channel and misc. information starts at bit 12.
107  */
108 #define	NPI_PORT_CHAN_SHIFT			12
109 
110 /*
111  * Software Block specific error codes start at 0x50.
112  */
113 #define	NPI_BK_ERROR_START		0x50
114 
115 /*
116  * Hardware block specific error codes start at 0x90.
117  */
118 #define	NPI_BK_HW_ER_START		0x90
119 
120 /* Structures for register tracing */
121 
122 typedef struct _rt_buf {
123 	uint32_t	ctl_addr;
124 	uint32_t	val_l32;
125 	uint32_t	val_h32;
126 } rt_buf_t;
127 
128 /*
129  * Control Address field format
130  *
131  * Bit 0 - 23: Address
132  * Bit 24 - 25: Function Number
133  * Bit 26 - 29: Instance Number
134  * Bit 30: Read/Write Direction bit
135  * Bit 31: Invalid bit
136  */
137 
138 #define	MAX_RTRACE_ENTRIES	1024
139 #define	MAX_RTRACE_IOC_ENTRIES	64
140 #define	TRACE_ADDR_MASK		0x00FFFFFF
141 #define	TRACE_FUNC_MASK		0x03000000
142 #define	TRACE_INST_MASK		0x3C000000
143 #define	TRACE_CTL_WR		0x40000000
144 #define	TRACE_CTL_INVALID	0x80000000
145 #define	TRACE_FUNC_SHIFT	24
146 #define	TRACE_INST_SHIFT	26
147 #define	MSG_BUF_SIZE		1024
148 
149 
150 typedef struct _rtrace {
151 	uint16_t	next_idx;
152 	uint16_t	last_idx;
153 	boolean_t	wrapped;
154 	rt_buf_t	buf[MAX_RTRACE_ENTRIES];
155 } rtrace_t;
156 
157 typedef struct _err_inject {
158 	uint8_t		blk_id;
159 	uint8_t		chan;
160 	uint32_t	err_id;
161 	uint32_t	control;
162 } err_inject_t;
163 
164 /* Configuration options */
165 typedef enum config_op {
166 	DISABLE = 0,
167 	ENABLE,
168 	INIT
169 } config_op_t;
170 
171 /* I/O options */
172 typedef enum io_op {
173 	OP_SET = 0,
174 	OP_GET,
175 	OP_UPDATE,
176 	OP_CLEAR
177 } io_op_t;
178 
179 /* Counter options */
180 typedef enum counter_op {
181 	SNAP_STICKY = 0,
182 	SNAP_ACCUMULATE,
183 	CLEAR
184 } counter_op_t;
185 
186 /* NPI attribute */
187 typedef struct _npi_attr_t {
188 	uint32_t type;
189 	uint32_t idata[16];
190 	uint32_t odata[16];
191 } npi_attr_t;
192 
193 /* NPI Handle */
194 typedef	struct	_npi_handle_function {
195 	uint16_t		instance;
196 	uint16_t		function;
197 } npi_handle_function_t;
198 
199 /* NPI Handle */
200 typedef	struct	_npi_handle {
201 	npi_reg_handle_t	regh;
202 	npi_reg_ptr_t		regp;
203 	boolean_t		is_vraddr; /* virtualization region address */
204 	npi_handle_function_t	function;
205 	void * nxgep;
206 } npi_handle_t;
207 
208 /* NPI Counter */
209 typedef struct _npi_counter_t {
210 	uint32_t id;
211 	char *name;
212 	uint32_t val;
213 } npi_counter_t;
214 
215 /*
216  * Commmon definitions for NPI RXDMA and TXDMA functions.
217  */
218 typedef struct _dma_log_page {
219 	uint8_t			page_num;
220 	boolean_t		valid;
221 	uint8_t			func_num;
222 	uint64_t		mask;
223 	uint64_t		value;
224 	uint64_t		reloc;
225 } dma_log_page_t, *p_dma_log_page_t;
226 
227 extern	rtrace_t npi_rtracebuf;
228 void npi_rtrace_buf_init(rtrace_t *);
229 void npi_rtrace_update(npi_handle_t, boolean_t, rtrace_t *,
230 			uint32_t, uint64_t);
231 void npi_rtrace_buf_init(rtrace_t *);
232 
233 void npi_debug_msg(npi_handle_function_t, uint64_t,
234 	char *, ...);
235 
236 #ifdef	NPI_DEBUG
237 #define	NPI_DEBUG_MSG(params) npi_debug_msg params
238 #else
239 #define	NPI_DEBUG_MSG(params)
240 #endif
241 
242 #define	NPI_ERROR_MSG(params) npi_debug_msg params
243 #define	NPI_REG_DUMP_MSG(params) npi_debug_msg params
244 
245 #ifdef	__cplusplus
246 }
247 #endif
248 
249 #endif	/* _NPI_H */
250