1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 28 #include "nge.h" 29 30 /* 31 * Describes the chip's DMA engine 32 */ 33 34 static ddi_dma_attr_t hot_dma_attr = { 35 DMA_ATTR_V0, /* dma_attr version */ 36 0x0000000000000000ull, /* dma_attr_addr_lo */ 37 0x000000FFFFFFFFFFull, /* dma_attr_addr_hi */ 38 0x000000007FFFFFFFull, /* dma_attr_count_max */ 39 0x0000000000000010ull, /* dma_attr_align */ 40 0x00000FFF, /* dma_attr_burstsizes */ 41 0x00000001, /* dma_attr_minxfer */ 42 0x000000000000FFFFull, /* dma_attr_maxxfer */ 43 0x000000FFFFFFFFFFull, /* dma_attr_seg */ 44 1, /* dma_attr_sgllen */ 45 0x00000001, /* dma_attr_granular */ 46 0 47 }; 48 49 static ddi_dma_attr_t hot_tx_dma_attr = { 50 DMA_ATTR_V0, /* dma_attr version */ 51 0x0000000000000000ull, /* dma_attr_addr_lo */ 52 0x000000FFFFFFFFFFull, /* dma_attr_addr_hi */ 53 0x0000000000003FFFull, /* dma_attr_count_max */ 54 0x0000000000000010ull, /* dma_attr_align */ 55 0x00000FFF, /* dma_attr_burstsizes */ 56 0x00000001, /* dma_attr_minxfer */ 57 0x0000000000003FFFull, /* dma_attr_maxxfer */ 58 0x000000FFFFFFFFFFull, /* dma_attr_seg */ 59 NGE_MAX_COOKIES, /* dma_attr_sgllen */ 60 1, /* dma_attr_granular */ 61 0 62 }; 63 64 static ddi_dma_attr_t sum_dma_attr = { 65 DMA_ATTR_V0, /* dma_attr version */ 66 0x0000000000000000ull, /* dma_attr_addr_lo */ 67 0x00000000FFFFFFFFull, /* dma_attr_addr_hi */ 68 0x000000007FFFFFFFull, /* dma_attr_count_max */ 69 0x0000000000000010ull, /* dma_attr_align */ 70 0x00000FFF, /* dma_attr_burstsizes */ 71 0x00000001, /* dma_attr_minxfer */ 72 0x000000000000FFFFull, /* dma_attr_maxxfer */ 73 0x00000000FFFFFFFFull, /* dma_attr_seg */ 74 1, /* dma_attr_sgllen */ 75 0x00000001, /* dma_attr_granular */ 76 0 77 }; 78 79 static ddi_dma_attr_t sum_tx_dma_attr = { 80 DMA_ATTR_V0, /* dma_attr version */ 81 0x0000000000000000ull, /* dma_attr_addr_lo */ 82 0x00000000FFFFFFFFull, /* dma_attr_addr_hi */ 83 0x0000000000003FFFull, /* dma_attr_count_max */ 84 0x0000000000000010ull, /* dma_attr_align */ 85 0x00000FFF, /* dma_attr_burstsizes */ 86 0x00000001, /* dma_attr_minxfer */ 87 0x0000000000003FFFull, /* dma_attr_maxxfer */ 88 0x00000000FFFFFFFFull, /* dma_attr_seg */ 89 NGE_MAX_COOKIES, /* dma_attr_sgllen */ 90 1, /* dma_attr_granular */ 91 0 92 }; 93 94 /* 95 * DMA access attributes for data. 96 */ 97 ddi_device_acc_attr_t nge_data_accattr = { 98 DDI_DEVICE_ATTR_V0, 99 DDI_STRUCTURE_LE_ACC, 100 DDI_STRICTORDER_ACC, 101 DDI_DEFAULT_ACC 102 }; 103 104 /* 105 * DMA access attributes for descriptors. 106 */ 107 static ddi_device_acc_attr_t nge_desc_accattr = { 108 DDI_DEVICE_ATTR_V0, 109 DDI_STRUCTURE_LE_ACC, 110 DDI_STRICTORDER_ACC, 111 DDI_DEFAULT_ACC 112 }; 113 114 /* 115 * PIO access attributes for registers 116 */ 117 static ddi_device_acc_attr_t nge_reg_accattr = { 118 DDI_DEVICE_ATTR_V0, 119 DDI_STRUCTURE_LE_ACC, 120 DDI_STRICTORDER_ACC, 121 DDI_DEFAULT_ACC 122 }; 123 124 /* 125 * NIC DESC MODE 2 126 */ 127 128 static const nge_desc_attr_t nge_sum_desc = { 129 130 sizeof (sum_rx_bd), 131 sizeof (sum_tx_bd), 132 &sum_dma_attr, 133 &sum_tx_dma_attr, 134 nge_sum_rxd_fill, 135 nge_sum_rxd_check, 136 nge_sum_txd_fill, 137 nge_sum_txd_check, 138 }; 139 140 /* 141 * NIC DESC MODE 3 142 */ 143 144 static const nge_desc_attr_t nge_hot_desc = { 145 146 sizeof (hot_rx_bd), 147 sizeof (hot_tx_bd), 148 &hot_dma_attr, 149 &hot_tx_dma_attr, 150 nge_hot_rxd_fill, 151 nge_hot_rxd_check, 152 nge_hot_txd_fill, 153 nge_hot_txd_check, 154 }; 155 156 static char nge_ident[] = "nVidia 1Gb Ethernet"; 157 static char clsize_propname[] = "cache-line-size"; 158 static char latency_propname[] = "latency-timer"; 159 static char debug_propname[] = "nge-debug-flags"; 160 static char intr_moderation[] = "intr-moderation"; 161 static char rx_data_hw[] = "rx-data-hw"; 162 static char rx_prd_lw[] = "rx-prd-lw"; 163 static char rx_prd_hw[] = "rx-prd-hw"; 164 static char sw_intr_intv[] = "sw-intr-intvl"; 165 static char nge_desc_mode[] = "desc-mode"; 166 static char default_mtu[] = "default_mtu"; 167 static char low_memory_mode[] = "minimal-memory-usage"; 168 extern kmutex_t nge_log_mutex[1]; 169 170 static int nge_m_start(void *); 171 static void nge_m_stop(void *); 172 static int nge_m_promisc(void *, boolean_t); 173 static int nge_m_multicst(void *, boolean_t, const uint8_t *); 174 static int nge_m_unicst(void *, const uint8_t *); 175 static void nge_m_ioctl(void *, queue_t *, mblk_t *); 176 static boolean_t nge_m_getcapab(void *, mac_capab_t, void *); 177 static int nge_m_setprop(void *, const char *, mac_prop_id_t, 178 uint_t, const void *); 179 static int nge_m_getprop(void *, const char *, mac_prop_id_t, 180 uint_t, uint_t, void *, uint_t *); 181 static int nge_set_priv_prop(nge_t *, const char *, uint_t, 182 const void *); 183 static int nge_get_priv_prop(nge_t *, const char *, uint_t, 184 uint_t, void *); 185 186 #define NGE_M_CALLBACK_FLAGS\ 187 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 188 189 static mac_callbacks_t nge_m_callbacks = { 190 NGE_M_CALLBACK_FLAGS, 191 nge_m_stat, 192 nge_m_start, 193 nge_m_stop, 194 nge_m_promisc, 195 nge_m_multicst, 196 nge_m_unicst, 197 nge_m_tx, 198 NULL, 199 nge_m_ioctl, 200 nge_m_getcapab, 201 NULL, 202 NULL, 203 nge_m_setprop, 204 nge_m_getprop 205 }; 206 207 mac_priv_prop_t nge_priv_props[] = { 208 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 209 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 210 {"_recv_max_packet", MAC_PROP_PERM_RW}, 211 {"_poll_quiet_time", MAC_PROP_PERM_RW}, 212 {"_poll_busy_time", MAC_PROP_PERM_RW}, 213 {"_rx_intr_hwater", MAC_PROP_PERM_RW}, 214 {"_rx_intr_lwater", MAC_PROP_PERM_RW}, 215 {"_adv_pause_cap", MAC_PROP_PERM_RW}, 216 {"_adv_asym_pause_cap", MAC_PROP_PERM_RW}, 217 {"_tx_n_intr", MAC_PROP_PERM_RW} 218 }; 219 220 #define NGE_MAX_PRIV_PROPS \ 221 (sizeof (nge_priv_props)/sizeof (mac_priv_prop_t)) 222 223 static int nge_add_intrs(nge_t *, int); 224 static void nge_rem_intrs(nge_t *); 225 static int nge_register_intrs_and_init_locks(nge_t *); 226 227 /* 228 * NGE MSI tunable: 229 */ 230 boolean_t nge_enable_msi = B_FALSE; 231 232 static enum ioc_reply 233 nge_set_loop_mode(nge_t *ngep, uint32_t mode) 234 { 235 /* 236 * If the mode isn't being changed, there's nothing to do ... 237 */ 238 if (mode == ngep->param_loop_mode) 239 return (IOC_ACK); 240 241 /* 242 * Validate the requested mode and prepare a suitable message 243 * to explain the link down/up cycle that the change will 244 * probably induce ... 245 */ 246 switch (mode) { 247 default: 248 return (IOC_INVAL); 249 250 case NGE_LOOP_NONE: 251 case NGE_LOOP_EXTERNAL_100: 252 case NGE_LOOP_EXTERNAL_10: 253 case NGE_LOOP_INTERNAL_PHY: 254 break; 255 } 256 257 /* 258 * All OK; tell the caller to reprogram 259 * the PHY and/or MAC for the new mode ... 260 */ 261 ngep->param_loop_mode = mode; 262 return (IOC_RESTART_ACK); 263 } 264 265 #undef NGE_DBG 266 #define NGE_DBG NGE_DBG_INIT 267 268 /* 269 * Utility routine to carve a slice off a chunk of allocated memory, 270 * updating the chunk descriptor accordingly. The size of the slice 271 * is given by the product of the <qty> and <size> parameters. 272 */ 273 void 274 nge_slice_chunk(dma_area_t *slice, dma_area_t *chunk, 275 uint32_t qty, uint32_t size) 276 { 277 size_t totsize; 278 279 totsize = qty*size; 280 ASSERT(size > 0); 281 ASSERT(totsize <= chunk->alength); 282 283 *slice = *chunk; 284 slice->nslots = qty; 285 slice->size = size; 286 slice->alength = totsize; 287 288 chunk->mem_va = (caddr_t)chunk->mem_va + totsize; 289 chunk->alength -= totsize; 290 chunk->offset += totsize; 291 chunk->cookie.dmac_laddress += totsize; 292 chunk->cookie.dmac_size -= totsize; 293 } 294 295 /* 296 * Allocate an area of memory and a DMA handle for accessing it 297 */ 298 int 299 nge_alloc_dma_mem(nge_t *ngep, size_t memsize, ddi_device_acc_attr_t *attr_p, 300 uint_t dma_flags, dma_area_t *dma_p) 301 { 302 int err; 303 caddr_t va; 304 305 NGE_TRACE(("nge_alloc_dma_mem($%p, %ld, $%p, 0x%x, $%p)", 306 (void *)ngep, memsize, attr_p, dma_flags, dma_p)); 307 /* 308 * Allocate handle 309 */ 310 err = ddi_dma_alloc_handle(ngep->devinfo, ngep->desc_attr.dma_attr, 311 DDI_DMA_DONTWAIT, NULL, &dma_p->dma_hdl); 312 if (err != DDI_SUCCESS) 313 goto fail; 314 315 /* 316 * Allocate memory 317 */ 318 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p, 319 dma_flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING), 320 DDI_DMA_DONTWAIT, NULL, &va, &dma_p->alength, &dma_p->acc_hdl); 321 if (err != DDI_SUCCESS) 322 goto fail; 323 324 /* 325 * Bind the two together 326 */ 327 dma_p->mem_va = va; 328 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL, 329 va, dma_p->alength, dma_flags, DDI_DMA_DONTWAIT, NULL, 330 &dma_p->cookie, &dma_p->ncookies); 331 332 if (err != DDI_DMA_MAPPED || dma_p->ncookies != 1) 333 goto fail; 334 335 dma_p->nslots = ~0U; 336 dma_p->size = ~0U; 337 dma_p->offset = 0; 338 339 return (DDI_SUCCESS); 340 341 fail: 342 nge_free_dma_mem(dma_p); 343 NGE_DEBUG(("nge_alloc_dma_mem: fail to alloc dma memory!")); 344 345 return (DDI_FAILURE); 346 } 347 348 /* 349 * Free one allocated area of DMAable memory 350 */ 351 void 352 nge_free_dma_mem(dma_area_t *dma_p) 353 { 354 if (dma_p->dma_hdl != NULL) { 355 if (dma_p->ncookies) { 356 (void) ddi_dma_unbind_handle(dma_p->dma_hdl); 357 dma_p->ncookies = 0; 358 } 359 } 360 if (dma_p->acc_hdl != NULL) { 361 ddi_dma_mem_free(&dma_p->acc_hdl); 362 dma_p->acc_hdl = NULL; 363 } 364 if (dma_p->dma_hdl != NULL) { 365 ddi_dma_free_handle(&dma_p->dma_hdl); 366 dma_p->dma_hdl = NULL; 367 } 368 } 369 370 #define ALLOC_TX_BUF 0x1 371 #define ALLOC_TX_DESC 0x2 372 #define ALLOC_RX_DESC 0x4 373 374 int 375 nge_alloc_bufs(nge_t *ngep) 376 { 377 int err; 378 int split; 379 int progress; 380 size_t txbuffsize; 381 size_t rxdescsize; 382 size_t txdescsize; 383 384 txbuffsize = ngep->tx_desc * ngep->buf_size; 385 rxdescsize = ngep->rx_desc; 386 txdescsize = ngep->tx_desc; 387 rxdescsize *= ngep->desc_attr.rxd_size; 388 txdescsize *= ngep->desc_attr.txd_size; 389 progress = 0; 390 391 NGE_TRACE(("nge_alloc_bufs($%p)", (void *)ngep)); 392 /* 393 * Allocate memory & handles for TX buffers 394 */ 395 ASSERT((txbuffsize % ngep->nge_split) == 0); 396 for (split = 0; split < ngep->nge_split; ++split) { 397 err = nge_alloc_dma_mem(ngep, txbuffsize/ngep->nge_split, 398 &nge_data_accattr, DDI_DMA_WRITE | NGE_DMA_MODE, 399 &ngep->send->buf[split]); 400 if (err != DDI_SUCCESS) 401 goto fail; 402 } 403 404 progress |= ALLOC_TX_BUF; 405 406 /* 407 * Allocate memory & handles for receive return rings and 408 * buffer (producer) descriptor rings 409 */ 410 err = nge_alloc_dma_mem(ngep, rxdescsize, &nge_desc_accattr, 411 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &ngep->recv->desc); 412 if (err != DDI_SUCCESS) 413 goto fail; 414 progress |= ALLOC_RX_DESC; 415 416 /* 417 * Allocate memory & handles for TX descriptor rings, 418 */ 419 err = nge_alloc_dma_mem(ngep, txdescsize, &nge_desc_accattr, 420 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &ngep->send->desc); 421 if (err != DDI_SUCCESS) 422 goto fail; 423 return (DDI_SUCCESS); 424 425 fail: 426 if (progress & ALLOC_RX_DESC) 427 nge_free_dma_mem(&ngep->recv->desc); 428 if (progress & ALLOC_TX_BUF) { 429 for (split = 0; split < ngep->nge_split; ++split) 430 nge_free_dma_mem(&ngep->send->buf[split]); 431 } 432 433 return (DDI_FAILURE); 434 } 435 436 /* 437 * This routine frees the transmit and receive buffers and descriptors. 438 * Make sure the chip is stopped before calling it! 439 */ 440 void 441 nge_free_bufs(nge_t *ngep) 442 { 443 int split; 444 445 NGE_TRACE(("nge_free_bufs($%p)", (void *)ngep)); 446 447 nge_free_dma_mem(&ngep->recv->desc); 448 nge_free_dma_mem(&ngep->send->desc); 449 450 for (split = 0; split < ngep->nge_split; ++split) 451 nge_free_dma_mem(&ngep->send->buf[split]); 452 } 453 454 /* 455 * Clean up initialisation done above before the memory is freed 456 */ 457 static void 458 nge_fini_send_ring(nge_t *ngep) 459 { 460 uint32_t slot; 461 size_t dmah_num; 462 send_ring_t *srp; 463 sw_tx_sbd_t *ssbdp; 464 465 srp = ngep->send; 466 ssbdp = srp->sw_sbds; 467 468 NGE_TRACE(("nge_fini_send_ring($%p)", (void *)ngep)); 469 470 dmah_num = sizeof (srp->dmahndl) / sizeof (srp->dmahndl[0]); 471 472 for (slot = 0; slot < dmah_num; ++slot) { 473 if (srp->dmahndl[slot].hndl) { 474 (void) ddi_dma_unbind_handle(srp->dmahndl[slot].hndl); 475 ddi_dma_free_handle(&srp->dmahndl[slot].hndl); 476 srp->dmahndl[slot].hndl = NULL; 477 srp->dmahndl[slot].next = NULL; 478 } 479 } 480 481 srp->dmah_free.head = NULL; 482 srp->dmah_free.tail = NULL; 483 484 kmem_free(ssbdp, srp->desc.nslots*sizeof (*ssbdp)); 485 486 } 487 488 /* 489 * Initialise the specified Send Ring, using the information in the 490 * <dma_area> descriptors that it contains to set up all the other 491 * fields. This routine should be called only once for each ring. 492 */ 493 static int 494 nge_init_send_ring(nge_t *ngep) 495 { 496 size_t dmah_num; 497 uint32_t nslots; 498 uint32_t err; 499 uint32_t slot; 500 uint32_t split; 501 send_ring_t *srp; 502 sw_tx_sbd_t *ssbdp; 503 dma_area_t desc; 504 dma_area_t pbuf; 505 506 srp = ngep->send; 507 srp->desc.nslots = ngep->tx_desc; 508 nslots = srp->desc.nslots; 509 510 NGE_TRACE(("nge_init_send_ring($%p)", (void *)ngep)); 511 /* 512 * Other one-off initialisation of per-ring data 513 */ 514 srp->ngep = ngep; 515 516 /* 517 * Allocate the array of s/w Send Buffer Descriptors 518 */ 519 ssbdp = kmem_zalloc(nslots*sizeof (*ssbdp), KM_SLEEP); 520 srp->sw_sbds = ssbdp; 521 522 /* 523 * Now initialise each array element once and for all 524 */ 525 desc = srp->desc; 526 for (split = 0; split < ngep->nge_split; ++split) { 527 pbuf = srp->buf[split]; 528 for (slot = 0; slot < nslots/ngep->nge_split; ++ssbdp, ++slot) { 529 nge_slice_chunk(&ssbdp->desc, &desc, 1, 530 ngep->desc_attr.txd_size); 531 nge_slice_chunk(&ssbdp->pbuf, &pbuf, 1, 532 ngep->buf_size); 533 } 534 ASSERT(pbuf.alength == 0); 535 } 536 ASSERT(desc.alength == 0); 537 538 dmah_num = sizeof (srp->dmahndl) / sizeof (srp->dmahndl[0]); 539 540 /* preallocate dma handles for tx buffer */ 541 for (slot = 0; slot < dmah_num; ++slot) { 542 543 err = ddi_dma_alloc_handle(ngep->devinfo, 544 ngep->desc_attr.tx_dma_attr, DDI_DMA_DONTWAIT, 545 NULL, &srp->dmahndl[slot].hndl); 546 547 if (err != DDI_SUCCESS) { 548 nge_fini_send_ring(ngep); 549 nge_error(ngep, 550 "nge_init_send_ring: alloc dma handle fails"); 551 return (DDI_FAILURE); 552 } 553 srp->dmahndl[slot].next = srp->dmahndl + slot + 1; 554 } 555 556 srp->dmah_free.head = srp->dmahndl; 557 srp->dmah_free.tail = srp->dmahndl + dmah_num - 1; 558 srp->dmah_free.tail->next = NULL; 559 560 return (DDI_SUCCESS); 561 } 562 563 /* 564 * Intialize the tx recycle pointer and tx sending pointer of tx ring 565 * and set the type of tx's data descriptor by default. 566 */ 567 static void 568 nge_reinit_send_ring(nge_t *ngep) 569 { 570 size_t dmah_num; 571 uint32_t slot; 572 send_ring_t *srp; 573 sw_tx_sbd_t *ssbdp; 574 575 srp = ngep->send; 576 577 /* 578 * Reinitialise control variables ... 579 */ 580 581 srp->tx_hwmark = NGE_DESC_MIN; 582 srp->tx_lwmark = NGE_DESC_MIN; 583 584 srp->tx_next = 0; 585 srp->tx_free = srp->desc.nslots; 586 srp->tc_next = 0; 587 588 dmah_num = sizeof (srp->dmahndl) / sizeof (srp->dmahndl[0]); 589 590 for (slot = 0; slot - dmah_num != 0; ++slot) 591 srp->dmahndl[slot].next = srp->dmahndl + slot + 1; 592 593 srp->dmah_free.head = srp->dmahndl; 594 srp->dmah_free.tail = srp->dmahndl + dmah_num - 1; 595 srp->dmah_free.tail->next = NULL; 596 597 /* 598 * Zero and sync all the h/w Send Buffer Descriptors 599 */ 600 for (slot = 0; slot < srp->desc.nslots; ++slot) { 601 ssbdp = &srp->sw_sbds[slot]; 602 ssbdp->flags = HOST_OWN; 603 } 604 605 DMA_ZERO(srp->desc); 606 DMA_SYNC(srp->desc, DDI_DMA_SYNC_FORDEV); 607 } 608 609 /* 610 * Initialize the slot number of rx's ring 611 */ 612 static void 613 nge_init_recv_ring(nge_t *ngep) 614 { 615 recv_ring_t *rrp; 616 617 rrp = ngep->recv; 618 rrp->desc.nslots = ngep->rx_desc; 619 rrp->ngep = ngep; 620 } 621 622 /* 623 * Intialize the rx recycle pointer and rx sending pointer of rx ring 624 */ 625 static void 626 nge_reinit_recv_ring(nge_t *ngep) 627 { 628 recv_ring_t *rrp; 629 630 rrp = ngep->recv; 631 632 /* 633 * Reinitialise control variables ... 634 */ 635 rrp->prod_index = 0; 636 /* 637 * Zero and sync all the h/w Send Buffer Descriptors 638 */ 639 DMA_ZERO(rrp->desc); 640 DMA_SYNC(rrp->desc, DDI_DMA_SYNC_FORDEV); 641 } 642 643 /* 644 * Clean up initialisation done above before the memory is freed 645 */ 646 static void 647 nge_fini_buff_ring(nge_t *ngep) 648 { 649 uint32_t i; 650 buff_ring_t *brp; 651 dma_area_t *bufp; 652 sw_rx_sbd_t *bsbdp; 653 654 brp = ngep->buff; 655 bsbdp = brp->sw_rbds; 656 657 NGE_DEBUG(("nge_fini_buff_ring($%p)", (void *)ngep)); 658 659 mutex_enter(brp->recycle_lock); 660 brp->buf_sign++; 661 mutex_exit(brp->recycle_lock); 662 for (i = 0; i < ngep->rx_desc; i++, ++bsbdp) { 663 if (bsbdp->bufp) { 664 if (bsbdp->bufp->mp) 665 freemsg(bsbdp->bufp->mp); 666 nge_free_dma_mem(bsbdp->bufp); 667 kmem_free(bsbdp->bufp, sizeof (dma_area_t)); 668 bsbdp->bufp = NULL; 669 } 670 } 671 while (brp->free_list != NULL) { 672 bufp = brp->free_list; 673 brp->free_list = bufp->next; 674 bufp->next = NULL; 675 if (bufp->mp) 676 freemsg(bufp->mp); 677 nge_free_dma_mem(bufp); 678 kmem_free(bufp, sizeof (dma_area_t)); 679 } 680 while (brp->recycle_list != NULL) { 681 bufp = brp->recycle_list; 682 brp->recycle_list = bufp->next; 683 bufp->next = NULL; 684 if (bufp->mp) 685 freemsg(bufp->mp); 686 nge_free_dma_mem(bufp); 687 kmem_free(bufp, sizeof (dma_area_t)); 688 } 689 690 691 kmem_free(brp->sw_rbds, (ngep->rx_desc * sizeof (*bsbdp))); 692 brp->sw_rbds = NULL; 693 } 694 695 /* 696 * Intialize the Rx's data ring and free ring 697 */ 698 static int 699 nge_init_buff_ring(nge_t *ngep) 700 { 701 uint32_t err; 702 uint32_t slot; 703 uint32_t nslots_buff; 704 uint32_t nslots_recv; 705 buff_ring_t *brp; 706 recv_ring_t *rrp; 707 dma_area_t desc; 708 dma_area_t *bufp; 709 sw_rx_sbd_t *bsbdp; 710 711 rrp = ngep->recv; 712 brp = ngep->buff; 713 brp->nslots = ngep->rx_buf; 714 brp->rx_bcopy = B_FALSE; 715 nslots_recv = rrp->desc.nslots; 716 nslots_buff = brp->nslots; 717 brp->ngep = ngep; 718 719 NGE_TRACE(("nge_init_buff_ring($%p)", (void *)ngep)); 720 721 /* 722 * Allocate the array of s/w Recv Buffer Descriptors 723 */ 724 bsbdp = kmem_zalloc(nslots_recv *sizeof (*bsbdp), KM_SLEEP); 725 brp->sw_rbds = bsbdp; 726 brp->free_list = NULL; 727 brp->recycle_list = NULL; 728 for (slot = 0; slot < nslots_buff; ++slot) { 729 bufp = kmem_zalloc(sizeof (dma_area_t), KM_SLEEP); 730 err = nge_alloc_dma_mem(ngep, (ngep->buf_size 731 + NGE_HEADROOM), 732 &nge_data_accattr, DDI_DMA_READ | NGE_DMA_MODE, bufp); 733 if (err != DDI_SUCCESS) { 734 kmem_free(bufp, sizeof (dma_area_t)); 735 return (DDI_FAILURE); 736 } 737 738 bufp->alength -= NGE_HEADROOM; 739 bufp->offset += NGE_HEADROOM; 740 bufp->private = (caddr_t)ngep; 741 bufp->rx_recycle.free_func = nge_recv_recycle; 742 bufp->rx_recycle.free_arg = (caddr_t)bufp; 743 bufp->signature = brp->buf_sign; 744 bufp->rx_delivered = B_FALSE; 745 bufp->mp = desballoc(DMA_VPTR(*bufp), 746 ngep->buf_size + NGE_HEADROOM, 747 0, &bufp->rx_recycle); 748 749 if (bufp->mp == NULL) { 750 return (DDI_FAILURE); 751 } 752 bufp->next = brp->free_list; 753 brp->free_list = bufp; 754 } 755 756 /* 757 * Now initialise each array element once and for all 758 */ 759 desc = rrp->desc; 760 for (slot = 0; slot < nslots_recv; ++slot, ++bsbdp) { 761 nge_slice_chunk(&bsbdp->desc, &desc, 1, 762 ngep->desc_attr.rxd_size); 763 bufp = brp->free_list; 764 brp->free_list = bufp->next; 765 bsbdp->bufp = bufp; 766 bsbdp->flags = CONTROLER_OWN; 767 bufp->next = NULL; 768 } 769 770 ASSERT(desc.alength == 0); 771 return (DDI_SUCCESS); 772 } 773 774 /* 775 * Fill the host address of data in rx' descriptor 776 * and initialize free pointers of rx free ring 777 */ 778 static int 779 nge_reinit_buff_ring(nge_t *ngep) 780 { 781 uint32_t slot; 782 uint32_t nslots_recv; 783 buff_ring_t *brp; 784 recv_ring_t *rrp; 785 sw_rx_sbd_t *bsbdp; 786 void *hw_bd_p; 787 788 brp = ngep->buff; 789 rrp = ngep->recv; 790 bsbdp = brp->sw_rbds; 791 nslots_recv = rrp->desc.nslots; 792 for (slot = 0; slot < nslots_recv; ++bsbdp, ++slot) { 793 hw_bd_p = DMA_VPTR(bsbdp->desc); 794 /* 795 * There is a scenario: When the traffic of small tcp 796 * packet is heavy, suspending the tcp traffic will 797 * cause the preallocated buffers for rx not to be 798 * released in time by tcp taffic and cause rx's buffer 799 * pointers not to be refilled in time. 800 * 801 * At this point, if we reinitialize the driver, the bufp 802 * pointer for rx's traffic will be NULL. 803 * So the result of the reinitializion fails. 804 */ 805 if (bsbdp->bufp == NULL) 806 return (DDI_FAILURE); 807 808 ngep->desc_attr.rxd_fill(hw_bd_p, &bsbdp->bufp->cookie, 809 bsbdp->bufp->alength); 810 } 811 return (DDI_SUCCESS); 812 } 813 814 static void 815 nge_init_ring_param_lock(nge_t *ngep) 816 { 817 buff_ring_t *brp; 818 send_ring_t *srp; 819 820 srp = ngep->send; 821 brp = ngep->buff; 822 823 /* Init the locks for send ring */ 824 mutex_init(srp->tx_lock, NULL, MUTEX_DRIVER, 825 DDI_INTR_PRI(ngep->intr_pri)); 826 mutex_init(srp->tc_lock, NULL, MUTEX_DRIVER, 827 DDI_INTR_PRI(ngep->intr_pri)); 828 mutex_init(&srp->dmah_lock, NULL, MUTEX_DRIVER, 829 DDI_INTR_PRI(ngep->intr_pri)); 830 831 /* Init parameters of buffer ring */ 832 brp->free_list = NULL; 833 brp->recycle_list = NULL; 834 brp->rx_hold = 0; 835 brp->buf_sign = 0; 836 837 /* Init recycle list lock */ 838 mutex_init(brp->recycle_lock, NULL, MUTEX_DRIVER, 839 DDI_INTR_PRI(ngep->intr_pri)); 840 } 841 842 int 843 nge_init_rings(nge_t *ngep) 844 { 845 uint32_t err; 846 847 err = nge_init_send_ring(ngep); 848 if (err != DDI_SUCCESS) { 849 return (err); 850 } 851 nge_init_recv_ring(ngep); 852 853 err = nge_init_buff_ring(ngep); 854 if (err != DDI_SUCCESS) { 855 nge_fini_send_ring(ngep); 856 return (DDI_FAILURE); 857 } 858 859 return (err); 860 } 861 862 static int 863 nge_reinit_ring(nge_t *ngep) 864 { 865 int err; 866 867 nge_reinit_recv_ring(ngep); 868 nge_reinit_send_ring(ngep); 869 err = nge_reinit_buff_ring(ngep); 870 return (err); 871 } 872 873 874 void 875 nge_fini_rings(nge_t *ngep) 876 { 877 /* 878 * For receive ring, nothing need to be finished. 879 * So only finish buffer ring and send ring here. 880 */ 881 nge_fini_buff_ring(ngep); 882 nge_fini_send_ring(ngep); 883 } 884 885 /* 886 * Loopback ioctl code 887 */ 888 889 static lb_property_t loopmodes[] = { 890 { normal, "normal", NGE_LOOP_NONE }, 891 { external, "100Mbps", NGE_LOOP_EXTERNAL_100 }, 892 { external, "10Mbps", NGE_LOOP_EXTERNAL_10 }, 893 { internal, "PHY", NGE_LOOP_INTERNAL_PHY }, 894 }; 895 896 enum ioc_reply 897 nge_loop_ioctl(nge_t *ngep, mblk_t *mp, struct iocblk *iocp) 898 { 899 int cmd; 900 uint32_t *lbmp; 901 lb_info_sz_t *lbsp; 902 lb_property_t *lbpp; 903 904 /* 905 * Validate format of ioctl 906 */ 907 if (mp->b_cont == NULL) 908 return (IOC_INVAL); 909 910 cmd = iocp->ioc_cmd; 911 912 switch (cmd) { 913 default: 914 return (IOC_INVAL); 915 916 case LB_GET_INFO_SIZE: 917 if (iocp->ioc_count != sizeof (lb_info_sz_t)) 918 return (IOC_INVAL); 919 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 920 *lbsp = sizeof (loopmodes); 921 return (IOC_REPLY); 922 923 case LB_GET_INFO: 924 if (iocp->ioc_count != sizeof (loopmodes)) 925 return (IOC_INVAL); 926 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 927 bcopy(loopmodes, lbpp, sizeof (loopmodes)); 928 return (IOC_REPLY); 929 930 case LB_GET_MODE: 931 if (iocp->ioc_count != sizeof (uint32_t)) 932 return (IOC_INVAL); 933 lbmp = (uint32_t *)mp->b_cont->b_rptr; 934 *lbmp = ngep->param_loop_mode; 935 return (IOC_REPLY); 936 937 case LB_SET_MODE: 938 if (iocp->ioc_count != sizeof (uint32_t)) 939 return (IOC_INVAL); 940 lbmp = (uint32_t *)mp->b_cont->b_rptr; 941 return (nge_set_loop_mode(ngep, *lbmp)); 942 } 943 } 944 945 #undef NGE_DBG 946 #define NGE_DBG NGE_DBG_NEMO 947 948 949 static void 950 nge_check_desc_prop(nge_t *ngep) 951 { 952 if (ngep->desc_mode != DESC_HOT && ngep->desc_mode != DESC_OFFLOAD) 953 ngep->desc_mode = DESC_HOT; 954 955 if (ngep->desc_mode == DESC_OFFLOAD) { 956 957 ngep->desc_attr = nge_sum_desc; 958 959 } else if (ngep->desc_mode == DESC_HOT) { 960 961 ngep->desc_attr = nge_hot_desc; 962 } 963 } 964 965 /* 966 * nge_get_props -- get the parameters to tune the driver 967 */ 968 static void 969 nge_get_props(nge_t *ngep) 970 { 971 chip_info_t *infop; 972 dev_info_t *devinfo; 973 nge_dev_spec_param_t *dev_param_p; 974 975 devinfo = ngep->devinfo; 976 infop = (chip_info_t *)&ngep->chipinfo; 977 dev_param_p = &ngep->dev_spec_param; 978 979 infop->clsize = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 980 DDI_PROP_DONTPASS, clsize_propname, 32); 981 982 infop->latency = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 983 DDI_PROP_DONTPASS, latency_propname, 64); 984 ngep->intr_moderation = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 985 DDI_PROP_DONTPASS, intr_moderation, NGE_SET); 986 ngep->rx_datahwm = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 987 DDI_PROP_DONTPASS, rx_data_hw, 0x20); 988 ngep->rx_prdlwm = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 989 DDI_PROP_DONTPASS, rx_prd_lw, 0x4); 990 ngep->rx_prdhwm = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 991 DDI_PROP_DONTPASS, rx_prd_hw, 0xc); 992 993 ngep->sw_intr_intv = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 994 DDI_PROP_DONTPASS, sw_intr_intv, SWTR_ITC); 995 ngep->debug = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 996 DDI_PROP_DONTPASS, debug_propname, NGE_DBG_CHIP); 997 ngep->desc_mode = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 998 DDI_PROP_DONTPASS, nge_desc_mode, dev_param_p->desc_type); 999 ngep->lowmem_mode = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 1000 DDI_PROP_DONTPASS, low_memory_mode, 0); 1001 1002 if (dev_param_p->jumbo) { 1003 ngep->default_mtu = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 1004 DDI_PROP_DONTPASS, default_mtu, ETHERMTU); 1005 } else 1006 ngep->default_mtu = ETHERMTU; 1007 1008 if (ngep->default_mtu > ETHERMTU && 1009 ngep->default_mtu <= NGE_MTU_2500) { 1010 ngep->buf_size = NGE_JB2500_BUFSZ; 1011 ngep->tx_desc = NGE_SEND_JB2500_SLOTS_DESC; 1012 ngep->rx_desc = NGE_RECV_JB2500_SLOTS_DESC; 1013 ngep->rx_buf = NGE_RECV_JB2500_SLOTS_DESC * 2; 1014 ngep->nge_split = NGE_SPLIT_256; 1015 } else if (ngep->default_mtu > NGE_MTU_2500 && 1016 ngep->default_mtu <= NGE_MTU_4500) { 1017 ngep->buf_size = NGE_JB4500_BUFSZ; 1018 ngep->tx_desc = NGE_SEND_JB4500_SLOTS_DESC; 1019 ngep->rx_desc = NGE_RECV_JB4500_SLOTS_DESC; 1020 ngep->rx_buf = NGE_RECV_JB4500_SLOTS_DESC * 2; 1021 ngep->nge_split = NGE_SPLIT_256; 1022 } else if (ngep->default_mtu > NGE_MTU_4500 && 1023 ngep->default_mtu <= NGE_MAX_MTU) { 1024 ngep->buf_size = NGE_JB9000_BUFSZ; 1025 ngep->tx_desc = NGE_SEND_JB9000_SLOTS_DESC; 1026 ngep->rx_desc = NGE_RECV_JB9000_SLOTS_DESC; 1027 ngep->rx_buf = NGE_RECV_JB9000_SLOTS_DESC * 2; 1028 ngep->nge_split = NGE_SPLIT_256; 1029 } else if (ngep->default_mtu > NGE_MAX_MTU) { 1030 ngep->default_mtu = NGE_MAX_MTU; 1031 ngep->buf_size = NGE_JB9000_BUFSZ; 1032 ngep->tx_desc = NGE_SEND_JB9000_SLOTS_DESC; 1033 ngep->rx_desc = NGE_RECV_JB9000_SLOTS_DESC; 1034 ngep->rx_buf = NGE_RECV_JB9000_SLOTS_DESC * 2; 1035 ngep->nge_split = NGE_SPLIT_256; 1036 } else if (ngep->lowmem_mode != 0) { 1037 ngep->default_mtu = ETHERMTU; 1038 ngep->buf_size = NGE_STD_BUFSZ; 1039 ngep->tx_desc = NGE_SEND_LOWMEM_SLOTS_DESC; 1040 ngep->rx_desc = NGE_RECV_LOWMEM_SLOTS_DESC; 1041 ngep->rx_buf = NGE_RECV_LOWMEM_SLOTS_DESC * 2; 1042 ngep->nge_split = NGE_SPLIT_32; 1043 } else { 1044 ngep->default_mtu = ETHERMTU; 1045 ngep->buf_size = NGE_STD_BUFSZ; 1046 ngep->tx_desc = dev_param_p->tx_desc_num; 1047 ngep->rx_desc = dev_param_p->rx_desc_num; 1048 ngep->rx_buf = dev_param_p->rx_desc_num * 2; 1049 ngep->nge_split = dev_param_p->nge_split; 1050 } 1051 1052 nge_check_desc_prop(ngep); 1053 } 1054 1055 1056 static int 1057 nge_reset_dev(nge_t *ngep) 1058 { 1059 int err; 1060 nge_mul_addr1 maddr1; 1061 nge_sw_statistics_t *sw_stp; 1062 sw_stp = &ngep->statistics.sw_statistics; 1063 send_ring_t *srp = ngep->send; 1064 1065 ASSERT(mutex_owned(ngep->genlock)); 1066 mutex_enter(srp->tc_lock); 1067 mutex_enter(srp->tx_lock); 1068 1069 nge_tx_recycle_all(ngep); 1070 err = nge_reinit_ring(ngep); 1071 if (err == DDI_FAILURE) { 1072 mutex_exit(srp->tx_lock); 1073 mutex_exit(srp->tc_lock); 1074 return (err); 1075 } 1076 err = nge_chip_reset(ngep); 1077 /* 1078 * Clear the Multicast mac address table 1079 */ 1080 nge_reg_put32(ngep, NGE_MUL_ADDR0, 0); 1081 maddr1.addr_val = nge_reg_get32(ngep, NGE_MUL_ADDR1); 1082 maddr1.addr_bits.addr = 0; 1083 nge_reg_put32(ngep, NGE_MUL_ADDR1, maddr1.addr_val); 1084 1085 mutex_exit(srp->tx_lock); 1086 mutex_exit(srp->tc_lock); 1087 if (err == DDI_FAILURE) 1088 return (err); 1089 ngep->watchdog = 0; 1090 ngep->resched_needed = B_FALSE; 1091 ngep->promisc = B_FALSE; 1092 ngep->param_loop_mode = NGE_LOOP_NONE; 1093 ngep->factotum_flag = 0; 1094 ngep->resched_needed = 0; 1095 ngep->nge_mac_state = NGE_MAC_RESET; 1096 ngep->max_sdu = ngep->default_mtu + ETHER_HEAD_LEN + ETHERFCSL; 1097 ngep->max_sdu += VTAG_SIZE; 1098 ngep->rx_def = 0x16; 1099 1100 /* Clear the software statistics */ 1101 sw_stp->recv_count = 0; 1102 sw_stp->xmit_count = 0; 1103 sw_stp->rbytes = 0; 1104 sw_stp->obytes = 0; 1105 1106 return (DDI_SUCCESS); 1107 } 1108 1109 static void 1110 nge_m_stop(void *arg) 1111 { 1112 nge_t *ngep = arg; /* private device info */ 1113 1114 NGE_TRACE(("nge_m_stop($%p)", arg)); 1115 1116 /* 1117 * Just stop processing, then record new MAC state 1118 */ 1119 mutex_enter(ngep->genlock); 1120 /* If suspended, the adapter is already stopped, just return. */ 1121 if (ngep->suspended) { 1122 ASSERT(ngep->nge_mac_state == NGE_MAC_STOPPED); 1123 mutex_exit(ngep->genlock); 1124 return; 1125 } 1126 rw_enter(ngep->rwlock, RW_WRITER); 1127 1128 (void) nge_chip_stop(ngep, B_FALSE); 1129 ngep->nge_mac_state = NGE_MAC_STOPPED; 1130 1131 /* Recycle all the TX BD */ 1132 nge_tx_recycle_all(ngep); 1133 nge_fini_rings(ngep); 1134 nge_free_bufs(ngep); 1135 1136 NGE_DEBUG(("nge_m_stop($%p) done", arg)); 1137 1138 rw_exit(ngep->rwlock); 1139 mutex_exit(ngep->genlock); 1140 } 1141 1142 static int 1143 nge_m_start(void *arg) 1144 { 1145 int err; 1146 nge_t *ngep = arg; 1147 1148 NGE_TRACE(("nge_m_start($%p)", arg)); 1149 1150 /* 1151 * Start processing and record new MAC state 1152 */ 1153 mutex_enter(ngep->genlock); 1154 /* 1155 * If suspended, don't start, as the resume processing 1156 * will recall this function with the suspended flag off. 1157 */ 1158 if (ngep->suspended) { 1159 mutex_exit(ngep->genlock); 1160 return (EIO); 1161 } 1162 rw_enter(ngep->rwlock, RW_WRITER); 1163 err = nge_alloc_bufs(ngep); 1164 if (err != DDI_SUCCESS) { 1165 nge_problem(ngep, "nge_m_start: DMA buffer allocation failed"); 1166 goto finish; 1167 } 1168 err = nge_init_rings(ngep); 1169 if (err != DDI_SUCCESS) { 1170 nge_free_bufs(ngep); 1171 nge_problem(ngep, "nge_init_rings() failed,err=%x", err); 1172 goto finish; 1173 } 1174 err = nge_restart(ngep); 1175 1176 NGE_DEBUG(("nge_m_start($%p) done", arg)); 1177 finish: 1178 rw_exit(ngep->rwlock); 1179 mutex_exit(ngep->genlock); 1180 1181 return (err == DDI_SUCCESS ? 0 : EIO); 1182 } 1183 1184 static int 1185 nge_m_unicst(void *arg, const uint8_t *macaddr) 1186 { 1187 nge_t *ngep = arg; 1188 1189 NGE_TRACE(("nge_m_unicst($%p)", arg)); 1190 /* 1191 * Remember the new current address in the driver state 1192 * Sync the chip's idea of the address too ... 1193 */ 1194 mutex_enter(ngep->genlock); 1195 1196 ethaddr_copy(macaddr, ngep->cur_uni_addr.addr); 1197 ngep->cur_uni_addr.set = 1; 1198 1199 /* 1200 * If we are suspended, we want to quit now, and not update 1201 * the chip. Doing so might put it in a bad state, but the 1202 * resume will get the unicast address installed. 1203 */ 1204 if (ngep->suspended) { 1205 mutex_exit(ngep->genlock); 1206 return (DDI_SUCCESS); 1207 } 1208 nge_chip_sync(ngep); 1209 1210 NGE_DEBUG(("nge_m_unicst($%p) done", arg)); 1211 mutex_exit(ngep->genlock); 1212 1213 return (0); 1214 } 1215 1216 static int 1217 nge_m_promisc(void *arg, boolean_t on) 1218 { 1219 nge_t *ngep = arg; 1220 1221 NGE_TRACE(("nge_m_promisc($%p)", arg)); 1222 1223 /* 1224 * Store specified mode and pass to chip layer to update h/w 1225 */ 1226 mutex_enter(ngep->genlock); 1227 /* 1228 * If suspended, there is no need to do anything, even 1229 * recording the promiscuious mode is not neccessary, as 1230 * it won't be properly set on resume. Just return failing. 1231 */ 1232 if (ngep->suspended) { 1233 mutex_exit(ngep->genlock); 1234 return (DDI_FAILURE); 1235 } 1236 if (ngep->promisc == on) { 1237 mutex_exit(ngep->genlock); 1238 NGE_DEBUG(("nge_m_promisc($%p) done", arg)); 1239 return (0); 1240 } 1241 ngep->promisc = on; 1242 ngep->record_promisc = ngep->promisc; 1243 nge_chip_sync(ngep); 1244 NGE_DEBUG(("nge_m_promisc($%p) done", arg)); 1245 mutex_exit(ngep->genlock); 1246 1247 return (0); 1248 } 1249 1250 static void nge_mulparam(nge_t *ngep) 1251 { 1252 uint8_t number; 1253 ether_addr_t pand; 1254 ether_addr_t por; 1255 mul_item *plist; 1256 1257 for (number = 0; number < ETHERADDRL; number++) { 1258 pand[number] = 0x00; 1259 por[number] = 0x00; 1260 } 1261 for (plist = ngep->pcur_mulist; plist != NULL; plist = plist->next) { 1262 for (number = 0; number < ETHERADDRL; number++) { 1263 pand[number] &= plist->mul_addr[number]; 1264 por[number] |= plist->mul_addr[number]; 1265 } 1266 } 1267 for (number = 0; number < ETHERADDRL; number++) { 1268 ngep->cur_mul_addr.addr[number] 1269 = pand[number] & por[number]; 1270 ngep->cur_mul_mask.addr[number] 1271 = pand [number] | (~por[number]); 1272 } 1273 } 1274 static int 1275 nge_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 1276 { 1277 boolean_t update; 1278 boolean_t b_eq; 1279 nge_t *ngep = arg; 1280 mul_item *plist; 1281 mul_item *plist_prev; 1282 mul_item *pitem; 1283 1284 NGE_TRACE(("nge_m_multicst($%p, %s, %s)", arg, 1285 (add) ? "add" : "remove", ether_sprintf((void *)mca))); 1286 1287 update = B_FALSE; 1288 plist = plist_prev = NULL; 1289 mutex_enter(ngep->genlock); 1290 if (add) { 1291 if (ngep->pcur_mulist != NULL) { 1292 for (plist = ngep->pcur_mulist; plist != NULL; 1293 plist = plist->next) { 1294 b_eq = ether_eq(plist->mul_addr, mca); 1295 if (b_eq) { 1296 plist->ref_cnt++; 1297 break; 1298 } 1299 plist_prev = plist; 1300 } 1301 } 1302 1303 if (plist == NULL) { 1304 pitem = kmem_zalloc(sizeof (mul_item), KM_SLEEP); 1305 ether_copy(mca, pitem->mul_addr); 1306 pitem ->ref_cnt++; 1307 pitem ->next = NULL; 1308 if (plist_prev == NULL) 1309 ngep->pcur_mulist = pitem; 1310 else 1311 plist_prev->next = pitem; 1312 update = B_TRUE; 1313 } 1314 } else { 1315 if (ngep->pcur_mulist != NULL) { 1316 for (plist = ngep->pcur_mulist; plist != NULL; 1317 plist = plist->next) { 1318 b_eq = ether_eq(plist->mul_addr, mca); 1319 if (b_eq) { 1320 update = B_TRUE; 1321 break; 1322 } 1323 plist_prev = plist; 1324 } 1325 1326 if (update) { 1327 if ((plist_prev == NULL) && 1328 (plist->next == NULL)) 1329 ngep->pcur_mulist = NULL; 1330 else if ((plist_prev == NULL) && 1331 (plist->next != NULL)) 1332 ngep->pcur_mulist = plist->next; 1333 else 1334 plist_prev->next = plist->next; 1335 kmem_free(plist, sizeof (mul_item)); 1336 } 1337 } 1338 } 1339 1340 if (update && !ngep->suspended) { 1341 nge_mulparam(ngep); 1342 nge_chip_sync(ngep); 1343 } 1344 NGE_DEBUG(("nge_m_multicst($%p) done", arg)); 1345 mutex_exit(ngep->genlock); 1346 1347 return (0); 1348 } 1349 1350 static void 1351 nge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 1352 { 1353 int err; 1354 int cmd; 1355 nge_t *ngep = arg; 1356 struct iocblk *iocp; 1357 enum ioc_reply status; 1358 boolean_t need_privilege; 1359 1360 /* 1361 * If suspended, we might actually be able to do some of 1362 * these ioctls, but it is harder to make sure they occur 1363 * without actually putting the hardware in an undesireable 1364 * state. So just NAK it. 1365 */ 1366 mutex_enter(ngep->genlock); 1367 if (ngep->suspended) { 1368 miocnak(wq, mp, 0, EINVAL); 1369 mutex_exit(ngep->genlock); 1370 return; 1371 } 1372 mutex_exit(ngep->genlock); 1373 1374 /* 1375 * Validate the command before bothering with the mutex ... 1376 */ 1377 iocp = (struct iocblk *)mp->b_rptr; 1378 iocp->ioc_error = 0; 1379 need_privilege = B_TRUE; 1380 cmd = iocp->ioc_cmd; 1381 1382 NGE_DEBUG(("nge_m_ioctl: cmd 0x%x", cmd)); 1383 switch (cmd) { 1384 default: 1385 NGE_LDB(NGE_DBG_BADIOC, 1386 ("nge_m_ioctl: unknown cmd 0x%x", cmd)); 1387 1388 miocnak(wq, mp, 0, EINVAL); 1389 return; 1390 1391 case NGE_MII_READ: 1392 case NGE_MII_WRITE: 1393 case NGE_SEE_READ: 1394 case NGE_SEE_WRITE: 1395 case NGE_DIAG: 1396 case NGE_PEEK: 1397 case NGE_POKE: 1398 case NGE_PHY_RESET: 1399 case NGE_SOFT_RESET: 1400 case NGE_HARD_RESET: 1401 break; 1402 1403 case LB_GET_INFO_SIZE: 1404 case LB_GET_INFO: 1405 case LB_GET_MODE: 1406 need_privilege = B_FALSE; 1407 break; 1408 case LB_SET_MODE: 1409 break; 1410 } 1411 1412 if (need_privilege) { 1413 /* 1414 * Check for specific net_config privilege. 1415 */ 1416 err = secpolicy_net_config(iocp->ioc_cr, B_FALSE); 1417 if (err != 0) { 1418 NGE_DEBUG(("nge_m_ioctl: rejected cmd 0x%x, err %d", 1419 cmd, err)); 1420 miocnak(wq, mp, 0, err); 1421 return; 1422 } 1423 } 1424 1425 mutex_enter(ngep->genlock); 1426 1427 switch (cmd) { 1428 default: 1429 _NOTE(NOTREACHED) 1430 status = IOC_INVAL; 1431 break; 1432 1433 case NGE_MII_READ: 1434 case NGE_MII_WRITE: 1435 case NGE_SEE_READ: 1436 case NGE_SEE_WRITE: 1437 case NGE_DIAG: 1438 case NGE_PEEK: 1439 case NGE_POKE: 1440 case NGE_PHY_RESET: 1441 case NGE_SOFT_RESET: 1442 case NGE_HARD_RESET: 1443 status = nge_chip_ioctl(ngep, mp, iocp); 1444 break; 1445 1446 case LB_GET_INFO_SIZE: 1447 case LB_GET_INFO: 1448 case LB_GET_MODE: 1449 case LB_SET_MODE: 1450 status = nge_loop_ioctl(ngep, mp, iocp); 1451 break; 1452 1453 } 1454 1455 /* 1456 * Do we need to reprogram the PHY and/or the MAC? 1457 * Do it now, while we still have the mutex. 1458 * 1459 * Note: update the PHY first, 'cos it controls the 1460 * speed/duplex parameters that the MAC code uses. 1461 */ 1462 1463 NGE_DEBUG(("nge_m_ioctl: cmd 0x%x status %d", cmd, status)); 1464 1465 switch (status) { 1466 case IOC_RESTART_REPLY: 1467 case IOC_RESTART_ACK: 1468 (*ngep->physops->phys_update)(ngep); 1469 nge_chip_sync(ngep); 1470 break; 1471 1472 default: 1473 break; 1474 } 1475 1476 mutex_exit(ngep->genlock); 1477 1478 /* 1479 * Finally, decide how to reply 1480 */ 1481 switch (status) { 1482 1483 default: 1484 case IOC_INVAL: 1485 miocnak(wq, mp, 0, iocp->ioc_error == 0 ? 1486 EINVAL : iocp->ioc_error); 1487 break; 1488 1489 case IOC_DONE: 1490 break; 1491 1492 case IOC_RESTART_ACK: 1493 case IOC_ACK: 1494 miocack(wq, mp, 0, 0); 1495 break; 1496 1497 case IOC_RESTART_REPLY: 1498 case IOC_REPLY: 1499 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1500 M_IOCACK : M_IOCNAK; 1501 qreply(wq, mp); 1502 break; 1503 } 1504 } 1505 1506 static boolean_t 1507 nge_param_locked(mac_prop_id_t pr_num) 1508 { 1509 /* 1510 * All adv_* parameters are locked (read-only) while 1511 * the device is in any sort of loopback mode ... 1512 */ 1513 switch (pr_num) { 1514 case MAC_PROP_ADV_1000FDX_CAP: 1515 case MAC_PROP_EN_1000FDX_CAP: 1516 case MAC_PROP_ADV_1000HDX_CAP: 1517 case MAC_PROP_EN_1000HDX_CAP: 1518 case MAC_PROP_ADV_100FDX_CAP: 1519 case MAC_PROP_EN_100FDX_CAP: 1520 case MAC_PROP_ADV_100HDX_CAP: 1521 case MAC_PROP_EN_100HDX_CAP: 1522 case MAC_PROP_ADV_10FDX_CAP: 1523 case MAC_PROP_EN_10FDX_CAP: 1524 case MAC_PROP_ADV_10HDX_CAP: 1525 case MAC_PROP_EN_10HDX_CAP: 1526 case MAC_PROP_AUTONEG: 1527 case MAC_PROP_FLOWCTRL: 1528 return (B_TRUE); 1529 } 1530 return (B_FALSE); 1531 } 1532 1533 /* 1534 * callback functions for set/get of properties 1535 */ 1536 static int 1537 nge_m_setprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 1538 uint_t pr_valsize, const void *pr_val) 1539 { 1540 nge_t *ngep = barg; 1541 int err = 0; 1542 uint32_t cur_mtu, new_mtu; 1543 link_flowctrl_t fl; 1544 1545 mutex_enter(ngep->genlock); 1546 if (ngep->param_loop_mode != NGE_LOOP_NONE && 1547 nge_param_locked(pr_num)) { 1548 /* 1549 * All adv_* parameters are locked (read-only) 1550 * while the device is in any sort of loopback mode. 1551 */ 1552 mutex_exit(ngep->genlock); 1553 return (EBUSY); 1554 } 1555 switch (pr_num) { 1556 case MAC_PROP_EN_1000FDX_CAP: 1557 ngep->param_en_1000fdx = *(uint8_t *)pr_val; 1558 ngep->param_adv_1000fdx = *(uint8_t *)pr_val; 1559 goto reprogram; 1560 case MAC_PROP_EN_100FDX_CAP: 1561 ngep->param_en_100fdx = *(uint8_t *)pr_val; 1562 ngep->param_adv_100fdx = *(uint8_t *)pr_val; 1563 goto reprogram; 1564 case MAC_PROP_EN_100HDX_CAP: 1565 ngep->param_en_100hdx = *(uint8_t *)pr_val; 1566 ngep->param_adv_100hdx = *(uint8_t *)pr_val; 1567 goto reprogram; 1568 case MAC_PROP_EN_10FDX_CAP: 1569 ngep->param_en_10fdx = *(uint8_t *)pr_val; 1570 ngep->param_adv_10fdx = *(uint8_t *)pr_val; 1571 goto reprogram; 1572 case MAC_PROP_EN_10HDX_CAP: 1573 ngep->param_en_10hdx = *(uint8_t *)pr_val; 1574 ngep->param_adv_10hdx = *(uint8_t *)pr_val; 1575 reprogram: 1576 (*ngep->physops->phys_update)(ngep); 1577 nge_chip_sync(ngep); 1578 break; 1579 1580 case MAC_PROP_ADV_1000FDX_CAP: 1581 case MAC_PROP_ADV_1000HDX_CAP: 1582 case MAC_PROP_ADV_100FDX_CAP: 1583 case MAC_PROP_ADV_100HDX_CAP: 1584 case MAC_PROP_ADV_10FDX_CAP: 1585 case MAC_PROP_ADV_10HDX_CAP: 1586 case MAC_PROP_STATUS: 1587 case MAC_PROP_SPEED: 1588 case MAC_PROP_DUPLEX: 1589 case MAC_PROP_EN_1000HDX_CAP: 1590 err = ENOTSUP; /* read-only prop. Can't set this */ 1591 break; 1592 case MAC_PROP_AUTONEG: 1593 ngep->param_adv_autoneg = *(uint8_t *)pr_val; 1594 (*ngep->physops->phys_update)(ngep); 1595 nge_chip_sync(ngep); 1596 break; 1597 case MAC_PROP_MTU: 1598 cur_mtu = ngep->default_mtu; 1599 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 1600 if (new_mtu == cur_mtu) { 1601 err = 0; 1602 break; 1603 } 1604 if (new_mtu < ETHERMTU || 1605 new_mtu > NGE_MAX_MTU) { 1606 err = EINVAL; 1607 break; 1608 } 1609 if ((new_mtu > ETHERMTU) && 1610 (!ngep->dev_spec_param.jumbo)) { 1611 err = EINVAL; 1612 break; 1613 } 1614 if (ngep->nge_mac_state == NGE_MAC_STARTED) { 1615 err = EBUSY; 1616 break; 1617 } 1618 1619 ngep->default_mtu = new_mtu; 1620 if (ngep->default_mtu > ETHERMTU && 1621 ngep->default_mtu <= NGE_MTU_2500) { 1622 ngep->buf_size = NGE_JB2500_BUFSZ; 1623 ngep->tx_desc = NGE_SEND_JB2500_SLOTS_DESC; 1624 ngep->rx_desc = NGE_RECV_JB2500_SLOTS_DESC; 1625 ngep->rx_buf = NGE_RECV_JB2500_SLOTS_DESC * 2; 1626 ngep->nge_split = NGE_SPLIT_256; 1627 } else if (ngep->default_mtu > NGE_MTU_2500 && 1628 ngep->default_mtu <= NGE_MTU_4500) { 1629 ngep->buf_size = NGE_JB4500_BUFSZ; 1630 ngep->tx_desc = NGE_SEND_JB4500_SLOTS_DESC; 1631 ngep->rx_desc = NGE_RECV_JB4500_SLOTS_DESC; 1632 ngep->rx_buf = NGE_RECV_JB4500_SLOTS_DESC * 2; 1633 ngep->nge_split = NGE_SPLIT_256; 1634 } else if (ngep->default_mtu > NGE_MTU_4500 && 1635 ngep->default_mtu <= NGE_MAX_MTU) { 1636 ngep->buf_size = NGE_JB9000_BUFSZ; 1637 ngep->tx_desc = NGE_SEND_JB9000_SLOTS_DESC; 1638 ngep->rx_desc = NGE_RECV_JB9000_SLOTS_DESC; 1639 ngep->rx_buf = NGE_RECV_JB9000_SLOTS_DESC * 2; 1640 ngep->nge_split = NGE_SPLIT_256; 1641 } else if (ngep->default_mtu > NGE_MAX_MTU) { 1642 ngep->default_mtu = NGE_MAX_MTU; 1643 ngep->buf_size = NGE_JB9000_BUFSZ; 1644 ngep->tx_desc = NGE_SEND_JB9000_SLOTS_DESC; 1645 ngep->rx_desc = NGE_RECV_JB9000_SLOTS_DESC; 1646 ngep->rx_buf = NGE_RECV_JB9000_SLOTS_DESC * 2; 1647 ngep->nge_split = NGE_SPLIT_256; 1648 } else if (ngep->lowmem_mode != 0) { 1649 ngep->default_mtu = ETHERMTU; 1650 ngep->buf_size = NGE_STD_BUFSZ; 1651 ngep->tx_desc = NGE_SEND_LOWMEM_SLOTS_DESC; 1652 ngep->rx_desc = NGE_RECV_LOWMEM_SLOTS_DESC; 1653 ngep->rx_buf = NGE_RECV_LOWMEM_SLOTS_DESC * 2; 1654 ngep->nge_split = NGE_SPLIT_32; 1655 } else { 1656 ngep->default_mtu = ETHERMTU; 1657 ngep->buf_size = NGE_STD_BUFSZ; 1658 ngep->tx_desc = 1659 ngep->dev_spec_param.tx_desc_num; 1660 ngep->rx_desc = 1661 ngep->dev_spec_param.rx_desc_num; 1662 ngep->rx_buf = 1663 ngep->dev_spec_param.rx_desc_num * 2; 1664 ngep->nge_split = 1665 ngep->dev_spec_param.nge_split; 1666 } 1667 1668 err = mac_maxsdu_update(ngep->mh, ngep->default_mtu); 1669 1670 break; 1671 case MAC_PROP_FLOWCTRL: 1672 bcopy(pr_val, &fl, sizeof (fl)); 1673 switch (fl) { 1674 default: 1675 err = ENOTSUP; 1676 break; 1677 case LINK_FLOWCTRL_NONE: 1678 ngep->param_adv_pause = 0; 1679 ngep->param_adv_asym_pause = 0; 1680 1681 ngep->param_link_rx_pause = B_FALSE; 1682 ngep->param_link_tx_pause = B_FALSE; 1683 break; 1684 case LINK_FLOWCTRL_RX: 1685 if (!((ngep->param_lp_pause == 0) && 1686 (ngep->param_lp_asym_pause == 1))) { 1687 err = EINVAL; 1688 break; 1689 } 1690 ngep->param_adv_pause = 1; 1691 ngep->param_adv_asym_pause = 1; 1692 1693 ngep->param_link_rx_pause = B_TRUE; 1694 ngep->param_link_tx_pause = B_FALSE; 1695 break; 1696 case LINK_FLOWCTRL_TX: 1697 if (!((ngep->param_lp_pause == 1) && 1698 (ngep->param_lp_asym_pause == 1))) { 1699 err = EINVAL; 1700 break; 1701 } 1702 ngep->param_adv_pause = 0; 1703 ngep->param_adv_asym_pause = 1; 1704 1705 ngep->param_link_rx_pause = B_FALSE; 1706 ngep->param_link_tx_pause = B_TRUE; 1707 break; 1708 case LINK_FLOWCTRL_BI: 1709 if (ngep->param_lp_pause != 1) { 1710 err = EINVAL; 1711 break; 1712 } 1713 ngep->param_adv_pause = 1; 1714 1715 ngep->param_link_rx_pause = B_TRUE; 1716 ngep->param_link_tx_pause = B_TRUE; 1717 break; 1718 } 1719 1720 if (err == 0) { 1721 (*ngep->physops->phys_update)(ngep); 1722 nge_chip_sync(ngep); 1723 } 1724 1725 break; 1726 case MAC_PROP_PRIVATE: 1727 err = nge_set_priv_prop(ngep, pr_name, pr_valsize, 1728 pr_val); 1729 if (err == 0) { 1730 (*ngep->physops->phys_update)(ngep); 1731 nge_chip_sync(ngep); 1732 } 1733 break; 1734 default: 1735 err = ENOTSUP; 1736 } 1737 mutex_exit(ngep->genlock); 1738 return (err); 1739 } 1740 1741 static int 1742 nge_m_getprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 1743 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 1744 { 1745 nge_t *ngep = barg; 1746 int err = 0; 1747 link_flowctrl_t fl; 1748 uint64_t speed; 1749 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 1750 1751 if (pr_valsize == 0) 1752 return (EINVAL); 1753 1754 *perm = MAC_PROP_PERM_RW; 1755 1756 bzero(pr_val, pr_valsize); 1757 1758 switch (pr_num) { 1759 case MAC_PROP_DUPLEX: 1760 *perm = MAC_PROP_PERM_READ; 1761 if (pr_valsize >= sizeof (link_duplex_t)) { 1762 bcopy(&ngep->param_link_duplex, pr_val, 1763 sizeof (link_duplex_t)); 1764 } else 1765 err = EINVAL; 1766 break; 1767 case MAC_PROP_SPEED: 1768 *perm = MAC_PROP_PERM_READ; 1769 if (pr_valsize >= sizeof (uint64_t)) { 1770 speed = ngep->param_link_speed * 1000000ull; 1771 bcopy(&speed, pr_val, sizeof (speed)); 1772 } else 1773 err = EINVAL; 1774 break; 1775 case MAC_PROP_AUTONEG: 1776 if (is_default) { 1777 *(uint8_t *)pr_val = 1; 1778 } else { 1779 *(uint8_t *)pr_val = ngep->param_adv_autoneg; 1780 } 1781 break; 1782 case MAC_PROP_FLOWCTRL: 1783 if (pr_valsize >= sizeof (link_flowctrl_t)) { 1784 if (pr_flags & MAC_PROP_DEFAULT) { 1785 fl = LINK_FLOWCTRL_BI; 1786 bcopy(&fl, pr_val, sizeof (fl)); 1787 break; 1788 } 1789 if (ngep->param_link_rx_pause && 1790 !ngep->param_link_tx_pause) 1791 fl = LINK_FLOWCTRL_RX; 1792 1793 if (!ngep->param_link_rx_pause && 1794 !ngep->param_link_tx_pause) 1795 fl = LINK_FLOWCTRL_NONE; 1796 1797 if (!ngep->param_link_rx_pause && 1798 ngep->param_link_tx_pause) 1799 fl = LINK_FLOWCTRL_TX; 1800 1801 if (ngep->param_link_rx_pause && 1802 ngep->param_link_tx_pause) 1803 fl = LINK_FLOWCTRL_BI; 1804 bcopy(&fl, pr_val, sizeof (fl)); 1805 } else 1806 err = EINVAL; 1807 break; 1808 case MAC_PROP_ADV_1000FDX_CAP: 1809 *perm = MAC_PROP_PERM_READ; 1810 if (is_default) { 1811 *(uint8_t *)pr_val = 1; 1812 } else { 1813 *(uint8_t *)pr_val = ngep->param_adv_1000fdx; 1814 } 1815 break; 1816 case MAC_PROP_EN_1000FDX_CAP: 1817 if (is_default) { 1818 *(uint8_t *)pr_val = 1; 1819 } else { 1820 *(uint8_t *)pr_val = ngep->param_en_1000fdx; 1821 } 1822 break; 1823 case MAC_PROP_ADV_1000HDX_CAP: 1824 *perm = MAC_PROP_PERM_READ; 1825 if (is_default) { 1826 *(uint8_t *)pr_val = 0; 1827 } else { 1828 *(uint8_t *)pr_val = ngep->param_adv_1000hdx; 1829 } 1830 break; 1831 case MAC_PROP_EN_1000HDX_CAP: 1832 *perm = MAC_PROP_PERM_READ; 1833 if (is_default) { 1834 *(uint8_t *)pr_val = 0; 1835 } else { 1836 *(uint8_t *)pr_val = ngep->param_en_1000hdx; 1837 } 1838 break; 1839 case MAC_PROP_ADV_100FDX_CAP: 1840 *perm = MAC_PROP_PERM_READ; 1841 if (is_default) { 1842 *(uint8_t *)pr_val = 1; 1843 } else { 1844 *(uint8_t *)pr_val = ngep->param_adv_100fdx; 1845 } 1846 break; 1847 case MAC_PROP_EN_100FDX_CAP: 1848 if (is_default) { 1849 *(uint8_t *)pr_val = 1; 1850 } else { 1851 *(uint8_t *)pr_val = ngep->param_en_100fdx; 1852 } 1853 break; 1854 case MAC_PROP_ADV_100HDX_CAP: 1855 *perm = MAC_PROP_PERM_READ; 1856 if (is_default) { 1857 *(uint8_t *)pr_val = 1; 1858 } else { 1859 *(uint8_t *)pr_val = ngep->param_adv_100hdx; 1860 } 1861 break; 1862 case MAC_PROP_EN_100HDX_CAP: 1863 if (is_default) { 1864 *(uint8_t *)pr_val = 1; 1865 } else { 1866 *(uint8_t *)pr_val = ngep->param_en_100hdx; 1867 } 1868 break; 1869 case MAC_PROP_ADV_10FDX_CAP: 1870 *perm = MAC_PROP_PERM_READ; 1871 if (is_default) { 1872 *(uint8_t *)pr_val = 1; 1873 } else { 1874 *(uint8_t *)pr_val = ngep->param_adv_10fdx; 1875 } 1876 break; 1877 case MAC_PROP_EN_10FDX_CAP: 1878 if (is_default) { 1879 *(uint8_t *)pr_val = 1; 1880 } else { 1881 *(uint8_t *)pr_val = ngep->param_en_10fdx; 1882 } 1883 break; 1884 case MAC_PROP_ADV_10HDX_CAP: 1885 *perm = MAC_PROP_PERM_READ; 1886 if (is_default) { 1887 *(uint8_t *)pr_val = 1; 1888 } else { 1889 *(uint8_t *)pr_val = ngep->param_adv_10hdx; 1890 } 1891 break; 1892 case MAC_PROP_EN_10HDX_CAP: 1893 if (is_default) { 1894 *(uint8_t *)pr_val = 1; 1895 } else { 1896 *(uint8_t *)pr_val = ngep->param_en_10hdx; 1897 } 1898 break; 1899 case MAC_PROP_ADV_100T4_CAP: 1900 case MAC_PROP_EN_100T4_CAP: 1901 *perm = MAC_PROP_PERM_READ; 1902 *(uint8_t *)pr_val = 0; 1903 break; 1904 case MAC_PROP_PRIVATE: 1905 err = nge_get_priv_prop(ngep, pr_name, pr_flags, 1906 pr_valsize, pr_val); 1907 break; 1908 default: 1909 err = ENOTSUP; 1910 } 1911 return (err); 1912 } 1913 1914 /* ARGSUSED */ 1915 static int 1916 nge_set_priv_prop(nge_t *ngep, const char *pr_name, uint_t pr_valsize, 1917 const void *pr_val) 1918 { 1919 int err = 0; 1920 long result; 1921 1922 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 1923 if (pr_val == NULL) { 1924 err = EINVAL; 1925 return (err); 1926 } 1927 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1928 if (result < 0 || result > NGE_MAX_SDU) { 1929 err = EINVAL; 1930 } else { 1931 ngep->param_txbcopy_threshold = (uint32_t)result; 1932 goto reprogram; 1933 } 1934 return (err); 1935 } 1936 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 1937 if (pr_val == NULL) { 1938 err = EINVAL; 1939 return (err); 1940 } 1941 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1942 if (result < 0 || result > NGE_MAX_SDU) { 1943 err = EINVAL; 1944 } else { 1945 ngep->param_rxbcopy_threshold = (uint32_t)result; 1946 goto reprogram; 1947 } 1948 return (err); 1949 } 1950 if (strcmp(pr_name, "_recv_max_packet") == 0) { 1951 if (pr_val == NULL) { 1952 err = EINVAL; 1953 return (err); 1954 } 1955 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1956 if (result < 0 || result > NGE_RECV_SLOTS_DESC_1024) { 1957 err = EINVAL; 1958 } else { 1959 ngep->param_recv_max_packet = (uint32_t)result; 1960 goto reprogram; 1961 } 1962 return (err); 1963 } 1964 if (strcmp(pr_name, "_poll_quiet_time") == 0) { 1965 if (pr_val == NULL) { 1966 err = EINVAL; 1967 return (err); 1968 } 1969 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1970 if (result < 0 || result > 10000) { 1971 err = EINVAL; 1972 } else { 1973 ngep->param_poll_quiet_time = (uint32_t)result; 1974 goto reprogram; 1975 } 1976 return (err); 1977 } 1978 if (strcmp(pr_name, "_poll_busy_time") == 0) { 1979 if (pr_val == NULL) { 1980 err = EINVAL; 1981 return (err); 1982 } 1983 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1984 if (result < 0 || result > 10000) { 1985 err = EINVAL; 1986 } else { 1987 ngep->param_poll_busy_time = (uint32_t)result; 1988 goto reprogram; 1989 } 1990 return (err); 1991 } 1992 if (strcmp(pr_name, "_rx_intr_hwater") == 0) { 1993 if (pr_val == NULL) { 1994 err = EINVAL; 1995 return (err); 1996 } 1997 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 1998 if (result < 0 || result > NGE_RECV_SLOTS_DESC_1024) { 1999 err = EINVAL; 2000 } else { 2001 ngep->param_rx_intr_hwater = (uint32_t)result; 2002 goto reprogram; 2003 } 2004 return (err); 2005 } 2006 if (strcmp(pr_name, "_rx_intr_lwater") == 0) { 2007 if (pr_val == NULL) { 2008 err = EINVAL; 2009 return (err); 2010 } 2011 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2012 if (result < 0 || result > NGE_RECV_SLOTS_DESC_1024) { 2013 err = EINVAL; 2014 } else { 2015 ngep->param_rx_intr_lwater = (uint32_t)result; 2016 goto reprogram; 2017 } 2018 return (err); 2019 } 2020 if (strcmp(pr_name, "_tx_n_intr") == 0) { 2021 if (pr_val == NULL) { 2022 err = EINVAL; 2023 return (err); 2024 } 2025 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2026 if (result < 1 || result > 10000) { 2027 err = EINVAL; 2028 } else { 2029 ngep->param_tx_n_intr = (uint32_t)result; 2030 goto reprogram; 2031 } 2032 return (err); 2033 } 2034 2035 err = ENOTSUP; 2036 return (err); 2037 2038 reprogram: 2039 if (err == 0) { 2040 (*ngep->physops->phys_update)(ngep); 2041 nge_chip_sync(ngep); 2042 } 2043 2044 return (err); 2045 } 2046 2047 static int 2048 nge_get_priv_prop(nge_t *ngep, const char *pr_name, uint_t pr_flags, 2049 uint_t pr_valsize, void *pr_val) 2050 { 2051 int err = ENOTSUP; 2052 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 2053 int value; 2054 2055 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 2056 value = (is_default ? 1 : ngep->param_adv_pause); 2057 err = 0; 2058 goto done; 2059 } 2060 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 2061 value = (is_default ? 1 : ngep->param_adv_asym_pause); 2062 err = 0; 2063 goto done; 2064 } 2065 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 2066 value = (is_default ? NGE_TX_COPY_SIZE : 2067 ngep->param_txbcopy_threshold); 2068 err = 0; 2069 goto done; 2070 } 2071 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 2072 value = (is_default ? NGE_RX_COPY_SIZE : 2073 ngep->param_rxbcopy_threshold); 2074 err = 0; 2075 goto done; 2076 } 2077 if (strcmp(pr_name, "_recv_max_packet") == 0) { 2078 value = (is_default ? 128 : ngep->param_recv_max_packet); 2079 err = 0; 2080 goto done; 2081 } 2082 if (strcmp(pr_name, "_poll_quiet_time") == 0) { 2083 value = (is_default ? NGE_POLL_QUIET_TIME : 2084 ngep->param_poll_quiet_time); 2085 err = 0; 2086 goto done; 2087 } 2088 if (strcmp(pr_name, "_poll_busy_time") == 0) { 2089 value = (is_default ? NGE_POLL_BUSY_TIME : 2090 ngep->param_poll_busy_time); 2091 err = 0; 2092 goto done; 2093 } 2094 if (strcmp(pr_name, "_rx_intr_hwater") == 0) { 2095 value = (is_default ? 1 : ngep->param_rx_intr_hwater); 2096 err = 0; 2097 goto done; 2098 } 2099 if (strcmp(pr_name, "_rx_intr_lwater") == 0) { 2100 value = (is_default ? 8 : ngep->param_rx_intr_lwater); 2101 err = 0; 2102 goto done; 2103 } 2104 if (strcmp(pr_name, "_tx_n_intr") == 0) { 2105 value = (is_default ? NGE_TX_N_INTR : 2106 ngep->param_tx_n_intr); 2107 err = 0; 2108 goto done; 2109 } 2110 2111 done: 2112 if (err == 0) { 2113 (void) snprintf(pr_val, pr_valsize, "%d", value); 2114 } 2115 return (err); 2116 } 2117 2118 /* ARGSUSED */ 2119 static boolean_t 2120 nge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2121 { 2122 nge_t *ngep = arg; 2123 nge_dev_spec_param_t *dev_param_p; 2124 2125 dev_param_p = &ngep->dev_spec_param; 2126 2127 switch (cap) { 2128 case MAC_CAPAB_HCKSUM: { 2129 uint32_t *hcksum_txflags = cap_data; 2130 2131 if (dev_param_p->tx_hw_checksum) { 2132 *hcksum_txflags = dev_param_p->tx_hw_checksum; 2133 } else 2134 return (B_FALSE); 2135 break; 2136 } 2137 case MAC_CAPAB_POLL: 2138 /* 2139 * There's nothing for us to fill in, simply returning 2140 * B_TRUE, stating that we support polling is sufficient. 2141 */ 2142 break; 2143 default: 2144 return (B_FALSE); 2145 } 2146 return (B_TRUE); 2147 } 2148 2149 #undef NGE_DBG 2150 #define NGE_DBG NGE_DBG_INIT /* debug flag for this code */ 2151 int 2152 nge_restart(nge_t *ngep) 2153 { 2154 int err = 0; 2155 err = nge_reset_dev(ngep); 2156 /* write back the promisc setting */ 2157 ngep->promisc = ngep->record_promisc; 2158 nge_chip_sync(ngep); 2159 if (!err) 2160 err = nge_chip_start(ngep); 2161 2162 if (err) { 2163 ngep->nge_mac_state = NGE_MAC_STOPPED; 2164 return (DDI_FAILURE); 2165 } else { 2166 ngep->nge_mac_state = NGE_MAC_STARTED; 2167 return (DDI_SUCCESS); 2168 } 2169 } 2170 2171 void 2172 nge_wake_factotum(nge_t *ngep) 2173 { 2174 mutex_enter(ngep->softlock); 2175 if (ngep->factotum_flag == 0) { 2176 ngep->factotum_flag = 1; 2177 (void) ddi_intr_trigger_softint(ngep->factotum_hdl, NULL); 2178 } 2179 mutex_exit(ngep->softlock); 2180 } 2181 2182 /* 2183 * High-level cyclic handler 2184 * 2185 * This routine schedules a (low-level) softint callback to the 2186 * factotum. 2187 */ 2188 2189 static void 2190 nge_chip_cyclic(void *arg) 2191 { 2192 nge_t *ngep; 2193 2194 ngep = (nge_t *)arg; 2195 2196 switch (ngep->nge_chip_state) { 2197 default: 2198 return; 2199 2200 case NGE_CHIP_RUNNING: 2201 break; 2202 2203 case NGE_CHIP_FAULT: 2204 case NGE_CHIP_ERROR: 2205 break; 2206 } 2207 2208 nge_wake_factotum(ngep); 2209 } 2210 2211 static void 2212 nge_unattach(nge_t *ngep) 2213 { 2214 send_ring_t *srp; 2215 buff_ring_t *brp; 2216 2217 srp = ngep->send; 2218 brp = ngep->buff; 2219 NGE_TRACE(("nge_unattach($%p)", (void *)ngep)); 2220 2221 /* 2222 * Flag that no more activity may be initiated 2223 */ 2224 ngep->progress &= ~PROGRESS_READY; 2225 ngep->nge_mac_state = NGE_MAC_UNATTACH; 2226 2227 /* 2228 * Quiesce the PHY and MAC (leave it reset but still powered). 2229 * Clean up and free all NGE data structures 2230 */ 2231 if (ngep->periodic_id != NULL) { 2232 ddi_periodic_delete(ngep->periodic_id); 2233 ngep->periodic_id = NULL; 2234 } 2235 2236 if (ngep->progress & PROGRESS_KSTATS) 2237 nge_fini_kstats(ngep); 2238 2239 if (ngep->progress & PROGRESS_HWINT) { 2240 mutex_enter(ngep->genlock); 2241 nge_restore_mac_addr(ngep); 2242 (void) nge_chip_stop(ngep, B_FALSE); 2243 mutex_exit(ngep->genlock); 2244 } 2245 2246 if (ngep->progress & PROGRESS_SWINT) 2247 nge_rem_intrs(ngep); 2248 2249 if (ngep->progress & PROGRESS_FACTOTUM) 2250 (void) ddi_intr_remove_softint(ngep->factotum_hdl); 2251 2252 if (ngep->progress & PROGRESS_RESCHED) 2253 (void) ddi_intr_remove_softint(ngep->resched_hdl); 2254 2255 if (ngep->progress & PROGRESS_INTR) { 2256 mutex_destroy(srp->tx_lock); 2257 mutex_destroy(srp->tc_lock); 2258 mutex_destroy(&srp->dmah_lock); 2259 mutex_destroy(brp->recycle_lock); 2260 2261 mutex_destroy(ngep->genlock); 2262 mutex_destroy(ngep->softlock); 2263 rw_destroy(ngep->rwlock); 2264 } 2265 2266 if (ngep->progress & PROGRESS_REGS) 2267 ddi_regs_map_free(&ngep->io_handle); 2268 2269 if (ngep->progress & PROGRESS_CFG) 2270 pci_config_teardown(&ngep->cfg_handle); 2271 2272 ddi_remove_minor_node(ngep->devinfo, NULL); 2273 2274 kmem_free(ngep, sizeof (*ngep)); 2275 } 2276 2277 static int 2278 nge_resume(dev_info_t *devinfo) 2279 { 2280 nge_t *ngep; 2281 chip_info_t *infop; 2282 int err; 2283 2284 ASSERT(devinfo != NULL); 2285 2286 ngep = ddi_get_driver_private(devinfo); 2287 err = 0; 2288 2289 /* 2290 * If there are state inconsistancies, this is bad. Returning 2291 * DDI_FAILURE here will eventually cause the machine to panic, 2292 * so it is best done here so that there is a possibility of 2293 * debugging the problem. 2294 */ 2295 if (ngep == NULL) 2296 cmn_err(CE_PANIC, 2297 "nge: ngep returned from ddi_get_driver_private was NULL"); 2298 infop = (chip_info_t *)&ngep->chipinfo; 2299 2300 if (ngep->devinfo != devinfo) 2301 cmn_err(CE_PANIC, 2302 "nge: passed devinfo not the same as saved devinfo"); 2303 2304 mutex_enter(ngep->genlock); 2305 rw_enter(ngep->rwlock, RW_WRITER); 2306 2307 /* 2308 * Fetch the config space. Even though we have most of it cached, 2309 * some values *might* change across a suspend/resume. 2310 */ 2311 nge_chip_cfg_init(ngep, infop, B_FALSE); 2312 2313 /* 2314 * Only in one case, this conditional branch can be executed: the port 2315 * hasn't been plumbed. 2316 */ 2317 if (ngep->suspended == B_FALSE) { 2318 rw_exit(ngep->rwlock); 2319 mutex_exit(ngep->genlock); 2320 return (DDI_SUCCESS); 2321 } 2322 2323 nge_tx_recycle_all(ngep); 2324 err = nge_reinit_ring(ngep); 2325 if (!err) { 2326 err = nge_chip_reset(ngep); 2327 if (!err) 2328 err = nge_chip_start(ngep); 2329 } 2330 2331 if (err) { 2332 /* 2333 * We note the failure, but return success, as the 2334 * system is still usable without this controller. 2335 */ 2336 cmn_err(CE_WARN, "nge: resume: failed to restart controller"); 2337 } else { 2338 ngep->nge_mac_state = NGE_MAC_STARTED; 2339 } 2340 ngep->suspended = B_FALSE; 2341 2342 rw_exit(ngep->rwlock); 2343 mutex_exit(ngep->genlock); 2344 2345 return (DDI_SUCCESS); 2346 } 2347 2348 /* 2349 * attach(9E) -- Attach a device to the system 2350 * 2351 * Called once for each board successfully probed. 2352 */ 2353 static int 2354 nge_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 2355 { 2356 int err; 2357 int i; 2358 int instance; 2359 caddr_t regs; 2360 nge_t *ngep; 2361 chip_info_t *infop; 2362 mac_register_t *macp; 2363 2364 switch (cmd) { 2365 default: 2366 return (DDI_FAILURE); 2367 2368 case DDI_RESUME: 2369 return (nge_resume(devinfo)); 2370 2371 case DDI_ATTACH: 2372 break; 2373 } 2374 2375 ngep = kmem_zalloc(sizeof (*ngep), KM_SLEEP); 2376 instance = ddi_get_instance(devinfo); 2377 ddi_set_driver_private(devinfo, ngep); 2378 ngep->devinfo = devinfo; 2379 2380 (void) snprintf(ngep->ifname, sizeof (ngep->ifname), "%s%d", 2381 NGE_DRIVER_NAME, instance); 2382 err = pci_config_setup(devinfo, &ngep->cfg_handle); 2383 if (err != DDI_SUCCESS) { 2384 nge_problem(ngep, "nge_attach: pci_config_setup() failed"); 2385 goto attach_fail; 2386 } 2387 /* 2388 * param_txbcopy_threshold and param_rxbcopy_threshold are tx/rx bcopy 2389 * thresholds. Bounds: min 0, max NGE_MAX_SDU 2390 */ 2391 ngep->param_txbcopy_threshold = NGE_TX_COPY_SIZE; 2392 ngep->param_rxbcopy_threshold = NGE_RX_COPY_SIZE; 2393 2394 /* 2395 * param_recv_max_packet is max packet received per interupt. 2396 * Bounds: min 0, max NGE_RECV_SLOTS_DESC_1024 2397 */ 2398 ngep->param_recv_max_packet = 128; 2399 2400 /* 2401 * param_poll_quiet_time and param_poll_busy_time are quiet/busy time 2402 * switch from per packet interrupt to polling interrupt. 2403 * Bounds: min 0, max 10000 2404 */ 2405 ngep->param_poll_quiet_time = NGE_POLL_QUIET_TIME; 2406 ngep->param_poll_busy_time = NGE_POLL_BUSY_TIME; 2407 2408 /* 2409 * param_rx_intr_hwater/param_rx_intr_lwater: ackets received 2410 * to trigger the poll_quiet_time/poll_busy_time counter. 2411 * Bounds: min 0, max NGE_RECV_SLOTS_DESC_1024. 2412 */ 2413 ngep->param_rx_intr_hwater = 1; 2414 ngep->param_rx_intr_lwater = 8; 2415 2416 /* 2417 * param_tx_n_intr: Per N tx packets to do tx recycle in poll mode. 2418 * Bounds: min 1, max 10000. 2419 */ 2420 ngep->param_tx_n_intr = NGE_TX_N_INTR; 2421 2422 infop = (chip_info_t *)&ngep->chipinfo; 2423 nge_chip_cfg_init(ngep, infop, B_FALSE); 2424 nge_init_dev_spec_param(ngep); 2425 nge_get_props(ngep); 2426 ngep->progress |= PROGRESS_CFG; 2427 2428 err = ddi_regs_map_setup(devinfo, NGE_PCI_OPREGS_RNUMBER, 2429 ®s, 0, 0, &nge_reg_accattr, &ngep->io_handle); 2430 if (err != DDI_SUCCESS) { 2431 nge_problem(ngep, "nge_attach: ddi_regs_map_setup() failed"); 2432 goto attach_fail; 2433 } 2434 ngep->io_regs = regs; 2435 ngep->progress |= PROGRESS_REGS; 2436 2437 err = nge_register_intrs_and_init_locks(ngep); 2438 if (err != DDI_SUCCESS) { 2439 nge_problem(ngep, "nge_attach:" 2440 " register intrs and init locks failed"); 2441 goto attach_fail; 2442 } 2443 nge_init_ring_param_lock(ngep); 2444 ngep->progress |= PROGRESS_INTR; 2445 2446 mutex_enter(ngep->genlock); 2447 2448 /* 2449 * Initialise link state variables 2450 * Stop, reset & reinitialise the chip. 2451 * Initialise the (internal) PHY. 2452 */ 2453 nge_phys_init(ngep); 2454 err = nge_chip_reset(ngep); 2455 if (err != DDI_SUCCESS) { 2456 nge_problem(ngep, "nge_attach: nge_chip_reset() failed"); 2457 mutex_exit(ngep->genlock); 2458 goto attach_fail; 2459 } 2460 nge_chip_sync(ngep); 2461 2462 /* 2463 * Now that mutex locks are initialized, enable interrupts. 2464 */ 2465 if (ngep->intr_cap & DDI_INTR_FLAG_BLOCK) { 2466 /* Call ddi_intr_block_enable() for MSI interrupts */ 2467 (void) ddi_intr_block_enable(ngep->htable, 2468 ngep->intr_actual_cnt); 2469 } else { 2470 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 2471 for (i = 0; i < ngep->intr_actual_cnt; i++) { 2472 (void) ddi_intr_enable(ngep->htable[i]); 2473 } 2474 } 2475 2476 ngep->link_state = LINK_STATE_UNKNOWN; 2477 ngep->progress |= PROGRESS_HWINT; 2478 2479 /* 2480 * Register NDD-tweakable parameters 2481 */ 2482 if (nge_nd_init(ngep)) { 2483 nge_problem(ngep, "nge_attach: nge_nd_init() failed"); 2484 mutex_exit(ngep->genlock); 2485 goto attach_fail; 2486 } 2487 ngep->progress |= PROGRESS_NDD; 2488 2489 /* 2490 * Create & initialise named kstats 2491 */ 2492 nge_init_kstats(ngep, instance); 2493 ngep->progress |= PROGRESS_KSTATS; 2494 2495 mutex_exit(ngep->genlock); 2496 2497 if ((macp = mac_alloc(MAC_VERSION)) == NULL) 2498 goto attach_fail; 2499 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 2500 macp->m_driver = ngep; 2501 macp->m_dip = devinfo; 2502 macp->m_src_addr = infop->vendor_addr.addr; 2503 macp->m_callbacks = &nge_m_callbacks; 2504 macp->m_min_sdu = 0; 2505 macp->m_max_sdu = ngep->default_mtu; 2506 macp->m_margin = VTAG_SIZE; 2507 macp->m_priv_props = nge_priv_props; 2508 macp->m_priv_prop_count = NGE_MAX_PRIV_PROPS; 2509 /* 2510 * Finally, we're ready to register ourselves with the mac 2511 * interface; if this succeeds, we're all ready to start() 2512 */ 2513 err = mac_register(macp, &ngep->mh); 2514 mac_free(macp); 2515 if (err != 0) 2516 goto attach_fail; 2517 2518 /* 2519 * Register a periodical handler. 2520 * nge_chip_cyclic() is invoked in kernel context. 2521 */ 2522 ngep->periodic_id = ddi_periodic_add(nge_chip_cyclic, ngep, 2523 NGE_CYCLIC_PERIOD, DDI_IPL_0); 2524 2525 ngep->progress |= PROGRESS_READY; 2526 return (DDI_SUCCESS); 2527 2528 attach_fail: 2529 nge_unattach(ngep); 2530 return (DDI_FAILURE); 2531 } 2532 2533 static int 2534 nge_suspend(nge_t *ngep) 2535 { 2536 mutex_enter(ngep->genlock); 2537 rw_enter(ngep->rwlock, RW_WRITER); 2538 2539 /* if the port hasn't been plumbed, just return */ 2540 if (ngep->nge_mac_state != NGE_MAC_STARTED) { 2541 rw_exit(ngep->rwlock); 2542 mutex_exit(ngep->genlock); 2543 return (DDI_SUCCESS); 2544 } 2545 ngep->suspended = B_TRUE; 2546 (void) nge_chip_stop(ngep, B_FALSE); 2547 ngep->nge_mac_state = NGE_MAC_STOPPED; 2548 2549 rw_exit(ngep->rwlock); 2550 mutex_exit(ngep->genlock); 2551 return (DDI_SUCCESS); 2552 } 2553 2554 /* 2555 * detach(9E) -- Detach a device from the system 2556 */ 2557 static int 2558 nge_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 2559 { 2560 int i; 2561 nge_t *ngep; 2562 mul_item *p, *nextp; 2563 buff_ring_t *brp; 2564 2565 NGE_GTRACE(("nge_detach($%p, %d)", (void *)devinfo, cmd)); 2566 2567 ngep = ddi_get_driver_private(devinfo); 2568 brp = ngep->buff; 2569 2570 switch (cmd) { 2571 default: 2572 return (DDI_FAILURE); 2573 2574 case DDI_SUSPEND: 2575 /* 2576 * Stop the NIC 2577 * Note: This driver doesn't currently support WOL, but 2578 * should it in the future, it is important to 2579 * make sure the PHY remains powered so that the 2580 * wakeup packet can actually be recieved. 2581 */ 2582 return (nge_suspend(ngep)); 2583 2584 case DDI_DETACH: 2585 break; 2586 } 2587 2588 /* Try to wait all the buffer post to upper layer be released */ 2589 for (i = 0; i < 1000; i++) { 2590 if (brp->rx_hold == 0) 2591 break; 2592 drv_usecwait(1000); 2593 } 2594 2595 /* If there is any posted buffer, reject to detach */ 2596 if (brp->rx_hold != 0) 2597 return (DDI_FAILURE); 2598 2599 /* 2600 * Unregister from the GLD subsystem. This can fail, in 2601 * particular if there are DLPI style-2 streams still open - 2602 * in which case we just return failure without shutting 2603 * down chip operations. 2604 */ 2605 if (mac_unregister(ngep->mh) != DDI_SUCCESS) 2606 return (DDI_FAILURE); 2607 2608 /* 2609 * Recycle the multicast table. mac_unregister() should be called 2610 * before it to ensure the multicast table can be used even if 2611 * mac_unregister() fails. 2612 */ 2613 for (p = ngep->pcur_mulist; p != NULL; p = nextp) { 2614 nextp = p->next; 2615 kmem_free(p, sizeof (mul_item)); 2616 } 2617 ngep->pcur_mulist = NULL; 2618 2619 /* 2620 * All activity stopped, so we can clean up & exit 2621 */ 2622 nge_unattach(ngep); 2623 return (DDI_SUCCESS); 2624 } 2625 2626 /* 2627 * quiesce(9E) entry point. 2628 * 2629 * This function is called when the system is single-threaded at high 2630 * PIL with preemption disabled. Therefore, this function must not be 2631 * blocked. 2632 * 2633 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 2634 * DDI_FAILURE indicates an error condition and should almost never happen. 2635 */ 2636 static int 2637 nge_quiesce(dev_info_t *devinfo) 2638 { 2639 nge_t *ngep; 2640 2641 ngep = ddi_get_driver_private(devinfo); 2642 2643 if (ngep == NULL) 2644 return (DDI_FAILURE); 2645 2646 /* 2647 * Turn off debug tracing 2648 */ 2649 nge_debug = 0; 2650 ngep->debug = 0; 2651 2652 nge_restore_mac_addr(ngep); 2653 (void) nge_chip_stop(ngep, B_FALSE); 2654 2655 return (DDI_SUCCESS); 2656 } 2657 2658 2659 2660 /* 2661 * ========== Module Loading Data & Entry Points ========== 2662 */ 2663 2664 DDI_DEFINE_STREAM_OPS(nge_dev_ops, nulldev, nulldev, nge_attach, nge_detach, 2665 NULL, NULL, D_MP, NULL, nge_quiesce); 2666 2667 2668 static struct modldrv nge_modldrv = { 2669 &mod_driverops, /* Type of module. This one is a driver */ 2670 nge_ident, /* short description */ 2671 &nge_dev_ops /* driver specific ops */ 2672 }; 2673 2674 static struct modlinkage modlinkage = { 2675 MODREV_1, (void *)&nge_modldrv, NULL 2676 }; 2677 2678 2679 int 2680 _info(struct modinfo *modinfop) 2681 { 2682 return (mod_info(&modlinkage, modinfop)); 2683 } 2684 2685 int 2686 _init(void) 2687 { 2688 int status; 2689 2690 mac_init_ops(&nge_dev_ops, "nge"); 2691 status = mod_install(&modlinkage); 2692 if (status != DDI_SUCCESS) 2693 mac_fini_ops(&nge_dev_ops); 2694 else 2695 mutex_init(nge_log_mutex, NULL, MUTEX_DRIVER, NULL); 2696 2697 return (status); 2698 } 2699 2700 int 2701 _fini(void) 2702 { 2703 int status; 2704 2705 status = mod_remove(&modlinkage); 2706 if (status == DDI_SUCCESS) { 2707 mac_fini_ops(&nge_dev_ops); 2708 mutex_destroy(nge_log_mutex); 2709 } 2710 2711 return (status); 2712 } 2713 2714 /* 2715 * ============ Init MSI/Fixed/SoftInterrupt routines ============== 2716 */ 2717 2718 /* 2719 * Register interrupts and initialize each mutex and condition variables 2720 */ 2721 2722 static int 2723 nge_register_intrs_and_init_locks(nge_t *ngep) 2724 { 2725 int err; 2726 int intr_types; 2727 uint_t soft_prip; 2728 nge_msi_mask msi_mask; 2729 nge_msi_map0_vec map0_vec; 2730 nge_msi_map1_vec map1_vec; 2731 2732 /* 2733 * Add the softint handlers: 2734 * 2735 * Both of these handlers are used to avoid restrictions on the 2736 * context and/or mutexes required for some operations. In 2737 * particular, the hardware interrupt handler and its subfunctions 2738 * can detect a number of conditions that we don't want to handle 2739 * in that context or with that set of mutexes held. So, these 2740 * softints are triggered instead: 2741 * 2742 * the <resched> softint is triggered if if we have previously 2743 * had to refuse to send a packet because of resource shortage 2744 * (we've run out of transmit buffers), but the send completion 2745 * interrupt handler has now detected that more buffers have 2746 * become available. Its only purpose is to call gld_sched() 2747 * to retry the pending transmits (we're not allowed to hold 2748 * driver-defined mutexes across gld_sched()). 2749 * 2750 * the <factotum> is triggered if the h/w interrupt handler 2751 * sees the <link state changed> or <error> bits in the status 2752 * block. It's also triggered periodically to poll the link 2753 * state, just in case we aren't getting link status change 2754 * interrupts ... 2755 */ 2756 err = ddi_intr_add_softint(ngep->devinfo, &ngep->resched_hdl, 2757 DDI_INTR_SOFTPRI_MIN, nge_reschedule, (caddr_t)ngep); 2758 if (err != DDI_SUCCESS) { 2759 nge_problem(ngep, 2760 "nge_attach: add nge_reschedule softintr failed"); 2761 2762 return (DDI_FAILURE); 2763 } 2764 ngep->progress |= PROGRESS_RESCHED; 2765 err = ddi_intr_add_softint(ngep->devinfo, &ngep->factotum_hdl, 2766 DDI_INTR_SOFTPRI_MIN, nge_chip_factotum, (caddr_t)ngep); 2767 if (err != DDI_SUCCESS) { 2768 nge_problem(ngep, 2769 "nge_attach: add nge_chip_factotum softintr failed!"); 2770 2771 return (DDI_FAILURE); 2772 } 2773 if (ddi_intr_get_softint_pri(ngep->factotum_hdl, &soft_prip) 2774 != DDI_SUCCESS) { 2775 nge_problem(ngep, "nge_attach: get softintr priority failed\n"); 2776 2777 return (DDI_FAILURE); 2778 } 2779 ngep->soft_pri = soft_prip; 2780 2781 ngep->progress |= PROGRESS_FACTOTUM; 2782 /* Get supported interrupt types */ 2783 if (ddi_intr_get_supported_types(ngep->devinfo, &intr_types) 2784 != DDI_SUCCESS) { 2785 nge_error(ngep, "ddi_intr_get_supported_types failed\n"); 2786 2787 return (DDI_FAILURE); 2788 } 2789 2790 NGE_DEBUG(("ddi_intr_get_supported_types() returned: %x", 2791 intr_types)); 2792 2793 if ((intr_types & DDI_INTR_TYPE_MSI) && nge_enable_msi) { 2794 2795 /* MSI Configurations for mcp55 chipset */ 2796 if (ngep->chipinfo.device == DEVICE_ID_MCP55_373 || 2797 ngep->chipinfo.device == DEVICE_ID_MCP55_372) { 2798 2799 2800 /* Enable the 8 vectors */ 2801 msi_mask.msi_mask_val = 2802 nge_reg_get32(ngep, NGE_MSI_MASK); 2803 msi_mask.msi_msk_bits.vec0 = NGE_SET; 2804 msi_mask.msi_msk_bits.vec1 = NGE_SET; 2805 msi_mask.msi_msk_bits.vec2 = NGE_SET; 2806 msi_mask.msi_msk_bits.vec3 = NGE_SET; 2807 msi_mask.msi_msk_bits.vec4 = NGE_SET; 2808 msi_mask.msi_msk_bits.vec5 = NGE_SET; 2809 msi_mask.msi_msk_bits.vec6 = NGE_SET; 2810 msi_mask.msi_msk_bits.vec7 = NGE_SET; 2811 nge_reg_put32(ngep, NGE_MSI_MASK, 2812 msi_mask.msi_mask_val); 2813 2814 /* 2815 * Remapping the MSI MAP0 and MAP1. MCP55 2816 * is default mapping all the interrupt to 0 vector. 2817 * Software needs to remapping this. 2818 * This mapping is same as CK804. 2819 */ 2820 map0_vec.msi_map0_val = 2821 nge_reg_get32(ngep, NGE_MSI_MAP0); 2822 map1_vec.msi_map1_val = 2823 nge_reg_get32(ngep, NGE_MSI_MAP1); 2824 map0_vec.vecs_bits.reint_vec = 0; 2825 map0_vec.vecs_bits.rcint_vec = 0; 2826 map0_vec.vecs_bits.miss_vec = 3; 2827 map0_vec.vecs_bits.teint_vec = 5; 2828 map0_vec.vecs_bits.tcint_vec = 5; 2829 map0_vec.vecs_bits.stint_vec = 2; 2830 map0_vec.vecs_bits.mint_vec = 6; 2831 map0_vec.vecs_bits.rfint_vec = 0; 2832 map1_vec.vecs_bits.tfint_vec = 5; 2833 map1_vec.vecs_bits.feint_vec = 6; 2834 map1_vec.vecs_bits.resv8_11 = 3; 2835 map1_vec.vecs_bits.resv12_15 = 1; 2836 map1_vec.vecs_bits.resv16_19 = 0; 2837 map1_vec.vecs_bits.resv20_23 = 7; 2838 map1_vec.vecs_bits.resv24_31 = 0xff; 2839 nge_reg_put32(ngep, NGE_MSI_MAP0, 2840 map0_vec.msi_map0_val); 2841 nge_reg_put32(ngep, NGE_MSI_MAP1, 2842 map1_vec.msi_map1_val); 2843 } 2844 if (nge_add_intrs(ngep, DDI_INTR_TYPE_MSI) != DDI_SUCCESS) { 2845 NGE_DEBUG(("MSI registration failed, " 2846 "trying FIXED interrupt type\n")); 2847 } else { 2848 nge_log(ngep, "Using MSI interrupt type\n"); 2849 2850 ngep->intr_type = DDI_INTR_TYPE_MSI; 2851 ngep->progress |= PROGRESS_SWINT; 2852 } 2853 } 2854 2855 if (!(ngep->progress & PROGRESS_SWINT) && 2856 (intr_types & DDI_INTR_TYPE_FIXED)) { 2857 if (nge_add_intrs(ngep, DDI_INTR_TYPE_FIXED) != DDI_SUCCESS) { 2858 nge_error(ngep, "FIXED interrupt " 2859 "registration failed\n"); 2860 2861 return (DDI_FAILURE); 2862 } 2863 2864 nge_log(ngep, "Using FIXED interrupt type\n"); 2865 2866 ngep->intr_type = DDI_INTR_TYPE_FIXED; 2867 ngep->progress |= PROGRESS_SWINT; 2868 } 2869 2870 2871 if (!(ngep->progress & PROGRESS_SWINT)) { 2872 nge_error(ngep, "No interrupts registered\n"); 2873 2874 return (DDI_FAILURE); 2875 } 2876 mutex_init(ngep->genlock, NULL, MUTEX_DRIVER, 2877 DDI_INTR_PRI(ngep->intr_pri)); 2878 mutex_init(ngep->softlock, NULL, MUTEX_DRIVER, 2879 DDI_INTR_PRI(ngep->soft_pri)); 2880 rw_init(ngep->rwlock, NULL, RW_DRIVER, 2881 DDI_INTR_PRI(ngep->intr_pri)); 2882 2883 return (DDI_SUCCESS); 2884 } 2885 2886 /* 2887 * nge_add_intrs: 2888 * 2889 * Register FIXED or MSI interrupts. 2890 */ 2891 static int 2892 nge_add_intrs(nge_t *ngep, int intr_type) 2893 { 2894 dev_info_t *dip = ngep->devinfo; 2895 int avail, actual, intr_size, count = 0; 2896 int i, flag, ret; 2897 2898 NGE_DEBUG(("nge_add_intrs: interrupt type 0x%x\n", intr_type)); 2899 2900 /* Get number of interrupts */ 2901 ret = ddi_intr_get_nintrs(dip, intr_type, &count); 2902 if ((ret != DDI_SUCCESS) || (count == 0)) { 2903 nge_error(ngep, "ddi_intr_get_nintrs() failure, ret: %d, " 2904 "count: %d", ret, count); 2905 2906 return (DDI_FAILURE); 2907 } 2908 2909 /* Get number of available interrupts */ 2910 ret = ddi_intr_get_navail(dip, intr_type, &avail); 2911 if ((ret != DDI_SUCCESS) || (avail == 0)) { 2912 nge_error(ngep, "ddi_intr_get_navail() failure, " 2913 "ret: %d, avail: %d\n", ret, avail); 2914 2915 return (DDI_FAILURE); 2916 } 2917 2918 if (avail < count) { 2919 NGE_DEBUG(("nitrs() returned %d, navail returned %d\n", 2920 count, avail)); 2921 } 2922 flag = DDI_INTR_ALLOC_NORMAL; 2923 2924 /* Allocate an array of interrupt handles */ 2925 intr_size = count * sizeof (ddi_intr_handle_t); 2926 ngep->htable = kmem_alloc(intr_size, KM_SLEEP); 2927 2928 /* Call ddi_intr_alloc() */ 2929 ret = ddi_intr_alloc(dip, ngep->htable, intr_type, 0, 2930 count, &actual, flag); 2931 2932 if ((ret != DDI_SUCCESS) || (actual == 0)) { 2933 nge_error(ngep, "ddi_intr_alloc() failed %d\n", ret); 2934 2935 kmem_free(ngep->htable, intr_size); 2936 return (DDI_FAILURE); 2937 } 2938 2939 if (actual < count) { 2940 NGE_DEBUG(("Requested: %d, Received: %d\n", 2941 count, actual)); 2942 } 2943 2944 ngep->intr_actual_cnt = actual; 2945 ngep->intr_req_cnt = count; 2946 2947 /* 2948 * Get priority for first msi, assume remaining are all the same 2949 */ 2950 if ((ret = ddi_intr_get_pri(ngep->htable[0], &ngep->intr_pri)) != 2951 DDI_SUCCESS) { 2952 nge_error(ngep, "ddi_intr_get_pri() failed %d\n", ret); 2953 2954 /* Free already allocated intr */ 2955 for (i = 0; i < actual; i++) { 2956 (void) ddi_intr_free(ngep->htable[i]); 2957 } 2958 2959 kmem_free(ngep->htable, intr_size); 2960 2961 return (DDI_FAILURE); 2962 } 2963 /* Test for high level mutex */ 2964 if (ngep->intr_pri >= ddi_intr_get_hilevel_pri()) { 2965 nge_error(ngep, "nge_add_intrs:" 2966 "Hi level interrupt not supported"); 2967 2968 for (i = 0; i < actual; i++) 2969 (void) ddi_intr_free(ngep->htable[i]); 2970 2971 kmem_free(ngep->htable, intr_size); 2972 2973 return (DDI_FAILURE); 2974 } 2975 2976 2977 /* Call ddi_intr_add_handler() */ 2978 for (i = 0; i < actual; i++) { 2979 if ((ret = ddi_intr_add_handler(ngep->htable[i], nge_chip_intr, 2980 (caddr_t)ngep, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 2981 nge_error(ngep, "ddi_intr_add_handler() " 2982 "failed %d\n", ret); 2983 2984 /* Free already allocated intr */ 2985 for (i = 0; i < actual; i++) { 2986 (void) ddi_intr_free(ngep->htable[i]); 2987 } 2988 2989 kmem_free(ngep->htable, intr_size); 2990 2991 return (DDI_FAILURE); 2992 } 2993 } 2994 2995 if ((ret = ddi_intr_get_cap(ngep->htable[0], &ngep->intr_cap)) 2996 != DDI_SUCCESS) { 2997 nge_error(ngep, "ddi_intr_get_cap() failed %d\n", ret); 2998 2999 for (i = 0; i < actual; i++) { 3000 (void) ddi_intr_remove_handler(ngep->htable[i]); 3001 (void) ddi_intr_free(ngep->htable[i]); 3002 } 3003 3004 kmem_free(ngep->htable, intr_size); 3005 3006 return (DDI_FAILURE); 3007 } 3008 3009 return (DDI_SUCCESS); 3010 } 3011 3012 /* 3013 * nge_rem_intrs: 3014 * 3015 * Unregister FIXED or MSI interrupts 3016 */ 3017 static void 3018 nge_rem_intrs(nge_t *ngep) 3019 { 3020 int i; 3021 3022 NGE_DEBUG(("nge_rem_intrs\n")); 3023 3024 /* Disable all interrupts */ 3025 if (ngep->intr_cap & DDI_INTR_FLAG_BLOCK) { 3026 /* Call ddi_intr_block_disable() */ 3027 (void) ddi_intr_block_disable(ngep->htable, 3028 ngep->intr_actual_cnt); 3029 } else { 3030 for (i = 0; i < ngep->intr_actual_cnt; i++) { 3031 (void) ddi_intr_disable(ngep->htable[i]); 3032 } 3033 } 3034 3035 /* Call ddi_intr_remove_handler() */ 3036 for (i = 0; i < ngep->intr_actual_cnt; i++) { 3037 (void) ddi_intr_remove_handler(ngep->htable[i]); 3038 (void) ddi_intr_free(ngep->htable[i]); 3039 } 3040 3041 kmem_free(ngep->htable, 3042 ngep->intr_req_cnt * sizeof (ddi_intr_handle_t)); 3043 } 3044