1 /* 2 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * This file may contain confidential information of Nvidia 8 * and should not be distributed in source form without approval 9 * from Sun Legal. 10 */ 11 12 #pragma ident "%Z%%M% %I% %E% SMI" 13 14 #include "nge.h" 15 static uint32_t nge_watchdog_count = 1 << 29; 16 extern boolean_t nge_enable_msi; 17 static void nge_sync_mac_modes(nge_t *); 18 19 #undef NGE_DBG 20 #define NGE_DBG NGE_DBG_CHIP 21 22 /* 23 * Operating register get/set access routines 24 */ 25 uint8_t nge_reg_get8(nge_t *ngep, nge_regno_t regno); 26 #pragma inline(nge_reg_get8) 27 28 uint8_t 29 nge_reg_get8(nge_t *ngep, nge_regno_t regno) 30 { 31 NGE_TRACE(("nge_reg_get8($%p, 0x%lx)", (void *)ngep, regno)); 32 33 return (ddi_get8(ngep->io_handle, PIO_ADDR(ngep, regno))); 34 } 35 36 void nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data); 37 #pragma inline(nge_reg_put8) 38 39 void 40 nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data) 41 { 42 NGE_TRACE(("nge_reg_put8($%p, 0x%lx, 0x%x)", 43 (void *)ngep, regno, data)); 44 ddi_put8(ngep->io_handle, PIO_ADDR(ngep, regno), data); 45 46 } 47 48 uint16_t nge_reg_get16(nge_t *ngep, nge_regno_t regno); 49 #pragma inline(nge_reg_get16) 50 51 uint16_t 52 nge_reg_get16(nge_t *ngep, nge_regno_t regno) 53 { 54 NGE_TRACE(("nge_reg_get16($%p, 0x%lx)", (void *)ngep, regno)); 55 return (ddi_get16(ngep->io_handle, PIO_ADDR(ngep, regno))); 56 } 57 58 void nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data); 59 #pragma inline(nge_reg_put16) 60 61 void 62 nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data) 63 { 64 NGE_TRACE(("nge_reg_put16($%p, 0x%lx, 0x%x)", 65 (void *)ngep, regno, data)); 66 ddi_put16(ngep->io_handle, PIO_ADDR(ngep, regno), data); 67 68 } 69 70 uint32_t nge_reg_get32(nge_t *ngep, nge_regno_t regno); 71 #pragma inline(nge_reg_get32) 72 73 uint32_t 74 nge_reg_get32(nge_t *ngep, nge_regno_t regno) 75 { 76 NGE_TRACE(("nge_reg_get32($%p, 0x%lx)", (void *)ngep, regno)); 77 return (ddi_get32(ngep->io_handle, PIO_ADDR(ngep, regno))); 78 } 79 80 void nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data); 81 #pragma inline(nge_reg_put32) 82 83 void 84 nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data) 85 { 86 NGE_TRACE(("nge_reg_put32($%p, 0x%lx, 0x%x)", 87 (void *)ngep, regno, data)); 88 ddi_put32(ngep->io_handle, PIO_ADDR(ngep, regno), data); 89 90 } 91 92 93 static int nge_chip_peek_cfg(nge_t *ngep, nge_peekpoke_t *ppd); 94 #pragma no_inline(nge_chip_peek_cfg) 95 96 static int 97 nge_chip_peek_cfg(nge_t *ngep, nge_peekpoke_t *ppd) 98 { 99 int err; 100 uint64_t regval; 101 uint64_t regno; 102 103 NGE_TRACE(("nge_chip_peek_cfg($%p, $%p)", 104 (void *)ngep, (void *)ppd)); 105 106 err = DDI_SUCCESS; 107 regno = ppd->pp_acc_offset; 108 109 switch (ppd->pp_acc_size) { 110 case 1: 111 regval = pci_config_get8(ngep->cfg_handle, regno); 112 break; 113 114 case 2: 115 regval = pci_config_get16(ngep->cfg_handle, regno); 116 break; 117 118 case 4: 119 regval = pci_config_get32(ngep->cfg_handle, regno); 120 break; 121 122 case 8: 123 regval = pci_config_get64(ngep->cfg_handle, regno); 124 break; 125 } 126 ppd->pp_acc_data = regval; 127 return (err); 128 } 129 130 static int nge_chip_poke_cfg(nge_t *ngep, nge_peekpoke_t *ppd); 131 132 static int 133 nge_chip_poke_cfg(nge_t *ngep, nge_peekpoke_t *ppd) 134 { 135 int err; 136 uint64_t regval; 137 uint64_t regno; 138 139 NGE_TRACE(("nge_chip_poke_cfg($%p, $%p)", 140 (void *)ngep, (void *)ppd)); 141 142 err = DDI_SUCCESS; 143 regno = ppd->pp_acc_offset; 144 regval = ppd->pp_acc_data; 145 146 switch (ppd->pp_acc_size) { 147 case 1: 148 pci_config_put8(ngep->cfg_handle, regno, regval); 149 break; 150 151 case 2: 152 pci_config_put16(ngep->cfg_handle, regno, regval); 153 break; 154 155 case 4: 156 pci_config_put32(ngep->cfg_handle, regno, regval); 157 break; 158 159 case 8: 160 pci_config_put64(ngep->cfg_handle, regno, regval); 161 break; 162 } 163 164 return (err); 165 166 } 167 168 static int nge_chip_peek_reg(nge_t *ngep, nge_peekpoke_t *ppd); 169 170 static int 171 nge_chip_peek_reg(nge_t *ngep, nge_peekpoke_t *ppd) 172 { 173 int err; 174 uint64_t regval; 175 void *regaddr; 176 177 NGE_TRACE(("nge_chip_peek_reg($%p, $%p)", 178 (void *)ngep, (void *)ppd)); 179 180 err = DDI_SUCCESS; 181 regaddr = PIO_ADDR(ngep, ppd->pp_acc_offset); 182 183 switch (ppd->pp_acc_size) { 184 case 1: 185 regval = ddi_get8(ngep->io_handle, regaddr); 186 break; 187 188 case 2: 189 regval = ddi_get16(ngep->io_handle, regaddr); 190 break; 191 192 case 4: 193 regval = ddi_get32(ngep->io_handle, regaddr); 194 break; 195 196 case 8: 197 regval = ddi_get64(ngep->io_handle, regaddr); 198 break; 199 200 default: 201 regval = 0x0ull; 202 break; 203 } 204 ppd->pp_acc_data = regval; 205 return (err); 206 } 207 208 static int nge_chip_poke_reg(nge_t *ngep, nge_peekpoke_t *ppd); 209 210 static int 211 nge_chip_poke_reg(nge_t *ngep, nge_peekpoke_t *ppd) 212 { 213 int err; 214 uint64_t regval; 215 void *regaddr; 216 217 NGE_TRACE(("nge_chip_poke_reg($%p, $%p)", 218 (void *)ngep, (void *)ppd)); 219 220 err = DDI_SUCCESS; 221 regaddr = PIO_ADDR(ngep, ppd->pp_acc_offset); 222 regval = ppd->pp_acc_data; 223 224 switch (ppd->pp_acc_size) { 225 case 1: 226 ddi_put8(ngep->io_handle, regaddr, regval); 227 break; 228 229 case 2: 230 ddi_put16(ngep->io_handle, regaddr, regval); 231 break; 232 233 case 4: 234 ddi_put32(ngep->io_handle, regaddr, regval); 235 break; 236 237 case 8: 238 ddi_put64(ngep->io_handle, regaddr, regval); 239 break; 240 } 241 return (err); 242 } 243 244 static int nge_chip_peek_mii(nge_t *ngep, nge_peekpoke_t *ppd); 245 #pragma no_inline(nge_chip_peek_mii) 246 247 static int 248 nge_chip_peek_mii(nge_t *ngep, nge_peekpoke_t *ppd) 249 { 250 int err; 251 252 err = DDI_SUCCESS; 253 ppd->pp_acc_data = nge_mii_get16(ngep, ppd->pp_acc_offset/2); 254 return (err); 255 } 256 257 static int nge_chip_poke_mii(nge_t *ngep, nge_peekpoke_t *ppd); 258 #pragma no_inline(nge_chip_poke_mii) 259 260 static int 261 nge_chip_poke_mii(nge_t *ngep, nge_peekpoke_t *ppd) 262 { 263 int err; 264 err = DDI_SUCCESS; 265 nge_mii_put16(ngep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 266 return (err); 267 } 268 269 /* 270 * Basic SEEPROM get/set access routine 271 * 272 * This uses the chip's SEEPROM auto-access method, controlled by the 273 * Serial EEPROM Address/Data Registers at 0x504h, so the CPU 274 * doesn't have to fiddle with the individual bits. 275 * 276 * The caller should hold <genlock> and *also* have already acquired 277 * the right to access the SEEPROM. 278 * 279 * Return value: 280 * 0 on success, 281 * ENODATA on access timeout (maybe retryable: device may just be busy) 282 * EPROTO on other h/w or s/w errors. 283 * 284 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 285 * from a (successful) SEEPROM_ACCESS_READ. 286 */ 287 288 static int 289 nge_seeprom_access(nge_t *ngep, uint32_t cmd, nge_regno_t addr, uint16_t *dp) 290 { 291 uint32_t tries; 292 nge_ep_cmd cmd_reg; 293 nge_ep_data data_reg; 294 295 NGE_TRACE(("nge_seeprom_access($%p, %d, %x, $%p)", 296 (void *)ngep, cmd, addr, (void *)dp)); 297 298 ASSERT(mutex_owned(ngep->genlock)); 299 300 /* 301 * Check there's no command in progress. 302 * 303 * Note: this *shouldn't* ever find that there is a command 304 * in progress, because we already hold the <genlock> mutex. 305 * Also, to ensure we don't have a conflict with the chip's 306 * internal firmware or a process accessing the same (shared) 307 * So this is just a final consistency check: we shouldn't 308 * see EITHER the START bit (command started but not complete) 309 * OR the COMPLETE bit (command completed but not cleared). 310 */ 311 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 312 for (tries = 0; tries < 30; tries++) { 313 if (cmd_reg.cmd_bits.sts == SEEPROM_READY) 314 break; 315 drv_usecwait(10); 316 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 317 } 318 319 /* 320 * This should not happen. If so, we have to restart eeprom 321 * state machine 322 */ 323 if (tries == 30) { 324 cmd_reg.cmd_bits.sts = SEEPROM_READY; 325 nge_reg_put32(ngep, NGE_EP_CMD, cmd_reg.cmd_val); 326 drv_usecwait(10); 327 /* 328 * Polling the status bit to make assure the eeprom is ready 329 */ 330 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 331 for (tries = 0; tries < 30; tries++) { 332 if (cmd_reg.cmd_bits.sts == SEEPROM_READY) 333 break; 334 drv_usecwait(10); 335 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 336 } 337 } 338 339 /* 340 * Assemble the command ... 341 */ 342 cmd_reg.cmd_bits.addr = addr; 343 cmd_reg.cmd_bits.cmd = cmd; 344 cmd_reg.cmd_bits.sts = 0; 345 346 nge_reg_put32(ngep, NGE_EP_CMD, cmd_reg.cmd_val); 347 348 /* 349 * Polling whether the access is successful. 350 * 351 */ 352 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 353 for (tries = 0; tries < 30; tries++) { 354 if (cmd_reg.cmd_bits.sts == SEEPROM_READY) 355 break; 356 drv_usecwait(10); 357 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 358 } 359 360 if (tries == 30) { 361 nge_report(ngep, NGE_HW_ROM); 362 return (DDI_FAILURE); 363 } 364 switch (cmd) { 365 default: 366 case SEEPROM_CMD_WRITE_ENABLE: 367 case SEEPROM_CMD_ERASE: 368 case SEEPROM_CMD_ERALSE_ALL: 369 case SEEPROM_CMD_WRITE_DIS: 370 break; 371 372 case SEEPROM_CMD_READ: 373 data_reg.data_val = nge_reg_get32(ngep, NGE_EP_DATA); 374 *dp = data_reg.data_bits.data; 375 break; 376 377 case SEEPROM_CMD_WRITE: 378 data_reg.data_val = nge_reg_get32(ngep, NGE_EP_DATA); 379 data_reg.data_bits.data = *dp; 380 nge_reg_put32(ngep, NGE_EP_DATA, data_reg.data_val); 381 break; 382 } 383 384 return (DDI_SUCCESS); 385 } 386 387 388 static int 389 nge_chip_peek_seeprom(nge_t *ngep, nge_peekpoke_t *ppd) 390 { 391 uint16_t data; 392 int err; 393 394 err = nge_seeprom_access(ngep, SEEPROM_CMD_READ, 395 ppd->pp_acc_offset, &data); 396 ppd->pp_acc_data = data; 397 return (err); 398 } 399 400 static int 401 nge_chip_poke_seeprom(nge_t *ngep, nge_peekpoke_t *ppd) 402 { 403 uint16_t data; 404 int err; 405 406 data = ppd->pp_acc_data; 407 err = nge_seeprom_access(ngep, SEEPROM_CMD_WRITE, 408 ppd->pp_acc_offset, &data); 409 return (err); 410 } 411 412 void 413 nge_init_dev_spec_param(nge_t *ngep) 414 { 415 nge_dev_spec_param_t *dev_param_p; 416 chip_info_t *infop; 417 418 dev_param_p = &ngep->dev_spec_param; 419 infop = (chip_info_t *)&ngep->chipinfo; 420 421 switch (infop->device) { 422 case DEVICE_ID_NF3_E6: 423 case DEVICE_ID_NF3_DF: 424 case DEVICE_ID_MCP61_3EE: 425 case DEVICE_ID_MCP61_3EF: 426 case DEVICE_ID_MCP04_37: 427 case DEVICE_ID_MCP04_38: 428 dev_param_p->msi = B_FALSE; 429 dev_param_p->msi_x = B_FALSE; 430 dev_param_p->vlan = B_FALSE; 431 dev_param_p->tx_pause_frame = B_FALSE; 432 dev_param_p->rx_pause_frame = B_FALSE; 433 dev_param_p->jumbo = B_FALSE; 434 dev_param_p->tx_rx_64byte = B_FALSE; 435 dev_param_p->rx_hw_checksum = B_FALSE; 436 dev_param_p->tx_hw_checksum = 0; 437 dev_param_p->desc_type = DESC_OFFLOAD; 438 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 439 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 440 dev_param_p->nge_split = NGE_SPLIT_32; 441 break; 442 443 case DEVICE_ID_CK804_56: 444 case DEVICE_ID_CK804_57: 445 dev_param_p->msi = B_TRUE; 446 dev_param_p->msi_x = B_TRUE; 447 dev_param_p->vlan = B_FALSE; 448 dev_param_p->tx_pause_frame = B_FALSE; 449 dev_param_p->rx_pause_frame = B_TRUE; 450 dev_param_p->jumbo = B_TRUE; 451 dev_param_p->tx_rx_64byte = B_FALSE; 452 dev_param_p->rx_hw_checksum = B_TRUE; 453 dev_param_p->tx_hw_checksum = HCKSUM_IPHDRCKSUM; 454 dev_param_p->desc_type = DESC_HOT; 455 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_3072; 456 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_3072; 457 dev_param_p->nge_split = NGE_SPLIT_96; 458 break; 459 460 case DEVICE_ID_MCP51_268: 461 case DEVICE_ID_MCP51_269: 462 dev_param_p->msi = B_FALSE; 463 dev_param_p->msi_x = B_FALSE; 464 dev_param_p->vlan = B_FALSE; 465 dev_param_p->tx_pause_frame = B_FALSE; 466 dev_param_p->rx_pause_frame = B_FALSE; 467 dev_param_p->jumbo = B_FALSE; 468 dev_param_p->tx_rx_64byte = B_TRUE; 469 dev_param_p->rx_hw_checksum = B_FALSE; 470 dev_param_p->tx_hw_checksum = 0; 471 dev_param_p->desc_type = DESC_OFFLOAD; 472 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 473 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 474 dev_param_p->nge_split = NGE_SPLIT_32; 475 break; 476 477 case DEVICE_ID_MCP55_372: 478 case DEVICE_ID_MCP55_373: 479 dev_param_p->msi = B_TRUE; 480 dev_param_p->msi_x = B_TRUE; 481 dev_param_p->vlan = B_TRUE; 482 dev_param_p->tx_pause_frame = B_TRUE; 483 dev_param_p->rx_pause_frame = B_TRUE; 484 dev_param_p->jumbo = B_TRUE; 485 dev_param_p->tx_rx_64byte = B_TRUE; 486 dev_param_p->rx_hw_checksum = B_TRUE; 487 dev_param_p->tx_hw_checksum = HCKSUM_IPHDRCKSUM; 488 dev_param_p->desc_type = DESC_HOT; 489 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_3072; 490 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_3072; 491 dev_param_p->nge_split = NGE_SPLIT_96; 492 break; 493 494 default: 495 dev_param_p->msi = B_FALSE; 496 dev_param_p->msi_x = B_FALSE; 497 dev_param_p->vlan = B_FALSE; 498 dev_param_p->tx_pause_frame = B_FALSE; 499 dev_param_p->rx_pause_frame = B_FALSE; 500 dev_param_p->jumbo = B_FALSE; 501 dev_param_p->tx_rx_64byte = B_FALSE; 502 dev_param_p->rx_hw_checksum = B_FALSE; 503 dev_param_p->tx_hw_checksum = 0; 504 dev_param_p->desc_type = DESC_OFFLOAD; 505 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 506 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 507 dev_param_p->nge_split = NGE_SPLIT_32; 508 return; 509 } 510 } 511 /* 512 * Perform first-stage chip (re-)initialisation, using only config-space 513 * accesses: 514 * 515 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 516 * returning the data in the structure pointed to by <infop>. 517 */ 518 void nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset); 519 #pragma no_inline(nge_chip_cfg_init) 520 521 void 522 nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset) 523 { 524 uint16_t command; 525 ddi_acc_handle_t handle; 526 nge_interbus_conf interbus_conf; 527 nge_msi_mask_conf msi_mask_conf; 528 nge_msi_map_cap_conf cap_conf; 529 530 NGE_TRACE(("nge_chip_cfg_init($%p, $%p, %d)", 531 (void *)ngep, (void *)infop, reset)); 532 533 /* 534 * save PCI cache line size and subsystem vendor ID 535 * 536 * Read all the config-space registers that characterise the 537 * chip, specifically vendor/device/revision/subsystem vendor 538 * and subsystem device id. We expect (but don't check) that 539 */ 540 handle = ngep->cfg_handle; 541 /* reading the vendor information once */ 542 if (reset == B_FALSE) { 543 infop->command = pci_config_get16(handle, 544 PCI_CONF_COMM); 545 infop->vendor = pci_config_get16(handle, 546 PCI_CONF_VENID); 547 infop->device = pci_config_get16(handle, 548 PCI_CONF_DEVID); 549 infop->subven = pci_config_get16(handle, 550 PCI_CONF_SUBVENID); 551 infop->subdev = pci_config_get16(handle, 552 PCI_CONF_SUBSYSID); 553 infop->class_code = pci_config_get8(handle, 554 PCI_CONF_BASCLASS); 555 infop->revision = pci_config_get8(handle, 556 PCI_CONF_REVID); 557 infop->clsize = pci_config_get8(handle, 558 PCI_CONF_CACHE_LINESZ); 559 infop->latency = pci_config_get8(handle, 560 PCI_CONF_LATENCY_TIMER); 561 } 562 if (nge_enable_msi) { 563 /* Disable the hidden for MSI support */ 564 interbus_conf.conf_val = pci_config_get32(handle, 565 PCI_CONF_HT_INTERNAL); 566 if ((infop->device == DEVICE_ID_MCP55_373) || 567 (infop->device == DEVICE_ID_MCP55_372)) 568 interbus_conf.conf_bits.msix_off = NGE_SET; 569 interbus_conf.conf_bits.msi_off = NGE_CLEAR; 570 pci_config_put32(handle, PCI_CONF_HT_INTERNAL, 571 interbus_conf.conf_val); 572 573 if ((infop->device == DEVICE_ID_MCP55_373) || 574 (infop->device == DEVICE_ID_MCP55_372)) { 575 576 /* Disable the vector off for mcp55 */ 577 msi_mask_conf.msi_mask_conf_val = 578 pci_config_get32(handle, PCI_CONF_HT_MSI_MASK); 579 msi_mask_conf.msi_mask_bits.vec0_off = NGE_CLEAR; 580 msi_mask_conf.msi_mask_bits.vec1_off = NGE_CLEAR; 581 msi_mask_conf.msi_mask_bits.vec2_off = NGE_CLEAR; 582 msi_mask_conf.msi_mask_bits.vec3_off = NGE_CLEAR; 583 msi_mask_conf.msi_mask_bits.vec4_off = NGE_CLEAR; 584 msi_mask_conf.msi_mask_bits.vec5_off = NGE_CLEAR; 585 msi_mask_conf.msi_mask_bits.vec6_off = NGE_CLEAR; 586 msi_mask_conf.msi_mask_bits.vec7_off = NGE_CLEAR; 587 pci_config_put32(handle, PCI_CONF_HT_MSI_MASK, 588 msi_mask_conf.msi_mask_conf_val); 589 590 /* Enable the MSI mapping */ 591 cap_conf.msi_map_cap_conf_val = 592 pci_config_get32(handle, PCI_CONF_HT_MSI_MAP_CAP); 593 cap_conf.map_cap_conf_bits.map_en = NGE_SET; 594 pci_config_put32(handle, PCI_CONF_HT_MSI_MAP_CAP, 595 cap_conf.msi_map_cap_conf_val); 596 } 597 } else { 598 interbus_conf.conf_val = pci_config_get32(handle, 599 PCI_CONF_HT_INTERNAL); 600 interbus_conf.conf_bits.msi_off = NGE_SET; 601 pci_config_put32(handle, PCI_CONF_HT_INTERNAL, 602 interbus_conf.conf_val); 603 } 604 command = infop->command | PCI_COMM_MAE; 605 command &= ~PCI_COMM_MEMWR_INVAL; 606 command |= PCI_COMM_ME; 607 pci_config_put16(handle, PCI_CONF_COMM, command); 608 pci_config_put16(handle, PCI_CONF_STAT, ~0); 609 610 } 611 612 int 613 nge_chip_stop(nge_t *ngep, boolean_t fault) 614 { 615 int err; 616 uint32_t reg_val; 617 uint32_t tries; 618 nge_intr_src intr_src; 619 nge_mintr_src mintr_src; 620 nge_mii_cs mii_cs; 621 nge_rx_poll rx_poll; 622 nge_tx_poll tx_poll; 623 nge_rx_en rx_en; 624 nge_tx_en tx_en; 625 nge_tx_sta tx_sta; 626 nge_rx_sta rx_sta; 627 nge_mode_cntl mode; 628 nge_pmu_cntl2 pmu_cntl2; 629 630 NGE_TRACE(("nge_chip_stop($%p, %d)", (void *)ngep, fault)); 631 632 err = DDI_SUCCESS; 633 /* Clear all pending interrupts */ 634 intr_src.intr_val = nge_reg_get32(ngep, NGE_INTR_SRC); 635 nge_reg_put32(ngep, NGE_INTR_SRC, intr_src.intr_val); 636 mintr_src.src_val = nge_reg_get8(ngep, NGE_MINTR_SRC); 637 nge_reg_put8(ngep, NGE_MINTR_SRC, mintr_src.src_val); 638 639 /* Mask all interrupts */ 640 reg_val = nge_reg_get32(ngep, NGE_INTR_MASK); 641 reg_val &= ~NGE_INTR_ALL_EN; 642 nge_reg_put32(ngep, NGE_INTR_MASK, reg_val); 643 644 /* Disable auto-polling of phy */ 645 mii_cs.cs_val = nge_reg_get32(ngep, NGE_MII_CS); 646 mii_cs.cs_bits.ap_en = NGE_CLEAR; 647 nge_reg_put32(ngep, NGE_MII_CS, mii_cs.cs_val); 648 649 /* Reset buffer management & DMA */ 650 mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 651 mode.mode_bits.bm_reset = NGE_SET; 652 mode.mode_bits.dma_dis = NGE_SET; 653 mode.mode_bits.desc_type = ngep->desc_mode; 654 nge_reg_put32(ngep, NGE_MODE_CNTL, mode.mode_val); 655 656 drv_usecwait(50000); 657 658 /* Restore buffer management */ 659 mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 660 mode.mode_bits.bm_reset = NGE_CLEAR; 661 mode.mode_bits.tx_rcom_en = NGE_SET; 662 nge_reg_put32(ngep, NGE_MODE_CNTL, mode.mode_val); 663 664 nge_reg_put32(ngep, NGE_MODE_CNTL, mode.mode_val); 665 for (tries = 0; tries < 5000; tries++) { 666 drv_usecwait(10); 667 mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 668 if (mode.mode_bits.dma_status == NGE_SET) 669 break; 670 } 671 if (tries == 5000) { 672 return (DDI_FAILURE); 673 } 674 675 /* 676 * For mcp55, the bits 1:31 of NGE_RX_EN and NGE_TX_EN are 677 * defined to be used by SMU. The newer PXE than 527 began to 678 * support SMU and bit 24 of NGE_RX_EN/NGE_TX_EN are set 679 * when leaving PXE to prevents the MAC from winning 680 * arbitration to the main transmit/receive channels. 681 */ 682 if (ngep->chipinfo.device == DEVICE_ID_MCP55_373 || 683 ngep->chipinfo.device == DEVICE_ID_MCP55_372) { 684 685 /* Disable rx's machine */ 686 nge_reg_put32(ngep, NGE_RX_EN, 0x0); 687 688 /* Disable tx's machine */ 689 nge_reg_put32(ngep, NGE_TX_EN, 0x0); 690 } else { 691 692 /* Disable rx's machine */ 693 rx_en.val = nge_reg_get8(ngep, NGE_RX_EN); 694 rx_en.bits.rx_en = NGE_CLEAR; 695 nge_reg_put8(ngep, NGE_RX_EN, rx_en.val); 696 697 698 /* Disable tx's machine */ 699 tx_en.val = nge_reg_get8(ngep, NGE_TX_EN); 700 tx_en.bits.tx_en = NGE_CLEAR; 701 nge_reg_put8(ngep, NGE_TX_EN, tx_en.val); 702 } 703 704 /* Disable auto-poll of rx's state machine */ 705 rx_poll.poll_val = nge_reg_get32(ngep, NGE_RX_POLL); 706 rx_poll.poll_bits.rpen = NGE_CLEAR; 707 rx_poll.poll_bits.rpi = NGE_CLEAR; 708 nge_reg_put32(ngep, NGE_RX_POLL, rx_poll.poll_val); 709 710 /* Disable auto-polling of tx's state machine */ 711 tx_poll.poll_val = nge_reg_get32(ngep, NGE_TX_POLL); 712 tx_poll.poll_bits.tpen = NGE_CLEAR; 713 tx_poll.poll_bits.tpi = NGE_CLEAR; 714 nge_reg_put32(ngep, NGE_TX_POLL, tx_poll.poll_val); 715 716 717 /* 718 * Clean the status of tx's state machine 719 * and Make assure the tx's channel is idle 720 */ 721 tx_sta.sta_val = nge_reg_get32(ngep, NGE_TX_STA); 722 for (tries = 0; tries < 1000; tries++) { 723 if (tx_sta.sta_bits.tx_chan_sta == NGE_CLEAR) 724 break; 725 drv_usecwait(10); 726 tx_sta.sta_val = nge_reg_get32(ngep, NGE_TX_STA); 727 } 728 if (tries == 1000) { 729 return (DDI_FAILURE); 730 } 731 nge_reg_put32(ngep, NGE_TX_STA, tx_sta.sta_val); 732 733 /* 734 * Clean the status of rx's state machine 735 * and Make assure the tx's channel is idle 736 */ 737 rx_sta.sta_val = nge_reg_get32(ngep, NGE_RX_STA); 738 for (tries = 0; tries < 1000; tries++) { 739 if (rx_sta.sta_bits.rx_chan_sta == NGE_CLEAR) 740 break; 741 drv_usecwait(10); 742 rx_sta.sta_val = nge_reg_get32(ngep, NGE_RX_STA); 743 } 744 if (tries == 1000) { 745 return (DDI_FAILURE); 746 } 747 nge_reg_put32(ngep, NGE_RX_STA, rx_sta.sta_val); 748 749 if (ngep->chipinfo.device == DEVICE_ID_MCP51_269 || 750 ngep->chipinfo.device == DEVICE_ID_MCP51_268) { 751 752 nge_reg_put32(ngep, NGE_PMU_CIDLE_LIMIT, 0); 753 nge_reg_put32(ngep, NGE_PMU_DIDLE_LIMIT, 0); 754 755 pmu_cntl2.cntl2_val = nge_reg_get32(ngep, NGE_PMU_CNTL2); 756 pmu_cntl2.cntl2_bits.cidle_timer = NGE_CLEAR; 757 pmu_cntl2.cntl2_bits.didle_timer = NGE_CLEAR; 758 nge_reg_put32(ngep, NGE_PMU_CNTL2, pmu_cntl2.cntl2_val); 759 } 760 if (fault) 761 ngep->nge_chip_state = NGE_CHIP_FAULT; 762 else 763 ngep->nge_chip_state = NGE_CHIP_STOPPED; 764 765 return (err); 766 } 767 768 static void 769 nge_rx_setup(nge_t *ngep) 770 { 771 uint64_t desc_addr; 772 nge_rxtx_dlen dlen; 773 nge_rx_poll rx_poll; 774 775 /* 776 * Filling the address and length of rx's descriptors 777 */ 778 desc_addr = ngep->recv->desc.cookie.dmac_laddress; 779 nge_reg_put32(ngep, NGE_RX_DADR, desc_addr); 780 nge_reg_put32(ngep, NGE_RX_DADR_HI, desc_addr >> 32); 781 dlen.dlen_val = nge_reg_get32(ngep, NGE_RXTX_DLEN); 782 dlen.dlen_bits.rdlen = ngep->recv->desc.nslots - 1; 783 nge_reg_put32(ngep, NGE_RXTX_DLEN, dlen.dlen_val); 784 785 rx_poll.poll_val = nge_reg_get32(ngep, NGE_RX_POLL); 786 rx_poll.poll_bits.rpi = RX_POLL_INTV_1G; 787 rx_poll.poll_bits.rpen = NGE_SET; 788 nge_reg_put32(ngep, NGE_RX_POLL, rx_poll.poll_val); 789 } 790 791 static void 792 nge_tx_setup(nge_t *ngep) 793 { 794 uint64_t desc_addr; 795 nge_rxtx_dlen dlen; 796 797 /* 798 * Filling the address and length of tx's descriptors 799 */ 800 desc_addr = ngep->send->desc.cookie.dmac_laddress; 801 nge_reg_put32(ngep, NGE_TX_DADR, desc_addr); 802 nge_reg_put32(ngep, NGE_TX_DADR_HI, desc_addr >> 32); 803 dlen.dlen_val = nge_reg_get32(ngep, NGE_RXTX_DLEN); 804 dlen.dlen_bits.tdlen = ngep->send->desc.nslots - 1; 805 nge_reg_put32(ngep, NGE_RXTX_DLEN, dlen.dlen_val); 806 } 807 808 static int 809 nge_buff_setup(nge_t *ngep) 810 { 811 nge_mode_cntl mode_cntl; 812 nge_dev_spec_param_t *dev_param_p; 813 814 dev_param_p = &ngep->dev_spec_param; 815 816 /* 817 * Configure Rx&Tx's buffer 818 */ 819 nge_rx_setup(ngep); 820 nge_tx_setup(ngep); 821 822 /* 823 * Configure buffer attribute 824 */ 825 mode_cntl.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 826 827 /* 828 * Enable Dma access request 829 */ 830 mode_cntl.mode_bits.dma_dis = NGE_CLEAR; 831 832 /* 833 * Enbale Buffer management 834 */ 835 mode_cntl.mode_bits.bm_reset = NGE_CLEAR; 836 837 /* 838 * Support Standoffload Descriptor 839 */ 840 mode_cntl.mode_bits.desc_type = ngep->desc_mode; 841 842 /* 843 * Support receive hardware checksum 844 */ 845 if (dev_param_p->rx_hw_checksum) { 846 mode_cntl.mode_bits.rx_sum_en = NGE_SET; 847 } else 848 mode_cntl.mode_bits.rx_sum_en = NGE_CLEAR; 849 850 /* 851 * Disable Tx PRD coarse update 852 */ 853 mode_cntl.mode_bits.tx_prd_cu_en = NGE_CLEAR; 854 855 /* 856 * Disable 64-byte access 857 */ 858 mode_cntl.mode_bits.w64_dis = NGE_SET; 859 860 /* 861 * Skip Rx Error Frame is not supported and if 862 * enable it, jumbo frame does not work any more. 863 */ 864 mode_cntl.mode_bits.rx_filter_en = NGE_CLEAR; 865 866 /* 867 * Can not support hot mode now 868 */ 869 mode_cntl.mode_bits.resv15 = NGE_CLEAR; 870 871 if (dev_param_p->vlan) { 872 /* Disable the vlan strip for devices which support vlan */ 873 mode_cntl.mode_bits.vlan_strip = NGE_CLEAR; 874 875 /* Disable the vlan insert for devices which supprot vlan */ 876 mode_cntl.mode_bits.vlan_ins = NGE_CLEAR; 877 } 878 879 if (dev_param_p->tx_rx_64byte) { 880 881 /* Set the maximum TX PRD fetch size to 64 bytes */ 882 mode_cntl.mode_bits.tx_fetch_prd = NGE_SET; 883 884 /* Set the maximum RX PRD fetch size to 64 bytes */ 885 mode_cntl.mode_bits.rx_fetch_prd = NGE_SET; 886 } 887 /* 888 * Upload Rx data as it arrives, rather than waiting for full frame 889 */ 890 mode_cntl.mode_bits.resv16 = NGE_CLEAR; 891 892 /* 893 * Normal HOT table accesses 894 */ 895 mode_cntl.mode_bits.resv17 = NGE_CLEAR; 896 897 /* 898 * Normal HOT buffer requesting 899 */ 900 mode_cntl.mode_bits.resv18 = NGE_CLEAR; 901 nge_reg_put32(ngep, NGE_MODE_CNTL, mode_cntl.mode_val); 902 903 /* 904 * Signal controller to check for new Rx descriptors 905 */ 906 mode_cntl.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 907 mode_cntl.mode_bits.rxdm = NGE_SET; 908 mode_cntl.mode_bits.tx_rcom_en = NGE_SET; 909 nge_reg_put32(ngep, NGE_MODE_CNTL, mode_cntl.mode_val); 910 911 912 return (DDI_SUCCESS); 913 } 914 915 /* 916 * When chipset resets, the chipset can not restore the orignial 917 * mac address to the mac address registers. 918 * 919 * When the driver is dettached, the function will write the orignial 920 * mac address to the mac address registers. 921 */ 922 923 void 924 nge_restore_mac_addr(nge_t *ngep) 925 { 926 uint32_t mac_addr; 927 928 mac_addr = (uint32_t)ngep->chipinfo.hw_mac_addr; 929 nge_reg_put32(ngep, NGE_UNI_ADDR0, mac_addr); 930 mac_addr = (uint32_t)(ngep->chipinfo.hw_mac_addr >> 32); 931 nge_reg_put32(ngep, NGE_UNI_ADDR1, mac_addr); 932 } 933 934 int 935 nge_chip_reset(nge_t *ngep) 936 { 937 int err; 938 uint8_t i; 939 uint32_t regno; 940 uint64_t mac; 941 nge_uni_addr1 uaddr1; 942 nge_mul_addr1 maddr1; 943 nge_cp_cntl ee_cntl; 944 nge_soft_misc soft_misc; 945 nge_pmu_cntl0 pmu_cntl0; 946 nge_pmu_cntl2 pmu_cntl2; 947 nge_pm_cntl2 pm_cntl2; 948 const nge_ksindex_t *ksip; 949 nge_sw_statistics_t *sw_stp; 950 sw_stp = &ngep->statistics.sw_statistics; 951 952 NGE_TRACE(("nge_chip_reset($%p)", (void *)ngep)); 953 954 /* 955 * Clear the statistics by reading the statistics register 956 */ 957 for (ksip = nge_statistics; ksip->name != NULL; ++ksip) { 958 regno = KS_BASE + ksip->index * sizeof (uint32_t); 959 (void) nge_reg_get32(ngep, regno); 960 } 961 /* Clear the software statistics */ 962 sw_stp->recv_count = 0; 963 sw_stp->xmit_count = 0; 964 sw_stp->rbytes = 0; 965 sw_stp->obytes = 0; 966 967 /* 968 * Clear the Multicast mac address table 969 */ 970 nge_reg_put32(ngep, NGE_MUL_ADDR0, 0); 971 maddr1.addr_val = nge_reg_get32(ngep, NGE_MUL_ADDR1); 972 maddr1.addr_bits.addr = 0; 973 nge_reg_put32(ngep, NGE_MUL_ADDR1, maddr1.addr_val); 974 975 /* 976 * Setup seeprom control 977 */ 978 ee_cntl.cntl_val = nge_reg_get32(ngep, NGE_EP_CNTL); 979 ee_cntl.cntl_bits.clkdiv = EEPROM_CLKDIV; 980 ee_cntl.cntl_bits.rom_size = EEPROM_32K; 981 ee_cntl.cntl_bits.word_wid = ACCESS_16BIT; 982 ee_cntl.cntl_bits.wait_slots = EEPROM_WAITCLK; 983 nge_reg_put32(ngep, NGE_EP_CNTL, ee_cntl.cntl_val); 984 985 /* 986 * Reading the unicast mac address table 987 */ 988 if (ngep->nge_chip_state == NGE_CHIP_INITIAL) { 989 uaddr1.addr_val = nge_reg_get32(ngep, NGE_UNI_ADDR1); 990 mac = uaddr1.addr_bits.addr; 991 mac <<= 32; 992 mac |= nge_reg_get32(ngep, NGE_UNI_ADDR0); 993 if (mac != 0ULL && mac != ~0ULL) { 994 ngep->chipinfo.hw_mac_addr = mac; 995 for (i = ETHERADDRL; i-- != 0; ) { 996 ngep->chipinfo.vendor_addr.addr[i] = 997 (uchar_t)mac; 998 ngep->cur_uni_addr.addr[i] = (uchar_t)mac; 999 mac >>= 8; 1000 } 1001 ngep->chipinfo.vendor_addr.set = 1; 1002 } 1003 } 1004 pci_config_put8(ngep->cfg_handle, PCI_CONF_CACHE_LINESZ, 1005 ngep->chipinfo.clsize); 1006 pci_config_put8(ngep->cfg_handle, PCI_CONF_LATENCY_TIMER, 1007 ngep->chipinfo.latency); 1008 1009 /* 1010 * Stop the chipset and clear buffer management 1011 */ 1012 err = nge_chip_stop(ngep, B_FALSE); 1013 if (err == DDI_FAILURE) 1014 return (err); 1015 if (ngep->chipinfo.device == DEVICE_ID_MCP51_269 || 1016 ngep->chipinfo.device == DEVICE_ID_MCP51_268) { 1017 1018 /* Program software misc register */ 1019 soft_misc.misc_val = nge_reg_get32(ngep, NGE_SOFT_MISC); 1020 soft_misc.misc_bits.rx_clk_vx_rst = NGE_SET; 1021 soft_misc.misc_bits.tx_clk_vx_rst = NGE_SET; 1022 soft_misc.misc_bits.clk12m_vx_rst = NGE_SET; 1023 soft_misc.misc_bits.fpci_clk_vx_rst = NGE_SET; 1024 soft_misc.misc_bits.rx_clk_vc_rst = NGE_SET; 1025 soft_misc.misc_bits.tx_clk_vc_rst = NGE_SET; 1026 soft_misc.misc_bits.fs_clk_vc_rst = NGE_SET; 1027 soft_misc.misc_bits.rst_ex_m2pintf = NGE_SET; 1028 nge_reg_put32(ngep, NGE_SOFT_MISC, soft_misc.misc_val); 1029 1030 /* wait for 4 us */ 1031 drv_usecwait(4); 1032 1033 soft_misc.misc_val = nge_reg_get32(ngep, NGE_SOFT_MISC); 1034 soft_misc.misc_bits.rx_clk_vx_rst = NGE_CLEAR; 1035 soft_misc.misc_bits.tx_clk_vx_rst = NGE_CLEAR; 1036 soft_misc.misc_bits.clk12m_vx_rst = NGE_CLEAR; 1037 soft_misc.misc_bits.fpci_clk_vx_rst = NGE_CLEAR; 1038 soft_misc.misc_bits.rx_clk_vc_rst = NGE_CLEAR; 1039 soft_misc.misc_bits.tx_clk_vc_rst = NGE_CLEAR; 1040 soft_misc.misc_bits.fs_clk_vc_rst = NGE_CLEAR; 1041 soft_misc.misc_bits.rst_ex_m2pintf = NGE_CLEAR; 1042 nge_reg_put32(ngep, NGE_SOFT_MISC, soft_misc.misc_val); 1043 1044 /* Program PMU registers */ 1045 pmu_cntl0.cntl0_val = nge_reg_get32(ngep, NGE_PMU_CNTL0); 1046 pmu_cntl0.cntl0_bits.core_spd10_fp = 1047 NGE_PMU_CORE_SPD10_BUSY; 1048 pmu_cntl0.cntl0_bits.core_spd10_idle = 1049 NGE_PMU_CORE_SPD10_IDLE; 1050 pmu_cntl0.cntl0_bits.core_spd100_fp = 1051 NGE_PMU_CORE_SPD100_BUSY; 1052 pmu_cntl0.cntl0_bits.core_spd100_idle = 1053 NGE_PMU_CORE_SPD100_IDLE; 1054 pmu_cntl0.cntl0_bits.core_spd1000_fp = 1055 NGE_PMU_CORE_SPD1000_BUSY; 1056 pmu_cntl0.cntl0_bits.core_spd1000_idle = 1057 NGE_PMU_CORE_SPD100_IDLE; 1058 pmu_cntl0.cntl0_bits.core_spd10_idle = 1059 NGE_PMU_CORE_SPD10_IDLE; 1060 nge_reg_put32(ngep, NGE_PMU_CNTL0, pmu_cntl0.cntl0_val); 1061 1062 /* Set the core idle limit value */ 1063 nge_reg_put32(ngep, NGE_PMU_CIDLE_LIMIT, 1064 NGE_PMU_CIDLE_LIMIT_DEF); 1065 1066 /* Set the device idle limit value */ 1067 nge_reg_put32(ngep, NGE_PMU_DIDLE_LIMIT, 1068 NGE_PMU_DIDLE_LIMIT_DEF); 1069 1070 /* Enable the core/device idle timer in PMU control 2 */ 1071 pmu_cntl2.cntl2_val = nge_reg_get32(ngep, NGE_PMU_CNTL2); 1072 pmu_cntl2.cntl2_bits.cidle_timer = NGE_SET; 1073 pmu_cntl2.cntl2_bits.didle_timer = NGE_SET; 1074 pmu_cntl2.cntl2_bits.core_enable = NGE_SET; 1075 pmu_cntl2.cntl2_bits.dev_enable = NGE_SET; 1076 nge_reg_put32(ngep, NGE_PMU_CNTL2, pmu_cntl2.cntl2_val); 1077 } 1078 1079 /* 1080 * Clear the power state bits for phy since interface no longer 1081 * works after rebooting from Windows on a multi-boot machine 1082 */ 1083 if (ngep->chipinfo.device == DEVICE_ID_MCP51_268 || 1084 ngep->chipinfo.device == DEVICE_ID_MCP51_269 || 1085 ngep->chipinfo.device == DEVICE_ID_MCP55_372 || 1086 ngep->chipinfo.device == DEVICE_ID_MCP55_373 || 1087 ngep->chipinfo.device == DEVICE_ID_MCP61_3EE || 1088 ngep->chipinfo.device == DEVICE_ID_MCP61_3EF) { 1089 1090 pm_cntl2.cntl_val = nge_reg_get32(ngep, NGE_PM_CNTL2); 1091 /* bring phy out of coma mode */ 1092 pm_cntl2.cntl_bits.phy_coma_set = NGE_CLEAR; 1093 /* disable auto reset coma bits */ 1094 pm_cntl2.cntl_bits.resv4 = NGE_CLEAR; 1095 /* restore power to gated clocks */ 1096 pm_cntl2.cntl_bits.resv8_11 = NGE_CLEAR; 1097 nge_reg_put32(ngep, NGE_PM_CNTL2, pm_cntl2.cntl_val); 1098 } 1099 1100 /* 1101 * Reset the external phy 1102 */ 1103 (void) nge_phy_reset(ngep); 1104 ngep->nge_chip_state = NGE_CHIP_RESET; 1105 return (DDI_SUCCESS); 1106 } 1107 1108 int 1109 nge_chip_start(nge_t *ngep) 1110 { 1111 int err; 1112 nge_itc itc; 1113 nge_tx_cntl tx_cntl; 1114 nge_rx_cntrl0 rx_cntl0; 1115 nge_rx_cntl1 rx_cntl1; 1116 nge_tx_en tx_en; 1117 nge_rx_en rx_en; 1118 nge_mii_cs mii_cs; 1119 nge_swtr_cntl swtr_cntl; 1120 nge_rx_fifo_wm rx_fifo; 1121 nge_intr_mask intr_mask; 1122 nge_mintr_mask mintr_mask; 1123 nge_dev_spec_param_t *dev_param_p; 1124 1125 NGE_TRACE(("nge_chip_start($%p)", (void *)ngep)); 1126 1127 /* 1128 * Setup buffer management 1129 */ 1130 err = nge_buff_setup(ngep); 1131 if (err == DDI_FAILURE) 1132 return (err); 1133 1134 dev_param_p = &ngep->dev_spec_param; 1135 1136 /* 1137 * Enable polling attribute 1138 */ 1139 mii_cs.cs_val = nge_reg_get32(ngep, NGE_MII_CS); 1140 mii_cs.cs_bits.ap_paddr = ngep->phy_xmii_addr; 1141 mii_cs.cs_bits.ap_en = NGE_SET; 1142 mii_cs.cs_bits.ap_intv = MII_POLL_INTV; 1143 nge_reg_put32(ngep, NGE_MII_CS, mii_cs.cs_val); 1144 1145 /* 1146 * Setup link 1147 */ 1148 (*ngep->physops->phys_update)(ngep); 1149 1150 /* 1151 * Configure the tx's parameters 1152 */ 1153 tx_cntl.cntl_val = nge_reg_get32(ngep, NGE_TX_CNTL); 1154 if (dev_param_p->tx_pause_frame) 1155 tx_cntl.cntl_bits.paen = NGE_SET; 1156 else 1157 tx_cntl.cntl_bits.paen = NGE_CLEAR; 1158 tx_cntl.cntl_bits.retry_en = NGE_SET; 1159 tx_cntl.cntl_bits.pad_en = NGE_SET; 1160 tx_cntl.cntl_bits.fappend_en = NGE_SET; 1161 tx_cntl.cntl_bits.two_def_en = NGE_SET; 1162 tx_cntl.cntl_bits.max_retry = 15; 1163 tx_cntl.cntl_bits.burst_en = NGE_CLEAR; 1164 tx_cntl.cntl_bits.uflo_err_mask = NGE_CLEAR; 1165 tx_cntl.cntl_bits.tlcol_mask = NGE_CLEAR; 1166 tx_cntl.cntl_bits.lcar_mask = NGE_CLEAR; 1167 tx_cntl.cntl_bits.def_mask = NGE_CLEAR; 1168 tx_cntl.cntl_bits.exdef_mask = NGE_SET; 1169 tx_cntl.cntl_bits.lcar_mask = NGE_SET; 1170 tx_cntl.cntl_bits.tlcol_mask = NGE_SET; 1171 tx_cntl.cntl_bits.uflo_err_mask = NGE_SET; 1172 tx_cntl.cntl_bits.jam_seq_en = NGE_CLEAR; 1173 nge_reg_put32(ngep, NGE_TX_CNTL, tx_cntl.cntl_val); 1174 1175 1176 /* 1177 * Configure the parameters of Rx's state machine 1178 * Enabe the parameters: 1179 * 1). Pad Strip 1180 * 2). FCS Relay 1181 * 3). Pause 1182 * 4). Address filter 1183 * 5). Runt Packet receive 1184 * 6). Broadcast 1185 * 7). Receive Deferral 1186 * 1187 * Disable the following parameters for decreasing 1188 * the number of interrupts: 1189 * 1). Runt Inerrupt. 1190 * 2). Rx's Late Collision interrupt. 1191 * 3). Rx's Max length Error Interrupt. 1192 * 4). Rx's Length Field error Interrupt. 1193 * 5). Rx's FCS error interrupt. 1194 * 6). Rx's overflow error interrupt. 1195 * 7). Rx's Frame alignment error interrupt. 1196 */ 1197 rx_cntl0.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0); 1198 rx_cntl0.cntl_bits.padsen = NGE_CLEAR; 1199 rx_cntl0.cntl_bits.fcsren = NGE_CLEAR; 1200 if (dev_param_p->rx_pause_frame) 1201 rx_cntl0.cntl_bits.paen = NGE_SET; 1202 else 1203 rx_cntl0.cntl_bits.paen = NGE_CLEAR; 1204 rx_cntl0.cntl_bits.lben = NGE_CLEAR; 1205 rx_cntl0.cntl_bits.afen = NGE_SET; 1206 rx_cntl0.cntl_bits.runten = NGE_CLEAR; 1207 rx_cntl0.cntl_bits.brdis = NGE_CLEAR; 1208 rx_cntl0.cntl_bits.rdfen = NGE_CLEAR; 1209 rx_cntl0.cntl_bits.runtm = NGE_CLEAR; 1210 rx_cntl0.cntl_bits.slfb = NGE_CLEAR; 1211 rx_cntl0.cntl_bits.rlcolm = NGE_CLEAR; 1212 rx_cntl0.cntl_bits.maxerm = NGE_CLEAR; 1213 rx_cntl0.cntl_bits.lferm = NGE_CLEAR; 1214 rx_cntl0.cntl_bits.crcm = NGE_CLEAR; 1215 rx_cntl0.cntl_bits.ofolm = NGE_CLEAR; 1216 rx_cntl0.cntl_bits.framerm = NGE_CLEAR; 1217 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val); 1218 1219 /* 1220 * Configure the watermark for the rx's statemachine 1221 */ 1222 rx_fifo.wm_val = nge_reg_get32(ngep, NGE_RX_FIFO_WM); 1223 rx_fifo.wm_bits.data_hwm = ngep->rx_datahwm; 1224 rx_fifo.wm_bits.prd_lwm = ngep->rx_prdlwm; 1225 rx_fifo.wm_bits.prd_hwm = ngep->rx_prdhwm; 1226 nge_reg_put32(ngep, NGE_RX_FIFO_WM, rx_fifo.wm_val); 1227 1228 /* 1229 * Configure the deffer time slot for rx's state machine 1230 */ 1231 nge_reg_put8(ngep, NGE_RX_DEf, ngep->rx_def); 1232 1233 /* 1234 * Configure the length of rx's packet 1235 */ 1236 rx_cntl1.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL1); 1237 rx_cntl1.cntl_bits.length = ngep->max_sdu; 1238 nge_reg_put32(ngep, NGE_RX_CNTL1, rx_cntl1.cntl_val); 1239 /* 1240 * Enable Tx's state machine 1241 */ 1242 tx_en.val = nge_reg_get8(ngep, NGE_TX_EN); 1243 tx_en.bits.tx_en = NGE_SET; 1244 nge_reg_put8(ngep, NGE_TX_EN, tx_en.val); 1245 1246 /* 1247 * Enable Rx's state machine 1248 */ 1249 rx_en.val = nge_reg_get8(ngep, NGE_RX_EN); 1250 rx_en.bits.rx_en = NGE_SET; 1251 nge_reg_put8(ngep, NGE_RX_EN, rx_en.val); 1252 1253 itc.itc_val = nge_reg_get32(ngep, NGE_SWTR_ITC); 1254 itc.itc_bits.sw_intv = ngep->sw_intr_intv; 1255 nge_reg_put32(ngep, NGE_SWTR_ITC, itc.itc_val); 1256 1257 swtr_cntl.ctrl_val = nge_reg_get8(ngep, NGE_SWTR_CNTL); 1258 swtr_cntl.cntl_bits.sten = NGE_SET; 1259 swtr_cntl.cntl_bits.stren = NGE_SET; 1260 nge_reg_put32(ngep, NGE_SWTR_CNTL, swtr_cntl.ctrl_val); 1261 1262 /* 1263 * Disable all mii read/write operation Interrupt 1264 */ 1265 mintr_mask.mask_val = nge_reg_get8(ngep, NGE_MINTR_MASK); 1266 mintr_mask.mask_bits.mrei = NGE_CLEAR; 1267 mintr_mask.mask_bits.mcc2 = NGE_CLEAR; 1268 mintr_mask.mask_bits.mcc1 = NGE_CLEAR; 1269 mintr_mask.mask_bits.mapi = NGE_SET; 1270 mintr_mask.mask_bits.mpdi = NGE_SET; 1271 nge_reg_put8(ngep, NGE_MINTR_MASK, mintr_mask.mask_val); 1272 1273 /* 1274 * Enable all interrupt event 1275 */ 1276 intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK); 1277 intr_mask.mask_bits.reint = NGE_SET; 1278 intr_mask.mask_bits.rcint = NGE_SET; 1279 intr_mask.mask_bits.miss = NGE_SET; 1280 intr_mask.mask_bits.teint = NGE_CLEAR; 1281 intr_mask.mask_bits.tcint = NGE_SET; 1282 intr_mask.mask_bits.stint = NGE_CLEAR; 1283 intr_mask.mask_bits.mint = NGE_CLEAR; 1284 intr_mask.mask_bits.rfint = NGE_CLEAR; 1285 intr_mask.mask_bits.tfint = NGE_CLEAR; 1286 intr_mask.mask_bits.feint = NGE_SET; 1287 intr_mask.mask_bits.resv10 = NGE_CLEAR; 1288 intr_mask.mask_bits.resv11 = NGE_CLEAR; 1289 intr_mask.mask_bits.resv12 = NGE_CLEAR; 1290 intr_mask.mask_bits.resv13 = NGE_CLEAR; 1291 intr_mask.mask_bits.phyint = NGE_CLEAR; 1292 ngep->intr_masks = intr_mask.mask_val; 1293 nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val); 1294 ngep->nge_chip_state = NGE_CHIP_RUNNING; 1295 return (DDI_SUCCESS); 1296 } 1297 1298 /* 1299 * nge_chip_sync() -- program the chip with the unicast MAC address, 1300 * the multicast hash table, the required level of promiscuity. 1301 */ 1302 void 1303 nge_chip_sync(nge_t *ngep) 1304 { 1305 uint8_t i; 1306 uint64_t macaddr; 1307 uint64_t mul_addr; 1308 uint64_t mul_mask; 1309 nge_rx_cntrl0 rx_cntl; 1310 nge_uni_addr1 uni_adr1; 1311 1312 NGE_TRACE(("nge_chip_sync($%p)", (void *)ngep)); 1313 1314 macaddr = 0x0ull; 1315 mul_addr = 0x0ull; 1316 mul_mask = 0x0ull; 1317 rx_cntl.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0); 1318 1319 if (ngep->promisc) { 1320 rx_cntl.cntl_bits.afen = NGE_CLEAR; 1321 rx_cntl.cntl_bits.brdis = NGE_SET; 1322 } else { 1323 rx_cntl.cntl_bits.afen = NGE_SET; 1324 rx_cntl.cntl_bits.brdis = NGE_CLEAR; 1325 } 1326 1327 /* 1328 * Transform the MAC address from host to chip format, the unicast 1329 * MAC address(es) ... 1330 */ 1331 for (i = ETHERADDRL, macaddr = 0ull; i != 0; --i) { 1332 macaddr |= ngep->cur_uni_addr.addr[i-1]; 1333 macaddr <<= (i > 1) ? 8 : 0; 1334 } 1335 1336 nge_reg_put32(ngep, NGE_UNI_ADDR0, (uint32_t)macaddr); 1337 macaddr = macaddr >>32; 1338 uni_adr1.addr_val = nge_reg_get32(ngep, NGE_UNI_ADDR1); 1339 uni_adr1.addr_bits.addr = (uint16_t)macaddr; 1340 uni_adr1.addr_bits.resv16_31 = (uint16_t)0; 1341 nge_reg_put32(ngep, NGE_UNI_ADDR1, uni_adr1.addr_val); 1342 1343 /* 1344 * Reprogram the multicast address table ... 1345 */ 1346 for (i = ETHERADDRL, mul_addr = 0ull; i != 0; --i) { 1347 mul_addr |= ngep->cur_mul_addr.addr[i-1]; 1348 mul_addr <<= (i > 1) ? 8 : 0; 1349 mul_mask |= ngep->cur_mul_mask.addr[i-1]; 1350 mul_mask <<= (i > 1) ? 8 : 0; 1351 } 1352 nge_reg_put32(ngep, NGE_MUL_ADDR0, (uint32_t)mul_addr); 1353 mul_addr >>= 32; 1354 nge_reg_put32(ngep, NGE_MUL_ADDR1, mul_addr); 1355 nge_reg_put32(ngep, NGE_MUL_MASK, (uint32_t)mul_mask); 1356 mul_mask >>= 32; 1357 nge_reg_put32(ngep, NGE_MUL_MASK1, mul_mask); 1358 /* 1359 * Set or clear the PROMISCUOUS mode bit 1360 */ 1361 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl.cntl_val); 1362 /* 1363 * For internal PHY loopback, the link will 1364 * not be up, so it need to sync mac modes directly. 1365 */ 1366 if (ngep->param_loop_mode == NGE_LOOP_INTERNAL_PHY) 1367 nge_sync_mac_modes(ngep); 1368 } 1369 1370 static void 1371 nge_chip_err(nge_t *ngep) 1372 { 1373 nge_reg010 reg010_ins; 1374 nge_sw_statistics_t *psw_stat; 1375 nge_intr_mask intr_mask; 1376 1377 NGE_TRACE(("nge_chip_err($%p)", (void *)ngep)); 1378 1379 psw_stat = (nge_sw_statistics_t *)&ngep->statistics.sw_statistics; 1380 reg010_ins.reg010_val = nge_reg_get32(ngep, NGE_REG010); 1381 if (reg010_ins.reg010_bits.resv0) 1382 psw_stat->fe_err.tso_err_mss ++; 1383 1384 if (reg010_ins.reg010_bits.resv1) 1385 psw_stat->fe_err.tso_dis ++; 1386 1387 if (reg010_ins.reg010_bits.resv2) 1388 psw_stat->fe_err.tso_err_nosum ++; 1389 1390 if (reg010_ins.reg010_bits.resv3) 1391 psw_stat->fe_err.tso_err_hov ++; 1392 1393 if (reg010_ins.reg010_bits.resv4) 1394 psw_stat->fe_err.tso_err_huf ++; 1395 1396 if (reg010_ins.reg010_bits.resv5) 1397 psw_stat->fe_err.tso_err_l2 ++; 1398 1399 if (reg010_ins.reg010_bits.resv6) 1400 psw_stat->fe_err.tso_err_ip ++; 1401 1402 if (reg010_ins.reg010_bits.resv7) 1403 psw_stat->fe_err.tso_err_l4 ++; 1404 1405 if (reg010_ins.reg010_bits.resv8) 1406 psw_stat->fe_err.tso_err_tcp ++; 1407 1408 if (reg010_ins.reg010_bits.resv9) 1409 psw_stat->fe_err.hsum_err_ip ++; 1410 1411 if (reg010_ins.reg010_bits.resv10) 1412 psw_stat->fe_err.hsum_err_l4 ++; 1413 1414 if (reg010_ins.reg010_val != 0) { 1415 1416 /* 1417 * Fatal error is triggered by malformed driver commands. 1418 * Disable unless debugging. 1419 */ 1420 intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK); 1421 intr_mask.mask_bits.feint = NGE_CLEAR; 1422 nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val); 1423 ngep->intr_masks = intr_mask.mask_val; 1424 1425 } 1426 } 1427 1428 static void 1429 nge_sync_mac_modes(nge_t *ngep) 1430 { 1431 nge_tx_def tx_def; 1432 nge_tx_fifo_wm tx_fifo; 1433 nge_bkoff_cntl bk_cntl; 1434 nge_mac2phy m2p; 1435 nge_rx_cntrl0 rx_cntl0; 1436 nge_dev_spec_param_t *dev_param_p; 1437 1438 dev_param_p = &ngep->dev_spec_param; 1439 1440 tx_def.def_val = nge_reg_get32(ngep, NGE_TX_DEF); 1441 m2p.m2p_val = nge_reg_get32(ngep, NGE_MAC2PHY); 1442 tx_fifo.wm_val = nge_reg_get32(ngep, NGE_TX_FIFO_WM); 1443 bk_cntl.cntl_val = nge_reg_get32(ngep, NGE_BKOFF_CNTL); 1444 bk_cntl.bkoff_bits.rseed = BKOFF_RSEED; 1445 switch (ngep->param_link_speed) { 1446 case 10: 1447 m2p.m2p_bits.speed = low_speed; 1448 tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT; 1449 if (ngep->phy_mode == RGMII_IN) { 1450 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_10_100; 1451 tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER; 1452 } else { 1453 tx_def.def_bits.if_def = TX_TIFG_MII; 1454 tx_def.def_bits.ifg2_def = TX_IFG2_MII; 1455 } 1456 tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_MII; 1457 bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_MII; 1458 break; 1459 1460 case 100: 1461 m2p.m2p_bits.speed = fast_speed; 1462 tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT; 1463 if (ngep->phy_mode == RGMII_IN) { 1464 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_10_100; 1465 tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER; 1466 } else { 1467 tx_def.def_bits.if_def = TX_TIFG_MII; 1468 tx_def.def_bits.ifg2_def = TX_IFG2_MII; 1469 } 1470 tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_MII; 1471 bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_MII; 1472 break; 1473 1474 case 1000: 1475 m2p.m2p_bits.speed = giga_speed; 1476 tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT; 1477 if (ngep->param_link_duplex == LINK_DUPLEX_FULL) { 1478 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_1000; 1479 tx_def.def_bits.if_def = TX_IFG_RGMII_1000_FD; 1480 } else { 1481 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_1000; 1482 tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER; 1483 } 1484 1485 tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_GMII; 1486 bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_GMII; 1487 break; 1488 } 1489 1490 if (ngep->chipinfo.device == DEVICE_ID_MCP55_373 || 1491 ngep->chipinfo.device == DEVICE_ID_MCP55_372) { 1492 m2p.m2p_bits.phyintr = NGE_CLEAR; 1493 m2p.m2p_bits.phyintrlvl = NGE_CLEAR; 1494 } 1495 if (ngep->param_link_duplex == LINK_DUPLEX_HALF) { 1496 m2p.m2p_bits.hdup_en = NGE_SET; 1497 } 1498 else 1499 m2p.m2p_bits.hdup_en = NGE_CLEAR; 1500 nge_reg_put32(ngep, NGE_MAC2PHY, m2p.m2p_val); 1501 nge_reg_put32(ngep, NGE_TX_DEF, tx_def.def_val); 1502 1503 tx_fifo.wm_bits.data_lwm = TX_FIFO_DATA_LWM; 1504 tx_fifo.wm_bits.prd_lwm = TX_FIFO_PRD_LWM; 1505 tx_fifo.wm_bits.uprd_hwm = TX_FIFO_PRD_HWM; 1506 tx_fifo.wm_bits.fb_wm = TX_FIFO_TBFW; 1507 nge_reg_put32(ngep, NGE_TX_FIFO_WM, tx_fifo.wm_val); 1508 1509 nge_reg_put32(ngep, NGE_BKOFF_CNTL, bk_cntl.cntl_val); 1510 1511 rx_cntl0.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0); 1512 if (ngep->param_link_rx_pause && dev_param_p->rx_pause_frame) 1513 rx_cntl0.cntl_bits.paen = NGE_SET; 1514 else 1515 rx_cntl0.cntl_bits.paen = NGE_CLEAR; 1516 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val); 1517 } 1518 1519 /* 1520 * Handler for hardware link state change. 1521 * 1522 * When this routine is called, the hardware link state has changed 1523 * and the new state is reflected in the param_* variables. Here 1524 * we must update the softstate, reprogram the MAC to match, and 1525 * record the change in the log and/or on the console. 1526 */ 1527 static void 1528 nge_factotum_link_handler(nge_t *ngep) 1529 { 1530 /* 1531 * Update the s/w link_state 1532 */ 1533 if (ngep->param_link_up) 1534 ngep->link_state = LINK_STATE_UP; 1535 else 1536 ngep->link_state = LINK_STATE_DOWN; 1537 1538 /* 1539 * Reprogram the MAC modes to match 1540 */ 1541 nge_sync_mac_modes(ngep); 1542 } 1543 1544 static boolean_t 1545 nge_factotum_link_check(nge_t *ngep) 1546 { 1547 boolean_t lchg; 1548 boolean_t check; 1549 1550 ASSERT(mutex_owned(ngep->genlock)); 1551 1552 (*ngep->physops->phys_check)(ngep); 1553 switch (ngep->link_state) { 1554 case LINK_STATE_UP: 1555 lchg = (ngep->param_link_up == B_FALSE); 1556 check = (ngep->param_link_up == B_FALSE); 1557 break; 1558 1559 case LINK_STATE_DOWN: 1560 lchg = (ngep->param_link_up == B_TRUE); 1561 check = (ngep->param_link_up == B_TRUE); 1562 break; 1563 1564 default: 1565 check = B_TRUE; 1566 break; 1567 } 1568 1569 /* 1570 * If <check> is false, we're sure the link hasn't changed. 1571 * If true, however, it's not yet definitive; we have to call 1572 * nge_phys_check() to determine whether the link has settled 1573 * into a new state yet ... and if it has, then call the link 1574 * state change handler.But when the chip is 5700 in Dell 6650 1575 * ,even if check is false, the link may have changed.So we 1576 * have to call nge_phys_check() to determine the link state. 1577 */ 1578 if (check) 1579 nge_factotum_link_handler(ngep); 1580 1581 return (lchg); 1582 } 1583 1584 /* 1585 * Factotum routine to check for Tx stall, using the 'watchdog' counter 1586 */ 1587 static boolean_t nge_factotum_stall_check(nge_t *ngep); 1588 1589 static boolean_t 1590 nge_factotum_stall_check(nge_t *ngep) 1591 { 1592 uint32_t dogval; 1593 /* 1594 * Specific check for Tx stall ... 1595 * 1596 * The 'watchdog' counter is incremented whenever a packet 1597 * is queued, reset to 1 when some (but not all) buffers 1598 * are reclaimed, reset to 0 (disabled) when all buffers 1599 * are reclaimed, and shifted left here. If it exceeds the 1600 * threshold value, the chip is assumed to have stalled and 1601 * is put into the ERROR state. The factotum will then reset 1602 * it on the next pass. 1603 * 1604 * All of which should ensure that we don't get into a state 1605 * where packets are left pending indefinitely! 1606 */ 1607 dogval = nge_atomic_shl32(&ngep->watchdog, 1); 1608 if (dogval < nge_watchdog_count) { 1609 ngep->stall_cknum = 0; 1610 } else { 1611 ngep->stall_cknum++; 1612 } 1613 if (ngep->stall_cknum < 8) { 1614 return (B_FALSE); 1615 } else { 1616 ngep->stall_cknum = 0; 1617 ngep->statistics.sw_statistics.tx_stall++; 1618 return (B_TRUE); 1619 } 1620 } 1621 1622 1623 1624 /* 1625 * The factotum is woken up when there's something to do that we'd rather 1626 * not do from inside a hardware interrupt handler or high-level cyclic. 1627 * Its two main tasks are: 1628 * reset & restart the chip after an error 1629 * check the link status whenever necessary 1630 */ 1631 /* ARGSUSED */ 1632 uint_t 1633 nge_chip_factotum(caddr_t args1, caddr_t args2) 1634 { 1635 uint_t result; 1636 nge_t *ngep; 1637 boolean_t err; 1638 boolean_t linkchg; 1639 1640 ngep = (nge_t *)args1; 1641 1642 NGE_TRACE(("nge_chip_factotum($%p)", (void *)ngep)); 1643 1644 mutex_enter(ngep->softlock); 1645 if (ngep->factotum_flag == 0) { 1646 mutex_exit(ngep->softlock); 1647 return (DDI_INTR_UNCLAIMED); 1648 } 1649 ngep->factotum_flag = 0; 1650 mutex_exit(ngep->softlock); 1651 err = B_FALSE; 1652 linkchg = B_FALSE; 1653 result = DDI_INTR_CLAIMED; 1654 1655 mutex_enter(ngep->genlock); 1656 switch (ngep->nge_chip_state) { 1657 default: 1658 break; 1659 1660 case NGE_CHIP_RUNNING: 1661 linkchg = nge_factotum_link_check(ngep); 1662 err = nge_factotum_stall_check(ngep); 1663 break; 1664 1665 case NGE_CHIP_FAULT: 1666 (void) nge_restart(ngep); 1667 NGE_REPORT((ngep, "automatic recovery activated")); 1668 break; 1669 } 1670 1671 if (err) 1672 (void) nge_chip_stop(ngep, B_TRUE); 1673 mutex_exit(ngep->genlock); 1674 1675 /* 1676 * If the link state changed, tell the world about it (if 1677 * this version of MAC supports link state notification). 1678 * Note: can't do this while still holding the mutex. 1679 */ 1680 if (linkchg) 1681 mac_link_update(ngep->mh, ngep->link_state); 1682 1683 return (result); 1684 1685 } 1686 1687 static void 1688 nge_intr_handle(nge_t *ngep, nge_intr_src *pintr_src) 1689 { 1690 boolean_t brx; 1691 boolean_t btx; 1692 nge_mintr_src mintr_src; 1693 1694 brx = B_FALSE; 1695 btx = B_FALSE; 1696 ngep->statistics.sw_statistics.intr_count++; 1697 ngep->statistics.sw_statistics.intr_lval = pintr_src->intr_val; 1698 brx = (pintr_src->int_bits.reint | pintr_src->int_bits.miss 1699 | pintr_src->int_bits.rcint | pintr_src->int_bits.stint) 1700 > 0 ? B_TRUE : B_FALSE; 1701 if (pintr_src->int_bits.reint) 1702 ngep->statistics.sw_statistics.rx_err++; 1703 if (pintr_src->int_bits.miss) 1704 ngep->statistics.sw_statistics.rx_nobuffer++; 1705 1706 if (brx) 1707 nge_receive(ngep); 1708 btx = (pintr_src->int_bits.teint | pintr_src->int_bits.tcint) 1709 > 0 ? B_TRUE : B_FALSE; 1710 if (btx) 1711 nge_tx_recycle(ngep, B_TRUE); 1712 if (pintr_src->int_bits.teint) 1713 ngep->statistics.sw_statistics.tx_stop_err++; 1714 if (pintr_src->int_bits.stint) { 1715 if ((ngep->poll) && 1716 (ngep->recv_count < INTR_HWATER)) { 1717 ngep->poll_time++; 1718 } 1719 if ((ngep->recv_count > POLL_LWATER) && 1720 (!ngep->poll)) { 1721 ngep->poll = B_TRUE; 1722 } 1723 1724 if (ngep->poll_time == 10) { 1725 ngep->poll = B_FALSE; 1726 ngep->poll_time = 0; 1727 } 1728 ngep->recv_count = 0; 1729 } 1730 if (pintr_src->int_bits.feint) 1731 nge_chip_err(ngep); 1732 /* link interrupt, check the link state */ 1733 if (pintr_src->int_bits.mint) { 1734 mintr_src.src_val = nge_reg_get32(ngep, NGE_MINTR_SRC); 1735 nge_reg_put32(ngep, NGE_MINTR_SRC, mintr_src.src_val); 1736 nge_wake_factotum(ngep); 1737 } 1738 } 1739 1740 /* 1741 * nge_chip_intr() -- handle chip interrupts 1742 */ 1743 /* ARGSUSED */ 1744 uint_t 1745 nge_chip_intr(caddr_t arg1, caddr_t arg2) 1746 { 1747 nge_t *ngep = (nge_t *)arg1; 1748 nge_intr_src intr_src; 1749 nge_intr_mask intr_mask; 1750 1751 mutex_enter(ngep->genlock); 1752 1753 /* 1754 * Check whether chip's says it's asserting #INTA; 1755 * if not, don't process or claim the interrupt. 1756 */ 1757 intr_src.intr_val = nge_reg_get32(ngep, NGE_INTR_SRC); 1758 if (intr_src.intr_val == 0) { 1759 mutex_exit(ngep->genlock); 1760 return (DDI_INTR_UNCLAIMED); 1761 } 1762 /* 1763 * Ack the interrupt 1764 */ 1765 nge_reg_put32(ngep, NGE_INTR_SRC, intr_src.intr_val); 1766 1767 if (ngep->nge_chip_state != NGE_CHIP_RUNNING) { 1768 mutex_exit(ngep->genlock); 1769 return (DDI_INTR_CLAIMED); 1770 } 1771 nge_intr_handle(ngep, &intr_src); 1772 if (ngep->poll && !ngep->ch_intr_mode) { 1773 intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK); 1774 intr_mask.mask_val &= ~(ngep->intr_masks); 1775 intr_mask.mask_bits.stint = NGE_SET; 1776 nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val); 1777 ngep->ch_intr_mode = B_TRUE; 1778 } else if ((ngep->ch_intr_mode) && (!ngep->poll)) { 1779 nge_reg_put32(ngep, NGE_INTR_MASK, ngep->intr_masks); 1780 ngep->ch_intr_mode = B_FALSE; 1781 } 1782 mutex_exit(ngep->genlock); 1783 return (DDI_INTR_CLAIMED); 1784 } 1785 1786 static enum ioc_reply 1787 nge_pp_ioctl(nge_t *ngep, int cmd, mblk_t *mp, struct iocblk *iocp) 1788 { 1789 int err; 1790 uint64_t sizemask; 1791 uint64_t mem_va; 1792 uint64_t maxoff; 1793 boolean_t peek; 1794 nge_peekpoke_t *ppd; 1795 int (*ppfn)(nge_t *ngep, nge_peekpoke_t *ppd); 1796 1797 switch (cmd) { 1798 default: 1799 return (IOC_INVAL); 1800 1801 case NGE_PEEK: 1802 peek = B_TRUE; 1803 break; 1804 1805 case NGE_POKE: 1806 peek = B_FALSE; 1807 break; 1808 } 1809 1810 /* 1811 * Validate format of ioctl 1812 */ 1813 if (iocp->ioc_count != sizeof (nge_peekpoke_t)) 1814 return (IOC_INVAL); 1815 if (mp->b_cont == NULL) 1816 return (IOC_INVAL); 1817 ppd = (nge_peekpoke_t *)mp->b_cont->b_rptr; 1818 1819 /* 1820 * Validate request parameters 1821 */ 1822 switch (ppd->pp_acc_space) { 1823 default: 1824 return (IOC_INVAL); 1825 1826 case NGE_PP_SPACE_CFG: 1827 /* 1828 * Config space 1829 */ 1830 sizemask = 8|4|2|1; 1831 mem_va = 0; 1832 maxoff = PCI_CONF_HDR_SIZE; 1833 ppfn = peek ? nge_chip_peek_cfg : nge_chip_poke_cfg; 1834 break; 1835 1836 case NGE_PP_SPACE_REG: 1837 /* 1838 * Memory-mapped I/O space 1839 */ 1840 sizemask = 8|4|2|1; 1841 mem_va = 0; 1842 maxoff = NGE_REG_SIZE; 1843 ppfn = peek ? nge_chip_peek_reg : nge_chip_poke_reg; 1844 break; 1845 1846 case NGE_PP_SPACE_MII: 1847 sizemask = 4|2|1; 1848 mem_va = 0; 1849 maxoff = NGE_MII_SIZE; 1850 ppfn = peek ? nge_chip_peek_mii : nge_chip_poke_mii; 1851 break; 1852 1853 case NGE_PP_SPACE_SEEPROM: 1854 sizemask = 4|2|1; 1855 mem_va = 0; 1856 maxoff = NGE_SEEROM_SIZE; 1857 ppfn = peek ? nge_chip_peek_seeprom : nge_chip_poke_seeprom; 1858 break; 1859 } 1860 1861 switch (ppd->pp_acc_size) { 1862 default: 1863 return (IOC_INVAL); 1864 1865 case 8: 1866 case 4: 1867 case 2: 1868 case 1: 1869 if ((ppd->pp_acc_size & sizemask) == 0) 1870 return (IOC_INVAL); 1871 break; 1872 } 1873 1874 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 1875 return (IOC_INVAL); 1876 1877 if (ppd->pp_acc_offset >= maxoff) 1878 return (IOC_INVAL); 1879 1880 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 1881 return (IOC_INVAL); 1882 1883 /* 1884 * All OK - go do it! 1885 */ 1886 ppd->pp_acc_offset += mem_va; 1887 if (ppfn) 1888 err = (*ppfn)(ngep, ppd); 1889 if (err != DDI_SUCCESS) 1890 return (IOC_INVAL); 1891 return (peek ? IOC_REPLY : IOC_ACK); 1892 } 1893 1894 static enum ioc_reply nge_diag_ioctl(nge_t *ngep, int cmd, mblk_t *mp, 1895 struct iocblk *iocp); 1896 #pragma no_inline(nge_diag_ioctl) 1897 1898 static enum ioc_reply 1899 nge_diag_ioctl(nge_t *ngep, int cmd, mblk_t *mp, struct iocblk *iocp) 1900 { 1901 ASSERT(mutex_owned(ngep->genlock)); 1902 1903 switch (cmd) { 1904 default: 1905 nge_error(ngep, "nge_diag_ioctl: invalid cmd 0x%x", cmd); 1906 return (IOC_INVAL); 1907 1908 case NGE_DIAG: 1909 return (IOC_ACK); 1910 1911 case NGE_PEEK: 1912 case NGE_POKE: 1913 return (nge_pp_ioctl(ngep, cmd, mp, iocp)); 1914 1915 case NGE_PHY_RESET: 1916 return (IOC_RESTART_ACK); 1917 1918 case NGE_SOFT_RESET: 1919 case NGE_HARD_RESET: 1920 return (IOC_ACK); 1921 } 1922 1923 /* NOTREACHED */ 1924 } 1925 1926 enum ioc_reply 1927 nge_chip_ioctl(nge_t *ngep, mblk_t *mp, struct iocblk *iocp) 1928 { 1929 int cmd; 1930 1931 ASSERT(mutex_owned(ngep->genlock)); 1932 1933 cmd = iocp->ioc_cmd; 1934 1935 switch (cmd) { 1936 default: 1937 return (IOC_INVAL); 1938 1939 case NGE_DIAG: 1940 case NGE_PEEK: 1941 case NGE_POKE: 1942 case NGE_PHY_RESET: 1943 case NGE_SOFT_RESET: 1944 case NGE_HARD_RESET: 1945 #if NGE_DEBUGGING 1946 return (nge_diag_ioctl(ngep, cmd, mp, iocp)); 1947 #else 1948 return (IOC_INVAL); 1949 #endif 1950 1951 case NGE_MII_READ: 1952 case NGE_MII_WRITE: 1953 return (IOC_INVAL); 1954 1955 #if NGE_SEE_IO32 1956 case NGE_SEE_READ: 1957 case NGE_SEE_WRITE: 1958 return (IOC_INVAL); 1959 #endif 1960 1961 #if NGE_FLASH_IO32 1962 case NGE_FLASH_READ: 1963 case NGE_FLASH_WRITE: 1964 return (IOC_INVAL); 1965 #endif 1966 } 1967 } 1968