1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "nge.h" 30 static uint32_t nge_watchdog_count = 1 << 29; 31 extern boolean_t nge_enable_msi; 32 static void nge_sync_mac_modes(nge_t *); 33 34 #undef NGE_DBG 35 #define NGE_DBG NGE_DBG_CHIP 36 37 /* 38 * Operating register get/set access routines 39 */ 40 uint8_t nge_reg_get8(nge_t *ngep, nge_regno_t regno); 41 #pragma inline(nge_reg_get8) 42 43 uint8_t 44 nge_reg_get8(nge_t *ngep, nge_regno_t regno) 45 { 46 NGE_TRACE(("nge_reg_get8($%p, 0x%lx)", (void *)ngep, regno)); 47 48 return (ddi_get8(ngep->io_handle, PIO_ADDR(ngep, regno))); 49 } 50 51 void nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data); 52 #pragma inline(nge_reg_put8) 53 54 void 55 nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data) 56 { 57 NGE_TRACE(("nge_reg_put8($%p, 0x%lx, 0x%x)", 58 (void *)ngep, regno, data)); 59 ddi_put8(ngep->io_handle, PIO_ADDR(ngep, regno), data); 60 61 } 62 63 uint16_t nge_reg_get16(nge_t *ngep, nge_regno_t regno); 64 #pragma inline(nge_reg_get16) 65 66 uint16_t 67 nge_reg_get16(nge_t *ngep, nge_regno_t regno) 68 { 69 NGE_TRACE(("nge_reg_get16($%p, 0x%lx)", (void *)ngep, regno)); 70 return (ddi_get16(ngep->io_handle, PIO_ADDR(ngep, regno))); 71 } 72 73 void nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data); 74 #pragma inline(nge_reg_put16) 75 76 void 77 nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data) 78 { 79 NGE_TRACE(("nge_reg_put16($%p, 0x%lx, 0x%x)", 80 (void *)ngep, regno, data)); 81 ddi_put16(ngep->io_handle, PIO_ADDR(ngep, regno), data); 82 83 } 84 85 uint32_t nge_reg_get32(nge_t *ngep, nge_regno_t regno); 86 #pragma inline(nge_reg_get32) 87 88 uint32_t 89 nge_reg_get32(nge_t *ngep, nge_regno_t regno) 90 { 91 NGE_TRACE(("nge_reg_get32($%p, 0x%lx)", (void *)ngep, regno)); 92 return (ddi_get32(ngep->io_handle, PIO_ADDR(ngep, regno))); 93 } 94 95 void nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data); 96 #pragma inline(nge_reg_put32) 97 98 void 99 nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data) 100 { 101 NGE_TRACE(("nge_reg_put32($%p, 0x%lx, 0x%x)", 102 (void *)ngep, regno, data)); 103 ddi_put32(ngep->io_handle, PIO_ADDR(ngep, regno), data); 104 105 } 106 107 108 static int nge_chip_peek_cfg(nge_t *ngep, nge_peekpoke_t *ppd); 109 #pragma no_inline(nge_chip_peek_cfg) 110 111 static int 112 nge_chip_peek_cfg(nge_t *ngep, nge_peekpoke_t *ppd) 113 { 114 int err; 115 uint64_t regval; 116 uint64_t regno; 117 118 NGE_TRACE(("nge_chip_peek_cfg($%p, $%p)", 119 (void *)ngep, (void *)ppd)); 120 121 err = DDI_SUCCESS; 122 regno = ppd->pp_acc_offset; 123 124 switch (ppd->pp_acc_size) { 125 case 1: 126 regval = pci_config_get8(ngep->cfg_handle, regno); 127 break; 128 129 case 2: 130 regval = pci_config_get16(ngep->cfg_handle, regno); 131 break; 132 133 case 4: 134 regval = pci_config_get32(ngep->cfg_handle, regno); 135 break; 136 137 case 8: 138 regval = pci_config_get64(ngep->cfg_handle, regno); 139 break; 140 } 141 ppd->pp_acc_data = regval; 142 return (err); 143 } 144 145 static int nge_chip_poke_cfg(nge_t *ngep, nge_peekpoke_t *ppd); 146 147 static int 148 nge_chip_poke_cfg(nge_t *ngep, nge_peekpoke_t *ppd) 149 { 150 int err; 151 uint64_t regval; 152 uint64_t regno; 153 154 NGE_TRACE(("nge_chip_poke_cfg($%p, $%p)", 155 (void *)ngep, (void *)ppd)); 156 157 err = DDI_SUCCESS; 158 regno = ppd->pp_acc_offset; 159 regval = ppd->pp_acc_data; 160 161 switch (ppd->pp_acc_size) { 162 case 1: 163 pci_config_put8(ngep->cfg_handle, regno, regval); 164 break; 165 166 case 2: 167 pci_config_put16(ngep->cfg_handle, regno, regval); 168 break; 169 170 case 4: 171 pci_config_put32(ngep->cfg_handle, regno, regval); 172 break; 173 174 case 8: 175 pci_config_put64(ngep->cfg_handle, regno, regval); 176 break; 177 } 178 179 return (err); 180 181 } 182 183 static int nge_chip_peek_reg(nge_t *ngep, nge_peekpoke_t *ppd); 184 185 static int 186 nge_chip_peek_reg(nge_t *ngep, nge_peekpoke_t *ppd) 187 { 188 int err; 189 uint64_t regval; 190 void *regaddr; 191 192 NGE_TRACE(("nge_chip_peek_reg($%p, $%p)", 193 (void *)ngep, (void *)ppd)); 194 195 err = DDI_SUCCESS; 196 regaddr = PIO_ADDR(ngep, ppd->pp_acc_offset); 197 198 switch (ppd->pp_acc_size) { 199 case 1: 200 regval = ddi_get8(ngep->io_handle, regaddr); 201 break; 202 203 case 2: 204 regval = ddi_get16(ngep->io_handle, regaddr); 205 break; 206 207 case 4: 208 regval = ddi_get32(ngep->io_handle, regaddr); 209 break; 210 211 case 8: 212 regval = ddi_get64(ngep->io_handle, regaddr); 213 break; 214 215 default: 216 regval = 0x0ull; 217 break; 218 } 219 ppd->pp_acc_data = regval; 220 return (err); 221 } 222 223 static int nge_chip_poke_reg(nge_t *ngep, nge_peekpoke_t *ppd); 224 225 static int 226 nge_chip_poke_reg(nge_t *ngep, nge_peekpoke_t *ppd) 227 { 228 int err; 229 uint64_t regval; 230 void *regaddr; 231 232 NGE_TRACE(("nge_chip_poke_reg($%p, $%p)", 233 (void *)ngep, (void *)ppd)); 234 235 err = DDI_SUCCESS; 236 regaddr = PIO_ADDR(ngep, ppd->pp_acc_offset); 237 regval = ppd->pp_acc_data; 238 239 switch (ppd->pp_acc_size) { 240 case 1: 241 ddi_put8(ngep->io_handle, regaddr, regval); 242 break; 243 244 case 2: 245 ddi_put16(ngep->io_handle, regaddr, regval); 246 break; 247 248 case 4: 249 ddi_put32(ngep->io_handle, regaddr, regval); 250 break; 251 252 case 8: 253 ddi_put64(ngep->io_handle, regaddr, regval); 254 break; 255 } 256 return (err); 257 } 258 259 static int nge_chip_peek_mii(nge_t *ngep, nge_peekpoke_t *ppd); 260 #pragma no_inline(nge_chip_peek_mii) 261 262 static int 263 nge_chip_peek_mii(nge_t *ngep, nge_peekpoke_t *ppd) 264 { 265 int err; 266 267 err = DDI_SUCCESS; 268 ppd->pp_acc_data = nge_mii_get16(ngep, ppd->pp_acc_offset/2); 269 return (err); 270 } 271 272 static int nge_chip_poke_mii(nge_t *ngep, nge_peekpoke_t *ppd); 273 #pragma no_inline(nge_chip_poke_mii) 274 275 static int 276 nge_chip_poke_mii(nge_t *ngep, nge_peekpoke_t *ppd) 277 { 278 int err; 279 err = DDI_SUCCESS; 280 nge_mii_put16(ngep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 281 return (err); 282 } 283 284 /* 285 * Basic SEEPROM get/set access routine 286 * 287 * This uses the chip's SEEPROM auto-access method, controlled by the 288 * Serial EEPROM Address/Data Registers at 0x504h, so the CPU 289 * doesn't have to fiddle with the individual bits. 290 * 291 * The caller should hold <genlock> and *also* have already acquired 292 * the right to access the SEEPROM. 293 * 294 * Return value: 295 * 0 on success, 296 * ENODATA on access timeout (maybe retryable: device may just be busy) 297 * EPROTO on other h/w or s/w errors. 298 * 299 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 300 * from a (successful) SEEPROM_ACCESS_READ. 301 */ 302 303 static int 304 nge_seeprom_access(nge_t *ngep, uint32_t cmd, nge_regno_t addr, uint16_t *dp) 305 { 306 uint32_t tries; 307 nge_ep_cmd cmd_reg; 308 nge_ep_data data_reg; 309 310 NGE_TRACE(("nge_seeprom_access($%p, %d, %x, $%p)", 311 (void *)ngep, cmd, addr, (void *)dp)); 312 313 ASSERT(mutex_owned(ngep->genlock)); 314 315 /* 316 * Check there's no command in progress. 317 * 318 * Note: this *shouldn't* ever find that there is a command 319 * in progress, because we already hold the <genlock> mutex. 320 * Also, to ensure we don't have a conflict with the chip's 321 * internal firmware or a process accessing the same (shared) 322 * So this is just a final consistency check: we shouldn't 323 * see EITHER the START bit (command started but not complete) 324 * OR the COMPLETE bit (command completed but not cleared). 325 */ 326 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 327 for (tries = 0; tries < 30; tries++) { 328 if (cmd_reg.cmd_bits.sts == SEEPROM_READY) 329 break; 330 drv_usecwait(10); 331 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 332 } 333 334 /* 335 * This should not happen. If so, we have to restart eeprom 336 * state machine 337 */ 338 if (tries == 30) { 339 cmd_reg.cmd_bits.sts = SEEPROM_READY; 340 nge_reg_put32(ngep, NGE_EP_CMD, cmd_reg.cmd_val); 341 drv_usecwait(10); 342 /* 343 * Polling the status bit to make assure the eeprom is ready 344 */ 345 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 346 for (tries = 0; tries < 30; tries++) { 347 if (cmd_reg.cmd_bits.sts == SEEPROM_READY) 348 break; 349 drv_usecwait(10); 350 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 351 } 352 } 353 354 /* 355 * Assemble the command ... 356 */ 357 cmd_reg.cmd_bits.addr = addr; 358 cmd_reg.cmd_bits.cmd = cmd; 359 cmd_reg.cmd_bits.sts = 0; 360 361 nge_reg_put32(ngep, NGE_EP_CMD, cmd_reg.cmd_val); 362 363 /* 364 * Polling whether the access is successful. 365 * 366 */ 367 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 368 for (tries = 0; tries < 30; tries++) { 369 if (cmd_reg.cmd_bits.sts == SEEPROM_READY) 370 break; 371 drv_usecwait(10); 372 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD); 373 } 374 375 if (tries == 30) { 376 nge_report(ngep, NGE_HW_ROM); 377 return (DDI_FAILURE); 378 } 379 switch (cmd) { 380 default: 381 case SEEPROM_CMD_WRITE_ENABLE: 382 case SEEPROM_CMD_ERASE: 383 case SEEPROM_CMD_ERALSE_ALL: 384 case SEEPROM_CMD_WRITE_DIS: 385 break; 386 387 case SEEPROM_CMD_READ: 388 data_reg.data_val = nge_reg_get32(ngep, NGE_EP_DATA); 389 *dp = data_reg.data_bits.data; 390 break; 391 392 case SEEPROM_CMD_WRITE: 393 data_reg.data_val = nge_reg_get32(ngep, NGE_EP_DATA); 394 data_reg.data_bits.data = *dp; 395 nge_reg_put32(ngep, NGE_EP_DATA, data_reg.data_val); 396 break; 397 } 398 399 return (DDI_SUCCESS); 400 } 401 402 403 static int 404 nge_chip_peek_seeprom(nge_t *ngep, nge_peekpoke_t *ppd) 405 { 406 uint16_t data; 407 int err; 408 409 err = nge_seeprom_access(ngep, SEEPROM_CMD_READ, 410 ppd->pp_acc_offset, &data); 411 ppd->pp_acc_data = data; 412 return (err); 413 } 414 415 static int 416 nge_chip_poke_seeprom(nge_t *ngep, nge_peekpoke_t *ppd) 417 { 418 uint16_t data; 419 int err; 420 421 data = ppd->pp_acc_data; 422 err = nge_seeprom_access(ngep, SEEPROM_CMD_WRITE, 423 ppd->pp_acc_offset, &data); 424 return (err); 425 } 426 427 void 428 nge_init_dev_spec_param(nge_t *ngep) 429 { 430 nge_dev_spec_param_t *dev_param_p; 431 chip_info_t *infop; 432 433 dev_param_p = &ngep->dev_spec_param; 434 infop = (chip_info_t *)&ngep->chipinfo; 435 436 switch (infop->device) { 437 case DEVICE_ID_NF3_E6: 438 case DEVICE_ID_NF3_DF: 439 case DEVICE_ID_MCP04_37: 440 case DEVICE_ID_MCP04_38: 441 dev_param_p->msi = B_FALSE; 442 dev_param_p->msi_x = B_FALSE; 443 dev_param_p->vlan = B_FALSE; 444 dev_param_p->advanced_pm = B_FALSE; 445 dev_param_p->tx_pause_frame = B_FALSE; 446 dev_param_p->rx_pause_frame = B_FALSE; 447 dev_param_p->jumbo = B_FALSE; 448 dev_param_p->tx_rx_64byte = B_FALSE; 449 dev_param_p->rx_hw_checksum = B_FALSE; 450 dev_param_p->tx_hw_checksum = 0; 451 dev_param_p->desc_type = DESC_OFFLOAD; 452 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 453 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 454 dev_param_p->nge_split = NGE_SPLIT_32; 455 break; 456 457 case DEVICE_ID_CK804_56: 458 case DEVICE_ID_CK804_57: 459 dev_param_p->msi = B_TRUE; 460 dev_param_p->msi_x = B_TRUE; 461 dev_param_p->vlan = B_FALSE; 462 dev_param_p->advanced_pm = B_FALSE; 463 dev_param_p->tx_pause_frame = B_FALSE; 464 dev_param_p->rx_pause_frame = B_TRUE; 465 dev_param_p->jumbo = B_TRUE; 466 dev_param_p->tx_rx_64byte = B_FALSE; 467 dev_param_p->rx_hw_checksum = B_TRUE; 468 dev_param_p->tx_hw_checksum = HCKSUM_IPHDRCKSUM; 469 dev_param_p->desc_type = DESC_HOT; 470 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_3072; 471 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_3072; 472 dev_param_p->nge_split = NGE_SPLIT_96; 473 break; 474 475 case DEVICE_ID_MCP61_3EE: 476 case DEVICE_ID_MCP61_3EF: 477 case DEVICE_ID_MCP51_268: 478 case DEVICE_ID_MCP51_269: 479 dev_param_p->msi = B_FALSE; 480 dev_param_p->msi_x = B_FALSE; 481 dev_param_p->vlan = B_FALSE; 482 dev_param_p->advanced_pm = B_TRUE; 483 dev_param_p->tx_pause_frame = B_FALSE; 484 dev_param_p->rx_pause_frame = B_FALSE; 485 dev_param_p->jumbo = B_FALSE; 486 dev_param_p->tx_rx_64byte = B_TRUE; 487 dev_param_p->rx_hw_checksum = B_FALSE; 488 dev_param_p->tx_hw_checksum = 0; 489 dev_param_p->desc_type = DESC_OFFLOAD; 490 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 491 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 492 dev_param_p->nge_split = NGE_SPLIT_32; 493 break; 494 495 case DEVICE_ID_MCP55_372: 496 case DEVICE_ID_MCP55_373: 497 dev_param_p->msi = B_TRUE; 498 dev_param_p->msi_x = B_TRUE; 499 dev_param_p->vlan = B_TRUE; 500 dev_param_p->advanced_pm = B_TRUE; 501 dev_param_p->tx_pause_frame = B_TRUE; 502 dev_param_p->rx_pause_frame = B_TRUE; 503 dev_param_p->jumbo = B_TRUE; 504 dev_param_p->tx_rx_64byte = B_TRUE; 505 dev_param_p->rx_hw_checksum = B_TRUE; 506 dev_param_p->tx_hw_checksum = HCKSUM_IPHDRCKSUM; 507 dev_param_p->desc_type = DESC_HOT; 508 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_3072; 509 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_3072; 510 dev_param_p->nge_split = NGE_SPLIT_96; 511 break; 512 513 default: 514 dev_param_p->msi = B_FALSE; 515 dev_param_p->msi_x = B_FALSE; 516 dev_param_p->vlan = B_FALSE; 517 dev_param_p->advanced_pm = B_FALSE; 518 dev_param_p->tx_pause_frame = B_FALSE; 519 dev_param_p->rx_pause_frame = B_FALSE; 520 dev_param_p->jumbo = B_FALSE; 521 dev_param_p->tx_rx_64byte = B_FALSE; 522 dev_param_p->rx_hw_checksum = B_FALSE; 523 dev_param_p->tx_hw_checksum = 0; 524 dev_param_p->desc_type = DESC_OFFLOAD; 525 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024; 526 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024; 527 dev_param_p->nge_split = NGE_SPLIT_32; 528 return; 529 } 530 } 531 /* 532 * Perform first-stage chip (re-)initialisation, using only config-space 533 * accesses: 534 * 535 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 536 * returning the data in the structure pointed to by <infop>. 537 */ 538 void nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset); 539 #pragma no_inline(nge_chip_cfg_init) 540 541 void 542 nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset) 543 { 544 uint16_t command; 545 ddi_acc_handle_t handle; 546 nge_interbus_conf interbus_conf; 547 nge_msi_mask_conf msi_mask_conf; 548 nge_msi_map_cap_conf cap_conf; 549 550 NGE_TRACE(("nge_chip_cfg_init($%p, $%p, %d)", 551 (void *)ngep, (void *)infop, reset)); 552 553 /* 554 * save PCI cache line size and subsystem vendor ID 555 * 556 * Read all the config-space registers that characterise the 557 * chip, specifically vendor/device/revision/subsystem vendor 558 * and subsystem device id. We expect (but don't check) that 559 */ 560 handle = ngep->cfg_handle; 561 /* reading the vendor information once */ 562 if (reset == B_FALSE) { 563 infop->command = pci_config_get16(handle, 564 PCI_CONF_COMM); 565 infop->vendor = pci_config_get16(handle, 566 PCI_CONF_VENID); 567 infop->device = pci_config_get16(handle, 568 PCI_CONF_DEVID); 569 infop->subven = pci_config_get16(handle, 570 PCI_CONF_SUBVENID); 571 infop->subdev = pci_config_get16(handle, 572 PCI_CONF_SUBSYSID); 573 infop->class_code = pci_config_get8(handle, 574 PCI_CONF_BASCLASS); 575 infop->revision = pci_config_get8(handle, 576 PCI_CONF_REVID); 577 infop->clsize = pci_config_get8(handle, 578 PCI_CONF_CACHE_LINESZ); 579 infop->latency = pci_config_get8(handle, 580 PCI_CONF_LATENCY_TIMER); 581 } 582 if (nge_enable_msi) { 583 /* Disable the hidden for MSI support */ 584 interbus_conf.conf_val = pci_config_get32(handle, 585 PCI_CONF_HT_INTERNAL); 586 if ((infop->device == DEVICE_ID_MCP55_373) || 587 (infop->device == DEVICE_ID_MCP55_372)) 588 interbus_conf.conf_bits.msix_off = NGE_SET; 589 interbus_conf.conf_bits.msi_off = NGE_CLEAR; 590 pci_config_put32(handle, PCI_CONF_HT_INTERNAL, 591 interbus_conf.conf_val); 592 593 if ((infop->device == DEVICE_ID_MCP55_373) || 594 (infop->device == DEVICE_ID_MCP55_372)) { 595 596 /* Disable the vector off for mcp55 */ 597 msi_mask_conf.msi_mask_conf_val = 598 pci_config_get32(handle, PCI_CONF_HT_MSI_MASK); 599 msi_mask_conf.msi_mask_bits.vec0_off = NGE_CLEAR; 600 msi_mask_conf.msi_mask_bits.vec1_off = NGE_CLEAR; 601 msi_mask_conf.msi_mask_bits.vec2_off = NGE_CLEAR; 602 msi_mask_conf.msi_mask_bits.vec3_off = NGE_CLEAR; 603 msi_mask_conf.msi_mask_bits.vec4_off = NGE_CLEAR; 604 msi_mask_conf.msi_mask_bits.vec5_off = NGE_CLEAR; 605 msi_mask_conf.msi_mask_bits.vec6_off = NGE_CLEAR; 606 msi_mask_conf.msi_mask_bits.vec7_off = NGE_CLEAR; 607 pci_config_put32(handle, PCI_CONF_HT_MSI_MASK, 608 msi_mask_conf.msi_mask_conf_val); 609 610 /* Enable the MSI mapping */ 611 cap_conf.msi_map_cap_conf_val = 612 pci_config_get32(handle, PCI_CONF_HT_MSI_MAP_CAP); 613 cap_conf.map_cap_conf_bits.map_en = NGE_SET; 614 pci_config_put32(handle, PCI_CONF_HT_MSI_MAP_CAP, 615 cap_conf.msi_map_cap_conf_val); 616 } 617 } else { 618 interbus_conf.conf_val = pci_config_get32(handle, 619 PCI_CONF_HT_INTERNAL); 620 interbus_conf.conf_bits.msi_off = NGE_SET; 621 pci_config_put32(handle, PCI_CONF_HT_INTERNAL, 622 interbus_conf.conf_val); 623 } 624 command = infop->command | PCI_COMM_MAE; 625 command &= ~PCI_COMM_MEMWR_INVAL; 626 command |= PCI_COMM_ME; 627 pci_config_put16(handle, PCI_CONF_COMM, command); 628 pci_config_put16(handle, PCI_CONF_STAT, ~0); 629 630 } 631 632 int 633 nge_chip_stop(nge_t *ngep, boolean_t fault) 634 { 635 int err; 636 uint32_t reg_val; 637 uint32_t tries; 638 nge_mintr_src mintr_src; 639 nge_mii_cs mii_cs; 640 nge_rx_poll rx_poll; 641 nge_tx_poll tx_poll; 642 nge_rx_en rx_en; 643 nge_tx_en tx_en; 644 nge_tx_sta tx_sta; 645 nge_rx_sta rx_sta; 646 nge_mode_cntl mode; 647 nge_pmu_cntl2 pmu_cntl2; 648 649 NGE_TRACE(("nge_chip_stop($%p, %d)", (void *)ngep, fault)); 650 651 err = DDI_SUCCESS; 652 653 /* Clear any pending PHY interrupt */ 654 mintr_src.src_val = nge_reg_get8(ngep, NGE_MINTR_SRC); 655 nge_reg_put8(ngep, NGE_MINTR_SRC, mintr_src.src_val); 656 657 /* Mask all interrupts */ 658 reg_val = nge_reg_get32(ngep, NGE_INTR_MASK); 659 reg_val &= ~NGE_INTR_ALL_EN; 660 nge_reg_put32(ngep, NGE_INTR_MASK, reg_val); 661 662 /* Disable auto-polling of phy */ 663 mii_cs.cs_val = nge_reg_get32(ngep, NGE_MII_CS); 664 mii_cs.cs_bits.ap_en = NGE_CLEAR; 665 nge_reg_put32(ngep, NGE_MII_CS, mii_cs.cs_val); 666 667 /* Reset buffer management & DMA */ 668 mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 669 mode.mode_bits.dma_dis = NGE_SET; 670 mode.mode_bits.desc_type = ngep->desc_mode; 671 nge_reg_put32(ngep, NGE_MODE_CNTL, mode.mode_val); 672 673 for (tries = 0; tries < 10000; tries++) { 674 drv_usecwait(10); 675 mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 676 if (mode.mode_bits.dma_status == NGE_SET) 677 break; 678 } 679 if (tries == 10000) { 680 ngep->nge_chip_state = NGE_CHIP_FAULT; 681 return (DDI_FAILURE); 682 } 683 684 /* 685 * For mcp55, the bits 1:31 of NGE_RX_EN and NGE_TX_EN are 686 * defined to be used by SMU. The newer PXE than 527 began to 687 * support SMU and bit 24 of NGE_RX_EN/NGE_TX_EN are set 688 * when leaving PXE to prevents the MAC from winning 689 * arbitration to the main transmit/receive channels. 690 */ 691 if (ngep->chipinfo.device == DEVICE_ID_MCP55_373 || 692 ngep->chipinfo.device == DEVICE_ID_MCP55_372) { 693 694 /* Disable rx's machine */ 695 nge_reg_put32(ngep, NGE_RX_EN, 0x0); 696 697 /* Disable tx's machine */ 698 nge_reg_put32(ngep, NGE_TX_EN, 0x0); 699 } else { 700 701 /* Disable rx's machine */ 702 rx_en.val = nge_reg_get8(ngep, NGE_RX_EN); 703 rx_en.bits.rx_en = NGE_CLEAR; 704 nge_reg_put8(ngep, NGE_RX_EN, rx_en.val); 705 706 707 /* Disable tx's machine */ 708 tx_en.val = nge_reg_get8(ngep, NGE_TX_EN); 709 tx_en.bits.tx_en = NGE_CLEAR; 710 nge_reg_put8(ngep, NGE_TX_EN, tx_en.val); 711 } 712 713 /* 714 * Clean the status of tx's state machine 715 * and Make assure the tx's channel is idle 716 */ 717 tx_sta.sta_val = nge_reg_get32(ngep, NGE_TX_STA); 718 for (tries = 0; tries < 1000; tries++) { 719 if (tx_sta.sta_bits.tx_chan_sta == NGE_CLEAR) 720 break; 721 drv_usecwait(10); 722 tx_sta.sta_val = nge_reg_get32(ngep, NGE_TX_STA); 723 } 724 if (tries == 1000) { 725 ngep->nge_chip_state = NGE_CHIP_FAULT; 726 return (DDI_FAILURE); 727 } 728 nge_reg_put32(ngep, NGE_TX_STA, tx_sta.sta_val); 729 730 /* 731 * Clean the status of rx's state machine 732 * and Make assure the tx's channel is idle 733 */ 734 rx_sta.sta_val = nge_reg_get32(ngep, NGE_RX_STA); 735 for (tries = 0; tries < 1000; tries++) { 736 if (rx_sta.sta_bits.rx_chan_sta == NGE_CLEAR) 737 break; 738 drv_usecwait(10); 739 rx_sta.sta_val = nge_reg_get32(ngep, NGE_RX_STA); 740 } 741 if (tries == 1000) { 742 ngep->nge_chip_state = NGE_CHIP_FAULT; 743 return (DDI_FAILURE); 744 } 745 nge_reg_put32(ngep, NGE_RX_STA, rx_sta.sta_val); 746 747 /* Disable auto-poll of rx's state machine */ 748 rx_poll.poll_val = nge_reg_get32(ngep, NGE_RX_POLL); 749 rx_poll.poll_bits.rpen = NGE_CLEAR; 750 rx_poll.poll_bits.rpi = NGE_CLEAR; 751 nge_reg_put32(ngep, NGE_RX_POLL, rx_poll.poll_val); 752 753 /* Disable auto-polling of tx's state machine */ 754 tx_poll.poll_val = nge_reg_get32(ngep, NGE_TX_POLL); 755 tx_poll.poll_bits.tpen = NGE_CLEAR; 756 tx_poll.poll_bits.tpi = NGE_CLEAR; 757 nge_reg_put32(ngep, NGE_TX_POLL, tx_poll.poll_val); 758 759 /* Restore buffer management */ 760 mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 761 mode.mode_bits.bm_reset = NGE_SET; 762 mode.mode_bits.tx_rcom_en = NGE_SET; 763 nge_reg_put32(ngep, NGE_MODE_CNTL, mode.mode_val); 764 765 if (ngep->dev_spec_param.advanced_pm) { 766 767 nge_reg_put32(ngep, NGE_PMU_CIDLE_LIMIT, 0); 768 nge_reg_put32(ngep, NGE_PMU_DIDLE_LIMIT, 0); 769 770 pmu_cntl2.cntl2_val = nge_reg_get32(ngep, NGE_PMU_CNTL2); 771 pmu_cntl2.cntl2_bits.cidle_timer = NGE_CLEAR; 772 pmu_cntl2.cntl2_bits.didle_timer = NGE_CLEAR; 773 nge_reg_put32(ngep, NGE_PMU_CNTL2, pmu_cntl2.cntl2_val); 774 } 775 if (fault) 776 ngep->nge_chip_state = NGE_CHIP_FAULT; 777 else 778 ngep->nge_chip_state = NGE_CHIP_STOPPED; 779 780 return (err); 781 } 782 783 static void 784 nge_rx_setup(nge_t *ngep) 785 { 786 uint64_t desc_addr; 787 nge_rxtx_dlen dlen; 788 nge_rx_poll rx_poll; 789 790 /* 791 * Filling the address and length of rx's descriptors 792 */ 793 desc_addr = ngep->recv->desc.cookie.dmac_laddress; 794 nge_reg_put32(ngep, NGE_RX_DADR, desc_addr); 795 nge_reg_put32(ngep, NGE_RX_DADR_HI, desc_addr >> 32); 796 dlen.dlen_val = nge_reg_get32(ngep, NGE_RXTX_DLEN); 797 dlen.dlen_bits.rdlen = ngep->recv->desc.nslots - 1; 798 nge_reg_put32(ngep, NGE_RXTX_DLEN, dlen.dlen_val); 799 800 rx_poll.poll_val = nge_reg_get32(ngep, NGE_RX_POLL); 801 rx_poll.poll_bits.rpi = RX_POLL_INTV_1G; 802 rx_poll.poll_bits.rpen = NGE_SET; 803 nge_reg_put32(ngep, NGE_RX_POLL, rx_poll.poll_val); 804 } 805 806 static void 807 nge_tx_setup(nge_t *ngep) 808 { 809 uint64_t desc_addr; 810 nge_rxtx_dlen dlen; 811 812 /* 813 * Filling the address and length of tx's descriptors 814 */ 815 desc_addr = ngep->send->desc.cookie.dmac_laddress; 816 nge_reg_put32(ngep, NGE_TX_DADR, desc_addr); 817 nge_reg_put32(ngep, NGE_TX_DADR_HI, desc_addr >> 32); 818 dlen.dlen_val = nge_reg_get32(ngep, NGE_RXTX_DLEN); 819 dlen.dlen_bits.tdlen = ngep->send->desc.nslots - 1; 820 nge_reg_put32(ngep, NGE_RXTX_DLEN, dlen.dlen_val); 821 } 822 823 static int 824 nge_buff_setup(nge_t *ngep) 825 { 826 nge_mode_cntl mode_cntl; 827 nge_dev_spec_param_t *dev_param_p; 828 829 dev_param_p = &ngep->dev_spec_param; 830 831 /* 832 * Configure Rx&Tx's buffer 833 */ 834 nge_rx_setup(ngep); 835 nge_tx_setup(ngep); 836 837 /* 838 * Configure buffer attribute 839 */ 840 mode_cntl.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 841 842 /* 843 * Enable Dma access request 844 */ 845 mode_cntl.mode_bits.dma_dis = NGE_CLEAR; 846 847 /* 848 * Enbale Buffer management 849 */ 850 mode_cntl.mode_bits.bm_reset = NGE_CLEAR; 851 852 /* 853 * Support Standoffload Descriptor 854 */ 855 mode_cntl.mode_bits.desc_type = ngep->desc_mode; 856 857 /* 858 * Support receive hardware checksum 859 */ 860 if (dev_param_p->rx_hw_checksum) { 861 mode_cntl.mode_bits.rx_sum_en = NGE_SET; 862 } else 863 mode_cntl.mode_bits.rx_sum_en = NGE_CLEAR; 864 865 /* 866 * Disable Tx PRD coarse update 867 */ 868 mode_cntl.mode_bits.tx_prd_cu_en = NGE_CLEAR; 869 870 /* 871 * Disable 64-byte access 872 */ 873 mode_cntl.mode_bits.w64_dis = NGE_SET; 874 875 /* 876 * Skip Rx Error Frame is not supported and if 877 * enable it, jumbo frame does not work any more. 878 */ 879 mode_cntl.mode_bits.rx_filter_en = NGE_CLEAR; 880 881 /* 882 * Can not support hot mode now 883 */ 884 mode_cntl.mode_bits.resv15 = NGE_CLEAR; 885 886 if (dev_param_p->vlan) { 887 /* Disable the vlan strip for devices which support vlan */ 888 mode_cntl.mode_bits.vlan_strip = NGE_CLEAR; 889 890 /* Disable the vlan insert for devices which supprot vlan */ 891 mode_cntl.mode_bits.vlan_ins = NGE_CLEAR; 892 } 893 894 if (dev_param_p->tx_rx_64byte) { 895 896 /* Set the maximum TX PRD fetch size to 64 bytes */ 897 mode_cntl.mode_bits.tx_fetch_prd = NGE_SET; 898 899 /* Set the maximum RX PRD fetch size to 64 bytes */ 900 mode_cntl.mode_bits.rx_fetch_prd = NGE_SET; 901 } 902 /* 903 * Upload Rx data as it arrives, rather than waiting for full frame 904 */ 905 mode_cntl.mode_bits.resv16 = NGE_CLEAR; 906 907 /* 908 * Normal HOT table accesses 909 */ 910 mode_cntl.mode_bits.resv17 = NGE_CLEAR; 911 912 /* 913 * Normal HOT buffer requesting 914 */ 915 mode_cntl.mode_bits.resv18 = NGE_CLEAR; 916 nge_reg_put32(ngep, NGE_MODE_CNTL, mode_cntl.mode_val); 917 918 /* 919 * Signal controller to check for new Rx descriptors 920 */ 921 mode_cntl.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL); 922 mode_cntl.mode_bits.rxdm = NGE_SET; 923 mode_cntl.mode_bits.tx_rcom_en = NGE_SET; 924 nge_reg_put32(ngep, NGE_MODE_CNTL, mode_cntl.mode_val); 925 926 927 return (DDI_SUCCESS); 928 } 929 930 /* 931 * When chipset resets, the chipset can not restore the orignial 932 * mac address to the mac address registers. 933 * 934 * When the driver is dettached, the function will write the orignial 935 * mac address to the mac address registers. 936 */ 937 938 void 939 nge_restore_mac_addr(nge_t *ngep) 940 { 941 uint32_t mac_addr; 942 943 mac_addr = (uint32_t)ngep->chipinfo.hw_mac_addr; 944 nge_reg_put32(ngep, NGE_UNI_ADDR0, mac_addr); 945 mac_addr = (uint32_t)(ngep->chipinfo.hw_mac_addr >> 32); 946 nge_reg_put32(ngep, NGE_UNI_ADDR1, mac_addr); 947 } 948 949 int 950 nge_chip_reset(nge_t *ngep) 951 { 952 int err; 953 uint8_t i; 954 uint32_t regno; 955 uint64_t mac; 956 nge_uni_addr1 uaddr1; 957 nge_cp_cntl ee_cntl; 958 nge_soft_misc soft_misc; 959 nge_pmu_cntl0 pmu_cntl0; 960 nge_pmu_cntl2 pmu_cntl2; 961 nge_pm_cntl2 pm_cntl2; 962 const nge_ksindex_t *ksip; 963 964 NGE_TRACE(("nge_chip_reset($%p)", (void *)ngep)); 965 966 /* 967 * Clear the statistics by reading the statistics register 968 */ 969 for (ksip = nge_statistics; ksip->name != NULL; ++ksip) { 970 regno = KS_BASE + ksip->index * sizeof (uint32_t); 971 (void) nge_reg_get32(ngep, regno); 972 } 973 974 /* 975 * Setup seeprom control 976 */ 977 ee_cntl.cntl_val = nge_reg_get32(ngep, NGE_EP_CNTL); 978 ee_cntl.cntl_bits.clkdiv = EEPROM_CLKDIV; 979 ee_cntl.cntl_bits.rom_size = EEPROM_32K; 980 ee_cntl.cntl_bits.word_wid = ACCESS_16BIT; 981 ee_cntl.cntl_bits.wait_slots = EEPROM_WAITCLK; 982 nge_reg_put32(ngep, NGE_EP_CNTL, ee_cntl.cntl_val); 983 984 /* 985 * Reading the unicast mac address table 986 */ 987 if (ngep->nge_chip_state == NGE_CHIP_INITIAL) { 988 uaddr1.addr_val = nge_reg_get32(ngep, NGE_UNI_ADDR1); 989 mac = uaddr1.addr_bits.addr; 990 mac <<= 32; 991 mac |= nge_reg_get32(ngep, NGE_UNI_ADDR0); 992 if (mac != 0ULL && mac != ~0ULL) { 993 ngep->chipinfo.hw_mac_addr = mac; 994 for (i = ETHERADDRL; i-- != 0; ) { 995 ngep->chipinfo.vendor_addr.addr[i] = 996 (uchar_t)mac; 997 ngep->cur_uni_addr.addr[i] = (uchar_t)mac; 998 mac >>= 8; 999 } 1000 ngep->chipinfo.vendor_addr.set = 1; 1001 } 1002 } 1003 pci_config_put8(ngep->cfg_handle, PCI_CONF_CACHE_LINESZ, 1004 ngep->chipinfo.clsize); 1005 pci_config_put8(ngep->cfg_handle, PCI_CONF_LATENCY_TIMER, 1006 ngep->chipinfo.latency); 1007 1008 1009 if (ngep->dev_spec_param.advanced_pm) { 1010 1011 /* Program software misc register */ 1012 soft_misc.misc_val = nge_reg_get32(ngep, NGE_SOFT_MISC); 1013 soft_misc.misc_bits.rx_clk_vx_rst = NGE_SET; 1014 soft_misc.misc_bits.tx_clk_vx_rst = NGE_SET; 1015 soft_misc.misc_bits.clk12m_vx_rst = NGE_SET; 1016 soft_misc.misc_bits.fpci_clk_vx_rst = NGE_SET; 1017 soft_misc.misc_bits.rx_clk_vc_rst = NGE_SET; 1018 soft_misc.misc_bits.tx_clk_vc_rst = NGE_SET; 1019 soft_misc.misc_bits.fs_clk_vc_rst = NGE_SET; 1020 soft_misc.misc_bits.rst_ex_m2pintf = NGE_SET; 1021 nge_reg_put32(ngep, NGE_SOFT_MISC, soft_misc.misc_val); 1022 1023 /* wait for 32 us */ 1024 drv_usecwait(32); 1025 1026 soft_misc.misc_val = nge_reg_get32(ngep, NGE_SOFT_MISC); 1027 soft_misc.misc_bits.rx_clk_vx_rst = NGE_CLEAR; 1028 soft_misc.misc_bits.tx_clk_vx_rst = NGE_CLEAR; 1029 soft_misc.misc_bits.clk12m_vx_rst = NGE_CLEAR; 1030 soft_misc.misc_bits.fpci_clk_vx_rst = NGE_CLEAR; 1031 soft_misc.misc_bits.rx_clk_vc_rst = NGE_CLEAR; 1032 soft_misc.misc_bits.tx_clk_vc_rst = NGE_CLEAR; 1033 soft_misc.misc_bits.fs_clk_vc_rst = NGE_CLEAR; 1034 soft_misc.misc_bits.rst_ex_m2pintf = NGE_CLEAR; 1035 nge_reg_put32(ngep, NGE_SOFT_MISC, soft_misc.misc_val); 1036 1037 /* Program PMU registers */ 1038 pmu_cntl0.cntl0_val = nge_reg_get32(ngep, NGE_PMU_CNTL0); 1039 pmu_cntl0.cntl0_bits.core_spd10_fp = 1040 NGE_PMU_CORE_SPD10_BUSY; 1041 pmu_cntl0.cntl0_bits.core_spd10_idle = 1042 NGE_PMU_CORE_SPD10_IDLE; 1043 pmu_cntl0.cntl0_bits.core_spd100_fp = 1044 NGE_PMU_CORE_SPD100_BUSY; 1045 pmu_cntl0.cntl0_bits.core_spd100_idle = 1046 NGE_PMU_CORE_SPD100_IDLE; 1047 pmu_cntl0.cntl0_bits.core_spd1000_fp = 1048 NGE_PMU_CORE_SPD1000_BUSY; 1049 pmu_cntl0.cntl0_bits.core_spd1000_idle = 1050 NGE_PMU_CORE_SPD100_IDLE; 1051 pmu_cntl0.cntl0_bits.core_spd10_idle = 1052 NGE_PMU_CORE_SPD10_IDLE; 1053 nge_reg_put32(ngep, NGE_PMU_CNTL0, pmu_cntl0.cntl0_val); 1054 1055 /* Set the core idle limit value */ 1056 nge_reg_put32(ngep, NGE_PMU_CIDLE_LIMIT, 1057 NGE_PMU_CIDLE_LIMIT_DEF); 1058 1059 /* Set the device idle limit value */ 1060 nge_reg_put32(ngep, NGE_PMU_DIDLE_LIMIT, 1061 NGE_PMU_DIDLE_LIMIT_DEF); 1062 1063 /* Enable the core/device idle timer in PMU control 2 */ 1064 pmu_cntl2.cntl2_val = nge_reg_get32(ngep, NGE_PMU_CNTL2); 1065 pmu_cntl2.cntl2_bits.cidle_timer = NGE_SET; 1066 pmu_cntl2.cntl2_bits.didle_timer = NGE_SET; 1067 pmu_cntl2.cntl2_bits.core_enable = NGE_SET; 1068 pmu_cntl2.cntl2_bits.dev_enable = NGE_SET; 1069 nge_reg_put32(ngep, NGE_PMU_CNTL2, pmu_cntl2.cntl2_val); 1070 } 1071 /* 1072 * Stop the chipset and clear buffer management 1073 */ 1074 err = nge_chip_stop(ngep, B_FALSE); 1075 if (err == DDI_FAILURE) 1076 return (err); 1077 /* 1078 * Clear the power state bits for phy since interface no longer 1079 * works after rebooting from Windows on a multi-boot machine 1080 */ 1081 if (ngep->chipinfo.device == DEVICE_ID_MCP51_268 || 1082 ngep->chipinfo.device == DEVICE_ID_MCP51_269 || 1083 ngep->chipinfo.device == DEVICE_ID_MCP55_372 || 1084 ngep->chipinfo.device == DEVICE_ID_MCP55_373 || 1085 ngep->chipinfo.device == DEVICE_ID_MCP61_3EE || 1086 ngep->chipinfo.device == DEVICE_ID_MCP61_3EF) { 1087 1088 pm_cntl2.cntl_val = nge_reg_get32(ngep, NGE_PM_CNTL2); 1089 /* bring phy out of coma mode */ 1090 pm_cntl2.cntl_bits.phy_coma_set = NGE_CLEAR; 1091 /* disable auto reset coma bits */ 1092 pm_cntl2.cntl_bits.resv4 = NGE_CLEAR; 1093 /* restore power to gated clocks */ 1094 pm_cntl2.cntl_bits.resv8_11 = NGE_CLEAR; 1095 nge_reg_put32(ngep, NGE_PM_CNTL2, pm_cntl2.cntl_val); 1096 } 1097 1098 /* 1099 * Reset the external phy 1100 */ 1101 if (!nge_phy_reset(ngep)) 1102 return (DDI_FAILURE); 1103 ngep->nge_chip_state = NGE_CHIP_RESET; 1104 return (DDI_SUCCESS); 1105 } 1106 1107 int 1108 nge_chip_start(nge_t *ngep) 1109 { 1110 int err; 1111 nge_itc itc; 1112 nge_tx_cntl tx_cntl; 1113 nge_rx_cntrl0 rx_cntl0; 1114 nge_rx_cntl1 rx_cntl1; 1115 nge_tx_en tx_en; 1116 nge_rx_en rx_en; 1117 nge_mii_cs mii_cs; 1118 nge_swtr_cntl swtr_cntl; 1119 nge_rx_fifo_wm rx_fifo; 1120 nge_intr_mask intr_mask; 1121 nge_mintr_mask mintr_mask; 1122 nge_dev_spec_param_t *dev_param_p; 1123 1124 NGE_TRACE(("nge_chip_start($%p)", (void *)ngep)); 1125 1126 /* 1127 * Setup buffer management 1128 */ 1129 err = nge_buff_setup(ngep); 1130 if (err == DDI_FAILURE) 1131 return (err); 1132 1133 dev_param_p = &ngep->dev_spec_param; 1134 1135 /* 1136 * Enable polling attribute 1137 */ 1138 mii_cs.cs_val = nge_reg_get32(ngep, NGE_MII_CS); 1139 mii_cs.cs_bits.ap_paddr = ngep->phy_xmii_addr; 1140 mii_cs.cs_bits.ap_en = NGE_SET; 1141 mii_cs.cs_bits.ap_intv = MII_POLL_INTV; 1142 nge_reg_put32(ngep, NGE_MII_CS, mii_cs.cs_val); 1143 1144 /* 1145 * Setup link 1146 */ 1147 (*ngep->physops->phys_update)(ngep); 1148 1149 /* 1150 * Configure the tx's parameters 1151 */ 1152 tx_cntl.cntl_val = nge_reg_get32(ngep, NGE_TX_CNTL); 1153 if (dev_param_p->tx_pause_frame) 1154 tx_cntl.cntl_bits.paen = NGE_SET; 1155 else 1156 tx_cntl.cntl_bits.paen = NGE_CLEAR; 1157 tx_cntl.cntl_bits.retry_en = NGE_SET; 1158 tx_cntl.cntl_bits.pad_en = NGE_SET; 1159 tx_cntl.cntl_bits.fappend_en = NGE_SET; 1160 tx_cntl.cntl_bits.two_def_en = NGE_SET; 1161 tx_cntl.cntl_bits.max_retry = 15; 1162 tx_cntl.cntl_bits.burst_en = NGE_CLEAR; 1163 tx_cntl.cntl_bits.uflo_err_mask = NGE_CLEAR; 1164 tx_cntl.cntl_bits.tlcol_mask = NGE_CLEAR; 1165 tx_cntl.cntl_bits.lcar_mask = NGE_CLEAR; 1166 tx_cntl.cntl_bits.def_mask = NGE_CLEAR; 1167 tx_cntl.cntl_bits.exdef_mask = NGE_SET; 1168 tx_cntl.cntl_bits.lcar_mask = NGE_SET; 1169 tx_cntl.cntl_bits.tlcol_mask = NGE_SET; 1170 tx_cntl.cntl_bits.uflo_err_mask = NGE_SET; 1171 tx_cntl.cntl_bits.jam_seq_en = NGE_CLEAR; 1172 nge_reg_put32(ngep, NGE_TX_CNTL, tx_cntl.cntl_val); 1173 1174 1175 /* 1176 * Configure the parameters of Rx's state machine 1177 * Enabe the parameters: 1178 * 1). Pad Strip 1179 * 2). FCS Relay 1180 * 3). Pause 1181 * 4). Address filter 1182 * 5). Runt Packet receive 1183 * 6). Broadcast 1184 * 7). Receive Deferral 1185 * 1186 * Disable the following parameters for decreasing 1187 * the number of interrupts: 1188 * 1). Runt Inerrupt. 1189 * 2). Rx's Late Collision interrupt. 1190 * 3). Rx's Max length Error Interrupt. 1191 * 4). Rx's Length Field error Interrupt. 1192 * 5). Rx's FCS error interrupt. 1193 * 6). Rx's overflow error interrupt. 1194 * 7). Rx's Frame alignment error interrupt. 1195 */ 1196 rx_cntl0.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0); 1197 rx_cntl0.cntl_bits.padsen = NGE_CLEAR; 1198 rx_cntl0.cntl_bits.fcsren = NGE_CLEAR; 1199 if (dev_param_p->rx_pause_frame) 1200 rx_cntl0.cntl_bits.paen = NGE_SET; 1201 else 1202 rx_cntl0.cntl_bits.paen = NGE_CLEAR; 1203 rx_cntl0.cntl_bits.lben = NGE_CLEAR; 1204 rx_cntl0.cntl_bits.afen = NGE_SET; 1205 rx_cntl0.cntl_bits.runten = NGE_CLEAR; 1206 rx_cntl0.cntl_bits.brdis = NGE_CLEAR; 1207 rx_cntl0.cntl_bits.rdfen = NGE_CLEAR; 1208 rx_cntl0.cntl_bits.runtm = NGE_CLEAR; 1209 rx_cntl0.cntl_bits.slfb = NGE_CLEAR; 1210 rx_cntl0.cntl_bits.rlcolm = NGE_CLEAR; 1211 rx_cntl0.cntl_bits.maxerm = NGE_CLEAR; 1212 rx_cntl0.cntl_bits.lferm = NGE_CLEAR; 1213 rx_cntl0.cntl_bits.crcm = NGE_CLEAR; 1214 rx_cntl0.cntl_bits.ofolm = NGE_CLEAR; 1215 rx_cntl0.cntl_bits.framerm = NGE_CLEAR; 1216 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val); 1217 1218 /* 1219 * Configure the watermark for the rx's statemachine 1220 */ 1221 rx_fifo.wm_val = nge_reg_get32(ngep, NGE_RX_FIFO_WM); 1222 rx_fifo.wm_bits.data_hwm = ngep->rx_datahwm; 1223 rx_fifo.wm_bits.prd_lwm = ngep->rx_prdlwm; 1224 rx_fifo.wm_bits.prd_hwm = ngep->rx_prdhwm; 1225 nge_reg_put32(ngep, NGE_RX_FIFO_WM, rx_fifo.wm_val); 1226 1227 /* 1228 * Configure the deffer time slot for rx's state machine 1229 */ 1230 nge_reg_put8(ngep, NGE_RX_DEf, ngep->rx_def); 1231 1232 /* 1233 * Configure the length of rx's packet 1234 */ 1235 rx_cntl1.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL1); 1236 rx_cntl1.cntl_bits.length = ngep->max_sdu; 1237 nge_reg_put32(ngep, NGE_RX_CNTL1, rx_cntl1.cntl_val); 1238 /* 1239 * Enable Tx's state machine 1240 */ 1241 tx_en.val = nge_reg_get8(ngep, NGE_TX_EN); 1242 tx_en.bits.tx_en = NGE_SET; 1243 nge_reg_put8(ngep, NGE_TX_EN, tx_en.val); 1244 1245 /* 1246 * Enable Rx's state machine 1247 */ 1248 rx_en.val = nge_reg_get8(ngep, NGE_RX_EN); 1249 rx_en.bits.rx_en = NGE_SET; 1250 nge_reg_put8(ngep, NGE_RX_EN, rx_en.val); 1251 1252 itc.itc_val = nge_reg_get32(ngep, NGE_SWTR_ITC); 1253 itc.itc_bits.sw_intv = ngep->sw_intr_intv; 1254 nge_reg_put32(ngep, NGE_SWTR_ITC, itc.itc_val); 1255 1256 swtr_cntl.ctrl_val = nge_reg_get8(ngep, NGE_SWTR_CNTL); 1257 swtr_cntl.cntl_bits.sten = NGE_SET; 1258 swtr_cntl.cntl_bits.stren = NGE_SET; 1259 nge_reg_put32(ngep, NGE_SWTR_CNTL, swtr_cntl.ctrl_val); 1260 1261 /* 1262 * Disable all mii read/write operation Interrupt 1263 */ 1264 mintr_mask.mask_val = nge_reg_get8(ngep, NGE_MINTR_MASK); 1265 mintr_mask.mask_bits.mrei = NGE_CLEAR; 1266 mintr_mask.mask_bits.mcc2 = NGE_CLEAR; 1267 mintr_mask.mask_bits.mcc1 = NGE_CLEAR; 1268 mintr_mask.mask_bits.mapi = NGE_SET; 1269 mintr_mask.mask_bits.mpdi = NGE_SET; 1270 nge_reg_put8(ngep, NGE_MINTR_MASK, mintr_mask.mask_val); 1271 1272 /* 1273 * Enable all interrupt event 1274 */ 1275 intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK); 1276 intr_mask.mask_bits.reint = NGE_SET; 1277 intr_mask.mask_bits.rcint = NGE_SET; 1278 intr_mask.mask_bits.miss = NGE_SET; 1279 intr_mask.mask_bits.teint = NGE_CLEAR; 1280 intr_mask.mask_bits.tcint = NGE_SET; 1281 intr_mask.mask_bits.stint = NGE_CLEAR; 1282 intr_mask.mask_bits.mint = NGE_CLEAR; 1283 intr_mask.mask_bits.rfint = NGE_CLEAR; 1284 intr_mask.mask_bits.tfint = NGE_CLEAR; 1285 intr_mask.mask_bits.feint = NGE_SET; 1286 intr_mask.mask_bits.resv10 = NGE_CLEAR; 1287 intr_mask.mask_bits.resv11 = NGE_CLEAR; 1288 intr_mask.mask_bits.resv12 = NGE_CLEAR; 1289 intr_mask.mask_bits.resv13 = NGE_CLEAR; 1290 intr_mask.mask_bits.phyint = NGE_CLEAR; 1291 ngep->intr_masks = intr_mask.mask_val; 1292 nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val); 1293 ngep->nge_chip_state = NGE_CHIP_RUNNING; 1294 return (DDI_SUCCESS); 1295 } 1296 1297 /* 1298 * nge_chip_sync() -- program the chip with the unicast MAC address, 1299 * the multicast hash table, the required level of promiscuity. 1300 */ 1301 void 1302 nge_chip_sync(nge_t *ngep) 1303 { 1304 uint8_t i; 1305 uint64_t macaddr; 1306 uint64_t mul_addr; 1307 uint64_t mul_mask; 1308 nge_rx_cntrl0 rx_cntl; 1309 nge_uni_addr1 uni_adr1; 1310 1311 NGE_TRACE(("nge_chip_sync($%p)", (void *)ngep)); 1312 1313 macaddr = 0x0ull; 1314 mul_addr = 0x0ull; 1315 mul_mask = 0x0ull; 1316 rx_cntl.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0); 1317 1318 if (ngep->promisc) { 1319 rx_cntl.cntl_bits.afen = NGE_CLEAR; 1320 rx_cntl.cntl_bits.brdis = NGE_SET; 1321 } else { 1322 rx_cntl.cntl_bits.afen = NGE_SET; 1323 rx_cntl.cntl_bits.brdis = NGE_CLEAR; 1324 } 1325 1326 /* 1327 * Transform the MAC address from host to chip format, the unicast 1328 * MAC address(es) ... 1329 */ 1330 for (i = ETHERADDRL, macaddr = 0ull; i != 0; --i) { 1331 macaddr |= ngep->cur_uni_addr.addr[i-1]; 1332 macaddr <<= (i > 1) ? 8 : 0; 1333 } 1334 1335 nge_reg_put32(ngep, NGE_UNI_ADDR0, (uint32_t)macaddr); 1336 macaddr = macaddr >>32; 1337 uni_adr1.addr_val = nge_reg_get32(ngep, NGE_UNI_ADDR1); 1338 uni_adr1.addr_bits.addr = (uint16_t)macaddr; 1339 uni_adr1.addr_bits.resv16_31 = (uint16_t)0; 1340 nge_reg_put32(ngep, NGE_UNI_ADDR1, uni_adr1.addr_val); 1341 1342 /* 1343 * Reprogram the multicast address table ... 1344 */ 1345 for (i = ETHERADDRL, mul_addr = 0ull; i != 0; --i) { 1346 mul_addr |= ngep->cur_mul_addr.addr[i-1]; 1347 mul_addr <<= (i > 1) ? 8 : 0; 1348 mul_mask |= ngep->cur_mul_mask.addr[i-1]; 1349 mul_mask <<= (i > 1) ? 8 : 0; 1350 } 1351 nge_reg_put32(ngep, NGE_MUL_ADDR0, (uint32_t)mul_addr); 1352 mul_addr >>= 32; 1353 nge_reg_put32(ngep, NGE_MUL_ADDR1, mul_addr); 1354 nge_reg_put32(ngep, NGE_MUL_MASK, (uint32_t)mul_mask); 1355 mul_mask >>= 32; 1356 nge_reg_put32(ngep, NGE_MUL_MASK1, mul_mask); 1357 /* 1358 * Set or clear the PROMISCUOUS mode bit 1359 */ 1360 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl.cntl_val); 1361 /* 1362 * For internal PHY loopback, the link will 1363 * not be up, so it need to sync mac modes directly. 1364 */ 1365 if (ngep->param_loop_mode == NGE_LOOP_INTERNAL_PHY) 1366 nge_sync_mac_modes(ngep); 1367 } 1368 1369 static void 1370 nge_chip_err(nge_t *ngep) 1371 { 1372 nge_reg010 reg010_ins; 1373 nge_sw_statistics_t *psw_stat; 1374 nge_intr_mask intr_mask; 1375 1376 NGE_TRACE(("nge_chip_err($%p)", (void *)ngep)); 1377 1378 psw_stat = (nge_sw_statistics_t *)&ngep->statistics.sw_statistics; 1379 reg010_ins.reg010_val = nge_reg_get32(ngep, NGE_REG010); 1380 if (reg010_ins.reg010_bits.resv0) 1381 psw_stat->fe_err.tso_err_mss ++; 1382 1383 if (reg010_ins.reg010_bits.resv1) 1384 psw_stat->fe_err.tso_dis ++; 1385 1386 if (reg010_ins.reg010_bits.resv2) 1387 psw_stat->fe_err.tso_err_nosum ++; 1388 1389 if (reg010_ins.reg010_bits.resv3) 1390 psw_stat->fe_err.tso_err_hov ++; 1391 1392 if (reg010_ins.reg010_bits.resv4) 1393 psw_stat->fe_err.tso_err_huf ++; 1394 1395 if (reg010_ins.reg010_bits.resv5) 1396 psw_stat->fe_err.tso_err_l2 ++; 1397 1398 if (reg010_ins.reg010_bits.resv6) 1399 psw_stat->fe_err.tso_err_ip ++; 1400 1401 if (reg010_ins.reg010_bits.resv7) 1402 psw_stat->fe_err.tso_err_l4 ++; 1403 1404 if (reg010_ins.reg010_bits.resv8) 1405 psw_stat->fe_err.tso_err_tcp ++; 1406 1407 if (reg010_ins.reg010_bits.resv9) 1408 psw_stat->fe_err.hsum_err_ip ++; 1409 1410 if (reg010_ins.reg010_bits.resv10) 1411 psw_stat->fe_err.hsum_err_l4 ++; 1412 1413 if (reg010_ins.reg010_val != 0) { 1414 1415 /* 1416 * Fatal error is triggered by malformed driver commands. 1417 * Disable unless debugging. 1418 */ 1419 intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK); 1420 intr_mask.mask_bits.feint = NGE_CLEAR; 1421 nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val); 1422 ngep->intr_masks = intr_mask.mask_val; 1423 1424 } 1425 } 1426 1427 static void 1428 nge_sync_mac_modes(nge_t *ngep) 1429 { 1430 nge_tx_def tx_def; 1431 nge_tx_fifo_wm tx_fifo; 1432 nge_bkoff_cntl bk_cntl; 1433 nge_mac2phy m2p; 1434 nge_rx_cntrl0 rx_cntl0; 1435 nge_dev_spec_param_t *dev_param_p; 1436 1437 dev_param_p = &ngep->dev_spec_param; 1438 1439 tx_def.def_val = nge_reg_get32(ngep, NGE_TX_DEF); 1440 m2p.m2p_val = nge_reg_get32(ngep, NGE_MAC2PHY); 1441 tx_fifo.wm_val = nge_reg_get32(ngep, NGE_TX_FIFO_WM); 1442 bk_cntl.cntl_val = nge_reg_get32(ngep, NGE_BKOFF_CNTL); 1443 bk_cntl.bkoff_bits.rseed = BKOFF_RSEED; 1444 switch (ngep->param_link_speed) { 1445 case 10: 1446 m2p.m2p_bits.speed = low_speed; 1447 tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT; 1448 if (ngep->phy_mode == RGMII_IN) { 1449 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_10_100; 1450 tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER; 1451 } else { 1452 tx_def.def_bits.if_def = TX_TIFG_MII; 1453 tx_def.def_bits.ifg2_def = TX_IFG2_MII; 1454 } 1455 tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_MII; 1456 bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_MII; 1457 break; 1458 1459 case 100: 1460 m2p.m2p_bits.speed = fast_speed; 1461 tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT; 1462 if (ngep->phy_mode == RGMII_IN) { 1463 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_10_100; 1464 tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER; 1465 } else { 1466 tx_def.def_bits.if_def = TX_TIFG_MII; 1467 tx_def.def_bits.ifg2_def = TX_IFG2_MII; 1468 } 1469 tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_MII; 1470 bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_MII; 1471 break; 1472 1473 case 1000: 1474 m2p.m2p_bits.speed = giga_speed; 1475 tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT; 1476 if (ngep->param_link_duplex == LINK_DUPLEX_FULL) { 1477 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_1000; 1478 tx_def.def_bits.if_def = TX_IFG_RGMII_1000_FD; 1479 } else { 1480 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_1000; 1481 tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER; 1482 } 1483 1484 tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_GMII; 1485 bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_GMII; 1486 break; 1487 } 1488 1489 if (ngep->chipinfo.device == DEVICE_ID_MCP55_373 || 1490 ngep->chipinfo.device == DEVICE_ID_MCP55_372) { 1491 m2p.m2p_bits.phyintr = NGE_CLEAR; 1492 m2p.m2p_bits.phyintrlvl = NGE_CLEAR; 1493 } 1494 if (ngep->param_link_duplex == LINK_DUPLEX_HALF) { 1495 m2p.m2p_bits.hdup_en = NGE_SET; 1496 } 1497 else 1498 m2p.m2p_bits.hdup_en = NGE_CLEAR; 1499 nge_reg_put32(ngep, NGE_MAC2PHY, m2p.m2p_val); 1500 nge_reg_put32(ngep, NGE_TX_DEF, tx_def.def_val); 1501 1502 tx_fifo.wm_bits.data_lwm = TX_FIFO_DATA_LWM; 1503 tx_fifo.wm_bits.prd_lwm = TX_FIFO_PRD_LWM; 1504 tx_fifo.wm_bits.uprd_hwm = TX_FIFO_PRD_HWM; 1505 tx_fifo.wm_bits.fb_wm = TX_FIFO_TBFW; 1506 nge_reg_put32(ngep, NGE_TX_FIFO_WM, tx_fifo.wm_val); 1507 1508 nge_reg_put32(ngep, NGE_BKOFF_CNTL, bk_cntl.cntl_val); 1509 1510 rx_cntl0.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0); 1511 if (ngep->param_link_rx_pause && dev_param_p->rx_pause_frame) 1512 rx_cntl0.cntl_bits.paen = NGE_SET; 1513 else 1514 rx_cntl0.cntl_bits.paen = NGE_CLEAR; 1515 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val); 1516 } 1517 1518 /* 1519 * Handler for hardware link state change. 1520 * 1521 * When this routine is called, the hardware link state has changed 1522 * and the new state is reflected in the param_* variables. Here 1523 * we must update the softstate, reprogram the MAC to match, and 1524 * record the change in the log and/or on the console. 1525 */ 1526 static void 1527 nge_factotum_link_handler(nge_t *ngep) 1528 { 1529 /* 1530 * Update the s/w link_state 1531 */ 1532 if (ngep->param_link_up) 1533 ngep->link_state = LINK_STATE_UP; 1534 else 1535 ngep->link_state = LINK_STATE_DOWN; 1536 1537 /* 1538 * Reprogram the MAC modes to match 1539 */ 1540 nge_sync_mac_modes(ngep); 1541 } 1542 1543 static boolean_t 1544 nge_factotum_link_check(nge_t *ngep) 1545 { 1546 boolean_t lchg; 1547 boolean_t check; 1548 1549 ASSERT(mutex_owned(ngep->genlock)); 1550 1551 (*ngep->physops->phys_check)(ngep); 1552 switch (ngep->link_state) { 1553 case LINK_STATE_UP: 1554 lchg = (ngep->param_link_up == B_FALSE); 1555 check = (ngep->param_link_up == B_FALSE); 1556 break; 1557 1558 case LINK_STATE_DOWN: 1559 lchg = (ngep->param_link_up == B_TRUE); 1560 check = (ngep->param_link_up == B_TRUE); 1561 break; 1562 1563 default: 1564 check = B_TRUE; 1565 break; 1566 } 1567 1568 /* 1569 * If <check> is false, we're sure the link hasn't changed. 1570 * If true, however, it's not yet definitive; we have to call 1571 * nge_phys_check() to determine whether the link has settled 1572 * into a new state yet ... and if it has, then call the link 1573 * state change handler.But when the chip is 5700 in Dell 6650 1574 * ,even if check is false, the link may have changed.So we 1575 * have to call nge_phys_check() to determine the link state. 1576 */ 1577 if (check) 1578 nge_factotum_link_handler(ngep); 1579 1580 return (lchg); 1581 } 1582 1583 /* 1584 * Factotum routine to check for Tx stall, using the 'watchdog' counter 1585 */ 1586 static boolean_t nge_factotum_stall_check(nge_t *ngep); 1587 1588 static boolean_t 1589 nge_factotum_stall_check(nge_t *ngep) 1590 { 1591 uint32_t dogval; 1592 /* 1593 * Specific check for Tx stall ... 1594 * 1595 * The 'watchdog' counter is incremented whenever a packet 1596 * is queued, reset to 1 when some (but not all) buffers 1597 * are reclaimed, reset to 0 (disabled) when all buffers 1598 * are reclaimed, and shifted left here. If it exceeds the 1599 * threshold value, the chip is assumed to have stalled and 1600 * is put into the ERROR state. The factotum will then reset 1601 * it on the next pass. 1602 * 1603 * All of which should ensure that we don't get into a state 1604 * where packets are left pending indefinitely! 1605 */ 1606 dogval = nge_atomic_shl32(&ngep->watchdog, 1); 1607 if (dogval < nge_watchdog_count) { 1608 ngep->stall_cknum = 0; 1609 } else { 1610 ngep->stall_cknum++; 1611 } 1612 if (ngep->stall_cknum < 16) { 1613 return (B_FALSE); 1614 } else { 1615 ngep->stall_cknum = 0; 1616 ngep->statistics.sw_statistics.tx_stall++; 1617 return (B_TRUE); 1618 } 1619 } 1620 1621 1622 1623 /* 1624 * The factotum is woken up when there's something to do that we'd rather 1625 * not do from inside a hardware interrupt handler or high-level cyclic. 1626 * Its two main tasks are: 1627 * reset & restart the chip after an error 1628 * check the link status whenever necessary 1629 */ 1630 /* ARGSUSED */ 1631 uint_t 1632 nge_chip_factotum(caddr_t args1, caddr_t args2) 1633 { 1634 uint_t result; 1635 nge_t *ngep; 1636 boolean_t err; 1637 boolean_t linkchg; 1638 1639 ngep = (nge_t *)args1; 1640 1641 NGE_TRACE(("nge_chip_factotum($%p)", (void *)ngep)); 1642 1643 mutex_enter(ngep->softlock); 1644 if (ngep->factotum_flag == 0) { 1645 mutex_exit(ngep->softlock); 1646 return (DDI_INTR_UNCLAIMED); 1647 } 1648 ngep->factotum_flag = 0; 1649 mutex_exit(ngep->softlock); 1650 err = B_FALSE; 1651 linkchg = B_FALSE; 1652 result = DDI_INTR_CLAIMED; 1653 1654 mutex_enter(ngep->genlock); 1655 switch (ngep->nge_chip_state) { 1656 default: 1657 break; 1658 1659 case NGE_CHIP_RUNNING: 1660 linkchg = nge_factotum_link_check(ngep); 1661 err = nge_factotum_stall_check(ngep); 1662 break; 1663 1664 case NGE_CHIP_FAULT: 1665 (void) nge_restart(ngep); 1666 NGE_REPORT((ngep, "automatic recovery activated")); 1667 break; 1668 } 1669 1670 if (err) 1671 (void) nge_chip_stop(ngep, B_TRUE); 1672 mutex_exit(ngep->genlock); 1673 1674 /* 1675 * If the link state changed, tell the world about it (if 1676 * this version of MAC supports link state notification). 1677 * Note: can't do this while still holding the mutex. 1678 */ 1679 if (linkchg) 1680 mac_link_update(ngep->mh, ngep->link_state); 1681 1682 return (result); 1683 1684 } 1685 1686 static void 1687 nge_intr_handle(nge_t *ngep, nge_intr_src *pintr_src) 1688 { 1689 boolean_t brx; 1690 boolean_t btx; 1691 nge_mintr_src mintr_src; 1692 1693 brx = B_FALSE; 1694 btx = B_FALSE; 1695 ngep->statistics.sw_statistics.intr_count++; 1696 ngep->statistics.sw_statistics.intr_lval = pintr_src->intr_val; 1697 brx = (pintr_src->int_bits.reint | pintr_src->int_bits.miss 1698 | pintr_src->int_bits.rcint | pintr_src->int_bits.stint) 1699 != 0 ? B_TRUE : B_FALSE; 1700 if (pintr_src->int_bits.reint) 1701 ngep->statistics.sw_statistics.rx_err++; 1702 if (pintr_src->int_bits.miss) 1703 ngep->statistics.sw_statistics.rx_nobuffer++; 1704 1705 btx = (pintr_src->int_bits.teint | pintr_src->int_bits.tcint) 1706 != 0 ? B_TRUE : B_FALSE; 1707 if (pintr_src->int_bits.stint && ngep->poll) 1708 ngep->stint_count ++; 1709 if (ngep->poll && (ngep->stint_count % ngep->param_tx_n_intr == 0)) 1710 btx = B_TRUE; 1711 if (btx) 1712 nge_tx_recycle(ngep, B_TRUE); 1713 if (brx) 1714 nge_receive(ngep); 1715 if (pintr_src->int_bits.teint) 1716 ngep->statistics.sw_statistics.tx_stop_err++; 1717 if (ngep->intr_moderation && brx) { 1718 if (ngep->poll) { 1719 if (ngep->recv_count < ngep->param_rx_intr_hwater) { 1720 ngep->quiet_time++; 1721 if (ngep->quiet_time == 1722 ngep->param_poll_quiet_time) { 1723 ngep->poll = B_FALSE; 1724 ngep->quiet_time = 0; 1725 ngep->stint_count = 0; 1726 nge_tx_recycle(ngep, B_TRUE); 1727 } 1728 } else 1729 ngep->quiet_time = 0; 1730 } else { 1731 if (ngep->recv_count > ngep->param_rx_intr_lwater) { 1732 ngep->busy_time++; 1733 if (ngep->busy_time == 1734 ngep->param_poll_busy_time) { 1735 ngep->poll = B_TRUE; 1736 ngep->busy_time = 0; 1737 } 1738 } else 1739 ngep->busy_time = 0; 1740 } 1741 } 1742 ngep->recv_count = 0; 1743 if (pintr_src->int_bits.feint) 1744 nge_chip_err(ngep); 1745 /* link interrupt, check the link state */ 1746 if (pintr_src->int_bits.mint) { 1747 mintr_src.src_val = nge_reg_get32(ngep, NGE_MINTR_SRC); 1748 nge_reg_put32(ngep, NGE_MINTR_SRC, mintr_src.src_val); 1749 nge_wake_factotum(ngep); 1750 } 1751 } 1752 1753 /* 1754 * nge_chip_intr() -- handle chip interrupts 1755 */ 1756 /* ARGSUSED */ 1757 uint_t 1758 nge_chip_intr(caddr_t arg1, caddr_t arg2) 1759 { 1760 nge_t *ngep = (nge_t *)arg1; 1761 nge_intr_src intr_src; 1762 nge_intr_mask intr_mask; 1763 1764 mutex_enter(ngep->genlock); 1765 1766 if (ngep->suspended) { 1767 mutex_exit(ngep->genlock); 1768 return (DDI_INTR_UNCLAIMED); 1769 } 1770 1771 /* 1772 * Check whether chip's says it's asserting #INTA; 1773 * if not, don't process or claim the interrupt. 1774 */ 1775 intr_src.intr_val = nge_reg_get32(ngep, NGE_INTR_SRC); 1776 if (intr_src.intr_val == 0) { 1777 mutex_exit(ngep->genlock); 1778 return (DDI_INTR_UNCLAIMED); 1779 } 1780 /* 1781 * Ack the interrupt 1782 */ 1783 nge_reg_put32(ngep, NGE_INTR_SRC, intr_src.intr_val); 1784 1785 if (ngep->nge_chip_state != NGE_CHIP_RUNNING) { 1786 mutex_exit(ngep->genlock); 1787 return (DDI_INTR_CLAIMED); 1788 } 1789 nge_intr_handle(ngep, &intr_src); 1790 if (ngep->poll && !ngep->ch_intr_mode) { 1791 intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK); 1792 intr_mask.mask_bits.stint = NGE_SET; 1793 intr_mask.mask_bits.rcint = NGE_CLEAR; 1794 intr_mask.mask_bits.reint = NGE_CLEAR; 1795 intr_mask.mask_bits.tcint = NGE_CLEAR; 1796 intr_mask.mask_bits.teint = NGE_CLEAR; 1797 nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val); 1798 ngep->ch_intr_mode = B_TRUE; 1799 } else if ((ngep->ch_intr_mode) && (!ngep->poll)) { 1800 nge_reg_put32(ngep, NGE_INTR_MASK, ngep->intr_masks); 1801 ngep->ch_intr_mode = B_FALSE; 1802 } 1803 mutex_exit(ngep->genlock); 1804 return (DDI_INTR_CLAIMED); 1805 } 1806 1807 static enum ioc_reply 1808 nge_pp_ioctl(nge_t *ngep, int cmd, mblk_t *mp, struct iocblk *iocp) 1809 { 1810 int err; 1811 uint64_t sizemask; 1812 uint64_t mem_va; 1813 uint64_t maxoff; 1814 boolean_t peek; 1815 nge_peekpoke_t *ppd; 1816 int (*ppfn)(nge_t *ngep, nge_peekpoke_t *ppd); 1817 1818 switch (cmd) { 1819 default: 1820 return (IOC_INVAL); 1821 1822 case NGE_PEEK: 1823 peek = B_TRUE; 1824 break; 1825 1826 case NGE_POKE: 1827 peek = B_FALSE; 1828 break; 1829 } 1830 1831 /* 1832 * Validate format of ioctl 1833 */ 1834 if (iocp->ioc_count != sizeof (nge_peekpoke_t)) 1835 return (IOC_INVAL); 1836 if (mp->b_cont == NULL) 1837 return (IOC_INVAL); 1838 ppd = (nge_peekpoke_t *)mp->b_cont->b_rptr; 1839 1840 /* 1841 * Validate request parameters 1842 */ 1843 switch (ppd->pp_acc_space) { 1844 default: 1845 return (IOC_INVAL); 1846 1847 case NGE_PP_SPACE_CFG: 1848 /* 1849 * Config space 1850 */ 1851 sizemask = 8|4|2|1; 1852 mem_va = 0; 1853 maxoff = PCI_CONF_HDR_SIZE; 1854 ppfn = peek ? nge_chip_peek_cfg : nge_chip_poke_cfg; 1855 break; 1856 1857 case NGE_PP_SPACE_REG: 1858 /* 1859 * Memory-mapped I/O space 1860 */ 1861 sizemask = 8|4|2|1; 1862 mem_va = 0; 1863 maxoff = NGE_REG_SIZE; 1864 ppfn = peek ? nge_chip_peek_reg : nge_chip_poke_reg; 1865 break; 1866 1867 case NGE_PP_SPACE_MII: 1868 sizemask = 4|2|1; 1869 mem_va = 0; 1870 maxoff = NGE_MII_SIZE; 1871 ppfn = peek ? nge_chip_peek_mii : nge_chip_poke_mii; 1872 break; 1873 1874 case NGE_PP_SPACE_SEEPROM: 1875 sizemask = 4|2|1; 1876 mem_va = 0; 1877 maxoff = NGE_SEEROM_SIZE; 1878 ppfn = peek ? nge_chip_peek_seeprom : nge_chip_poke_seeprom; 1879 break; 1880 } 1881 1882 switch (ppd->pp_acc_size) { 1883 default: 1884 return (IOC_INVAL); 1885 1886 case 8: 1887 case 4: 1888 case 2: 1889 case 1: 1890 if ((ppd->pp_acc_size & sizemask) == 0) 1891 return (IOC_INVAL); 1892 break; 1893 } 1894 1895 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 1896 return (IOC_INVAL); 1897 1898 if (ppd->pp_acc_offset >= maxoff) 1899 return (IOC_INVAL); 1900 1901 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 1902 return (IOC_INVAL); 1903 1904 /* 1905 * All OK - go do it! 1906 */ 1907 ppd->pp_acc_offset += mem_va; 1908 if (ppfn) 1909 err = (*ppfn)(ngep, ppd); 1910 if (err != DDI_SUCCESS) 1911 return (IOC_INVAL); 1912 return (peek ? IOC_REPLY : IOC_ACK); 1913 } 1914 1915 static enum ioc_reply nge_diag_ioctl(nge_t *ngep, int cmd, mblk_t *mp, 1916 struct iocblk *iocp); 1917 #pragma no_inline(nge_diag_ioctl) 1918 1919 static enum ioc_reply 1920 nge_diag_ioctl(nge_t *ngep, int cmd, mblk_t *mp, struct iocblk *iocp) 1921 { 1922 ASSERT(mutex_owned(ngep->genlock)); 1923 1924 switch (cmd) { 1925 default: 1926 nge_error(ngep, "nge_diag_ioctl: invalid cmd 0x%x", cmd); 1927 return (IOC_INVAL); 1928 1929 case NGE_DIAG: 1930 return (IOC_ACK); 1931 1932 case NGE_PEEK: 1933 case NGE_POKE: 1934 return (nge_pp_ioctl(ngep, cmd, mp, iocp)); 1935 1936 case NGE_PHY_RESET: 1937 return (IOC_RESTART_ACK); 1938 1939 case NGE_SOFT_RESET: 1940 case NGE_HARD_RESET: 1941 return (IOC_ACK); 1942 } 1943 1944 /* NOTREACHED */ 1945 } 1946 1947 enum ioc_reply 1948 nge_chip_ioctl(nge_t *ngep, mblk_t *mp, struct iocblk *iocp) 1949 { 1950 int cmd; 1951 1952 ASSERT(mutex_owned(ngep->genlock)); 1953 1954 cmd = iocp->ioc_cmd; 1955 1956 switch (cmd) { 1957 default: 1958 return (IOC_INVAL); 1959 1960 case NGE_DIAG: 1961 case NGE_PEEK: 1962 case NGE_POKE: 1963 case NGE_PHY_RESET: 1964 case NGE_SOFT_RESET: 1965 case NGE_HARD_RESET: 1966 #if NGE_DEBUGGING 1967 return (nge_diag_ioctl(ngep, cmd, mp, iocp)); 1968 #else 1969 return (IOC_INVAL); 1970 #endif 1971 1972 case NGE_MII_READ: 1973 case NGE_MII_WRITE: 1974 return (IOC_INVAL); 1975 1976 #if NGE_SEE_IO32 1977 case NGE_SEE_READ: 1978 case NGE_SEE_WRITE: 1979 return (IOC_INVAL); 1980 #endif 1981 1982 #if NGE_FLASH_IO32 1983 case NGE_FLASH_READ: 1984 case NGE_FLASH_WRITE: 1985 return (IOC_INVAL); 1986 #endif 1987 } 1988 } 1989