1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 23 /* 24 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 25 * Use is subject to license terms. 26 */ 27 28 #ifndef _IXGBE_SW_H 29 #define _IXGBE_SW_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/types.h> 36 #include <sys/conf.h> 37 #include <sys/debug.h> 38 #include <sys/stropts.h> 39 #include <sys/stream.h> 40 #include <sys/strsun.h> 41 #include <sys/strlog.h> 42 #include <sys/kmem.h> 43 #include <sys/stat.h> 44 #include <sys/kstat.h> 45 #include <sys/modctl.h> 46 #include <sys/errno.h> 47 #include <sys/dlpi.h> 48 #include <sys/mac_provider.h> 49 #include <sys/mac_ether.h> 50 #include <sys/vlan.h> 51 #include <sys/ddi.h> 52 #include <sys/sunddi.h> 53 #include <sys/pci.h> 54 #include <sys/pcie.h> 55 #include <sys/sdt.h> 56 #include <sys/ethernet.h> 57 #include <sys/pattr.h> 58 #include <sys/strsubr.h> 59 #include <sys/netlb.h> 60 #include <sys/random.h> 61 #include <inet/common.h> 62 #include <inet/tcp.h> 63 #include <inet/ip.h> 64 #include <inet/mi.h> 65 #include <inet/nd.h> 66 #include <sys/bitmap.h> 67 #include <sys/ddifm.h> 68 #include <sys/fm/protocol.h> 69 #include <sys/fm/util.h> 70 #include <sys/fm/io/ddi.h> 71 #include "ixgbe_api.h" 72 73 #define MODULE_NAME "ixgbe" /* module name */ 74 75 #define IXGBE_FAILURE DDI_FAILURE 76 77 #define IXGBE_UNKNOWN 0x00 78 #define IXGBE_INITIALIZED 0x01 79 #define IXGBE_STARTED 0x02 80 #define IXGBE_SUSPENDED 0x04 81 82 #define MAX_NUM_UNICAST_ADDRESSES 0x10 83 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000 84 #define IXGBE_INTR_NONE 0 85 #define IXGBE_INTR_MSIX 1 86 #define IXGBE_INTR_MSI 2 87 #define IXGBE_INTR_LEGACY 3 88 89 #define IXGBE_POLL_NULL -1 90 91 #define MAX_COOKIE 18 92 #define MIN_NUM_TX_DESC 2 93 94 #define IXGBE_ADAPTER_REGSET 1 /* map adapter registers */ 95 96 /* 97 * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all 98 * supported silicon types. 99 */ 100 #define MAX_TX_QUEUE_NUM 128 101 #define MAX_RX_QUEUE_NUM 128 102 #define MAX_INTR_VECTOR 64 103 104 /* 105 * Maximum values for user configurable parameters 106 */ 107 #define MAX_RX_GROUP_NUM 1 108 #define MAX_TX_RING_SIZE 4096 109 #define MAX_RX_RING_SIZE 4096 110 111 #define MAX_MTU 16366 112 #define MAX_RX_LIMIT_PER_INTR 4096 113 #define MAX_INTR_THROTTLING_82598 65535 114 #define MAX_INTR_THROTTLING_82599 0x7FC 115 116 #define MAX_RX_COPY_THRESHOLD 9216 117 #define MAX_TX_COPY_THRESHOLD 9216 118 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 119 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 120 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 121 122 /* 123 * Minimum values for user configurable parameters 124 */ 125 #define MIN_RX_GROUP_NUM 1 126 #define MIN_TX_RING_SIZE 64 127 #define MIN_RX_RING_SIZE 64 128 129 #define MIN_MTU ETHERMIN 130 #define MIN_RX_LIMIT_PER_INTR 16 131 #define MIN_INTR_THROTTLING 0 132 #define MIN_TX_COPY_THRESHOLD 0 133 #define MIN_RX_COPY_THRESHOLD 0 134 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 135 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 136 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 137 138 /* 139 * Default values for user configurable parameters 140 */ 141 #define DEFAULT_RX_GROUP_NUM 1 142 #define DEFAULT_TX_RING_SIZE 1024 143 #define DEFAULT_RX_RING_SIZE 1024 144 145 #define DEFAULT_MTU ETHERMTU 146 #define DEFAULT_RX_LIMIT_PER_INTR 256 147 #define DEFAULT_INTR_THROTTLING_82598 200 /* In unit of 256 nsec */ 148 #define DEFAULT_INTR_THROTTLING_82599 26 /* In unit of 2 usec */ 149 #define DEFAULT_RX_COPY_THRESHOLD 128 150 #define DEFAULT_TX_COPY_THRESHOLD 512 151 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 152 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 153 #define DEFAULT_TX_RESCHED_THRESHOLD 128 154 #define DEFAULT_FCRTH 0x20000 155 #define DEFAULT_FCRTL 0x10000 156 #define DEFAULT_FCPAUSE 0xFFFF 157 158 #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE 159 #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE 160 #define DEFAULT_LSO_ENABLE B_TRUE 161 #define DEFAULT_MR_ENABLE B_TRUE 162 #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE 163 164 #define IXGBE_LSO_MAXLEN 65535 165 166 #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE 167 #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE 168 #define DEFAULT_LSO_ENABLE B_TRUE 169 #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE 170 171 #define IXGBE_LSO_MAXLEN 65535 172 173 #define TX_DRAIN_TIME 200 174 #define RX_DRAIN_TIME 200 175 176 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 177 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 178 179 /* 180 * Extra register bit masks for 82598 181 */ 182 #define IXGBE_PCS1GANA_FDC 0x20 183 #define IXGBE_PCS1GANLP_LPFD 0x20 184 #define IXGBE_PCS1GANLP_LPHD 0x40 185 186 /* 187 * Defined for IP header alignment. 188 */ 189 #define IPHDR_ALIGN_ROOM 2 190 191 /* 192 * Bit flags for attach_progress 193 */ 194 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 195 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 196 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 197 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 198 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 199 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 200 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 201 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 202 #define ATTACH_PROGRESS_INIT_RINGS 0x0100 /* Rings initialized */ 203 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 204 #define ATTACH_PROGRESS_NDD 0x0400 /* NDD initialized */ 205 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 206 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 207 #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */ 208 #define ATTACH_PROGRESS_LSC_TASKQ 0x4000 /* LSC taskq created */ 209 210 #define PROP_DEFAULT_MTU "default_mtu" 211 #define PROP_FLOW_CONTROL "flow_control" 212 #define PROP_TX_QUEUE_NUM "tx_queue_number" 213 #define PROP_TX_RING_SIZE "tx_ring_size" 214 #define PROP_RX_QUEUE_NUM "rx_queue_number" 215 #define PROP_RX_RING_SIZE "rx_ring_size" 216 #define PROP_RX_GROUP_NUM "rx_group_number" 217 218 #define PROP_INTR_FORCE "intr_force" 219 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 220 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 221 #define PROP_LSO_ENABLE "lso_enable" 222 #define PROP_MR_ENABLE "mr_enable" 223 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 224 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 225 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 226 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 227 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 228 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 229 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 230 #define PROP_INTR_THROTTLING "intr_throttling" 231 #define PROP_FM_CAPABLE "fm_capable" 232 233 #define IXGBE_LB_NONE 0 234 #define IXGBE_LB_EXTERNAL 1 235 #define IXGBE_LB_INTERNAL_MAC 2 236 #define IXGBE_LB_INTERNAL_PHY 3 237 #define IXGBE_LB_INTERNAL_SERDES 4 238 239 /* 240 * capability/feature flags 241 * Flags named _CAPABLE are set when the NIC hardware is capable of the feature. 242 * Separately, the flag named _ENABLED is set when the feature is enabled. 243 */ 244 #define IXGBE_FLAG_DCA_ENABLED (u32)(1) 245 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 1) 246 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 2) 247 #define IXGBE_FLAG_DCB_CAPABLE (u32)(1 << 4) 248 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 4) 249 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 5) 250 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 6) 251 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 7) 252 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 8) 253 254 /* adapter-specific info for each supported device type */ 255 typedef struct adapter_info { 256 uint32_t max_rx_que_num; /* maximum number of rx queues */ 257 uint32_t min_rx_que_num; /* minimum number of rx queues */ 258 uint32_t def_rx_que_num; /* default number of rx queues */ 259 uint32_t max_tx_que_num; /* maximum number of tx queues */ 260 uint32_t min_tx_que_num; /* minimum number of tx queues */ 261 uint32_t def_tx_que_num; /* default number of tx queues */ 262 uint32_t max_msix_vect; /* maximum total msix vectors */ 263 uint32_t max_ring_vect; /* maximum number of ring vectors */ 264 uint32_t max_other_vect; /* maximum number of other vectors */ 265 uint32_t other_intr; /* "other" interrupt types handled */ 266 uint32_t flags; /* capability flags */ 267 } adapter_info_t; 268 269 /* bits representing all interrupt types other than tx & rx */ 270 #define IXGBE_OTHER_INTR 0x3ff00000 271 #define IXGBE_82599_OTHER_INTR 0x86100000 272 273 /* 274 * Shorthand for the NDD parameters 275 */ 276 #define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].val 277 #define param_pause_cap nd_params[PARAM_PAUSE_CAP].val 278 #define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].val 279 #define param_10000fdx_cap nd_params[PARAM_10000FDX_CAP].val 280 #define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].val 281 #define param_100fdx_cap nd_params[PARAM_1000FDX_CAP].val 282 #define param_rem_fault nd_params[PARAM_REM_FAULT].val 283 284 #define param_adv_autoneg_cap nd_params[PARAM_ADV_AUTONEG_CAP].val 285 #define param_adv_pause_cap nd_params[PARAM_ADV_PAUSE_CAP].val 286 #define param_adv_asym_pause_cap nd_params[PARAM_ADV_ASYM_PAUSE_CAP].val 287 #define param_adv_10000fdx_cap nd_params[PARAM_ADV_10000FDX_CAP].val 288 #define param_adv_1000fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 289 #define param_adv_100fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 290 #define param_adv_rem_fault nd_params[PARAM_ADV_REM_FAULT].val 291 292 #define param_lp_autoneg_cap nd_params[PARAM_LP_AUTONEG_CAP].val 293 #define param_lp_pause_cap nd_params[PARAM_LP_PAUSE_CAP].val 294 #define param_lp_asym_pause_cap nd_params[PARAM_LP_ASYM_PAUSE_CAP].val 295 #define param_lp_10000fdx_cap nd_params[PARAM_LP_10000FDX_CAP].val 296 #define param_lp_1000fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 297 #define param_lp_100fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 298 #define param_lp_rem_fault nd_params[PARAM_LP_REM_FAULT].val 299 300 enum ioc_reply { 301 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 302 IOC_DONE, /* OK, reply sent */ 303 IOC_ACK, /* OK, just send ACK */ 304 IOC_REPLY /* OK, just send reply */ 305 }; 306 307 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 308 0, 0, (flag))) 309 310 /* 311 * Defined for ring index operations 312 * ASSERT(index < limit) 313 * ASSERT(step < limit) 314 * ASSERT(index1 < limit) 315 * ASSERT(index2 < limit) 316 */ 317 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 318 (index) + (step) : (index) + (step) - (limit)) 319 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 320 (index) - (step) : (index) + (limit) - (step)) 321 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 322 (index2) - (index1) : (index2) + (limit) - (index1)) 323 324 #define LINK_LIST_INIT(_LH) \ 325 (_LH)->head = (_LH)->tail = NULL 326 327 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 328 329 #define LIST_POP_HEAD(_LH) \ 330 (single_link_t *)(_LH)->head; \ 331 { \ 332 if ((_LH)->head != NULL) { \ 333 (_LH)->head = (_LH)->head->link; \ 334 if ((_LH)->head == NULL) \ 335 (_LH)->tail = NULL; \ 336 } \ 337 } 338 339 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 340 341 #define LIST_PUSH_TAIL(_LH, _E) \ 342 if ((_LH)->tail != NULL) { \ 343 (_LH)->tail->link = (single_link_t *)(_E); \ 344 (_LH)->tail = (single_link_t *)(_E); \ 345 } else { \ 346 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 347 } \ 348 (_E)->link = NULL; 349 350 #define LIST_GET_NEXT(_LH, _E) \ 351 (((_LH)->tail == (single_link_t *)(_E)) ? \ 352 NULL : ((single_link_t *)(_E))->link) 353 354 355 typedef struct single_link { 356 struct single_link *link; 357 } single_link_t; 358 359 typedef struct link_list { 360 single_link_t *head; 361 single_link_t *tail; 362 } link_list_t; 363 364 /* 365 * Property lookups 366 */ 367 #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 368 DDI_PROP_DONTPASS, (n)) 369 #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 370 DDI_PROP_DONTPASS, (n), -1) 371 372 373 /* 374 * Named Data (ND) Parameter Management Structure 375 */ 376 typedef struct { 377 struct ixgbe *private; 378 uint32_t info; 379 uint32_t min; 380 uint32_t max; 381 uint32_t val; 382 char *name; 383 } nd_param_t; 384 385 /* 386 * NDD parameter indexes, divided into: 387 * 388 * read-only parameters describing the hardware's capabilities 389 * read-write parameters controlling the advertised capabilities 390 * read-only parameters describing the partner's capabilities 391 * read-write parameters controlling the force speed and duplex 392 * read-only parameters describing the link state 393 * read-only parameters describing the driver properties 394 * read-write parameters controlling the driver properties 395 */ 396 enum { 397 PARAM_AUTONEG_CAP, 398 PARAM_PAUSE_CAP, 399 PARAM_ASYM_PAUSE_CAP, 400 PARAM_10000FDX_CAP, 401 PARAM_1000FDX_CAP, 402 PARAM_100FDX_CAP, 403 PARAM_REM_FAULT, 404 405 PARAM_ADV_AUTONEG_CAP, 406 PARAM_ADV_PAUSE_CAP, 407 PARAM_ADV_ASYM_PAUSE_CAP, 408 PARAM_ADV_10000FDX_CAP, 409 PARAM_ADV_1000FDX_CAP, 410 PARAM_ADV_100FDX_CAP, 411 PARAM_ADV_REM_FAULT, 412 413 PARAM_LP_AUTONEG_CAP, 414 PARAM_LP_PAUSE_CAP, 415 PARAM_LP_ASYM_PAUSE_CAP, 416 PARAM_LP_10000FDX_CAP, 417 PARAM_LP_1000FDX_CAP, 418 PARAM_LP_100FDX_CAP, 419 PARAM_LP_REM_FAULT, 420 421 PARAM_LINK_STATUS, 422 PARAM_LINK_SPEED, 423 PARAM_LINK_DUPLEX, 424 425 PARAM_COUNT 426 }; 427 428 typedef union ixgbe_ether_addr { 429 struct { 430 uint32_t high; 431 uint32_t low; 432 } reg; 433 struct { 434 uint8_t set; 435 uint8_t redundant; 436 uint8_t addr[ETHERADDRL]; 437 } mac; 438 } ixgbe_ether_addr_t; 439 440 typedef enum { 441 USE_NONE, 442 USE_COPY, 443 USE_DMA 444 } tx_type_t; 445 446 typedef enum { 447 RCB_FREE, 448 RCB_SENDUP 449 } rcb_state_t; 450 451 typedef struct ixgbe_tx_context { 452 uint32_t hcksum_flags; 453 uint32_t ip_hdr_len; 454 uint32_t mac_hdr_len; 455 uint32_t l4_proto; 456 uint32_t mss; 457 uint32_t l4_hdr_len; 458 boolean_t lso_flag; 459 } ixgbe_tx_context_t; 460 461 /* 462 * Hold address/length of each DMA segment 463 */ 464 typedef struct sw_desc { 465 uint64_t address; 466 size_t length; 467 } sw_desc_t; 468 469 /* 470 * Handles and addresses of DMA buffer 471 */ 472 typedef struct dma_buffer { 473 caddr_t address; /* Virtual address */ 474 uint64_t dma_address; /* DMA (Hardware) address */ 475 ddi_acc_handle_t acc_handle; /* Data access handle */ 476 ddi_dma_handle_t dma_handle; /* DMA handle */ 477 size_t size; /* Buffer size */ 478 size_t len; /* Data length in the buffer */ 479 } dma_buffer_t; 480 481 /* 482 * Tx Control Block 483 */ 484 typedef struct tx_control_block { 485 single_link_t link; 486 uint32_t frag_num; 487 uint32_t desc_num; 488 mblk_t *mp; 489 tx_type_t tx_type; 490 ddi_dma_handle_t tx_dma_handle; 491 dma_buffer_t tx_buf; 492 sw_desc_t desc[MAX_COOKIE]; 493 } tx_control_block_t; 494 495 /* 496 * RX Control Block 497 */ 498 typedef struct rx_control_block { 499 mblk_t *mp; 500 rcb_state_t state; 501 dma_buffer_t rx_buf; 502 frtn_t free_rtn; 503 struct ixgbe_rx_ring *rx_ring; 504 } rx_control_block_t; 505 506 /* 507 * Software Data Structure for Tx Ring 508 */ 509 typedef struct ixgbe_tx_ring { 510 uint32_t index; /* Ring index */ 511 uint32_t intr_vector; /* Interrupt vector index */ 512 uint32_t vect_bit; /* vector's bit in register */ 513 514 /* 515 * Mutexes 516 */ 517 kmutex_t tx_lock; 518 kmutex_t recycle_lock; 519 kmutex_t tcb_head_lock; 520 kmutex_t tcb_tail_lock; 521 522 /* 523 * Tx descriptor ring definitions 524 */ 525 dma_buffer_t tbd_area; 526 union ixgbe_adv_tx_desc *tbd_ring; 527 uint32_t tbd_head; /* Index of next tbd to recycle */ 528 uint32_t tbd_tail; /* Index of next tbd to transmit */ 529 uint32_t tbd_free; /* Number of free tbd */ 530 531 /* 532 * Tx control block list definitions 533 */ 534 tx_control_block_t *tcb_area; 535 tx_control_block_t **work_list; 536 tx_control_block_t **free_list; 537 uint32_t tcb_head; /* Head index of free list */ 538 uint32_t tcb_tail; /* Tail index of free list */ 539 uint32_t tcb_free; /* Number of free tcb in free list */ 540 541 uint32_t *tbd_head_wb; /* Head write-back */ 542 uint32_t (*tx_recycle)(struct ixgbe_tx_ring *); 543 544 /* 545 * s/w context structure for TCP/UDP checksum offload 546 * and LSO. 547 */ 548 ixgbe_tx_context_t tx_context; 549 550 /* 551 * Tx ring settings and status 552 */ 553 uint32_t ring_size; /* Tx descriptor ring size */ 554 uint32_t free_list_size; /* Tx free list size */ 555 uint32_t copy_thresh; 556 uint32_t recycle_thresh; 557 uint32_t overload_thresh; 558 uint32_t resched_thresh; 559 560 boolean_t reschedule; 561 uint32_t recycle_fail; 562 uint32_t stall_watchdog; 563 564 #ifdef IXGBE_DEBUG 565 /* 566 * Debug statistics 567 */ 568 uint32_t stat_overload; 569 uint32_t stat_fail_no_tbd; 570 uint32_t stat_fail_no_tcb; 571 uint32_t stat_fail_dma_bind; 572 uint32_t stat_reschedule; 573 uint32_t stat_lso_header_fail; 574 #endif 575 576 mac_ring_handle_t ring_handle; 577 578 /* 579 * Pointer to the ixgbe struct 580 */ 581 struct ixgbe *ixgbe; 582 } ixgbe_tx_ring_t; 583 584 /* 585 * Software Receive Ring 586 */ 587 typedef struct ixgbe_rx_ring { 588 uint32_t index; /* Ring index */ 589 uint32_t intr_vector; /* Interrupt vector index */ 590 uint32_t vect_bit; /* vector's bit in register */ 591 592 /* 593 * Mutexes 594 */ 595 kmutex_t rx_lock; /* Rx access lock */ 596 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 597 598 /* 599 * Rx descriptor ring definitions 600 */ 601 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 602 union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */ 603 uint32_t rbd_next; /* Index of next rx desc */ 604 605 /* 606 * Rx control block list definitions 607 */ 608 rx_control_block_t *rcb_area; 609 rx_control_block_t **work_list; /* Work list of rcbs */ 610 rx_control_block_t **free_list; /* Free list of rcbs */ 611 uint32_t rcb_head; /* Index of next free rcb */ 612 uint32_t rcb_tail; /* Index to put recycled rcb */ 613 uint32_t rcb_free; /* Number of free rcbs */ 614 615 /* 616 * Rx ring settings and status 617 */ 618 uint32_t ring_size; /* Rx descriptor ring size */ 619 uint32_t free_list_size; /* Rx free list size */ 620 uint32_t limit_per_intr; /* Max packets per interrupt */ 621 uint32_t copy_thresh; 622 623 #ifdef IXGBE_DEBUG 624 /* 625 * Debug statistics 626 */ 627 uint32_t stat_frame_error; 628 uint32_t stat_cksum_error; 629 uint32_t stat_exceed_pkt; 630 #endif 631 632 mac_ring_handle_t ring_handle; 633 uint64_t ring_gen_num; 634 635 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 636 } ixgbe_rx_ring_t; 637 638 /* 639 * Software Receive Ring Group 640 */ 641 typedef struct ixgbe_rx_group { 642 uint32_t index; /* Group index */ 643 mac_group_handle_t group_handle; /* call back group handle */ 644 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 645 } ixgbe_rx_group_t; 646 647 /* 648 * structure to map interrupt cleanup to msi-x vector 649 */ 650 typedef struct ixgbe_intr_vector { 651 struct ixgbe *ixgbe; /* point to my adapter */ 652 ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */ 653 int rxr_cnt; /* count rx rings */ 654 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */ 655 int txr_cnt; /* count tx rings */ 656 ulong_t other_map[BT_BITOUL(2)]; /* bitmap of other */ 657 int other_cnt; /* count other interrupt */ 658 } ixgbe_intr_vector_t; 659 660 /* 661 * Software adapter state 662 */ 663 typedef struct ixgbe { 664 int instance; 665 mac_handle_t mac_hdl; 666 dev_info_t *dip; 667 struct ixgbe_hw hw; 668 struct ixgbe_osdep osdep; 669 670 adapter_info_t *capab; /* adapter hardware capabilities */ 671 ddi_taskq_t *lsc_taskq; /* link-status-change taskq */ 672 uint32_t eims; /* interrupt mask setting */ 673 uint32_t eimc; /* interrupt mask clear */ 674 uint32_t eicr; /* interrupt cause reg */ 675 676 uint32_t ixgbe_state; 677 link_state_t link_state; 678 uint32_t link_speed; 679 uint32_t link_duplex; 680 uint32_t link_down_timeout; 681 682 uint32_t reset_count; 683 uint32_t attach_progress; 684 uint32_t loopback_mode; 685 uint32_t default_mtu; 686 uint32_t max_frame_size; 687 688 /* 689 * Each msi-x vector: map vector to interrupt cleanup 690 */ 691 ixgbe_intr_vector_t vect_map[MAX_INTR_VECTOR]; 692 693 /* 694 * Receive Rings 695 */ 696 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */ 697 uint32_t num_rx_rings; /* Number of rx rings in use */ 698 uint32_t rx_ring_size; /* Rx descriptor ring size */ 699 uint32_t rx_buf_size; /* Rx buffer size */ 700 701 /* 702 * Receive Groups 703 */ 704 ixgbe_rx_group_t *rx_groups; /* Array of rx groups */ 705 uint32_t num_rx_groups; /* Number of rx groups in use */ 706 707 /* 708 * Transmit Rings 709 */ 710 ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */ 711 uint32_t num_tx_rings; /* Number of tx rings in use */ 712 uint32_t tx_ring_size; /* Tx descriptor ring size */ 713 uint32_t tx_buf_size; /* Tx buffer size */ 714 715 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 716 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 717 boolean_t lso_enable; /* Large Segment Offload */ 718 boolean_t mr_enable; /* Multiple Tx and Rx Ring */ 719 uint32_t tx_copy_thresh; /* Tx copy threshold */ 720 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 721 uint32_t tx_overload_thresh; /* Tx overload threshold */ 722 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 723 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 724 uint32_t rx_copy_thresh; /* Rx copy threshold */ 725 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 726 uint32_t intr_throttling[MAX_INTR_VECTOR]; 727 uint32_t intr_force; 728 int fm_capabilities; /* FMA capabilities */ 729 730 int intr_type; 731 int intr_cnt; 732 int intr_cap; 733 size_t intr_size; 734 uint_t intr_pri; 735 ddi_intr_handle_t *htable; 736 uint32_t eims_mask; 737 738 kmutex_t gen_lock; /* General lock for device access */ 739 kmutex_t watchdog_lock; 740 741 boolean_t watchdog_enable; 742 boolean_t watchdog_start; 743 timeout_id_t watchdog_tid; 744 745 boolean_t unicst_init; 746 uint32_t unicst_avail; 747 uint32_t unicst_total; 748 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 749 uint32_t mcast_count; 750 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 751 752 ulong_t sys_page_size; 753 754 /* 755 * Kstat definitions 756 */ 757 kstat_t *ixgbe_ks; 758 759 /* 760 * NDD definitions 761 */ 762 caddr_t nd_data; 763 nd_param_t nd_params[PARAM_COUNT]; 764 } ixgbe_t; 765 766 typedef struct ixgbe_stat { 767 kstat_named_t link_speed; /* Link Speed */ 768 769 kstat_named_t reset_count; /* Reset Count */ 770 771 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 772 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 773 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 774 775 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 776 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 777 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 778 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 779 kstat_named_t tx_reschedule; /* Tx Reschedule */ 780 781 kstat_named_t gprc; /* Good Packets Received Count */ 782 kstat_named_t gptc; /* Good Packets Xmitted Count */ 783 kstat_named_t gor; /* Good Octets Received Count */ 784 kstat_named_t got; /* Good Octets Xmitd Count */ 785 kstat_named_t prc64; /* Packets Received - 64b */ 786 kstat_named_t prc127; /* Packets Received - 65-127b */ 787 kstat_named_t prc255; /* Packets Received - 127-255b */ 788 kstat_named_t prc511; /* Packets Received - 256-511b */ 789 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 790 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 791 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 792 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 793 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 794 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 795 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 796 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 797 kstat_named_t qprc[16]; /* Queue Packets Received Count */ 798 kstat_named_t qptc[16]; /* Queue Packets Transmitted Count */ 799 kstat_named_t qbrc[16]; /* Queue Bytes Received Count */ 800 kstat_named_t qbtc[16]; /* Queue Bytes Transmitted Count */ 801 802 kstat_named_t crcerrs; /* CRC Error Count */ 803 kstat_named_t illerrc; /* Illegal Byte Error Count */ 804 kstat_named_t errbc; /* Error Byte Count */ 805 kstat_named_t mspdc; /* MAC Short Packet Discard Count */ 806 kstat_named_t mpc; /* Missed Packets Count */ 807 kstat_named_t mlfc; /* MAC Local Fault Count */ 808 kstat_named_t mrfc; /* MAC Remote Fault Count */ 809 kstat_named_t rlec; /* Receive Length Error Count */ 810 kstat_named_t lxontxc; /* Link XON Transmitted Count */ 811 kstat_named_t lxonrxc; /* Link XON Received Count */ 812 kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */ 813 kstat_named_t lxoffrxc; /* Link XOFF Received Count */ 814 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 815 kstat_named_t mprc; /* Multicast Pkts Received Count */ 816 kstat_named_t rnbc; /* Receive No Buffers Count */ 817 kstat_named_t ruc; /* Receive Undersize Count */ 818 kstat_named_t rfc; /* Receive Frag Count */ 819 kstat_named_t roc; /* Receive Oversize Count */ 820 kstat_named_t rjc; /* Receive Jabber Count */ 821 kstat_named_t tor; /* Total Octets Recvd Count */ 822 kstat_named_t tot; /* Total Octets Xmitted Count */ 823 kstat_named_t tpr; /* Total Packets Received */ 824 kstat_named_t tpt; /* Total Packets Xmitted */ 825 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 826 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 827 } ixgbe_stat_t; 828 829 /* 830 * Function prototypes in ixgbe_buf.c 831 */ 832 int ixgbe_alloc_dma(ixgbe_t *); 833 void ixgbe_free_dma(ixgbe_t *); 834 void ixgbe_set_fma_flags(int, int); 835 836 /* 837 * Function prototypes in ixgbe_main.c 838 */ 839 int ixgbe_start(ixgbe_t *); 840 void ixgbe_stop(ixgbe_t *); 841 int ixgbe_driver_setup_link(ixgbe_t *, boolean_t); 842 int ixgbe_multicst_add(ixgbe_t *, const uint8_t *); 843 int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *); 844 enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *); 845 846 void ixgbe_enable_watchdog_timer(ixgbe_t *); 847 void ixgbe_disable_watchdog_timer(ixgbe_t *); 848 int ixgbe_atomic_reserve(uint32_t *, uint32_t); 849 850 int ixgbe_check_acc_handle(ddi_acc_handle_t handle); 851 int ixgbe_check_dma_handle(ddi_dma_handle_t handle); 852 void ixgbe_fm_ereport(ixgbe_t *, char *); 853 854 void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int, 855 mac_ring_info_t *, mac_ring_handle_t); 856 void ixgbe_fill_group(void *arg, mac_ring_type_t, const int, 857 mac_group_info_t *, mac_group_handle_t); 858 int ixgbe_rx_ring_intr_enable(mac_intr_handle_t); 859 int ixgbe_rx_ring_intr_disable(mac_intr_handle_t); 860 861 /* 862 * Function prototypes in ixgbe_gld.c 863 */ 864 int ixgbe_m_start(void *); 865 void ixgbe_m_stop(void *); 866 int ixgbe_m_promisc(void *, boolean_t); 867 int ixgbe_m_multicst(void *, boolean_t, const uint8_t *); 868 int ixgbe_m_stat(void *, uint_t, uint64_t *); 869 void ixgbe_m_resources(void *); 870 void ixgbe_m_ioctl(void *, queue_t *, mblk_t *); 871 boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *); 872 873 /* 874 * Function prototypes in ixgbe_rx.c 875 */ 876 mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int); 877 void ixgbe_rx_recycle(caddr_t arg); 878 mblk_t *ixgbe_ring_rx_poll(void *, int); 879 880 /* 881 * Function prototypes in ixgbe_tx.c 882 */ 883 mblk_t *ixgbe_ring_tx(void *, mblk_t *); 884 void ixgbe_free_tcb(tx_control_block_t *); 885 void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *); 886 uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *); 887 uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *); 888 889 /* 890 * Function prototypes in ixgbe_log.c 891 */ 892 void ixgbe_notice(void *, const char *, ...); 893 void ixgbe_log(void *, const char *, ...); 894 void ixgbe_error(void *, const char *, ...); 895 896 /* 897 * Function prototypes in ixgbe_ndd.c 898 */ 899 int ixgbe_nd_init(ixgbe_t *); 900 void ixgbe_nd_cleanup(ixgbe_t *); 901 enum ioc_reply ixgbe_nd_ioctl(ixgbe_t *, queue_t *, mblk_t *, struct iocblk *); 902 903 /* 904 * Function prototypes in ixgbe_stat.c 905 */ 906 int ixgbe_init_stats(ixgbe_t *); 907 908 #ifdef __cplusplus 909 } 910 #endif 911 912 #endif /* _IXGBE_SW_H */ 913