1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #ifndef _IXGBE_SW_H 30 #define _IXGBE_SW_H 31 32 #pragma ident "%Z%%M% %I% %E% SMI" 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #include <sys/types.h> 39 #include <sys/conf.h> 40 #include <sys/debug.h> 41 #include <sys/stropts.h> 42 #include <sys/stream.h> 43 #include <sys/strsun.h> 44 #include <sys/strlog.h> 45 #include <sys/kmem.h> 46 #include <sys/stat.h> 47 #include <sys/kstat.h> 48 #include <sys/modctl.h> 49 #include <sys/errno.h> 50 #include <sys/dlpi.h> 51 #include <sys/mac.h> 52 #include <sys/mac_ether.h> 53 #include <sys/vlan.h> 54 #include <sys/ddi.h> 55 #include <sys/sunddi.h> 56 #include <sys/pci.h> 57 #include <sys/pcie.h> 58 #include <sys/sdt.h> 59 #include <sys/ethernet.h> 60 #include <sys/pattr.h> 61 #include <sys/strsubr.h> 62 #include <sys/netlb.h> 63 #include <sys/random.h> 64 #include <inet/common.h> 65 #include <inet/tcp.h> 66 #include <inet/ip.h> 67 #include <inet/mi.h> 68 #include <inet/nd.h> 69 #include <sys/bitmap.h> 70 #include <sys/ddifm.h> 71 #include <sys/fm/protocol.h> 72 #include <sys/fm/util.h> 73 #include <sys/fm/io/ddi.h> 74 #include "ixgbe_api.h" 75 76 #define MODULE_NAME "ixgbe" /* module name */ 77 78 #define IXGBE_FAILURE DDI_FAILURE 79 80 #define IXGBE_UNKNOWN 0x00 81 #define IXGBE_INITIALIZED 0x01 82 #define IXGBE_STARTED 0x02 83 #define IXGBE_SUSPENDED 0x04 84 85 #define MAX_NUM_UNICAST_ADDRESSES 0x10 86 #define MAX_NUM_MULTICAST_ADDRESSES 0x1000 87 #define IXGBE_INTR_NONE 0 88 #define IXGBE_INTR_MSIX 1 89 #define IXGBE_INTR_MSI 2 90 #define IXGBE_INTR_LEGACY 3 91 92 #define MAX_COOKIE 18 93 #define MIN_NUM_TX_DESC 2 94 95 /* 96 * Maximum values for user configurable parameters 97 */ 98 99 /* 100 * MAX_xx_QUEUE_NUM values need to be the maximum of all supported 101 * silicon types. 102 */ 103 #define MAX_TX_QUEUE_NUM 32 104 #define MAX_RX_QUEUE_NUM 64 105 106 #define MAX_TX_RING_SIZE 4096 107 #define MAX_RX_RING_SIZE 4096 108 109 #define MAX_MTU 16366 110 #define MAX_RX_LIMIT_PER_INTR 4096 111 #define MAX_INTR_THROTTLING 65535 112 113 #define MAX_RX_COPY_THRESHOLD 9216 114 #define MAX_TX_COPY_THRESHOLD 9216 115 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 116 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 117 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 118 119 /* 120 * Minimum values for user configurable parameters 121 */ 122 #define MIN_TX_QUEUE_NUM 1 123 #define MIN_RX_QUEUE_NUM 1 124 #define MIN_TX_RING_SIZE 64 125 #define MIN_RX_RING_SIZE 64 126 127 #define MIN_MTU ETHERMIN 128 #define MIN_RX_LIMIT_PER_INTR 16 129 #define MIN_INTR_THROTTLING 0 130 #define MIN_TX_COPY_THRESHOLD 0 131 #define MIN_RX_COPY_THRESHOLD 0 132 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 133 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 134 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 135 136 /* 137 * Default values for user configurable parameters 138 */ 139 #define DEFAULT_TX_QUEUE_NUM 1 140 #define DEFAULT_RX_QUEUE_NUM 1 141 #define DEFAULT_TX_RING_SIZE 512 142 #define DEFAULT_RX_RING_SIZE 512 143 144 #define DEFAULT_MTU ETHERMTU 145 #define DEFAULT_RX_LIMIT_PER_INTR 256 146 #define DEFAULT_INTR_THROTTLING 200 /* In unit of 256 nsec */ 147 #define DEFAULT_RX_COPY_THRESHOLD 128 148 #define DEFAULT_TX_COPY_THRESHOLD 512 149 #define DEFAULT_TX_RECYCLE_THRESHOLD MAX_COOKIE 150 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 151 #define DEFAULT_TX_RESCHED_THRESHOLD 128 152 #define DEFAULT_FCRTH 0x20000 153 #define DEFAULT_FCRTL 0x10000 154 #define DEFAULT_FCPAUSE 0xFFFF 155 156 #define DEFAULT_TX_HCKSUM_ENABLE B_TRUE 157 #define DEFAULT_RX_HCKSUM_ENABLE B_TRUE 158 #define DEFAULT_LSO_ENABLE B_TRUE 159 #define DEFAULT_TX_HEAD_WB_ENABLE B_TRUE 160 161 #define IXGBE_LSO_MAXLEN 65535 162 163 #define TX_DRAIN_TIME 200 164 #define RX_DRAIN_TIME 200 165 166 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 167 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 168 169 /* 170 * limits on msi-x vectors for 82598 171 */ 172 #define IXGBE_MAX_INTR_VECTOR 18 173 #define IXGBE_MAX_OTHER_VECTOR 2 174 #define IXGBE_MAX_RING_VECTOR (IXGBE_MAX_INTR_VECTOR - IXGBE_MAX_OTHER_VECTOR) 175 176 /* 177 * Extra register bit masks for 82598 178 */ 179 #define IXGBE_PCS1GANA_FDC 0x20 180 #define IXGBE_PCS1GANLP_LPFD 0x20 181 #define IXGBE_PCS1GANLP_LPHD 0x40 182 183 /* 184 * Defined for IP header alignment. 185 */ 186 #define IPHDR_ALIGN_ROOM 2 187 188 /* 189 * Bit flags for attach_progress 190 */ 191 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 192 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 193 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 194 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 195 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 196 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 197 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 198 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 199 #define ATTACH_PROGRESS_INIT_RINGS 0x0100 /* Rings initialized */ 200 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 201 #define ATTACH_PROGRESS_NDD 0x0400 /* NDD initialized */ 202 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 203 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 204 #define ATTACH_PROGRESS_FM_INIT 0x2000 /* FMA initialized */ 205 206 #define PROP_DEFAULT_MTU "default_mtu" 207 #define PROP_FLOW_CONTROL "flow_control" 208 #define PROP_TX_QUEUE_NUM "tx_queue_number" 209 #define PROP_TX_RING_SIZE "tx_ring_size" 210 #define PROP_RX_QUEUE_NUM "rx_queue_number" 211 #define PROP_RX_RING_SIZE "rx_ring_size" 212 213 #define PROP_INTR_FORCE "intr_force" 214 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 215 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 216 #define PROP_LSO_ENABLE "lso_enable" 217 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 218 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 219 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 220 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 221 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 222 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 223 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 224 #define PROP_INTR_THROTTLING "intr_throttling" 225 #define PROP_FM_CAPABLE "fm_capable" 226 227 #define IXGBE_LB_NONE 0 228 #define IXGBE_LB_EXTERNAL 1 229 #define IXGBE_LB_INTERNAL_MAC 2 230 #define IXGBE_LB_INTERNAL_PHY 3 231 #define IXGBE_LB_INTERNAL_SERDES 4 232 233 /* 234 * Shorthand for the NDD parameters 235 */ 236 #define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].val 237 #define param_pause_cap nd_params[PARAM_PAUSE_CAP].val 238 #define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].val 239 #define param_10000fdx_cap nd_params[PARAM_10000FDX_CAP].val 240 #define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].val 241 #define param_100fdx_cap nd_params[PARAM_1000FDX_CAP].val 242 #define param_rem_fault nd_params[PARAM_REM_FAULT].val 243 244 #define param_adv_autoneg_cap nd_params[PARAM_ADV_AUTONEG_CAP].val 245 #define param_adv_pause_cap nd_params[PARAM_ADV_PAUSE_CAP].val 246 #define param_adv_asym_pause_cap nd_params[PARAM_ADV_ASYM_PAUSE_CAP].val 247 #define param_adv_10000fdx_cap nd_params[PARAM_ADV_10000FDX_CAP].val 248 #define param_adv_1000fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 249 #define param_adv_100fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 250 #define param_adv_rem_fault nd_params[PARAM_ADV_REM_FAULT].val 251 252 #define param_lp_autoneg_cap nd_params[PARAM_LP_AUTONEG_CAP].val 253 #define param_lp_pause_cap nd_params[PARAM_LP_PAUSE_CAP].val 254 #define param_lp_asym_pause_cap nd_params[PARAM_LP_ASYM_PAUSE_CAP].val 255 #define param_lp_10000fdx_cap nd_params[PARAM_LP_10000FDX_CAP].val 256 #define param_lp_1000fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 257 #define param_lp_100fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 258 #define param_lp_rem_fault nd_params[PARAM_LP_REM_FAULT].val 259 260 enum ioc_reply { 261 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 262 IOC_DONE, /* OK, reply sent */ 263 IOC_ACK, /* OK, just send ACK */ 264 IOC_REPLY /* OK, just send reply */ 265 }; 266 267 #define MBLK_LEN(mp) ((uintptr_t)(mp)->b_wptr - \ 268 (uintptr_t)(mp)->b_rptr) 269 270 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 271 0, 0, (flag))) 272 273 /* 274 * Defined for ring index operations 275 * ASSERT(index < limit) 276 * ASSERT(step < limit) 277 * ASSERT(index1 < limit) 278 * ASSERT(index2 < limit) 279 */ 280 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 281 (index) + (step) : (index) + (step) - (limit)) 282 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 283 (index) - (step) : (index) + (limit) - (step)) 284 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 285 (index2) - (index1) : (index2) + (limit) - (index1)) 286 287 #define LINK_LIST_INIT(_LH) \ 288 (_LH)->head = (_LH)->tail = NULL 289 290 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 291 292 #define LIST_POP_HEAD(_LH) \ 293 (single_link_t *)(_LH)->head; \ 294 { \ 295 if ((_LH)->head != NULL) { \ 296 (_LH)->head = (_LH)->head->link; \ 297 if ((_LH)->head == NULL) \ 298 (_LH)->tail = NULL; \ 299 } \ 300 } 301 302 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 303 304 #define LIST_PUSH_TAIL(_LH, _E) \ 305 if ((_LH)->tail != NULL) { \ 306 (_LH)->tail->link = (single_link_t *)(_E); \ 307 (_LH)->tail = (single_link_t *)(_E); \ 308 } else { \ 309 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 310 } \ 311 (_E)->link = NULL; 312 313 #define LIST_GET_NEXT(_LH, _E) \ 314 (((_LH)->tail == (single_link_t *)(_E)) ? \ 315 NULL : ((single_link_t *)(_E))->link) 316 317 318 typedef struct single_link { 319 struct single_link *link; 320 } single_link_t; 321 322 typedef struct link_list { 323 single_link_t *head; 324 single_link_t *tail; 325 } link_list_t; 326 327 /* 328 * Property lookups 329 */ 330 #define IXGBE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 331 DDI_PROP_DONTPASS, (n)) 332 #define IXGBE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 333 DDI_PROP_DONTPASS, (n), -1) 334 335 336 /* 337 * Named Data (ND) Parameter Management Structure 338 */ 339 typedef struct { 340 struct ixgbe *private; 341 uint32_t info; 342 uint32_t min; 343 uint32_t max; 344 uint32_t val; 345 char *name; 346 } nd_param_t; 347 348 /* 349 * NDD parameter indexes, divided into: 350 * 351 * read-only parameters describing the hardware's capabilities 352 * read-write parameters controlling the advertised capabilities 353 * read-only parameters describing the partner's capabilities 354 * read-write parameters controlling the force speed and duplex 355 * read-only parameters describing the link state 356 * read-only parameters describing the driver properties 357 * read-write parameters controlling the driver properties 358 */ 359 enum { 360 PARAM_AUTONEG_CAP, 361 PARAM_PAUSE_CAP, 362 PARAM_ASYM_PAUSE_CAP, 363 PARAM_10000FDX_CAP, 364 PARAM_1000FDX_CAP, 365 PARAM_100FDX_CAP, 366 PARAM_REM_FAULT, 367 368 PARAM_ADV_AUTONEG_CAP, 369 PARAM_ADV_PAUSE_CAP, 370 PARAM_ADV_ASYM_PAUSE_CAP, 371 PARAM_ADV_10000FDX_CAP, 372 PARAM_ADV_1000FDX_CAP, 373 PARAM_ADV_100FDX_CAP, 374 PARAM_ADV_REM_FAULT, 375 376 PARAM_LP_AUTONEG_CAP, 377 PARAM_LP_PAUSE_CAP, 378 PARAM_LP_ASYM_PAUSE_CAP, 379 PARAM_LP_10000FDX_CAP, 380 PARAM_LP_1000FDX_CAP, 381 PARAM_LP_100FDX_CAP, 382 PARAM_LP_REM_FAULT, 383 384 PARAM_LINK_STATUS, 385 PARAM_LINK_SPEED, 386 PARAM_LINK_DUPLEX, 387 388 PARAM_COUNT 389 }; 390 391 typedef union ixgbe_ether_addr { 392 struct { 393 uint32_t high; 394 uint32_t low; 395 } reg; 396 struct { 397 uint8_t set; 398 uint8_t redundant; 399 uint8_t addr[ETHERADDRL]; 400 } mac; 401 } ixgbe_ether_addr_t; 402 403 typedef enum { 404 USE_NONE, 405 USE_COPY, 406 USE_DMA 407 } tx_type_t; 408 409 typedef enum { 410 RCB_FREE, 411 RCB_SENDUP 412 } rcb_state_t; 413 414 typedef struct ixgbe_tx_context { 415 uint32_t hcksum_flags; 416 uint32_t ip_hdr_len; 417 uint32_t mac_hdr_len; 418 uint32_t l4_proto; 419 uint32_t mss; 420 uint32_t l4_hdr_len; 421 boolean_t lso_flag; 422 } ixgbe_tx_context_t; 423 424 /* 425 * Hold address/length of each DMA segment 426 */ 427 typedef struct sw_desc { 428 uint64_t address; 429 size_t length; 430 } sw_desc_t; 431 432 /* 433 * Handles and addresses of DMA buffer 434 */ 435 typedef struct dma_buffer { 436 caddr_t address; /* Virtual address */ 437 uint64_t dma_address; /* DMA (Hardware) address */ 438 ddi_acc_handle_t acc_handle; /* Data access handle */ 439 ddi_dma_handle_t dma_handle; /* DMA handle */ 440 size_t size; /* Buffer size */ 441 size_t len; /* Data length in the buffer */ 442 } dma_buffer_t; 443 444 /* 445 * Tx Control Block 446 */ 447 typedef struct tx_control_block { 448 single_link_t link; 449 uint32_t frag_num; 450 uint32_t desc_num; 451 mblk_t *mp; 452 tx_type_t tx_type; 453 ddi_dma_handle_t tx_dma_handle; 454 dma_buffer_t tx_buf; 455 sw_desc_t desc[MAX_COOKIE]; 456 } tx_control_block_t; 457 458 /* 459 * RX Control Block 460 */ 461 typedef struct rx_control_block { 462 mblk_t *mp; 463 rcb_state_t state; 464 dma_buffer_t rx_buf; 465 frtn_t free_rtn; 466 struct ixgbe_rx_ring *rx_ring; 467 } rx_control_block_t; 468 469 /* 470 * Software Data Structure for Tx Ring 471 */ 472 typedef struct ixgbe_tx_ring { 473 uint32_t index; /* Ring index */ 474 uint32_t intr_vector; /* Interrupt vector index */ 475 uint32_t vect_bit; /* vector's bit in register */ 476 477 /* 478 * Mutexes 479 */ 480 kmutex_t tx_lock; 481 kmutex_t recycle_lock; 482 kmutex_t tcb_head_lock; 483 kmutex_t tcb_tail_lock; 484 485 /* 486 * Tx descriptor ring definitions 487 */ 488 dma_buffer_t tbd_area; 489 union ixgbe_adv_tx_desc *tbd_ring; 490 uint32_t tbd_head; /* Index of next tbd to recycle */ 491 uint32_t tbd_tail; /* Index of next tbd to transmit */ 492 uint32_t tbd_free; /* Number of free tbd */ 493 494 /* 495 * Tx control block list definitions 496 */ 497 tx_control_block_t *tcb_area; 498 tx_control_block_t **work_list; 499 tx_control_block_t **free_list; 500 uint32_t tcb_head; /* Head index of free list */ 501 uint32_t tcb_tail; /* Tail index of free list */ 502 uint32_t tcb_free; /* Number of free tcb in free list */ 503 504 uint32_t *tbd_head_wb; /* Head write-back */ 505 uint32_t (*tx_recycle)(struct ixgbe_tx_ring *); 506 507 /* 508 * s/w context structure for TCP/UDP checksum offload 509 * and LSO. 510 */ 511 ixgbe_tx_context_t tx_context; 512 513 /* 514 * Tx ring settings and status 515 */ 516 uint32_t ring_size; /* Tx descriptor ring size */ 517 uint32_t free_list_size; /* Tx free list size */ 518 uint32_t copy_thresh; 519 uint32_t recycle_thresh; 520 uint32_t overload_thresh; 521 uint32_t resched_thresh; 522 523 boolean_t reschedule; 524 uint32_t recycle_fail; 525 uint32_t stall_watchdog; 526 527 #ifdef IXGBE_DEBUG 528 /* 529 * Debug statistics 530 */ 531 uint32_t stat_overload; 532 uint32_t stat_fail_no_tbd; 533 uint32_t stat_fail_no_tcb; 534 uint32_t stat_fail_dma_bind; 535 uint32_t stat_reschedule; 536 #endif 537 538 /* 539 * Pointer to the ixgbe struct 540 */ 541 struct ixgbe *ixgbe; 542 543 } ixgbe_tx_ring_t; 544 545 /* 546 * Software Receive Ring 547 */ 548 typedef struct ixgbe_rx_ring { 549 uint32_t index; /* Ring index */ 550 uint32_t intr_vector; /* Interrupt vector index */ 551 uint32_t vect_bit; /* vector's bit in register */ 552 553 /* 554 * Mutexes 555 */ 556 kmutex_t rx_lock; /* Rx access lock */ 557 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 558 559 /* 560 * Rx descriptor ring definitions 561 */ 562 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 563 union ixgbe_adv_rx_desc *rbd_ring; /* Rx desc ring */ 564 uint32_t rbd_next; /* Index of next rx desc */ 565 566 /* 567 * Rx control block list definitions 568 */ 569 rx_control_block_t *rcb_area; 570 rx_control_block_t **work_list; /* Work list of rcbs */ 571 rx_control_block_t **free_list; /* Free list of rcbs */ 572 uint32_t rcb_head; /* Index of next free rcb */ 573 uint32_t rcb_tail; /* Index to put recycled rcb */ 574 uint32_t rcb_free; /* Number of free rcbs */ 575 576 /* 577 * Rx ring settings and status 578 */ 579 uint32_t ring_size; /* Rx descriptor ring size */ 580 uint32_t free_list_size; /* Rx free list size */ 581 uint32_t limit_per_intr; /* Max packets per interrupt */ 582 uint32_t copy_thresh; 583 584 #ifdef IXGBE_DEBUG 585 /* 586 * Debug statistics 587 */ 588 uint32_t stat_frame_error; 589 uint32_t stat_cksum_error; 590 uint32_t stat_exceed_pkt; 591 #endif 592 593 struct ixgbe *ixgbe; /* Pointer to ixgbe struct */ 594 595 } ixgbe_rx_ring_t; 596 597 /* 598 * structure to map ring cleanup to msi-x vector 599 */ 600 typedef struct ixgbe_ring_vector { 601 struct ixgbe *ixgbe; /* point to my adapter */ 602 ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)]; /* bitmap of rx rings */ 603 int rxr_cnt; /* count rx rings */ 604 ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)]; /* bitmap of tx rings */ 605 int txr_cnt; /* count tx rings */ 606 } ixgbe_ring_vector_t; 607 608 /* 609 * Software adapter state 610 */ 611 typedef struct ixgbe { 612 int instance; 613 mac_handle_t mac_hdl; 614 dev_info_t *dip; 615 struct ixgbe_hw hw; 616 struct ixgbe_osdep osdep; 617 618 uint32_t ixgbe_state; 619 link_state_t link_state; 620 uint32_t link_speed; 621 uint32_t link_duplex; 622 uint32_t link_down_timeout; 623 624 uint32_t reset_count; 625 uint32_t attach_progress; 626 uint32_t loopback_mode; 627 uint32_t default_mtu; 628 uint32_t max_frame_size; 629 630 /* 631 * Each msi-x vector: map vector to ring cleanup 632 */ 633 ixgbe_ring_vector_t vect_map[IXGBE_MAX_RING_VECTOR]; 634 635 /* 636 * Receive Rings 637 */ 638 ixgbe_rx_ring_t *rx_rings; /* Array of rx rings */ 639 uint32_t num_rx_rings; /* Number of rx rings in use */ 640 uint32_t rx_ring_size; /* Rx descriptor ring size */ 641 uint32_t rx_buf_size; /* Rx buffer size */ 642 643 /* 644 * Transmit Rings 645 */ 646 ixgbe_tx_ring_t *tx_rings; /* Array of tx rings */ 647 uint32_t num_tx_rings; /* Number of tx rings in use */ 648 uint32_t tx_ring_size; /* Tx descriptor ring size */ 649 uint32_t tx_buf_size; /* Tx buffer size */ 650 651 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 652 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 653 boolean_t lso_enable; /* Large Segment Offload */ 654 uint32_t tx_copy_thresh; /* Tx copy threshold */ 655 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 656 uint32_t tx_overload_thresh; /* Tx overload threshold */ 657 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 658 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 659 uint32_t rx_copy_thresh; /* Rx copy threshold */ 660 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 661 uint32_t intr_throttling[IXGBE_MAX_RING_VECTOR]; 662 uint32_t intr_force; 663 int fm_capabilities; /* FMA capabilities */ 664 665 int intr_type; 666 int intr_cnt; 667 int intr_cap; 668 size_t intr_size; 669 uint_t intr_pri; 670 ddi_intr_handle_t *htable; 671 uint32_t eims_mask; 672 673 kmutex_t gen_lock; /* General lock for device access */ 674 kmutex_t watchdog_lock; 675 676 boolean_t watchdog_enable; 677 boolean_t watchdog_start; 678 timeout_id_t watchdog_tid; 679 680 boolean_t unicst_init; 681 uint32_t unicst_avail; 682 uint32_t unicst_total; 683 ixgbe_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 684 uint32_t mcast_count; 685 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 686 687 /* 688 * Kstat definitions 689 */ 690 kstat_t *ixgbe_ks; 691 692 /* 693 * NDD definitions 694 */ 695 caddr_t nd_data; 696 nd_param_t nd_params[PARAM_COUNT]; 697 698 } ixgbe_t; 699 700 typedef struct ixgbe_stat { 701 702 kstat_named_t link_speed; /* Link Speed */ 703 #ifdef IXGBE_DEBUG 704 kstat_named_t reset_count; /* Reset Count */ 705 706 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 707 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 708 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 709 710 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 711 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 712 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 713 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 714 kstat_named_t tx_reschedule; /* Tx Reschedule */ 715 716 kstat_named_t gprc; /* Good Packets Received Count */ 717 kstat_named_t gptc; /* Good Packets Xmitted Count */ 718 kstat_named_t gor; /* Good Octets Received Count */ 719 kstat_named_t got; /* Good Octets Xmitd Count */ 720 kstat_named_t prc64; /* Packets Received - 64b */ 721 kstat_named_t prc127; /* Packets Received - 65-127b */ 722 kstat_named_t prc255; /* Packets Received - 127-255b */ 723 kstat_named_t prc511; /* Packets Received - 256-511b */ 724 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 725 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 726 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 727 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 728 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 729 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 730 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 731 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 732 #endif 733 kstat_named_t crcerrs; /* CRC Error Count */ 734 kstat_named_t illerrc; /* Illegal Byte Error Count */ 735 kstat_named_t errbc; /* Error Byte Count */ 736 kstat_named_t mspdc; /* MAC Short Packet Discard Count */ 737 kstat_named_t mpc; /* Missed Packets Count */ 738 kstat_named_t mlfc; /* MAC Local Fault Count */ 739 kstat_named_t mrfc; /* MAC Remote Fault Count */ 740 kstat_named_t rlec; /* Receive Length Error Count */ 741 kstat_named_t lxontxc; /* Link XON Transmitted Count */ 742 kstat_named_t lxonrxc; /* Link XON Received Count */ 743 kstat_named_t lxofftxc; /* Link XOFF Transmitted Count */ 744 kstat_named_t lxoffrxc; /* Link XOFF Received Count */ 745 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 746 kstat_named_t mprc; /* Multicast Pkts Received Count */ 747 kstat_named_t rnbc; /* Receive No Buffers Count */ 748 kstat_named_t ruc; /* Receive Undersize Count */ 749 kstat_named_t rfc; /* Receive Frag Count */ 750 kstat_named_t roc; /* Receive Oversize Count */ 751 kstat_named_t rjc; /* Receive Jabber Count */ 752 kstat_named_t tor; /* Total Octets Recvd Count */ 753 kstat_named_t tpr; /* Total Packets Received */ 754 kstat_named_t tpt; /* Total Packets Xmitted */ 755 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 756 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 757 } ixgbe_stat_t; 758 759 /* 760 * Function prototypes in ixgbe_buf.c 761 */ 762 int ixgbe_alloc_dma(ixgbe_t *); 763 void ixgbe_free_dma(ixgbe_t *); 764 void ixgbe_set_fma_flags(int, int); 765 766 /* 767 * Function prototypes in ixgbe_main.c 768 */ 769 int ixgbe_start(ixgbe_t *); 770 void ixgbe_stop(ixgbe_t *); 771 int ixgbe_driver_setup_link(ixgbe_t *, boolean_t); 772 int ixgbe_unicst_set(ixgbe_t *, const uint8_t *, mac_addr_slot_t); 773 int ixgbe_multicst_add(ixgbe_t *, const uint8_t *); 774 int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *); 775 enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *); 776 777 void ixgbe_enable_watchdog_timer(ixgbe_t *); 778 void ixgbe_disable_watchdog_timer(ixgbe_t *); 779 int ixgbe_atomic_reserve(uint32_t *, uint32_t); 780 781 int ixgbe_check_acc_handle(ddi_acc_handle_t handle); 782 int ixgbe_check_dma_handle(ddi_dma_handle_t handle); 783 void ixgbe_fm_ereport(ixgbe_t *, char *); 784 785 /* 786 * Function prototypes in ixgbe_gld.c 787 */ 788 int ixgbe_m_start(void *); 789 void ixgbe_m_stop(void *); 790 int ixgbe_m_promisc(void *, boolean_t); 791 int ixgbe_m_multicst(void *, boolean_t, const uint8_t *); 792 int ixgbe_m_unicst(void *, const uint8_t *); 793 int ixgbe_m_stat(void *, uint_t, uint64_t *); 794 void ixgbe_m_resources(void *); 795 void ixgbe_m_ioctl(void *, queue_t *, mblk_t *); 796 int ixgbe_m_unicst_add(void *, mac_multi_addr_t *); 797 int ixgbe_m_unicst_remove(void *, mac_addr_slot_t); 798 int ixgbe_m_unicst_modify(void *, mac_multi_addr_t *); 799 int ixgbe_m_unicst_get(void *, mac_multi_addr_t *); 800 boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *); 801 802 /* 803 * Function prototypes in ixgbe_rx.c 804 */ 805 mblk_t *ixgbe_rx(ixgbe_rx_ring_t *); 806 void ixgbe_rx_recycle(caddr_t arg); 807 808 /* 809 * Function prototypes in ixgbe_tx.c 810 */ 811 mblk_t *ixgbe_m_tx(void *, mblk_t *); 812 void ixgbe_free_tcb(tx_control_block_t *); 813 void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *); 814 uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *); 815 uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *); 816 817 /* 818 * Function prototypes in ixgbe_log.c 819 */ 820 void ixgbe_notice(void *, const char *, ...); 821 void ixgbe_log(void *, const char *, ...); 822 void ixgbe_error(void *, const char *, ...); 823 824 /* 825 * Function prototypes in ixgbe_ndd.c 826 */ 827 int ixgbe_nd_init(ixgbe_t *); 828 void ixgbe_nd_cleanup(ixgbe_t *); 829 enum ioc_reply ixgbe_nd_ioctl(ixgbe_t *, queue_t *, mblk_t *, struct iocblk *); 830 831 /* 832 * Function prototypes in ixgbe_stat.c 833 */ 834 int ixgbe_init_stats(ixgbe_t *); 835 836 837 #ifdef __cplusplus 838 } 839 #endif 840 841 #endif /* _IXGBE_SW_H */ 842