xref: /titanic_51/usr/src/uts/common/io/ixgbe/ixgbe_sw.h (revision 7b3411b6ce9d5ba373d2e36a6c8db48b2dfb74b7)
1 /*
2  * CDDL HEADER START
3  *
4  * Copyright(c) 2007-2009 Intel Corporation. All rights reserved.
5  * The contents of this file are subject to the terms of the
6  * Common Development and Distribution License (the "License").
7  * You may not use this file except in compliance with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 
23 /*
24  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
25  * Use is subject to license terms.
26  */
27 
28 #ifndef	_IXGBE_SW_H
29 #define	_IXGBE_SW_H
30 
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34 
35 #include <sys/types.h>
36 #include <sys/conf.h>
37 #include <sys/debug.h>
38 #include <sys/stropts.h>
39 #include <sys/stream.h>
40 #include <sys/strsun.h>
41 #include <sys/strlog.h>
42 #include <sys/kmem.h>
43 #include <sys/stat.h>
44 #include <sys/kstat.h>
45 #include <sys/modctl.h>
46 #include <sys/errno.h>
47 #include <sys/dlpi.h>
48 #include <sys/mac_provider.h>
49 #include <sys/mac_ether.h>
50 #include <sys/vlan.h>
51 #include <sys/ddi.h>
52 #include <sys/sunddi.h>
53 #include <sys/pci.h>
54 #include <sys/pcie.h>
55 #include <sys/sdt.h>
56 #include <sys/ethernet.h>
57 #include <sys/pattr.h>
58 #include <sys/strsubr.h>
59 #include <sys/netlb.h>
60 #include <sys/random.h>
61 #include <inet/common.h>
62 #include <inet/tcp.h>
63 #include <inet/ip.h>
64 #include <inet/mi.h>
65 #include <inet/nd.h>
66 #include <sys/bitmap.h>
67 #include <sys/ddifm.h>
68 #include <sys/fm/protocol.h>
69 #include <sys/fm/util.h>
70 #include <sys/fm/io/ddi.h>
71 #include "ixgbe_api.h"
72 
73 #define	MODULE_NAME			"ixgbe"	/* module name */
74 
75 #define	IXGBE_FAILURE			DDI_FAILURE
76 
77 #define	IXGBE_UNKNOWN			0x00
78 #define	IXGBE_INITIALIZED		0x01
79 #define	IXGBE_STARTED			0x02
80 #define	IXGBE_SUSPENDED			0x04
81 
82 #define	MAX_NUM_UNICAST_ADDRESSES 	0x10
83 #define	MAX_NUM_MULTICAST_ADDRESSES 	0x1000
84 #define	IXGBE_INTR_NONE			0
85 #define	IXGBE_INTR_MSIX			1
86 #define	IXGBE_INTR_MSI			2
87 #define	IXGBE_INTR_LEGACY		3
88 
89 #define	IXGBE_POLL_NULL			-1
90 
91 #define	MAX_COOKIE			18
92 #define	MIN_NUM_TX_DESC			2
93 
94 #define	IXGBE_TX_DESC_LIMIT		32	/* tx desc limitation	*/
95 
96 #define	IXGBE_ADAPTER_REGSET		1	/* map adapter registers */
97 
98 #define	IXGBE_RX_STOPPED		0x1
99 
100 /*
101  * MAX_xx_QUEUE_NUM and MAX_INTR_VECTOR values need to be the maximum of all
102  * supported silicon types.
103  */
104 #define	MAX_TX_QUEUE_NUM		128
105 #define	MAX_RX_QUEUE_NUM		128
106 #define	MAX_INTR_VECTOR			64
107 
108 /*
109  * Maximum values for user configurable parameters
110  */
111 #define	MAX_RX_GROUP_NUM		1
112 #define	MAX_TX_RING_SIZE		4096
113 #define	MAX_RX_RING_SIZE		4096
114 
115 #define	MAX_MTU				16366
116 #define	MAX_RX_LIMIT_PER_INTR		4096
117 
118 #define	MAX_RX_COPY_THRESHOLD		9216
119 #define	MAX_TX_COPY_THRESHOLD		9216
120 #define	MAX_TX_RECYCLE_THRESHOLD	DEFAULT_TX_RING_SIZE
121 #define	MAX_TX_OVERLOAD_THRESHOLD	DEFAULT_TX_RING_SIZE
122 #define	MAX_TX_RESCHED_THRESHOLD	DEFAULT_TX_RING_SIZE
123 
124 /*
125  * Minimum values for user configurable parameters
126  */
127 #define	MIN_RX_GROUP_NUM		1
128 #define	MIN_TX_RING_SIZE		64
129 #define	MIN_RX_RING_SIZE		64
130 
131 #define	MIN_MTU				ETHERMIN
132 #define	MIN_RX_LIMIT_PER_INTR		16
133 #define	MIN_TX_COPY_THRESHOLD		0
134 #define	MIN_RX_COPY_THRESHOLD		0
135 #define	MIN_TX_RECYCLE_THRESHOLD	MIN_NUM_TX_DESC
136 #define	MIN_TX_OVERLOAD_THRESHOLD	MIN_NUM_TX_DESC
137 #define	MIN_TX_RESCHED_THRESHOLD	MIN_NUM_TX_DESC
138 
139 /*
140  * Default values for user configurable parameters
141  */
142 #define	DEFAULT_RX_GROUP_NUM		1
143 #define	DEFAULT_TX_RING_SIZE		1024
144 #define	DEFAULT_RX_RING_SIZE		1024
145 
146 #define	DEFAULT_MTU			ETHERMTU
147 #define	DEFAULT_RX_LIMIT_PER_INTR	256
148 #define	DEFAULT_RX_COPY_THRESHOLD	128
149 #define	DEFAULT_TX_COPY_THRESHOLD	512
150 #define	DEFAULT_TX_RECYCLE_THRESHOLD	(MAX_COOKIE + 1)
151 #define	DEFAULT_TX_OVERLOAD_THRESHOLD	MIN_NUM_TX_DESC
152 #define	DEFAULT_TX_RESCHED_THRESHOLD	128
153 #define	DEFAULT_FCRTH			0x20000
154 #define	DEFAULT_FCRTL			0x10000
155 #define	DEFAULT_FCPAUSE			0xFFFF
156 
157 #define	DEFAULT_TX_HCKSUM_ENABLE	B_TRUE
158 #define	DEFAULT_RX_HCKSUM_ENABLE	B_TRUE
159 #define	DEFAULT_LSO_ENABLE		B_TRUE
160 #define	DEFAULT_MR_ENABLE		B_TRUE
161 #define	DEFAULT_TX_HEAD_WB_ENABLE	B_TRUE
162 
163 #define	IXGBE_LSO_MAXLEN		65535
164 
165 #define	TX_DRAIN_TIME			200
166 #define	RX_DRAIN_TIME			200
167 
168 #define	STALL_WATCHDOG_TIMEOUT		8	/* 8 seconds */
169 #define	MAX_LINK_DOWN_TIMEOUT		8	/* 8 seconds */
170 
171 /*
172  * Extra register bit masks for 82598
173  */
174 #define	IXGBE_PCS1GANA_FDC	0x20
175 #define	IXGBE_PCS1GANLP_LPFD	0x20
176 #define	IXGBE_PCS1GANLP_LPHD	0x40
177 
178 /*
179  * Defined for IP header alignment.
180  */
181 #define	IPHDR_ALIGN_ROOM		2
182 
183 /*
184  * Bit flags for attach_progress
185  */
186 #define	ATTACH_PROGRESS_PCI_CONFIG	0x0001	/* PCI config setup */
187 #define	ATTACH_PROGRESS_REGS_MAP	0x0002	/* Registers mapped */
188 #define	ATTACH_PROGRESS_PROPS		0x0004	/* Properties initialized */
189 #define	ATTACH_PROGRESS_ALLOC_INTR	0x0008	/* Interrupts allocated */
190 #define	ATTACH_PROGRESS_ALLOC_RINGS	0x0010	/* Rings allocated */
191 #define	ATTACH_PROGRESS_ADD_INTR	0x0020	/* Intr handlers added */
192 #define	ATTACH_PROGRESS_LOCKS		0x0040	/* Locks initialized */
193 #define	ATTACH_PROGRESS_INIT		0x0080	/* Device initialized */
194 #define	ATTACH_PROGRESS_STATS		0x0200	/* Kstats created */
195 #define	ATTACH_PROGRESS_MAC		0x0800	/* MAC registered */
196 #define	ATTACH_PROGRESS_ENABLE_INTR	0x1000	/* DDI interrupts enabled */
197 #define	ATTACH_PROGRESS_FM_INIT		0x2000	/* FMA initialized */
198 #define	ATTACH_PROGRESS_LSC_TASKQ	0x4000	/* LSC taskq created */
199 
200 #define	PROP_DEFAULT_MTU		"default_mtu"
201 #define	PROP_FLOW_CONTROL		"flow_control"
202 #define	PROP_TX_QUEUE_NUM		"tx_queue_number"
203 #define	PROP_TX_RING_SIZE		"tx_ring_size"
204 #define	PROP_RX_QUEUE_NUM		"rx_queue_number"
205 #define	PROP_RX_RING_SIZE		"rx_ring_size"
206 #define	PROP_RX_GROUP_NUM		"rx_group_number"
207 
208 #define	PROP_INTR_FORCE			"intr_force"
209 #define	PROP_TX_HCKSUM_ENABLE		"tx_hcksum_enable"
210 #define	PROP_RX_HCKSUM_ENABLE		"rx_hcksum_enable"
211 #define	PROP_LSO_ENABLE			"lso_enable"
212 #define	PROP_MR_ENABLE			"mr_enable"
213 #define	PROP_TX_HEAD_WB_ENABLE		"tx_head_wb_enable"
214 #define	PROP_TX_COPY_THRESHOLD		"tx_copy_threshold"
215 #define	PROP_TX_RECYCLE_THRESHOLD	"tx_recycle_threshold"
216 #define	PROP_TX_OVERLOAD_THRESHOLD	"tx_overload_threshold"
217 #define	PROP_TX_RESCHED_THRESHOLD	"tx_resched_threshold"
218 #define	PROP_RX_COPY_THRESHOLD		"rx_copy_threshold"
219 #define	PROP_RX_LIMIT_PER_INTR		"rx_limit_per_intr"
220 #define	PROP_INTR_THROTTLING		"intr_throttling"
221 #define	PROP_FM_CAPABLE			"fm_capable"
222 
223 #define	IXGBE_LB_NONE			0
224 #define	IXGBE_LB_EXTERNAL		1
225 #define	IXGBE_LB_INTERNAL_MAC		2
226 #define	IXGBE_LB_INTERNAL_PHY		3
227 #define	IXGBE_LB_INTERNAL_SERDES	4
228 
229 /*
230  * capability/feature flags
231  * Flags named _CAPABLE are set when the NIC hardware is capable of the feature.
232  * Separately, the flag named _ENABLED is set when the feature is enabled.
233  */
234 #define	IXGBE_FLAG_DCA_ENABLED		(u32)(1)
235 #define	IXGBE_FLAG_DCA_CAPABLE		(u32)(1 << 1)
236 #define	IXGBE_FLAG_DCB_ENABLED		(u32)(1 << 2)
237 #define	IXGBE_FLAG_DCB_CAPABLE		(u32)(1 << 4)
238 #define	IXGBE_FLAG_RSS_ENABLED		(u32)(1 << 4)
239 #define	IXGBE_FLAG_RSS_CAPABLE		(u32)(1 << 5)
240 #define	IXGBE_FLAG_VMDQ_CAPABLE		(u32)(1 << 6)
241 #define	IXGBE_FLAG_VMDQ_ENABLED		(u32)(1 << 7)
242 #define	IXGBE_FLAG_FAN_FAIL_CAPABLE	(u32)(1 << 8)
243 
244 /* adapter-specific info for each supported device type */
245 typedef struct adapter_info {
246 	uint32_t	max_rx_que_num;	/* maximum number of rx queues */
247 	uint32_t	min_rx_que_num;	/* minimum number of rx queues */
248 	uint32_t	def_rx_que_num;	/* default number of rx queues */
249 	uint32_t	max_tx_que_num;	/* maximum number of tx queues */
250 	uint32_t	min_tx_que_num;	/* minimum number of tx queues */
251 	uint32_t	def_tx_que_num;	/* default number of tx queues */
252 
253 	/*
254 	 * Interrupt throttling is in unit of 256 nsec
255 	 */
256 	uint32_t	max_intr_throttle; /* maximum interrupt throttle */
257 	uint32_t	min_intr_throttle; /* minimum interrupt throttle */
258 	uint32_t	def_intr_throttle; /* default interrupt throttle */
259 
260 	uint32_t	max_msix_vect;	/* maximum total msix vectors */
261 	uint32_t	max_ring_vect;	/* maximum number of ring vectors */
262 	uint32_t	max_other_vect;	/* maximum number of other vectors */
263 	uint32_t	other_intr;	/* "other" interrupt types handled */
264 	uint32_t	flags;		/* capability flags */
265 } adapter_info_t;
266 
267 /* bits representing all interrupt types other than tx & rx */
268 #define	IXGBE_OTHER_INTR	0x3ff00000
269 #define	IXGBE_82599_OTHER_INTR	0x86100000
270 
271 enum ioc_reply {
272 	IOC_INVAL = -1,	/* bad, NAK with EINVAL */
273 	IOC_DONE, 	/* OK, reply sent */
274 	IOC_ACK,	/* OK, just send ACK */
275 	IOC_REPLY	/* OK, just send reply */
276 };
277 
278 #define	DMA_SYNC(area, flag)	((void) ddi_dma_sync((area)->dma_handle, \
279 				    0, 0, (flag)))
280 
281 /*
282  * Defined for ring index operations
283  * ASSERT(index < limit)
284  * ASSERT(step < limit)
285  * ASSERT(index1 < limit)
286  * ASSERT(index2 < limit)
287  */
288 #define	NEXT_INDEX(index, step, limit)	(((index) + (step)) < (limit) ? \
289 	(index) + (step) : (index) + (step) - (limit))
290 #define	PREV_INDEX(index, step, limit)	((index) >= (step) ? \
291 	(index) - (step) : (index) + (limit) - (step))
292 #define	OFFSET(index1, index2, limit)	((index1) <= (index2) ? \
293 	(index2) - (index1) : (index2) + (limit) - (index1))
294 
295 #define	LINK_LIST_INIT(_LH)	\
296 	(_LH)->head = (_LH)->tail = NULL
297 
298 #define	LIST_GET_HEAD(_LH)	((single_link_t *)((_LH)->head))
299 
300 #define	LIST_POP_HEAD(_LH)	\
301 	(single_link_t *)(_LH)->head; \
302 	{ \
303 		if ((_LH)->head != NULL) { \
304 			(_LH)->head = (_LH)->head->link; \
305 			if ((_LH)->head == NULL) \
306 				(_LH)->tail = NULL; \
307 		} \
308 	}
309 
310 #define	LIST_GET_TAIL(_LH)	((single_link_t *)((_LH)->tail))
311 
312 #define	LIST_PUSH_TAIL(_LH, _E)	\
313 	if ((_LH)->tail != NULL) { \
314 		(_LH)->tail->link = (single_link_t *)(_E); \
315 		(_LH)->tail = (single_link_t *)(_E); \
316 	} else { \
317 		(_LH)->head = (_LH)->tail = (single_link_t *)(_E); \
318 	} \
319 	(_E)->link = NULL;
320 
321 #define	LIST_GET_NEXT(_LH, _E)		\
322 	(((_LH)->tail == (single_link_t *)(_E)) ? \
323 	NULL : ((single_link_t *)(_E))->link)
324 
325 
326 typedef struct single_link {
327 	struct single_link	*link;
328 } single_link_t;
329 
330 typedef struct link_list {
331 	single_link_t		*head;
332 	single_link_t		*tail;
333 } link_list_t;
334 
335 /*
336  * Property lookups
337  */
338 #define	IXGBE_PROP_EXISTS(d, n)	ddi_prop_exists(DDI_DEV_T_ANY, (d), \
339 				    DDI_PROP_DONTPASS, (n))
340 #define	IXGBE_PROP_GET_INT(d, n)	ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
341 				    DDI_PROP_DONTPASS, (n), -1)
342 
343 
344 /*
345  * Named Data (ND) Parameter Management Structure
346  */
347 typedef struct {
348 	struct ixgbe *private;
349 	uint32_t info;
350 	uint32_t min;
351 	uint32_t max;
352 	uint32_t val;
353 	char *name;
354 } nd_param_t;
355 
356 typedef union ixgbe_ether_addr {
357 	struct {
358 		uint32_t	high;
359 		uint32_t	low;
360 	} reg;
361 	struct {
362 		uint8_t		set;
363 		uint8_t		redundant;
364 		uint8_t		addr[ETHERADDRL];
365 	} mac;
366 } ixgbe_ether_addr_t;
367 
368 typedef enum {
369 	USE_NONE,
370 	USE_COPY,
371 	USE_DMA
372 } tx_type_t;
373 
374 typedef struct ixgbe_tx_context {
375 	uint32_t		hcksum_flags;
376 	uint32_t		ip_hdr_len;
377 	uint32_t		mac_hdr_len;
378 	uint32_t		l4_proto;
379 	uint32_t		mss;
380 	uint32_t		l4_hdr_len;
381 	boolean_t		lso_flag;
382 } ixgbe_tx_context_t;
383 
384 /*
385  * Hold address/length of each DMA segment
386  */
387 typedef struct sw_desc {
388 	uint64_t		address;
389 	size_t			length;
390 } sw_desc_t;
391 
392 /*
393  * Handles and addresses of DMA buffer
394  */
395 typedef struct dma_buffer {
396 	caddr_t			address;	/* Virtual address */
397 	uint64_t		dma_address;	/* DMA (Hardware) address */
398 	ddi_acc_handle_t	acc_handle;	/* Data access handle */
399 	ddi_dma_handle_t	dma_handle;	/* DMA handle */
400 	size_t			size;		/* Buffer size */
401 	size_t			len;		/* Data length in the buffer */
402 } dma_buffer_t;
403 
404 /*
405  * Tx Control Block
406  */
407 typedef struct tx_control_block {
408 	single_link_t		link;
409 	uint32_t		last_index; /* last descriptor of the pkt */
410 	uint32_t		frag_num;
411 	uint32_t		desc_num;
412 	mblk_t			*mp;
413 	tx_type_t		tx_type;
414 	ddi_dma_handle_t	tx_dma_handle;
415 	dma_buffer_t		tx_buf;
416 	sw_desc_t		desc[MAX_COOKIE];
417 } tx_control_block_t;
418 
419 /*
420  * RX Control Block
421  */
422 typedef struct rx_control_block {
423 	mblk_t			*mp;
424 	uint32_t		ref_cnt;
425 	dma_buffer_t		rx_buf;
426 	frtn_t			free_rtn;
427 	struct ixgbe_rx_data	*rx_data;
428 } rx_control_block_t;
429 
430 /*
431  * Software Data Structure for Tx Ring
432  */
433 typedef struct ixgbe_tx_ring {
434 	uint32_t		index;	/* Ring index */
435 	uint32_t		intr_vector;	/* Interrupt vector index */
436 	uint32_t		vect_bit;	/* vector's bit in register */
437 
438 	/*
439 	 * Mutexes
440 	 */
441 	kmutex_t		tx_lock;
442 	kmutex_t		recycle_lock;
443 	kmutex_t		tcb_head_lock;
444 	kmutex_t		tcb_tail_lock;
445 
446 	/*
447 	 * Tx descriptor ring definitions
448 	 */
449 	dma_buffer_t		tbd_area;
450 	union ixgbe_adv_tx_desc	*tbd_ring;
451 	uint32_t		tbd_head; /* Index of next tbd to recycle */
452 	uint32_t		tbd_tail; /* Index of next tbd to transmit */
453 	uint32_t		tbd_free; /* Number of free tbd */
454 
455 	/*
456 	 * Tx control block list definitions
457 	 */
458 	tx_control_block_t	*tcb_area;
459 	tx_control_block_t	**work_list;
460 	tx_control_block_t	**free_list;
461 	uint32_t		tcb_head; /* Head index of free list */
462 	uint32_t		tcb_tail; /* Tail index of free list */
463 	uint32_t		tcb_free; /* Number of free tcb in free list */
464 
465 	uint32_t		*tbd_head_wb; /* Head write-back */
466 	uint32_t		(*tx_recycle)(struct ixgbe_tx_ring *);
467 
468 	/*
469 	 * s/w context structure for TCP/UDP checksum offload
470 	 * and LSO.
471 	 */
472 	ixgbe_tx_context_t	tx_context;
473 
474 	/*
475 	 * Tx ring settings and status
476 	 */
477 	uint32_t		ring_size; /* Tx descriptor ring size */
478 	uint32_t		free_list_size;	/* Tx free list size */
479 
480 	boolean_t		reschedule;
481 	uint32_t		recycle_fail;
482 	uint32_t		stall_watchdog;
483 
484 #ifdef IXGBE_DEBUG
485 	/*
486 	 * Debug statistics
487 	 */
488 	uint32_t		stat_overload;
489 	uint32_t		stat_fail_no_tbd;
490 	uint32_t		stat_fail_no_tcb;
491 	uint32_t		stat_fail_dma_bind;
492 	uint32_t		stat_reschedule;
493 	uint32_t		stat_break_tbd_limit;
494 	uint32_t		stat_lso_header_fail;
495 #endif
496 
497 	mac_ring_handle_t	ring_handle;
498 
499 	/*
500 	 * Pointer to the ixgbe struct
501 	 */
502 	struct ixgbe		*ixgbe;
503 } ixgbe_tx_ring_t;
504 
505 /*
506  * Software Receive Ring
507  */
508 typedef struct ixgbe_rx_data {
509 	kmutex_t		recycle_lock;	/* Recycle lock, for rcb_tail */
510 
511 	/*
512 	 * Rx descriptor ring definitions
513 	 */
514 	dma_buffer_t		rbd_area;	/* DMA buffer of rx desc ring */
515 	union ixgbe_adv_rx_desc	*rbd_ring;	/* Rx desc ring */
516 	uint32_t		rbd_next;	/* Index of next rx desc */
517 
518 	/*
519 	 * Rx control block list definitions
520 	 */
521 	rx_control_block_t	*rcb_area;
522 	rx_control_block_t	**work_list;	/* Work list of rcbs */
523 	rx_control_block_t	**free_list;	/* Free list of rcbs */
524 	uint32_t		rcb_head;	/* Index of next free rcb */
525 	uint32_t		rcb_tail;	/* Index to put recycled rcb */
526 	uint32_t		rcb_free;	/* Number of free rcbs */
527 
528 	/*
529 	 * Rx sw ring settings and status
530 	 */
531 	uint32_t		ring_size;	/* Rx descriptor ring size */
532 	uint32_t		free_list_size;	/* Rx free list size */
533 
534 	uint32_t		rcb_pending;
535 	uint32_t		flag;
536 
537 	struct ixgbe_rx_ring	*rx_ring;	/* Pointer to rx ring */
538 } ixgbe_rx_data_t;
539 
540 /*
541  * Software Data Structure for Rx Ring
542  */
543 typedef struct ixgbe_rx_ring {
544 	uint32_t		index;		/* Ring index */
545 	uint32_t		intr_vector;	/* Interrupt vector index */
546 	uint32_t		vect_bit;	/* vector's bit in register */
547 
548 	ixgbe_rx_data_t		*rx_data;	/* Rx software ring */
549 
550 	kmutex_t		rx_lock;	/* Rx access lock */
551 
552 #ifdef IXGBE_DEBUG
553 	/*
554 	 * Debug statistics
555 	 */
556 	uint32_t		stat_frame_error;
557 	uint32_t		stat_cksum_error;
558 	uint32_t		stat_exceed_pkt;
559 #endif
560 
561 	mac_ring_handle_t	ring_handle;
562 	uint64_t		ring_gen_num;
563 
564 	struct ixgbe		*ixgbe;		/* Pointer to ixgbe struct */
565 } ixgbe_rx_ring_t;
566 /*
567  * Software Receive Ring Group
568  */
569 typedef struct ixgbe_rx_group {
570 	uint32_t		index;		/* Group index */
571 	mac_group_handle_t	group_handle;   /* call back group handle */
572 	struct ixgbe		*ixgbe;		/* Pointer to ixgbe struct */
573 } ixgbe_rx_group_t;
574 
575 /*
576  * structure to map interrupt cleanup to msi-x vector
577  */
578 typedef struct ixgbe_intr_vector {
579 	struct ixgbe *ixgbe;	/* point to my adapter */
580 	ulong_t rx_map[BT_BITOUL(MAX_RX_QUEUE_NUM)];	/* bitmap of rx rings */
581 	int	rxr_cnt;	/* count rx rings */
582 	ulong_t tx_map[BT_BITOUL(MAX_TX_QUEUE_NUM)];	/* bitmap of tx rings */
583 	int	txr_cnt;	/* count tx rings */
584 	ulong_t other_map[BT_BITOUL(2)];		/* bitmap of other */
585 	int	other_cnt;	/* count other interrupt */
586 } ixgbe_intr_vector_t;
587 
588 /*
589  * Software adapter state
590  */
591 typedef struct ixgbe {
592 	int 			instance;
593 	mac_handle_t		mac_hdl;
594 	dev_info_t		*dip;
595 	struct ixgbe_hw		hw;
596 	struct ixgbe_osdep	osdep;
597 
598 	adapter_info_t		*capab;	/* adapter hardware capabilities */
599 	ddi_taskq_t		*lsc_taskq;	/* link-status-change taskq */
600 	uint32_t		eims;		/* interrupt mask setting */
601 	uint32_t		eimc;		/* interrupt mask clear */
602 	uint32_t		eicr;		/* interrupt cause reg */
603 
604 	uint32_t		ixgbe_state;
605 	link_state_t		link_state;
606 	uint32_t		link_speed;
607 	uint32_t		link_duplex;
608 	uint32_t		link_down_timeout;
609 
610 	uint32_t		reset_count;
611 	uint32_t		attach_progress;
612 	uint32_t		loopback_mode;
613 	uint32_t		default_mtu;
614 	uint32_t		max_frame_size;
615 
616 	uint32_t		rcb_pending;
617 
618 	/*
619 	 * Each msi-x vector: map vector to interrupt cleanup
620 	 */
621 	ixgbe_intr_vector_t	vect_map[MAX_INTR_VECTOR];
622 
623 	/*
624 	 * Receive Rings
625 	 */
626 	ixgbe_rx_ring_t		*rx_rings;	/* Array of rx rings */
627 	uint32_t		num_rx_rings;	/* Number of rx rings in use */
628 	uint32_t		rx_ring_size;	/* Rx descriptor ring size */
629 	uint32_t		rx_buf_size;	/* Rx buffer size */
630 
631 	/*
632 	 * Receive Groups
633 	 */
634 	ixgbe_rx_group_t	*rx_groups;	/* Array of rx groups */
635 	uint32_t		num_rx_groups;	/* Number of rx groups in use */
636 
637 	/*
638 	 * Transmit Rings
639 	 */
640 	ixgbe_tx_ring_t		*tx_rings;	/* Array of tx rings */
641 	uint32_t		num_tx_rings;	/* Number of tx rings in use */
642 	uint32_t		tx_ring_size;	/* Tx descriptor ring size */
643 	uint32_t		tx_buf_size;	/* Tx buffer size */
644 
645 	boolean_t		tx_ring_init;
646 	boolean_t		tx_head_wb_enable; /* Tx head wrtie-back */
647 	boolean_t		tx_hcksum_enable; /* Tx h/w cksum offload */
648 	boolean_t 		lso_enable; 	/* Large Segment Offload */
649 	boolean_t 		mr_enable; 	/* Multiple Tx and Rx Ring */
650 	uint32_t		tx_copy_thresh;	/* Tx copy threshold */
651 	uint32_t		tx_recycle_thresh; /* Tx recycle threshold */
652 	uint32_t		tx_overload_thresh; /* Tx overload threshold */
653 	uint32_t		tx_resched_thresh; /* Tx reschedule threshold */
654 	boolean_t		rx_hcksum_enable; /* Rx h/w cksum offload */
655 	uint32_t		rx_copy_thresh; /* Rx copy threshold */
656 	uint32_t		rx_limit_per_intr; /* Rx pkts per interrupt */
657 	uint32_t		intr_throttling[MAX_INTR_VECTOR];
658 	uint32_t		intr_force;
659 	int			fm_capabilities; /* FMA capabilities */
660 
661 	int			intr_type;
662 	int			intr_cnt;
663 	int			intr_cap;
664 	size_t			intr_size;
665 	uint_t			intr_pri;
666 	ddi_intr_handle_t	*htable;
667 	uint32_t		eims_mask;
668 
669 	kmutex_t		gen_lock; /* General lock for device access */
670 	kmutex_t		watchdog_lock;
671 	kmutex_t		rx_pending_lock;
672 
673 	boolean_t		watchdog_enable;
674 	boolean_t		watchdog_start;
675 	timeout_id_t		watchdog_tid;
676 
677 	boolean_t		unicst_init;
678 	uint32_t		unicst_avail;
679 	uint32_t		unicst_total;
680 	ixgbe_ether_addr_t	unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
681 	uint32_t		mcast_count;
682 	struct ether_addr	mcast_table[MAX_NUM_MULTICAST_ADDRESSES];
683 
684 	ulong_t			sys_page_size;
685 
686 	/*
687 	 * Kstat definitions
688 	 */
689 	kstat_t			*ixgbe_ks;
690 
691 	uint32_t		param_en_10000fdx_cap:1,
692 				param_en_1000fdx_cap:1,
693 				param_en_100fdx_cap:1,
694 				param_adv_10000fdx_cap:1,
695 				param_adv_1000fdx_cap:1,
696 				param_adv_100fdx_cap:1,
697 				param_pause_cap:1,
698 				param_asym_pause_cap:1,
699 				param_rem_fault:1,
700 				param_adv_autoneg_cap:1,
701 				param_adv_pause_cap:1,
702 				param_adv_asym_pause_cap:1,
703 				param_adv_rem_fault:1,
704 				param_lp_10000fdx_cap:1,
705 				param_lp_1000fdx_cap:1,
706 				param_lp_100fdx_cap:1,
707 				param_lp_autoneg_cap:1,
708 				param_lp_pause_cap:1,
709 				param_lp_asym_pause_cap:1,
710 				param_lp_rem_fault,
711 				param_pad_to_32:12;
712 } ixgbe_t;
713 
714 typedef struct ixgbe_stat {
715 	kstat_named_t link_speed;	/* Link Speed */
716 
717 	kstat_named_t reset_count;	/* Reset Count */
718 
719 	kstat_named_t rx_frame_error;	/* Rx Error in Packet */
720 	kstat_named_t rx_cksum_error;	/* Rx Checksum Error */
721 	kstat_named_t rx_exceed_pkt;	/* Rx Exceed Max Pkt Count */
722 
723 	kstat_named_t tx_overload;	/* Tx Desc Ring Overload */
724 	kstat_named_t tx_fail_no_tcb;	/* Tx Fail Freelist Empty */
725 	kstat_named_t tx_fail_no_tbd;	/* Tx Fail Desc Ring Empty */
726 	kstat_named_t tx_fail_dma_bind;	/* Tx Fail DMA bind */
727 	kstat_named_t tx_reschedule;	/* Tx Reschedule */
728 
729 	kstat_named_t gprc;	/* Good Packets Received Count */
730 	kstat_named_t gptc;	/* Good Packets Xmitted Count */
731 	kstat_named_t gor;	/* Good Octets Received Count */
732 	kstat_named_t got;	/* Good Octets Xmitd Count */
733 	kstat_named_t prc64;	/* Packets Received - 64b */
734 	kstat_named_t prc127;	/* Packets Received - 65-127b */
735 	kstat_named_t prc255;	/* Packets Received - 127-255b */
736 	kstat_named_t prc511;	/* Packets Received - 256-511b */
737 	kstat_named_t prc1023;	/* Packets Received - 511-1023b */
738 	kstat_named_t prc1522;	/* Packets Received - 1024-1522b */
739 	kstat_named_t ptc64;	/* Packets Xmitted (64b) */
740 	kstat_named_t ptc127;	/* Packets Xmitted (64-127b) */
741 	kstat_named_t ptc255;	/* Packets Xmitted (128-255b) */
742 	kstat_named_t ptc511;	/* Packets Xmitted (255-511b) */
743 	kstat_named_t ptc1023;	/* Packets Xmitted (512-1023b) */
744 	kstat_named_t ptc1522;	/* Packets Xmitted (1024-1522b */
745 	kstat_named_t qprc[16];	/* Queue Packets Received Count */
746 	kstat_named_t qptc[16];	/* Queue Packets Transmitted Count */
747 	kstat_named_t qbrc[16];	/* Queue Bytes Received Count */
748 	kstat_named_t qbtc[16];	/* Queue Bytes Transmitted Count */
749 
750 	kstat_named_t crcerrs;	/* CRC Error Count */
751 	kstat_named_t illerrc;	/* Illegal Byte Error Count */
752 	kstat_named_t errbc;	/* Error Byte Count */
753 	kstat_named_t mspdc;	/* MAC Short Packet Discard Count */
754 	kstat_named_t mpc;	/* Missed Packets Count */
755 	kstat_named_t mlfc;	/* MAC Local Fault Count */
756 	kstat_named_t mrfc;	/* MAC Remote Fault Count */
757 	kstat_named_t rlec;	/* Receive Length Error Count */
758 	kstat_named_t lxontxc;	/* Link XON Transmitted Count */
759 	kstat_named_t lxonrxc;	/* Link XON Received Count */
760 	kstat_named_t lxofftxc;	/* Link XOFF Transmitted Count */
761 	kstat_named_t lxoffrxc;	/* Link XOFF Received Count */
762 	kstat_named_t bprc;	/* Broadcasts Pkts Received Count */
763 	kstat_named_t mprc;	/* Multicast Pkts Received Count */
764 	kstat_named_t rnbc;	/* Receive No Buffers Count */
765 	kstat_named_t ruc;	/* Receive Undersize Count */
766 	kstat_named_t rfc;	/* Receive Frag Count */
767 	kstat_named_t roc;	/* Receive Oversize Count */
768 	kstat_named_t rjc;	/* Receive Jabber Count */
769 	kstat_named_t tor;	/* Total Octets Recvd Count */
770 	kstat_named_t tot;	/* Total Octets Xmitted Count */
771 	kstat_named_t tpr;	/* Total Packets Received */
772 	kstat_named_t tpt;	/* Total Packets Xmitted */
773 	kstat_named_t mptc;	/* Multicast Packets Xmited Count */
774 	kstat_named_t bptc;	/* Broadcast Packets Xmited Count */
775 } ixgbe_stat_t;
776 
777 /*
778  * Function prototypes in ixgbe_buf.c
779  */
780 int ixgbe_alloc_dma(ixgbe_t *);
781 void ixgbe_free_dma(ixgbe_t *);
782 void ixgbe_set_fma_flags(int, int);
783 void ixgbe_free_dma_buffer(dma_buffer_t *);
784 int ixgbe_alloc_rx_ring_data(ixgbe_rx_ring_t *rx_ring);
785 void ixgbe_free_rx_ring_data(ixgbe_rx_data_t *rx_data);
786 
787 /*
788  * Function prototypes in ixgbe_main.c
789  */
790 int ixgbe_start(ixgbe_t *, boolean_t);
791 void ixgbe_stop(ixgbe_t *, boolean_t);
792 int ixgbe_driver_setup_link(ixgbe_t *, boolean_t);
793 int ixgbe_multicst_add(ixgbe_t *, const uint8_t *);
794 int ixgbe_multicst_remove(ixgbe_t *, const uint8_t *);
795 enum ioc_reply ixgbe_loopback_ioctl(ixgbe_t *, struct iocblk *, mblk_t *);
796 
797 void ixgbe_enable_watchdog_timer(ixgbe_t *);
798 void ixgbe_disable_watchdog_timer(ixgbe_t *);
799 int ixgbe_atomic_reserve(uint32_t *, uint32_t);
800 
801 int ixgbe_check_acc_handle(ddi_acc_handle_t handle);
802 int ixgbe_check_dma_handle(ddi_dma_handle_t handle);
803 void ixgbe_fm_ereport(ixgbe_t *, char *);
804 
805 void ixgbe_fill_ring(void *, mac_ring_type_t, const int, const int,
806     mac_ring_info_t *, mac_ring_handle_t);
807 void ixgbe_fill_group(void *arg, mac_ring_type_t, const int,
808     mac_group_info_t *, mac_group_handle_t);
809 int ixgbe_rx_ring_intr_enable(mac_intr_handle_t);
810 int ixgbe_rx_ring_intr_disable(mac_intr_handle_t);
811 
812 /*
813  * Function prototypes in ixgbe_gld.c
814  */
815 int ixgbe_m_start(void *);
816 void ixgbe_m_stop(void *);
817 int ixgbe_m_promisc(void *, boolean_t);
818 int ixgbe_m_multicst(void *, boolean_t, const uint8_t *);
819 int ixgbe_m_stat(void *, uint_t, uint64_t *);
820 void ixgbe_m_resources(void *);
821 void ixgbe_m_ioctl(void *, queue_t *, mblk_t *);
822 boolean_t ixgbe_m_getcapab(void *, mac_capab_t, void *);
823 int ixgbe_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *);
824 int ixgbe_m_getprop(void *, const char *, mac_prop_id_t,
825     uint_t, uint_t, void *, uint_t *);
826 int ixgbe_set_priv_prop(ixgbe_t *, const char *, uint_t, const void *);
827 int ixgbe_get_priv_prop(ixgbe_t *, const char *,
828     uint_t, uint_t, void *, uint_t *);
829 boolean_t ixgbe_param_locked(mac_prop_id_t);
830 
831 /*
832  * Function prototypes in ixgbe_rx.c
833  */
834 mblk_t *ixgbe_ring_rx(ixgbe_rx_ring_t *, int);
835 void ixgbe_rx_recycle(caddr_t arg);
836 mblk_t *ixgbe_ring_rx_poll(void *, int);
837 
838 /*
839  * Function prototypes in ixgbe_tx.c
840  */
841 mblk_t *ixgbe_ring_tx(void *, mblk_t *);
842 void ixgbe_free_tcb(tx_control_block_t *);
843 void ixgbe_put_free_list(ixgbe_tx_ring_t *, link_list_t *);
844 uint32_t ixgbe_tx_recycle_legacy(ixgbe_tx_ring_t *);
845 uint32_t ixgbe_tx_recycle_head_wb(ixgbe_tx_ring_t *);
846 
847 /*
848  * Function prototypes in ixgbe_log.c
849  */
850 void ixgbe_notice(void *, const char *, ...);
851 void ixgbe_log(void *, const char *, ...);
852 void ixgbe_error(void *, const char *, ...);
853 
854 /*
855  * Function prototypes in ixgbe_stat.c
856  */
857 int ixgbe_init_stats(ixgbe_t *);
858 
859 #ifdef __cplusplus
860 }
861 #endif
862 
863 #endif /* _IXGBE_SW_H */
864