1 /* 2 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2007, Intel Corporation 8 * All rights reserved. 9 */ 10 11 /* 12 * Copyright (c) 2006 13 * Copyright (c) 2007 14 * Damien Bergamini <damien.bergamini@free.fr> 15 * 16 * Permission to use, copy, modify, and distribute this software for any 17 * purpose with or without fee is hereby granted, provided that the above 18 * copyright notice and this permission notice appear in all copies. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 21 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 22 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 23 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 24 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 25 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 26 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 27 */ 28 29 #ifndef _IWK_VAR_H 30 #define _IWK_VAR_H 31 32 #pragma ident "%Z%%M% %I% %E% SMI" 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #define IWK_DMA_SYNC(area, flag) \ 39 (void) ddi_dma_sync((area).dma_hdl, (area).offset, \ 40 (area).alength, (flag)) 41 42 typedef struct iwk_dma_area { 43 ddi_acc_handle_t acc_hdl; /* handle for memory */ 44 caddr_t mem_va; /* CPU VA of memory */ 45 uint32_t nslots; /* number of slots */ 46 uint32_t size; /* size per slot */ 47 size_t alength; /* allocated size */ 48 /* >= product of above */ 49 ddi_dma_handle_t dma_hdl; /* DMA handle */ 50 offset_t offset; /* relative to handle */ 51 ddi_dma_cookie_t cookie; /* associated cookie */ 52 uint32_t ncookies; 53 uint32_t token; /* arbitrary identifier */ 54 } iwk_dma_t; 55 56 typedef struct iwk_tx_data { 57 iwk_dma_t dma_data; 58 iwk_tx_desc_t *desc; 59 uint32_t paddr_desc; 60 iwk_cmd_t *cmd; 61 uint32_t paddr_cmd; 62 } iwk_tx_data_t; 63 64 typedef struct iwk_tx_ring { 65 iwk_dma_t dma_desc; 66 iwk_dma_t dma_cmd; 67 iwk_tx_data_t *data; 68 int qid; 69 int count; 70 int window; 71 int queued; 72 int cur; 73 } iwk_tx_ring_t; 74 75 typedef struct iwk_rx_data { 76 iwk_dma_t dma_data; 77 } iwk_rx_data_t; 78 79 typedef struct iwk_rx_ring { 80 iwk_dma_t dma_desc; 81 uint32_t *desc; 82 iwk_rx_data_t data[RX_QUEUE_SIZE]; 83 int cur; 84 } iwk_rx_ring_t; 85 86 typedef struct iwk_softc { 87 struct ieee80211com sc_ic; 88 dev_info_t *sc_dip; 89 int (*sc_newstate)(struct ieee80211com *, 90 enum ieee80211_state, int); 91 enum ieee80211_state sc_ostate; 92 kmutex_t sc_glock; 93 kmutex_t sc_mt_lock; 94 kmutex_t sc_tx_lock; 95 kcondvar_t sc_mt_cv; 96 kcondvar_t sc_tx_cv; 97 kcondvar_t sc_cmd_cv; 98 kcondvar_t sc_fw_cv; 99 100 kthread_t *sc_mf_thread; 101 uint32_t sc_mf_thread_switch; 102 103 uint32_t sc_flags; 104 uint32_t sc_dmabuf_sz; 105 uint16_t sc_clsz; 106 uint8_t sc_rev; 107 uint8_t sc_resv; 108 uint16_t sc_assoc_id; 109 uint16_t sc_reserved0; 110 111 /* shared area */ 112 iwk_dma_t sc_dma_sh; 113 iwk_shared_t *sc_shared; 114 /* keep warm area */ 115 iwk_dma_t sc_dma_kw; 116 /* tx scheduler base address */ 117 uint32_t sc_scd_base_addr; 118 119 iwk_tx_ring_t sc_txq[IWK_NUM_QUEUES]; 120 iwk_rx_ring_t sc_rxq; 121 122 /* firmware dma */ 123 iwk_firmware_hdr_t *sc_hdr; 124 char *sc_boot; 125 iwk_dma_t sc_dma_fw_text; 126 iwk_dma_t sc_dma_fw_init_text; 127 iwk_dma_t sc_dma_fw_data; 128 iwk_dma_t sc_dma_fw_data_bak; 129 iwk_dma_t sc_dma_fw_init_data; 130 131 ddi_acc_handle_t sc_cfg_handle; 132 caddr_t sc_cfg_base; 133 ddi_acc_handle_t sc_handle; 134 caddr_t sc_base; 135 ddi_iblock_cookie_t sc_iblk; 136 137 iwk_rxon_cmd_t sc_config; 138 struct iwk_eep sc_eep_map; /* eeprom map */ 139 uint32_t sc_scd_base; 140 141 struct iwk_alive_resp sc_card_alive_run; 142 struct iwk_init_alive_resp sc_card_alive_init; 143 144 uint32_t sc_tx_timer; 145 uint8_t *sc_fw_bin; 146 147 ddi_softintr_t sc_rx_softint_id; 148 uint32_t sc_rx_softint_pending; 149 uint32_t sc_need_reschedule; 150 151 /* kstats */ 152 uint32_t sc_tx_nobuf; 153 uint32_t sc_rx_nobuf; 154 uint32_t sc_tx_err; 155 uint32_t sc_rx_err; 156 uint32_t sc_tx_retries; 157 } iwk_sc_t; 158 159 #define IWK_F_ATTACHED (1 << 0) 160 #define IWK_F_CMD_DONE (1 << 1) 161 #define IWK_F_FW_INIT (1 << 2) 162 #define IWK_F_HW_ERR_RECOVER (1 << 3) 163 #define IWK_F_RATE_AUTO_CTL (1 << 4) 164 #define IWK_F_RUNNING (1 << 5) 165 #define IWK_F_SCANNING (1 << 6) 166 167 #define IWK_SUCCESS 0 168 #define IWK_FAIL 1 169 #ifdef __cplusplus 170 } 171 #endif 172 173 #endif /* _IWK_VAR_H */ 174