1 /* 2 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2007, Intel Corporation 8 * All rights reserved. 9 */ 10 11 /* 12 * Copyright (c) 2006 13 * Copyright (c) 2007 14 * Damien Bergamini <damien.bergamini@free.fr> 15 * 16 * Permission to use, copy, modify, and distribute this software for any 17 * purpose with or without fee is hereby granted, provided that the above 18 * copyright notice and this permission notice appear in all copies. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 21 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 22 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 23 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 24 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 25 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 26 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 27 */ 28 29 #ifndef _IWK_VAR_H 30 #define _IWK_VAR_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #define IWK_DMA_SYNC(area, flag) \ 37 (void) ddi_dma_sync((area).dma_hdl, (area).offset, \ 38 (area).alength, (flag)) 39 40 typedef struct iwk_dma_area { 41 ddi_acc_handle_t acc_hdl; /* handle for memory */ 42 caddr_t mem_va; /* CPU VA of memory */ 43 uint32_t nslots; /* number of slots */ 44 uint32_t size; /* size per slot */ 45 size_t alength; /* allocated size */ 46 /* >= product of above */ 47 ddi_dma_handle_t dma_hdl; /* DMA handle */ 48 offset_t offset; /* relative to handle */ 49 ddi_dma_cookie_t cookie; /* associated cookie */ 50 uint32_t ncookies; 51 uint32_t token; /* arbitrary identifier */ 52 } iwk_dma_t; 53 54 typedef struct iwk_tx_data { 55 iwk_dma_t dma_data; 56 iwk_tx_desc_t *desc; 57 uint32_t paddr_desc; 58 iwk_cmd_t *cmd; 59 uint32_t paddr_cmd; 60 } iwk_tx_data_t; 61 62 typedef struct iwk_tx_ring { 63 iwk_dma_t dma_desc; 64 iwk_dma_t dma_cmd; 65 iwk_tx_data_t *data; 66 int qid; 67 int count; 68 int window; 69 int queued; 70 int cur; 71 } iwk_tx_ring_t; 72 73 typedef struct iwk_rx_data { 74 iwk_dma_t dma_data; 75 } iwk_rx_data_t; 76 77 typedef struct iwk_rx_ring { 78 iwk_dma_t dma_desc; 79 uint32_t *desc; 80 iwk_rx_data_t data[RX_QUEUE_SIZE]; 81 int cur; 82 } iwk_rx_ring_t; 83 84 typedef struct iwk_amrr { 85 ieee80211_node_t in; /* must be the first */ 86 int txcnt; 87 int retrycnt; 88 int success; 89 int success_threshold; 90 int recovery; 91 } iwk_amrr_t; 92 93 typedef struct iwk_ibss_node { 94 iwk_add_sta_t node; 95 int8_t used; 96 } iwk_ibss_node_t; 97 98 typedef struct iwk_ibss_beacon { 99 /* for update beacon frame dynamically */ 100 struct ieee80211_beacon_offsets iwk_boff; 101 uint32_t beacon_cmd_len; 102 iwk_tx_beacon_cmd_t beacon_cmd; 103 uint8_t syncbeacon; 104 /* beacon frame allocated from net80211 module */ 105 mblk_t *mp; 106 } iwk_ibss_beacon_t; 107 108 typedef struct iwk_ibss { 109 iwk_ibss_node_t ibss_node_tb[IWK_STATION_COUNT]; 110 uint32_t node_number; 111 kmutex_t node_tb_lock; 112 iwk_ibss_beacon_t ibss_beacon; 113 } iwk_ibss_t; 114 115 typedef struct iwk_softc { 116 struct ieee80211com sc_ic; 117 dev_info_t *sc_dip; 118 int (*sc_newstate)(struct ieee80211com *, 119 enum ieee80211_state, int); 120 void (*sc_recv_mgmt)(ieee80211com_t *, mblk_t *, 121 ieee80211_node_t *, int, int, uint32_t); 122 enum ieee80211_state sc_ostate; 123 kmutex_t sc_glock; 124 kmutex_t sc_mt_lock; 125 kmutex_t sc_tx_lock; 126 kcondvar_t sc_mt_cv; 127 kcondvar_t sc_tx_cv; 128 kcondvar_t sc_cmd_cv; 129 kcondvar_t sc_fw_cv; 130 131 kthread_t *sc_mf_thread; 132 uint32_t sc_mf_thread_switch; 133 134 uint32_t sc_flags; 135 uint32_t sc_dmabuf_sz; 136 uint16_t sc_clsz; 137 uint8_t sc_rev; 138 uint8_t sc_resv; 139 uint16_t sc_assoc_id; 140 uint16_t sc_reserved0; 141 142 /* shared area */ 143 iwk_dma_t sc_dma_sh; 144 iwk_shared_t *sc_shared; 145 /* keep warm area */ 146 iwk_dma_t sc_dma_kw; 147 /* tx scheduler base address */ 148 uint32_t sc_scd_base_addr; 149 150 iwk_tx_ring_t sc_txq[IWK_NUM_QUEUES]; 151 iwk_rx_ring_t sc_rxq; 152 153 /* firmware dma */ 154 iwk_firmware_hdr_t *sc_hdr; 155 char *sc_boot; 156 iwk_dma_t sc_dma_fw_text; 157 iwk_dma_t sc_dma_fw_init_text; 158 iwk_dma_t sc_dma_fw_data; 159 iwk_dma_t sc_dma_fw_data_bak; 160 iwk_dma_t sc_dma_fw_init_data; 161 162 ddi_acc_handle_t sc_cfg_handle; 163 caddr_t sc_cfg_base; 164 ddi_acc_handle_t sc_handle; 165 caddr_t sc_base; 166 ddi_intr_handle_t *sc_intr_htable; 167 uint_t sc_intr_pri; 168 169 iwk_rxon_cmd_t sc_config; 170 struct iwk_eep sc_eep_map; /* eeprom map */ 171 uint32_t sc_scd_base; 172 173 struct iwk_alive_resp sc_card_alive_run; 174 struct iwk_init_alive_resp sc_card_alive_init; 175 176 int32_t sc_tempera; 177 int32_t sc_last_tempera; 178 int32_t sc_user_txpower; 179 struct iwk_notif_statistics sc_statistics; 180 struct iwk_rx_gain_diff sc_rxgain_diff; 181 struct iwk_rx_sensitivity sc_rx_sens; 182 183 uint32_t sc_tx_timer; 184 uint32_t sc_scan_pending; 185 uint8_t *sc_fw_bin; 186 187 ddi_softint_handle_t sc_soft_hdl; 188 uint32_t sc_rx_softint_pending; 189 uint32_t sc_need_reschedule; 190 191 clock_t sc_clk; 192 193 /* kstats */ 194 uint32_t sc_tx_nobuf; 195 uint32_t sc_rx_nobuf; 196 uint32_t sc_tx_err; 197 uint32_t sc_rx_err; 198 uint32_t sc_tx_retries; 199 iwk_ibss_t sc_ibss; 200 } iwk_sc_t; 201 202 #define IWK_F_ATTACHED (1 << 0) 203 #define IWK_F_CMD_DONE (1 << 1) 204 #define IWK_F_FW_INIT (1 << 2) 205 #define IWK_F_HW_ERR_RECOVER (1 << 3) 206 #define IWK_F_RATE_AUTO_CTL (1 << 4) 207 #define IWK_F_RUNNING (1 << 5) 208 #define IWK_F_SCANNING (1 << 6) 209 #define IWK_F_SUSPEND (1 << 7) 210 #define IWK_F_RADIO_OFF (1 << 8) 211 #define IWK_F_STATISTICS (1 << 9) 212 #define IWK_F_QUIESCED (1 << 10) 213 #define IWK_F_LAZY_RESUME (1 << 11) 214 215 #define IWK_SUCCESS 0 216 #define IWK_FAIL EIO 217 #ifdef __cplusplus 218 } 219 #endif 220 221 #endif /* _IWK_VAR_H */ 222