1 /* 2 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2008, Intel Corporation 8 * All rights reserved. 9 */ 10 11 /* 12 * Copyright (c) 2006 13 * Copyright (c) 2007 14 * Damien Bergamini <damien.bergamini@free.fr> 15 * 16 * Permission to use, copy, modify, and distribute this software for any 17 * purpose with or without fee is hereby granted, provided that the above 18 * copyright notice and this permission notice appear in all copies. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 21 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 22 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 23 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 24 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 25 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 26 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 27 */ 28 29 #ifndef _IWH_VAR_H 30 #define _IWH_VAR_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #define IWH_DMA_SYNC(area, flag) \ 37 (void) ddi_dma_sync((area).dma_hdl, (area).offset, \ 38 (area).alength, (flag)) 39 40 typedef struct iwh_dma_area { 41 ddi_acc_handle_t acc_hdl; /* handle for memory */ 42 caddr_t mem_va; /* CPU VA of memory */ 43 uint32_t nslots; /* number of slots */ 44 uint32_t size; /* size per slot */ 45 size_t alength; /* allocated size */ 46 /* >= product of above */ 47 ddi_dma_handle_t dma_hdl; /* DMA handle */ 48 offset_t offset; /* relative to handle */ 49 ddi_dma_cookie_t cookie; /* associated cookie */ 50 uint32_t ncookies; 51 uint32_t token; /* arbitrary identifier */ 52 } iwh_dma_t; 53 54 typedef struct iwh_tx_data { 55 iwh_dma_t dma_data; /* for sending frames */ 56 iwh_tx_desc_t *desc; 57 uint32_t paddr_desc; 58 iwh_cmd_t *cmd; 59 uint32_t paddr_cmd; 60 } iwh_tx_data_t; 61 62 typedef struct iwh_tx_ring { 63 iwh_dma_t dma_desc; /* for descriptor itself */ 64 iwh_dma_t dma_cmd; /* for command to ucode */ 65 iwh_tx_data_t *data; 66 int qid; /* ID of queue */ 67 int count; 68 int window; 69 int queued; 70 int cur; 71 } iwh_tx_ring_t; 72 73 typedef struct iwh_rx_data { 74 iwh_dma_t dma_data; 75 } iwh_rx_data_t; 76 77 typedef struct iwh_rx_ring { 78 iwh_dma_t dma_desc; 79 uint32_t *desc; 80 iwh_rx_data_t data[RX_QUEUE_SIZE]; 81 int cur; 82 } iwh_rx_ring_t; 83 84 85 typedef struct iwh_amrr { 86 ieee80211_node_t in; /* must be the first */ 87 int txcnt; 88 int retrycnt; 89 int success; 90 int success_threshold; 91 int recovery; 92 } iwh_amrr_t; 93 94 struct iwh_phy_rx { 95 uint8_t flag; 96 uint8_t reserved[3]; 97 uint8_t buf[128]; 98 }; 99 100 typedef struct iwh_softc { 101 struct ieee80211com sc_ic; 102 dev_info_t *sc_dip; 103 int (*sc_newstate)(struct ieee80211com *, 104 enum ieee80211_state, int); 105 106 enum ieee80211_state sc_ostate; 107 kmutex_t sc_glock; 108 kmutex_t sc_mt_lock; 109 kmutex_t sc_tx_lock; 110 kmutex_t sc_ucode_lock; 111 kcondvar_t sc_mt_cv; 112 kcondvar_t sc_tx_cv; 113 kcondvar_t sc_cmd_cv; 114 kcondvar_t sc_fw_cv; 115 kcondvar_t sc_put_seg_cv; 116 kcondvar_t sc_ucode_cv; 117 118 kthread_t *sc_mf_thread; 119 volatile uint32_t sc_mf_thread_switch; 120 121 volatile uint32_t sc_flags; 122 uint32_t sc_dmabuf_sz; 123 uint16_t sc_clsz; 124 uint8_t sc_rev; 125 uint8_t sc_resv; 126 uint16_t sc_assoc_id; 127 uint16_t sc_reserved0; 128 129 /* shared area */ 130 iwh_dma_t sc_dma_sh; 131 iwh_shared_t *sc_shared; 132 /* keep warm area */ 133 iwh_dma_t sc_dma_kw; 134 /* tx scheduler base address */ 135 uint32_t sc_scd_base_addr; 136 137 uint32_t sc_hw_rev; 138 struct iwh_phy_rx sc_rx_phy_res; 139 140 iwh_tx_ring_t sc_txq[IWH_NUM_QUEUES]; 141 iwh_rx_ring_t sc_rxq; 142 143 /* firmware dma */ 144 iwh_firmware_hdr_t *sc_hdr; 145 char *sc_boot; 146 iwh_dma_t sc_dma_fw_text; 147 iwh_dma_t sc_dma_fw_init_text; 148 iwh_dma_t sc_dma_fw_data; 149 iwh_dma_t sc_dma_fw_data_bak; 150 iwh_dma_t sc_dma_fw_init_data; 151 152 ddi_acc_handle_t sc_cfg_handle; 153 caddr_t sc_cfg_base; 154 ddi_acc_handle_t sc_handle; 155 caddr_t sc_base; 156 ddi_intr_handle_t *sc_intr_htable; 157 uint_t sc_intr_pri; 158 159 iwh_rxon_cmd_t sc_config; 160 uint8_t sc_eep_map[IWH_SP_EEPROM_SIZE]; 161 struct iwh_eep_calibration *sc_eep_calib; 162 struct iwh_calib_results sc_calib_results; 163 uint32_t sc_scd_base; 164 165 struct iwh_alive_resp sc_card_alive_run; 166 struct iwh_init_alive_resp sc_card_alive_init; 167 168 uint32_t sc_tx_timer; 169 uint32_t sc_scan_pending; 170 uint8_t *sc_fw_bin; 171 172 ddi_softint_handle_t sc_soft_hdl; 173 174 uint32_t sc_rx_softint_pending; 175 uint32_t sc_need_reschedule; 176 177 clock_t sc_clk; 178 179 /* kstats */ 180 uint32_t sc_tx_nobuf; 181 uint32_t sc_rx_nobuf; 182 uint32_t sc_tx_err; 183 uint32_t sc_rx_err; 184 uint32_t sc_tx_retries; 185 } iwh_sc_t; 186 187 #define IWH_F_ATTACHED (1 << 0) 188 #define IWH_F_CMD_DONE (1 << 1) 189 #define IWH_F_FW_INIT (1 << 2) 190 #define IWH_F_HW_ERR_RECOVER (1 << 3) 191 #define IWH_F_RATE_AUTO_CTL (1 << 4) 192 #define IWH_F_RUNNING (1 << 5) 193 #define IWH_F_SCANNING (1 << 6) 194 #define IWH_F_SUSPEND (1 << 7) 195 #define IWH_F_RADIO_OFF (1 << 8) 196 #define IWH_F_STATISTICS (1 << 9) 197 #define IWH_F_READY (1 << 10) 198 #define IWH_F_PUT_SEG (1 << 11) 199 #define IWH_F_QUIESCED (1 << 12) 200 201 #define IWH_SUCCESS 0 202 #define IWH_FAIL EIO 203 #ifdef __cplusplus 204 } 205 #endif 206 207 #endif /* _IWH_VAR_H */ 208