1 /* 2 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright(c) 2004 8 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice unmodified, this list of conditions, and the following 15 * disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #ifndef _SYS_IPW2100_IMPL_H 34 #define _SYS_IPW2100_IMPL_H 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /* 41 * Intel Wireless PRO/2100 mini-PCI adapter driver 42 * ipw2100_impl.h includes: 43 * . implementation of ipw2100 44 * . hardware operation and interface define for ipw2100 45 * . firmware operation and interface define for ipw2100 46 */ 47 #include <sys/ddi.h> 48 #include <sys/sunddi.h> 49 #include <sys/mac.h> 50 #include <sys/net80211.h> 51 52 /* 53 * Implementation of ipw2100 54 */ 55 #define IPW2100_NODENAME "ipw" 56 57 #define IPW2100_PCI_CFG_RNUM (0) /* pci config space */ 58 #define IPW2100_PCI_CSR_RNUM (1) /* device CSR space */ 59 60 #define IPW2100_NUM_TXBD (128) 61 #define IPW2100_TXBD_SIZE (IPW2100_NUM_TXBD * sizeof (struct ipw2100_bd)) 62 #define IPW2100_NUM_TXBUF (IPW2100_NUM_TXBD/2) /* ipw2100_txb number */ 63 #define IPW2100_TXBUF_SIZE (sizeof (struct ipw2100_txb)) 64 65 #define IPW2100_NUM_RXBD (128) 66 #define IPW2100_STATUS_SIZE (IPW2100_NUM_RXBD * sizeof (struct ipw2100_status)) 67 #define IPW2100_RXBD_SIZE (IPW2100_NUM_RXBD * sizeof (struct ipw2100_bd)) 68 #define IPW2100_NUM_RXBUF (IPW2100_NUM_RXBD) 69 #define IPW2100_RXBUF_SIZE (sizeof (struct ipw2100_rxb)) 70 71 #define IPW2100_CMD_SIZE (sizeof (struct ipw2100_cmd)) 72 73 struct dma_region { 74 ddi_dma_handle_t dr_hnd; 75 ddi_acc_handle_t dr_acc; 76 ddi_dma_cookie_t dr_cookie; 77 uint_t dr_ccnt; 78 uint32_t dr_pbase; 79 caddr_t dr_base; 80 size_t dr_size; 81 const char *dr_name; 82 }; 83 84 struct ipw2100_firmware { 85 uint8_t *bin_base; /* image */ 86 size_t bin_size; 87 uint8_t *fw_base; /* firmware code */ 88 size_t fw_size; 89 uint8_t *uc_base; /* u-controller code */ 90 size_t uc_size; 91 }; 92 93 /* 94 * per-instance soft-state structure 95 */ 96 struct ipw2100_softc { 97 struct ieee80211com sc_ic; 98 dev_info_t *sc_dip; 99 int (*sc_newstate)(struct ieee80211com *, 100 enum ieee80211_state, int); 101 int sc_authmode; 102 /* CSR */ 103 ddi_acc_handle_t sc_ioh; 104 caddr_t sc_regs; 105 /* interrupt */ 106 ddi_iblock_cookie_t sc_iblk; 107 /* soft interrupt */ 108 ddi_softintr_t sc_link_softint; 109 /* link state */ 110 int32_t sc_linkstate; 111 /* mutex to protect interrupt handler */ 112 kmutex_t sc_ilock; 113 kcondvar_t sc_fw_cond; 114 /* flags */ 115 uint_t sc_flags; 116 #define IPW2100_FLAG_FW_CACHED (1 << 0) 117 #define IPW2100_FLAG_FW_INITED (1 << 1) 118 #define IPW2100_FLAG_RUNNING (1 << 2) 119 #define IPW2100_FLAG_LINK_CHANGE (1 << 3) 120 #define IPW2100_FLAG_TX_SCHED (1 << 4) 121 #define IPW2100_FLAG_CMD_WAIT (1 << 5) 122 #define IPW2100_FLAG_SCAN_COMPLETE (1 << 6) 123 #define IPW2100_FLAG_HW_ERR_RECOVER (1 << 7) 124 #define IPW2100_FLAG_QUIESCED (1 << 8) 125 #define IPW2100_FLAG_HAS_RADIO_SWITCH (1 << 16) 126 /* command */ 127 struct ipw2100_cmd *sc_cmd; 128 int sc_done; /* command is done */ 129 kcondvar_t sc_cmd_cond; 130 /* reschedule lock */ 131 kmutex_t sc_resched_lock; 132 /* tx ring, bd->hdr&buf */ 133 kmutex_t sc_tx_lock; 134 kcondvar_t sc_tx_cond; 135 uint32_t sc_tx_cur; 136 uint32_t sc_tx_free; 137 struct ipw2100_bd *sc_txbd; 138 struct ipw2100_txb *sc_txbufs[IPW2100_NUM_TXBUF]; 139 /* rx ring, status, bd->buf */ 140 uint32_t sc_rx_cur; 141 uint32_t sc_rx_free; 142 struct ipw2100_status *sc_status; 143 struct ipw2100_bd *sc_rxbd; 144 struct ipw2100_rxb *sc_rxbufs[IPW2100_NUM_RXBUF]; 145 /* DMA resources */ 146 struct dma_region sc_dma_txbd; /* tx buffer descriptor */ 147 struct dma_region sc_dma_txbufs[IPW2100_NUM_TXBUF]; 148 struct dma_region sc_dma_rxbd; /* rx buffer descriptor */ 149 struct dma_region sc_dma_rxbufs[IPW2100_NUM_RXBUF]; 150 struct dma_region sc_dma_status; 151 struct dma_region sc_dma_cmd; /* command */ 152 /* hw configuration values */ 153 uint8_t sc_macaddr[IEEE80211_ADDR_LEN]; 154 uint16_t sc_chmask; 155 /* MAC address string */ 156 char sc_macstr[32]; 157 /* tables */ 158 uint32_t sc_table1_base; 159 uint32_t sc_table2_base; 160 /* firmware */ 161 struct ipw2100_firmware sc_fw; 162 /* mfthread related */ 163 kmutex_t sc_mflock; 164 kcondvar_t sc_mfthread_cv; 165 kcondvar_t sc_scan_cv; /* used for active scan */ 166 kthread_t *sc_mf_thread; 167 uint32_t sc_mfthread_switch; /* 0/1 indicate off/on */ 168 int if_flags; 169 }; 170 171 /* 172 * RING_BACKWARD - move 'x' backward 's' steps in a 'b'-sized ring 173 * RING_FORWARD - move 'x' forward 's' steps in a 'b'-sized ring 174 * 175 * note that there must be 0 <= 'x' < 'b' && 0 <= 's' < 'b' 176 */ 177 #define RING_FLEN(x, y, b) ((((x) > (y)) ? ((b)+(y)-(x)) : ((y)-(x)))) 178 #define RING_FORWARD(x, s, b) (((x)+(s))%(b)) 179 #define RING_BACKWARD(x, s, b) RING_FORWARD((x), (b)-(s), (b)) 180 181 /* 182 * field_offset 183 */ 184 #define OFFSETOF(s, m) ((size_t)(&(((s *)0)->m))) 185 186 extern int ipw2100_init(struct ipw2100_softc *sc); 187 extern int ipw2100_disable(struct ipw2100_softc *sc); 188 189 /* 190 * Below structure and functions will be used for statistic 191 */ 192 struct statistic { 193 int index; 194 const char *desc; 195 int unit; 196 #define INT 1 197 #define HEX 2 198 #define MASK HEX 199 #define PERCENTAGE 3 200 #define BOOL 4 201 }; 202 extern void ipw2100_get_statistics(struct ipw2100_softc *sc); 203 204 /* 205 * Hardware related definations and interfaces. 206 */ 207 #define IPW2100_CSR_INTR (0x0008) 208 #define IPW2100_CSR_INTR_MASK (0x000c) 209 #define IPW2100_CSR_INDIRECT_ADDR (0x0010) 210 #define IPW2100_CSR_INDIRECT_DATA (0x0014) 211 #define IPW2100_CSR_AUTOINC_ADDR (0x0018) 212 #define IPW2100_CSR_AUTOINC_DATA (0x001c) 213 #define IPW2100_CSR_RST (0x0020) 214 #define IPW2100_CSR_CTL (0x0024) 215 #define IPW2100_CSR_IO (0x0030) 216 #define IPW2100_CSR_DEBUG_AREA (0x0090) 217 218 #define IPW2100_CSR_TX_BD_BASE (0x0200) 219 #define IPW2100_CSR_TX_BD_SIZE (0x0204) 220 #define IPW2100_CSR_RX_BD_BASE (0x0240) 221 #define IPW2100_CSR_RX_STATUS_BASE (0x0244) 222 #define IPW2100_CSR_RX_BD_SIZE (0x0248) 223 #define IPW2100_CSR_TABLE1_BASE (0x0380) 224 #define IPW2100_CSR_TABLE2_BASE (0x0384) 225 /* 226 * tx-rd-index the entry to be processed by HW, i.e. empty tx buffer 227 * tx-wr-index the entry just being filled by SW with new data to transmit 228 */ 229 #define IPW2100_CSR_TX_READ_INDEX (0x0280) 230 #define IPW2100_CSR_TX_WRITE_INDEX (0x0f80) 231 /* 232 * rx-rd-index the entry just being processed by HW, i.e. new received data 233 * rx-wr-index the entry just being set by SW to empty buffer to receive 234 */ 235 #define IPW2100_CSR_RX_READ_INDEX (0x02a0) 236 #define IPW2100_CSR_RX_WRITE_INDEX (0x0fa0) 237 238 /* 239 * CSR flags: IPW2100_CSR_INTR 240 * The interrupt register is used to indicate the h/w status 241 */ 242 #define IPW2100_INTR_TX_TRANSFER (0x00000001) 243 #define IPW2100_INTR_RX_TRANSFER (0x00000002) 244 #define IPW2100_INTR_STATUS_CHANGE (0x00000010) 245 #define IPW2100_INTR_COMMAND_DONE (0x00010000) 246 #define IPW2100_INTR_FW_INIT_DONE (0x01000000) 247 #define IPW2100_INTR_FATAL_ERROR (0x40000000) 248 #define IPW2100_INTR_PARITY_ERROR (0x80000000) 249 #define IPW2100_INTR_MASK_ALL (IPW2100_INTR_TX_TRANSFER | \ 250 IPW2100_INTR_RX_TRANSFER | \ 251 IPW2100_INTR_STATUS_CHANGE | \ 252 IPW2100_INTR_COMMAND_DONE | \ 253 IPW2100_INTR_FW_INIT_DONE | \ 254 IPW2100_INTR_FATAL_ERROR | \ 255 IPW2100_INTR_PARITY_ERROR) 256 #define IPW2100_INTR_MASK_ERR (IPW2100_INTR_FATAL_ERROR | \ 257 IPW2100_INTR_PARITY_ERROR) 258 259 /* 260 * CSR flags: IPW2100_CSR_RST 261 * The reset register is used to reset hardware 262 */ 263 #define IPW2100_RST_PRINCETON_RESET (0x00000001) 264 #define IPW2100_RST_SW_RESET (0x00000080) 265 #define IPW2100_RST_MASTER_DISABLED (0x00000100) 266 #define IPW2100_RST_STOP_MASTER (0x00000200) 267 268 /* 269 * CSR flags: IPW2100_CSR_CTL 270 */ 271 #define IPW2100_CTL_CLOCK_READY (0x00000001) 272 #define IPW2100_CTL_ALLOW_STANDBY (0x00000002) 273 #define IPW2100_CTL_INIT (0x00000004) 274 275 /* 276 * CSR flags: IPW2100_CSR_IO 277 */ 278 #define IPW2100_IO_GPIO1_ENABLE (0x00000008) 279 #define IPW2100_IO_GPIO1_MASK (0x0000000c) 280 #define IPW2100_IO_GPIO3_MASK (0x000000c0) 281 #define IPW2100_IO_LED_OFF (0x00002000) 282 #define IPW2100_IO_RADIO_DISABLED (0x00010000) 283 284 /* 285 * States code 286 */ 287 #define IPW2100_STATE_ASSOCIATED (0x0004) 288 #define IPW2100_STATE_ASSOCIATION_LOST (0x0008) 289 #define IPW2100_STATE_SCAN_COMPLETE (0x0020) 290 #define IPW2100_STATE_RADIO_DISABLED (0x0100) 291 #define IPW2100_STATE_DISABLED (0x0200) 292 #define IPW2100_STATE_SCANNING (0x0800) 293 294 /* 295 * table1 offsets 296 */ 297 #define IPW2100_INFO_LOCK (480) 298 #define IPW2100_INFO_APS_CNT (604) 299 #define IPW2100_INFO_APS_BASE (608) 300 #define IPW2100_INFO_CARD_DISABLED (628) 301 #define IPW2100_INFO_CURRENT_CHANNEL (756) 302 #define IPW2100_INFO_CURRENT_TX_RATE (768) 303 304 /* 305 * table2 offsets 306 */ 307 #define IPW2100_INFO_CURRENT_SSID (48) 308 #define IPW2100_INFO_CURRENT_BSSID (112) 309 310 /* 311 * supported rates 312 */ 313 #define IPW2100_RATE_DS1 (1) 314 #define IPW2100_RATE_DS2 (2) 315 #define IPW2100_RATE_DS5 (4) 316 #define IPW2100_RATE_DS11 (8) 317 318 /* hw structures, packed */ 319 #pragma pack(1) 320 /* 321 * firmware binary image header 322 */ 323 struct ipw2100_firmware_hdr { 324 uint32_t version; 325 uint32_t fw_size; 326 uint32_t uc_size; 327 }; 328 329 /* 330 * buffer descriptor 331 */ 332 struct ipw2100_bd { 333 uint32_t phyaddr; 334 uint32_t len; 335 uint8_t flags; 336 /* flags */ 337 #define IPW2100_BD_FLAG_TX_LAST_FRAGMENT (0x08) 338 #define IPW2100_BD_FLAG_TX_NOT_LAST_FRAGMENT (0x01) 339 /* data content */ 340 #define IPW2100_BD_FLAG_TX_FRAME_802_3 (0x00) 341 #define IPW2100_BD_FLAG_TX_FRAME_COMMAND (0x02) 342 #define IPW2100_BD_FLAG_TX_FRAME_802_11 (0x04) 343 /* number of fragments, only 1st BD is needed */ 344 uint8_t nfrag; 345 uint8_t reserved[6]; 346 }; 347 348 /* 349 * status descriptor 350 */ 351 struct ipw2100_status { 352 uint32_t len; 353 uint16_t code; 354 #define IPW2100_STATUS_CODE_COMMAND (0) 355 #define IPW2100_STATUS_CODE_NEWSTATE (1) 356 #define IPW2100_STATUS_CODE_DATA_802_11 (2) 357 #define IPW2100_STATUS_CODE_DATA_802_3 (3) 358 #define IPW2100_STATUS_CODE_NOTIFICATION (4) 359 uint8_t flags; 360 #define IPW2100_STATUS_FLAG_DECRYPTED (0x01) 361 #define IPW2100_STATUS_FLAG_WEP_ENCRYPTED (0x02) 362 #define IPW2100_STATUS_FLAG_CRC_ERROR (0x04) 363 /* received signal strength indicator */ 364 uint8_t rssi; 365 }; 366 367 /* 368 * data header 369 */ 370 struct ipw2100_hdr { 371 uint32_t type; 372 uint32_t subtype; 373 uint8_t encrypted; 374 uint8_t encrypt; 375 uint8_t keyidx; 376 uint8_t keysz; 377 uint8_t key[IEEE80211_KEYBUF_SIZE]; 378 uint8_t reserved[10]; 379 uint8_t saddr[IEEE80211_ADDR_LEN]; 380 uint8_t daddr[IEEE80211_ADDR_LEN]; 381 uint16_t fragsz; 382 }; 383 384 /* 385 * command 386 */ 387 struct ipw2100_cmd { 388 uint32_t type; 389 #define IPW2100_CMD_ENABLE (2) 390 #define IPW2100_CMD_SET_CONFIGURATION (6) 391 #define IPW2100_CMD_SET_ESSID (8) 392 #define IPW2100_CMD_SET_MANDATORY_BSSID (9) 393 #define IPW2100_CMD_SET_AUTH_TYPE (10) 394 #define IPW2100_CMD_SET_MAC_ADDRESS (11) 395 #define IPW2100_CMD_SET_MODE (12) 396 #define IPW2100_CMD_SET_I18N_MODE (13) 397 #define IPW2100_CMD_SET_CHANNEL (14) 398 #define IPW2100_CMD_SET_RTS_THRESHOLD (15) 399 #define IPW2100_CMD_SET_FRAG_THRESHOLD (16) 400 #define IPW2100_CMD_SET_POWER_MODE (17) 401 #define IPW2100_CMD_SET_TX_RATES (18) 402 #define IPW2100_CMD_SET_BASIC_TX_RATES (19) 403 #define IPW2100_CMD_SET_WEP_KEY (20) 404 #define IPW2100_CMD_SET_WEP_KEY_INDEX (25) 405 #define IPW2100_CMD_SET_WEP_FLAGS (26) 406 #define IPW2100_CMD_ADD_MULTICAST (27) 407 #define IPW2100_CMD_CLR_MULTICAST (28) 408 #define IPW2100_CMD_SET_BEACON_INTERVAL (29) 409 #define IPW2100_CMD_CLR_STATISTICS (31) 410 #define IPW2100_CMD_SEND (33) 411 #define IPW2100_CMD_SET_TX_POWER_INDEX (36) 412 #define IPW2100_CMD_BROADCAST_SCAN (43) 413 #define IPW2100_CMD_DISABLE (44) 414 #define IPW2100_CMD_SET_DESIRED_BSSID (45) 415 #define IPW2100_CMD_SET_SCAN_OPTIONS (46) 416 #define IPW2100_CMD_PREPARE_POWER_DOWN (58) 417 #define IPW2100_CMD_DISABLE_PHY (61) 418 #define IPW2100_CMD_SET_SECURITY_INFORMATION (67) 419 #define IPW2100_CMD_SET_WPA_IE (69) 420 uint32_t subtype; 421 uint32_t seq; 422 uint32_t len; 423 uint8_t data[400]; 424 uint32_t status; 425 uint8_t reserved[68]; 426 }; 427 428 /* 429 * IPW2100_CMD_SET_POWER_MODE 430 */ 431 #define IPW2100_POWER_MODE_CAM (0) 432 #define IPW2100_POWER_AUTOMATIC (6) 433 434 /* 435 * IPW2100_CMD_SET_MODE 436 */ 437 #define IPW2100_MODE_BSS (0) 438 #define IPW2100_MODE_IBSS (1) 439 #define IPW2100_MODE_MONITOR (2) 440 441 /* 442 * structure for IPW2100_CMD_SET_WEP_KEY 443 */ 444 struct ipw2100_wep_key { 445 uint8_t idx; 446 uint8_t len; 447 uint8_t key[13]; 448 }; 449 450 /* 451 * structure for IPW2100_CMD_SET_SECURITY_INFORMATION 452 */ 453 struct ipw2100_security { 454 uint32_t ciphers; 455 #define IPW2100_CIPHER_NONE (0x00000001) 456 #define IPW2100_CIPHER_WEP40 (0x00000002) 457 #define IPW2100_CIPHER_WEP104 (0x00000020) 458 uint16_t version; 459 uint8_t authmode; 460 #define IPW2100_AUTH_OPEN (0) 461 #define IPW2100_AUTH_SHARED (1) 462 uint8_t replay_counters_number; 463 uint8_t unicast_using_group; 464 }; 465 466 /* 467 * structure for IPW2100_CMD_SET_SCAN_OPTIONS 468 */ 469 struct ipw2100_scan_options { 470 uint32_t flags; 471 #define IPW2100_SCAN_DO_NOT_ASSOCIATE (0x00000001) 472 #define IPW2100_SCAN_PASSIVE (0x00000008) 473 uint32_t channels; 474 }; 475 476 /* 477 * structure for IPW2100_CMD_SET_CONFIGURATION 478 */ 479 struct ipw2100_configuration { 480 uint32_t flags; 481 #define IPW2100_CFG_PROMISCUOUS (0x00000004) 482 #define IPW2100_CFG_PREAMBLE_AUTO (0x00000010) 483 #define IPW2100_CFG_IBSS_AUTO_START (0x00000020) 484 #define IPW2100_CFG_802_1x_ENABLE (0x00004000) 485 #define IPW2100_CFG_BSS_MASK (0x00008000) 486 #define IPW2100_CFG_IBSS_MASK (0x00010000) 487 uint32_t bss_chan; 488 uint32_t ibss_chan; 489 }; 490 491 /* 492 * element in AP table 493 */ 494 struct ipw2100_node { 495 uint32_t reserved_1[2]; 496 uint8_t bssid[IEEE80211_ADDR_LEN]; 497 uint8_t chan; 498 uint8_t rates; 499 uint16_t reserved_2; 500 uint16_t capinfo; 501 uint16_t reserved_3; 502 uint16_t intval; 503 uint8_t reserved_4[28]; 504 uint8_t essid[IEEE80211_NWID_LEN]; 505 uint16_t reserved_5; 506 uint8_t esslen; 507 uint8_t reserved_6[7]; 508 uint8_t rssi; 509 }; 510 #pragma pack() 511 512 /* 513 * transmit buffer block 514 */ 515 struct ipw2100_txb { 516 struct ipw2100_hdr txb_hdr; /* header */ 517 uint8_t txb_dat[IEEE80211_MAX_LEN]; /* payload */ 518 }; 519 520 /* 521 * maximum frame header lenght: 4 MAC addresses + 1 fc + 1 id + 1 seqctl 522 */ 523 #define IEEE80211_MAX_FHLEN (4*6+2+2+2) 524 525 /* 526 * receive buffer block 527 */ 528 struct ipw2100_rxb { 529 uint8_t rxb_dat[IEEE80211_MAX_FHLEN /* frame */ 530 + IEEE80211_MAX_LEN /* payload */ 531 + IEEE80211_CRC_LEN]; /* FCS */ 532 }; 533 534 /* 535 * ROM entries 536 */ 537 #define IPW2100_ROM_RADIO (0x11) 538 #define IPW2100_ROM_MAC (0x21) 539 #define IPW2100_ROM_CHANNEL_LIST (0x37) 540 541 /* 542 * EEPROM controls 543 */ 544 #define IPW2100_IMEM_EEPROM_CTL (0x00300040) 545 #define IPW2100_EEPROM_DELAY (1) 546 547 /* 548 * CSR access routines 549 */ 550 extern uint8_t ipw2100_csr_get8(struct ipw2100_softc *sc, uint32_t off); 551 extern uint16_t ipw2100_csr_get16(struct ipw2100_softc *sc, uint32_t off); 552 extern uint32_t ipw2100_csr_get32(struct ipw2100_softc *sc, uint32_t off); 553 extern void ipw2100_csr_rep_get16(struct ipw2100_softc *sc, uint32_t off, 554 uint16_t *buf, size_t cnt); 555 extern void ipw2100_csr_put8(struct ipw2100_softc *sc, uint32_t off, 556 uint8_t val); 557 extern void ipw2100_csr_put16(struct ipw2100_softc *sc, 558 uint32_t off, uint16_t val); 559 extern void ipw2100_csr_put32(struct ipw2100_softc *sc, 560 uint32_t off, uint32_t val); 561 extern void ipw2100_csr_rep_put8(struct ipw2100_softc *sc, 562 uint32_t off, uint8_t *buf, size_t cnt); 563 extern uint8_t ipw2100_imem_get8(struct ipw2100_softc *sc, int32_t addr); 564 extern uint16_t ipw2100_imem_get16(struct ipw2100_softc *sc, 565 uint32_t addr); 566 extern uint32_t ipw2100_imem_get32(struct ipw2100_softc *sc, 567 uint32_t addr); 568 extern void ipw2100_imem_rep_get16(struct ipw2100_softc *sc, 569 uint32_t addr, uint16_t *buf, size_t cnt); 570 extern void ipw2100_imem_put8(struct ipw2100_softc *sc, 571 uint32_t addr, uint8_t val); 572 extern void ipw2100_imem_put16(struct ipw2100_softc *sc, 573 uint32_t addr, uint16_t val); 574 extern void ipw2100_imem_put32(struct ipw2100_softc *sc, 575 uint32_t addr, uint32_t val); 576 extern void ipw2100_imem_rep_put8(struct ipw2100_softc *sc, 577 uint32_t addr, uint8_t *buf, size_t cnt); 578 extern void ipw2100_imem_getbuf(struct ipw2100_softc *sc, 579 uint32_t addr, uint8_t *buf, size_t cnt); 580 extern void ipw2100_imem_putbuf(struct ipw2100_softc *sc, 581 uint32_t addr, uint8_t *buf, size_t cnt); 582 extern void ipw2100_rom_control(struct ipw2100_softc *sc, uint32_t val); 583 extern uint8_t ipw2100_table1_get8(struct ipw2100_softc *sc, uint32_t off); 584 extern uint32_t ipw2100_table1_get32(struct ipw2100_softc *sc, 585 uint32_t off); 586 extern void ipw2100_table1_put32(struct ipw2100_softc *sc, 587 uint32_t off, uint32_t val); 588 extern int ipw2100_table2_getbuf(struct ipw2100_softc *sc, 589 uint32_t off, uint8_t *buf, uint32_t *len); 590 591 extern uint16_t ipw2100_rom_get16(struct ipw2100_softc *sc, uint8_t addr); 592 593 /* 594 * Firmware related definations and interfaces. 595 */ 596 extern int ipw2100_cache_firmware(struct ipw2100_softc *sc); 597 extern int ipw2100_free_firmware(struct ipw2100_softc *sc); 598 extern int ipw2100_load_uc(struct ipw2100_softc *sc); 599 extern int ipw2100_load_fw(struct ipw2100_softc *sc); 600 601 #ifdef __cplusplus 602 } 603 #endif 604 605 #endif /* _SYS_IPW2100_IMPL_H */ 606