1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #ifndef _IGB_SW_H 30 #define _IGB_SW_H 31 32 #pragma ident "%Z%%M% %I% %E% SMI" 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #include <sys/types.h> 39 #include <sys/conf.h> 40 #include <sys/debug.h> 41 #include <sys/stropts.h> 42 #include <sys/stream.h> 43 #include <sys/strsun.h> 44 #include <sys/strlog.h> 45 #include <sys/kmem.h> 46 #include <sys/stat.h> 47 #include <sys/kstat.h> 48 #include <sys/modctl.h> 49 #include <sys/errno.h> 50 #include <sys/dlpi.h> 51 #include <sys/mac.h> 52 #include <sys/mac_ether.h> 53 #include <sys/vlan.h> 54 #include <sys/ddi.h> 55 #include <sys/sunddi.h> 56 #include <sys/pci.h> 57 #include <sys/pcie.h> 58 #include <sys/sdt.h> 59 #include <sys/ethernet.h> 60 #include <sys/pattr.h> 61 #include <sys/strsubr.h> 62 #include <sys/netlb.h> 63 #include <sys/random.h> 64 #include <inet/common.h> 65 #include <inet/ip.h> 66 #include <inet/mi.h> 67 #include <inet/nd.h> 68 #include <sys/ddifm.h> 69 #include <sys/fm/protocol.h> 70 #include <sys/fm/util.h> 71 #include <sys/fm/io/ddi.h> 72 #include "igb_api.h" 73 #include "igb_82575.h" 74 75 76 #define MODULE_NAME "igb" /* module name */ 77 78 #define IGB_SUCCESS DDI_SUCCESS 79 #define IGB_FAILURE DDI_FAILURE 80 81 #define IGB_UNKNOWN 0x00 82 #define IGB_INITIALIZED 0x01 83 #define IGB_STARTED 0x02 84 #define IGB_SUSPENDED 0x04 85 86 #define IGB_INTR_NONE 0 87 #define IGB_INTR_MSIX 1 88 #define IGB_INTR_MSI 2 89 #define IGB_INTR_LEGACY 3 90 91 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 92 #define MAX_NUM_MULTICAST_ADDRESSES 256 93 #define MAX_NUM_EITR 10 94 #define MAX_COOKIE 16 95 #define MIN_NUM_TX_DESC 2 96 97 /* 98 * Maximum values for user configurable parameters 99 */ 100 #define MAX_TX_QUEUE_NUM 4 101 #define MAX_RX_QUEUE_NUM 4 102 #define MAX_TX_RING_SIZE 4096 103 #define MAX_RX_RING_SIZE 4096 104 105 #define MAX_MTU 9000 106 #define MAX_RX_LIMIT_PER_INTR 4096 107 #define MAX_RX_INTR_DELAY 65535 108 #define MAX_RX_INTR_ABS_DELAY 65535 109 #define MAX_TX_INTR_DELAY 65535 110 #define MAX_TX_INTR_ABS_DELAY 65535 111 #define MAX_INTR_THROTTLING 65535 112 113 #define MAX_RX_COPY_THRESHOLD 9216 114 #define MAX_TX_COPY_THRESHOLD 9216 115 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 116 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 117 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 118 119 /* 120 * Minimum values for user configurable parameters 121 */ 122 #define MIN_TX_QUEUE_NUM 1 123 #define MIN_RX_QUEUE_NUM 1 124 #define MIN_TX_RING_SIZE 64 125 #define MIN_RX_RING_SIZE 64 126 127 #define MIN_MTU ETHERMIN 128 #define MIN_RX_LIMIT_PER_INTR 16 129 #define MIN_RX_INTR_DELAY 0 130 #define MIN_RX_INTR_ABS_DELAY 0 131 #define MIN_TX_INTR_DELAY 0 132 #define MIN_TX_INTR_ABS_DELAY 0 133 #define MIN_INTR_THROTTLING 0 134 #define MIN_RX_COPY_THRESHOLD 0 135 #define MIN_TX_COPY_THRESHOLD 0 136 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 137 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 138 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 139 140 /* 141 * Default values for user configurable parameters 142 */ 143 #define DEFAULT_TX_QUEUE_NUM 1 144 #define DEFAULT_RX_QUEUE_NUM 1 145 #define DEFAULT_TX_RING_SIZE 512 146 #define DEFAULT_RX_RING_SIZE 512 147 148 #define DEFAULT_MTU ETHERMTU 149 #define DEFAULT_RX_LIMIT_PER_INTR 256 150 #define DEFAULT_RX_INTR_DELAY 0 151 #define DEFAULT_RX_INTR_ABS_DELAY 0 152 #define DEFAULT_TX_INTR_DELAY 300 153 #define DEFAULT_TX_INTR_ABS_DELAY 0 154 #define DEFAULT_INTR_THROTTLING 200 /* In unit of 256 nsec */ 155 #define DEFAULT_RX_COPY_THRESHOLD 128 156 #define DEFAULT_TX_COPY_THRESHOLD 512 157 #define DEFAULT_TX_RECYCLE_THRESHOLD MAX_COOKIE 158 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 159 #define DEFAULT_TX_RESCHED_THRESHOLD 128 160 161 #define TX_DRAIN_TIME 200 162 #define RX_DRAIN_TIME 200 163 164 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 165 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 166 167 /* 168 * Defined for IP header alignment. 169 */ 170 #define IPHDR_ALIGN_ROOM 2 171 172 /* 173 * Bit flags for attach_progress 174 */ 175 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 176 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 177 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 178 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 179 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 180 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 181 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 182 #define ATTACH_PROGRESS_INIT 0x0080 /* Device initialized */ 183 #define ATTACH_PROGRESS_INIT_RINGS 0x0100 /* Rings initialized */ 184 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 185 #define ATTACH_PROGRESS_NDD 0x0400 /* NDD initialized */ 186 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 187 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 188 #define ATTACH_PROGRESS_FMINIT 0x2000 /* FMA initialized */ 189 190 191 #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap" 192 #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap" 193 #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap" 194 #define PROP_ADV_100FDX_CAP "adv_100fdx_cap" 195 #define PROP_ADV_100HDX_CAP "adv_100hdx_cap" 196 #define PROP_ADV_10FDX_CAP "adv_10fdx_cap" 197 #define PROP_ADV_10HDX_CAP "adv_10hdx_cap" 198 #define PROP_DEFAULT_MTU "default_mtu" 199 #define PROP_FLOW_CONTROL "flow_control" 200 #define PROP_TX_QUEUE_NUM "tx_queue_number" 201 #define PROP_TX_RING_SIZE "tx_ring_size" 202 #define PROP_RX_QUEUE_NUM "rx_queue_number" 203 #define PROP_RX_RING_SIZE "rx_ring_size" 204 205 #define PROP_INTR_FORCE "intr_force" 206 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 207 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 208 #define PROP_LSO_ENABLE "lso_enable" 209 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 210 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 211 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 212 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 213 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 214 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 215 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 216 #define PROP_INTR_THROTTLING "intr_throttling" 217 218 #define IGB_LB_NONE 0 219 #define IGB_LB_EXTERNAL 1 220 #define IGB_LB_INTERNAL_MAC 2 221 #define IGB_LB_INTERNAL_PHY 3 222 #define IGB_LB_INTERNAL_SERDES 4 223 224 /* 225 * Shorthand for the NDD parameters 226 */ 227 #define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].val 228 #define param_pause_cap nd_params[PARAM_PAUSE_CAP].val 229 #define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].val 230 #define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].val 231 #define param_1000hdx_cap nd_params[PARAM_1000HDX_CAP].val 232 #define param_100t4_cap nd_params[PARAM_100T4_CAP].val 233 #define param_100fdx_cap nd_params[PARAM_100FDX_CAP].val 234 #define param_100hdx_cap nd_params[PARAM_100HDX_CAP].val 235 #define param_10fdx_cap nd_params[PARAM_10FDX_CAP].val 236 #define param_10hdx_cap nd_params[PARAM_10HDX_CAP].val 237 #define param_rem_fault nd_params[PARAM_REM_FAULT].val 238 239 #define param_adv_autoneg_cap nd_params[PARAM_ADV_AUTONEG_CAP].val 240 #define param_adv_pause_cap nd_params[PARAM_ADV_PAUSE_CAP].val 241 #define param_adv_asym_pause_cap nd_params[PARAM_ADV_ASYM_PAUSE_CAP].val 242 #define param_adv_1000fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 243 #define param_adv_1000hdx_cap nd_params[PARAM_ADV_1000HDX_CAP].val 244 #define param_adv_100t4_cap nd_params[PARAM_ADV_100T4_CAP].val 245 #define param_adv_100fdx_cap nd_params[PARAM_ADV_100FDX_CAP].val 246 #define param_adv_100hdx_cap nd_params[PARAM_ADV_100HDX_CAP].val 247 #define param_adv_10fdx_cap nd_params[PARAM_ADV_10FDX_CAP].val 248 #define param_adv_10hdx_cap nd_params[PARAM_ADV_10HDX_CAP].val 249 #define param_adv_rem_fault nd_params[PARAM_ADV_REM_FAULT].val 250 251 #define param_lp_autoneg_cap nd_params[PARAM_LP_AUTONEG_CAP].val 252 #define param_lp_pause_cap nd_params[PARAM_LP_PAUSE_CAP].val 253 #define param_lp_asym_pause_cap nd_params[PARAM_LP_ASYM_PAUSE_CAP].val 254 #define param_lp_1000fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 255 #define param_lp_1000hdx_cap nd_params[PARAM_LP_1000HDX_CAP].val 256 #define param_lp_100t4_cap nd_params[PARAM_LP_100T4_CAP].val 257 #define param_lp_100fdx_cap nd_params[PARAM_LP_100FDX_CAP].val 258 #define param_lp_100hdx_cap nd_params[PARAM_LP_100HDX_CAP].val 259 #define param_lp_10fdx_cap nd_params[PARAM_LP_10FDX_CAP].val 260 #define param_lp_10hdx_cap nd_params[PARAM_LP_10HDX_CAP].val 261 #define param_lp_rem_fault nd_params[PARAM_LP_REM_FAULT].val 262 263 enum ioc_reply { 264 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 265 IOC_DONE, /* OK, reply sent */ 266 IOC_ACK, /* OK, just send ACK */ 267 IOC_REPLY /* OK, just send reply */ 268 }; 269 270 #define MBLK_LEN(mp) ((uintptr_t)(mp)->b_wptr - \ 271 (uintptr_t)(mp)->b_rptr) 272 273 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 274 0, 0, (flag))) 275 276 /* 277 * Defined for ring index operations 278 * ASSERT(index < limit) 279 * ASSERT(step < limit) 280 * ASSERT(index1 < limit) 281 * ASSERT(index2 < limit) 282 */ 283 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 284 (index) + (step) : (index) + (step) - (limit)) 285 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 286 (index) - (step) : (index) + (limit) - (step)) 287 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 288 (index2) - (index1) : (index2) + (limit) - (index1)) 289 290 #define LINK_LIST_INIT(_LH) \ 291 (_LH)->head = (_LH)->tail = NULL 292 293 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 294 295 #define LIST_POP_HEAD(_LH) \ 296 (single_link_t *)(_LH)->head; \ 297 { \ 298 if ((_LH)->head != NULL) { \ 299 (_LH)->head = (_LH)->head->link; \ 300 if ((_LH)->head == NULL) \ 301 (_LH)->tail = NULL; \ 302 } \ 303 } 304 305 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 306 307 #define LIST_PUSH_TAIL(_LH, _E) \ 308 if ((_LH)->tail != NULL) { \ 309 (_LH)->tail->link = (single_link_t *)(_E); \ 310 (_LH)->tail = (single_link_t *)(_E); \ 311 } else { \ 312 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 313 } \ 314 (_E)->link = NULL; 315 316 #define LIST_GET_NEXT(_LH, _E) \ 317 (((_LH)->tail == (single_link_t *)(_E)) ? \ 318 NULL : ((single_link_t *)(_E))->link) 319 320 321 typedef struct single_link { 322 struct single_link *link; 323 } single_link_t; 324 325 typedef struct link_list { 326 single_link_t *head; 327 single_link_t *tail; 328 } link_list_t; 329 330 /* 331 * Property lookups 332 */ 333 #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 334 DDI_PROP_DONTPASS, (n)) 335 #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 336 DDI_PROP_DONTPASS, (n), -1) 337 338 339 /* 340 * Named Data (ND) Parameter Management Structure 341 */ 342 typedef struct { 343 struct igb *private; 344 uint32_t info; 345 uint32_t min; 346 uint32_t max; 347 uint32_t val; 348 char *name; 349 } nd_param_t; 350 351 /* 352 * NDD parameter indexes, divided into: 353 * 354 * read-only parameters describing the hardware's capabilities 355 * read-write parameters controlling the advertised capabilities 356 * read-only parameters describing the partner's capabilities 357 * read-write parameters controlling the force speed and duplex 358 * read-only parameters describing the link state 359 * read-only parameters describing the driver properties 360 * read-write parameters controlling the driver properties 361 */ 362 enum { 363 PARAM_AUTONEG_CAP, 364 PARAM_PAUSE_CAP, 365 PARAM_ASYM_PAUSE_CAP, 366 PARAM_1000FDX_CAP, 367 PARAM_1000HDX_CAP, 368 PARAM_100T4_CAP, 369 PARAM_100FDX_CAP, 370 PARAM_100HDX_CAP, 371 PARAM_10FDX_CAP, 372 PARAM_10HDX_CAP, 373 PARAM_REM_FAULT, 374 375 PARAM_ADV_AUTONEG_CAP, 376 PARAM_ADV_PAUSE_CAP, 377 PARAM_ADV_ASYM_PAUSE_CAP, 378 PARAM_ADV_1000FDX_CAP, 379 PARAM_ADV_1000HDX_CAP, 380 PARAM_ADV_100T4_CAP, 381 PARAM_ADV_100FDX_CAP, 382 PARAM_ADV_100HDX_CAP, 383 PARAM_ADV_10FDX_CAP, 384 PARAM_ADV_10HDX_CAP, 385 PARAM_ADV_REM_FAULT, 386 387 PARAM_LP_AUTONEG_CAP, 388 PARAM_LP_PAUSE_CAP, 389 PARAM_LP_ASYM_PAUSE_CAP, 390 PARAM_LP_1000FDX_CAP, 391 PARAM_LP_1000HDX_CAP, 392 PARAM_LP_100T4_CAP, 393 PARAM_LP_100FDX_CAP, 394 PARAM_LP_100HDX_CAP, 395 PARAM_LP_10FDX_CAP, 396 PARAM_LP_10HDX_CAP, 397 PARAM_LP_REM_FAULT, 398 399 PARAM_LINK_STATUS, 400 PARAM_LINK_SPEED, 401 PARAM_LINK_DUPLEX, 402 403 PARAM_COUNT 404 }; 405 406 typedef union igb_ether_addr { 407 struct { 408 uint32_t high; 409 uint32_t low; 410 } reg; 411 struct { 412 uint8_t set; 413 uint8_t redundant; 414 uint8_t addr[ETHERADDRL]; 415 } mac; 416 } igb_ether_addr_t; 417 418 typedef enum { 419 USE_NONE, 420 USE_COPY, 421 USE_DMA 422 } tx_type_t; 423 424 typedef enum { 425 RCB_FREE, 426 RCB_SENDUP 427 } rcb_state_t; 428 429 typedef struct hcksum_context { 430 uint32_t hcksum_flags; 431 uint32_t ip_hdr_len; 432 uint32_t mac_hdr_len; 433 uint32_t l4_proto; 434 } hcksum_context_t; 435 436 /* Hold address/length of each DMA segment */ 437 typedef struct sw_desc { 438 uint64_t address; 439 size_t length; 440 } sw_desc_t; 441 442 /* Handles and addresses of DMA buffer */ 443 typedef struct dma_buffer { 444 caddr_t address; /* Virtual address */ 445 uint64_t dma_address; /* DMA (Hardware) address */ 446 ddi_acc_handle_t acc_handle; /* Data access handle */ 447 ddi_dma_handle_t dma_handle; /* DMA handle */ 448 size_t size; /* Buffer size */ 449 size_t len; /* Data length in the buffer */ 450 } dma_buffer_t; 451 452 /* 453 * Tx Control Block 454 */ 455 typedef struct tx_control_block { 456 single_link_t link; 457 uint32_t frag_num; 458 uint32_t desc_num; 459 mblk_t *mp; 460 tx_type_t tx_type; 461 ddi_dma_handle_t tx_dma_handle; 462 dma_buffer_t tx_buf; 463 sw_desc_t desc[MAX_COOKIE]; 464 } tx_control_block_t; 465 466 /* 467 * RX Control Block 468 */ 469 typedef struct rx_control_block { 470 mblk_t *mp; 471 rcb_state_t state; 472 dma_buffer_t rx_buf; 473 frtn_t free_rtn; 474 struct igb_rx_ring *rx_ring; 475 } rx_control_block_t; 476 477 /* 478 * Software Data Structure for Tx Ring 479 */ 480 typedef struct igb_tx_ring { 481 uint32_t index; /* Ring index */ 482 483 /* 484 * Mutexes 485 */ 486 kmutex_t tx_lock; 487 kmutex_t recycle_lock; 488 kmutex_t tcb_head_lock; 489 kmutex_t tcb_tail_lock; 490 491 /* 492 * Tx descriptor ring definitions 493 */ 494 dma_buffer_t tbd_area; 495 union e1000_adv_tx_desc *tbd_ring; 496 uint32_t tbd_head; /* Index of next tbd to recycle */ 497 uint32_t tbd_tail; /* Index of next tbd to transmit */ 498 uint32_t tbd_free; /* Number of free tbd */ 499 500 /* 501 * Tx control block list definitions 502 */ 503 tx_control_block_t *tcb_area; 504 tx_control_block_t **work_list; 505 tx_control_block_t **free_list; 506 uint32_t tcb_head; /* Head index of free list */ 507 uint32_t tcb_tail; /* Tail index of free list */ 508 uint32_t tcb_free; /* Number of free tcb in free list */ 509 510 uint32_t *tbd_head_wb; /* Head write-back */ 511 uint32_t (*tx_recycle)(struct igb_tx_ring *); 512 513 /* 514 * TCP/UDP checksum offload 515 */ 516 hcksum_context_t hcksum_context; 517 518 /* 519 * Tx ring settings and status 520 */ 521 uint32_t ring_size; /* Tx descriptor ring size */ 522 uint32_t free_list_size; /* Tx free list size */ 523 uint32_t copy_thresh; 524 uint32_t recycle_thresh; 525 uint32_t overload_thresh; 526 uint32_t resched_thresh; 527 528 boolean_t reschedule; 529 uint32_t recycle_fail; 530 uint32_t stall_watchdog; 531 532 #ifdef IGB_DEBUG 533 /* 534 * Debug statistics 535 */ 536 uint32_t stat_overload; 537 uint32_t stat_fail_no_tbd; 538 uint32_t stat_fail_no_tcb; 539 uint32_t stat_fail_dma_bind; 540 uint32_t stat_reschedule; 541 #endif 542 543 /* 544 * Pointer to the igb struct 545 */ 546 struct igb *igb; 547 548 } igb_tx_ring_t; 549 550 /* 551 * Software Receive Ring 552 */ 553 typedef struct igb_rx_ring { 554 uint32_t index; /* Ring index */ 555 uint32_t intr_vector; /* Interrupt vector index */ 556 557 /* 558 * Mutexes 559 */ 560 kmutex_t rx_lock; /* Rx access lock */ 561 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 562 563 /* 564 * Rx descriptor ring definitions 565 */ 566 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 567 union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */ 568 uint32_t rbd_next; /* Index of next rx desc */ 569 570 /* 571 * Rx control block list definitions 572 */ 573 rx_control_block_t *rcb_area; 574 rx_control_block_t **work_list; /* Work list of rcbs */ 575 rx_control_block_t **free_list; /* Free list of rcbs */ 576 uint32_t rcb_head; /* Index of next free rcb */ 577 uint32_t rcb_tail; /* Index to put recycled rcb */ 578 uint32_t rcb_free; /* Number of free rcbs */ 579 580 /* 581 * Rx ring settings and status 582 */ 583 uint32_t ring_size; /* Rx descriptor ring size */ 584 uint32_t free_list_size; /* Rx free list size */ 585 uint32_t limit_per_intr; /* Max packets per interrupt */ 586 uint32_t copy_thresh; 587 588 #ifdef IGB_DEBUG 589 /* 590 * Debug statistics 591 */ 592 uint32_t stat_frame_error; 593 uint32_t stat_cksum_error; 594 uint32_t stat_exceed_pkt; 595 #endif 596 597 struct igb *igb; /* Pointer to igb struct */ 598 599 } igb_rx_ring_t; 600 601 typedef struct igb { 602 int instance; 603 mac_handle_t mac_hdl; 604 dev_info_t *dip; 605 struct e1000_hw hw; 606 struct igb_osdep osdep; 607 608 uint32_t igb_state; 609 link_state_t link_state; 610 uint32_t link_speed; 611 uint32_t link_duplex; 612 uint32_t link_down_timeout; 613 614 uint32_t reset_count; 615 uint32_t attach_progress; 616 uint32_t loopback_mode; 617 uint32_t max_frame_size; 618 619 /* 620 * Receive Rings 621 */ 622 igb_rx_ring_t *rx_rings; /* Array of rx rings */ 623 uint32_t num_rx_rings; /* Number of rx rings in use */ 624 uint32_t rx_ring_size; /* Rx descriptor ring size */ 625 uint32_t rx_buf_size; /* Rx buffer size */ 626 627 /* 628 * Transmit Rings 629 */ 630 igb_tx_ring_t *tx_rings; /* Array of tx rings */ 631 uint32_t num_tx_rings; /* Number of tx rings in use */ 632 uint32_t tx_ring_size; /* Tx descriptor ring size */ 633 uint32_t tx_buf_size; /* Tx buffer size */ 634 635 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 636 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 637 boolean_t lso_enable; /* Large Segment Offload */ 638 uint32_t tx_copy_thresh; /* Tx copy threshold */ 639 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 640 uint32_t tx_overload_thresh; /* Tx overload threshold */ 641 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 642 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 643 uint32_t rx_copy_thresh; /* Rx copy threshold */ 644 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 645 uint32_t intr_throttling[MAX_NUM_EITR]; 646 uint32_t intr_force; 647 648 int intr_type; 649 int intr_cnt; 650 int intr_cap; 651 size_t intr_size; 652 uint_t intr_pri; 653 ddi_intr_handle_t *htable; 654 uint32_t eims_mask; 655 656 kmutex_t gen_lock; /* General lock for device access */ 657 kmutex_t watchdog_lock; 658 659 boolean_t watchdog_enable; 660 boolean_t watchdog_start; 661 timeout_id_t watchdog_tid; 662 663 boolean_t unicst_init; 664 uint32_t unicst_avail; 665 uint32_t unicst_total; 666 igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 667 uint32_t mcast_count; 668 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 669 670 /* 671 * Kstat definitions 672 */ 673 kstat_t *igb_ks; 674 675 /* 676 * NDD definitions 677 */ 678 caddr_t nd_data; 679 nd_param_t nd_params[PARAM_COUNT]; 680 681 /* 682 * FMA capabilities 683 */ 684 int fm_capabilities; 685 686 } igb_t; 687 688 typedef struct igb_stat { 689 690 kstat_named_t link_speed; /* Link Speed */ 691 #ifdef IGB_DEBUG 692 kstat_named_t reset_count; /* Reset Count */ 693 694 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 695 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 696 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 697 698 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 699 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 700 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 701 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 702 kstat_named_t tx_reschedule; /* Tx Reschedule */ 703 704 kstat_named_t gprc; /* Good Packets Received Count */ 705 kstat_named_t gptc; /* Good Packets Xmitted Count */ 706 kstat_named_t gor; /* Good Octets Received Count */ 707 kstat_named_t got; /* Good Octets Xmitd Count */ 708 kstat_named_t prc64; /* Packets Received - 64b */ 709 kstat_named_t prc127; /* Packets Received - 65-127b */ 710 kstat_named_t prc255; /* Packets Received - 127-255b */ 711 kstat_named_t prc511; /* Packets Received - 256-511b */ 712 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 713 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 714 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 715 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 716 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 717 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 718 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 719 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 720 #endif 721 kstat_named_t crcerrs; /* CRC Error Count */ 722 kstat_named_t symerrs; /* Symbol Error Count */ 723 kstat_named_t mpc; /* Missed Packet Count */ 724 kstat_named_t scc; /* Single Collision Count */ 725 kstat_named_t ecol; /* Excessive Collision Count */ 726 kstat_named_t mcc; /* Multiple Collision Count */ 727 kstat_named_t latecol; /* Late Collision Count */ 728 kstat_named_t colc; /* Collision Count */ 729 kstat_named_t dc; /* Defer Count */ 730 kstat_named_t sec; /* Sequence Error Count */ 731 kstat_named_t rlec; /* Receive Length Error Count */ 732 kstat_named_t xonrxc; /* XON Received Count */ 733 kstat_named_t xontxc; /* XON Xmitted Count */ 734 kstat_named_t xoffrxc; /* XOFF Received Count */ 735 kstat_named_t xofftxc; /* Xoff Xmitted Count */ 736 kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 737 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 738 kstat_named_t mprc; /* Multicast Pkts Received Count */ 739 kstat_named_t rnbc; /* Receive No Buffers Count */ 740 kstat_named_t ruc; /* Receive Undersize Count */ 741 kstat_named_t rfc; /* Receive Frag Count */ 742 kstat_named_t roc; /* Receive Oversize Count */ 743 kstat_named_t rjc; /* Receive Jabber Count */ 744 kstat_named_t tor; /* Total Octets Recvd Count */ 745 kstat_named_t tot; /* Total Octets Xmted Count */ 746 kstat_named_t tpr; /* Total Packets Received */ 747 kstat_named_t tpt; /* Total Packets Xmitted */ 748 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 749 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 750 kstat_named_t algnerrc; /* Alignment Error count */ 751 kstat_named_t rxerrc; /* Rx Error Count */ 752 kstat_named_t tncrs; /* Transmit with no CRS */ 753 kstat_named_t cexterr; /* Carrier Extension Error count */ 754 kstat_named_t tsctc; /* TCP seg contexts xmit count */ 755 kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */ 756 } igb_stat_t; 757 758 /* 759 * Function prototypes in e1000_osdep.c 760 */ 761 void e1000_enable_pciex_master(struct e1000_hw *); 762 763 /* 764 * Function prototypes in igb_buf.c 765 */ 766 int igb_alloc_dma(igb_t *); 767 void igb_free_dma(igb_t *); 768 769 /* 770 * Function prototypes in igb_main.c 771 */ 772 int igb_start(igb_t *); 773 void igb_stop(igb_t *); 774 int igb_setup_link(igb_t *, boolean_t); 775 int igb_unicst_set(igb_t *, const uint8_t *, mac_addr_slot_t); 776 int igb_multicst_add(igb_t *, const uint8_t *); 777 int igb_multicst_remove(igb_t *, const uint8_t *); 778 enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *); 779 void igb_enable_watchdog_timer(igb_t *); 780 void igb_disable_watchdog_timer(igb_t *); 781 int igb_atomic_reserve(uint32_t *, uint32_t); 782 int igb_check_acc_handle(ddi_acc_handle_t); 783 int igb_check_dma_handle(ddi_dma_handle_t); 784 void igb_fm_ereport(igb_t *, char *); 785 void igb_set_fma_flags(int, int); 786 787 /* 788 * Function prototypes in igb_gld.c 789 */ 790 int igb_m_start(void *); 791 void igb_m_stop(void *); 792 int igb_m_promisc(void *, boolean_t); 793 int igb_m_multicst(void *, boolean_t, const uint8_t *); 794 int igb_m_unicst(void *, const uint8_t *); 795 int igb_m_stat(void *, uint_t, uint64_t *); 796 void igb_m_resources(void *); 797 void igb_m_ioctl(void *, queue_t *, mblk_t *); 798 int igb_m_unicst_add(void *, mac_multi_addr_t *); 799 int igb_m_unicst_remove(void *, mac_addr_slot_t); 800 int igb_m_unicst_modify(void *, mac_multi_addr_t *); 801 int igb_m_unicst_get(void *, mac_multi_addr_t *); 802 boolean_t igb_m_getcapab(void *, mac_capab_t, void *); 803 804 /* 805 * Function prototypes in igb_rx.c 806 */ 807 mblk_t *igb_rx(igb_rx_ring_t *); 808 void igb_rx_recycle(caddr_t arg); 809 810 /* 811 * Function prototypes in igb_tx.c 812 */ 813 mblk_t *igb_m_tx(void *, mblk_t *); 814 void igb_free_tcb(tx_control_block_t *); 815 void igb_put_free_list(igb_tx_ring_t *, link_list_t *); 816 uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *); 817 uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *); 818 819 /* 820 * Function prototypes in igb_log.c 821 */ 822 void igb_notice(void *, const char *, ...); 823 void igb_log(void *, const char *, ...); 824 void igb_error(void *, const char *, ...); 825 826 /* 827 * Function prototypes in igb_ndd.c 828 */ 829 int igb_nd_init(igb_t *); 830 void igb_nd_cleanup(igb_t *); 831 enum ioc_reply igb_nd_ioctl(igb_t *, queue_t *, mblk_t *, struct iocblk *); 832 833 /* 834 * Function prototypes in igb_stat.c 835 */ 836 int igb_init_stats(igb_t *); 837 838 839 #ifdef __cplusplus 840 } 841 #endif 842 843 #endif /* _IGB_SW_H */ 844