1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #include "igb_sw.h" 30 #include "igb_debug.h" 31 32 #ifdef IGB_DEBUG 33 extern ddi_device_acc_attr_t igb_regs_acc_attr; 34 35 void 36 pci_dump(void *arg) 37 { 38 igb_t *igb = (igb_t *)arg; 39 ddi_acc_handle_t handle; 40 uint8_t cap_ptr; 41 uint8_t next_ptr; 42 uint32_t msix_bar; 43 uint32_t msix_ctrl; 44 uint32_t msix_tbl_sz; 45 uint32_t tbl_offset; 46 uint32_t tbl_bir; 47 uint32_t pba_offset; 48 uint32_t pba_bir; 49 off_t offset; 50 off_t mem_size; 51 uintptr_t base; 52 ddi_acc_handle_t acc_hdl; 53 int i; 54 55 handle = igb->osdep.cfg_handle; 56 57 igb_log(igb, "Begin dump PCI config space"); 58 59 igb_log(igb, 60 "PCI_CONF_VENID:\t0x%x\n", 61 pci_config_get16(handle, PCI_CONF_VENID)); 62 igb_log(igb, 63 "PCI_CONF_DEVID:\t0x%x\n", 64 pci_config_get16(handle, PCI_CONF_DEVID)); 65 igb_log(igb, 66 "PCI_CONF_COMMAND:\t0x%x\n", 67 pci_config_get16(handle, PCI_CONF_COMM)); 68 igb_log(igb, 69 "PCI_CONF_STATUS:\t0x%x\n", 70 pci_config_get16(handle, PCI_CONF_STAT)); 71 igb_log(igb, 72 "PCI_CONF_REVID:\t0x%x\n", 73 pci_config_get8(handle, PCI_CONF_REVID)); 74 igb_log(igb, 75 "PCI_CONF_PROG_CLASS:\t0x%x\n", 76 pci_config_get8(handle, PCI_CONF_PROGCLASS)); 77 igb_log(igb, 78 "PCI_CONF_SUB_CLASS:\t0x%x\n", 79 pci_config_get8(handle, PCI_CONF_SUBCLASS)); 80 igb_log(igb, 81 "PCI_CONF_BAS_CLASS:\t0x%x\n", 82 pci_config_get8(handle, PCI_CONF_BASCLASS)); 83 igb_log(igb, 84 "PCI_CONF_CACHE_LINESZ:\t0x%x\n", 85 pci_config_get8(handle, PCI_CONF_CACHE_LINESZ)); 86 igb_log(igb, 87 "PCI_CONF_LATENCY_TIMER:\t0x%x\n", 88 pci_config_get8(handle, PCI_CONF_LATENCY_TIMER)); 89 igb_log(igb, 90 "PCI_CONF_HEADER_TYPE:\t0x%x\n", 91 pci_config_get8(handle, PCI_CONF_HEADER)); 92 igb_log(igb, 93 "PCI_CONF_BIST:\t0x%x\n", 94 pci_config_get8(handle, PCI_CONF_BIST)); 95 igb_log(igb, 96 "PCI_CONF_BASE0:\t0x%x\n", 97 pci_config_get32(handle, PCI_CONF_BASE0)); 98 igb_log(igb, 99 "PCI_CONF_BASE1:\t0x%x\n", 100 pci_config_get32(handle, PCI_CONF_BASE1)); 101 igb_log(igb, 102 "PCI_CONF_BASE2:\t0x%x\n", 103 pci_config_get32(handle, PCI_CONF_BASE2)); 104 105 /* MSI-X BAR */ 106 msix_bar = pci_config_get32(handle, PCI_CONF_BASE3); 107 igb_log(igb, 108 "PCI_CONF_BASE3:\t0x%x\n", msix_bar); 109 110 igb_log(igb, 111 "PCI_CONF_BASE4:\t0x%x\n", 112 pci_config_get32(handle, PCI_CONF_BASE4)); 113 igb_log(igb, 114 "PCI_CONF_BASE5:\t0x%x\n", 115 pci_config_get32(handle, PCI_CONF_BASE5)); 116 igb_log(igb, 117 "PCI_CONF_CIS:\t0x%x\n", 118 pci_config_get32(handle, PCI_CONF_CIS)); 119 igb_log(igb, 120 "PCI_CONF_SUBVENID:\t0x%x\n", 121 pci_config_get16(handle, PCI_CONF_SUBVENID)); 122 igb_log(igb, 123 "PCI_CONF_SUBSYSID:\t0x%x\n", 124 pci_config_get16(handle, PCI_CONF_SUBSYSID)); 125 igb_log(igb, 126 "PCI_CONF_ROM:\t0x%x\n", 127 pci_config_get32(handle, PCI_CONF_ROM)); 128 129 cap_ptr = pci_config_get8(handle, PCI_CONF_CAP_PTR); 130 131 igb_log(igb, 132 "PCI_CONF_CAP_PTR:\t0x%x\n", cap_ptr); 133 igb_log(igb, 134 "PCI_CONF_ILINE:\t0x%x\n", 135 pci_config_get8(handle, PCI_CONF_ILINE)); 136 igb_log(igb, 137 "PCI_CONF_IPIN:\t0x%x\n", 138 pci_config_get8(handle, PCI_CONF_IPIN)); 139 igb_log(igb, 140 "PCI_CONF_MIN_G:\t0x%x\n", 141 pci_config_get8(handle, PCI_CONF_MIN_G)); 142 igb_log(igb, 143 "PCI_CONF_MAX_L:\t0x%x\n", 144 pci_config_get8(handle, PCI_CONF_MAX_L)); 145 146 /* Power Management */ 147 offset = cap_ptr; 148 149 igb_log(igb, 150 "PCI_PM_CAP_ID:\t0x%x\n", 151 pci_config_get8(handle, offset)); 152 153 next_ptr = pci_config_get8(handle, offset + 1); 154 155 igb_log(igb, 156 "PCI_PM_NEXT_PTR:\t0x%x\n", next_ptr); 157 igb_log(igb, 158 "PCI_PM_CAP:\t0x%x\n", 159 pci_config_get16(handle, offset + PCI_PMCAP)); 160 igb_log(igb, 161 "PCI_PM_CSR:\t0x%x\n", 162 pci_config_get16(handle, offset + PCI_PMCSR)); 163 igb_log(igb, 164 "PCI_PM_CSR_BSE:\t0x%x\n", 165 pci_config_get8(handle, offset + PCI_PMCSR_BSE)); 166 igb_log(igb, 167 "PCI_PM_DATA:\t0x%x\n", 168 pci_config_get8(handle, offset + PCI_PMDATA)); 169 170 /* MSI Configuration */ 171 offset = next_ptr; 172 173 igb_log(igb, 174 "PCI_MSI_CAP_ID:\t0x%x\n", 175 pci_config_get8(handle, offset)); 176 177 next_ptr = pci_config_get8(handle, offset + 1); 178 179 igb_log(igb, 180 "PCI_MSI_NEXT_PTR:\t0x%x\n", next_ptr); 181 igb_log(igb, 182 "PCI_MSI_CTRL:\t0x%x\n", 183 pci_config_get16(handle, offset + PCI_MSI_CTRL)); 184 igb_log(igb, 185 "PCI_MSI_ADDR:\t0x%x\n", 186 pci_config_get32(handle, offset + PCI_MSI_ADDR_OFFSET)); 187 igb_log(igb, 188 "PCI_MSI_ADDR_HI:\t0x%x\n", 189 pci_config_get32(handle, offset + 0x8)); 190 igb_log(igb, 191 "PCI_MSI_DATA:\t0x%x\n", 192 pci_config_get16(handle, offset + 0xC)); 193 194 /* MSI-X Configuration */ 195 offset = next_ptr; 196 197 igb_log(igb, 198 "PCI_MSIX_CAP_ID:\t0x%x\n", 199 pci_config_get8(handle, offset)); 200 201 next_ptr = pci_config_get8(handle, offset + 1); 202 igb_log(igb, 203 "PCI_MSIX_NEXT_PTR:\t0x%x\n", next_ptr); 204 205 msix_ctrl = pci_config_get16(handle, offset + PCI_MSIX_CTRL); 206 msix_tbl_sz = msix_ctrl & 0x7ff; 207 igb_log(igb, 208 "PCI_MSIX_CTRL:\t0x%x\n", msix_ctrl); 209 210 tbl_offset = pci_config_get32(handle, offset + PCI_MSIX_TBL_OFFSET); 211 tbl_bir = tbl_offset & PCI_MSIX_TBL_BIR_MASK; 212 tbl_offset = tbl_offset & ~PCI_MSIX_TBL_BIR_MASK; 213 igb_log(igb, 214 "PCI_MSIX_TBL_OFFSET:\t0x%x\n", tbl_offset); 215 igb_log(igb, 216 "PCI_MSIX_TBL_BIR:\t0x%x\n", tbl_bir); 217 218 pba_offset = pci_config_get32(handle, offset + PCI_MSIX_PBA_OFFSET); 219 pba_bir = pba_offset & PCI_MSIX_PBA_BIR_MASK; 220 pba_offset = pba_offset & ~PCI_MSIX_PBA_BIR_MASK; 221 igb_log(igb, 222 "PCI_MSIX_PBA_OFFSET:\t0x%x\n", pba_offset); 223 igb_log(igb, 224 "PCI_MSIX_PBA_BIR:\t0x%x\n", pba_bir); 225 226 /* PCI Express Configuration */ 227 offset = next_ptr; 228 229 igb_log(igb, 230 "PCIE_CAP_ID:\t0x%x\n", 231 pci_config_get8(handle, offset + PCIE_CAP_ID)); 232 233 next_ptr = pci_config_get8(handle, offset + PCIE_CAP_NEXT_PTR); 234 235 igb_log(igb, 236 "PCIE_CAP_NEXT_PTR:\t0x%x\n", next_ptr); 237 igb_log(igb, 238 "PCIE_PCIECAP:\t0x%x\n", 239 pci_config_get16(handle, offset + PCIE_PCIECAP)); 240 igb_log(igb, 241 "PCIE_DEVCAP:\t0x%x\n", 242 pci_config_get32(handle, offset + PCIE_DEVCAP)); 243 igb_log(igb, 244 "PCIE_DEVCTL:\t0x%x\n", 245 pci_config_get16(handle, offset + PCIE_DEVCTL)); 246 igb_log(igb, 247 "PCIE_DEVSTS:\t0x%x\n", 248 pci_config_get16(handle, offset + PCIE_DEVSTS)); 249 igb_log(igb, 250 "PCIE_LINKCAP:\t0x%x\n", 251 pci_config_get32(handle, offset + PCIE_LINKCAP)); 252 igb_log(igb, 253 "PCIE_LINKCTL:\t0x%x\n", 254 pci_config_get16(handle, offset + PCIE_LINKCTL)); 255 igb_log(igb, 256 "PCIE_LINKSTS:\t0x%x\n", 257 pci_config_get16(handle, offset + PCIE_LINKSTS)); 258 259 /* MSI-X Memory Space */ 260 if (ddi_dev_regsize(igb->dip, IGB_ADAPTER_MSIXTAB, &mem_size) != 261 DDI_SUCCESS) { 262 igb_log(igb, "ddi_dev_regsize() failed"); 263 return; 264 } 265 266 if ((ddi_regs_map_setup(igb->dip, IGB_ADAPTER_MSIXTAB, (caddr_t *)&base, 267 0, mem_size, &igb_regs_acc_attr, &acc_hdl)) != DDI_SUCCESS) { 268 igb_log(igb, "ddi_regs_map_setup() failed"); 269 return; 270 } 271 272 igb_log(igb, "MSI-X Memory Space: (mem_size = %d, base = %x)", 273 mem_size, base); 274 275 for (i = 0; i <= msix_tbl_sz; i++) { 276 igb_log(igb, "MSI-X Table Entry(%d):", i); 277 igb_log(igb, "lo_addr:\t%x", 278 ddi_get32(acc_hdl, 279 (uint32_t *)(base + tbl_offset + (i * 16)))); 280 igb_log(igb, "up_addr:\t%x", 281 ddi_get32(acc_hdl, 282 (uint32_t *)(base + tbl_offset + (i * 16) + 4))); 283 igb_log(igb, "msg_data:\t%x", 284 ddi_get32(acc_hdl, 285 (uint32_t *)(base + tbl_offset + (i * 16) + 8))); 286 igb_log(igb, "vct_ctrl:\t%x", 287 ddi_get32(acc_hdl, 288 (uint32_t *)(base + tbl_offset + (i * 16) + 12))); 289 } 290 291 igb_log(igb, "MSI-X Pending Bits:\t%x", 292 ddi_get32(acc_hdl, (uint32_t *)(base + pba_offset))); 293 294 ddi_regs_map_free(&acc_hdl); 295 } 296 #endif 297