1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <hxge_impl.h> 27 #include <hxge_rxdma.h> 28 29 /* 30 * Globals: tunable parameters (/etc/system or adb) 31 * 32 */ 33 extern uint32_t hxge_rbr_size; 34 extern uint32_t hxge_rcr_size; 35 extern uint32_t hxge_rbr_spare_size; 36 extern uint32_t hxge_mblks_pending; 37 38 /* 39 * Tunable to reduce the amount of time spent in the 40 * ISR doing Rx Processing. 41 */ 42 extern uint32_t hxge_max_rx_pkts; 43 44 /* 45 * Tunables to manage the receive buffer blocks. 46 * 47 * hxge_rx_threshold_hi: copy all buffers. 48 * hxge_rx_bcopy_size_type: receive buffer block size type. 49 * hxge_rx_threshold_lo: copy only up to tunable block size type. 50 */ 51 extern hxge_rxbuf_threshold_t hxge_rx_threshold_hi; 52 extern hxge_rxbuf_type_t hxge_rx_buf_size_type; 53 extern hxge_rxbuf_threshold_t hxge_rx_threshold_lo; 54 55 static hxge_status_t hxge_map_rxdma(p_hxge_t hxgep); 56 static void hxge_unmap_rxdma(p_hxge_t hxgep); 57 static hxge_status_t hxge_rxdma_hw_start_common(p_hxge_t hxgep); 58 static hxge_status_t hxge_rxdma_hw_start(p_hxge_t hxgep); 59 static void hxge_rxdma_hw_stop(p_hxge_t hxgep); 60 static hxge_status_t hxge_map_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 61 p_hxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 62 uint32_t num_chunks, p_hxge_dma_common_t *dma_rbr_cntl_p, 63 p_hxge_dma_common_t *dma_rcr_cntl_p, p_hxge_dma_common_t *dma_mbox_cntl_p, 64 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p); 65 static void hxge_unmap_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 66 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p); 67 static hxge_status_t hxge_map_rxdma_channel_cfg_ring(p_hxge_t hxgep, 68 uint16_t dma_channel, p_hxge_dma_common_t *dma_rbr_cntl_p, 69 p_hxge_dma_common_t *dma_rcr_cntl_p, p_hxge_dma_common_t *dma_mbox_cntl_p, 70 p_rx_rbr_ring_t *rbr_p, p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p); 71 static void hxge_unmap_rxdma_channel_cfg_ring(p_hxge_t hxgep, 72 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p); 73 static hxge_status_t hxge_map_rxdma_channel_buf_ring(p_hxge_t hxgep, 74 uint16_t channel, p_hxge_dma_common_t *dma_buf_p, 75 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks); 76 static void hxge_unmap_rxdma_channel_buf_ring(p_hxge_t hxgep, 77 p_rx_rbr_ring_t rbr_p); 78 static hxge_status_t hxge_rxdma_start_channel(p_hxge_t hxgep, uint16_t channel, 79 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p); 80 static hxge_status_t hxge_rxdma_stop_channel(p_hxge_t hxgep, uint16_t channel); 81 static mblk_t *hxge_rx_pkts(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp, 82 p_rx_rcr_ring_t *rcr_p, rdc_stat_t cs); 83 static void hxge_receive_packet(p_hxge_t hxgep, p_rx_rcr_ring_t rcr_p, 84 p_rcr_entry_t rcr_desc_rd_head_p, boolean_t *multi_p, 85 mblk_t ** mp, mblk_t ** mp_cont, uint32_t *invalid_rcr_entry); 86 static hxge_status_t hxge_disable_rxdma_channel(p_hxge_t hxgep, 87 uint16_t channel); 88 static p_rx_msg_t hxge_allocb(size_t, uint32_t, p_hxge_dma_common_t); 89 static void hxge_freeb(p_rx_msg_t); 90 static void hxge_rx_pkts_vring(p_hxge_t hxgep, uint_t vindex, 91 p_hxge_ldv_t ldvp, rdc_stat_t cs); 92 static hxge_status_t hxge_rx_err_evnts(p_hxge_t hxgep, uint_t index, 93 p_hxge_ldv_t ldvp, rdc_stat_t cs); 94 static hxge_status_t hxge_rxbuf_index_info_init(p_hxge_t hxgep, 95 p_rx_rbr_ring_t rx_dmap); 96 static hxge_status_t hxge_rxdma_fatal_err_recover(p_hxge_t hxgep, 97 uint16_t channel); 98 static hxge_status_t hxge_rx_port_fatal_err_recover(p_hxge_t hxgep); 99 100 #define HXGE_RXDMA_RBB_MAX(x) (((x) >> 4) * 15) 101 #define HXGE_RXDMA_RBB_MIN(x) ((x) >> 4) 102 #define HXGE_RXDMA_RBB_THRESHOLD(x) (((x) >> 4) * 14) 103 104 hxge_status_t 105 hxge_init_rxdma_channels(p_hxge_t hxgep) 106 { 107 hxge_status_t status = HXGE_OK; 108 block_reset_t reset_reg; 109 110 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_init_rxdma_channels")); 111 112 /* Reset RDC block from PEU to clear any previous state */ 113 reset_reg.value = 0; 114 reset_reg.bits.rdc_rst = 1; 115 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value); 116 HXGE_DELAY(1000); 117 118 status = hxge_map_rxdma(hxgep); 119 if (status != HXGE_OK) { 120 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 121 "<== hxge_init_rxdma: status 0x%x", status)); 122 return (status); 123 } 124 125 status = hxge_rxdma_hw_start_common(hxgep); 126 if (status != HXGE_OK) { 127 hxge_unmap_rxdma(hxgep); 128 } 129 130 status = hxge_rxdma_hw_start(hxgep); 131 if (status != HXGE_OK) { 132 hxge_unmap_rxdma(hxgep); 133 } 134 135 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 136 "<== hxge_init_rxdma_channels: status 0x%x", status)); 137 return (status); 138 } 139 140 void 141 hxge_uninit_rxdma_channels(p_hxge_t hxgep) 142 { 143 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_uninit_rxdma_channels")); 144 145 hxge_rxdma_hw_stop(hxgep); 146 hxge_unmap_rxdma(hxgep); 147 148 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_uinit_rxdma_channels")); 149 } 150 151 hxge_status_t 152 hxge_init_rxdma_channel_cntl_stat(p_hxge_t hxgep, uint16_t channel, 153 rdc_stat_t *cs_p) 154 { 155 hpi_handle_t handle; 156 hpi_status_t rs = HPI_SUCCESS; 157 hxge_status_t status = HXGE_OK; 158 159 HXGE_DEBUG_MSG((hxgep, DMA_CTL, 160 "<== hxge_init_rxdma_channel_cntl_stat")); 161 162 handle = HXGE_DEV_HPI_HANDLE(hxgep); 163 rs = hpi_rxdma_control_status(handle, OP_SET, channel, cs_p); 164 165 if (rs != HPI_SUCCESS) { 166 status = HXGE_ERROR | rs; 167 } 168 return (status); 169 } 170 171 172 hxge_status_t 173 hxge_enable_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 174 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 175 { 176 hpi_handle_t handle; 177 rdc_desc_cfg_t rdc_desc; 178 rdc_rcr_cfg_b_t *cfgb_p; 179 hpi_status_t rs = HPI_SUCCESS; 180 181 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel")); 182 handle = HXGE_DEV_HPI_HANDLE(hxgep); 183 184 /* 185 * Use configuration data composed at init time. Write to hardware the 186 * receive ring configurations. 187 */ 188 rdc_desc.mbox_enable = 1; 189 rdc_desc.mbox_addr = mbox_p->mbox_addr; 190 HXGE_DEBUG_MSG((hxgep, RX_CTL, 191 "==> hxge_enable_rxdma_channel: mboxp $%p($%p)", 192 mbox_p->mbox_addr, rdc_desc.mbox_addr)); 193 194 rdc_desc.rbr_len = rbr_p->rbb_max; 195 rdc_desc.rbr_addr = rbr_p->rbr_addr; 196 197 switch (hxgep->rx_bksize_code) { 198 case RBR_BKSIZE_4K: 199 rdc_desc.page_size = SIZE_4KB; 200 break; 201 case RBR_BKSIZE_8K: 202 rdc_desc.page_size = SIZE_8KB; 203 break; 204 } 205 206 rdc_desc.size0 = rbr_p->hpi_pkt_buf_size0; 207 rdc_desc.valid0 = 1; 208 209 rdc_desc.size1 = rbr_p->hpi_pkt_buf_size1; 210 rdc_desc.valid1 = 1; 211 212 rdc_desc.size2 = rbr_p->hpi_pkt_buf_size2; 213 rdc_desc.valid2 = 1; 214 215 rdc_desc.full_hdr = rcr_p->full_hdr_flag; 216 rdc_desc.offset = rcr_p->sw_priv_hdr_len; 217 218 rdc_desc.rcr_len = rcr_p->comp_size; 219 rdc_desc.rcr_addr = rcr_p->rcr_addr; 220 221 cfgb_p = &(rcr_p->rcr_cfgb); 222 rdc_desc.rcr_threshold = cfgb_p->bits.pthres; 223 rdc_desc.rcr_timeout = cfgb_p->bits.timeout; 224 rdc_desc.rcr_timeout_enable = cfgb_p->bits.entout; 225 226 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel: " 227 "rbr_len qlen %d pagesize code %d rcr_len %d", 228 rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len)); 229 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel: " 230 "size 0 %d size 1 %d size 2 %d", 231 rbr_p->hpi_pkt_buf_size0, rbr_p->hpi_pkt_buf_size1, 232 rbr_p->hpi_pkt_buf_size2)); 233 234 rs = hpi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc, &rdc_desc); 235 if (rs != HPI_SUCCESS) { 236 return (HXGE_ERROR | rs); 237 } 238 239 /* 240 * Enable the timeout and threshold. 241 */ 242 rs = hpi_rxdma_cfg_rdc_rcr_threshold(handle, channel, 243 rdc_desc.rcr_threshold); 244 if (rs != HPI_SUCCESS) { 245 return (HXGE_ERROR | rs); 246 } 247 248 rs = hpi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 249 rdc_desc.rcr_timeout); 250 if (rs != HPI_SUCCESS) { 251 return (HXGE_ERROR | rs); 252 } 253 254 /* Enable the DMA */ 255 rs = hpi_rxdma_cfg_rdc_enable(handle, channel); 256 if (rs != HPI_SUCCESS) { 257 return (HXGE_ERROR | rs); 258 } 259 260 /* 261 * Kick the DMA engine with the initial kick and indicate 262 * that we have remaining blocks to post. 263 */ 264 rbr_p->pages_to_post = HXGE_RXDMA_RBB_MIN(rbr_p->rbb_max); 265 hpi_rxdma_rdc_rbr_kick(handle, channel, 266 HXGE_RXDMA_RBB_MAX(rbr_p->rbb_max)); 267 268 /* Clear the rbr empty bit */ 269 (void) hpi_rxdma_channel_rbr_empty_clear(handle, channel); 270 271 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_enable_rxdma_channel")); 272 273 return (HXGE_OK); 274 } 275 276 static hxge_status_t 277 hxge_disable_rxdma_channel(p_hxge_t hxgep, uint16_t channel) 278 { 279 hpi_handle_t handle; 280 hpi_status_t rs = HPI_SUCCESS; 281 282 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_disable_rxdma_channel")); 283 284 handle = HXGE_DEV_HPI_HANDLE(hxgep); 285 286 /* disable the DMA */ 287 rs = hpi_rxdma_cfg_rdc_disable(handle, channel); 288 if (rs != HPI_SUCCESS) { 289 HXGE_DEBUG_MSG((hxgep, RX_CTL, 290 "<== hxge_disable_rxdma_channel:failed (0x%x)", rs)); 291 return (HXGE_ERROR | rs); 292 } 293 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_disable_rxdma_channel")); 294 return (HXGE_OK); 295 } 296 297 hxge_status_t 298 hxge_rxdma_channel_rcrflush(p_hxge_t hxgep, uint8_t channel) 299 { 300 hpi_handle_t handle; 301 hxge_status_t status = HXGE_OK; 302 303 HXGE_DEBUG_MSG((hxgep, DMA_CTL, 304 "==> hxge_rxdma_channel_rcrflush")); 305 306 handle = HXGE_DEV_HPI_HANDLE(hxgep); 307 hpi_rxdma_rdc_rcr_flush(handle, channel); 308 309 HXGE_DEBUG_MSG((hxgep, DMA_CTL, 310 "<== hxge_rxdma_channel_rcrflush")); 311 return (status); 312 313 } 314 315 #define MID_INDEX(l, r) ((r + l + 1) >> 1) 316 317 #define TO_LEFT -1 318 #define TO_RIGHT 1 319 #define BOTH_RIGHT (TO_RIGHT + TO_RIGHT) 320 #define BOTH_LEFT (TO_LEFT + TO_LEFT) 321 #define IN_MIDDLE (TO_RIGHT + TO_LEFT) 322 #define NO_HINT 0xffffffff 323 324 /*ARGSUSED*/ 325 hxge_status_t 326 hxge_rxbuf_pp_to_vp(p_hxge_t hxgep, p_rx_rbr_ring_t rbr_p, 327 uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp, 328 uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index) 329 { 330 int bufsize; 331 uint64_t pktbuf_pp; 332 uint64_t dvma_addr; 333 rxring_info_t *ring_info; 334 int base_side, end_side; 335 int r_index, l_index, anchor_index; 336 int found, search_done; 337 uint32_t offset, chunk_size, block_size, page_size_mask; 338 uint32_t chunk_index, block_index, total_index; 339 int max_iterations, iteration; 340 rxbuf_index_info_t *bufinfo; 341 342 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> hxge_rxbuf_pp_to_vp")); 343 344 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 345 "==> hxge_rxbuf_pp_to_vp: buf_pp $%p btype %d", 346 pkt_buf_addr_pp, pktbufsz_type)); 347 348 #if defined(__i386) 349 pktbuf_pp = (uint64_t)(uint32_t)pkt_buf_addr_pp; 350 #else 351 pktbuf_pp = (uint64_t)pkt_buf_addr_pp; 352 #endif 353 354 switch (pktbufsz_type) { 355 case 0: 356 bufsize = rbr_p->pkt_buf_size0; 357 break; 358 case 1: 359 bufsize = rbr_p->pkt_buf_size1; 360 break; 361 case 2: 362 bufsize = rbr_p->pkt_buf_size2; 363 break; 364 case RCR_SINGLE_BLOCK: 365 bufsize = 0; 366 anchor_index = 0; 367 break; 368 default: 369 return (HXGE_ERROR); 370 } 371 372 if (rbr_p->num_blocks == 1) { 373 anchor_index = 0; 374 ring_info = rbr_p->ring_info; 375 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 376 377 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 378 "==> hxge_rxbuf_pp_to_vp: (found, 1 block) " 379 "buf_pp $%p btype %d anchor_index %d bufinfo $%p", 380 pkt_buf_addr_pp, pktbufsz_type, anchor_index, bufinfo)); 381 382 goto found_index; 383 } 384 385 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 386 "==> hxge_rxbuf_pp_to_vp: buf_pp $%p btype %d anchor_index %d", 387 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 388 389 ring_info = rbr_p->ring_info; 390 found = B_FALSE; 391 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 392 iteration = 0; 393 max_iterations = ring_info->max_iterations; 394 395 /* 396 * First check if this block have been seen recently. This is indicated 397 * by a hint which is initialized when the first buffer of the block is 398 * seen. The hint is reset when the last buffer of the block has been 399 * processed. As three block sizes are supported, three hints are kept. 400 * The idea behind the hints is that once the hardware uses a block 401 * for a buffer of that size, it will use it exclusively for that size 402 * and will use it until it is exhausted. It is assumed that there 403 * would a single block being used for the same buffer sizes at any 404 * given time. 405 */ 406 if (ring_info->hint[pktbufsz_type] != NO_HINT) { 407 anchor_index = ring_info->hint[pktbufsz_type]; 408 dvma_addr = bufinfo[anchor_index].dvma_addr; 409 chunk_size = bufinfo[anchor_index].buf_size; 410 if ((pktbuf_pp >= dvma_addr) && 411 (pktbuf_pp < (dvma_addr + chunk_size))) { 412 found = B_TRUE; 413 /* 414 * check if this is the last buffer in the block If so, 415 * then reset the hint for the size; 416 */ 417 418 if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size)) 419 ring_info->hint[pktbufsz_type] = NO_HINT; 420 } 421 } 422 423 if (found == B_FALSE) { 424 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 425 "==> hxge_rxbuf_pp_to_vp: (!found)" 426 "buf_pp $%p btype %d anchor_index %d", 427 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 428 429 /* 430 * This is the first buffer of the block of this size. Need to 431 * search the whole information array. the search algorithm 432 * uses a binary tree search algorithm. It assumes that the 433 * information is already sorted with increasing order info[0] 434 * < info[1] < info[2] .... < info[n-1] where n is the size of 435 * the information array 436 */ 437 r_index = rbr_p->num_blocks - 1; 438 l_index = 0; 439 search_done = B_FALSE; 440 anchor_index = MID_INDEX(r_index, l_index); 441 while (search_done == B_FALSE) { 442 if ((r_index == l_index) || 443 (iteration >= max_iterations)) 444 search_done = B_TRUE; 445 446 end_side = TO_RIGHT; /* to the right */ 447 base_side = TO_LEFT; /* to the left */ 448 /* read the DVMA address information and sort it */ 449 dvma_addr = bufinfo[anchor_index].dvma_addr; 450 chunk_size = bufinfo[anchor_index].buf_size; 451 452 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 453 "==> hxge_rxbuf_pp_to_vp: (searching)" 454 "buf_pp $%p btype %d " 455 "anchor_index %d chunk_size %d dvmaaddr $%p", 456 pkt_buf_addr_pp, pktbufsz_type, anchor_index, 457 chunk_size, dvma_addr)); 458 459 if (pktbuf_pp >= dvma_addr) 460 base_side = TO_RIGHT; /* to the right */ 461 if (pktbuf_pp < (dvma_addr + chunk_size)) 462 end_side = TO_LEFT; /* to the left */ 463 464 switch (base_side + end_side) { 465 case IN_MIDDLE: 466 /* found */ 467 found = B_TRUE; 468 search_done = B_TRUE; 469 if ((pktbuf_pp + bufsize) < 470 (dvma_addr + chunk_size)) 471 ring_info->hint[pktbufsz_type] = 472 bufinfo[anchor_index].buf_index; 473 break; 474 case BOTH_RIGHT: 475 /* not found: go to the right */ 476 l_index = anchor_index + 1; 477 anchor_index = MID_INDEX(r_index, l_index); 478 break; 479 480 case BOTH_LEFT: 481 /* not found: go to the left */ 482 r_index = anchor_index - 1; 483 anchor_index = MID_INDEX(r_index, l_index); 484 break; 485 default: /* should not come here */ 486 return (HXGE_ERROR); 487 } 488 iteration++; 489 } 490 491 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 492 "==> hxge_rxbuf_pp_to_vp: (search done)" 493 "buf_pp $%p btype %d anchor_index %d", 494 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 495 } 496 497 if (found == B_FALSE) { 498 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 499 "==> hxge_rxbuf_pp_to_vp: (search failed)" 500 "buf_pp $%p btype %d anchor_index %d", 501 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 502 return (HXGE_ERROR); 503 } 504 505 found_index: 506 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 507 "==> hxge_rxbuf_pp_to_vp: (FOUND1)" 508 "buf_pp $%p btype %d bufsize %d anchor_index %d", 509 pkt_buf_addr_pp, pktbufsz_type, bufsize, anchor_index)); 510 511 /* index of the first block in this chunk */ 512 chunk_index = bufinfo[anchor_index].start_index; 513 dvma_addr = bufinfo[anchor_index].dvma_addr; 514 page_size_mask = ring_info->block_size_mask; 515 516 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 517 "==> hxge_rxbuf_pp_to_vp: (FOUND3), get chunk)" 518 "buf_pp $%p btype %d bufsize %d " 519 "anchor_index %d chunk_index %d dvma $%p", 520 pkt_buf_addr_pp, pktbufsz_type, bufsize, 521 anchor_index, chunk_index, dvma_addr)); 522 523 offset = pktbuf_pp - dvma_addr; /* offset within the chunk */ 524 block_size = rbr_p->block_size; /* System block(page) size */ 525 526 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 527 "==> hxge_rxbuf_pp_to_vp: (FOUND4), get chunk)" 528 "buf_pp $%p btype %d bufsize %d " 529 "anchor_index %d chunk_index %d dvma $%p " 530 "offset %d block_size %d", 531 pkt_buf_addr_pp, pktbufsz_type, bufsize, anchor_index, 532 chunk_index, dvma_addr, offset, block_size)); 533 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> getting total index")); 534 535 block_index = (offset / block_size); /* index within chunk */ 536 total_index = chunk_index + block_index; 537 538 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 539 "==> hxge_rxbuf_pp_to_vp: " 540 "total_index %d dvma_addr $%p " 541 "offset %d block_size %d " 542 "block_index %d ", 543 total_index, dvma_addr, offset, block_size, block_index)); 544 545 #if defined(__i386) 546 *pkt_buf_addr_p = (uint64_t *)((uint32_t)bufinfo[anchor_index].kaddr + 547 (uint32_t)offset); 548 #else 549 *pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr + 550 offset); 551 #endif 552 553 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 554 "==> hxge_rxbuf_pp_to_vp: " 555 "total_index %d dvma_addr $%p " 556 "offset %d block_size %d " 557 "block_index %d " 558 "*pkt_buf_addr_p $%p", 559 total_index, dvma_addr, offset, block_size, 560 block_index, *pkt_buf_addr_p)); 561 562 *msg_index = total_index; 563 *bufoffset = (offset & page_size_mask); 564 565 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 566 "==> hxge_rxbuf_pp_to_vp: get msg index: " 567 "msg_index %d bufoffset_index %d", 568 *msg_index, *bufoffset)); 569 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "<== hxge_rxbuf_pp_to_vp")); 570 571 return (HXGE_OK); 572 } 573 574 575 /* 576 * used by quick sort (qsort) function 577 * to perform comparison 578 */ 579 static int 580 hxge_sort_compare(const void *p1, const void *p2) 581 { 582 583 rxbuf_index_info_t *a, *b; 584 585 a = (rxbuf_index_info_t *)p1; 586 b = (rxbuf_index_info_t *)p2; 587 588 if (a->dvma_addr > b->dvma_addr) 589 return (1); 590 if (a->dvma_addr < b->dvma_addr) 591 return (-1); 592 return (0); 593 } 594 595 /* 596 * Grabbed this sort implementation from common/syscall/avl.c 597 * 598 * Generic shellsort, from K&R (1st ed, p 58.), somewhat modified. 599 * v = Ptr to array/vector of objs 600 * n = # objs in the array 601 * s = size of each obj (must be multiples of a word size) 602 * f = ptr to function to compare two objs 603 * returns (-1 = less than, 0 = equal, 1 = greater than 604 */ 605 void 606 hxge_ksort(caddr_t v, int n, int s, int (*f) ()) 607 { 608 int g, i, j, ii; 609 unsigned int *p1, *p2; 610 unsigned int tmp; 611 612 /* No work to do */ 613 if (v == NULL || n <= 1) 614 return; 615 /* Sanity check on arguments */ 616 ASSERT(((uintptr_t)v & 0x3) == 0 && (s & 0x3) == 0); 617 ASSERT(s > 0); 618 619 for (g = n / 2; g > 0; g /= 2) { 620 for (i = g; i < n; i++) { 621 for (j = i - g; j >= 0 && 622 (*f) (v + j * s, v + (j + g) * s) == 1; j -= g) { 623 p1 = (unsigned *)(v + j * s); 624 p2 = (unsigned *)(v + (j + g) * s); 625 for (ii = 0; ii < s / 4; ii++) { 626 tmp = *p1; 627 *p1++ = *p2; 628 *p2++ = tmp; 629 } 630 } 631 } 632 } 633 } 634 635 /* 636 * Initialize data structures required for rxdma 637 * buffer dvma->vmem address lookup 638 */ 639 /*ARGSUSED*/ 640 static hxge_status_t 641 hxge_rxbuf_index_info_init(p_hxge_t hxgep, p_rx_rbr_ring_t rbrp) 642 { 643 int index; 644 rxring_info_t *ring_info; 645 int max_iteration = 0, max_index = 0; 646 647 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_rxbuf_index_info_init")); 648 649 ring_info = rbrp->ring_info; 650 ring_info->hint[0] = NO_HINT; 651 ring_info->hint[1] = NO_HINT; 652 ring_info->hint[2] = NO_HINT; 653 max_index = rbrp->num_blocks; 654 655 /* read the DVMA address information and sort it */ 656 /* do init of the information array */ 657 658 HXGE_DEBUG_MSG((hxgep, DMA2_CTL, 659 " hxge_rxbuf_index_info_init Sort ptrs")); 660 661 /* sort the array */ 662 hxge_ksort((void *) ring_info->buffer, max_index, 663 sizeof (rxbuf_index_info_t), hxge_sort_compare); 664 665 for (index = 0; index < max_index; index++) { 666 HXGE_DEBUG_MSG((hxgep, DMA2_CTL, 667 " hxge_rxbuf_index_info_init: sorted chunk %d " 668 " ioaddr $%p kaddr $%p size %x", 669 index, ring_info->buffer[index].dvma_addr, 670 ring_info->buffer[index].kaddr, 671 ring_info->buffer[index].buf_size)); 672 } 673 674 max_iteration = 0; 675 while (max_index >= (1ULL << max_iteration)) 676 max_iteration++; 677 ring_info->max_iterations = max_iteration + 1; 678 679 HXGE_DEBUG_MSG((hxgep, DMA2_CTL, 680 " hxge_rxbuf_index_info_init Find max iter %d", 681 ring_info->max_iterations)); 682 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_rxbuf_index_info_init")); 683 684 return (HXGE_OK); 685 } 686 687 /*ARGSUSED*/ 688 void 689 hxge_dump_rcr_entry(p_hxge_t hxgep, p_rcr_entry_t entry_p) 690 { 691 #ifdef HXGE_DEBUG 692 693 uint32_t bptr; 694 uint64_t pp; 695 696 bptr = entry_p->bits.pkt_buf_addr; 697 698 HXGE_DEBUG_MSG((hxgep, RX_CTL, 699 "\trcr entry $%p " 700 "\trcr entry 0x%0llx " 701 "\trcr entry 0x%08x " 702 "\trcr entry 0x%08x " 703 "\tvalue 0x%0llx\n" 704 "\tmulti = %d\n" 705 "\tpkt_type = 0x%x\n" 706 "\terror = 0x%04x\n" 707 "\tl2_len = %d\n" 708 "\tpktbufsize = %d\n" 709 "\tpkt_buf_addr = $%p\n" 710 "\tpkt_buf_addr (<< 6) = $%p\n", 711 entry_p, 712 *(int64_t *)entry_p, 713 *(int32_t *)entry_p, 714 *(int32_t *)((char *)entry_p + 32), 715 entry_p->value, 716 entry_p->bits.multi, 717 entry_p->bits.pkt_type, 718 entry_p->bits.error, 719 entry_p->bits.l2_len, 720 entry_p->bits.pktbufsz, 721 bptr, 722 entry_p->bits.pkt_buf_addr_l)); 723 724 pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) << 725 RCR_PKT_BUF_ADDR_SHIFT; 726 727 HXGE_DEBUG_MSG((hxgep, RX_CTL, "rcr pp 0x%llx l2 len %d", 728 pp, (*(int64_t *)entry_p >> 40) & 0x3fff)); 729 #endif 730 } 731 732 /*ARGSUSED*/ 733 void 734 hxge_rxdma_stop(p_hxge_t hxgep) 735 { 736 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop")); 737 738 (void) hxge_rx_vmac_disable(hxgep); 739 (void) hxge_rxdma_hw_mode(hxgep, HXGE_DMA_STOP); 740 741 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop")); 742 } 743 744 void 745 hxge_rxdma_stop_reinit(p_hxge_t hxgep) 746 { 747 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_reinit")); 748 749 (void) hxge_rxdma_stop(hxgep); 750 (void) hxge_uninit_rxdma_channels(hxgep); 751 (void) hxge_init_rxdma_channels(hxgep); 752 753 (void) hxge_rx_vmac_enable(hxgep); 754 755 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop_reinit")); 756 } 757 758 hxge_status_t 759 hxge_rxdma_hw_mode(p_hxge_t hxgep, boolean_t enable) 760 { 761 int i, ndmas; 762 uint16_t channel; 763 p_rx_rbr_rings_t rx_rbr_rings; 764 p_rx_rbr_ring_t *rbr_rings; 765 hpi_handle_t handle; 766 hpi_status_t rs = HPI_SUCCESS; 767 hxge_status_t status = HXGE_OK; 768 769 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 770 "==> hxge_rxdma_hw_mode: mode %d", enable)); 771 772 if (!(hxgep->drv_state & STATE_HW_INITIALIZED)) { 773 HXGE_DEBUG_MSG((hxgep, RX_CTL, 774 "<== hxge_rxdma_mode: not initialized")); 775 return (HXGE_ERROR); 776 } 777 778 rx_rbr_rings = hxgep->rx_rbr_rings; 779 if (rx_rbr_rings == NULL) { 780 HXGE_DEBUG_MSG((hxgep, RX_CTL, 781 "<== hxge_rxdma_mode: NULL ring pointer")); 782 return (HXGE_ERROR); 783 } 784 785 if (rx_rbr_rings->rbr_rings == NULL) { 786 HXGE_DEBUG_MSG((hxgep, RX_CTL, 787 "<== hxge_rxdma_mode: NULL rbr rings pointer")); 788 return (HXGE_ERROR); 789 } 790 791 ndmas = rx_rbr_rings->ndmas; 792 if (!ndmas) { 793 HXGE_DEBUG_MSG((hxgep, RX_CTL, 794 "<== hxge_rxdma_mode: no channel")); 795 return (HXGE_ERROR); 796 } 797 798 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 799 "==> hxge_rxdma_mode (ndmas %d)", ndmas)); 800 801 rbr_rings = rx_rbr_rings->rbr_rings; 802 803 handle = HXGE_DEV_HPI_HANDLE(hxgep); 804 805 for (i = 0; i < ndmas; i++) { 806 if (rbr_rings == NULL || rbr_rings[i] == NULL) { 807 continue; 808 } 809 channel = rbr_rings[i]->rdc; 810 if (enable) { 811 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 812 "==> hxge_rxdma_hw_mode: channel %d (enable)", 813 channel)); 814 rs = hpi_rxdma_cfg_rdc_enable(handle, channel); 815 } else { 816 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 817 "==> hxge_rxdma_hw_mode: channel %d (disable)", 818 channel)); 819 rs = hpi_rxdma_cfg_rdc_disable(handle, channel); 820 } 821 } 822 823 status = ((rs == HPI_SUCCESS) ? HXGE_OK : HXGE_ERROR | rs); 824 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 825 "<== hxge_rxdma_hw_mode: status 0x%x", status)); 826 827 return (status); 828 } 829 830 int 831 hxge_rxdma_get_ring_index(p_hxge_t hxgep, uint16_t channel) 832 { 833 int i, ndmas; 834 uint16_t rdc; 835 p_rx_rbr_rings_t rx_rbr_rings; 836 p_rx_rbr_ring_t *rbr_rings; 837 838 HXGE_DEBUG_MSG((hxgep, RX_CTL, 839 "==> hxge_rxdma_get_ring_index: channel %d", channel)); 840 841 rx_rbr_rings = hxgep->rx_rbr_rings; 842 if (rx_rbr_rings == NULL) { 843 HXGE_DEBUG_MSG((hxgep, RX_CTL, 844 "<== hxge_rxdma_get_ring_index: NULL ring pointer")); 845 return (-1); 846 } 847 848 ndmas = rx_rbr_rings->ndmas; 849 if (!ndmas) { 850 HXGE_DEBUG_MSG((hxgep, RX_CTL, 851 "<== hxge_rxdma_get_ring_index: no channel")); 852 return (-1); 853 } 854 855 HXGE_DEBUG_MSG((hxgep, RX_CTL, 856 "==> hxge_rxdma_get_ring_index (ndmas %d)", ndmas)); 857 858 rbr_rings = rx_rbr_rings->rbr_rings; 859 for (i = 0; i < ndmas; i++) { 860 rdc = rbr_rings[i]->rdc; 861 if (channel == rdc) { 862 HXGE_DEBUG_MSG((hxgep, RX_CTL, 863 "==> hxge_rxdma_get_rbr_ring: " 864 "channel %d (index %d) " 865 "ring %d", channel, i, rbr_rings[i])); 866 867 return (i); 868 } 869 } 870 871 HXGE_DEBUG_MSG((hxgep, RX_CTL, 872 "<== hxge_rxdma_get_rbr_ring_index: not found")); 873 874 return (-1); 875 } 876 877 /* 878 * Static functions start here. 879 */ 880 static p_rx_msg_t 881 hxge_allocb(size_t size, uint32_t pri, p_hxge_dma_common_t dmabuf_p) 882 { 883 p_rx_msg_t hxge_mp = NULL; 884 p_hxge_dma_common_t dmamsg_p; 885 uchar_t *buffer; 886 887 hxge_mp = KMEM_ZALLOC(sizeof (rx_msg_t), KM_NOSLEEP); 888 if (hxge_mp == NULL) { 889 HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, 890 "Allocation of a rx msg failed.")); 891 goto hxge_allocb_exit; 892 } 893 894 hxge_mp->use_buf_pool = B_FALSE; 895 if (dmabuf_p) { 896 hxge_mp->use_buf_pool = B_TRUE; 897 898 dmamsg_p = (p_hxge_dma_common_t)&hxge_mp->buf_dma; 899 *dmamsg_p = *dmabuf_p; 900 dmamsg_p->nblocks = 1; 901 dmamsg_p->block_size = size; 902 dmamsg_p->alength = size; 903 buffer = (uchar_t *)dmabuf_p->kaddrp; 904 905 dmabuf_p->kaddrp = (void *)((char *)dmabuf_p->kaddrp + size); 906 dmabuf_p->ioaddr_pp = (void *) 907 ((char *)dmabuf_p->ioaddr_pp + size); 908 909 dmabuf_p->alength -= size; 910 dmabuf_p->offset += size; 911 dmabuf_p->dma_cookie.dmac_laddress += size; 912 dmabuf_p->dma_cookie.dmac_size -= size; 913 } else { 914 buffer = KMEM_ALLOC(size, KM_NOSLEEP); 915 if (buffer == NULL) { 916 HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, 917 "Allocation of a receive page failed.")); 918 goto hxge_allocb_fail1; 919 } 920 } 921 922 hxge_mp->rx_mblk_p = desballoc(buffer, size, pri, &hxge_mp->freeb); 923 if (hxge_mp->rx_mblk_p == NULL) { 924 HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, "desballoc failed.")); 925 goto hxge_allocb_fail2; 926 } 927 hxge_mp->buffer = buffer; 928 hxge_mp->block_size = size; 929 hxge_mp->freeb.free_func = (void (*) ()) hxge_freeb; 930 hxge_mp->freeb.free_arg = (caddr_t)hxge_mp; 931 hxge_mp->ref_cnt = 1; 932 hxge_mp->free = B_TRUE; 933 hxge_mp->rx_use_bcopy = B_FALSE; 934 935 atomic_inc_32(&hxge_mblks_pending); 936 937 goto hxge_allocb_exit; 938 939 hxge_allocb_fail2: 940 if (!hxge_mp->use_buf_pool) { 941 KMEM_FREE(buffer, size); 942 } 943 hxge_allocb_fail1: 944 KMEM_FREE(hxge_mp, sizeof (rx_msg_t)); 945 hxge_mp = NULL; 946 947 hxge_allocb_exit: 948 return (hxge_mp); 949 } 950 951 p_mblk_t 952 hxge_dupb(p_rx_msg_t hxge_mp, uint_t offset, size_t size) 953 { 954 p_mblk_t mp; 955 956 HXGE_DEBUG_MSG((NULL, MEM_CTL, "==> hxge_dupb")); 957 HXGE_DEBUG_MSG((NULL, MEM_CTL, "hxge_mp = $%p " 958 "offset = 0x%08X " "size = 0x%08X", hxge_mp, offset, size)); 959 960 mp = desballoc(&hxge_mp->buffer[offset], size, 0, &hxge_mp->freeb); 961 if (mp == NULL) { 962 HXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 963 goto hxge_dupb_exit; 964 } 965 966 atomic_inc_32(&hxge_mp->ref_cnt); 967 968 hxge_dupb_exit: 969 HXGE_DEBUG_MSG((NULL, MEM_CTL, "<== hxge_dupb mp = $%p", hxge_mp)); 970 return (mp); 971 } 972 973 p_mblk_t 974 hxge_dupb_bcopy(p_rx_msg_t hxge_mp, uint_t offset, size_t size) 975 { 976 p_mblk_t mp; 977 uchar_t *dp; 978 979 mp = allocb(size + HXGE_RXBUF_EXTRA, 0); 980 if (mp == NULL) { 981 HXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 982 goto hxge_dupb_bcopy_exit; 983 } 984 dp = mp->b_rptr = mp->b_rptr + HXGE_RXBUF_EXTRA; 985 bcopy((void *) &hxge_mp->buffer[offset], dp, size); 986 mp->b_wptr = dp + size; 987 988 hxge_dupb_bcopy_exit: 989 990 HXGE_DEBUG_MSG((NULL, MEM_CTL, "<== hxge_dupb mp = $%p", hxge_mp)); 991 992 return (mp); 993 } 994 995 void hxge_post_page(p_hxge_t hxgep, p_rx_rbr_ring_t rx_rbr_p, 996 p_rx_msg_t rx_msg_p); 997 998 void 999 hxge_post_page(p_hxge_t hxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p) 1000 { 1001 hpi_handle_t handle; 1002 uint64_t rbr_qlen, blocks_to_post = 0ULL; 1003 1004 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_post_page")); 1005 1006 /* Reuse this buffer */ 1007 rx_msg_p->free = B_FALSE; 1008 rx_msg_p->cur_usage_cnt = 0; 1009 rx_msg_p->max_usage_cnt = 0; 1010 rx_msg_p->pkt_buf_size = 0; 1011 1012 if (rx_rbr_p->rbr_use_bcopy) { 1013 rx_msg_p->rx_use_bcopy = B_FALSE; 1014 atomic_dec_32(&rx_rbr_p->rbr_consumed); 1015 } 1016 1017 /* 1018 * Get the rbr header pointer and its offset index. 1019 */ 1020 rx_rbr_p->rbr_wr_index = ((rx_rbr_p->rbr_wr_index + 1) & 1021 rx_rbr_p->rbr_wrap_mask); 1022 rx_rbr_p->rbr_desc_vp[rx_rbr_p->rbr_wr_index] = rx_msg_p->shifted_addr; 1023 1024 /* 1025 * Don't post when index is close to 0 or near the max to reduce the 1026 * number rbr_emepty errors 1027 */ 1028 rx_rbr_p->pages_to_post++; 1029 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1030 1031 /* 1032 * False RBR Empty Workaround 1033 */ 1034 RXDMA_REG_READ64(handle, RDC_RBR_QLEN, rx_rbr_p->rdc, &rbr_qlen); 1035 rbr_qlen = rbr_qlen & 0xffff; 1036 1037 if ((rbr_qlen > 0) && 1038 (rbr_qlen < HXGE_RXDMA_RBB_THRESHOLD(rx_rbr_p->rbb_max))) { 1039 blocks_to_post = 1040 HXGE_RXDMA_RBB_MAX(rx_rbr_p->rbb_max) - rbr_qlen; 1041 } 1042 1043 /* 1044 * Clamp posting to what we have available. 1045 */ 1046 if ((blocks_to_post > 0) && 1047 (blocks_to_post > rx_rbr_p->pages_to_post)) { 1048 blocks_to_post = rx_rbr_p->pages_to_post; 1049 } 1050 1051 /* 1052 * Post blocks to the hardware, if any is available. 1053 */ 1054 if (blocks_to_post > 0) { 1055 hpi_rxdma_rdc_rbr_kick(handle, rx_rbr_p->rdc, blocks_to_post); 1056 rx_rbr_p->pages_to_post -= blocks_to_post; 1057 } 1058 1059 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1060 "<== hxge_post_page (channel %d post_next_index %d)", 1061 rx_rbr_p->rdc, rx_rbr_p->rbr_wr_index)); 1062 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_post_page")); 1063 } 1064 1065 void 1066 hxge_freeb(p_rx_msg_t rx_msg_p) 1067 { 1068 size_t size; 1069 uchar_t *buffer = NULL; 1070 int ref_cnt; 1071 boolean_t free_state = B_FALSE; 1072 rx_rbr_ring_t *ring = rx_msg_p->rx_rbr_p; 1073 1074 HXGE_DEBUG_MSG((NULL, MEM2_CTL, "==> hxge_freeb")); 1075 HXGE_DEBUG_MSG((NULL, MEM2_CTL, 1076 "hxge_freeb:rx_msg_p = $%p (block pending %d)", 1077 rx_msg_p, hxge_mblks_pending)); 1078 1079 MUTEX_ENTER(&ring->post_lock); 1080 1081 /* 1082 * First we need to get the free state, then 1083 * atomic decrement the reference count to prevent 1084 * the race condition with the interrupt thread that 1085 * is processing a loaned up buffer block. 1086 */ 1087 free_state = rx_msg_p->free; 1088 1089 ref_cnt = atomic_add_32_nv(&rx_msg_p->ref_cnt, -1); 1090 if (!ref_cnt) { 1091 atomic_dec_32(&hxge_mblks_pending); 1092 1093 buffer = rx_msg_p->buffer; 1094 size = rx_msg_p->block_size; 1095 1096 HXGE_DEBUG_MSG((NULL, MEM2_CTL, "hxge_freeb: " 1097 "will free: rx_msg_p = $%p (block pending %d)", 1098 rx_msg_p, hxge_mblks_pending)); 1099 1100 if (!rx_msg_p->use_buf_pool) { 1101 KMEM_FREE(buffer, size); 1102 } 1103 1104 KMEM_FREE(rx_msg_p, sizeof (rx_msg_t)); 1105 /* Decrement the receive buffer ring's reference count, too. */ 1106 atomic_dec_32(&ring->rbr_ref_cnt); 1107 1108 /* 1109 * Free the receive buffer ring, iff 1110 * 1. all the receive buffers have been freed 1111 * 2. and we are in the proper state (that is, 1112 * we are not UNMAPPING). 1113 */ 1114 if (ring->rbr_ref_cnt == 0 && ring->rbr_state == RBR_UNMAPPED) { 1115 KMEM_FREE(ring, sizeof (*ring)); 1116 } 1117 goto hxge_freeb_exit; 1118 } 1119 1120 /* 1121 * Repost buffer. 1122 */ 1123 if (free_state && (ref_cnt == 1)) { 1124 HXGE_DEBUG_MSG((NULL, RX_CTL, 1125 "hxge_freeb: post page $%p:", rx_msg_p)); 1126 if (ring->rbr_state == RBR_POSTING) 1127 hxge_post_page(rx_msg_p->hxgep, ring, rx_msg_p); 1128 } 1129 1130 hxge_freeb_exit: 1131 MUTEX_EXIT(&ring->post_lock); 1132 HXGE_DEBUG_MSG((NULL, MEM2_CTL, "<== hxge_freeb")); 1133 } 1134 1135 uint_t 1136 hxge_rx_intr(caddr_t arg1, caddr_t arg2) 1137 { 1138 p_hxge_ldv_t ldvp = (p_hxge_ldv_t)arg1; 1139 p_hxge_t hxgep = (p_hxge_t)arg2; 1140 p_hxge_ldg_t ldgp; 1141 uint8_t channel; 1142 hpi_handle_t handle; 1143 rdc_stat_t cs; 1144 uint_t serviced = DDI_INTR_UNCLAIMED; 1145 1146 if (ldvp == NULL) { 1147 HXGE_DEBUG_MSG((NULL, RX_INT_CTL, 1148 "<== hxge_rx_intr: arg2 $%p arg1 $%p", hxgep, ldvp)); 1149 return (DDI_INTR_UNCLAIMED); 1150 } 1151 1152 if (arg2 == NULL || (void *) ldvp->hxgep != arg2) { 1153 hxgep = ldvp->hxgep; 1154 } 1155 1156 /* 1157 * If the interface is not started, just swallow the interrupt 1158 * for the logical device and don't rearm it. 1159 */ 1160 if (hxgep->hxge_mac_state != HXGE_MAC_STARTED) 1161 return (DDI_INTR_CLAIMED); 1162 1163 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1164 "==> hxge_rx_intr: arg2 $%p arg1 $%p", hxgep, ldvp)); 1165 1166 /* 1167 * This interrupt handler is for a specific receive dma channel. 1168 */ 1169 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1170 1171 /* 1172 * Get the control and status for this channel. 1173 */ 1174 channel = ldvp->channel; 1175 ldgp = ldvp->ldgp; 1176 RXDMA_REG_READ64(handle, RDC_STAT, channel, &cs.value); 1177 1178 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_intr:channel %d " 1179 "cs 0x%016llx rcrto 0x%x rcrthres %x", 1180 channel, cs.value, cs.bits.rcr_to, cs.bits.rcr_thres)); 1181 1182 hxge_rx_pkts_vring(hxgep, ldvp->vdma_index, ldvp, cs); 1183 serviced = DDI_INTR_CLAIMED; 1184 1185 /* error events. */ 1186 if (cs.value & RDC_STAT_ERROR) { 1187 (void) hxge_rx_err_evnts(hxgep, ldvp->vdma_index, ldvp, cs); 1188 } 1189 1190 hxge_intr_exit: 1191 /* 1192 * Enable the mailbox update interrupt if we want to use mailbox. We 1193 * probably don't need to use mailbox as it only saves us one pio read. 1194 * Also write 1 to rcrthres and rcrto to clear these two edge triggered 1195 * bits. 1196 */ 1197 cs.value &= RDC_STAT_WR1C; 1198 cs.bits.mex = 1; 1199 cs.bits.ptrread = 0; 1200 cs.bits.pktread = 0; 1201 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); 1202 1203 /* 1204 * Rearm this logical group if this is a single device group. 1205 */ 1206 if (ldgp->nldvs == 1) { 1207 ld_intr_mgmt_t mgm; 1208 1209 mgm.value = 0; 1210 mgm.bits.arm = 1; 1211 mgm.bits.timer = ldgp->ldg_timer; 1212 HXGE_REG_WR32(handle, 1213 LD_INTR_MGMT + LDSV_OFFSET(ldgp->ldg), mgm.value); 1214 } 1215 1216 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1217 "<== hxge_rx_intr: serviced %d", serviced)); 1218 1219 return (serviced); 1220 } 1221 1222 static void 1223 hxge_rx_pkts_vring(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp, 1224 rdc_stat_t cs) 1225 { 1226 p_mblk_t mp; 1227 p_rx_rcr_ring_t rcrp; 1228 1229 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts_vring")); 1230 if ((mp = hxge_rx_pkts(hxgep, vindex, ldvp, &rcrp, cs)) == NULL) { 1231 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1232 "<== hxge_rx_pkts_vring: no mp")); 1233 return; 1234 } 1235 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_pkts_vring: $%p", mp)); 1236 1237 #ifdef HXGE_DEBUG 1238 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1239 "==> hxge_rx_pkts_vring:calling mac_rx (NEMO) " 1240 "LEN %d mp $%p mp->b_next $%p rcrp $%p " 1241 "mac_handle $%p", 1242 (mp->b_wptr - mp->b_rptr), mp, mp->b_next, 1243 rcrp, rcrp->rcr_mac_handle)); 1244 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1245 "==> hxge_rx_pkts_vring: dump packets " 1246 "(mp $%p b_rptr $%p b_wptr $%p):\n %s", 1247 mp, mp->b_rptr, mp->b_wptr, 1248 hxge_dump_packet((char *)mp->b_rptr, 64))); 1249 1250 if (mp->b_cont) { 1251 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1252 "==> hxge_rx_pkts_vring: dump b_cont packets " 1253 "(mp->b_cont $%p b_rptr $%p b_wptr $%p):\n %s", 1254 mp->b_cont, mp->b_cont->b_rptr, mp->b_cont->b_wptr, 1255 hxge_dump_packet((char *)mp->b_cont->b_rptr, 1256 mp->b_cont->b_wptr - mp->b_cont->b_rptr))); 1257 } 1258 if (mp->b_next) { 1259 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1260 "==> hxge_rx_pkts_vring: dump next packets " 1261 "(b_rptr $%p): %s", 1262 mp->b_next->b_rptr, 1263 hxge_dump_packet((char *)mp->b_next->b_rptr, 64))); 1264 } 1265 #endif 1266 1267 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1268 "==> hxge_rx_pkts_vring: send packet to stack")); 1269 mac_rx(hxgep->mach, rcrp->rcr_mac_handle, mp); 1270 1271 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rx_pkts_vring")); 1272 } 1273 1274 /*ARGSUSED*/ 1275 mblk_t * 1276 hxge_rx_pkts(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp, 1277 p_rx_rcr_ring_t *rcrp, rdc_stat_t cs) 1278 { 1279 hpi_handle_t handle; 1280 uint8_t channel; 1281 p_rx_rcr_rings_t rx_rcr_rings; 1282 p_rx_rcr_ring_t rcr_p; 1283 uint32_t comp_rd_index; 1284 p_rcr_entry_t rcr_desc_rd_head_p; 1285 p_rcr_entry_t rcr_desc_rd_head_pp; 1286 p_mblk_t nmp, mp_cont, head_mp, *tail_mp; 1287 uint16_t qlen, nrcr_read, npkt_read; 1288 uint32_t qlen_hw, qlen_sw; 1289 uint32_t invalid_rcr_entry; 1290 boolean_t multi; 1291 rdc_rcr_cfg_b_t rcr_cfg_b; 1292 p_rx_mbox_t rx_mboxp; 1293 p_rxdma_mailbox_t mboxp; 1294 uint64_t rcr_head_index, rcr_tail_index; 1295 uint64_t rcr_tail; 1296 uint64_t value; 1297 rdc_rcr_tail_t rcr_tail_reg; 1298 p_hxge_rx_ring_stats_t rdc_stats; 1299 1300 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts:vindex %d " 1301 "channel %d", vindex, ldvp->channel)); 1302 1303 if (!(hxgep->drv_state & STATE_HW_INITIALIZED)) { 1304 return (NULL); 1305 } 1306 1307 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1308 rx_rcr_rings = hxgep->rx_rcr_rings; 1309 rcr_p = rx_rcr_rings->rcr_rings[vindex]; 1310 channel = rcr_p->rdc; 1311 if (channel != ldvp->channel) { 1312 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts:index %d " 1313 "channel %d, and rcr channel %d not matched.", 1314 vindex, ldvp->channel, channel)); 1315 return (NULL); 1316 } 1317 1318 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1319 "==> hxge_rx_pkts: START: rcr channel %d " 1320 "head_p $%p head_pp $%p index %d ", 1321 channel, rcr_p->rcr_desc_rd_head_p, 1322 rcr_p->rcr_desc_rd_head_pp, rcr_p->comp_rd_index)); 1323 1324 rx_mboxp = hxgep->rx_mbox_areas_p->rxmbox_areas[channel]; 1325 mboxp = (p_rxdma_mailbox_t)rx_mboxp->rx_mbox.kaddrp; 1326 1327 (void) hpi_rxdma_rdc_rcr_qlen_get(handle, channel, &qlen); 1328 RXDMA_REG_READ64(handle, RDC_RCR_TAIL, channel, &rcr_tail_reg.value); 1329 rcr_tail = rcr_tail_reg.bits.tail; 1330 1331 if (!qlen) { 1332 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1333 "<== hxge_rx_pkts:rcr channel %d qlen %d (no pkts)", 1334 channel, qlen)); 1335 return (NULL); 1336 } 1337 1338 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_pkts:rcr channel %d " 1339 "qlen %d", channel, qlen)); 1340 1341 comp_rd_index = rcr_p->comp_rd_index; 1342 1343 rcr_desc_rd_head_p = rcr_p->rcr_desc_rd_head_p; 1344 rcr_desc_rd_head_pp = rcr_p->rcr_desc_rd_head_pp; 1345 nrcr_read = npkt_read = 0; 1346 1347 /* 1348 * Number of packets queued (The jumbo or multi packet will be counted 1349 * as only one paccket and it may take up more than one completion 1350 * entry). 1351 */ 1352 qlen_hw = (qlen < hxge_max_rx_pkts) ? qlen : hxge_max_rx_pkts; 1353 head_mp = NULL; 1354 tail_mp = &head_mp; 1355 nmp = mp_cont = NULL; 1356 multi = B_FALSE; 1357 1358 rcr_head_index = rcr_p->rcr_desc_rd_head_p - rcr_p->rcr_desc_first_p; 1359 rcr_tail_index = rcr_tail - rcr_p->rcr_tail_begin; 1360 1361 if (rcr_tail_index >= rcr_head_index) { 1362 qlen_sw = rcr_tail_index - rcr_head_index; 1363 } else { 1364 /* rcr_tail has wrapped around */ 1365 qlen_sw = (rcr_p->comp_size - rcr_head_index) + rcr_tail_index; 1366 } 1367 1368 if (qlen_hw > qlen_sw) { 1369 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1370 "Channel %d, rcr_qlen from reg %d and from rcr_tail %d\n", 1371 channel, qlen_hw, qlen_sw)); 1372 qlen_hw = qlen_sw; 1373 } 1374 1375 while (qlen_hw) { 1376 #ifdef HXGE_DEBUG 1377 hxge_dump_rcr_entry(hxgep, rcr_desc_rd_head_p); 1378 #endif 1379 /* 1380 * Process one completion ring entry. 1381 */ 1382 invalid_rcr_entry = 0; 1383 hxge_receive_packet(hxgep, 1384 rcr_p, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont, 1385 &invalid_rcr_entry); 1386 if (invalid_rcr_entry != 0) { 1387 rdc_stats = rcr_p->rdc_stats; 1388 rdc_stats->rcr_invalids++; 1389 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1390 "Channel %d could only read 0x%x packets, " 1391 "but 0x%x pending\n", channel, npkt_read, qlen_hw)); 1392 break; 1393 } 1394 1395 /* 1396 * message chaining modes (nemo msg chaining) 1397 */ 1398 if (nmp) { 1399 nmp->b_next = NULL; 1400 if (!multi && !mp_cont) { /* frame fits a partition */ 1401 *tail_mp = nmp; 1402 tail_mp = &nmp->b_next; 1403 nmp = NULL; 1404 } else if (multi && !mp_cont) { /* first segment */ 1405 *tail_mp = nmp; 1406 tail_mp = &nmp->b_cont; 1407 } else if (multi && mp_cont) { /* mid of multi segs */ 1408 *tail_mp = mp_cont; 1409 tail_mp = &mp_cont->b_cont; 1410 } else if (!multi && mp_cont) { /* last segment */ 1411 *tail_mp = mp_cont; 1412 tail_mp = &nmp->b_next; 1413 nmp = NULL; 1414 } 1415 } 1416 1417 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1418 "==> hxge_rx_pkts: loop: rcr channel %d " 1419 "before updating: multi %d " 1420 "nrcr_read %d " 1421 "npk read %d " 1422 "head_pp $%p index %d ", 1423 channel, multi, 1424 nrcr_read, npkt_read, rcr_desc_rd_head_pp, comp_rd_index)); 1425 1426 if (!multi) { 1427 qlen_hw--; 1428 npkt_read++; 1429 } 1430 1431 /* 1432 * Update the next read entry. 1433 */ 1434 comp_rd_index = NEXT_ENTRY(comp_rd_index, 1435 rcr_p->comp_wrap_mask); 1436 1437 rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p, 1438 rcr_p->rcr_desc_first_p, rcr_p->rcr_desc_last_p); 1439 1440 nrcr_read++; 1441 1442 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1443 "<== hxge_rx_pkts: (SAM, process one packet) " 1444 "nrcr_read %d", nrcr_read)); 1445 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1446 "==> hxge_rx_pkts: loop: rcr channel %d " 1447 "multi %d nrcr_read %d npk read %d head_pp $%p index %d ", 1448 channel, multi, nrcr_read, npkt_read, rcr_desc_rd_head_pp, 1449 comp_rd_index)); 1450 } 1451 1452 rcr_p->rcr_desc_rd_head_pp = rcr_desc_rd_head_pp; 1453 rcr_p->comp_rd_index = comp_rd_index; 1454 rcr_p->rcr_desc_rd_head_p = rcr_desc_rd_head_p; 1455 1456 /* Adjust the mailbox queue length for a hardware bug workaround */ 1457 mboxp->rcrstat_a.bits.qlen -= npkt_read; 1458 1459 if ((hxgep->intr_timeout != rcr_p->intr_timeout) || 1460 (hxgep->intr_threshold != rcr_p->intr_threshold)) { 1461 rcr_p->intr_timeout = hxgep->intr_timeout; 1462 rcr_p->intr_threshold = hxgep->intr_threshold; 1463 rcr_cfg_b.value = 0x0ULL; 1464 if (rcr_p->intr_timeout) 1465 rcr_cfg_b.bits.entout = 1; 1466 rcr_cfg_b.bits.timeout = rcr_p->intr_timeout; 1467 rcr_cfg_b.bits.pthres = rcr_p->intr_threshold; 1468 RXDMA_REG_WRITE64(handle, RDC_RCR_CFG_B, 1469 channel, rcr_cfg_b.value); 1470 } 1471 1472 cs.bits.pktread = npkt_read; 1473 cs.bits.ptrread = nrcr_read; 1474 value = cs.value; 1475 cs.value &= 0xffffffffULL; 1476 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); 1477 1478 cs.value = value & ~0xffffffffULL; 1479 cs.bits.pktread = 0; 1480 cs.bits.ptrread = 0; 1481 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); 1482 1483 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1484 "==> hxge_rx_pkts: EXIT: rcr channel %d " 1485 "head_pp $%p index %016llx ", 1486 channel, rcr_p->rcr_desc_rd_head_pp, rcr_p->comp_rd_index)); 1487 1488 /* 1489 * Update RCR buffer pointer read and number of packets read. 1490 */ 1491 1492 *rcrp = rcr_p; 1493 1494 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "<== hxge_rx_pkts")); 1495 1496 return (head_mp); 1497 } 1498 1499 #define RCR_ENTRY_PATTERN 0x5a5a6b6b7c7c8d8dULL 1500 1501 /*ARGSUSED*/ 1502 void 1503 hxge_receive_packet(p_hxge_t hxgep, 1504 p_rx_rcr_ring_t rcr_p, p_rcr_entry_t rcr_desc_rd_head_p, 1505 boolean_t *multi_p, mblk_t **mp, mblk_t **mp_cont, 1506 uint32_t *invalid_rcr_entry) 1507 { 1508 p_mblk_t nmp = NULL; 1509 uint64_t multi; 1510 uint8_t channel; 1511 1512 boolean_t first_entry = B_TRUE; 1513 boolean_t is_tcp_udp = B_FALSE; 1514 boolean_t buffer_free = B_FALSE; 1515 boolean_t error_send_up = B_FALSE; 1516 uint8_t error_type; 1517 uint16_t l2_len; 1518 uint16_t skip_len; 1519 uint8_t pktbufsz_type; 1520 uint64_t rcr_entry; 1521 uint64_t *pkt_buf_addr_pp; 1522 uint64_t *pkt_buf_addr_p; 1523 uint32_t buf_offset; 1524 uint32_t bsize; 1525 uint32_t msg_index; 1526 p_rx_rbr_ring_t rx_rbr_p; 1527 p_rx_msg_t *rx_msg_ring_p; 1528 p_rx_msg_t rx_msg_p; 1529 1530 uint16_t sw_offset_bytes = 0, hdr_size = 0; 1531 hxge_status_t status = HXGE_OK; 1532 boolean_t is_valid = B_FALSE; 1533 p_hxge_rx_ring_stats_t rdc_stats; 1534 uint32_t bytes_read; 1535 1536 uint64_t pkt_type; 1537 1538 channel = rcr_p->rdc; 1539 1540 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> hxge_receive_packet")); 1541 1542 first_entry = (*mp == NULL) ? B_TRUE : B_FALSE; 1543 rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); 1544 1545 /* Verify the content of the rcr_entry for a hardware bug workaround */ 1546 if ((rcr_entry == 0x0) || (rcr_entry == RCR_ENTRY_PATTERN)) { 1547 *invalid_rcr_entry = 1; 1548 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "hxge_receive_packet " 1549 "Channel %d invalid RCR entry 0x%llx found, returning\n", 1550 channel, (long long) rcr_entry)); 1551 return; 1552 } 1553 *((uint64_t *)rcr_desc_rd_head_p) = RCR_ENTRY_PATTERN; 1554 1555 multi = (rcr_entry & RCR_MULTI_MASK); 1556 pkt_type = (rcr_entry & RCR_PKT_TYPE_MASK); 1557 1558 error_type = ((rcr_entry & RCR_ERROR_MASK) >> RCR_ERROR_SHIFT); 1559 l2_len = ((rcr_entry & RCR_L2_LEN_MASK) >> RCR_L2_LEN_SHIFT); 1560 1561 /* 1562 * Hardware does not strip the CRC due bug ID 11451 where 1563 * the hardware mis handles minimum size packets. 1564 */ 1565 l2_len -= ETHERFCSL; 1566 1567 pktbufsz_type = ((rcr_entry & RCR_PKTBUFSZ_MASK) >> 1568 RCR_PKTBUFSZ_SHIFT); 1569 #if defined(__i386) 1570 pkt_buf_addr_pp = (uint64_t *)(uint32_t)((rcr_entry & 1571 RCR_PKT_BUF_ADDR_MASK) << RCR_PKT_BUF_ADDR_SHIFT); 1572 #else 1573 pkt_buf_addr_pp = (uint64_t *)((rcr_entry & RCR_PKT_BUF_ADDR_MASK) << 1574 RCR_PKT_BUF_ADDR_SHIFT); 1575 #endif 1576 1577 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1578 "==> hxge_receive_packet: entryp $%p entry 0x%0llx " 1579 "pkt_buf_addr_pp $%p l2_len %d multi %d " 1580 "error_type 0x%x pkt_type 0x%x " 1581 "pktbufsz_type %d ", 1582 rcr_desc_rd_head_p, rcr_entry, pkt_buf_addr_pp, l2_len, 1583 multi, error_type, pkt_type, pktbufsz_type)); 1584 1585 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1586 "==> hxge_receive_packet: entryp $%p entry 0x%0llx " 1587 "pkt_buf_addr_pp $%p l2_len %d multi %d " 1588 "error_type 0x%x pkt_type 0x%x ", rcr_desc_rd_head_p, 1589 rcr_entry, pkt_buf_addr_pp, l2_len, multi, error_type, pkt_type)); 1590 1591 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1592 "==> (rbr) hxge_receive_packet: entry 0x%0llx " 1593 "full pkt_buf_addr_pp $%p l2_len %d", 1594 rcr_entry, pkt_buf_addr_pp, l2_len)); 1595 1596 /* get the stats ptr */ 1597 rdc_stats = rcr_p->rdc_stats; 1598 1599 if (!l2_len) { 1600 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1601 "<== hxge_receive_packet: failed: l2 length is 0.")); 1602 return; 1603 } 1604 1605 /* shift 6 bits to get the full io address */ 1606 #if defined(__i386) 1607 pkt_buf_addr_pp = (uint64_t *)((uint32_t)pkt_buf_addr_pp << 1608 RCR_PKT_BUF_ADDR_SHIFT_FULL); 1609 #else 1610 pkt_buf_addr_pp = (uint64_t *)((uint64_t)pkt_buf_addr_pp << 1611 RCR_PKT_BUF_ADDR_SHIFT_FULL); 1612 #endif 1613 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1614 "==> (rbr) hxge_receive_packet: entry 0x%0llx " 1615 "full pkt_buf_addr_pp $%p l2_len %d", 1616 rcr_entry, pkt_buf_addr_pp, l2_len)); 1617 1618 rx_rbr_p = rcr_p->rx_rbr_p; 1619 rx_msg_ring_p = rx_rbr_p->rx_msg_ring; 1620 1621 if (first_entry) { 1622 hdr_size = (rcr_p->full_hdr_flag ? RXDMA_HDR_SIZE_FULL : 1623 RXDMA_HDR_SIZE_DEFAULT); 1624 1625 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1626 "==> hxge_receive_packet: first entry 0x%016llx " 1627 "pkt_buf_addr_pp $%p l2_len %d hdr %d", 1628 rcr_entry, pkt_buf_addr_pp, l2_len, hdr_size)); 1629 } 1630 1631 MUTEX_ENTER(&rcr_p->lock); 1632 MUTEX_ENTER(&rx_rbr_p->lock); 1633 1634 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1635 "==> (rbr 1) hxge_receive_packet: entry 0x%0llx " 1636 "full pkt_buf_addr_pp $%p l2_len %d", 1637 rcr_entry, pkt_buf_addr_pp, l2_len)); 1638 1639 /* 1640 * Packet buffer address in the completion entry points to the starting 1641 * buffer address (offset 0). Use the starting buffer address to locate 1642 * the corresponding kernel address. 1643 */ 1644 status = hxge_rxbuf_pp_to_vp(hxgep, rx_rbr_p, 1645 pktbufsz_type, pkt_buf_addr_pp, &pkt_buf_addr_p, 1646 &buf_offset, &msg_index); 1647 1648 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1649 "==> (rbr 2) hxge_receive_packet: entry 0x%0llx " 1650 "full pkt_buf_addr_pp $%p l2_len %d", 1651 rcr_entry, pkt_buf_addr_pp, l2_len)); 1652 1653 if (status != HXGE_OK) { 1654 MUTEX_EXIT(&rx_rbr_p->lock); 1655 MUTEX_EXIT(&rcr_p->lock); 1656 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1657 "<== hxge_receive_packet: found vaddr failed %d", status)); 1658 return; 1659 } 1660 1661 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1662 "==> (rbr 3) hxge_receive_packet: entry 0x%0llx " 1663 "full pkt_buf_addr_pp $%p l2_len %d", 1664 rcr_entry, pkt_buf_addr_pp, l2_len)); 1665 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1666 "==> (rbr 4 msgindex %d) hxge_receive_packet: entry 0x%0llx " 1667 "full pkt_buf_addr_pp $%p l2_len %d", 1668 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 1669 1670 if (msg_index >= rx_rbr_p->tnblocks) { 1671 MUTEX_EXIT(&rx_rbr_p->lock); 1672 MUTEX_EXIT(&rcr_p->lock); 1673 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1674 "==> hxge_receive_packet: FATAL msg_index (%d) " 1675 "should be smaller than tnblocks (%d)\n", 1676 msg_index, rx_rbr_p->tnblocks)); 1677 return; 1678 } 1679 1680 rx_msg_p = rx_msg_ring_p[msg_index]; 1681 1682 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1683 "==> (rbr 4 msgindex %d) hxge_receive_packet: entry 0x%0llx " 1684 "full pkt_buf_addr_pp $%p l2_len %d", 1685 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 1686 1687 switch (pktbufsz_type) { 1688 case RCR_PKTBUFSZ_0: 1689 bsize = rx_rbr_p->pkt_buf_size0_bytes; 1690 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1691 "==> hxge_receive_packet: 0 buf %d", bsize)); 1692 break; 1693 case RCR_PKTBUFSZ_1: 1694 bsize = rx_rbr_p->pkt_buf_size1_bytes; 1695 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1696 "==> hxge_receive_packet: 1 buf %d", bsize)); 1697 break; 1698 case RCR_PKTBUFSZ_2: 1699 bsize = rx_rbr_p->pkt_buf_size2_bytes; 1700 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1701 "==> hxge_receive_packet: 2 buf %d", bsize)); 1702 break; 1703 case RCR_SINGLE_BLOCK: 1704 bsize = rx_msg_p->block_size; 1705 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1706 "==> hxge_receive_packet: single %d", bsize)); 1707 1708 break; 1709 default: 1710 MUTEX_EXIT(&rx_rbr_p->lock); 1711 MUTEX_EXIT(&rcr_p->lock); 1712 return; 1713 } 1714 1715 DMA_COMMON_SYNC_OFFSET(rx_msg_p->buf_dma, 1716 (buf_offset + sw_offset_bytes), (hdr_size + l2_len), 1717 DDI_DMA_SYNC_FORCPU); 1718 1719 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1720 "==> hxge_receive_packet: after first dump:usage count")); 1721 1722 if (rx_msg_p->cur_usage_cnt == 0) { 1723 if (rx_rbr_p->rbr_use_bcopy) { 1724 atomic_inc_32(&rx_rbr_p->rbr_consumed); 1725 if (rx_rbr_p->rbr_consumed < 1726 rx_rbr_p->rbr_threshold_hi) { 1727 if (rx_rbr_p->rbr_threshold_lo == 0 || 1728 ((rx_rbr_p->rbr_consumed >= 1729 rx_rbr_p->rbr_threshold_lo) && 1730 (rx_rbr_p->rbr_bufsize_type >= 1731 pktbufsz_type))) { 1732 rx_msg_p->rx_use_bcopy = B_TRUE; 1733 } 1734 } else { 1735 rx_msg_p->rx_use_bcopy = B_TRUE; 1736 } 1737 } 1738 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1739 "==> hxge_receive_packet: buf %d (new block) ", bsize)); 1740 1741 rx_msg_p->pkt_buf_size_code = pktbufsz_type; 1742 rx_msg_p->pkt_buf_size = bsize; 1743 rx_msg_p->cur_usage_cnt = 1; 1744 if (pktbufsz_type == RCR_SINGLE_BLOCK) { 1745 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1746 "==> hxge_receive_packet: buf %d (single block) ", 1747 bsize)); 1748 /* 1749 * Buffer can be reused once the free function is 1750 * called. 1751 */ 1752 rx_msg_p->max_usage_cnt = 1; 1753 buffer_free = B_TRUE; 1754 } else { 1755 rx_msg_p->max_usage_cnt = rx_msg_p->block_size / bsize; 1756 if (rx_msg_p->max_usage_cnt == 1) { 1757 buffer_free = B_TRUE; 1758 } 1759 } 1760 } else { 1761 rx_msg_p->cur_usage_cnt++; 1762 if (rx_msg_p->cur_usage_cnt == rx_msg_p->max_usage_cnt) { 1763 buffer_free = B_TRUE; 1764 } 1765 } 1766 1767 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1768 "msgbuf index = %d l2len %d bytes usage %d max_usage %d ", 1769 msg_index, l2_len, 1770 rx_msg_p->cur_usage_cnt, rx_msg_p->max_usage_cnt)); 1771 1772 if (error_type) { 1773 rdc_stats->ierrors++; 1774 /* Update error stats */ 1775 rdc_stats->errlog.compl_err_type = error_type; 1776 HXGE_FM_REPORT_ERROR(hxgep, NULL, HXGE_FM_EREPORT_RDMC_RCR_ERR); 1777 1778 if (error_type & RCR_CTRL_FIFO_DED) { 1779 rdc_stats->ctrl_fifo_ecc_err++; 1780 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1781 " hxge_receive_packet: " 1782 " channel %d RCR ctrl_fifo_ded error", channel)); 1783 } else if (error_type & RCR_DATA_FIFO_DED) { 1784 rdc_stats->data_fifo_ecc_err++; 1785 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1786 " hxge_receive_packet: channel %d" 1787 " RCR data_fifo_ded error", channel)); 1788 } 1789 1790 /* 1791 * Update and repost buffer block if max usage count is 1792 * reached. 1793 */ 1794 if (error_send_up == B_FALSE) { 1795 atomic_inc_32(&rx_msg_p->ref_cnt); 1796 if (buffer_free == B_TRUE) { 1797 rx_msg_p->free = B_TRUE; 1798 } 1799 1800 MUTEX_EXIT(&rx_rbr_p->lock); 1801 MUTEX_EXIT(&rcr_p->lock); 1802 hxge_freeb(rx_msg_p); 1803 return; 1804 } 1805 } 1806 1807 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1808 "==> hxge_receive_packet: DMA sync second ")); 1809 1810 bytes_read = rcr_p->rcvd_pkt_bytes; 1811 skip_len = sw_offset_bytes + hdr_size; 1812 if (!rx_msg_p->rx_use_bcopy) { 1813 /* 1814 * For loaned up buffers, the driver reference count 1815 * will be incremented first and then the free state. 1816 */ 1817 if ((nmp = hxge_dupb(rx_msg_p, buf_offset, bsize)) != NULL) { 1818 if (first_entry) { 1819 nmp->b_rptr = &nmp->b_rptr[skip_len]; 1820 if (l2_len < bsize - skip_len) { 1821 nmp->b_wptr = &nmp->b_rptr[l2_len]; 1822 } else { 1823 nmp->b_wptr = &nmp->b_rptr[bsize 1824 - skip_len]; 1825 } 1826 } else { 1827 if (l2_len - bytes_read < bsize) { 1828 nmp->b_wptr = 1829 &nmp->b_rptr[l2_len - bytes_read]; 1830 } else { 1831 nmp->b_wptr = &nmp->b_rptr[bsize]; 1832 } 1833 } 1834 } 1835 } else { 1836 if (first_entry) { 1837 nmp = hxge_dupb_bcopy(rx_msg_p, buf_offset + skip_len, 1838 l2_len < bsize - skip_len ? 1839 l2_len : bsize - skip_len); 1840 } else { 1841 nmp = hxge_dupb_bcopy(rx_msg_p, buf_offset, 1842 l2_len - bytes_read < bsize ? 1843 l2_len - bytes_read : bsize); 1844 } 1845 } 1846 1847 if (nmp != NULL) { 1848 if (first_entry) 1849 bytes_read = nmp->b_wptr - nmp->b_rptr; 1850 else 1851 bytes_read += nmp->b_wptr - nmp->b_rptr; 1852 1853 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1854 "==> hxge_receive_packet after dupb: " 1855 "rbr consumed %d " 1856 "pktbufsz_type %d " 1857 "nmp $%p rptr $%p wptr $%p " 1858 "buf_offset %d bzise %d l2_len %d skip_len %d", 1859 rx_rbr_p->rbr_consumed, 1860 pktbufsz_type, 1861 nmp, nmp->b_rptr, nmp->b_wptr, 1862 buf_offset, bsize, l2_len, skip_len)); 1863 } else { 1864 cmn_err(CE_WARN, "!hxge_receive_packet: update stats (error)"); 1865 1866 atomic_inc_32(&rx_msg_p->ref_cnt); 1867 if (buffer_free == B_TRUE) { 1868 rx_msg_p->free = B_TRUE; 1869 } 1870 1871 MUTEX_EXIT(&rx_rbr_p->lock); 1872 MUTEX_EXIT(&rcr_p->lock); 1873 hxge_freeb(rx_msg_p); 1874 return; 1875 } 1876 1877 if (buffer_free == B_TRUE) { 1878 rx_msg_p->free = B_TRUE; 1879 } 1880 1881 /* 1882 * ERROR, FRAG and PKT_TYPE are only reported in the first entry. If a 1883 * packet is not fragmented and no error bit is set, then L4 checksum 1884 * is OK. 1885 */ 1886 is_valid = (nmp != NULL); 1887 if (first_entry) { 1888 rdc_stats->ipackets++; /* count only 1st seg for jumbo */ 1889 if (l2_len > (STD_FRAME_SIZE - ETHERFCSL)) 1890 rdc_stats->jumbo_pkts++; 1891 rdc_stats->ibytes += skip_len + l2_len < bsize ? 1892 l2_len : bsize; 1893 } else { 1894 /* 1895 * Add the current portion of the packet to the kstats. 1896 * The current portion of the packet is calculated by using 1897 * length of the packet and the previously received portion. 1898 */ 1899 rdc_stats->ibytes += l2_len - rcr_p->rcvd_pkt_bytes < bsize ? 1900 l2_len - rcr_p->rcvd_pkt_bytes : bsize; 1901 } 1902 1903 rcr_p->rcvd_pkt_bytes = bytes_read; 1904 1905 if (rx_msg_p->free && rx_msg_p->rx_use_bcopy) { 1906 atomic_inc_32(&rx_msg_p->ref_cnt); 1907 MUTEX_EXIT(&rx_rbr_p->lock); 1908 MUTEX_EXIT(&rcr_p->lock); 1909 hxge_freeb(rx_msg_p); 1910 } else { 1911 MUTEX_EXIT(&rx_rbr_p->lock); 1912 MUTEX_EXIT(&rcr_p->lock); 1913 } 1914 1915 if (is_valid) { 1916 nmp->b_cont = NULL; 1917 if (first_entry) { 1918 *mp = nmp; 1919 *mp_cont = NULL; 1920 } else { 1921 *mp_cont = nmp; 1922 } 1923 } 1924 1925 /* 1926 * Update stats and hardware checksuming. 1927 */ 1928 if (is_valid && !multi) { 1929 is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP || 1930 pkt_type == RCR_PKT_IS_UDP) ? B_TRUE : B_FALSE); 1931 1932 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_receive_packet: " 1933 "is_valid 0x%x multi %d pkt %d d error %d", 1934 is_valid, multi, is_tcp_udp, error_type)); 1935 1936 if (is_tcp_udp && !error_type) { 1937 (void) hcksum_assoc(nmp, NULL, NULL, 0, 0, 0, 0, 1938 HCK_FULLCKSUM_OK | HCK_FULLCKSUM, 0); 1939 1940 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1941 "==> hxge_receive_packet: Full tcp/udp cksum " 1942 "is_valid 0x%x multi %d pkt %d " 1943 "error %d", 1944 is_valid, multi, is_tcp_udp, error_type)); 1945 } 1946 } 1947 1948 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1949 "==> hxge_receive_packet: *mp 0x%016llx", *mp)); 1950 1951 *multi_p = (multi == RCR_MULTI_MASK); 1952 1953 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_receive_packet: " 1954 "multi %d nmp 0x%016llx *mp 0x%016llx *mp_cont 0x%016llx", 1955 *multi_p, nmp, *mp, *mp_cont)); 1956 } 1957 1958 /*ARGSUSED*/ 1959 static hxge_status_t 1960 hxge_rx_err_evnts(p_hxge_t hxgep, uint_t index, p_hxge_ldv_t ldvp, 1961 rdc_stat_t cs) 1962 { 1963 p_hxge_rx_ring_stats_t rdc_stats; 1964 hpi_handle_t handle; 1965 boolean_t rxchan_fatal = B_FALSE; 1966 uint8_t channel; 1967 hxge_status_t status = HXGE_OK; 1968 uint64_t cs_val; 1969 1970 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_rx_err_evnts")); 1971 1972 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1973 channel = ldvp->channel; 1974 1975 /* Clear the interrupts */ 1976 cs.bits.pktread = 0; 1977 cs.bits.ptrread = 0; 1978 cs_val = cs.value & RDC_STAT_WR1C; 1979 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs_val); 1980 1981 rdc_stats = &hxgep->statsp->rdc_stats[ldvp->vdma_index]; 1982 1983 if (cs.bits.rbr_cpl_to) { 1984 rdc_stats->rbr_tmout++; 1985 HXGE_FM_REPORT_ERROR(hxgep, channel, 1986 HXGE_FM_EREPORT_RDMC_RBR_CPL_TO); 1987 rxchan_fatal = B_TRUE; 1988 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1989 "==> hxge_rx_err_evnts(channel %d): " 1990 "fatal error: rx_rbr_timeout", channel)); 1991 } 1992 1993 if ((cs.bits.rcr_shadow_par_err) || (cs.bits.rbr_prefetch_par_err)) { 1994 (void) hpi_rxdma_ring_perr_stat_get(handle, 1995 &rdc_stats->errlog.pre_par, &rdc_stats->errlog.sha_par); 1996 } 1997 1998 if (cs.bits.rcr_shadow_par_err) { 1999 rdc_stats->rcr_sha_par++; 2000 HXGE_FM_REPORT_ERROR(hxgep, channel, 2001 HXGE_FM_EREPORT_RDMC_RCR_SHA_PAR); 2002 rxchan_fatal = B_TRUE; 2003 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2004 "==> hxge_rx_err_evnts(channel %d): " 2005 "fatal error: rcr_shadow_par_err", channel)); 2006 } 2007 2008 if (cs.bits.rbr_prefetch_par_err) { 2009 rdc_stats->rbr_pre_par++; 2010 HXGE_FM_REPORT_ERROR(hxgep, channel, 2011 HXGE_FM_EREPORT_RDMC_RBR_PRE_PAR); 2012 rxchan_fatal = B_TRUE; 2013 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2014 "==> hxge_rx_err_evnts(channel %d): " 2015 "fatal error: rbr_prefetch_par_err", channel)); 2016 } 2017 2018 if (cs.bits.rbr_pre_empty) { 2019 rdc_stats->rbr_pre_empty++; 2020 HXGE_FM_REPORT_ERROR(hxgep, channel, 2021 HXGE_FM_EREPORT_RDMC_RBR_PRE_EMPTY); 2022 rxchan_fatal = B_TRUE; 2023 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2024 "==> hxge_rx_err_evnts(channel %d): " 2025 "fatal error: rbr_pre_empty", channel)); 2026 } 2027 2028 if (cs.bits.peu_resp_err) { 2029 rdc_stats->peu_resp_err++; 2030 HXGE_FM_REPORT_ERROR(hxgep, channel, 2031 HXGE_FM_EREPORT_RDMC_PEU_RESP_ERR); 2032 rxchan_fatal = B_TRUE; 2033 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2034 "==> hxge_rx_err_evnts(channel %d): " 2035 "fatal error: peu_resp_err", channel)); 2036 } 2037 2038 if (cs.bits.rcr_thres) { 2039 rdc_stats->rcr_thres++; 2040 } 2041 2042 if (cs.bits.rcr_to) { 2043 rdc_stats->rcr_to++; 2044 } 2045 2046 if (cs.bits.rcr_shadow_full) { 2047 rdc_stats->rcr_shadow_full++; 2048 HXGE_FM_REPORT_ERROR(hxgep, channel, 2049 HXGE_FM_EREPORT_RDMC_RCR_SHA_FULL); 2050 rxchan_fatal = B_TRUE; 2051 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2052 "==> hxge_rx_err_evnts(channel %d): " 2053 "fatal error: rcr_shadow_full", channel)); 2054 } 2055 2056 if (cs.bits.rcr_full) { 2057 rdc_stats->rcrfull++; 2058 HXGE_FM_REPORT_ERROR(hxgep, channel, 2059 HXGE_FM_EREPORT_RDMC_RCRFULL); 2060 rxchan_fatal = B_TRUE; 2061 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2062 "==> hxge_rx_err_evnts(channel %d): " 2063 "fatal error: rcrfull error", channel)); 2064 } 2065 2066 if (cs.bits.rbr_empty) { 2067 rdc_stats->rbr_empty++; 2068 if (rdc_stats->rbr_empty == 1) 2069 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2070 "==> hxge_rx_err_evnts(channel %d): " 2071 "rbr empty error", channel)); 2072 /* 2073 * DMA channel is disabled due to rbr_empty bit is set 2074 * although it is not fatal. Enable the DMA channel here 2075 * to work-around the hardware bug. 2076 */ 2077 (void) hpi_rxdma_cfg_rdc_enable(handle, channel); 2078 } 2079 2080 if (cs.bits.rbr_full) { 2081 rdc_stats->rbrfull++; 2082 HXGE_FM_REPORT_ERROR(hxgep, channel, 2083 HXGE_FM_EREPORT_RDMC_RBRFULL); 2084 rxchan_fatal = B_TRUE; 2085 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2086 "==> hxge_rx_err_evnts(channel %d): " 2087 "fatal error: rbr_full error", channel)); 2088 } 2089 2090 if (rxchan_fatal) { 2091 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2092 " hxge_rx_err_evnts: fatal error on Channel #%d\n", 2093 channel)); 2094 status = hxge_rxdma_fatal_err_recover(hxgep, channel); 2095 if (status == HXGE_OK) { 2096 FM_SERVICE_RESTORED(hxgep); 2097 } 2098 } 2099 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_rx_err_evnts")); 2100 2101 return (status); 2102 } 2103 2104 static hxge_status_t 2105 hxge_map_rxdma(p_hxge_t hxgep) 2106 { 2107 int i, ndmas; 2108 uint16_t channel; 2109 p_rx_rbr_rings_t rx_rbr_rings; 2110 p_rx_rbr_ring_t *rbr_rings; 2111 p_rx_rcr_rings_t rx_rcr_rings; 2112 p_rx_rcr_ring_t *rcr_rings; 2113 p_rx_mbox_areas_t rx_mbox_areas_p; 2114 p_rx_mbox_t *rx_mbox_p; 2115 p_hxge_dma_pool_t dma_buf_poolp; 2116 p_hxge_dma_common_t *dma_buf_p; 2117 p_hxge_dma_pool_t dma_rbr_cntl_poolp; 2118 p_hxge_dma_common_t *dma_rbr_cntl_p; 2119 p_hxge_dma_pool_t dma_rcr_cntl_poolp; 2120 p_hxge_dma_common_t *dma_rcr_cntl_p; 2121 p_hxge_dma_pool_t dma_mbox_cntl_poolp; 2122 p_hxge_dma_common_t *dma_mbox_cntl_p; 2123 uint32_t *num_chunks; 2124 hxge_status_t status = HXGE_OK; 2125 2126 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_map_rxdma")); 2127 2128 dma_buf_poolp = hxgep->rx_buf_pool_p; 2129 dma_rbr_cntl_poolp = hxgep->rx_rbr_cntl_pool_p; 2130 dma_rcr_cntl_poolp = hxgep->rx_rcr_cntl_pool_p; 2131 dma_mbox_cntl_poolp = hxgep->rx_mbox_cntl_pool_p; 2132 2133 if (!dma_buf_poolp->buf_allocated || 2134 !dma_rbr_cntl_poolp->buf_allocated || 2135 !dma_rcr_cntl_poolp->buf_allocated || 2136 !dma_mbox_cntl_poolp->buf_allocated) { 2137 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2138 "<== hxge_map_rxdma: buf not allocated")); 2139 return (HXGE_ERROR); 2140 } 2141 2142 ndmas = dma_buf_poolp->ndmas; 2143 if (!ndmas) { 2144 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2145 "<== hxge_map_rxdma: no dma allocated")); 2146 return (HXGE_ERROR); 2147 } 2148 2149 num_chunks = dma_buf_poolp->num_chunks; 2150 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2151 dma_rbr_cntl_p = dma_rbr_cntl_poolp->dma_buf_pool_p; 2152 dma_rcr_cntl_p = dma_rcr_cntl_poolp->dma_buf_pool_p; 2153 dma_mbox_cntl_p = dma_mbox_cntl_poolp->dma_buf_pool_p; 2154 2155 rx_rbr_rings = (p_rx_rbr_rings_t) 2156 KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2157 rbr_rings = (p_rx_rbr_ring_t *)KMEM_ZALLOC( 2158 sizeof (p_rx_rbr_ring_t) * ndmas, KM_SLEEP); 2159 2160 rx_rcr_rings = (p_rx_rcr_rings_t) 2161 KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2162 rcr_rings = (p_rx_rcr_ring_t *)KMEM_ZALLOC( 2163 sizeof (p_rx_rcr_ring_t) * ndmas, KM_SLEEP); 2164 2165 rx_mbox_areas_p = (p_rx_mbox_areas_t) 2166 KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2167 rx_mbox_p = (p_rx_mbox_t *)KMEM_ZALLOC( 2168 sizeof (p_rx_mbox_t) * ndmas, KM_SLEEP); 2169 2170 /* 2171 * Timeout should be set based on the system clock divider. 2172 * The following timeout value of 1 assumes that the 2173 * granularity (1000) is 3 microseconds running at 300MHz. 2174 */ 2175 2176 hxgep->intr_threshold = RXDMA_RCR_PTHRES_DEFAULT; 2177 hxgep->intr_timeout = RXDMA_RCR_TO_DEFAULT; 2178 2179 /* 2180 * Map descriptors from the buffer polls for each dam channel. 2181 */ 2182 for (i = 0; i < ndmas; i++) { 2183 /* 2184 * Set up and prepare buffer blocks, descriptors and mailbox. 2185 */ 2186 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 2187 status = hxge_map_rxdma_channel(hxgep, channel, 2188 (p_hxge_dma_common_t *)&dma_buf_p[i], 2189 (p_rx_rbr_ring_t *)&rbr_rings[i], 2190 num_chunks[i], 2191 (p_hxge_dma_common_t *)&dma_rbr_cntl_p[i], 2192 (p_hxge_dma_common_t *)&dma_rcr_cntl_p[i], 2193 (p_hxge_dma_common_t *)&dma_mbox_cntl_p[i], 2194 (p_rx_rcr_ring_t *)&rcr_rings[i], 2195 (p_rx_mbox_t *)&rx_mbox_p[i]); 2196 if (status != HXGE_OK) { 2197 goto hxge_map_rxdma_fail1; 2198 } 2199 rbr_rings[i]->index = (uint16_t)i; 2200 rcr_rings[i]->index = (uint16_t)i; 2201 rcr_rings[i]->rdc_stats = &hxgep->statsp->rdc_stats[i]; 2202 } 2203 2204 rx_rbr_rings->ndmas = rx_rcr_rings->ndmas = ndmas; 2205 rx_rbr_rings->rbr_rings = rbr_rings; 2206 hxgep->rx_rbr_rings = rx_rbr_rings; 2207 rx_rcr_rings->rcr_rings = rcr_rings; 2208 hxgep->rx_rcr_rings = rx_rcr_rings; 2209 2210 rx_mbox_areas_p->rxmbox_areas = rx_mbox_p; 2211 hxgep->rx_mbox_areas_p = rx_mbox_areas_p; 2212 2213 goto hxge_map_rxdma_exit; 2214 2215 hxge_map_rxdma_fail1: 2216 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2217 "==> hxge_map_rxdma: unmap rbr,rcr (status 0x%x channel %d i %d)", 2218 status, channel, i)); 2219 i--; 2220 for (; i >= 0; i--) { 2221 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 2222 hxge_unmap_rxdma_channel(hxgep, channel, 2223 rbr_rings[i], rcr_rings[i], rx_mbox_p[i]); 2224 } 2225 2226 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2227 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2228 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2229 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2230 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2231 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2232 2233 hxge_map_rxdma_exit: 2234 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2235 "<== hxge_map_rxdma: (status 0x%x channel %d)", status, channel)); 2236 2237 return (status); 2238 } 2239 2240 static void 2241 hxge_unmap_rxdma(p_hxge_t hxgep) 2242 { 2243 int i, ndmas; 2244 uint16_t channel; 2245 p_rx_rbr_rings_t rx_rbr_rings; 2246 p_rx_rbr_ring_t *rbr_rings; 2247 p_rx_rcr_rings_t rx_rcr_rings; 2248 p_rx_rcr_ring_t *rcr_rings; 2249 p_rx_mbox_areas_t rx_mbox_areas_p; 2250 p_rx_mbox_t *rx_mbox_p; 2251 p_hxge_dma_pool_t dma_buf_poolp; 2252 p_hxge_dma_pool_t dma_rbr_cntl_poolp; 2253 p_hxge_dma_pool_t dma_rcr_cntl_poolp; 2254 p_hxge_dma_pool_t dma_mbox_cntl_poolp; 2255 p_hxge_dma_common_t *dma_buf_p; 2256 2257 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_unmap_rxdma")); 2258 2259 dma_buf_poolp = hxgep->rx_buf_pool_p; 2260 dma_rbr_cntl_poolp = hxgep->rx_rbr_cntl_pool_p; 2261 dma_rcr_cntl_poolp = hxgep->rx_rcr_cntl_pool_p; 2262 dma_mbox_cntl_poolp = hxgep->rx_mbox_cntl_pool_p; 2263 2264 if (!dma_buf_poolp->buf_allocated || 2265 !dma_rbr_cntl_poolp->buf_allocated || 2266 !dma_rcr_cntl_poolp->buf_allocated || 2267 !dma_mbox_cntl_poolp->buf_allocated) { 2268 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2269 "<== hxge_unmap_rxdma: NULL buf pointers")); 2270 return; 2271 } 2272 2273 rx_rbr_rings = hxgep->rx_rbr_rings; 2274 rx_rcr_rings = hxgep->rx_rcr_rings; 2275 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 2276 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2277 "<== hxge_unmap_rxdma: NULL pointers")); 2278 return; 2279 } 2280 2281 ndmas = rx_rbr_rings->ndmas; 2282 if (!ndmas) { 2283 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2284 "<== hxge_unmap_rxdma: no channel")); 2285 return; 2286 } 2287 2288 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2289 "==> hxge_unmap_rxdma (ndmas %d)", ndmas)); 2290 2291 rbr_rings = rx_rbr_rings->rbr_rings; 2292 rcr_rings = rx_rcr_rings->rcr_rings; 2293 rx_mbox_areas_p = hxgep->rx_mbox_areas_p; 2294 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 2295 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2296 2297 for (i = 0; i < ndmas; i++) { 2298 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 2299 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2300 "==> hxge_unmap_rxdma (ndmas %d) channel %d", 2301 ndmas, channel)); 2302 (void) hxge_unmap_rxdma_channel(hxgep, channel, 2303 (p_rx_rbr_ring_t)rbr_rings[i], 2304 (p_rx_rcr_ring_t)rcr_rings[i], 2305 (p_rx_mbox_t)rx_mbox_p[i]); 2306 } 2307 2308 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2309 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2310 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2311 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2312 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2313 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2314 2315 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_unmap_rxdma")); 2316 } 2317 2318 hxge_status_t 2319 hxge_map_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 2320 p_hxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 2321 uint32_t num_chunks, p_hxge_dma_common_t *dma_rbr_cntl_p, 2322 p_hxge_dma_common_t *dma_rcr_cntl_p, p_hxge_dma_common_t *dma_mbox_cntl_p, 2323 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 2324 { 2325 int status = HXGE_OK; 2326 2327 /* 2328 * Set up and prepare buffer blocks, descriptors and mailbox. 2329 */ 2330 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2331 "==> hxge_map_rxdma_channel (channel %d)", channel)); 2332 2333 /* 2334 * Receive buffer blocks 2335 */ 2336 status = hxge_map_rxdma_channel_buf_ring(hxgep, channel, 2337 dma_buf_p, rbr_p, num_chunks); 2338 if (status != HXGE_OK) { 2339 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2340 "==> hxge_map_rxdma_channel (channel %d): " 2341 "map buffer failed 0x%x", channel, status)); 2342 goto hxge_map_rxdma_channel_exit; 2343 } 2344 2345 /* 2346 * Receive block ring, completion ring and mailbox. 2347 */ 2348 status = hxge_map_rxdma_channel_cfg_ring(hxgep, channel, 2349 dma_rbr_cntl_p, dma_rcr_cntl_p, dma_mbox_cntl_p, 2350 rbr_p, rcr_p, rx_mbox_p); 2351 if (status != HXGE_OK) { 2352 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2353 "==> hxge_map_rxdma_channel (channel %d): " 2354 "map config failed 0x%x", channel, status)); 2355 goto hxge_map_rxdma_channel_fail2; 2356 } 2357 goto hxge_map_rxdma_channel_exit; 2358 2359 hxge_map_rxdma_channel_fail3: 2360 /* Free rbr, rcr */ 2361 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2362 "==> hxge_map_rxdma_channel: free rbr/rcr (status 0x%x channel %d)", 2363 status, channel)); 2364 hxge_unmap_rxdma_channel_cfg_ring(hxgep, *rcr_p, *rx_mbox_p); 2365 2366 hxge_map_rxdma_channel_fail2: 2367 /* Free buffer blocks */ 2368 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2369 "==> hxge_map_rxdma_channel: free rx buffers" 2370 "(hxgep 0x%x status 0x%x channel %d)", 2371 hxgep, status, channel)); 2372 hxge_unmap_rxdma_channel_buf_ring(hxgep, *rbr_p); 2373 2374 status = HXGE_ERROR; 2375 2376 hxge_map_rxdma_channel_exit: 2377 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2378 "<== hxge_map_rxdma_channel: (hxgep 0x%x status 0x%x channel %d)", 2379 hxgep, status, channel)); 2380 2381 return (status); 2382 } 2383 2384 /*ARGSUSED*/ 2385 static void 2386 hxge_unmap_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 2387 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 2388 { 2389 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2390 "==> hxge_unmap_rxdma_channel (channel %d)", channel)); 2391 2392 /* 2393 * unmap receive block ring, completion ring and mailbox. 2394 */ 2395 (void) hxge_unmap_rxdma_channel_cfg_ring(hxgep, rcr_p, rx_mbox_p); 2396 2397 /* unmap buffer blocks */ 2398 (void) hxge_unmap_rxdma_channel_buf_ring(hxgep, rbr_p); 2399 2400 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_unmap_rxdma_channel")); 2401 } 2402 2403 /*ARGSUSED*/ 2404 static hxge_status_t 2405 hxge_map_rxdma_channel_cfg_ring(p_hxge_t hxgep, uint16_t dma_channel, 2406 p_hxge_dma_common_t *dma_rbr_cntl_p, p_hxge_dma_common_t *dma_rcr_cntl_p, 2407 p_hxge_dma_common_t *dma_mbox_cntl_p, p_rx_rbr_ring_t *rbr_p, 2408 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 2409 { 2410 p_rx_rbr_ring_t rbrp; 2411 p_rx_rcr_ring_t rcrp; 2412 p_rx_mbox_t mboxp; 2413 p_hxge_dma_common_t cntl_dmap; 2414 p_hxge_dma_common_t dmap; 2415 p_rx_msg_t *rx_msg_ring; 2416 p_rx_msg_t rx_msg_p; 2417 rdc_rbr_cfg_a_t *rcfga_p; 2418 rdc_rbr_cfg_b_t *rcfgb_p; 2419 rdc_rcr_cfg_a_t *cfga_p; 2420 rdc_rcr_cfg_b_t *cfgb_p; 2421 rdc_rx_cfg1_t *cfig1_p; 2422 rdc_rx_cfg2_t *cfig2_p; 2423 rdc_rbr_kick_t *kick_p; 2424 uint32_t dmaaddrp; 2425 uint32_t *rbr_vaddrp; 2426 uint32_t bkaddr; 2427 hxge_status_t status = HXGE_OK; 2428 int i; 2429 uint32_t hxge_port_rcr_size; 2430 2431 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2432 "==> hxge_map_rxdma_channel_cfg_ring")); 2433 2434 cntl_dmap = *dma_rbr_cntl_p; 2435 2436 /* 2437 * Map in the receive block ring 2438 */ 2439 rbrp = *rbr_p; 2440 dmap = (p_hxge_dma_common_t)&rbrp->rbr_desc; 2441 hxge_setup_dma_common(dmap, cntl_dmap, rbrp->rbb_max, 4); 2442 2443 /* 2444 * Zero out buffer block ring descriptors. 2445 */ 2446 bzero((caddr_t)dmap->kaddrp, dmap->alength); 2447 2448 rcfga_p = &(rbrp->rbr_cfga); 2449 rcfgb_p = &(rbrp->rbr_cfgb); 2450 kick_p = &(rbrp->rbr_kick); 2451 rcfga_p->value = 0; 2452 rcfgb_p->value = 0; 2453 kick_p->value = 0; 2454 rbrp->rbr_addr = dmap->dma_cookie.dmac_laddress; 2455 rcfga_p->value = (rbrp->rbr_addr & 2456 (RBR_CFIG_A_STDADDR_MASK | RBR_CFIG_A_STDADDR_BASE_MASK)); 2457 rcfga_p->value |= ((uint64_t)rbrp->rbb_max << RBR_CFIG_A_LEN_SHIFT); 2458 2459 /* XXXX: how to choose packet buffer sizes */ 2460 rcfgb_p->bits.bufsz0 = rbrp->pkt_buf_size0; 2461 rcfgb_p->bits.vld0 = 1; 2462 rcfgb_p->bits.bufsz1 = rbrp->pkt_buf_size1; 2463 rcfgb_p->bits.vld1 = 1; 2464 rcfgb_p->bits.bufsz2 = rbrp->pkt_buf_size2; 2465 rcfgb_p->bits.vld2 = 1; 2466 rcfgb_p->bits.bksize = hxgep->rx_bksize_code; 2467 2468 /* 2469 * For each buffer block, enter receive block address to the ring. 2470 */ 2471 rbr_vaddrp = (uint32_t *)dmap->kaddrp; 2472 rbrp->rbr_desc_vp = (uint32_t *)dmap->kaddrp; 2473 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2474 "==> hxge_map_rxdma_channel_cfg_ring: channel %d " 2475 "rbr_vaddrp $%p", dma_channel, rbr_vaddrp)); 2476 2477 rx_msg_ring = rbrp->rx_msg_ring; 2478 for (i = 0; i < rbrp->tnblocks; i++) { 2479 rx_msg_p = rx_msg_ring[i]; 2480 rx_msg_p->hxgep = hxgep; 2481 rx_msg_p->rx_rbr_p = rbrp; 2482 bkaddr = (uint32_t) 2483 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 2484 RBR_BKADDR_SHIFT)); 2485 rx_msg_p->free = B_FALSE; 2486 rx_msg_p->max_usage_cnt = 0xbaddcafe; 2487 2488 *rbr_vaddrp++ = bkaddr; 2489 } 2490 2491 kick_p->bits.bkadd = rbrp->rbb_max; 2492 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 2493 2494 rbrp->rbr_rd_index = 0; 2495 2496 rbrp->rbr_consumed = 0; 2497 rbrp->rbr_use_bcopy = B_TRUE; 2498 rbrp->rbr_bufsize_type = RCR_PKTBUFSZ_0; 2499 2500 /* 2501 * Do bcopy on packets greater than bcopy size once the lo threshold is 2502 * reached. This lo threshold should be less than the hi threshold. 2503 * 2504 * Do bcopy on every packet once the hi threshold is reached. 2505 */ 2506 if (hxge_rx_threshold_lo >= hxge_rx_threshold_hi) { 2507 /* default it to use hi */ 2508 hxge_rx_threshold_lo = hxge_rx_threshold_hi; 2509 } 2510 if (hxge_rx_buf_size_type > HXGE_RBR_TYPE2) { 2511 hxge_rx_buf_size_type = HXGE_RBR_TYPE2; 2512 } 2513 rbrp->rbr_bufsize_type = hxge_rx_buf_size_type; 2514 2515 switch (hxge_rx_threshold_hi) { 2516 default: 2517 case HXGE_RX_COPY_NONE: 2518 /* Do not do bcopy at all */ 2519 rbrp->rbr_use_bcopy = B_FALSE; 2520 rbrp->rbr_threshold_hi = rbrp->rbb_max; 2521 break; 2522 2523 case HXGE_RX_COPY_1: 2524 case HXGE_RX_COPY_2: 2525 case HXGE_RX_COPY_3: 2526 case HXGE_RX_COPY_4: 2527 case HXGE_RX_COPY_5: 2528 case HXGE_RX_COPY_6: 2529 case HXGE_RX_COPY_7: 2530 rbrp->rbr_threshold_hi = 2531 rbrp->rbb_max * (hxge_rx_threshold_hi) / 2532 HXGE_RX_BCOPY_SCALE; 2533 break; 2534 2535 case HXGE_RX_COPY_ALL: 2536 rbrp->rbr_threshold_hi = 0; 2537 break; 2538 } 2539 2540 switch (hxge_rx_threshold_lo) { 2541 default: 2542 case HXGE_RX_COPY_NONE: 2543 /* Do not do bcopy at all */ 2544 if (rbrp->rbr_use_bcopy) { 2545 rbrp->rbr_use_bcopy = B_FALSE; 2546 } 2547 rbrp->rbr_threshold_lo = rbrp->rbb_max; 2548 break; 2549 2550 case HXGE_RX_COPY_1: 2551 case HXGE_RX_COPY_2: 2552 case HXGE_RX_COPY_3: 2553 case HXGE_RX_COPY_4: 2554 case HXGE_RX_COPY_5: 2555 case HXGE_RX_COPY_6: 2556 case HXGE_RX_COPY_7: 2557 rbrp->rbr_threshold_lo = 2558 rbrp->rbb_max * (hxge_rx_threshold_lo) / 2559 HXGE_RX_BCOPY_SCALE; 2560 break; 2561 2562 case HXGE_RX_COPY_ALL: 2563 rbrp->rbr_threshold_lo = 0; 2564 break; 2565 } 2566 2567 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2568 "hxge_map_rxdma_channel_cfg_ring: channel %d rbb_max %d " 2569 "rbrp->rbr_bufsize_type %d rbb_threshold_hi %d " 2570 "rbb_threshold_lo %d", 2571 dma_channel, rbrp->rbb_max, rbrp->rbr_bufsize_type, 2572 rbrp->rbr_threshold_hi, rbrp->rbr_threshold_lo)); 2573 2574 /* Map in the receive completion ring */ 2575 rcrp = (p_rx_rcr_ring_t)KMEM_ZALLOC(sizeof (rx_rcr_ring_t), KM_SLEEP); 2576 rcrp->rdc = dma_channel; 2577 2578 hxge_port_rcr_size = hxgep->hxge_port_rcr_size; 2579 rcrp->comp_size = hxge_port_rcr_size; 2580 rcrp->comp_wrap_mask = hxge_port_rcr_size - 1; 2581 2582 rcrp->max_receive_pkts = hxge_max_rx_pkts; 2583 2584 cntl_dmap = *dma_rcr_cntl_p; 2585 2586 dmap = (p_hxge_dma_common_t)&rcrp->rcr_desc; 2587 hxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size, 2588 sizeof (rcr_entry_t)); 2589 rcrp->comp_rd_index = 0; 2590 rcrp->comp_wt_index = 0; 2591 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 2592 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 2593 #if defined(__i386) 2594 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 2595 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 2596 #else 2597 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 2598 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 2599 #endif 2600 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 2601 (hxge_port_rcr_size - 1); 2602 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 2603 (hxge_port_rcr_size - 1); 2604 2605 rcrp->rcr_tail_begin = DMA_COMMON_IOADDR(rcrp->rcr_desc); 2606 rcrp->rcr_tail_begin = (rcrp->rcr_tail_begin & 0x7ffffULL) >> 3; 2607 2608 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2609 "==> hxge_map_rxdma_channel_cfg_ring: channel %d " 2610 "rbr_vaddrp $%p rcr_desc_rd_head_p $%p " 2611 "rcr_desc_rd_head_pp $%p rcr_desc_rd_last_p $%p " 2612 "rcr_desc_rd_last_pp $%p ", 2613 dma_channel, rbr_vaddrp, rcrp->rcr_desc_rd_head_p, 2614 rcrp->rcr_desc_rd_head_pp, rcrp->rcr_desc_last_p, 2615 rcrp->rcr_desc_last_pp)); 2616 2617 /* 2618 * Zero out buffer block ring descriptors. 2619 */ 2620 bzero((caddr_t)dmap->kaddrp, dmap->alength); 2621 rcrp->intr_timeout = hxgep->intr_timeout; 2622 rcrp->intr_threshold = hxgep->intr_threshold; 2623 rcrp->full_hdr_flag = B_FALSE; 2624 rcrp->sw_priv_hdr_len = 0; 2625 2626 cfga_p = &(rcrp->rcr_cfga); 2627 cfgb_p = &(rcrp->rcr_cfgb); 2628 cfga_p->value = 0; 2629 cfgb_p->value = 0; 2630 rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress; 2631 2632 cfga_p->value = (rcrp->rcr_addr & 2633 (RCRCFIG_A_STADDR_MASK | RCRCFIG_A_STADDR_BASE_MASK)); 2634 2635 cfga_p->value |= ((uint64_t)rcrp->comp_size << RCRCFIG_A_LEN_SHIF); 2636 2637 /* 2638 * Timeout should be set based on the system clock divider. The 2639 * following timeout value of 1 assumes that the granularity (1000) is 2640 * 3 microseconds running at 300MHz. 2641 */ 2642 cfgb_p->bits.pthres = rcrp->intr_threshold; 2643 cfgb_p->bits.timeout = rcrp->intr_timeout; 2644 cfgb_p->bits.entout = 1; 2645 2646 /* Map in the mailbox */ 2647 cntl_dmap = *dma_mbox_cntl_p; 2648 mboxp = (p_rx_mbox_t)KMEM_ZALLOC(sizeof (rx_mbox_t), KM_SLEEP); 2649 dmap = (p_hxge_dma_common_t)&mboxp->rx_mbox; 2650 hxge_setup_dma_common(dmap, cntl_dmap, 1, sizeof (rxdma_mailbox_t)); 2651 cfig1_p = (rdc_rx_cfg1_t *)&mboxp->rx_cfg1; 2652 cfig2_p = (rdc_rx_cfg2_t *)&mboxp->rx_cfg2; 2653 cfig1_p->value = cfig2_p->value = 0; 2654 2655 mboxp->mbox_addr = dmap->dma_cookie.dmac_laddress; 2656 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2657 "==> hxge_map_rxdma_channel_cfg_ring: " 2658 "channel %d cfg1 0x%016llx cfig2 0x%016llx cookie 0x%016llx", 2659 dma_channel, cfig1_p->value, cfig2_p->value, 2660 mboxp->mbox_addr)); 2661 2662 dmaaddrp = (uint32_t)((dmap->dma_cookie.dmac_laddress >> 32) & 0xfff); 2663 cfig1_p->bits.mbaddr_h = dmaaddrp; 2664 2665 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 0xffffffff); 2666 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 2667 RXDMA_CFIG2_MBADDR_L_MASK); 2668 2669 cfig2_p->bits.mbaddr_l = (dmaaddrp >> RXDMA_CFIG2_MBADDR_L_SHIFT); 2670 2671 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2672 "==> hxge_map_rxdma_channel_cfg_ring: channel %d damaddrp $%p " 2673 "cfg1 0x%016llx cfig2 0x%016llx", 2674 dma_channel, dmaaddrp, cfig1_p->value, cfig2_p->value)); 2675 2676 cfig2_p->bits.full_hdr = rcrp->full_hdr_flag; 2677 cfig2_p->bits.offset = rcrp->sw_priv_hdr_len; 2678 2679 rbrp->rx_rcr_p = rcrp; 2680 rcrp->rx_rbr_p = rbrp; 2681 *rcr_p = rcrp; 2682 *rx_mbox_p = mboxp; 2683 2684 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2685 "<== hxge_map_rxdma_channel_cfg_ring status 0x%08x", status)); 2686 return (status); 2687 } 2688 2689 /*ARGSUSED*/ 2690 static void 2691 hxge_unmap_rxdma_channel_cfg_ring(p_hxge_t hxgep, 2692 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 2693 { 2694 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2695 "==> hxge_unmap_rxdma_channel_cfg_ring: channel %d", rcr_p->rdc)); 2696 2697 KMEM_FREE(rcr_p, sizeof (rx_rcr_ring_t)); 2698 KMEM_FREE(rx_mbox_p, sizeof (rx_mbox_t)); 2699 2700 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2701 "<== hxge_unmap_rxdma_channel_cfg_ring")); 2702 } 2703 2704 static hxge_status_t 2705 hxge_map_rxdma_channel_buf_ring(p_hxge_t hxgep, uint16_t channel, 2706 p_hxge_dma_common_t *dma_buf_p, 2707 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks) 2708 { 2709 p_rx_rbr_ring_t rbrp; 2710 p_hxge_dma_common_t dma_bufp, tmp_bufp; 2711 p_rx_msg_t *rx_msg_ring; 2712 p_rx_msg_t rx_msg_p; 2713 p_mblk_t mblk_p; 2714 2715 rxring_info_t *ring_info; 2716 hxge_status_t status = HXGE_OK; 2717 int i, j, index; 2718 uint32_t size, bsize, nblocks, nmsgs; 2719 2720 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2721 "==> hxge_map_rxdma_channel_buf_ring: channel %d", channel)); 2722 2723 dma_bufp = tmp_bufp = *dma_buf_p; 2724 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2725 " hxge_map_rxdma_channel_buf_ring: channel %d to map %d " 2726 "chunks bufp 0x%016llx", channel, num_chunks, dma_bufp)); 2727 2728 nmsgs = 0; 2729 for (i = 0; i < num_chunks; i++, tmp_bufp++) { 2730 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2731 "==> hxge_map_rxdma_channel_buf_ring: channel %d " 2732 "bufp 0x%016llx nblocks %d nmsgs %d", 2733 channel, tmp_bufp, tmp_bufp->nblocks, nmsgs)); 2734 nmsgs += tmp_bufp->nblocks; 2735 } 2736 if (!nmsgs) { 2737 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2738 "<== hxge_map_rxdma_channel_buf_ring: channel %d " 2739 "no msg blocks", channel)); 2740 status = HXGE_ERROR; 2741 goto hxge_map_rxdma_channel_buf_ring_exit; 2742 } 2743 rbrp = (p_rx_rbr_ring_t)KMEM_ZALLOC(sizeof (rx_rbr_ring_t), KM_SLEEP); 2744 2745 size = nmsgs * sizeof (p_rx_msg_t); 2746 rx_msg_ring = KMEM_ZALLOC(size, KM_SLEEP); 2747 ring_info = (rxring_info_t *)KMEM_ZALLOC(sizeof (rxring_info_t), 2748 KM_SLEEP); 2749 2750 MUTEX_INIT(&rbrp->lock, NULL, MUTEX_DRIVER, 2751 (void *) hxgep->interrupt_cookie); 2752 MUTEX_INIT(&rbrp->post_lock, NULL, MUTEX_DRIVER, 2753 (void *) hxgep->interrupt_cookie); 2754 rbrp->rdc = channel; 2755 rbrp->num_blocks = num_chunks; 2756 rbrp->tnblocks = nmsgs; 2757 rbrp->rbb_max = nmsgs; 2758 rbrp->rbr_max_size = nmsgs; 2759 rbrp->rbr_wrap_mask = (rbrp->rbb_max - 1); 2760 2761 rbrp->pages_to_post = 0; 2762 rbrp->pages_to_skip = 20; 2763 rbrp->pages_to_post_threshold = rbrp->rbb_max - rbrp->pages_to_skip / 2; 2764 2765 /* 2766 * Buffer sizes suggested by NIU architect. 256, 512 and 2K. 2767 */ 2768 2769 rbrp->pkt_buf_size0 = RBR_BUFSZ0_256B; 2770 rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_256_BYTES; 2771 rbrp->hpi_pkt_buf_size0 = SIZE_256B; 2772 2773 rbrp->pkt_buf_size1 = RBR_BUFSZ1_1K; 2774 rbrp->pkt_buf_size1_bytes = RBR_BUFSZ1_1K_BYTES; 2775 rbrp->hpi_pkt_buf_size1 = SIZE_1KB; 2776 2777 rbrp->block_size = hxgep->rx_default_block_size; 2778 2779 if (!hxgep->param_arr[param_accept_jumbo].value) { 2780 rbrp->pkt_buf_size2 = RBR_BUFSZ2_2K; 2781 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_2K_BYTES; 2782 rbrp->hpi_pkt_buf_size2 = SIZE_2KB; 2783 } else { 2784 if (rbrp->block_size >= 0x2000) { 2785 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2786 "<== hxge_map_rxdma_channel_buf_ring: channel %d " 2787 "no msg blocks", channel)); 2788 status = HXGE_ERROR; 2789 goto hxge_map_rxdma_channel_buf_ring_fail1; 2790 } else { 2791 rbrp->pkt_buf_size2 = RBR_BUFSZ2_4K; 2792 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_4K_BYTES; 2793 rbrp->hpi_pkt_buf_size2 = SIZE_4KB; 2794 } 2795 } 2796 2797 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2798 "==> hxge_map_rxdma_channel_buf_ring: channel %d " 2799 "actual rbr max %d rbb_max %d nmsgs %d " 2800 "rbrp->block_size %d default_block_size %d " 2801 "(config hxge_rbr_size %d hxge_rbr_spare_size %d)", 2802 channel, rbrp->rbr_max_size, rbrp->rbb_max, nmsgs, 2803 rbrp->block_size, hxgep->rx_default_block_size, 2804 hxge_rbr_size, hxge_rbr_spare_size)); 2805 2806 /* 2807 * Map in buffers from the buffer pool. 2808 * Note that num_blocks is the num_chunks. For Sparc, there is likely 2809 * only one chunk. For x86, there will be many chunks. 2810 * Loop over chunks. 2811 */ 2812 index = 0; 2813 for (i = 0; i < rbrp->num_blocks; i++, dma_bufp++) { 2814 bsize = dma_bufp->block_size; 2815 nblocks = dma_bufp->nblocks; 2816 #if defined(__i386) 2817 ring_info->buffer[i].dvma_addr = (uint32_t)dma_bufp->ioaddr_pp; 2818 #else 2819 ring_info->buffer[i].dvma_addr = (uint64_t)dma_bufp->ioaddr_pp; 2820 #endif 2821 ring_info->buffer[i].buf_index = i; 2822 ring_info->buffer[i].buf_size = dma_bufp->alength; 2823 ring_info->buffer[i].start_index = index; 2824 #if defined(__i386) 2825 ring_info->buffer[i].kaddr = (uint32_t)dma_bufp->kaddrp; 2826 #else 2827 ring_info->buffer[i].kaddr = (uint64_t)dma_bufp->kaddrp; 2828 #endif 2829 2830 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2831 " hxge_map_rxdma_channel_buf_ring: map channel %d " 2832 "chunk %d nblocks %d chunk_size %x block_size 0x%x " 2833 "dma_bufp $%p dvma_addr $%p", channel, i, 2834 dma_bufp->nblocks, 2835 ring_info->buffer[i].buf_size, bsize, dma_bufp, 2836 ring_info->buffer[i].dvma_addr)); 2837 2838 /* loop over blocks within a chunk */ 2839 for (j = 0; j < nblocks; j++) { 2840 if ((rx_msg_p = hxge_allocb(bsize, BPRI_LO, 2841 dma_bufp)) == NULL) { 2842 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2843 "allocb failed (index %d i %d j %d)", 2844 index, i, j)); 2845 goto hxge_map_rxdma_channel_buf_ring_fail1; 2846 } 2847 rx_msg_ring[index] = rx_msg_p; 2848 rx_msg_p->block_index = index; 2849 rx_msg_p->shifted_addr = (uint32_t) 2850 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 2851 RBR_BKADDR_SHIFT)); 2852 /* 2853 * Too much output 2854 * HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2855 * "index %d j %d rx_msg_p $%p mblk %p", 2856 * index, j, rx_msg_p, rx_msg_p->rx_mblk_p)); 2857 */ 2858 mblk_p = rx_msg_p->rx_mblk_p; 2859 mblk_p->b_wptr = mblk_p->b_rptr + bsize; 2860 2861 rbrp->rbr_ref_cnt++; 2862 index++; 2863 rx_msg_p->buf_dma.dma_channel = channel; 2864 } 2865 } 2866 if (i < rbrp->num_blocks) { 2867 goto hxge_map_rxdma_channel_buf_ring_fail1; 2868 } 2869 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2870 "hxge_map_rxdma_channel_buf_ring: done buf init " 2871 "channel %d msg block entries %d", channel, index)); 2872 ring_info->block_size_mask = bsize - 1; 2873 rbrp->rx_msg_ring = rx_msg_ring; 2874 rbrp->dma_bufp = dma_buf_p; 2875 rbrp->ring_info = ring_info; 2876 2877 status = hxge_rxbuf_index_info_init(hxgep, rbrp); 2878 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, " hxge_map_rxdma_channel_buf_ring: " 2879 "channel %d done buf info init", channel)); 2880 2881 /* 2882 * Finally, permit hxge_freeb() to call hxge_post_page(). 2883 */ 2884 rbrp->rbr_state = RBR_POSTING; 2885 2886 *rbr_p = rbrp; 2887 2888 goto hxge_map_rxdma_channel_buf_ring_exit; 2889 2890 hxge_map_rxdma_channel_buf_ring_fail1: 2891 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2892 " hxge_map_rxdma_channel_buf_ring: failed channel (0x%x)", 2893 channel, status)); 2894 2895 index--; 2896 for (; index >= 0; index--) { 2897 rx_msg_p = rx_msg_ring[index]; 2898 if (rx_msg_p != NULL) { 2899 hxge_freeb(rx_msg_p); 2900 rx_msg_ring[index] = NULL; 2901 } 2902 } 2903 2904 hxge_map_rxdma_channel_buf_ring_fail: 2905 MUTEX_DESTROY(&rbrp->post_lock); 2906 MUTEX_DESTROY(&rbrp->lock); 2907 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 2908 KMEM_FREE(rx_msg_ring, size); 2909 KMEM_FREE(rbrp, sizeof (rx_rbr_ring_t)); 2910 2911 status = HXGE_ERROR; 2912 2913 hxge_map_rxdma_channel_buf_ring_exit: 2914 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2915 "<== hxge_map_rxdma_channel_buf_ring status 0x%08x", status)); 2916 2917 return (status); 2918 } 2919 2920 /*ARGSUSED*/ 2921 static void 2922 hxge_unmap_rxdma_channel_buf_ring(p_hxge_t hxgep, 2923 p_rx_rbr_ring_t rbr_p) 2924 { 2925 p_rx_msg_t *rx_msg_ring; 2926 p_rx_msg_t rx_msg_p; 2927 rxring_info_t *ring_info; 2928 int i; 2929 uint32_t size; 2930 2931 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2932 "==> hxge_unmap_rxdma_channel_buf_ring")); 2933 if (rbr_p == NULL) { 2934 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2935 "<== hxge_unmap_rxdma_channel_buf_ring: NULL rbrp")); 2936 return; 2937 } 2938 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2939 "==> hxge_unmap_rxdma_channel_buf_ring: channel %d", rbr_p->rdc)); 2940 2941 rx_msg_ring = rbr_p->rx_msg_ring; 2942 ring_info = rbr_p->ring_info; 2943 2944 if (rx_msg_ring == NULL || ring_info == NULL) { 2945 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2946 "<== hxge_unmap_rxdma_channel_buf_ring: " 2947 "rx_msg_ring $%p ring_info $%p", rx_msg_p, ring_info)); 2948 return; 2949 } 2950 2951 size = rbr_p->tnblocks * sizeof (p_rx_msg_t); 2952 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2953 " hxge_unmap_rxdma_channel_buf_ring: channel %d chunks %d " 2954 "tnblocks %d (max %d) size ptrs %d ", rbr_p->rdc, rbr_p->num_blocks, 2955 rbr_p->tnblocks, rbr_p->rbr_max_size, size)); 2956 2957 for (i = 0; i < rbr_p->tnblocks; i++) { 2958 rx_msg_p = rx_msg_ring[i]; 2959 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2960 " hxge_unmap_rxdma_channel_buf_ring: " 2961 "rx_msg_p $%p", rx_msg_p)); 2962 if (rx_msg_p != NULL) { 2963 hxge_freeb(rx_msg_p); 2964 rx_msg_ring[i] = NULL; 2965 } 2966 } 2967 2968 /* 2969 * We no longer may use the mutex <post_lock>. By setting 2970 * <rbr_state> to anything but POSTING, we prevent 2971 * hxge_post_page() from accessing a dead mutex. 2972 */ 2973 rbr_p->rbr_state = RBR_UNMAPPING; 2974 MUTEX_DESTROY(&rbr_p->post_lock); 2975 2976 MUTEX_DESTROY(&rbr_p->lock); 2977 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 2978 KMEM_FREE(rx_msg_ring, size); 2979 2980 if (rbr_p->rbr_ref_cnt == 0) { 2981 /* This is the normal state of affairs. */ 2982 KMEM_FREE(rbr_p, sizeof (*rbr_p)); 2983 } else { 2984 /* 2985 * Some of our buffers are still being used. 2986 * Therefore, tell hxge_freeb() this ring is 2987 * unmapped, so it may free <rbr_p> for us. 2988 */ 2989 rbr_p->rbr_state = RBR_UNMAPPED; 2990 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2991 "unmap_rxdma_buf_ring: %d %s outstanding.", 2992 rbr_p->rbr_ref_cnt, 2993 rbr_p->rbr_ref_cnt == 1 ? "msg" : "msgs")); 2994 } 2995 2996 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2997 "<== hxge_unmap_rxdma_channel_buf_ring")); 2998 } 2999 3000 static hxge_status_t 3001 hxge_rxdma_hw_start_common(p_hxge_t hxgep) 3002 { 3003 hxge_status_t status = HXGE_OK; 3004 3005 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start_common")); 3006 3007 /* 3008 * Load the sharable parameters by writing to the function zero control 3009 * registers. These FZC registers should be initialized only once for 3010 * the entire chip. 3011 */ 3012 (void) hxge_init_fzc_rx_common(hxgep); 3013 3014 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start_common")); 3015 3016 return (status); 3017 } 3018 3019 static hxge_status_t 3020 hxge_rxdma_hw_start(p_hxge_t hxgep) 3021 { 3022 int i, ndmas; 3023 uint16_t channel; 3024 p_rx_rbr_rings_t rx_rbr_rings; 3025 p_rx_rbr_ring_t *rbr_rings; 3026 p_rx_rcr_rings_t rx_rcr_rings; 3027 p_rx_rcr_ring_t *rcr_rings; 3028 p_rx_mbox_areas_t rx_mbox_areas_p; 3029 p_rx_mbox_t *rx_mbox_p; 3030 hxge_status_t status = HXGE_OK; 3031 3032 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start")); 3033 3034 rx_rbr_rings = hxgep->rx_rbr_rings; 3035 rx_rcr_rings = hxgep->rx_rcr_rings; 3036 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3037 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3038 "<== hxge_rxdma_hw_start: NULL ring pointers")); 3039 return (HXGE_ERROR); 3040 } 3041 3042 ndmas = rx_rbr_rings->ndmas; 3043 if (ndmas == 0) { 3044 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3045 "<== hxge_rxdma_hw_start: no dma channel allocated")); 3046 return (HXGE_ERROR); 3047 } 3048 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3049 "==> hxge_rxdma_hw_start (ndmas %d)", ndmas)); 3050 3051 /* 3052 * Scrub the RDC Rx DMA Prefetch Buffer Command. 3053 */ 3054 for (i = 0; i < 128; i++) { 3055 HXGE_REG_WR64(hxgep->hpi_handle, RDC_PREF_CMD, i); 3056 } 3057 3058 /* 3059 * Scrub Rx DMA Shadow Tail Command. 3060 */ 3061 for (i = 0; i < 64; i++) { 3062 HXGE_REG_WR64(hxgep->hpi_handle, RDC_SHADOW_CMD, i); 3063 } 3064 3065 /* 3066 * Scrub Rx DMA Control Fifo Command. 3067 */ 3068 for (i = 0; i < 512; i++) { 3069 HXGE_REG_WR64(hxgep->hpi_handle, RDC_CTRL_FIFO_CMD, i); 3070 } 3071 3072 /* 3073 * Scrub Rx DMA Data Fifo Command. 3074 */ 3075 for (i = 0; i < 1536; i++) { 3076 HXGE_REG_WR64(hxgep->hpi_handle, RDC_DATA_FIFO_CMD, i); 3077 } 3078 3079 /* 3080 * Reset the FIFO Error Stat. 3081 */ 3082 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_STAT, 0xFF); 3083 3084 /* Set the error mask to receive interrupts */ 3085 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_INT_MASK, 0x0); 3086 3087 rbr_rings = rx_rbr_rings->rbr_rings; 3088 rcr_rings = rx_rcr_rings->rcr_rings; 3089 rx_mbox_areas_p = hxgep->rx_mbox_areas_p; 3090 if (rx_mbox_areas_p) { 3091 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 3092 } 3093 3094 for (i = 0; i < ndmas; i++) { 3095 channel = rbr_rings[i]->rdc; 3096 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3097 "==> hxge_rxdma_hw_start (ndmas %d) channel %d", 3098 ndmas, channel)); 3099 status = hxge_rxdma_start_channel(hxgep, channel, 3100 (p_rx_rbr_ring_t)rbr_rings[i], 3101 (p_rx_rcr_ring_t)rcr_rings[i], 3102 (p_rx_mbox_t)rx_mbox_p[i]); 3103 if (status != HXGE_OK) { 3104 goto hxge_rxdma_hw_start_fail1; 3105 } 3106 } 3107 3108 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start: " 3109 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3110 rx_rbr_rings, rx_rcr_rings)); 3111 goto hxge_rxdma_hw_start_exit; 3112 3113 hxge_rxdma_hw_start_fail1: 3114 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3115 "==> hxge_rxdma_hw_start: disable " 3116 "(status 0x%x channel %d i %d)", status, channel, i)); 3117 for (; i >= 0; i--) { 3118 channel = rbr_rings[i]->rdc; 3119 (void) hxge_rxdma_stop_channel(hxgep, channel); 3120 } 3121 3122 hxge_rxdma_hw_start_exit: 3123 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3124 "==> hxge_rxdma_hw_start: (status 0x%x)", status)); 3125 return (status); 3126 } 3127 3128 static void 3129 hxge_rxdma_hw_stop(p_hxge_t hxgep) 3130 { 3131 int i, ndmas; 3132 uint16_t channel; 3133 p_rx_rbr_rings_t rx_rbr_rings; 3134 p_rx_rbr_ring_t *rbr_rings; 3135 p_rx_rcr_rings_t rx_rcr_rings; 3136 3137 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_stop")); 3138 3139 rx_rbr_rings = hxgep->rx_rbr_rings; 3140 rx_rcr_rings = hxgep->rx_rcr_rings; 3141 3142 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3143 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3144 "<== hxge_rxdma_hw_stop: NULL ring pointers")); 3145 return; 3146 } 3147 3148 ndmas = rx_rbr_rings->ndmas; 3149 if (!ndmas) { 3150 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3151 "<== hxge_rxdma_hw_stop: no dma channel allocated")); 3152 return; 3153 } 3154 3155 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3156 "==> hxge_rxdma_hw_stop (ndmas %d)", ndmas)); 3157 3158 rbr_rings = rx_rbr_rings->rbr_rings; 3159 for (i = 0; i < ndmas; i++) { 3160 channel = rbr_rings[i]->rdc; 3161 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3162 "==> hxge_rxdma_hw_stop (ndmas %d) channel %d", 3163 ndmas, channel)); 3164 (void) hxge_rxdma_stop_channel(hxgep, channel); 3165 } 3166 3167 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_stop: " 3168 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3169 rx_rbr_rings, rx_rcr_rings)); 3170 3171 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_rxdma_hw_stop")); 3172 } 3173 3174 static hxge_status_t 3175 hxge_rxdma_start_channel(p_hxge_t hxgep, uint16_t channel, 3176 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 3177 { 3178 hpi_handle_t handle; 3179 hpi_status_t rs = HPI_SUCCESS; 3180 rdc_stat_t cs; 3181 rdc_int_mask_t ent_mask; 3182 hxge_status_t status = HXGE_OK; 3183 3184 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel")); 3185 3186 handle = HXGE_DEV_HPI_HANDLE(hxgep); 3187 3188 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "hxge_rxdma_start_channel: " 3189 "hpi handle addr $%p acc $%p", 3190 hxgep->hpi_handle.regp, hxgep->hpi_handle.regh)); 3191 3192 /* Reset RXDMA channel */ 3193 rs = hpi_rxdma_cfg_rdc_reset(handle, channel); 3194 if (rs != HPI_SUCCESS) { 3195 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3196 "==> hxge_rxdma_start_channel: " 3197 "reset rxdma failed (0x%08x channel %d)", 3198 status, channel)); 3199 return (HXGE_ERROR | rs); 3200 } 3201 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3202 "==> hxge_rxdma_start_channel: reset done: channel %d", channel)); 3203 3204 /* 3205 * Initialize the RXDMA channel specific FZC control configurations. 3206 * These FZC registers are pertaining to each RX channel (logical 3207 * pages). 3208 */ 3209 status = hxge_init_fzc_rxdma_channel(hxgep, 3210 channel, rbr_p, rcr_p, mbox_p); 3211 if (status != HXGE_OK) { 3212 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3213 "==> hxge_rxdma_start_channel: " 3214 "init fzc rxdma failed (0x%08x channel %d)", 3215 status, channel)); 3216 return (status); 3217 } 3218 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3219 "==> hxge_rxdma_start_channel: fzc done")); 3220 3221 /* 3222 * Zero out the shadow and prefetch ram. 3223 */ 3224 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3225 "==> hxge_rxdma_start_channel: ram done")); 3226 3227 /* Set up the interrupt event masks. */ 3228 ent_mask.value = 0; 3229 rs = hpi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 3230 if (rs != HPI_SUCCESS) { 3231 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3232 "==> hxge_rxdma_start_channel: " 3233 "init rxdma event masks failed (0x%08x channel %d)", 3234 status, channel)); 3235 return (HXGE_ERROR | rs); 3236 } 3237 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3238 "event done: channel %d (mask 0x%016llx)", 3239 channel, ent_mask.value)); 3240 3241 /* 3242 * Load RXDMA descriptors, buffers, mailbox, initialise the receive DMA 3243 * channels and enable each DMA channel. 3244 */ 3245 status = hxge_enable_rxdma_channel(hxgep, 3246 channel, rbr_p, rcr_p, mbox_p); 3247 if (status != HXGE_OK) { 3248 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3249 " hxge_rxdma_start_channel: " 3250 " init enable rxdma failed (0x%08x channel %d)", 3251 status, channel)); 3252 return (status); 3253 } 3254 3255 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3256 "control done - channel %d cs 0x%016llx", channel, cs.value)); 3257 3258 /* 3259 * Initialize the receive DMA control and status register 3260 * Note that rdc_stat HAS to be set after RBR and RCR rings are set 3261 */ 3262 cs.value = 0; 3263 cs.bits.mex = 1; 3264 cs.bits.rcr_thres = 1; 3265 cs.bits.rcr_to = 1; 3266 cs.bits.rbr_empty = 1; 3267 status = hxge_init_rxdma_channel_cntl_stat(hxgep, channel, &cs); 3268 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3269 "channel %d rx_dma_cntl_stat 0x%0016llx", channel, cs.value)); 3270 if (status != HXGE_OK) { 3271 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3272 "==> hxge_rxdma_start_channel: " 3273 "init rxdma control register failed (0x%08x channel %d", 3274 status, channel)); 3275 return (status); 3276 } 3277 3278 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3279 "control done - channel %d cs 0x%016llx", channel, cs.value)); 3280 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3281 "==> hxge_rxdma_start_channel: enable done")); 3282 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_rxdma_start_channel")); 3283 3284 return (HXGE_OK); 3285 } 3286 3287 static hxge_status_t 3288 hxge_rxdma_stop_channel(p_hxge_t hxgep, uint16_t channel) 3289 { 3290 hpi_handle_t handle; 3291 hpi_status_t rs = HPI_SUCCESS; 3292 rdc_stat_t cs; 3293 rdc_int_mask_t ent_mask; 3294 hxge_status_t status = HXGE_OK; 3295 3296 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_channel")); 3297 3298 handle = HXGE_DEV_HPI_HANDLE(hxgep); 3299 3300 HXGE_DEBUG_MSG((hxgep, RX_CTL, "hxge_rxdma_stop_channel: " 3301 "hpi handle addr $%p acc $%p", 3302 hxgep->hpi_handle.regp, hxgep->hpi_handle.regh)); 3303 3304 /* Reset RXDMA channel */ 3305 rs = hpi_rxdma_cfg_rdc_reset(handle, channel); 3306 if (rs != HPI_SUCCESS) { 3307 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3308 " hxge_rxdma_stop_channel: " 3309 " reset rxdma failed (0x%08x channel %d)", 3310 rs, channel)); 3311 return (HXGE_ERROR | rs); 3312 } 3313 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3314 "==> hxge_rxdma_stop_channel: reset done")); 3315 3316 /* Set up the interrupt event masks. */ 3317 ent_mask.value = RDC_INT_MASK_ALL; 3318 rs = hpi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 3319 if (rs != HPI_SUCCESS) { 3320 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3321 "==> hxge_rxdma_stop_channel: " 3322 "set rxdma event masks failed (0x%08x channel %d)", 3323 rs, channel)); 3324 return (HXGE_ERROR | rs); 3325 } 3326 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3327 "==> hxge_rxdma_stop_channel: event done")); 3328 3329 /* Initialize the receive DMA control and status register */ 3330 cs.value = 0; 3331 status = hxge_init_rxdma_channel_cntl_stat(hxgep, channel, &cs); 3332 3333 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_channel: control " 3334 " to default (all 0s) 0x%08x", cs.value)); 3335 3336 if (status != HXGE_OK) { 3337 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3338 " hxge_rxdma_stop_channel: init rxdma" 3339 " control register failed (0x%08x channel %d", 3340 status, channel)); 3341 return (status); 3342 } 3343 3344 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3345 "==> hxge_rxdma_stop_channel: control done")); 3346 3347 /* disable dma channel */ 3348 status = hxge_disable_rxdma_channel(hxgep, channel); 3349 3350 if (status != HXGE_OK) { 3351 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3352 " hxge_rxdma_stop_channel: " 3353 " init enable rxdma failed (0x%08x channel %d)", 3354 status, channel)); 3355 return (status); 3356 } 3357 3358 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3359 "==> hxge_rxdma_stop_channel: disable done")); 3360 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop_channel")); 3361 3362 return (HXGE_OK); 3363 } 3364 3365 hxge_status_t 3366 hxge_rxdma_handle_sys_errors(p_hxge_t hxgep) 3367 { 3368 hpi_handle_t handle; 3369 p_hxge_rdc_sys_stats_t statsp; 3370 rdc_fifo_err_stat_t stat; 3371 hxge_status_t status = HXGE_OK; 3372 3373 handle = hxgep->hpi_handle; 3374 statsp = (p_hxge_rdc_sys_stats_t)&hxgep->statsp->rdc_sys_stats; 3375 3376 /* Clear the int_dbg register in case it is an injected err */ 3377 HXGE_REG_WR64(handle, RDC_FIFO_ERR_INT_DBG, 0x0); 3378 3379 /* Get the error status and clear the register */ 3380 HXGE_REG_RD64(handle, RDC_FIFO_ERR_STAT, &stat.value); 3381 HXGE_REG_WR64(handle, RDC_FIFO_ERR_STAT, stat.value); 3382 3383 if (stat.bits.rx_ctrl_fifo_sec) { 3384 statsp->ctrl_fifo_sec++; 3385 if (statsp->ctrl_fifo_sec == 1) 3386 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3387 "==> hxge_rxdma_handle_sys_errors: " 3388 "rx_ctrl_fifo_sec")); 3389 } 3390 3391 if (stat.bits.rx_ctrl_fifo_ded) { 3392 /* Global fatal error encountered */ 3393 statsp->ctrl_fifo_ded++; 3394 HXGE_FM_REPORT_ERROR(hxgep, NULL, 3395 HXGE_FM_EREPORT_RDMC_CTRL_FIFO_DED); 3396 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3397 "==> hxge_rxdma_handle_sys_errors: " 3398 "fatal error: rx_ctrl_fifo_ded error")); 3399 } 3400 3401 if (stat.bits.rx_data_fifo_sec) { 3402 statsp->data_fifo_sec++; 3403 if (statsp->data_fifo_sec == 1) 3404 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3405 "==> hxge_rxdma_handle_sys_errors: " 3406 "rx_data_fifo_sec")); 3407 } 3408 3409 if (stat.bits.rx_data_fifo_ded) { 3410 /* Global fatal error encountered */ 3411 statsp->data_fifo_ded++; 3412 HXGE_FM_REPORT_ERROR(hxgep, NULL, 3413 HXGE_FM_EREPORT_RDMC_DATA_FIFO_DED); 3414 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3415 "==> hxge_rxdma_handle_sys_errors: " 3416 "fatal error: rx_data_fifo_ded error")); 3417 } 3418 3419 if (stat.bits.rx_ctrl_fifo_ded || stat.bits.rx_data_fifo_ded) { 3420 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3421 " hxge_rxdma_handle_sys_errors: fatal error\n")); 3422 status = hxge_rx_port_fatal_err_recover(hxgep); 3423 if (status == HXGE_OK) { 3424 FM_SERVICE_RESTORED(hxgep); 3425 } 3426 } 3427 3428 return (HXGE_OK); 3429 } 3430 3431 static hxge_status_t 3432 hxge_rxdma_fatal_err_recover(p_hxge_t hxgep, uint16_t channel) 3433 { 3434 hpi_handle_t handle; 3435 hpi_status_t rs = HPI_SUCCESS; 3436 hxge_status_t status = HXGE_OK; 3437 p_rx_rbr_ring_t rbrp; 3438 p_rx_rcr_ring_t rcrp; 3439 p_rx_mbox_t mboxp; 3440 rdc_int_mask_t ent_mask; 3441 p_hxge_dma_common_t dmap; 3442 int ring_idx; 3443 p_rx_msg_t rx_msg_p; 3444 int i; 3445 uint32_t hxge_port_rcr_size; 3446 uint64_t tmp; 3447 3448 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_fatal_err_recover")); 3449 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3450 "Recovering from RxDMAChannel#%d error...", channel)); 3451 3452 /* 3453 * Stop the dma channel waits for the stop done. If the stop done bit 3454 * is not set, then create an error. 3455 */ 3456 3457 handle = HXGE_DEV_HPI_HANDLE(hxgep); 3458 3459 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Rx DMA stop...")); 3460 3461 ring_idx = hxge_rxdma_get_ring_index(hxgep, channel); 3462 rbrp = (p_rx_rbr_ring_t)hxgep->rx_rbr_rings->rbr_rings[ring_idx]; 3463 rcrp = (p_rx_rcr_ring_t)hxgep->rx_rcr_rings->rcr_rings[ring_idx]; 3464 3465 MUTEX_ENTER(&rcrp->lock); 3466 MUTEX_ENTER(&rbrp->lock); 3467 MUTEX_ENTER(&rbrp->post_lock); 3468 3469 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxDMA channel...")); 3470 3471 rs = hpi_rxdma_cfg_rdc_disable(handle, channel); 3472 if (rs != HPI_SUCCESS) { 3473 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3474 "hxge_disable_rxdma_channel:failed")); 3475 goto fail; 3476 } 3477 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxDMA interrupt...")); 3478 3479 /* Disable interrupt */ 3480 ent_mask.value = RDC_INT_MASK_ALL; 3481 rs = hpi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 3482 if (rs != HPI_SUCCESS) { 3483 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3484 "Set rxdma event masks failed (channel %d)", channel)); 3485 } 3486 HXGE_DEBUG_MSG((hxgep, RX_CTL, "RxDMA channel reset...")); 3487 3488 /* Reset RXDMA channel */ 3489 rs = hpi_rxdma_cfg_rdc_reset(handle, channel); 3490 if (rs != HPI_SUCCESS) { 3491 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3492 "Reset rxdma failed (channel %d)", channel)); 3493 goto fail; 3494 } 3495 hxge_port_rcr_size = hxgep->hxge_port_rcr_size; 3496 mboxp = (p_rx_mbox_t)hxgep->rx_mbox_areas_p->rxmbox_areas[ring_idx]; 3497 3498 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 3499 rbrp->rbr_rd_index = 0; 3500 rbrp->pages_to_post = 0; 3501 3502 rcrp->comp_rd_index = 0; 3503 rcrp->comp_wt_index = 0; 3504 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 3505 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 3506 #if defined(__i386) 3507 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3508 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3509 #else 3510 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3511 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3512 #endif 3513 3514 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 3515 (hxge_port_rcr_size - 1); 3516 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 3517 (hxge_port_rcr_size - 1); 3518 3519 rcrp->rcr_tail_begin = DMA_COMMON_IOADDR(rcrp->rcr_desc); 3520 rcrp->rcr_tail_begin = (rcrp->rcr_tail_begin & 0x7ffffULL) >> 3; 3521 3522 dmap = (p_hxge_dma_common_t)&rcrp->rcr_desc; 3523 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3524 3525 HXGE_DEBUG_MSG((hxgep, RX_CTL, "rbr entries = %d\n", 3526 rbrp->rbr_max_size)); 3527 3528 for (i = 0; i < rbrp->rbr_max_size; i++) { 3529 /* Reset all the buffers */ 3530 rx_msg_p = rbrp->rx_msg_ring[i]; 3531 rx_msg_p->ref_cnt = 1; 3532 rx_msg_p->free = B_TRUE; 3533 rx_msg_p->cur_usage_cnt = 0; 3534 rx_msg_p->max_usage_cnt = 0; 3535 rx_msg_p->pkt_buf_size = 0; 3536 } 3537 3538 HXGE_DEBUG_MSG((hxgep, RX_CTL, "RxDMA channel re-start...")); 3539 3540 status = hxge_rxdma_start_channel(hxgep, channel, rbrp, rcrp, mboxp); 3541 if (status != HXGE_OK) { 3542 goto fail; 3543 } 3544 3545 /* 3546 * The DMA channel may disable itself automatically. 3547 * The following is a work-around. 3548 */ 3549 HXGE_REG_RD64(handle, RDC_RX_CFG1, &tmp); 3550 rs = hpi_rxdma_cfg_rdc_enable(handle, channel); 3551 if (rs != HPI_SUCCESS) { 3552 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3553 "hpi_rxdma_cfg_rdc_enable (channel %d)", channel)); 3554 } 3555 3556 MUTEX_EXIT(&rbrp->post_lock); 3557 MUTEX_EXIT(&rbrp->lock); 3558 MUTEX_EXIT(&rcrp->lock); 3559 3560 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3561 "Recovery Successful, RxDMAChannel#%d Restored", channel)); 3562 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_fatal_err_recover")); 3563 3564 return (HXGE_OK); 3565 3566 fail: 3567 MUTEX_EXIT(&rbrp->post_lock); 3568 MUTEX_EXIT(&rbrp->lock); 3569 MUTEX_EXIT(&rcrp->lock); 3570 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovery failed")); 3571 3572 return (HXGE_ERROR | rs); 3573 } 3574 3575 static hxge_status_t 3576 hxge_rx_port_fatal_err_recover(p_hxge_t hxgep) 3577 { 3578 hxge_status_t status = HXGE_OK; 3579 p_hxge_dma_common_t *dma_buf_p; 3580 uint16_t channel; 3581 int ndmas; 3582 int i; 3583 block_reset_t reset_reg; 3584 3585 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_port_fatal_err_recover")); 3586 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovering from RDC error ...")); 3587 3588 /* Reset RDC block from PEU for this fatal error */ 3589 reset_reg.value = 0; 3590 reset_reg.bits.rdc_rst = 1; 3591 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value); 3592 3593 /* Disable RxMAC */ 3594 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxMAC...\n")); 3595 if (hxge_rx_vmac_disable(hxgep) != HXGE_OK) 3596 goto fail; 3597 3598 HXGE_DELAY(1000); 3599 3600 /* Restore any common settings after PEU reset */ 3601 if (hxge_rxdma_hw_start_common(hxgep) != HXGE_OK) 3602 goto fail; 3603 3604 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Stop all RxDMA channels...")); 3605 3606 ndmas = hxgep->rx_buf_pool_p->ndmas; 3607 dma_buf_p = hxgep->rx_buf_pool_p->dma_buf_pool_p; 3608 3609 for (i = 0; i < ndmas; i++) { 3610 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 3611 if (hxge_rxdma_fatal_err_recover(hxgep, channel) != HXGE_OK) { 3612 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3613 "Could not recover channel %d", channel)); 3614 } 3615 } 3616 3617 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Reset RxMAC...")); 3618 3619 /* Reset RxMAC */ 3620 if (hxge_rx_vmac_reset(hxgep) != HXGE_OK) { 3621 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3622 "hxge_rx_port_fatal_err_recover: Failed to reset RxMAC")); 3623 goto fail; 3624 } 3625 3626 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Re-initialize RxMAC...")); 3627 3628 /* Re-Initialize RxMAC */ 3629 if ((status = hxge_rx_vmac_init(hxgep)) != HXGE_OK) { 3630 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3631 "hxge_rx_port_fatal_err_recover: Failed to reset RxMAC")); 3632 goto fail; 3633 } 3634 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Re-enable RxMAC...")); 3635 3636 /* Re-enable RxMAC */ 3637 if ((status = hxge_rx_vmac_enable(hxgep)) != HXGE_OK) { 3638 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3639 "hxge_rx_port_fatal_err_recover: Failed to enable RxMAC")); 3640 goto fail; 3641 } 3642 3643 /* Reset the error mask since PEU reset cleared it */ 3644 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_INT_MASK, 0x0); 3645 3646 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3647 "Recovery Successful, RxPort Restored")); 3648 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rx_port_fatal_err_recover")); 3649 3650 return (HXGE_OK); 3651 fail: 3652 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovery failed")); 3653 return (status); 3654 } 3655