1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <hxge_impl.h> 27 #include <hxge_rxdma.h> 28 29 /* 30 * Globals: tunable parameters (/etc/system or adb) 31 * 32 */ 33 extern uint32_t hxge_rbr_size; 34 extern uint32_t hxge_rcr_size; 35 extern uint32_t hxge_rbr_spare_size; 36 37 extern uint32_t hxge_mblks_pending; 38 39 /* 40 * Tunable to reduce the amount of time spent in the 41 * ISR doing Rx Processing. 42 */ 43 extern uint32_t hxge_max_rx_pkts; 44 boolean_t hxge_jumbo_enable; 45 46 /* 47 * Tunables to manage the receive buffer blocks. 48 * 49 * hxge_rx_threshold_hi: copy all buffers. 50 * hxge_rx_bcopy_size_type: receive buffer block size type. 51 * hxge_rx_threshold_lo: copy only up to tunable block size type. 52 */ 53 extern hxge_rxbuf_threshold_t hxge_rx_threshold_hi; 54 extern hxge_rxbuf_type_t hxge_rx_buf_size_type; 55 extern hxge_rxbuf_threshold_t hxge_rx_threshold_lo; 56 57 static hxge_status_t hxge_map_rxdma(p_hxge_t hxgep); 58 static void hxge_unmap_rxdma(p_hxge_t hxgep); 59 static hxge_status_t hxge_rxdma_hw_start_common(p_hxge_t hxgep); 60 static hxge_status_t hxge_rxdma_hw_start(p_hxge_t hxgep); 61 static void hxge_rxdma_hw_stop(p_hxge_t hxgep); 62 static hxge_status_t hxge_map_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 63 p_hxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 64 uint32_t num_chunks, p_hxge_dma_common_t *dma_cntl_p, 65 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p); 66 static void hxge_unmap_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 67 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p); 68 static hxge_status_t hxge_map_rxdma_channel_cfg_ring(p_hxge_t hxgep, 69 uint16_t dma_channel, p_hxge_dma_common_t *dma_cntl_p, 70 p_rx_rbr_ring_t *rbr_p, p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p); 71 static void hxge_unmap_rxdma_channel_cfg_ring(p_hxge_t hxgep, 72 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p); 73 static hxge_status_t hxge_map_rxdma_channel_buf_ring(p_hxge_t hxgep, 74 uint16_t channel, p_hxge_dma_common_t *dma_buf_p, 75 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks); 76 static void hxge_unmap_rxdma_channel_buf_ring(p_hxge_t hxgep, 77 p_rx_rbr_ring_t rbr_p); 78 static hxge_status_t hxge_rxdma_start_channel(p_hxge_t hxgep, uint16_t channel, 79 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p); 80 static hxge_status_t hxge_rxdma_stop_channel(p_hxge_t hxgep, uint16_t channel); 81 static mblk_t *hxge_rx_pkts(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp, 82 p_rx_rcr_ring_t *rcr_p, rdc_stat_t cs); 83 static void hxge_receive_packet(p_hxge_t hxgep, p_rx_rcr_ring_t rcr_p, 84 p_rcr_entry_t rcr_desc_rd_head_p, boolean_t *multi_p, 85 mblk_t ** mp, mblk_t ** mp_cont, uint32_t *invalid_rcr_entry); 86 static hxge_status_t hxge_disable_rxdma_channel(p_hxge_t hxgep, 87 uint16_t channel); 88 static p_rx_msg_t hxge_allocb(size_t, uint32_t, p_hxge_dma_common_t); 89 static void hxge_freeb(p_rx_msg_t); 90 static void hxge_rx_pkts_vring(p_hxge_t hxgep, uint_t vindex, 91 p_hxge_ldv_t ldvp, rdc_stat_t cs); 92 static hxge_status_t hxge_rx_err_evnts(p_hxge_t hxgep, uint_t index, 93 p_hxge_ldv_t ldvp, rdc_stat_t cs); 94 static hxge_status_t hxge_rxbuf_index_info_init(p_hxge_t hxgep, 95 p_rx_rbr_ring_t rx_dmap); 96 static hxge_status_t hxge_rxdma_fatal_err_recover(p_hxge_t hxgep, 97 uint16_t channel); 98 static hxge_status_t hxge_rx_port_fatal_err_recover(p_hxge_t hxgep); 99 100 #define HXGE_RXDMA_RBB_MAX(x) (((x) >> 4) * 15) 101 #define HXGE_RXDMA_RBB_MIN(x) ((x) >> 4) 102 #define HXGE_RXDMA_RBB_THRESHOLD(x) (((x) >> 4) * 14) 103 104 hxge_status_t 105 hxge_init_rxdma_channels(p_hxge_t hxgep) 106 { 107 hxge_status_t status = HXGE_OK; 108 block_reset_t reset_reg; 109 110 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_init_rxdma_channels")); 111 112 /* Reset RDC block from PEU to clear any previous state */ 113 reset_reg.value = 0; 114 reset_reg.bits.rdc_rst = 1; 115 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value); 116 HXGE_DELAY(1000); 117 118 status = hxge_map_rxdma(hxgep); 119 if (status != HXGE_OK) { 120 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 121 "<== hxge_init_rxdma: status 0x%x", status)); 122 return (status); 123 } 124 125 status = hxge_rxdma_hw_start_common(hxgep); 126 if (status != HXGE_OK) { 127 hxge_unmap_rxdma(hxgep); 128 } 129 130 status = hxge_rxdma_hw_start(hxgep); 131 if (status != HXGE_OK) { 132 hxge_unmap_rxdma(hxgep); 133 } 134 135 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 136 "<== hxge_init_rxdma_channels: status 0x%x", status)); 137 return (status); 138 } 139 140 void 141 hxge_uninit_rxdma_channels(p_hxge_t hxgep) 142 { 143 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_uninit_rxdma_channels")); 144 145 hxge_rxdma_hw_stop(hxgep); 146 hxge_unmap_rxdma(hxgep); 147 148 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_uinit_rxdma_channels")); 149 } 150 151 hxge_status_t 152 hxge_init_rxdma_channel_cntl_stat(p_hxge_t hxgep, uint16_t channel, 153 rdc_stat_t *cs_p) 154 { 155 hpi_handle_t handle; 156 hpi_status_t rs = HPI_SUCCESS; 157 hxge_status_t status = HXGE_OK; 158 159 HXGE_DEBUG_MSG((hxgep, DMA_CTL, 160 "<== hxge_init_rxdma_channel_cntl_stat")); 161 162 handle = HXGE_DEV_HPI_HANDLE(hxgep); 163 rs = hpi_rxdma_control_status(handle, OP_SET, channel, cs_p); 164 165 if (rs != HPI_SUCCESS) { 166 status = HXGE_ERROR | rs; 167 } 168 return (status); 169 } 170 171 172 hxge_status_t 173 hxge_enable_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 174 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 175 { 176 hpi_handle_t handle; 177 rdc_desc_cfg_t rdc_desc; 178 rdc_rcr_cfg_b_t *cfgb_p; 179 hpi_status_t rs = HPI_SUCCESS; 180 181 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel")); 182 handle = HXGE_DEV_HPI_HANDLE(hxgep); 183 184 /* 185 * Use configuration data composed at init time. Write to hardware the 186 * receive ring configurations. 187 */ 188 rdc_desc.mbox_enable = 1; 189 rdc_desc.mbox_addr = mbox_p->mbox_addr; 190 HXGE_DEBUG_MSG((hxgep, RX_CTL, 191 "==> hxge_enable_rxdma_channel: mboxp $%p($%p)", 192 mbox_p->mbox_addr, rdc_desc.mbox_addr)); 193 194 rdc_desc.rbr_len = rbr_p->rbb_max; 195 rdc_desc.rbr_addr = rbr_p->rbr_addr; 196 197 switch (hxgep->rx_bksize_code) { 198 case RBR_BKSIZE_4K: 199 rdc_desc.page_size = SIZE_4KB; 200 break; 201 case RBR_BKSIZE_8K: 202 rdc_desc.page_size = SIZE_8KB; 203 break; 204 } 205 206 rdc_desc.size0 = rbr_p->hpi_pkt_buf_size0; 207 rdc_desc.valid0 = 1; 208 209 rdc_desc.size1 = rbr_p->hpi_pkt_buf_size1; 210 rdc_desc.valid1 = 1; 211 212 rdc_desc.size2 = rbr_p->hpi_pkt_buf_size2; 213 rdc_desc.valid2 = 1; 214 215 rdc_desc.full_hdr = rcr_p->full_hdr_flag; 216 rdc_desc.offset = rcr_p->sw_priv_hdr_len; 217 218 rdc_desc.rcr_len = rcr_p->comp_size; 219 rdc_desc.rcr_addr = rcr_p->rcr_addr; 220 221 cfgb_p = &(rcr_p->rcr_cfgb); 222 rdc_desc.rcr_threshold = cfgb_p->bits.pthres; 223 rdc_desc.rcr_timeout = cfgb_p->bits.timeout; 224 rdc_desc.rcr_timeout_enable = cfgb_p->bits.entout; 225 226 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel: " 227 "rbr_len qlen %d pagesize code %d rcr_len %d", 228 rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len)); 229 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel: " 230 "size 0 %d size 1 %d size 2 %d", 231 rbr_p->hpi_pkt_buf_size0, rbr_p->hpi_pkt_buf_size1, 232 rbr_p->hpi_pkt_buf_size2)); 233 234 rs = hpi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc, &rdc_desc); 235 if (rs != HPI_SUCCESS) { 236 return (HXGE_ERROR | rs); 237 } 238 239 /* 240 * Enable the timeout and threshold. 241 */ 242 rs = hpi_rxdma_cfg_rdc_rcr_threshold(handle, channel, 243 rdc_desc.rcr_threshold); 244 if (rs != HPI_SUCCESS) { 245 return (HXGE_ERROR | rs); 246 } 247 248 rs = hpi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 249 rdc_desc.rcr_timeout); 250 if (rs != HPI_SUCCESS) { 251 return (HXGE_ERROR | rs); 252 } 253 254 /* Enable the DMA */ 255 rs = hpi_rxdma_cfg_rdc_enable(handle, channel); 256 if (rs != HPI_SUCCESS) { 257 return (HXGE_ERROR | rs); 258 } 259 260 /* 261 * Kick the DMA engine with the initial kick and indicate 262 * that we have remaining blocks to post. 263 */ 264 rbr_p->pages_to_post = HXGE_RXDMA_RBB_MIN(rbr_p->rbb_max); 265 hpi_rxdma_rdc_rbr_kick(handle, channel, 266 HXGE_RXDMA_RBB_MAX(rbr_p->rbb_max)); 267 268 /* Clear the rbr empty bit */ 269 (void) hpi_rxdma_channel_rbr_empty_clear(handle, channel); 270 271 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_enable_rxdma_channel")); 272 273 return (HXGE_OK); 274 } 275 276 static hxge_status_t 277 hxge_disable_rxdma_channel(p_hxge_t hxgep, uint16_t channel) 278 { 279 hpi_handle_t handle; 280 hpi_status_t rs = HPI_SUCCESS; 281 282 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_disable_rxdma_channel")); 283 284 handle = HXGE_DEV_HPI_HANDLE(hxgep); 285 286 /* disable the DMA */ 287 rs = hpi_rxdma_cfg_rdc_disable(handle, channel); 288 if (rs != HPI_SUCCESS) { 289 HXGE_DEBUG_MSG((hxgep, RX_CTL, 290 "<== hxge_disable_rxdma_channel:failed (0x%x)", rs)); 291 return (HXGE_ERROR | rs); 292 } 293 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_disable_rxdma_channel")); 294 return (HXGE_OK); 295 } 296 297 hxge_status_t 298 hxge_rxdma_channel_rcrflush(p_hxge_t hxgep, uint8_t channel) 299 { 300 hpi_handle_t handle; 301 hxge_status_t status = HXGE_OK; 302 303 HXGE_DEBUG_MSG((hxgep, DMA_CTL, 304 "==> hxge_rxdma_channel_rcrflush")); 305 306 handle = HXGE_DEV_HPI_HANDLE(hxgep); 307 hpi_rxdma_rdc_rcr_flush(handle, channel); 308 309 HXGE_DEBUG_MSG((hxgep, DMA_CTL, 310 "<== hxge_rxdma_channel_rcrflush")); 311 return (status); 312 313 } 314 315 #define MID_INDEX(l, r) ((r + l + 1) >> 1) 316 317 #define TO_LEFT -1 318 #define TO_RIGHT 1 319 #define BOTH_RIGHT (TO_RIGHT + TO_RIGHT) 320 #define BOTH_LEFT (TO_LEFT + TO_LEFT) 321 #define IN_MIDDLE (TO_RIGHT + TO_LEFT) 322 #define NO_HINT 0xffffffff 323 324 /*ARGSUSED*/ 325 hxge_status_t 326 hxge_rxbuf_pp_to_vp(p_hxge_t hxgep, p_rx_rbr_ring_t rbr_p, 327 uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp, 328 uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index) 329 { 330 int bufsize; 331 uint64_t pktbuf_pp; 332 uint64_t dvma_addr; 333 rxring_info_t *ring_info; 334 int base_side, end_side; 335 int r_index, l_index, anchor_index; 336 int found, search_done; 337 uint32_t offset, chunk_size, block_size, page_size_mask; 338 uint32_t chunk_index, block_index, total_index; 339 int max_iterations, iteration; 340 rxbuf_index_info_t *bufinfo; 341 342 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> hxge_rxbuf_pp_to_vp")); 343 344 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 345 "==> hxge_rxbuf_pp_to_vp: buf_pp $%p btype %d", 346 pkt_buf_addr_pp, pktbufsz_type)); 347 348 #if defined(__i386) 349 pktbuf_pp = (uint64_t)(uint32_t)pkt_buf_addr_pp; 350 #else 351 pktbuf_pp = (uint64_t)pkt_buf_addr_pp; 352 #endif 353 354 switch (pktbufsz_type) { 355 case 0: 356 bufsize = rbr_p->pkt_buf_size0; 357 break; 358 case 1: 359 bufsize = rbr_p->pkt_buf_size1; 360 break; 361 case 2: 362 bufsize = rbr_p->pkt_buf_size2; 363 break; 364 case RCR_SINGLE_BLOCK: 365 bufsize = 0; 366 anchor_index = 0; 367 break; 368 default: 369 return (HXGE_ERROR); 370 } 371 372 if (rbr_p->num_blocks == 1) { 373 anchor_index = 0; 374 ring_info = rbr_p->ring_info; 375 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 376 377 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 378 "==> hxge_rxbuf_pp_to_vp: (found, 1 block) " 379 "buf_pp $%p btype %d anchor_index %d bufinfo $%p", 380 pkt_buf_addr_pp, pktbufsz_type, anchor_index, bufinfo)); 381 382 goto found_index; 383 } 384 385 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 386 "==> hxge_rxbuf_pp_to_vp: buf_pp $%p btype %d anchor_index %d", 387 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 388 389 ring_info = rbr_p->ring_info; 390 found = B_FALSE; 391 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 392 iteration = 0; 393 max_iterations = ring_info->max_iterations; 394 395 /* 396 * First check if this block have been seen recently. This is indicated 397 * by a hint which is initialized when the first buffer of the block is 398 * seen. The hint is reset when the last buffer of the block has been 399 * processed. As three block sizes are supported, three hints are kept. 400 * The idea behind the hints is that once the hardware uses a block 401 * for a buffer of that size, it will use it exclusively for that size 402 * and will use it until it is exhausted. It is assumed that there 403 * would a single block being used for the same buffer sizes at any 404 * given time. 405 */ 406 if (ring_info->hint[pktbufsz_type] != NO_HINT) { 407 anchor_index = ring_info->hint[pktbufsz_type]; 408 dvma_addr = bufinfo[anchor_index].dvma_addr; 409 chunk_size = bufinfo[anchor_index].buf_size; 410 if ((pktbuf_pp >= dvma_addr) && 411 (pktbuf_pp < (dvma_addr + chunk_size))) { 412 found = B_TRUE; 413 /* 414 * check if this is the last buffer in the block If so, 415 * then reset the hint for the size; 416 */ 417 418 if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size)) 419 ring_info->hint[pktbufsz_type] = NO_HINT; 420 } 421 } 422 423 if (found == B_FALSE) { 424 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 425 "==> hxge_rxbuf_pp_to_vp: (!found)" 426 "buf_pp $%p btype %d anchor_index %d", 427 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 428 429 /* 430 * This is the first buffer of the block of this size. Need to 431 * search the whole information array. the search algorithm 432 * uses a binary tree search algorithm. It assumes that the 433 * information is already sorted with increasing order info[0] 434 * < info[1] < info[2] .... < info[n-1] where n is the size of 435 * the information array 436 */ 437 r_index = rbr_p->num_blocks - 1; 438 l_index = 0; 439 search_done = B_FALSE; 440 anchor_index = MID_INDEX(r_index, l_index); 441 while (search_done == B_FALSE) { 442 if ((r_index == l_index) || 443 (iteration >= max_iterations)) 444 search_done = B_TRUE; 445 446 end_side = TO_RIGHT; /* to the right */ 447 base_side = TO_LEFT; /* to the left */ 448 /* read the DVMA address information and sort it */ 449 dvma_addr = bufinfo[anchor_index].dvma_addr; 450 chunk_size = bufinfo[anchor_index].buf_size; 451 452 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 453 "==> hxge_rxbuf_pp_to_vp: (searching)" 454 "buf_pp $%p btype %d " 455 "anchor_index %d chunk_size %d dvmaaddr $%p", 456 pkt_buf_addr_pp, pktbufsz_type, anchor_index, 457 chunk_size, dvma_addr)); 458 459 if (pktbuf_pp >= dvma_addr) 460 base_side = TO_RIGHT; /* to the right */ 461 if (pktbuf_pp < (dvma_addr + chunk_size)) 462 end_side = TO_LEFT; /* to the left */ 463 464 switch (base_side + end_side) { 465 case IN_MIDDLE: 466 /* found */ 467 found = B_TRUE; 468 search_done = B_TRUE; 469 if ((pktbuf_pp + bufsize) < 470 (dvma_addr + chunk_size)) 471 ring_info->hint[pktbufsz_type] = 472 bufinfo[anchor_index].buf_index; 473 break; 474 case BOTH_RIGHT: 475 /* not found: go to the right */ 476 l_index = anchor_index + 1; 477 anchor_index = MID_INDEX(r_index, l_index); 478 break; 479 480 case BOTH_LEFT: 481 /* not found: go to the left */ 482 r_index = anchor_index - 1; 483 anchor_index = MID_INDEX(r_index, l_index); 484 break; 485 default: /* should not come here */ 486 return (HXGE_ERROR); 487 } 488 iteration++; 489 } 490 491 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 492 "==> hxge_rxbuf_pp_to_vp: (search done)" 493 "buf_pp $%p btype %d anchor_index %d", 494 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 495 } 496 497 if (found == B_FALSE) { 498 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 499 "==> hxge_rxbuf_pp_to_vp: (search failed)" 500 "buf_pp $%p btype %d anchor_index %d", 501 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 502 return (HXGE_ERROR); 503 } 504 505 found_index: 506 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 507 "==> hxge_rxbuf_pp_to_vp: (FOUND1)" 508 "buf_pp $%p btype %d bufsize %d anchor_index %d", 509 pkt_buf_addr_pp, pktbufsz_type, bufsize, anchor_index)); 510 511 /* index of the first block in this chunk */ 512 chunk_index = bufinfo[anchor_index].start_index; 513 dvma_addr = bufinfo[anchor_index].dvma_addr; 514 page_size_mask = ring_info->block_size_mask; 515 516 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 517 "==> hxge_rxbuf_pp_to_vp: (FOUND3), get chunk)" 518 "buf_pp $%p btype %d bufsize %d " 519 "anchor_index %d chunk_index %d dvma $%p", 520 pkt_buf_addr_pp, pktbufsz_type, bufsize, 521 anchor_index, chunk_index, dvma_addr)); 522 523 offset = pktbuf_pp - dvma_addr; /* offset within the chunk */ 524 block_size = rbr_p->block_size; /* System block(page) size */ 525 526 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 527 "==> hxge_rxbuf_pp_to_vp: (FOUND4), get chunk)" 528 "buf_pp $%p btype %d bufsize %d " 529 "anchor_index %d chunk_index %d dvma $%p " 530 "offset %d block_size %d", 531 pkt_buf_addr_pp, pktbufsz_type, bufsize, anchor_index, 532 chunk_index, dvma_addr, offset, block_size)); 533 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> getting total index")); 534 535 block_index = (offset / block_size); /* index within chunk */ 536 total_index = chunk_index + block_index; 537 538 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 539 "==> hxge_rxbuf_pp_to_vp: " 540 "total_index %d dvma_addr $%p " 541 "offset %d block_size %d " 542 "block_index %d ", 543 total_index, dvma_addr, offset, block_size, block_index)); 544 545 #if defined(__i386) 546 *pkt_buf_addr_p = (uint64_t *)((uint32_t)bufinfo[anchor_index].kaddr + 547 (uint32_t)offset); 548 #else 549 *pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr + 550 offset); 551 #endif 552 553 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 554 "==> hxge_rxbuf_pp_to_vp: " 555 "total_index %d dvma_addr $%p " 556 "offset %d block_size %d " 557 "block_index %d " 558 "*pkt_buf_addr_p $%p", 559 total_index, dvma_addr, offset, block_size, 560 block_index, *pkt_buf_addr_p)); 561 562 *msg_index = total_index; 563 *bufoffset = (offset & page_size_mask); 564 565 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 566 "==> hxge_rxbuf_pp_to_vp: get msg index: " 567 "msg_index %d bufoffset_index %d", 568 *msg_index, *bufoffset)); 569 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "<== hxge_rxbuf_pp_to_vp")); 570 571 return (HXGE_OK); 572 } 573 574 575 /* 576 * used by quick sort (qsort) function 577 * to perform comparison 578 */ 579 static int 580 hxge_sort_compare(const void *p1, const void *p2) 581 { 582 583 rxbuf_index_info_t *a, *b; 584 585 a = (rxbuf_index_info_t *)p1; 586 b = (rxbuf_index_info_t *)p2; 587 588 if (a->dvma_addr > b->dvma_addr) 589 return (1); 590 if (a->dvma_addr < b->dvma_addr) 591 return (-1); 592 return (0); 593 } 594 595 /* 596 * Grabbed this sort implementation from common/syscall/avl.c 597 * 598 * Generic shellsort, from K&R (1st ed, p 58.), somewhat modified. 599 * v = Ptr to array/vector of objs 600 * n = # objs in the array 601 * s = size of each obj (must be multiples of a word size) 602 * f = ptr to function to compare two objs 603 * returns (-1 = less than, 0 = equal, 1 = greater than 604 */ 605 void 606 hxge_ksort(caddr_t v, int n, int s, int (*f) ()) 607 { 608 int g, i, j, ii; 609 unsigned int *p1, *p2; 610 unsigned int tmp; 611 612 /* No work to do */ 613 if (v == NULL || n <= 1) 614 return; 615 /* Sanity check on arguments */ 616 ASSERT(((uintptr_t)v & 0x3) == 0 && (s & 0x3) == 0); 617 ASSERT(s > 0); 618 619 for (g = n / 2; g > 0; g /= 2) { 620 for (i = g; i < n; i++) { 621 for (j = i - g; j >= 0 && 622 (*f) (v + j * s, v + (j + g) * s) == 1; j -= g) { 623 p1 = (unsigned *)(v + j * s); 624 p2 = (unsigned *)(v + (j + g) * s); 625 for (ii = 0; ii < s / 4; ii++) { 626 tmp = *p1; 627 *p1++ = *p2; 628 *p2++ = tmp; 629 } 630 } 631 } 632 } 633 } 634 635 /* 636 * Initialize data structures required for rxdma 637 * buffer dvma->vmem address lookup 638 */ 639 /*ARGSUSED*/ 640 static hxge_status_t 641 hxge_rxbuf_index_info_init(p_hxge_t hxgep, p_rx_rbr_ring_t rbrp) 642 { 643 int index; 644 rxring_info_t *ring_info; 645 int max_iteration = 0, max_index = 0; 646 647 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_rxbuf_index_info_init")); 648 649 ring_info = rbrp->ring_info; 650 ring_info->hint[0] = NO_HINT; 651 ring_info->hint[1] = NO_HINT; 652 ring_info->hint[2] = NO_HINT; 653 max_index = rbrp->num_blocks; 654 655 /* read the DVMA address information and sort it */ 656 /* do init of the information array */ 657 658 HXGE_DEBUG_MSG((hxgep, DMA2_CTL, 659 " hxge_rxbuf_index_info_init Sort ptrs")); 660 661 /* sort the array */ 662 hxge_ksort((void *) ring_info->buffer, max_index, 663 sizeof (rxbuf_index_info_t), hxge_sort_compare); 664 665 for (index = 0; index < max_index; index++) { 666 HXGE_DEBUG_MSG((hxgep, DMA2_CTL, 667 " hxge_rxbuf_index_info_init: sorted chunk %d " 668 " ioaddr $%p kaddr $%p size %x", 669 index, ring_info->buffer[index].dvma_addr, 670 ring_info->buffer[index].kaddr, 671 ring_info->buffer[index].buf_size)); 672 } 673 674 max_iteration = 0; 675 while (max_index >= (1ULL << max_iteration)) 676 max_iteration++; 677 ring_info->max_iterations = max_iteration + 1; 678 679 HXGE_DEBUG_MSG((hxgep, DMA2_CTL, 680 " hxge_rxbuf_index_info_init Find max iter %d", 681 ring_info->max_iterations)); 682 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_rxbuf_index_info_init")); 683 684 return (HXGE_OK); 685 } 686 687 /*ARGSUSED*/ 688 void 689 hxge_dump_rcr_entry(p_hxge_t hxgep, p_rcr_entry_t entry_p) 690 { 691 #ifdef HXGE_DEBUG 692 693 uint32_t bptr; 694 uint64_t pp; 695 696 bptr = entry_p->bits.pkt_buf_addr; 697 698 HXGE_DEBUG_MSG((hxgep, RX_CTL, 699 "\trcr entry $%p " 700 "\trcr entry 0x%0llx " 701 "\trcr entry 0x%08x " 702 "\trcr entry 0x%08x " 703 "\tvalue 0x%0llx\n" 704 "\tmulti = %d\n" 705 "\tpkt_type = 0x%x\n" 706 "\terror = 0x%04x\n" 707 "\tl2_len = %d\n" 708 "\tpktbufsize = %d\n" 709 "\tpkt_buf_addr = $%p\n" 710 "\tpkt_buf_addr (<< 6) = $%p\n", 711 entry_p, 712 *(int64_t *)entry_p, 713 *(int32_t *)entry_p, 714 *(int32_t *)((char *)entry_p + 32), 715 entry_p->value, 716 entry_p->bits.multi, 717 entry_p->bits.pkt_type, 718 entry_p->bits.error, 719 entry_p->bits.l2_len, 720 entry_p->bits.pktbufsz, 721 bptr, 722 entry_p->bits.pkt_buf_addr_l)); 723 724 pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) << 725 RCR_PKT_BUF_ADDR_SHIFT; 726 727 HXGE_DEBUG_MSG((hxgep, RX_CTL, "rcr pp 0x%llx l2 len %d", 728 pp, (*(int64_t *)entry_p >> 40) & 0x3fff)); 729 #endif 730 } 731 732 /*ARGSUSED*/ 733 void 734 hxge_rxdma_stop(p_hxge_t hxgep) 735 { 736 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop")); 737 738 (void) hxge_rx_vmac_disable(hxgep); 739 (void) hxge_rxdma_hw_mode(hxgep, HXGE_DMA_STOP); 740 741 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop")); 742 } 743 744 void 745 hxge_rxdma_stop_reinit(p_hxge_t hxgep) 746 { 747 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_reinit")); 748 749 (void) hxge_rxdma_stop(hxgep); 750 (void) hxge_uninit_rxdma_channels(hxgep); 751 (void) hxge_init_rxdma_channels(hxgep); 752 753 (void) hxge_rx_vmac_enable(hxgep); 754 755 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop_reinit")); 756 } 757 758 hxge_status_t 759 hxge_rxdma_hw_mode(p_hxge_t hxgep, boolean_t enable) 760 { 761 int i, ndmas; 762 uint16_t channel; 763 p_rx_rbr_rings_t rx_rbr_rings; 764 p_rx_rbr_ring_t *rbr_rings; 765 hpi_handle_t handle; 766 hpi_status_t rs = HPI_SUCCESS; 767 hxge_status_t status = HXGE_OK; 768 769 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 770 "==> hxge_rxdma_hw_mode: mode %d", enable)); 771 772 if (!(hxgep->drv_state & STATE_HW_INITIALIZED)) { 773 HXGE_DEBUG_MSG((hxgep, RX_CTL, 774 "<== hxge_rxdma_mode: not initialized")); 775 return (HXGE_ERROR); 776 } 777 778 rx_rbr_rings = hxgep->rx_rbr_rings; 779 if (rx_rbr_rings == NULL) { 780 HXGE_DEBUG_MSG((hxgep, RX_CTL, 781 "<== hxge_rxdma_mode: NULL ring pointer")); 782 return (HXGE_ERROR); 783 } 784 785 if (rx_rbr_rings->rbr_rings == NULL) { 786 HXGE_DEBUG_MSG((hxgep, RX_CTL, 787 "<== hxge_rxdma_mode: NULL rbr rings pointer")); 788 return (HXGE_ERROR); 789 } 790 791 ndmas = rx_rbr_rings->ndmas; 792 if (!ndmas) { 793 HXGE_DEBUG_MSG((hxgep, RX_CTL, 794 "<== hxge_rxdma_mode: no channel")); 795 return (HXGE_ERROR); 796 } 797 798 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 799 "==> hxge_rxdma_mode (ndmas %d)", ndmas)); 800 801 rbr_rings = rx_rbr_rings->rbr_rings; 802 803 handle = HXGE_DEV_HPI_HANDLE(hxgep); 804 805 for (i = 0; i < ndmas; i++) { 806 if (rbr_rings == NULL || rbr_rings[i] == NULL) { 807 continue; 808 } 809 channel = rbr_rings[i]->rdc; 810 if (enable) { 811 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 812 "==> hxge_rxdma_hw_mode: channel %d (enable)", 813 channel)); 814 rs = hpi_rxdma_cfg_rdc_enable(handle, channel); 815 } else { 816 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 817 "==> hxge_rxdma_hw_mode: channel %d (disable)", 818 channel)); 819 rs = hpi_rxdma_cfg_rdc_disable(handle, channel); 820 } 821 } 822 823 status = ((rs == HPI_SUCCESS) ? HXGE_OK : HXGE_ERROR | rs); 824 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 825 "<== hxge_rxdma_hw_mode: status 0x%x", status)); 826 827 return (status); 828 } 829 830 int 831 hxge_rxdma_get_ring_index(p_hxge_t hxgep, uint16_t channel) 832 { 833 int i, ndmas; 834 uint16_t rdc; 835 p_rx_rbr_rings_t rx_rbr_rings; 836 p_rx_rbr_ring_t *rbr_rings; 837 838 HXGE_DEBUG_MSG((hxgep, RX_CTL, 839 "==> hxge_rxdma_get_ring_index: channel %d", channel)); 840 841 rx_rbr_rings = hxgep->rx_rbr_rings; 842 if (rx_rbr_rings == NULL) { 843 HXGE_DEBUG_MSG((hxgep, RX_CTL, 844 "<== hxge_rxdma_get_ring_index: NULL ring pointer")); 845 return (-1); 846 } 847 848 ndmas = rx_rbr_rings->ndmas; 849 if (!ndmas) { 850 HXGE_DEBUG_MSG((hxgep, RX_CTL, 851 "<== hxge_rxdma_get_ring_index: no channel")); 852 return (-1); 853 } 854 855 HXGE_DEBUG_MSG((hxgep, RX_CTL, 856 "==> hxge_rxdma_get_ring_index (ndmas %d)", ndmas)); 857 858 rbr_rings = rx_rbr_rings->rbr_rings; 859 for (i = 0; i < ndmas; i++) { 860 rdc = rbr_rings[i]->rdc; 861 if (channel == rdc) { 862 HXGE_DEBUG_MSG((hxgep, RX_CTL, 863 "==> hxge_rxdma_get_rbr_ring: " 864 "channel %d (index %d) " 865 "ring %d", channel, i, rbr_rings[i])); 866 867 return (i); 868 } 869 } 870 871 HXGE_DEBUG_MSG((hxgep, RX_CTL, 872 "<== hxge_rxdma_get_rbr_ring_index: not found")); 873 874 return (-1); 875 } 876 877 /* 878 * Static functions start here. 879 */ 880 static p_rx_msg_t 881 hxge_allocb(size_t size, uint32_t pri, p_hxge_dma_common_t dmabuf_p) 882 { 883 p_rx_msg_t hxge_mp = NULL; 884 p_hxge_dma_common_t dmamsg_p; 885 uchar_t *buffer; 886 887 hxge_mp = KMEM_ZALLOC(sizeof (rx_msg_t), KM_NOSLEEP); 888 if (hxge_mp == NULL) { 889 HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, 890 "Allocation of a rx msg failed.")); 891 goto hxge_allocb_exit; 892 } 893 894 hxge_mp->use_buf_pool = B_FALSE; 895 if (dmabuf_p) { 896 hxge_mp->use_buf_pool = B_TRUE; 897 898 dmamsg_p = (p_hxge_dma_common_t)&hxge_mp->buf_dma; 899 *dmamsg_p = *dmabuf_p; 900 dmamsg_p->nblocks = 1; 901 dmamsg_p->block_size = size; 902 dmamsg_p->alength = size; 903 buffer = (uchar_t *)dmabuf_p->kaddrp; 904 905 dmabuf_p->kaddrp = (void *)((char *)dmabuf_p->kaddrp + size); 906 dmabuf_p->ioaddr_pp = (void *) 907 ((char *)dmabuf_p->ioaddr_pp + size); 908 909 dmabuf_p->alength -= size; 910 dmabuf_p->offset += size; 911 dmabuf_p->dma_cookie.dmac_laddress += size; 912 dmabuf_p->dma_cookie.dmac_size -= size; 913 } else { 914 buffer = KMEM_ALLOC(size, KM_NOSLEEP); 915 if (buffer == NULL) { 916 HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, 917 "Allocation of a receive page failed.")); 918 goto hxge_allocb_fail1; 919 } 920 } 921 922 hxge_mp->rx_mblk_p = desballoc(buffer, size, pri, &hxge_mp->freeb); 923 if (hxge_mp->rx_mblk_p == NULL) { 924 HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, "desballoc failed.")); 925 goto hxge_allocb_fail2; 926 } 927 hxge_mp->buffer = buffer; 928 hxge_mp->block_size = size; 929 hxge_mp->freeb.free_func = (void (*) ()) hxge_freeb; 930 hxge_mp->freeb.free_arg = (caddr_t)hxge_mp; 931 hxge_mp->ref_cnt = 1; 932 hxge_mp->free = B_TRUE; 933 hxge_mp->rx_use_bcopy = B_FALSE; 934 935 atomic_inc_32(&hxge_mblks_pending); 936 937 goto hxge_allocb_exit; 938 939 hxge_allocb_fail2: 940 if (!hxge_mp->use_buf_pool) { 941 KMEM_FREE(buffer, size); 942 } 943 hxge_allocb_fail1: 944 KMEM_FREE(hxge_mp, sizeof (rx_msg_t)); 945 hxge_mp = NULL; 946 947 hxge_allocb_exit: 948 return (hxge_mp); 949 } 950 951 p_mblk_t 952 hxge_dupb(p_rx_msg_t hxge_mp, uint_t offset, size_t size) 953 { 954 p_mblk_t mp; 955 956 HXGE_DEBUG_MSG((NULL, MEM_CTL, "==> hxge_dupb")); 957 HXGE_DEBUG_MSG((NULL, MEM_CTL, "hxge_mp = $%p " 958 "offset = 0x%08X " "size = 0x%08X", hxge_mp, offset, size)); 959 960 mp = desballoc(&hxge_mp->buffer[offset], size, 0, &hxge_mp->freeb); 961 if (mp == NULL) { 962 HXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 963 goto hxge_dupb_exit; 964 } 965 966 atomic_inc_32(&hxge_mp->ref_cnt); 967 968 hxge_dupb_exit: 969 HXGE_DEBUG_MSG((NULL, MEM_CTL, "<== hxge_dupb mp = $%p", hxge_mp)); 970 return (mp); 971 } 972 973 p_mblk_t 974 hxge_dupb_bcopy(p_rx_msg_t hxge_mp, uint_t offset, size_t size) 975 { 976 p_mblk_t mp; 977 uchar_t *dp; 978 979 mp = allocb(size + HXGE_RXBUF_EXTRA, 0); 980 if (mp == NULL) { 981 HXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 982 goto hxge_dupb_bcopy_exit; 983 } 984 dp = mp->b_rptr = mp->b_rptr + HXGE_RXBUF_EXTRA; 985 bcopy((void *) &hxge_mp->buffer[offset], dp, size); 986 mp->b_wptr = dp + size; 987 988 hxge_dupb_bcopy_exit: 989 990 HXGE_DEBUG_MSG((NULL, MEM_CTL, "<== hxge_dupb mp = $%p", hxge_mp)); 991 992 return (mp); 993 } 994 995 void hxge_post_page(p_hxge_t hxgep, p_rx_rbr_ring_t rx_rbr_p, 996 p_rx_msg_t rx_msg_p); 997 998 void 999 hxge_post_page(p_hxge_t hxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p) 1000 { 1001 hpi_handle_t handle; 1002 uint64_t rbr_qlen, blocks_to_post = 0ULL; 1003 1004 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_post_page")); 1005 1006 /* Reuse this buffer */ 1007 rx_msg_p->free = B_FALSE; 1008 rx_msg_p->cur_usage_cnt = 0; 1009 rx_msg_p->max_usage_cnt = 0; 1010 rx_msg_p->pkt_buf_size = 0; 1011 1012 if (rx_rbr_p->rbr_use_bcopy) { 1013 rx_msg_p->rx_use_bcopy = B_FALSE; 1014 atomic_dec_32(&rx_rbr_p->rbr_consumed); 1015 } 1016 1017 /* 1018 * Get the rbr header pointer and its offset index. 1019 */ 1020 rx_rbr_p->rbr_wr_index = ((rx_rbr_p->rbr_wr_index + 1) & 1021 rx_rbr_p->rbr_wrap_mask); 1022 rx_rbr_p->rbr_desc_vp[rx_rbr_p->rbr_wr_index] = rx_msg_p->shifted_addr; 1023 1024 /* 1025 * Don't post when index is close to 0 or near the max to reduce the 1026 * number rbr_emepty errors 1027 */ 1028 rx_rbr_p->pages_to_post++; 1029 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1030 1031 /* 1032 * False RBR Empty Workaround 1033 */ 1034 RXDMA_REG_READ64(handle, RDC_RBR_QLEN, rx_rbr_p->rdc, &rbr_qlen); 1035 rbr_qlen = rbr_qlen & 0xffff; 1036 1037 if ((rbr_qlen > 0) && 1038 (rbr_qlen < HXGE_RXDMA_RBB_THRESHOLD(rx_rbr_p->rbb_max))) { 1039 blocks_to_post = 1040 HXGE_RXDMA_RBB_MAX(rx_rbr_p->rbb_max) - rbr_qlen; 1041 } 1042 1043 /* 1044 * Clamp posting to what we have available. 1045 */ 1046 if ((blocks_to_post > 0) && 1047 (blocks_to_post > rx_rbr_p->pages_to_post)) { 1048 blocks_to_post = rx_rbr_p->pages_to_post; 1049 } 1050 1051 /* 1052 * Post blocks to the hardware, if any is available. 1053 */ 1054 if (blocks_to_post > 0) { 1055 hpi_rxdma_rdc_rbr_kick(handle, rx_rbr_p->rdc, blocks_to_post); 1056 rx_rbr_p->pages_to_post -= blocks_to_post; 1057 } 1058 1059 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1060 "<== hxge_post_page (channel %d post_next_index %d)", 1061 rx_rbr_p->rdc, rx_rbr_p->rbr_wr_index)); 1062 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_post_page")); 1063 } 1064 1065 void 1066 hxge_freeb(p_rx_msg_t rx_msg_p) 1067 { 1068 size_t size; 1069 uchar_t *buffer = NULL; 1070 int ref_cnt; 1071 boolean_t free_state = B_FALSE; 1072 rx_rbr_ring_t *ring = rx_msg_p->rx_rbr_p; 1073 1074 HXGE_DEBUG_MSG((NULL, MEM2_CTL, "==> hxge_freeb")); 1075 HXGE_DEBUG_MSG((NULL, MEM2_CTL, 1076 "hxge_freeb:rx_msg_p = $%p (block pending %d)", 1077 rx_msg_p, hxge_mblks_pending)); 1078 1079 MUTEX_ENTER(&ring->post_lock); 1080 1081 /* 1082 * First we need to get the free state, then 1083 * atomic decrement the reference count to prevent 1084 * the race condition with the interrupt thread that 1085 * is processing a loaned up buffer block. 1086 */ 1087 free_state = rx_msg_p->free; 1088 1089 ref_cnt = atomic_add_32_nv(&rx_msg_p->ref_cnt, -1); 1090 if (!ref_cnt) { 1091 atomic_dec_32(&hxge_mblks_pending); 1092 1093 buffer = rx_msg_p->buffer; 1094 size = rx_msg_p->block_size; 1095 1096 HXGE_DEBUG_MSG((NULL, MEM2_CTL, "hxge_freeb: " 1097 "will free: rx_msg_p = $%p (block pending %d)", 1098 rx_msg_p, hxge_mblks_pending)); 1099 1100 if (!rx_msg_p->use_buf_pool) { 1101 KMEM_FREE(buffer, size); 1102 } 1103 1104 KMEM_FREE(rx_msg_p, sizeof (rx_msg_t)); 1105 /* Decrement the receive buffer ring's reference count, too. */ 1106 atomic_dec_32(&ring->rbr_ref_cnt); 1107 1108 /* 1109 * Free the receive buffer ring, iff 1110 * 1. all the receive buffers have been freed 1111 * 2. and we are in the proper state (that is, 1112 * we are not UNMAPPING). 1113 */ 1114 if (ring->rbr_ref_cnt == 0 && ring->rbr_state == RBR_UNMAPPED) { 1115 KMEM_FREE(ring, sizeof (*ring)); 1116 } 1117 goto hxge_freeb_exit; 1118 } 1119 1120 /* 1121 * Repost buffer. 1122 */ 1123 if (free_state && (ref_cnt == 1)) { 1124 HXGE_DEBUG_MSG((NULL, RX_CTL, 1125 "hxge_freeb: post page $%p:", rx_msg_p)); 1126 if (ring->rbr_state == RBR_POSTING) 1127 hxge_post_page(rx_msg_p->hxgep, ring, rx_msg_p); 1128 } 1129 1130 hxge_freeb_exit: 1131 MUTEX_EXIT(&ring->post_lock); 1132 HXGE_DEBUG_MSG((NULL, MEM2_CTL, "<== hxge_freeb")); 1133 } 1134 1135 uint_t 1136 hxge_rx_intr(caddr_t arg1, caddr_t arg2) 1137 { 1138 p_hxge_ldv_t ldvp = (p_hxge_ldv_t)arg1; 1139 p_hxge_t hxgep = (p_hxge_t)arg2; 1140 p_hxge_ldg_t ldgp; 1141 uint8_t channel; 1142 hpi_handle_t handle; 1143 rdc_stat_t cs; 1144 uint_t serviced = DDI_INTR_UNCLAIMED; 1145 1146 if (ldvp == NULL) { 1147 HXGE_DEBUG_MSG((NULL, RX_INT_CTL, 1148 "<== hxge_rx_intr: arg2 $%p arg1 $%p", hxgep, ldvp)); 1149 return (DDI_INTR_UNCLAIMED); 1150 } 1151 1152 if (arg2 == NULL || (void *) ldvp->hxgep != arg2) { 1153 hxgep = ldvp->hxgep; 1154 } 1155 1156 /* 1157 * If the interface is not started, just swallow the interrupt 1158 * for the logical device and don't rearm it. 1159 */ 1160 if (hxgep->hxge_mac_state != HXGE_MAC_STARTED) 1161 return (DDI_INTR_CLAIMED); 1162 1163 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1164 "==> hxge_rx_intr: arg2 $%p arg1 $%p", hxgep, ldvp)); 1165 1166 /* 1167 * This interrupt handler is for a specific receive dma channel. 1168 */ 1169 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1170 1171 /* 1172 * Get the control and status for this channel. 1173 */ 1174 channel = ldvp->channel; 1175 ldgp = ldvp->ldgp; 1176 RXDMA_REG_READ64(handle, RDC_STAT, channel, &cs.value); 1177 1178 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_intr:channel %d " 1179 "cs 0x%016llx rcrto 0x%x rcrthres %x", 1180 channel, cs.value, cs.bits.rcr_to, cs.bits.rcr_thres)); 1181 1182 hxge_rx_pkts_vring(hxgep, ldvp->vdma_index, ldvp, cs); 1183 serviced = DDI_INTR_CLAIMED; 1184 1185 /* error events. */ 1186 if (cs.value & RDC_STAT_ERROR) { 1187 (void) hxge_rx_err_evnts(hxgep, ldvp->vdma_index, ldvp, cs); 1188 } 1189 1190 hxge_intr_exit: 1191 /* 1192 * Enable the mailbox update interrupt if we want to use mailbox. We 1193 * probably don't need to use mailbox as it only saves us one pio read. 1194 * Also write 1 to rcrthres and rcrto to clear these two edge triggered 1195 * bits. 1196 */ 1197 cs.value &= RDC_STAT_WR1C; 1198 cs.bits.mex = 1; 1199 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); 1200 1201 /* 1202 * Rearm this logical group if this is a single device group. 1203 */ 1204 if (ldgp->nldvs == 1) { 1205 ld_intr_mgmt_t mgm; 1206 1207 mgm.value = 0; 1208 mgm.bits.arm = 1; 1209 mgm.bits.timer = ldgp->ldg_timer; 1210 HXGE_REG_WR32(handle, 1211 LD_INTR_MGMT + LDSV_OFFSET(ldgp->ldg), mgm.value); 1212 } 1213 1214 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1215 "<== hxge_rx_intr: serviced %d", serviced)); 1216 1217 return (serviced); 1218 } 1219 1220 static void 1221 hxge_rx_pkts_vring(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp, 1222 rdc_stat_t cs) 1223 { 1224 p_mblk_t mp; 1225 p_rx_rcr_ring_t rcrp; 1226 1227 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts_vring")); 1228 if ((mp = hxge_rx_pkts(hxgep, vindex, ldvp, &rcrp, cs)) == NULL) { 1229 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1230 "<== hxge_rx_pkts_vring: no mp")); 1231 return; 1232 } 1233 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_pkts_vring: $%p", mp)); 1234 1235 #ifdef HXGE_DEBUG 1236 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1237 "==> hxge_rx_pkts_vring:calling mac_rx (NEMO) " 1238 "LEN %d mp $%p mp->b_next $%p rcrp $%p " 1239 "mac_handle $%p", 1240 (mp->b_wptr - mp->b_rptr), mp, mp->b_next, 1241 rcrp, rcrp->rcr_mac_handle)); 1242 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1243 "==> hxge_rx_pkts_vring: dump packets " 1244 "(mp $%p b_rptr $%p b_wptr $%p):\n %s", 1245 mp, mp->b_rptr, mp->b_wptr, 1246 hxge_dump_packet((char *)mp->b_rptr, 64))); 1247 1248 if (mp->b_cont) { 1249 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1250 "==> hxge_rx_pkts_vring: dump b_cont packets " 1251 "(mp->b_cont $%p b_rptr $%p b_wptr $%p):\n %s", 1252 mp->b_cont, mp->b_cont->b_rptr, mp->b_cont->b_wptr, 1253 hxge_dump_packet((char *)mp->b_cont->b_rptr, 1254 mp->b_cont->b_wptr - mp->b_cont->b_rptr))); 1255 } 1256 if (mp->b_next) { 1257 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1258 "==> hxge_rx_pkts_vring: dump next packets " 1259 "(b_rptr $%p): %s", 1260 mp->b_next->b_rptr, 1261 hxge_dump_packet((char *)mp->b_next->b_rptr, 64))); 1262 } 1263 #endif 1264 1265 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1266 "==> hxge_rx_pkts_vring: send packet to stack")); 1267 mac_rx(hxgep->mach, rcrp->rcr_mac_handle, mp); 1268 1269 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rx_pkts_vring")); 1270 } 1271 1272 /*ARGSUSED*/ 1273 mblk_t * 1274 hxge_rx_pkts(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp, 1275 p_rx_rcr_ring_t *rcrp, rdc_stat_t cs) 1276 { 1277 hpi_handle_t handle; 1278 uint8_t channel; 1279 p_rx_rcr_rings_t rx_rcr_rings; 1280 p_rx_rcr_ring_t rcr_p; 1281 uint32_t comp_rd_index; 1282 p_rcr_entry_t rcr_desc_rd_head_p; 1283 p_rcr_entry_t rcr_desc_rd_head_pp; 1284 p_mblk_t nmp, mp_cont, head_mp, *tail_mp; 1285 uint16_t qlen, nrcr_read, npkt_read; 1286 uint32_t qlen_hw; 1287 uint32_t invalid_rcr_entry; 1288 boolean_t multi; 1289 rdc_rcr_cfg_b_t rcr_cfg_b; 1290 #if defined(_BIG_ENDIAN) 1291 hpi_status_t rs = HPI_SUCCESS; 1292 #else 1293 p_rx_mbox_t rx_mboxp; 1294 p_rxdma_mailbox_t mboxp; 1295 #endif 1296 1297 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts:vindex %d " 1298 "channel %d", vindex, ldvp->channel)); 1299 1300 if (!(hxgep->drv_state & STATE_HW_INITIALIZED)) { 1301 return (NULL); 1302 } 1303 1304 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1305 rx_rcr_rings = hxgep->rx_rcr_rings; 1306 rcr_p = rx_rcr_rings->rcr_rings[vindex]; 1307 channel = rcr_p->rdc; 1308 if (channel != ldvp->channel) { 1309 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts:index %d " 1310 "channel %d, and rcr channel %d not matched.", 1311 vindex, ldvp->channel, channel)); 1312 return (NULL); 1313 } 1314 1315 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1316 "==> hxge_rx_pkts: START: rcr channel %d " 1317 "head_p $%p head_pp $%p index %d ", 1318 channel, rcr_p->rcr_desc_rd_head_p, 1319 rcr_p->rcr_desc_rd_head_pp, rcr_p->comp_rd_index)); 1320 1321 #if defined(_BIG_ENDIAN) 1322 rs = hpi_rxdma_rdc_rcr_qlen_get(handle, channel, &qlen); 1323 if (rs != HPI_SUCCESS) { 1324 return (NULL); 1325 } 1326 #else 1327 rx_mboxp = hxgep->rx_mbox_areas_p->rxmbox_areas[channel]; 1328 mboxp = (p_rxdma_mailbox_t)rx_mboxp->rx_mbox.kaddrp; 1329 qlen = mboxp->rcrstat_a.bits.qlen; 1330 #endif 1331 1332 if (!qlen) { 1333 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1334 "<== hxge_rx_pkts:rcr channel %d qlen %d (no pkts)", 1335 channel, qlen)); 1336 return (NULL); 1337 } 1338 1339 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_pkts:rcr channel %d " 1340 "qlen %d", channel, qlen)); 1341 1342 comp_rd_index = rcr_p->comp_rd_index; 1343 1344 rcr_desc_rd_head_p = rcr_p->rcr_desc_rd_head_p; 1345 rcr_desc_rd_head_pp = rcr_p->rcr_desc_rd_head_pp; 1346 nrcr_read = npkt_read = 0; 1347 1348 /* 1349 * Number of packets queued (The jumbo or multi packet will be counted 1350 * as only one paccket and it may take up more than one completion 1351 * entry). 1352 */ 1353 qlen_hw = (qlen < hxge_max_rx_pkts) ? qlen : hxge_max_rx_pkts; 1354 head_mp = NULL; 1355 tail_mp = &head_mp; 1356 nmp = mp_cont = NULL; 1357 multi = B_FALSE; 1358 1359 while (qlen_hw) { 1360 #ifdef HXGE_DEBUG 1361 hxge_dump_rcr_entry(hxgep, rcr_desc_rd_head_p); 1362 #endif 1363 /* 1364 * Process one completion ring entry. 1365 */ 1366 invalid_rcr_entry = 0; 1367 hxge_receive_packet(hxgep, 1368 rcr_p, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont, 1369 &invalid_rcr_entry); 1370 if (invalid_rcr_entry != 0) { 1371 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1372 "Channel %d could only read 0x%x packets, " 1373 "but 0x%x pending\n", channel, npkt_read, qlen_hw)); 1374 break; 1375 } 1376 1377 /* 1378 * message chaining modes (nemo msg chaining) 1379 */ 1380 if (nmp) { 1381 nmp->b_next = NULL; 1382 if (!multi && !mp_cont) { /* frame fits a partition */ 1383 *tail_mp = nmp; 1384 tail_mp = &nmp->b_next; 1385 nmp = NULL; 1386 } else if (multi && !mp_cont) { /* first segment */ 1387 *tail_mp = nmp; 1388 tail_mp = &nmp->b_cont; 1389 } else if (multi && mp_cont) { /* mid of multi segs */ 1390 *tail_mp = mp_cont; 1391 tail_mp = &mp_cont->b_cont; 1392 } else if (!multi && mp_cont) { /* last segment */ 1393 *tail_mp = mp_cont; 1394 tail_mp = &nmp->b_next; 1395 nmp = NULL; 1396 } 1397 } 1398 1399 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1400 "==> hxge_rx_pkts: loop: rcr channel %d " 1401 "before updating: multi %d " 1402 "nrcr_read %d " 1403 "npk read %d " 1404 "head_pp $%p index %d ", 1405 channel, multi, 1406 nrcr_read, npkt_read, rcr_desc_rd_head_pp, comp_rd_index)); 1407 1408 if (!multi) { 1409 qlen_hw--; 1410 npkt_read++; 1411 } 1412 1413 /* 1414 * Update the next read entry. 1415 */ 1416 comp_rd_index = NEXT_ENTRY(comp_rd_index, 1417 rcr_p->comp_wrap_mask); 1418 1419 rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p, 1420 rcr_p->rcr_desc_first_p, rcr_p->rcr_desc_last_p); 1421 1422 nrcr_read++; 1423 1424 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1425 "<== hxge_rx_pkts: (SAM, process one packet) " 1426 "nrcr_read %d", nrcr_read)); 1427 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1428 "==> hxge_rx_pkts: loop: rcr channel %d " 1429 "multi %d nrcr_read %d npk read %d head_pp $%p index %d ", 1430 channel, multi, nrcr_read, npkt_read, rcr_desc_rd_head_pp, 1431 comp_rd_index)); 1432 } 1433 1434 rcr_p->rcr_desc_rd_head_pp = rcr_desc_rd_head_pp; 1435 rcr_p->comp_rd_index = comp_rd_index; 1436 rcr_p->rcr_desc_rd_head_p = rcr_desc_rd_head_p; 1437 1438 #if !defined(_BIG_ENDIAN) 1439 /* Adjust the mailbox queue length for a hardware bug workaround */ 1440 mboxp->rcrstat_a.bits.qlen -= npkt_read; 1441 #endif 1442 1443 if ((hxgep->intr_timeout != rcr_p->intr_timeout) || 1444 (hxgep->intr_threshold != rcr_p->intr_threshold)) { 1445 rcr_p->intr_timeout = hxgep->intr_timeout; 1446 rcr_p->intr_threshold = hxgep->intr_threshold; 1447 rcr_cfg_b.value = 0x0ULL; 1448 if (rcr_p->intr_timeout) 1449 rcr_cfg_b.bits.entout = 1; 1450 rcr_cfg_b.bits.timeout = rcr_p->intr_timeout; 1451 rcr_cfg_b.bits.pthres = rcr_p->intr_threshold; 1452 RXDMA_REG_WRITE64(handle, RDC_RCR_CFG_B, 1453 channel, rcr_cfg_b.value); 1454 } 1455 1456 cs.bits.pktread = npkt_read; 1457 cs.bits.ptrread = nrcr_read; 1458 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); 1459 1460 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1461 "==> hxge_rx_pkts: EXIT: rcr channel %d " 1462 "head_pp $%p index %016llx ", 1463 channel, rcr_p->rcr_desc_rd_head_pp, rcr_p->comp_rd_index)); 1464 1465 /* 1466 * Update RCR buffer pointer read and number of packets read. 1467 */ 1468 1469 *rcrp = rcr_p; 1470 1471 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "<== hxge_rx_pkts")); 1472 1473 return (head_mp); 1474 } 1475 1476 #define RCR_ENTRY_PATTERN 0x5a5a6b6b7c7c8d8dULL 1477 1478 /*ARGSUSED*/ 1479 void 1480 hxge_receive_packet(p_hxge_t hxgep, 1481 p_rx_rcr_ring_t rcr_p, p_rcr_entry_t rcr_desc_rd_head_p, 1482 boolean_t *multi_p, mblk_t **mp, mblk_t **mp_cont, 1483 uint32_t *invalid_rcr_entry) 1484 { 1485 p_mblk_t nmp = NULL; 1486 uint64_t multi; 1487 uint8_t channel; 1488 1489 boolean_t first_entry = B_TRUE; 1490 boolean_t is_tcp_udp = B_FALSE; 1491 boolean_t buffer_free = B_FALSE; 1492 boolean_t error_send_up = B_FALSE; 1493 uint8_t error_type; 1494 uint16_t l2_len; 1495 uint16_t skip_len; 1496 uint8_t pktbufsz_type; 1497 uint64_t rcr_entry; 1498 uint64_t *pkt_buf_addr_pp; 1499 uint64_t *pkt_buf_addr_p; 1500 uint32_t buf_offset; 1501 uint32_t bsize; 1502 uint32_t msg_index; 1503 p_rx_rbr_ring_t rx_rbr_p; 1504 p_rx_msg_t *rx_msg_ring_p; 1505 p_rx_msg_t rx_msg_p; 1506 1507 uint16_t sw_offset_bytes = 0, hdr_size = 0; 1508 hxge_status_t status = HXGE_OK; 1509 boolean_t is_valid = B_FALSE; 1510 p_hxge_rx_ring_stats_t rdc_stats; 1511 uint32_t bytes_read; 1512 1513 uint64_t pkt_type; 1514 1515 channel = rcr_p->rdc; 1516 1517 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> hxge_receive_packet")); 1518 1519 first_entry = (*mp == NULL) ? B_TRUE : B_FALSE; 1520 rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); 1521 1522 /* Verify the content of the rcr_entry for a hardware bug workaround */ 1523 if ((rcr_entry == 0x0) || (rcr_entry == RCR_ENTRY_PATTERN)) { 1524 *invalid_rcr_entry = 1; 1525 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "hxge_receive_packet " 1526 "Channel %d invalid RCR entry 0x%llx found, returning\n", 1527 channel, (long long) rcr_entry)); 1528 return; 1529 } 1530 *((uint64_t *)rcr_desc_rd_head_p) = RCR_ENTRY_PATTERN; 1531 1532 multi = (rcr_entry & RCR_MULTI_MASK); 1533 pkt_type = (rcr_entry & RCR_PKT_TYPE_MASK); 1534 1535 error_type = ((rcr_entry & RCR_ERROR_MASK) >> RCR_ERROR_SHIFT); 1536 l2_len = ((rcr_entry & RCR_L2_LEN_MASK) >> RCR_L2_LEN_SHIFT); 1537 1538 /* 1539 * Hardware does not strip the CRC due bug ID 11451 where 1540 * the hardware mis handles minimum size packets. 1541 */ 1542 l2_len -= ETHERFCSL; 1543 1544 pktbufsz_type = ((rcr_entry & RCR_PKTBUFSZ_MASK) >> 1545 RCR_PKTBUFSZ_SHIFT); 1546 #if defined(__i386) 1547 pkt_buf_addr_pp = (uint64_t *)(uint32_t)((rcr_entry & 1548 RCR_PKT_BUF_ADDR_MASK) << RCR_PKT_BUF_ADDR_SHIFT); 1549 #else 1550 pkt_buf_addr_pp = (uint64_t *)((rcr_entry & RCR_PKT_BUF_ADDR_MASK) << 1551 RCR_PKT_BUF_ADDR_SHIFT); 1552 #endif 1553 1554 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1555 "==> hxge_receive_packet: entryp $%p entry 0x%0llx " 1556 "pkt_buf_addr_pp $%p l2_len %d multi %d " 1557 "error_type 0x%x pkt_type 0x%x " 1558 "pktbufsz_type %d ", 1559 rcr_desc_rd_head_p, rcr_entry, pkt_buf_addr_pp, l2_len, 1560 multi, error_type, pkt_type, pktbufsz_type)); 1561 1562 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1563 "==> hxge_receive_packet: entryp $%p entry 0x%0llx " 1564 "pkt_buf_addr_pp $%p l2_len %d multi %d " 1565 "error_type 0x%x pkt_type 0x%x ", rcr_desc_rd_head_p, 1566 rcr_entry, pkt_buf_addr_pp, l2_len, multi, error_type, pkt_type)); 1567 1568 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1569 "==> (rbr) hxge_receive_packet: entry 0x%0llx " 1570 "full pkt_buf_addr_pp $%p l2_len %d", 1571 rcr_entry, pkt_buf_addr_pp, l2_len)); 1572 1573 /* get the stats ptr */ 1574 rdc_stats = rcr_p->rdc_stats; 1575 if (l2_len > (STD_FRAME_SIZE - ETHERFCSL)) 1576 rdc_stats->jumbo_pkts++; 1577 1578 if (!l2_len) { 1579 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1580 "<== hxge_receive_packet: failed: l2 length is 0.")); 1581 return; 1582 } 1583 1584 /* shift 6 bits to get the full io address */ 1585 #if defined(__i386) 1586 pkt_buf_addr_pp = (uint64_t *)((uint32_t)pkt_buf_addr_pp << 1587 RCR_PKT_BUF_ADDR_SHIFT_FULL); 1588 #else 1589 pkt_buf_addr_pp = (uint64_t *)((uint64_t)pkt_buf_addr_pp << 1590 RCR_PKT_BUF_ADDR_SHIFT_FULL); 1591 #endif 1592 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1593 "==> (rbr) hxge_receive_packet: entry 0x%0llx " 1594 "full pkt_buf_addr_pp $%p l2_len %d", 1595 rcr_entry, pkt_buf_addr_pp, l2_len)); 1596 1597 rx_rbr_p = rcr_p->rx_rbr_p; 1598 rx_msg_ring_p = rx_rbr_p->rx_msg_ring; 1599 1600 if (first_entry) { 1601 hdr_size = (rcr_p->full_hdr_flag ? RXDMA_HDR_SIZE_FULL : 1602 RXDMA_HDR_SIZE_DEFAULT); 1603 1604 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1605 "==> hxge_receive_packet: first entry 0x%016llx " 1606 "pkt_buf_addr_pp $%p l2_len %d hdr %d", 1607 rcr_entry, pkt_buf_addr_pp, l2_len, hdr_size)); 1608 } 1609 1610 MUTEX_ENTER(&rcr_p->lock); 1611 MUTEX_ENTER(&rx_rbr_p->lock); 1612 1613 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1614 "==> (rbr 1) hxge_receive_packet: entry 0x%0llx " 1615 "full pkt_buf_addr_pp $%p l2_len %d", 1616 rcr_entry, pkt_buf_addr_pp, l2_len)); 1617 1618 /* 1619 * Packet buffer address in the completion entry points to the starting 1620 * buffer address (offset 0). Use the starting buffer address to locate 1621 * the corresponding kernel address. 1622 */ 1623 status = hxge_rxbuf_pp_to_vp(hxgep, rx_rbr_p, 1624 pktbufsz_type, pkt_buf_addr_pp, &pkt_buf_addr_p, 1625 &buf_offset, &msg_index); 1626 1627 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1628 "==> (rbr 2) hxge_receive_packet: entry 0x%0llx " 1629 "full pkt_buf_addr_pp $%p l2_len %d", 1630 rcr_entry, pkt_buf_addr_pp, l2_len)); 1631 1632 if (status != HXGE_OK) { 1633 MUTEX_EXIT(&rx_rbr_p->lock); 1634 MUTEX_EXIT(&rcr_p->lock); 1635 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1636 "<== hxge_receive_packet: found vaddr failed %d", status)); 1637 return; 1638 } 1639 1640 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1641 "==> (rbr 3) hxge_receive_packet: entry 0x%0llx " 1642 "full pkt_buf_addr_pp $%p l2_len %d", 1643 rcr_entry, pkt_buf_addr_pp, l2_len)); 1644 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1645 "==> (rbr 4 msgindex %d) hxge_receive_packet: entry 0x%0llx " 1646 "full pkt_buf_addr_pp $%p l2_len %d", 1647 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 1648 1649 if (msg_index >= rx_rbr_p->tnblocks) { 1650 MUTEX_EXIT(&rx_rbr_p->lock); 1651 MUTEX_EXIT(&rcr_p->lock); 1652 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1653 "==> hxge_receive_packet: FATAL msg_index (%d) " 1654 "should be smaller than tnblocks (%d)\n", 1655 msg_index, rx_rbr_p->tnblocks)); 1656 return; 1657 } 1658 1659 rx_msg_p = rx_msg_ring_p[msg_index]; 1660 1661 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1662 "==> (rbr 4 msgindex %d) hxge_receive_packet: entry 0x%0llx " 1663 "full pkt_buf_addr_pp $%p l2_len %d", 1664 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 1665 1666 switch (pktbufsz_type) { 1667 case RCR_PKTBUFSZ_0: 1668 bsize = rx_rbr_p->pkt_buf_size0_bytes; 1669 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1670 "==> hxge_receive_packet: 0 buf %d", bsize)); 1671 break; 1672 case RCR_PKTBUFSZ_1: 1673 bsize = rx_rbr_p->pkt_buf_size1_bytes; 1674 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1675 "==> hxge_receive_packet: 1 buf %d", bsize)); 1676 break; 1677 case RCR_PKTBUFSZ_2: 1678 bsize = rx_rbr_p->pkt_buf_size2_bytes; 1679 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1680 "==> hxge_receive_packet: 2 buf %d", bsize)); 1681 break; 1682 case RCR_SINGLE_BLOCK: 1683 bsize = rx_msg_p->block_size; 1684 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1685 "==> hxge_receive_packet: single %d", bsize)); 1686 1687 break; 1688 default: 1689 MUTEX_EXIT(&rx_rbr_p->lock); 1690 MUTEX_EXIT(&rcr_p->lock); 1691 return; 1692 } 1693 1694 DMA_COMMON_SYNC_OFFSET(rx_msg_p->buf_dma, 1695 (buf_offset + sw_offset_bytes), (hdr_size + l2_len), 1696 DDI_DMA_SYNC_FORCPU); 1697 1698 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1699 "==> hxge_receive_packet: after first dump:usage count")); 1700 1701 if (rx_msg_p->cur_usage_cnt == 0) { 1702 if (rx_rbr_p->rbr_use_bcopy) { 1703 atomic_inc_32(&rx_rbr_p->rbr_consumed); 1704 if (rx_rbr_p->rbr_consumed < 1705 rx_rbr_p->rbr_threshold_hi) { 1706 if (rx_rbr_p->rbr_threshold_lo == 0 || 1707 ((rx_rbr_p->rbr_consumed >= 1708 rx_rbr_p->rbr_threshold_lo) && 1709 (rx_rbr_p->rbr_bufsize_type >= 1710 pktbufsz_type))) { 1711 rx_msg_p->rx_use_bcopy = B_TRUE; 1712 } 1713 } else { 1714 rx_msg_p->rx_use_bcopy = B_TRUE; 1715 } 1716 } 1717 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1718 "==> hxge_receive_packet: buf %d (new block) ", bsize)); 1719 1720 rx_msg_p->pkt_buf_size_code = pktbufsz_type; 1721 rx_msg_p->pkt_buf_size = bsize; 1722 rx_msg_p->cur_usage_cnt = 1; 1723 if (pktbufsz_type == RCR_SINGLE_BLOCK) { 1724 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1725 "==> hxge_receive_packet: buf %d (single block) ", 1726 bsize)); 1727 /* 1728 * Buffer can be reused once the free function is 1729 * called. 1730 */ 1731 rx_msg_p->max_usage_cnt = 1; 1732 buffer_free = B_TRUE; 1733 } else { 1734 rx_msg_p->max_usage_cnt = rx_msg_p->block_size / bsize; 1735 if (rx_msg_p->max_usage_cnt == 1) { 1736 buffer_free = B_TRUE; 1737 } 1738 } 1739 } else { 1740 rx_msg_p->cur_usage_cnt++; 1741 if (rx_msg_p->cur_usage_cnt == rx_msg_p->max_usage_cnt) { 1742 buffer_free = B_TRUE; 1743 } 1744 } 1745 1746 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1747 "msgbuf index = %d l2len %d bytes usage %d max_usage %d ", 1748 msg_index, l2_len, 1749 rx_msg_p->cur_usage_cnt, rx_msg_p->max_usage_cnt)); 1750 1751 if (error_type) { 1752 rdc_stats->ierrors++; 1753 /* Update error stats */ 1754 rdc_stats->errlog.compl_err_type = error_type; 1755 HXGE_FM_REPORT_ERROR(hxgep, NULL, HXGE_FM_EREPORT_RDMC_RCR_ERR); 1756 1757 if (error_type & RCR_CTRL_FIFO_DED) { 1758 rdc_stats->ctrl_fifo_ecc_err++; 1759 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1760 " hxge_receive_packet: " 1761 " channel %d RCR ctrl_fifo_ded error", channel)); 1762 } else if (error_type & RCR_DATA_FIFO_DED) { 1763 rdc_stats->data_fifo_ecc_err++; 1764 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1765 " hxge_receive_packet: channel %d" 1766 " RCR data_fifo_ded error", channel)); 1767 } 1768 1769 /* 1770 * Update and repost buffer block if max usage count is 1771 * reached. 1772 */ 1773 if (error_send_up == B_FALSE) { 1774 atomic_inc_32(&rx_msg_p->ref_cnt); 1775 if (buffer_free == B_TRUE) { 1776 rx_msg_p->free = B_TRUE; 1777 } 1778 1779 MUTEX_EXIT(&rx_rbr_p->lock); 1780 MUTEX_EXIT(&rcr_p->lock); 1781 hxge_freeb(rx_msg_p); 1782 return; 1783 } 1784 } 1785 1786 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1787 "==> hxge_receive_packet: DMA sync second ")); 1788 1789 bytes_read = rcr_p->rcvd_pkt_bytes; 1790 skip_len = sw_offset_bytes + hdr_size; 1791 if (!rx_msg_p->rx_use_bcopy) { 1792 /* 1793 * For loaned up buffers, the driver reference count 1794 * will be incremented first and then the free state. 1795 */ 1796 if ((nmp = hxge_dupb(rx_msg_p, buf_offset, bsize)) != NULL) { 1797 if (first_entry) { 1798 nmp->b_rptr = &nmp->b_rptr[skip_len]; 1799 if (l2_len < bsize - skip_len) { 1800 nmp->b_wptr = &nmp->b_rptr[l2_len]; 1801 } else { 1802 nmp->b_wptr = &nmp->b_rptr[bsize 1803 - skip_len]; 1804 } 1805 } else { 1806 if (l2_len - bytes_read < bsize) { 1807 nmp->b_wptr = 1808 &nmp->b_rptr[l2_len - bytes_read]; 1809 } else { 1810 nmp->b_wptr = &nmp->b_rptr[bsize]; 1811 } 1812 } 1813 } 1814 } else { 1815 if (first_entry) { 1816 nmp = hxge_dupb_bcopy(rx_msg_p, buf_offset + skip_len, 1817 l2_len < bsize - skip_len ? 1818 l2_len : bsize - skip_len); 1819 } else { 1820 nmp = hxge_dupb_bcopy(rx_msg_p, buf_offset, 1821 l2_len - bytes_read < bsize ? 1822 l2_len - bytes_read : bsize); 1823 } 1824 } 1825 1826 if (nmp != NULL) { 1827 if (first_entry) 1828 bytes_read = nmp->b_wptr - nmp->b_rptr; 1829 else 1830 bytes_read += nmp->b_wptr - nmp->b_rptr; 1831 1832 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1833 "==> hxge_receive_packet after dupb: " 1834 "rbr consumed %d " 1835 "pktbufsz_type %d " 1836 "nmp $%p rptr $%p wptr $%p " 1837 "buf_offset %d bzise %d l2_len %d skip_len %d", 1838 rx_rbr_p->rbr_consumed, 1839 pktbufsz_type, 1840 nmp, nmp->b_rptr, nmp->b_wptr, 1841 buf_offset, bsize, l2_len, skip_len)); 1842 } else { 1843 cmn_err(CE_WARN, "!hxge_receive_packet: update stats (error)"); 1844 1845 atomic_inc_32(&rx_msg_p->ref_cnt); 1846 if (buffer_free == B_TRUE) { 1847 rx_msg_p->free = B_TRUE; 1848 } 1849 1850 MUTEX_EXIT(&rx_rbr_p->lock); 1851 MUTEX_EXIT(&rcr_p->lock); 1852 hxge_freeb(rx_msg_p); 1853 return; 1854 } 1855 1856 if (buffer_free == B_TRUE) { 1857 rx_msg_p->free = B_TRUE; 1858 } 1859 1860 /* 1861 * ERROR, FRAG and PKT_TYPE are only reported in the first entry. If a 1862 * packet is not fragmented and no error bit is set, then L4 checksum 1863 * is OK. 1864 */ 1865 is_valid = (nmp != NULL); 1866 if (first_entry) { 1867 rdc_stats->ipackets++; /* count only 1st seg for jumbo */ 1868 rdc_stats->ibytes += skip_len + l2_len < bsize ? 1869 l2_len : bsize; 1870 } else { 1871 rdc_stats->ibytes += l2_len - bytes_read < bsize ? 1872 l2_len - bytes_read : bsize; 1873 } 1874 1875 rcr_p->rcvd_pkt_bytes = bytes_read; 1876 1877 if (rx_msg_p->free && rx_msg_p->rx_use_bcopy) { 1878 atomic_inc_32(&rx_msg_p->ref_cnt); 1879 MUTEX_EXIT(&rx_rbr_p->lock); 1880 MUTEX_EXIT(&rcr_p->lock); 1881 hxge_freeb(rx_msg_p); 1882 } else { 1883 MUTEX_EXIT(&rx_rbr_p->lock); 1884 MUTEX_EXIT(&rcr_p->lock); 1885 } 1886 1887 if (is_valid) { 1888 nmp->b_cont = NULL; 1889 if (first_entry) { 1890 *mp = nmp; 1891 *mp_cont = NULL; 1892 } else { 1893 *mp_cont = nmp; 1894 } 1895 } 1896 1897 /* 1898 * Update stats and hardware checksuming. 1899 */ 1900 if (is_valid && !multi) { 1901 is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP || 1902 pkt_type == RCR_PKT_IS_UDP) ? B_TRUE : B_FALSE); 1903 1904 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_receive_packet: " 1905 "is_valid 0x%x multi %d pkt %d d error %d", 1906 is_valid, multi, is_tcp_udp, error_type)); 1907 1908 if (is_tcp_udp && !error_type) { 1909 (void) hcksum_assoc(nmp, NULL, NULL, 0, 0, 0, 0, 1910 HCK_FULLCKSUM_OK | HCK_FULLCKSUM, 0); 1911 1912 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1913 "==> hxge_receive_packet: Full tcp/udp cksum " 1914 "is_valid 0x%x multi %d pkt %d " 1915 "error %d", 1916 is_valid, multi, is_tcp_udp, error_type)); 1917 } 1918 } 1919 1920 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1921 "==> hxge_receive_packet: *mp 0x%016llx", *mp)); 1922 1923 *multi_p = (multi == RCR_MULTI_MASK); 1924 1925 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_receive_packet: " 1926 "multi %d nmp 0x%016llx *mp 0x%016llx *mp_cont 0x%016llx", 1927 *multi_p, nmp, *mp, *mp_cont)); 1928 } 1929 1930 /*ARGSUSED*/ 1931 static hxge_status_t 1932 hxge_rx_err_evnts(p_hxge_t hxgep, uint_t index, p_hxge_ldv_t ldvp, 1933 rdc_stat_t cs) 1934 { 1935 p_hxge_rx_ring_stats_t rdc_stats; 1936 hpi_handle_t handle; 1937 boolean_t rxchan_fatal = B_FALSE; 1938 uint8_t channel; 1939 hxge_status_t status = HXGE_OK; 1940 uint64_t cs_val; 1941 1942 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_rx_err_evnts")); 1943 1944 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1945 channel = ldvp->channel; 1946 1947 /* Clear the interrupts */ 1948 cs_val = cs.value & RDC_STAT_WR1C; 1949 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs_val); 1950 1951 rdc_stats = &hxgep->statsp->rdc_stats[ldvp->vdma_index]; 1952 1953 if (cs.bits.rbr_cpl_to) { 1954 rdc_stats->rbr_tmout++; 1955 HXGE_FM_REPORT_ERROR(hxgep, channel, 1956 HXGE_FM_EREPORT_RDMC_RBR_CPL_TO); 1957 rxchan_fatal = B_TRUE; 1958 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1959 "==> hxge_rx_err_evnts(channel %d): " 1960 "fatal error: rx_rbr_timeout", channel)); 1961 } 1962 1963 if ((cs.bits.rcr_shadow_par_err) || (cs.bits.rbr_prefetch_par_err)) { 1964 (void) hpi_rxdma_ring_perr_stat_get(handle, 1965 &rdc_stats->errlog.pre_par, &rdc_stats->errlog.sha_par); 1966 } 1967 1968 if (cs.bits.rcr_shadow_par_err) { 1969 rdc_stats->rcr_sha_par++; 1970 HXGE_FM_REPORT_ERROR(hxgep, channel, 1971 HXGE_FM_EREPORT_RDMC_RCR_SHA_PAR); 1972 rxchan_fatal = B_TRUE; 1973 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1974 "==> hxge_rx_err_evnts(channel %d): " 1975 "fatal error: rcr_shadow_par_err", channel)); 1976 } 1977 1978 if (cs.bits.rbr_prefetch_par_err) { 1979 rdc_stats->rbr_pre_par++; 1980 HXGE_FM_REPORT_ERROR(hxgep, channel, 1981 HXGE_FM_EREPORT_RDMC_RBR_PRE_PAR); 1982 rxchan_fatal = B_TRUE; 1983 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1984 "==> hxge_rx_err_evnts(channel %d): " 1985 "fatal error: rbr_prefetch_par_err", channel)); 1986 } 1987 1988 if (cs.bits.rbr_pre_empty) { 1989 rdc_stats->rbr_pre_empty++; 1990 HXGE_FM_REPORT_ERROR(hxgep, channel, 1991 HXGE_FM_EREPORT_RDMC_RBR_PRE_EMPTY); 1992 rxchan_fatal = B_TRUE; 1993 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1994 "==> hxge_rx_err_evnts(channel %d): " 1995 "fatal error: rbr_pre_empty", channel)); 1996 } 1997 1998 if (cs.bits.peu_resp_err) { 1999 rdc_stats->peu_resp_err++; 2000 HXGE_FM_REPORT_ERROR(hxgep, channel, 2001 HXGE_FM_EREPORT_RDMC_PEU_RESP_ERR); 2002 rxchan_fatal = B_TRUE; 2003 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2004 "==> hxge_rx_err_evnts(channel %d): " 2005 "fatal error: peu_resp_err", channel)); 2006 } 2007 2008 if (cs.bits.rcr_thres) { 2009 rdc_stats->rcr_thres++; 2010 } 2011 2012 if (cs.bits.rcr_to) { 2013 rdc_stats->rcr_to++; 2014 } 2015 2016 if (cs.bits.rcr_shadow_full) { 2017 rdc_stats->rcr_shadow_full++; 2018 HXGE_FM_REPORT_ERROR(hxgep, channel, 2019 HXGE_FM_EREPORT_RDMC_RCR_SHA_FULL); 2020 rxchan_fatal = B_TRUE; 2021 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2022 "==> hxge_rx_err_evnts(channel %d): " 2023 "fatal error: rcr_shadow_full", channel)); 2024 } 2025 2026 if (cs.bits.rcr_full) { 2027 rdc_stats->rcrfull++; 2028 HXGE_FM_REPORT_ERROR(hxgep, channel, 2029 HXGE_FM_EREPORT_RDMC_RCRFULL); 2030 rxchan_fatal = B_TRUE; 2031 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2032 "==> hxge_rx_err_evnts(channel %d): " 2033 "fatal error: rcrfull error", channel)); 2034 } 2035 2036 if (cs.bits.rbr_empty) { 2037 rdc_stats->rbr_empty++; 2038 if (rdc_stats->rbr_empty == 1) 2039 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2040 "==> hxge_rx_err_evnts(channel %d): " 2041 "rbr empty error", channel)); 2042 /* 2043 * DMA channel is disabled due to rbr_empty bit is set 2044 * although it is not fatal. Enable the DMA channel here 2045 * to work-around the hardware bug. 2046 */ 2047 (void) hpi_rxdma_cfg_rdc_enable(handle, channel); 2048 } 2049 2050 if (cs.bits.rbr_full) { 2051 rdc_stats->rbrfull++; 2052 HXGE_FM_REPORT_ERROR(hxgep, channel, 2053 HXGE_FM_EREPORT_RDMC_RBRFULL); 2054 rxchan_fatal = B_TRUE; 2055 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2056 "==> hxge_rx_err_evnts(channel %d): " 2057 "fatal error: rbr_full error", channel)); 2058 } 2059 2060 if (rxchan_fatal) { 2061 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2062 " hxge_rx_err_evnts: fatal error on Channel #%d\n", 2063 channel)); 2064 status = hxge_rxdma_fatal_err_recover(hxgep, channel); 2065 if (status == HXGE_OK) { 2066 FM_SERVICE_RESTORED(hxgep); 2067 } 2068 } 2069 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_rx_err_evnts")); 2070 2071 return (status); 2072 } 2073 2074 static hxge_status_t 2075 hxge_map_rxdma(p_hxge_t hxgep) 2076 { 2077 int i, ndmas; 2078 uint16_t channel; 2079 p_rx_rbr_rings_t rx_rbr_rings; 2080 p_rx_rbr_ring_t *rbr_rings; 2081 p_rx_rcr_rings_t rx_rcr_rings; 2082 p_rx_rcr_ring_t *rcr_rings; 2083 p_rx_mbox_areas_t rx_mbox_areas_p; 2084 p_rx_mbox_t *rx_mbox_p; 2085 p_hxge_dma_pool_t dma_buf_poolp; 2086 p_hxge_dma_pool_t dma_cntl_poolp; 2087 p_hxge_dma_common_t *dma_buf_p; 2088 p_hxge_dma_common_t *dma_cntl_p; 2089 uint32_t *num_chunks; 2090 hxge_status_t status = HXGE_OK; 2091 2092 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_map_rxdma")); 2093 2094 dma_buf_poolp = hxgep->rx_buf_pool_p; 2095 dma_cntl_poolp = hxgep->rx_cntl_pool_p; 2096 2097 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 2098 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2099 "<== hxge_map_rxdma: buf not allocated")); 2100 return (HXGE_ERROR); 2101 } 2102 2103 ndmas = dma_buf_poolp->ndmas; 2104 if (!ndmas) { 2105 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2106 "<== hxge_map_rxdma: no dma allocated")); 2107 return (HXGE_ERROR); 2108 } 2109 2110 num_chunks = dma_buf_poolp->num_chunks; 2111 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2112 dma_cntl_p = dma_cntl_poolp->dma_buf_pool_p; 2113 rx_rbr_rings = (p_rx_rbr_rings_t) 2114 KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2115 rbr_rings = (p_rx_rbr_ring_t *)KMEM_ZALLOC( 2116 sizeof (p_rx_rbr_ring_t) * ndmas, KM_SLEEP); 2117 2118 rx_rcr_rings = (p_rx_rcr_rings_t) 2119 KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2120 rcr_rings = (p_rx_rcr_ring_t *)KMEM_ZALLOC( 2121 sizeof (p_rx_rcr_ring_t) * ndmas, KM_SLEEP); 2122 2123 rx_mbox_areas_p = (p_rx_mbox_areas_t) 2124 KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2125 rx_mbox_p = (p_rx_mbox_t *)KMEM_ZALLOC( 2126 sizeof (p_rx_mbox_t) * ndmas, KM_SLEEP); 2127 2128 /* 2129 * Timeout should be set based on the system clock divider. 2130 * The following timeout value of 1 assumes that the 2131 * granularity (1000) is 3 microseconds running at 300MHz. 2132 */ 2133 2134 hxgep->intr_threshold = RXDMA_RCR_PTHRES_DEFAULT; 2135 hxgep->intr_timeout = RXDMA_RCR_TO_DEFAULT; 2136 2137 /* 2138 * Map descriptors from the buffer polls for each dam channel. 2139 */ 2140 for (i = 0; i < ndmas; i++) { 2141 /* 2142 * Set up and prepare buffer blocks, descriptors and mailbox. 2143 */ 2144 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 2145 status = hxge_map_rxdma_channel(hxgep, channel, 2146 (p_hxge_dma_common_t *)&dma_buf_p[i], 2147 (p_rx_rbr_ring_t *)&rbr_rings[i], 2148 num_chunks[i], (p_hxge_dma_common_t *)&dma_cntl_p[i], 2149 (p_rx_rcr_ring_t *)&rcr_rings[i], 2150 (p_rx_mbox_t *)&rx_mbox_p[i]); 2151 if (status != HXGE_OK) { 2152 goto hxge_map_rxdma_fail1; 2153 } 2154 rbr_rings[i]->index = (uint16_t)i; 2155 rcr_rings[i]->index = (uint16_t)i; 2156 rcr_rings[i]->rdc_stats = &hxgep->statsp->rdc_stats[i]; 2157 } 2158 2159 rx_rbr_rings->ndmas = rx_rcr_rings->ndmas = ndmas; 2160 rx_rbr_rings->rbr_rings = rbr_rings; 2161 hxgep->rx_rbr_rings = rx_rbr_rings; 2162 rx_rcr_rings->rcr_rings = rcr_rings; 2163 hxgep->rx_rcr_rings = rx_rcr_rings; 2164 2165 rx_mbox_areas_p->rxmbox_areas = rx_mbox_p; 2166 hxgep->rx_mbox_areas_p = rx_mbox_areas_p; 2167 2168 goto hxge_map_rxdma_exit; 2169 2170 hxge_map_rxdma_fail1: 2171 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2172 "==> hxge_map_rxdma: unmap rbr,rcr (status 0x%x channel %d i %d)", 2173 status, channel, i)); 2174 i--; 2175 for (; i >= 0; i--) { 2176 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 2177 hxge_unmap_rxdma_channel(hxgep, channel, 2178 rbr_rings[i], rcr_rings[i], rx_mbox_p[i]); 2179 } 2180 2181 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2182 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2183 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2184 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2185 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2186 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2187 2188 hxge_map_rxdma_exit: 2189 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2190 "<== hxge_map_rxdma: (status 0x%x channel %d)", status, channel)); 2191 2192 return (status); 2193 } 2194 2195 static void 2196 hxge_unmap_rxdma(p_hxge_t hxgep) 2197 { 2198 int i, ndmas; 2199 uint16_t channel; 2200 p_rx_rbr_rings_t rx_rbr_rings; 2201 p_rx_rbr_ring_t *rbr_rings; 2202 p_rx_rcr_rings_t rx_rcr_rings; 2203 p_rx_rcr_ring_t *rcr_rings; 2204 p_rx_mbox_areas_t rx_mbox_areas_p; 2205 p_rx_mbox_t *rx_mbox_p; 2206 p_hxge_dma_pool_t dma_buf_poolp; 2207 p_hxge_dma_pool_t dma_cntl_poolp; 2208 p_hxge_dma_common_t *dma_buf_p; 2209 2210 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_unmap_rxdma")); 2211 2212 dma_buf_poolp = hxgep->rx_buf_pool_p; 2213 dma_cntl_poolp = hxgep->rx_cntl_pool_p; 2214 2215 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 2216 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2217 "<== hxge_unmap_rxdma: NULL buf pointers")); 2218 return; 2219 } 2220 2221 rx_rbr_rings = hxgep->rx_rbr_rings; 2222 rx_rcr_rings = hxgep->rx_rcr_rings; 2223 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 2224 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2225 "<== hxge_unmap_rxdma: NULL ring pointers")); 2226 return; 2227 } 2228 2229 ndmas = rx_rbr_rings->ndmas; 2230 if (!ndmas) { 2231 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2232 "<== hxge_unmap_rxdma: no channel")); 2233 return; 2234 } 2235 2236 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2237 "==> hxge_unmap_rxdma (ndmas %d)", ndmas)); 2238 2239 rbr_rings = rx_rbr_rings->rbr_rings; 2240 rcr_rings = rx_rcr_rings->rcr_rings; 2241 rx_mbox_areas_p = hxgep->rx_mbox_areas_p; 2242 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 2243 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2244 2245 for (i = 0; i < ndmas; i++) { 2246 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 2247 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2248 "==> hxge_unmap_rxdma (ndmas %d) channel %d", 2249 ndmas, channel)); 2250 (void) hxge_unmap_rxdma_channel(hxgep, channel, 2251 (p_rx_rbr_ring_t)rbr_rings[i], 2252 (p_rx_rcr_ring_t)rcr_rings[i], 2253 (p_rx_mbox_t)rx_mbox_p[i]); 2254 } 2255 2256 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2257 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2258 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2259 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2260 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2261 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2262 2263 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_unmap_rxdma")); 2264 } 2265 2266 hxge_status_t 2267 hxge_map_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 2268 p_hxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 2269 uint32_t num_chunks, p_hxge_dma_common_t *dma_cntl_p, 2270 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 2271 { 2272 int status = HXGE_OK; 2273 2274 /* 2275 * Set up and prepare buffer blocks, descriptors and mailbox. 2276 */ 2277 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2278 "==> hxge_map_rxdma_channel (channel %d)", channel)); 2279 2280 /* 2281 * Receive buffer blocks 2282 */ 2283 status = hxge_map_rxdma_channel_buf_ring(hxgep, channel, 2284 dma_buf_p, rbr_p, num_chunks); 2285 if (status != HXGE_OK) { 2286 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2287 "==> hxge_map_rxdma_channel (channel %d): " 2288 "map buffer failed 0x%x", channel, status)); 2289 goto hxge_map_rxdma_channel_exit; 2290 } 2291 2292 /* 2293 * Receive block ring, completion ring and mailbox. 2294 */ 2295 status = hxge_map_rxdma_channel_cfg_ring(hxgep, channel, 2296 dma_cntl_p, rbr_p, rcr_p, rx_mbox_p); 2297 if (status != HXGE_OK) { 2298 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2299 "==> hxge_map_rxdma_channel (channel %d): " 2300 "map config failed 0x%x", channel, status)); 2301 goto hxge_map_rxdma_channel_fail2; 2302 } 2303 goto hxge_map_rxdma_channel_exit; 2304 2305 hxge_map_rxdma_channel_fail3: 2306 /* Free rbr, rcr */ 2307 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2308 "==> hxge_map_rxdma_channel: free rbr/rcr (status 0x%x channel %d)", 2309 status, channel)); 2310 hxge_unmap_rxdma_channel_cfg_ring(hxgep, *rcr_p, *rx_mbox_p); 2311 2312 hxge_map_rxdma_channel_fail2: 2313 /* Free buffer blocks */ 2314 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2315 "==> hxge_map_rxdma_channel: free rx buffers" 2316 "(hxgep 0x%x status 0x%x channel %d)", 2317 hxgep, status, channel)); 2318 hxge_unmap_rxdma_channel_buf_ring(hxgep, *rbr_p); 2319 2320 status = HXGE_ERROR; 2321 2322 hxge_map_rxdma_channel_exit: 2323 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2324 "<== hxge_map_rxdma_channel: (hxgep 0x%x status 0x%x channel %d)", 2325 hxgep, status, channel)); 2326 2327 return (status); 2328 } 2329 2330 /*ARGSUSED*/ 2331 static void 2332 hxge_unmap_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 2333 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 2334 { 2335 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2336 "==> hxge_unmap_rxdma_channel (channel %d)", channel)); 2337 2338 /* 2339 * unmap receive block ring, completion ring and mailbox. 2340 */ 2341 (void) hxge_unmap_rxdma_channel_cfg_ring(hxgep, rcr_p, rx_mbox_p); 2342 2343 /* unmap buffer blocks */ 2344 (void) hxge_unmap_rxdma_channel_buf_ring(hxgep, rbr_p); 2345 2346 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_unmap_rxdma_channel")); 2347 } 2348 2349 /*ARGSUSED*/ 2350 static hxge_status_t 2351 hxge_map_rxdma_channel_cfg_ring(p_hxge_t hxgep, uint16_t dma_channel, 2352 p_hxge_dma_common_t *dma_cntl_p, p_rx_rbr_ring_t *rbr_p, 2353 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 2354 { 2355 p_rx_rbr_ring_t rbrp; 2356 p_rx_rcr_ring_t rcrp; 2357 p_rx_mbox_t mboxp; 2358 p_hxge_dma_common_t cntl_dmap; 2359 p_hxge_dma_common_t dmap; 2360 p_rx_msg_t *rx_msg_ring; 2361 p_rx_msg_t rx_msg_p; 2362 rdc_rbr_cfg_a_t *rcfga_p; 2363 rdc_rbr_cfg_b_t *rcfgb_p; 2364 rdc_rcr_cfg_a_t *cfga_p; 2365 rdc_rcr_cfg_b_t *cfgb_p; 2366 rdc_rx_cfg1_t *cfig1_p; 2367 rdc_rx_cfg2_t *cfig2_p; 2368 rdc_rbr_kick_t *kick_p; 2369 uint32_t dmaaddrp; 2370 uint32_t *rbr_vaddrp; 2371 uint32_t bkaddr; 2372 hxge_status_t status = HXGE_OK; 2373 int i; 2374 uint32_t hxge_port_rcr_size; 2375 2376 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2377 "==> hxge_map_rxdma_channel_cfg_ring")); 2378 2379 cntl_dmap = *dma_cntl_p; 2380 2381 /* Map in the receive block ring */ 2382 rbrp = *rbr_p; 2383 dmap = (p_hxge_dma_common_t)&rbrp->rbr_desc; 2384 hxge_setup_dma_common(dmap, cntl_dmap, rbrp->rbb_max, 4); 2385 2386 /* 2387 * Zero out buffer block ring descriptors. 2388 */ 2389 bzero((caddr_t)dmap->kaddrp, dmap->alength); 2390 2391 rcfga_p = &(rbrp->rbr_cfga); 2392 rcfgb_p = &(rbrp->rbr_cfgb); 2393 kick_p = &(rbrp->rbr_kick); 2394 rcfga_p->value = 0; 2395 rcfgb_p->value = 0; 2396 kick_p->value = 0; 2397 rbrp->rbr_addr = dmap->dma_cookie.dmac_laddress; 2398 rcfga_p->value = (rbrp->rbr_addr & 2399 (RBR_CFIG_A_STDADDR_MASK | RBR_CFIG_A_STDADDR_BASE_MASK)); 2400 rcfga_p->value |= ((uint64_t)rbrp->rbb_max << RBR_CFIG_A_LEN_SHIFT); 2401 2402 /* XXXX: how to choose packet buffer sizes */ 2403 rcfgb_p->bits.bufsz0 = rbrp->pkt_buf_size0; 2404 rcfgb_p->bits.vld0 = 1; 2405 rcfgb_p->bits.bufsz1 = rbrp->pkt_buf_size1; 2406 rcfgb_p->bits.vld1 = 1; 2407 rcfgb_p->bits.bufsz2 = rbrp->pkt_buf_size2; 2408 rcfgb_p->bits.vld2 = 1; 2409 rcfgb_p->bits.bksize = hxgep->rx_bksize_code; 2410 2411 /* 2412 * For each buffer block, enter receive block address to the ring. 2413 */ 2414 rbr_vaddrp = (uint32_t *)dmap->kaddrp; 2415 rbrp->rbr_desc_vp = (uint32_t *)dmap->kaddrp; 2416 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2417 "==> hxge_map_rxdma_channel_cfg_ring: channel %d " 2418 "rbr_vaddrp $%p", dma_channel, rbr_vaddrp)); 2419 2420 rx_msg_ring = rbrp->rx_msg_ring; 2421 for (i = 0; i < rbrp->tnblocks; i++) { 2422 rx_msg_p = rx_msg_ring[i]; 2423 rx_msg_p->hxgep = hxgep; 2424 rx_msg_p->rx_rbr_p = rbrp; 2425 bkaddr = (uint32_t) 2426 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 2427 RBR_BKADDR_SHIFT)); 2428 rx_msg_p->free = B_FALSE; 2429 rx_msg_p->max_usage_cnt = 0xbaddcafe; 2430 2431 *rbr_vaddrp++ = bkaddr; 2432 } 2433 2434 kick_p->bits.bkadd = rbrp->rbb_max; 2435 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 2436 2437 rbrp->rbr_rd_index = 0; 2438 2439 rbrp->rbr_consumed = 0; 2440 rbrp->rbr_use_bcopy = B_TRUE; 2441 rbrp->rbr_bufsize_type = RCR_PKTBUFSZ_0; 2442 2443 /* 2444 * Do bcopy on packets greater than bcopy size once the lo threshold is 2445 * reached. This lo threshold should be less than the hi threshold. 2446 * 2447 * Do bcopy on every packet once the hi threshold is reached. 2448 */ 2449 if (hxge_rx_threshold_lo >= hxge_rx_threshold_hi) { 2450 /* default it to use hi */ 2451 hxge_rx_threshold_lo = hxge_rx_threshold_hi; 2452 } 2453 if (hxge_rx_buf_size_type > HXGE_RBR_TYPE2) { 2454 hxge_rx_buf_size_type = HXGE_RBR_TYPE2; 2455 } 2456 rbrp->rbr_bufsize_type = hxge_rx_buf_size_type; 2457 2458 switch (hxge_rx_threshold_hi) { 2459 default: 2460 case HXGE_RX_COPY_NONE: 2461 /* Do not do bcopy at all */ 2462 rbrp->rbr_use_bcopy = B_FALSE; 2463 rbrp->rbr_threshold_hi = rbrp->rbb_max; 2464 break; 2465 2466 case HXGE_RX_COPY_1: 2467 case HXGE_RX_COPY_2: 2468 case HXGE_RX_COPY_3: 2469 case HXGE_RX_COPY_4: 2470 case HXGE_RX_COPY_5: 2471 case HXGE_RX_COPY_6: 2472 case HXGE_RX_COPY_7: 2473 rbrp->rbr_threshold_hi = 2474 rbrp->rbb_max * (hxge_rx_threshold_hi) / 2475 HXGE_RX_BCOPY_SCALE; 2476 break; 2477 2478 case HXGE_RX_COPY_ALL: 2479 rbrp->rbr_threshold_hi = 0; 2480 break; 2481 } 2482 2483 switch (hxge_rx_threshold_lo) { 2484 default: 2485 case HXGE_RX_COPY_NONE: 2486 /* Do not do bcopy at all */ 2487 if (rbrp->rbr_use_bcopy) { 2488 rbrp->rbr_use_bcopy = B_FALSE; 2489 } 2490 rbrp->rbr_threshold_lo = rbrp->rbb_max; 2491 break; 2492 2493 case HXGE_RX_COPY_1: 2494 case HXGE_RX_COPY_2: 2495 case HXGE_RX_COPY_3: 2496 case HXGE_RX_COPY_4: 2497 case HXGE_RX_COPY_5: 2498 case HXGE_RX_COPY_6: 2499 case HXGE_RX_COPY_7: 2500 rbrp->rbr_threshold_lo = 2501 rbrp->rbb_max * (hxge_rx_threshold_lo) / 2502 HXGE_RX_BCOPY_SCALE; 2503 break; 2504 2505 case HXGE_RX_COPY_ALL: 2506 rbrp->rbr_threshold_lo = 0; 2507 break; 2508 } 2509 2510 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2511 "hxge_map_rxdma_channel_cfg_ring: channel %d rbb_max %d " 2512 "rbrp->rbr_bufsize_type %d rbb_threshold_hi %d " 2513 "rbb_threshold_lo %d", 2514 dma_channel, rbrp->rbb_max, rbrp->rbr_bufsize_type, 2515 rbrp->rbr_threshold_hi, rbrp->rbr_threshold_lo)); 2516 2517 /* Map in the receive completion ring */ 2518 rcrp = (p_rx_rcr_ring_t)KMEM_ZALLOC(sizeof (rx_rcr_ring_t), KM_SLEEP); 2519 rcrp->rdc = dma_channel; 2520 2521 hxge_port_rcr_size = hxgep->hxge_port_rcr_size; 2522 rcrp->comp_size = hxge_port_rcr_size; 2523 rcrp->comp_wrap_mask = hxge_port_rcr_size - 1; 2524 2525 rcrp->max_receive_pkts = hxge_max_rx_pkts; 2526 2527 dmap = (p_hxge_dma_common_t)&rcrp->rcr_desc; 2528 hxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size, 2529 sizeof (rcr_entry_t)); 2530 rcrp->comp_rd_index = 0; 2531 rcrp->comp_wt_index = 0; 2532 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 2533 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 2534 #if defined(__i386) 2535 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 2536 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 2537 #else 2538 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 2539 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 2540 #endif 2541 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 2542 (hxge_port_rcr_size - 1); 2543 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 2544 (hxge_port_rcr_size - 1); 2545 2546 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2547 "==> hxge_map_rxdma_channel_cfg_ring: channel %d " 2548 "rbr_vaddrp $%p rcr_desc_rd_head_p $%p " 2549 "rcr_desc_rd_head_pp $%p rcr_desc_rd_last_p $%p " 2550 "rcr_desc_rd_last_pp $%p ", 2551 dma_channel, rbr_vaddrp, rcrp->rcr_desc_rd_head_p, 2552 rcrp->rcr_desc_rd_head_pp, rcrp->rcr_desc_last_p, 2553 rcrp->rcr_desc_last_pp)); 2554 2555 /* 2556 * Zero out buffer block ring descriptors. 2557 */ 2558 bzero((caddr_t)dmap->kaddrp, dmap->alength); 2559 rcrp->intr_timeout = hxgep->intr_timeout; 2560 rcrp->intr_threshold = hxgep->intr_threshold; 2561 rcrp->full_hdr_flag = B_FALSE; 2562 rcrp->sw_priv_hdr_len = 0; 2563 2564 cfga_p = &(rcrp->rcr_cfga); 2565 cfgb_p = &(rcrp->rcr_cfgb); 2566 cfga_p->value = 0; 2567 cfgb_p->value = 0; 2568 rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress; 2569 2570 cfga_p->value = (rcrp->rcr_addr & 2571 (RCRCFIG_A_STADDR_MASK | RCRCFIG_A_STADDR_BASE_MASK)); 2572 2573 cfga_p->value |= ((uint64_t)rcrp->comp_size << RCRCFIG_A_LEN_SHIF); 2574 2575 /* 2576 * Timeout should be set based on the system clock divider. The 2577 * following timeout value of 1 assumes that the granularity (1000) is 2578 * 3 microseconds running at 300MHz. 2579 */ 2580 cfgb_p->bits.pthres = rcrp->intr_threshold; 2581 cfgb_p->bits.timeout = rcrp->intr_timeout; 2582 cfgb_p->bits.entout = 1; 2583 2584 /* Map in the mailbox */ 2585 mboxp = (p_rx_mbox_t)KMEM_ZALLOC(sizeof (rx_mbox_t), KM_SLEEP); 2586 dmap = (p_hxge_dma_common_t)&mboxp->rx_mbox; 2587 hxge_setup_dma_common(dmap, cntl_dmap, 1, sizeof (rxdma_mailbox_t)); 2588 cfig1_p = (rdc_rx_cfg1_t *)&mboxp->rx_cfg1; 2589 cfig2_p = (rdc_rx_cfg2_t *)&mboxp->rx_cfg2; 2590 cfig1_p->value = cfig2_p->value = 0; 2591 2592 mboxp->mbox_addr = dmap->dma_cookie.dmac_laddress; 2593 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2594 "==> hxge_map_rxdma_channel_cfg_ring: " 2595 "channel %d cfg1 0x%016llx cfig2 0x%016llx cookie 0x%016llx", 2596 dma_channel, cfig1_p->value, cfig2_p->value, 2597 mboxp->mbox_addr)); 2598 2599 dmaaddrp = (uint32_t)((dmap->dma_cookie.dmac_laddress >> 32) & 0xfff); 2600 cfig1_p->bits.mbaddr_h = dmaaddrp; 2601 2602 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 0xffffffff); 2603 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 2604 RXDMA_CFIG2_MBADDR_L_MASK); 2605 2606 cfig2_p->bits.mbaddr_l = (dmaaddrp >> RXDMA_CFIG2_MBADDR_L_SHIFT); 2607 2608 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2609 "==> hxge_map_rxdma_channel_cfg_ring: channel %d damaddrp $%p " 2610 "cfg1 0x%016llx cfig2 0x%016llx", 2611 dma_channel, dmaaddrp, cfig1_p->value, cfig2_p->value)); 2612 2613 cfig2_p->bits.full_hdr = rcrp->full_hdr_flag; 2614 cfig2_p->bits.offset = rcrp->sw_priv_hdr_len; 2615 2616 rbrp->rx_rcr_p = rcrp; 2617 rcrp->rx_rbr_p = rbrp; 2618 *rcr_p = rcrp; 2619 *rx_mbox_p = mboxp; 2620 2621 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2622 "<== hxge_map_rxdma_channel_cfg_ring status 0x%08x", status)); 2623 return (status); 2624 } 2625 2626 /*ARGSUSED*/ 2627 static void 2628 hxge_unmap_rxdma_channel_cfg_ring(p_hxge_t hxgep, 2629 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 2630 { 2631 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2632 "==> hxge_unmap_rxdma_channel_cfg_ring: channel %d", rcr_p->rdc)); 2633 2634 KMEM_FREE(rcr_p, sizeof (rx_rcr_ring_t)); 2635 KMEM_FREE(rx_mbox_p, sizeof (rx_mbox_t)); 2636 2637 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2638 "<== hxge_unmap_rxdma_channel_cfg_ring")); 2639 } 2640 2641 static hxge_status_t 2642 hxge_map_rxdma_channel_buf_ring(p_hxge_t hxgep, uint16_t channel, 2643 p_hxge_dma_common_t *dma_buf_p, 2644 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks) 2645 { 2646 p_rx_rbr_ring_t rbrp; 2647 p_hxge_dma_common_t dma_bufp, tmp_bufp; 2648 p_rx_msg_t *rx_msg_ring; 2649 p_rx_msg_t rx_msg_p; 2650 p_mblk_t mblk_p; 2651 2652 rxring_info_t *ring_info; 2653 hxge_status_t status = HXGE_OK; 2654 int i, j, index; 2655 uint32_t size, bsize, nblocks, nmsgs; 2656 2657 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2658 "==> hxge_map_rxdma_channel_buf_ring: channel %d", channel)); 2659 2660 dma_bufp = tmp_bufp = *dma_buf_p; 2661 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2662 " hxge_map_rxdma_channel_buf_ring: channel %d to map %d " 2663 "chunks bufp 0x%016llx", channel, num_chunks, dma_bufp)); 2664 2665 nmsgs = 0; 2666 for (i = 0; i < num_chunks; i++, tmp_bufp++) { 2667 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2668 "==> hxge_map_rxdma_channel_buf_ring: channel %d " 2669 "bufp 0x%016llx nblocks %d nmsgs %d", 2670 channel, tmp_bufp, tmp_bufp->nblocks, nmsgs)); 2671 nmsgs += tmp_bufp->nblocks; 2672 } 2673 if (!nmsgs) { 2674 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2675 "<== hxge_map_rxdma_channel_buf_ring: channel %d " 2676 "no msg blocks", channel)); 2677 status = HXGE_ERROR; 2678 goto hxge_map_rxdma_channel_buf_ring_exit; 2679 } 2680 rbrp = (p_rx_rbr_ring_t)KMEM_ZALLOC(sizeof (rx_rbr_ring_t), KM_SLEEP); 2681 2682 size = nmsgs * sizeof (p_rx_msg_t); 2683 rx_msg_ring = KMEM_ZALLOC(size, KM_SLEEP); 2684 ring_info = (rxring_info_t *)KMEM_ZALLOC(sizeof (rxring_info_t), 2685 KM_SLEEP); 2686 2687 MUTEX_INIT(&rbrp->lock, NULL, MUTEX_DRIVER, 2688 (void *) hxgep->interrupt_cookie); 2689 MUTEX_INIT(&rbrp->post_lock, NULL, MUTEX_DRIVER, 2690 (void *) hxgep->interrupt_cookie); 2691 rbrp->rdc = channel; 2692 rbrp->num_blocks = num_chunks; 2693 rbrp->tnblocks = nmsgs; 2694 rbrp->rbb_max = nmsgs; 2695 rbrp->rbr_max_size = nmsgs; 2696 rbrp->rbr_wrap_mask = (rbrp->rbb_max - 1); 2697 2698 rbrp->pages_to_post = 0; 2699 rbrp->pages_to_skip = 20; 2700 rbrp->pages_to_post_threshold = rbrp->rbb_max - rbrp->pages_to_skip / 2; 2701 2702 /* 2703 * Buffer sizes suggested by NIU architect. 256, 512 and 2K. 2704 */ 2705 2706 rbrp->pkt_buf_size0 = RBR_BUFSZ0_256B; 2707 rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_256_BYTES; 2708 rbrp->hpi_pkt_buf_size0 = SIZE_256B; 2709 2710 rbrp->pkt_buf_size1 = RBR_BUFSZ1_1K; 2711 rbrp->pkt_buf_size1_bytes = RBR_BUFSZ1_1K_BYTES; 2712 rbrp->hpi_pkt_buf_size1 = SIZE_1KB; 2713 2714 rbrp->block_size = hxgep->rx_default_block_size; 2715 2716 if (!hxge_jumbo_enable && !hxgep->param_arr[param_accept_jumbo].value) { 2717 rbrp->pkt_buf_size2 = RBR_BUFSZ2_2K; 2718 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_2K_BYTES; 2719 rbrp->hpi_pkt_buf_size2 = SIZE_2KB; 2720 } else { 2721 if (rbrp->block_size >= 0x2000) { 2722 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2723 "<== hxge_map_rxdma_channel_buf_ring: channel %d " 2724 "no msg blocks", channel)); 2725 status = HXGE_ERROR; 2726 goto hxge_map_rxdma_channel_buf_ring_fail1; 2727 } else { 2728 rbrp->pkt_buf_size2 = RBR_BUFSZ2_4K; 2729 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_4K_BYTES; 2730 rbrp->hpi_pkt_buf_size2 = SIZE_4KB; 2731 } 2732 } 2733 2734 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2735 "==> hxge_map_rxdma_channel_buf_ring: channel %d " 2736 "actual rbr max %d rbb_max %d nmsgs %d " 2737 "rbrp->block_size %d default_block_size %d " 2738 "(config hxge_rbr_size %d hxge_rbr_spare_size %d)", 2739 channel, rbrp->rbr_max_size, rbrp->rbb_max, nmsgs, 2740 rbrp->block_size, hxgep->rx_default_block_size, 2741 hxge_rbr_size, hxge_rbr_spare_size)); 2742 2743 /* 2744 * Map in buffers from the buffer pool. 2745 * Note that num_blocks is the num_chunks. For Sparc, there is likely 2746 * only one chunk. For x86, there will be many chunks. 2747 * Loop over chunks. 2748 */ 2749 index = 0; 2750 for (i = 0; i < rbrp->num_blocks; i++, dma_bufp++) { 2751 bsize = dma_bufp->block_size; 2752 nblocks = dma_bufp->nblocks; 2753 #if defined(__i386) 2754 ring_info->buffer[i].dvma_addr = (uint32_t)dma_bufp->ioaddr_pp; 2755 #else 2756 ring_info->buffer[i].dvma_addr = (uint64_t)dma_bufp->ioaddr_pp; 2757 #endif 2758 ring_info->buffer[i].buf_index = i; 2759 ring_info->buffer[i].buf_size = dma_bufp->alength; 2760 ring_info->buffer[i].start_index = index; 2761 #if defined(__i386) 2762 ring_info->buffer[i].kaddr = (uint32_t)dma_bufp->kaddrp; 2763 #else 2764 ring_info->buffer[i].kaddr = (uint64_t)dma_bufp->kaddrp; 2765 #endif 2766 2767 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2768 " hxge_map_rxdma_channel_buf_ring: map channel %d " 2769 "chunk %d nblocks %d chunk_size %x block_size 0x%x " 2770 "dma_bufp $%p dvma_addr $%p", channel, i, 2771 dma_bufp->nblocks, 2772 ring_info->buffer[i].buf_size, bsize, dma_bufp, 2773 ring_info->buffer[i].dvma_addr)); 2774 2775 /* loop over blocks within a chunk */ 2776 for (j = 0; j < nblocks; j++) { 2777 if ((rx_msg_p = hxge_allocb(bsize, BPRI_LO, 2778 dma_bufp)) == NULL) { 2779 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2780 "allocb failed (index %d i %d j %d)", 2781 index, i, j)); 2782 goto hxge_map_rxdma_channel_buf_ring_fail1; 2783 } 2784 rx_msg_ring[index] = rx_msg_p; 2785 rx_msg_p->block_index = index; 2786 rx_msg_p->shifted_addr = (uint32_t) 2787 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 2788 RBR_BKADDR_SHIFT)); 2789 /* 2790 * Too much output 2791 * HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2792 * "index %d j %d rx_msg_p $%p mblk %p", 2793 * index, j, rx_msg_p, rx_msg_p->rx_mblk_p)); 2794 */ 2795 mblk_p = rx_msg_p->rx_mblk_p; 2796 mblk_p->b_wptr = mblk_p->b_rptr + bsize; 2797 2798 rbrp->rbr_ref_cnt++; 2799 index++; 2800 rx_msg_p->buf_dma.dma_channel = channel; 2801 } 2802 } 2803 if (i < rbrp->num_blocks) { 2804 goto hxge_map_rxdma_channel_buf_ring_fail1; 2805 } 2806 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2807 "hxge_map_rxdma_channel_buf_ring: done buf init " 2808 "channel %d msg block entries %d", channel, index)); 2809 ring_info->block_size_mask = bsize - 1; 2810 rbrp->rx_msg_ring = rx_msg_ring; 2811 rbrp->dma_bufp = dma_buf_p; 2812 rbrp->ring_info = ring_info; 2813 2814 status = hxge_rxbuf_index_info_init(hxgep, rbrp); 2815 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, " hxge_map_rxdma_channel_buf_ring: " 2816 "channel %d done buf info init", channel)); 2817 2818 /* 2819 * Finally, permit hxge_freeb() to call hxge_post_page(). 2820 */ 2821 rbrp->rbr_state = RBR_POSTING; 2822 2823 *rbr_p = rbrp; 2824 2825 goto hxge_map_rxdma_channel_buf_ring_exit; 2826 2827 hxge_map_rxdma_channel_buf_ring_fail1: 2828 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2829 " hxge_map_rxdma_channel_buf_ring: failed channel (0x%x)", 2830 channel, status)); 2831 2832 index--; 2833 for (; index >= 0; index--) { 2834 rx_msg_p = rx_msg_ring[index]; 2835 if (rx_msg_p != NULL) { 2836 hxge_freeb(rx_msg_p); 2837 rx_msg_ring[index] = NULL; 2838 } 2839 } 2840 2841 hxge_map_rxdma_channel_buf_ring_fail: 2842 MUTEX_DESTROY(&rbrp->post_lock); 2843 MUTEX_DESTROY(&rbrp->lock); 2844 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 2845 KMEM_FREE(rx_msg_ring, size); 2846 KMEM_FREE(rbrp, sizeof (rx_rbr_ring_t)); 2847 2848 status = HXGE_ERROR; 2849 2850 hxge_map_rxdma_channel_buf_ring_exit: 2851 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2852 "<== hxge_map_rxdma_channel_buf_ring status 0x%08x", status)); 2853 2854 return (status); 2855 } 2856 2857 /*ARGSUSED*/ 2858 static void 2859 hxge_unmap_rxdma_channel_buf_ring(p_hxge_t hxgep, 2860 p_rx_rbr_ring_t rbr_p) 2861 { 2862 p_rx_msg_t *rx_msg_ring; 2863 p_rx_msg_t rx_msg_p; 2864 rxring_info_t *ring_info; 2865 int i; 2866 uint32_t size; 2867 2868 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2869 "==> hxge_unmap_rxdma_channel_buf_ring")); 2870 if (rbr_p == NULL) { 2871 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2872 "<== hxge_unmap_rxdma_channel_buf_ring: NULL rbrp")); 2873 return; 2874 } 2875 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2876 "==> hxge_unmap_rxdma_channel_buf_ring: channel %d", rbr_p->rdc)); 2877 2878 rx_msg_ring = rbr_p->rx_msg_ring; 2879 ring_info = rbr_p->ring_info; 2880 2881 if (rx_msg_ring == NULL || ring_info == NULL) { 2882 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2883 "<== hxge_unmap_rxdma_channel_buf_ring: " 2884 "rx_msg_ring $%p ring_info $%p", rx_msg_p, ring_info)); 2885 return; 2886 } 2887 2888 size = rbr_p->tnblocks * sizeof (p_rx_msg_t); 2889 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2890 " hxge_unmap_rxdma_channel_buf_ring: channel %d chunks %d " 2891 "tnblocks %d (max %d) size ptrs %d ", rbr_p->rdc, rbr_p->num_blocks, 2892 rbr_p->tnblocks, rbr_p->rbr_max_size, size)); 2893 2894 for (i = 0; i < rbr_p->tnblocks; i++) { 2895 rx_msg_p = rx_msg_ring[i]; 2896 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2897 " hxge_unmap_rxdma_channel_buf_ring: " 2898 "rx_msg_p $%p", rx_msg_p)); 2899 if (rx_msg_p != NULL) { 2900 hxge_freeb(rx_msg_p); 2901 rx_msg_ring[i] = NULL; 2902 } 2903 } 2904 2905 /* 2906 * We no longer may use the mutex <post_lock>. By setting 2907 * <rbr_state> to anything but POSTING, we prevent 2908 * hxge_post_page() from accessing a dead mutex. 2909 */ 2910 rbr_p->rbr_state = RBR_UNMAPPING; 2911 MUTEX_DESTROY(&rbr_p->post_lock); 2912 2913 MUTEX_DESTROY(&rbr_p->lock); 2914 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 2915 KMEM_FREE(rx_msg_ring, size); 2916 2917 if (rbr_p->rbr_ref_cnt == 0) { 2918 /* This is the normal state of affairs. */ 2919 KMEM_FREE(rbr_p, sizeof (*rbr_p)); 2920 } else { 2921 /* 2922 * Some of our buffers are still being used. 2923 * Therefore, tell hxge_freeb() this ring is 2924 * unmapped, so it may free <rbr_p> for us. 2925 */ 2926 rbr_p->rbr_state = RBR_UNMAPPED; 2927 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2928 "unmap_rxdma_buf_ring: %d %s outstanding.", 2929 rbr_p->rbr_ref_cnt, 2930 rbr_p->rbr_ref_cnt == 1 ? "msg" : "msgs")); 2931 } 2932 2933 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2934 "<== hxge_unmap_rxdma_channel_buf_ring")); 2935 } 2936 2937 static hxge_status_t 2938 hxge_rxdma_hw_start_common(p_hxge_t hxgep) 2939 { 2940 hxge_status_t status = HXGE_OK; 2941 2942 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start_common")); 2943 2944 /* 2945 * Load the sharable parameters by writing to the function zero control 2946 * registers. These FZC registers should be initialized only once for 2947 * the entire chip. 2948 */ 2949 (void) hxge_init_fzc_rx_common(hxgep); 2950 2951 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start_common")); 2952 2953 return (status); 2954 } 2955 2956 static hxge_status_t 2957 hxge_rxdma_hw_start(p_hxge_t hxgep) 2958 { 2959 int i, ndmas; 2960 uint16_t channel; 2961 p_rx_rbr_rings_t rx_rbr_rings; 2962 p_rx_rbr_ring_t *rbr_rings; 2963 p_rx_rcr_rings_t rx_rcr_rings; 2964 p_rx_rcr_ring_t *rcr_rings; 2965 p_rx_mbox_areas_t rx_mbox_areas_p; 2966 p_rx_mbox_t *rx_mbox_p; 2967 hxge_status_t status = HXGE_OK; 2968 2969 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start")); 2970 2971 rx_rbr_rings = hxgep->rx_rbr_rings; 2972 rx_rcr_rings = hxgep->rx_rcr_rings; 2973 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 2974 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2975 "<== hxge_rxdma_hw_start: NULL ring pointers")); 2976 return (HXGE_ERROR); 2977 } 2978 2979 ndmas = rx_rbr_rings->ndmas; 2980 if (ndmas == 0) { 2981 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2982 "<== hxge_rxdma_hw_start: no dma channel allocated")); 2983 return (HXGE_ERROR); 2984 } 2985 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2986 "==> hxge_rxdma_hw_start (ndmas %d)", ndmas)); 2987 2988 /* 2989 * Scrub the RDC Rx DMA Prefetch Buffer Command. 2990 */ 2991 for (i = 0; i < 128; i++) { 2992 HXGE_REG_WR64(hxgep->hpi_handle, RDC_PREF_CMD, i); 2993 } 2994 2995 /* 2996 * Scrub Rx DMA Shadow Tail Command. 2997 */ 2998 for (i = 0; i < 64; i++) { 2999 HXGE_REG_WR64(hxgep->hpi_handle, RDC_SHADOW_CMD, i); 3000 } 3001 3002 /* 3003 * Scrub Rx DMA Control Fifo Command. 3004 */ 3005 for (i = 0; i < 512; i++) { 3006 HXGE_REG_WR64(hxgep->hpi_handle, RDC_CTRL_FIFO_CMD, i); 3007 } 3008 3009 /* 3010 * Scrub Rx DMA Data Fifo Command. 3011 */ 3012 for (i = 0; i < 1536; i++) { 3013 HXGE_REG_WR64(hxgep->hpi_handle, RDC_DATA_FIFO_CMD, i); 3014 } 3015 3016 /* 3017 * Reset the FIFO Error Stat. 3018 */ 3019 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_STAT, 0xFF); 3020 3021 /* Set the error mask to receive interrupts */ 3022 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_INT_MASK, 0x0); 3023 3024 rbr_rings = rx_rbr_rings->rbr_rings; 3025 rcr_rings = rx_rcr_rings->rcr_rings; 3026 rx_mbox_areas_p = hxgep->rx_mbox_areas_p; 3027 if (rx_mbox_areas_p) { 3028 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 3029 } 3030 3031 for (i = 0; i < ndmas; i++) { 3032 channel = rbr_rings[i]->rdc; 3033 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3034 "==> hxge_rxdma_hw_start (ndmas %d) channel %d", 3035 ndmas, channel)); 3036 status = hxge_rxdma_start_channel(hxgep, channel, 3037 (p_rx_rbr_ring_t)rbr_rings[i], 3038 (p_rx_rcr_ring_t)rcr_rings[i], 3039 (p_rx_mbox_t)rx_mbox_p[i]); 3040 if (status != HXGE_OK) { 3041 goto hxge_rxdma_hw_start_fail1; 3042 } 3043 } 3044 3045 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start: " 3046 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3047 rx_rbr_rings, rx_rcr_rings)); 3048 goto hxge_rxdma_hw_start_exit; 3049 3050 hxge_rxdma_hw_start_fail1: 3051 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3052 "==> hxge_rxdma_hw_start: disable " 3053 "(status 0x%x channel %d i %d)", status, channel, i)); 3054 for (; i >= 0; i--) { 3055 channel = rbr_rings[i]->rdc; 3056 (void) hxge_rxdma_stop_channel(hxgep, channel); 3057 } 3058 3059 hxge_rxdma_hw_start_exit: 3060 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3061 "==> hxge_rxdma_hw_start: (status 0x%x)", status)); 3062 return (status); 3063 } 3064 3065 static void 3066 hxge_rxdma_hw_stop(p_hxge_t hxgep) 3067 { 3068 int i, ndmas; 3069 uint16_t channel; 3070 p_rx_rbr_rings_t rx_rbr_rings; 3071 p_rx_rbr_ring_t *rbr_rings; 3072 p_rx_rcr_rings_t rx_rcr_rings; 3073 3074 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_stop")); 3075 3076 rx_rbr_rings = hxgep->rx_rbr_rings; 3077 rx_rcr_rings = hxgep->rx_rcr_rings; 3078 3079 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3080 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3081 "<== hxge_rxdma_hw_stop: NULL ring pointers")); 3082 return; 3083 } 3084 3085 ndmas = rx_rbr_rings->ndmas; 3086 if (!ndmas) { 3087 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3088 "<== hxge_rxdma_hw_stop: no dma channel allocated")); 3089 return; 3090 } 3091 3092 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3093 "==> hxge_rxdma_hw_stop (ndmas %d)", ndmas)); 3094 3095 rbr_rings = rx_rbr_rings->rbr_rings; 3096 for (i = 0; i < ndmas; i++) { 3097 channel = rbr_rings[i]->rdc; 3098 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3099 "==> hxge_rxdma_hw_stop (ndmas %d) channel %d", 3100 ndmas, channel)); 3101 (void) hxge_rxdma_stop_channel(hxgep, channel); 3102 } 3103 3104 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_stop: " 3105 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3106 rx_rbr_rings, rx_rcr_rings)); 3107 3108 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_rxdma_hw_stop")); 3109 } 3110 3111 static hxge_status_t 3112 hxge_rxdma_start_channel(p_hxge_t hxgep, uint16_t channel, 3113 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 3114 { 3115 hpi_handle_t handle; 3116 hpi_status_t rs = HPI_SUCCESS; 3117 rdc_stat_t cs; 3118 rdc_int_mask_t ent_mask; 3119 hxge_status_t status = HXGE_OK; 3120 3121 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel")); 3122 3123 handle = HXGE_DEV_HPI_HANDLE(hxgep); 3124 3125 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "hxge_rxdma_start_channel: " 3126 "hpi handle addr $%p acc $%p", 3127 hxgep->hpi_handle.regp, hxgep->hpi_handle.regh)); 3128 3129 /* Reset RXDMA channel */ 3130 rs = hpi_rxdma_cfg_rdc_reset(handle, channel); 3131 if (rs != HPI_SUCCESS) { 3132 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3133 "==> hxge_rxdma_start_channel: " 3134 "reset rxdma failed (0x%08x channel %d)", 3135 status, channel)); 3136 return (HXGE_ERROR | rs); 3137 } 3138 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3139 "==> hxge_rxdma_start_channel: reset done: channel %d", channel)); 3140 3141 /* 3142 * Initialize the RXDMA channel specific FZC control configurations. 3143 * These FZC registers are pertaining to each RX channel (logical 3144 * pages). 3145 */ 3146 status = hxge_init_fzc_rxdma_channel(hxgep, 3147 channel, rbr_p, rcr_p, mbox_p); 3148 if (status != HXGE_OK) { 3149 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3150 "==> hxge_rxdma_start_channel: " 3151 "init fzc rxdma failed (0x%08x channel %d)", 3152 status, channel)); 3153 return (status); 3154 } 3155 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3156 "==> hxge_rxdma_start_channel: fzc done")); 3157 3158 /* 3159 * Zero out the shadow and prefetch ram. 3160 */ 3161 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3162 "==> hxge_rxdma_start_channel: ram done")); 3163 3164 /* Set up the interrupt event masks. */ 3165 ent_mask.value = 0; 3166 rs = hpi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 3167 if (rs != HPI_SUCCESS) { 3168 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3169 "==> hxge_rxdma_start_channel: " 3170 "init rxdma event masks failed (0x%08x channel %d)", 3171 status, channel)); 3172 return (HXGE_ERROR | rs); 3173 } 3174 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3175 "event done: channel %d (mask 0x%016llx)", 3176 channel, ent_mask.value)); 3177 3178 /* 3179 * Load RXDMA descriptors, buffers, mailbox, initialise the receive DMA 3180 * channels and enable each DMA channel. 3181 */ 3182 status = hxge_enable_rxdma_channel(hxgep, 3183 channel, rbr_p, rcr_p, mbox_p); 3184 if (status != HXGE_OK) { 3185 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3186 " hxge_rxdma_start_channel: " 3187 " init enable rxdma failed (0x%08x channel %d)", 3188 status, channel)); 3189 return (status); 3190 } 3191 3192 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3193 "control done - channel %d cs 0x%016llx", channel, cs.value)); 3194 3195 /* 3196 * Initialize the receive DMA control and status register 3197 * Note that rdc_stat HAS to be set after RBR and RCR rings are set 3198 */ 3199 cs.value = 0; 3200 cs.bits.mex = 1; 3201 cs.bits.rcr_thres = 1; 3202 cs.bits.rcr_to = 1; 3203 cs.bits.rbr_empty = 1; 3204 status = hxge_init_rxdma_channel_cntl_stat(hxgep, channel, &cs); 3205 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3206 "channel %d rx_dma_cntl_stat 0x%0016llx", channel, cs.value)); 3207 if (status != HXGE_OK) { 3208 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3209 "==> hxge_rxdma_start_channel: " 3210 "init rxdma control register failed (0x%08x channel %d", 3211 status, channel)); 3212 return (status); 3213 } 3214 3215 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3216 "control done - channel %d cs 0x%016llx", channel, cs.value)); 3217 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3218 "==> hxge_rxdma_start_channel: enable done")); 3219 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_rxdma_start_channel")); 3220 3221 return (HXGE_OK); 3222 } 3223 3224 static hxge_status_t 3225 hxge_rxdma_stop_channel(p_hxge_t hxgep, uint16_t channel) 3226 { 3227 hpi_handle_t handle; 3228 hpi_status_t rs = HPI_SUCCESS; 3229 rdc_stat_t cs; 3230 rdc_int_mask_t ent_mask; 3231 hxge_status_t status = HXGE_OK; 3232 3233 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_channel")); 3234 3235 handle = HXGE_DEV_HPI_HANDLE(hxgep); 3236 3237 HXGE_DEBUG_MSG((hxgep, RX_CTL, "hxge_rxdma_stop_channel: " 3238 "hpi handle addr $%p acc $%p", 3239 hxgep->hpi_handle.regp, hxgep->hpi_handle.regh)); 3240 3241 /* Reset RXDMA channel */ 3242 rs = hpi_rxdma_cfg_rdc_reset(handle, channel); 3243 if (rs != HPI_SUCCESS) { 3244 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3245 " hxge_rxdma_stop_channel: " 3246 " reset rxdma failed (0x%08x channel %d)", 3247 rs, channel)); 3248 return (HXGE_ERROR | rs); 3249 } 3250 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3251 "==> hxge_rxdma_stop_channel: reset done")); 3252 3253 /* Set up the interrupt event masks. */ 3254 ent_mask.value = RDC_INT_MASK_ALL; 3255 rs = hpi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 3256 if (rs != HPI_SUCCESS) { 3257 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3258 "==> hxge_rxdma_stop_channel: " 3259 "set rxdma event masks failed (0x%08x channel %d)", 3260 rs, channel)); 3261 return (HXGE_ERROR | rs); 3262 } 3263 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3264 "==> hxge_rxdma_stop_channel: event done")); 3265 3266 /* Initialize the receive DMA control and status register */ 3267 cs.value = 0; 3268 status = hxge_init_rxdma_channel_cntl_stat(hxgep, channel, &cs); 3269 3270 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_channel: control " 3271 " to default (all 0s) 0x%08x", cs.value)); 3272 3273 if (status != HXGE_OK) { 3274 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3275 " hxge_rxdma_stop_channel: init rxdma" 3276 " control register failed (0x%08x channel %d", 3277 status, channel)); 3278 return (status); 3279 } 3280 3281 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3282 "==> hxge_rxdma_stop_channel: control done")); 3283 3284 /* disable dma channel */ 3285 status = hxge_disable_rxdma_channel(hxgep, channel); 3286 3287 if (status != HXGE_OK) { 3288 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3289 " hxge_rxdma_stop_channel: " 3290 " init enable rxdma failed (0x%08x channel %d)", 3291 status, channel)); 3292 return (status); 3293 } 3294 3295 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3296 "==> hxge_rxdma_stop_channel: disable done")); 3297 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop_channel")); 3298 3299 return (HXGE_OK); 3300 } 3301 3302 hxge_status_t 3303 hxge_rxdma_handle_sys_errors(p_hxge_t hxgep) 3304 { 3305 hpi_handle_t handle; 3306 p_hxge_rdc_sys_stats_t statsp; 3307 rdc_fifo_err_stat_t stat; 3308 hxge_status_t status = HXGE_OK; 3309 3310 handle = hxgep->hpi_handle; 3311 statsp = (p_hxge_rdc_sys_stats_t)&hxgep->statsp->rdc_sys_stats; 3312 3313 /* Clear the int_dbg register in case it is an injected err */ 3314 HXGE_REG_WR64(handle, RDC_FIFO_ERR_INT_DBG, 0x0); 3315 3316 /* Get the error status and clear the register */ 3317 HXGE_REG_RD64(handle, RDC_FIFO_ERR_STAT, &stat.value); 3318 HXGE_REG_WR64(handle, RDC_FIFO_ERR_STAT, stat.value); 3319 3320 if (stat.bits.rx_ctrl_fifo_sec) { 3321 statsp->ctrl_fifo_sec++; 3322 if (statsp->ctrl_fifo_sec == 1) 3323 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3324 "==> hxge_rxdma_handle_sys_errors: " 3325 "rx_ctrl_fifo_sec")); 3326 } 3327 3328 if (stat.bits.rx_ctrl_fifo_ded) { 3329 /* Global fatal error encountered */ 3330 statsp->ctrl_fifo_ded++; 3331 HXGE_FM_REPORT_ERROR(hxgep, NULL, 3332 HXGE_FM_EREPORT_RDMC_CTRL_FIFO_DED); 3333 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3334 "==> hxge_rxdma_handle_sys_errors: " 3335 "fatal error: rx_ctrl_fifo_ded error")); 3336 } 3337 3338 if (stat.bits.rx_data_fifo_sec) { 3339 statsp->data_fifo_sec++; 3340 if (statsp->data_fifo_sec == 1) 3341 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3342 "==> hxge_rxdma_handle_sys_errors: " 3343 "rx_data_fifo_sec")); 3344 } 3345 3346 if (stat.bits.rx_data_fifo_ded) { 3347 /* Global fatal error encountered */ 3348 statsp->data_fifo_ded++; 3349 HXGE_FM_REPORT_ERROR(hxgep, NULL, 3350 HXGE_FM_EREPORT_RDMC_DATA_FIFO_DED); 3351 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3352 "==> hxge_rxdma_handle_sys_errors: " 3353 "fatal error: rx_data_fifo_ded error")); 3354 } 3355 3356 if (stat.bits.rx_ctrl_fifo_ded || stat.bits.rx_data_fifo_ded) { 3357 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3358 " hxge_rxdma_handle_sys_errors: fatal error\n")); 3359 status = hxge_rx_port_fatal_err_recover(hxgep); 3360 if (status == HXGE_OK) { 3361 FM_SERVICE_RESTORED(hxgep); 3362 } 3363 } 3364 3365 return (HXGE_OK); 3366 } 3367 3368 static hxge_status_t 3369 hxge_rxdma_fatal_err_recover(p_hxge_t hxgep, uint16_t channel) 3370 { 3371 hpi_handle_t handle; 3372 hpi_status_t rs = HPI_SUCCESS; 3373 hxge_status_t status = HXGE_OK; 3374 p_rx_rbr_ring_t rbrp; 3375 p_rx_rcr_ring_t rcrp; 3376 p_rx_mbox_t mboxp; 3377 rdc_int_mask_t ent_mask; 3378 p_hxge_dma_common_t dmap; 3379 int ring_idx; 3380 p_rx_msg_t rx_msg_p; 3381 int i; 3382 uint32_t hxge_port_rcr_size; 3383 uint64_t tmp; 3384 3385 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_fatal_err_recover")); 3386 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3387 "Recovering from RxDMAChannel#%d error...", channel)); 3388 3389 /* 3390 * Stop the dma channel waits for the stop done. If the stop done bit 3391 * is not set, then create an error. 3392 */ 3393 3394 handle = HXGE_DEV_HPI_HANDLE(hxgep); 3395 3396 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Rx DMA stop...")); 3397 3398 ring_idx = hxge_rxdma_get_ring_index(hxgep, channel); 3399 rbrp = (p_rx_rbr_ring_t)hxgep->rx_rbr_rings->rbr_rings[ring_idx]; 3400 rcrp = (p_rx_rcr_ring_t)hxgep->rx_rcr_rings->rcr_rings[ring_idx]; 3401 3402 MUTEX_ENTER(&rcrp->lock); 3403 MUTEX_ENTER(&rbrp->lock); 3404 MUTEX_ENTER(&rbrp->post_lock); 3405 3406 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxDMA channel...")); 3407 3408 rs = hpi_rxdma_cfg_rdc_disable(handle, channel); 3409 if (rs != HPI_SUCCESS) { 3410 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3411 "hxge_disable_rxdma_channel:failed")); 3412 goto fail; 3413 } 3414 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxDMA interrupt...")); 3415 3416 /* Disable interrupt */ 3417 ent_mask.value = RDC_INT_MASK_ALL; 3418 rs = hpi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 3419 if (rs != HPI_SUCCESS) { 3420 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3421 "Set rxdma event masks failed (channel %d)", channel)); 3422 } 3423 HXGE_DEBUG_MSG((hxgep, RX_CTL, "RxDMA channel reset...")); 3424 3425 /* Reset RXDMA channel */ 3426 rs = hpi_rxdma_cfg_rdc_reset(handle, channel); 3427 if (rs != HPI_SUCCESS) { 3428 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3429 "Reset rxdma failed (channel %d)", channel)); 3430 goto fail; 3431 } 3432 hxge_port_rcr_size = hxgep->hxge_port_rcr_size; 3433 mboxp = (p_rx_mbox_t)hxgep->rx_mbox_areas_p->rxmbox_areas[ring_idx]; 3434 3435 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 3436 rbrp->rbr_rd_index = 0; 3437 rbrp->pages_to_post = 0; 3438 3439 rcrp->comp_rd_index = 0; 3440 rcrp->comp_wt_index = 0; 3441 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 3442 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 3443 #if defined(__i386) 3444 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3445 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3446 #else 3447 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3448 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3449 #endif 3450 3451 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 3452 (hxge_port_rcr_size - 1); 3453 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 3454 (hxge_port_rcr_size - 1); 3455 3456 dmap = (p_hxge_dma_common_t)&rcrp->rcr_desc; 3457 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3458 3459 HXGE_DEBUG_MSG((hxgep, RX_CTL, "rbr entries = %d\n", 3460 rbrp->rbr_max_size)); 3461 3462 for (i = 0; i < rbrp->rbr_max_size; i++) { 3463 /* Reset all the buffers */ 3464 rx_msg_p = rbrp->rx_msg_ring[i]; 3465 rx_msg_p->ref_cnt = 1; 3466 rx_msg_p->free = B_TRUE; 3467 rx_msg_p->cur_usage_cnt = 0; 3468 rx_msg_p->max_usage_cnt = 0; 3469 rx_msg_p->pkt_buf_size = 0; 3470 } 3471 3472 HXGE_DEBUG_MSG((hxgep, RX_CTL, "RxDMA channel re-start...")); 3473 3474 status = hxge_rxdma_start_channel(hxgep, channel, rbrp, rcrp, mboxp); 3475 if (status != HXGE_OK) { 3476 goto fail; 3477 } 3478 3479 /* 3480 * The DMA channel may disable itself automatically. 3481 * The following is a work-around. 3482 */ 3483 HXGE_REG_RD64(handle, RDC_RX_CFG1, &tmp); 3484 rs = hpi_rxdma_cfg_rdc_enable(handle, channel); 3485 if (rs != HPI_SUCCESS) { 3486 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3487 "hpi_rxdma_cfg_rdc_enable (channel %d)", channel)); 3488 } 3489 3490 MUTEX_EXIT(&rbrp->post_lock); 3491 MUTEX_EXIT(&rbrp->lock); 3492 MUTEX_EXIT(&rcrp->lock); 3493 3494 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3495 "Recovery Successful, RxDMAChannel#%d Restored", channel)); 3496 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_fatal_err_recover")); 3497 3498 return (HXGE_OK); 3499 3500 fail: 3501 MUTEX_EXIT(&rbrp->post_lock); 3502 MUTEX_EXIT(&rbrp->lock); 3503 MUTEX_EXIT(&rcrp->lock); 3504 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovery failed")); 3505 3506 return (HXGE_ERROR | rs); 3507 } 3508 3509 static hxge_status_t 3510 hxge_rx_port_fatal_err_recover(p_hxge_t hxgep) 3511 { 3512 hxge_status_t status = HXGE_OK; 3513 p_hxge_dma_common_t *dma_buf_p; 3514 uint16_t channel; 3515 int ndmas; 3516 int i; 3517 block_reset_t reset_reg; 3518 3519 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_port_fatal_err_recover")); 3520 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovering from RDC error ...")); 3521 3522 /* Reset RDC block from PEU for this fatal error */ 3523 reset_reg.value = 0; 3524 reset_reg.bits.rdc_rst = 1; 3525 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value); 3526 3527 /* Disable RxMAC */ 3528 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxMAC...\n")); 3529 if (hxge_rx_vmac_disable(hxgep) != HXGE_OK) 3530 goto fail; 3531 3532 HXGE_DELAY(1000); 3533 3534 /* Restore any common settings after PEU reset */ 3535 if (hxge_rxdma_hw_start_common(hxgep) != HXGE_OK) 3536 goto fail; 3537 3538 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Stop all RxDMA channels...")); 3539 3540 ndmas = hxgep->rx_buf_pool_p->ndmas; 3541 dma_buf_p = hxgep->rx_buf_pool_p->dma_buf_pool_p; 3542 3543 for (i = 0; i < ndmas; i++) { 3544 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 3545 if (hxge_rxdma_fatal_err_recover(hxgep, channel) != HXGE_OK) { 3546 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3547 "Could not recover channel %d", channel)); 3548 } 3549 } 3550 3551 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Reset RxMAC...")); 3552 3553 /* Reset RxMAC */ 3554 if (hxge_rx_vmac_reset(hxgep) != HXGE_OK) { 3555 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3556 "hxge_rx_port_fatal_err_recover: Failed to reset RxMAC")); 3557 goto fail; 3558 } 3559 3560 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Re-initialize RxMAC...")); 3561 3562 /* Re-Initialize RxMAC */ 3563 if ((status = hxge_rx_vmac_init(hxgep)) != HXGE_OK) { 3564 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3565 "hxge_rx_port_fatal_err_recover: Failed to reset RxMAC")); 3566 goto fail; 3567 } 3568 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Re-enable RxMAC...")); 3569 3570 /* Re-enable RxMAC */ 3571 if ((status = hxge_rx_vmac_enable(hxgep)) != HXGE_OK) { 3572 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3573 "hxge_rx_port_fatal_err_recover: Failed to enable RxMAC")); 3574 goto fail; 3575 } 3576 3577 /* Reset the error mask since PEU reset cleared it */ 3578 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_INT_MASK, 0x0); 3579 3580 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3581 "Recovery Successful, RxPort Restored")); 3582 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rx_port_fatal_err_recover")); 3583 3584 return (HXGE_OK); 3585 fail: 3586 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovery failed")); 3587 return (status); 3588 } 3589