1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <hxge_impl.h> 27 #include <hxge_rxdma.h> 28 29 /* 30 * Number of blocks to accumulate before re-enabling DMA 31 * when we get RBR empty. 32 */ 33 #define HXGE_RBR_EMPTY_THRESHOLD 64 34 35 /* 36 * Globals: tunable parameters (/etc/system or adb) 37 * 38 */ 39 extern uint32_t hxge_rbr_size; 40 extern uint32_t hxge_rcr_size; 41 extern uint32_t hxge_rbr_spare_size; 42 extern uint32_t hxge_mblks_pending; 43 44 /* 45 * Tunable to reduce the amount of time spent in the 46 * ISR doing Rx Processing. 47 */ 48 extern uint32_t hxge_max_rx_pkts; 49 50 /* 51 * Tunables to manage the receive buffer blocks. 52 * 53 * hxge_rx_threshold_hi: copy all buffers. 54 * hxge_rx_bcopy_size_type: receive buffer block size type. 55 * hxge_rx_threshold_lo: copy only up to tunable block size type. 56 */ 57 extern hxge_rxbuf_threshold_t hxge_rx_threshold_hi; 58 extern hxge_rxbuf_type_t hxge_rx_buf_size_type; 59 extern hxge_rxbuf_threshold_t hxge_rx_threshold_lo; 60 61 /* 62 * Static local functions. 63 */ 64 static hxge_status_t hxge_map_rxdma(p_hxge_t hxgep); 65 static void hxge_unmap_rxdma(p_hxge_t hxgep); 66 static hxge_status_t hxge_rxdma_hw_start_common(p_hxge_t hxgep); 67 static hxge_status_t hxge_rxdma_hw_start(p_hxge_t hxgep); 68 static void hxge_rxdma_hw_stop(p_hxge_t hxgep); 69 static hxge_status_t hxge_map_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 70 p_hxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 71 uint32_t num_chunks, p_hxge_dma_common_t *dma_rbr_cntl_p, 72 p_hxge_dma_common_t *dma_rcr_cntl_p, p_hxge_dma_common_t *dma_mbox_cntl_p, 73 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p); 74 static void hxge_unmap_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 75 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p); 76 static hxge_status_t hxge_map_rxdma_channel_cfg_ring(p_hxge_t hxgep, 77 uint16_t dma_channel, p_hxge_dma_common_t *dma_rbr_cntl_p, 78 p_hxge_dma_common_t *dma_rcr_cntl_p, p_hxge_dma_common_t *dma_mbox_cntl_p, 79 p_rx_rbr_ring_t *rbr_p, p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p); 80 static void hxge_unmap_rxdma_channel_cfg_ring(p_hxge_t hxgep, 81 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p); 82 static hxge_status_t hxge_map_rxdma_channel_buf_ring(p_hxge_t hxgep, 83 uint16_t channel, p_hxge_dma_common_t *dma_buf_p, 84 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks); 85 static void hxge_unmap_rxdma_channel_buf_ring(p_hxge_t hxgep, 86 p_rx_rbr_ring_t rbr_p); 87 static hxge_status_t hxge_rxdma_start_channel(p_hxge_t hxgep, uint16_t channel, 88 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p, 89 int n_init_kick); 90 static hxge_status_t hxge_rxdma_stop_channel(p_hxge_t hxgep, uint16_t channel); 91 static mblk_t *hxge_rx_pkts(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp, 92 p_rx_rcr_ring_t *rcr_p, rdc_stat_t cs); 93 static void hxge_receive_packet(p_hxge_t hxgep, p_rx_rcr_ring_t rcr_p, 94 p_rcr_entry_t rcr_desc_rd_head_p, boolean_t *multi_p, 95 mblk_t ** mp, mblk_t ** mp_cont, uint32_t *invalid_rcr_entry); 96 static hxge_status_t hxge_disable_rxdma_channel(p_hxge_t hxgep, 97 uint16_t channel); 98 static p_rx_msg_t hxge_allocb(size_t, uint32_t, p_hxge_dma_common_t); 99 static void hxge_freeb(p_rx_msg_t); 100 static void hxge_rx_pkts_vring(p_hxge_t hxgep, uint_t vindex, 101 p_hxge_ldv_t ldvp, rdc_stat_t cs); 102 static hxge_status_t hxge_rx_err_evnts(p_hxge_t hxgep, uint_t index, 103 p_hxge_ldv_t ldvp, rdc_stat_t cs); 104 static hxge_status_t hxge_rxbuf_index_info_init(p_hxge_t hxgep, 105 p_rx_rbr_ring_t rx_dmap); 106 static hxge_status_t hxge_rxdma_fatal_err_recover(p_hxge_t hxgep, 107 uint16_t channel); 108 static hxge_status_t hxge_rx_port_fatal_err_recover(p_hxge_t hxgep); 109 110 hxge_status_t 111 hxge_init_rxdma_channels(p_hxge_t hxgep) 112 { 113 hxge_status_t status = HXGE_OK; 114 block_reset_t reset_reg; 115 116 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_init_rxdma_channels")); 117 118 /* Reset RDC block from PEU to clear any previous state */ 119 reset_reg.value = 0; 120 reset_reg.bits.rdc_rst = 1; 121 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value); 122 HXGE_DELAY(1000); 123 124 status = hxge_map_rxdma(hxgep); 125 if (status != HXGE_OK) { 126 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 127 "<== hxge_init_rxdma: status 0x%x", status)); 128 return (status); 129 } 130 131 status = hxge_rxdma_hw_start_common(hxgep); 132 if (status != HXGE_OK) { 133 hxge_unmap_rxdma(hxgep); 134 } 135 136 status = hxge_rxdma_hw_start(hxgep); 137 if (status != HXGE_OK) { 138 hxge_unmap_rxdma(hxgep); 139 } 140 141 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 142 "<== hxge_init_rxdma_channels: status 0x%x", status)); 143 return (status); 144 } 145 146 void 147 hxge_uninit_rxdma_channels(p_hxge_t hxgep) 148 { 149 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_uninit_rxdma_channels")); 150 151 hxge_rxdma_hw_stop(hxgep); 152 hxge_unmap_rxdma(hxgep); 153 154 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_uinit_rxdma_channels")); 155 } 156 157 hxge_status_t 158 hxge_init_rxdma_channel_cntl_stat(p_hxge_t hxgep, uint16_t channel, 159 rdc_stat_t *cs_p) 160 { 161 hpi_handle_t handle; 162 hpi_status_t rs = HPI_SUCCESS; 163 hxge_status_t status = HXGE_OK; 164 165 HXGE_DEBUG_MSG((hxgep, DMA_CTL, 166 "<== hxge_init_rxdma_channel_cntl_stat")); 167 168 handle = HXGE_DEV_HPI_HANDLE(hxgep); 169 rs = hpi_rxdma_control_status(handle, OP_SET, channel, cs_p); 170 171 if (rs != HPI_SUCCESS) { 172 status = HXGE_ERROR | rs; 173 } 174 return (status); 175 } 176 177 178 hxge_status_t 179 hxge_enable_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 180 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p, 181 int n_init_kick) 182 { 183 hpi_handle_t handle; 184 rdc_desc_cfg_t rdc_desc; 185 rdc_rcr_cfg_b_t *cfgb_p; 186 hpi_status_t rs = HPI_SUCCESS; 187 188 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel")); 189 handle = HXGE_DEV_HPI_HANDLE(hxgep); 190 191 /* 192 * Use configuration data composed at init time. Write to hardware the 193 * receive ring configurations. 194 */ 195 rdc_desc.mbox_enable = 1; 196 rdc_desc.mbox_addr = mbox_p->mbox_addr; 197 HXGE_DEBUG_MSG((hxgep, RX_CTL, 198 "==> hxge_enable_rxdma_channel: mboxp $%p($%p)", 199 mbox_p->mbox_addr, rdc_desc.mbox_addr)); 200 201 rdc_desc.rbr_len = rbr_p->rbb_max; 202 rdc_desc.rbr_addr = rbr_p->rbr_addr; 203 204 switch (hxgep->rx_bksize_code) { 205 case RBR_BKSIZE_4K: 206 rdc_desc.page_size = SIZE_4KB; 207 break; 208 case RBR_BKSIZE_8K: 209 rdc_desc.page_size = SIZE_8KB; 210 break; 211 } 212 213 rdc_desc.size0 = rbr_p->hpi_pkt_buf_size0; 214 rdc_desc.valid0 = 1; 215 216 rdc_desc.size1 = rbr_p->hpi_pkt_buf_size1; 217 rdc_desc.valid1 = 1; 218 219 rdc_desc.size2 = rbr_p->hpi_pkt_buf_size2; 220 rdc_desc.valid2 = 1; 221 222 rdc_desc.full_hdr = rcr_p->full_hdr_flag; 223 rdc_desc.offset = rcr_p->sw_priv_hdr_len; 224 225 rdc_desc.rcr_len = rcr_p->comp_size; 226 rdc_desc.rcr_addr = rcr_p->rcr_addr; 227 228 cfgb_p = &(rcr_p->rcr_cfgb); 229 rdc_desc.rcr_threshold = cfgb_p->bits.pthres; 230 rdc_desc.rcr_timeout = cfgb_p->bits.timeout; 231 rdc_desc.rcr_timeout_enable = cfgb_p->bits.entout; 232 233 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel: " 234 "rbr_len qlen %d pagesize code %d rcr_len %d", 235 rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len)); 236 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel: " 237 "size 0 %d size 1 %d size 2 %d", 238 rbr_p->hpi_pkt_buf_size0, rbr_p->hpi_pkt_buf_size1, 239 rbr_p->hpi_pkt_buf_size2)); 240 241 rs = hpi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc, &rdc_desc); 242 if (rs != HPI_SUCCESS) { 243 return (HXGE_ERROR | rs); 244 } 245 246 /* 247 * Enable the timeout and threshold. 248 */ 249 rs = hpi_rxdma_cfg_rdc_rcr_threshold(handle, channel, 250 rdc_desc.rcr_threshold); 251 if (rs != HPI_SUCCESS) { 252 return (HXGE_ERROR | rs); 253 } 254 255 rs = hpi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 256 rdc_desc.rcr_timeout); 257 if (rs != HPI_SUCCESS) { 258 return (HXGE_ERROR | rs); 259 } 260 261 /* Enable the DMA */ 262 rs = hpi_rxdma_cfg_rdc_enable(handle, channel); 263 if (rs != HPI_SUCCESS) { 264 return (HXGE_ERROR | rs); 265 } 266 267 /* Kick the DMA engine */ 268 hpi_rxdma_rdc_rbr_kick(handle, channel, n_init_kick); 269 270 /* Clear the rbr empty bit */ 271 (void) hpi_rxdma_channel_rbr_empty_clear(handle, channel); 272 273 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_enable_rxdma_channel")); 274 275 return (HXGE_OK); 276 } 277 278 static hxge_status_t 279 hxge_disable_rxdma_channel(p_hxge_t hxgep, uint16_t channel) 280 { 281 hpi_handle_t handle; 282 hpi_status_t rs = HPI_SUCCESS; 283 284 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_disable_rxdma_channel")); 285 286 handle = HXGE_DEV_HPI_HANDLE(hxgep); 287 288 /* disable the DMA */ 289 rs = hpi_rxdma_cfg_rdc_disable(handle, channel); 290 if (rs != HPI_SUCCESS) { 291 HXGE_DEBUG_MSG((hxgep, RX_CTL, 292 "<== hxge_disable_rxdma_channel:failed (0x%x)", rs)); 293 return (HXGE_ERROR | rs); 294 } 295 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_disable_rxdma_channel")); 296 return (HXGE_OK); 297 } 298 299 hxge_status_t 300 hxge_rxdma_channel_rcrflush(p_hxge_t hxgep, uint8_t channel) 301 { 302 hpi_handle_t handle; 303 hxge_status_t status = HXGE_OK; 304 305 HXGE_DEBUG_MSG((hxgep, DMA_CTL, 306 "==> hxge_rxdma_channel_rcrflush")); 307 308 handle = HXGE_DEV_HPI_HANDLE(hxgep); 309 hpi_rxdma_rdc_rcr_flush(handle, channel); 310 311 HXGE_DEBUG_MSG((hxgep, DMA_CTL, 312 "<== hxge_rxdma_channel_rcrflush")); 313 return (status); 314 315 } 316 317 #define MID_INDEX(l, r) ((r + l + 1) >> 1) 318 319 #define TO_LEFT -1 320 #define TO_RIGHT 1 321 #define BOTH_RIGHT (TO_RIGHT + TO_RIGHT) 322 #define BOTH_LEFT (TO_LEFT + TO_LEFT) 323 #define IN_MIDDLE (TO_RIGHT + TO_LEFT) 324 #define NO_HINT 0xffffffff 325 326 /*ARGSUSED*/ 327 hxge_status_t 328 hxge_rxbuf_pp_to_vp(p_hxge_t hxgep, p_rx_rbr_ring_t rbr_p, 329 uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp, 330 uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index) 331 { 332 int bufsize; 333 uint64_t pktbuf_pp; 334 uint64_t dvma_addr; 335 rxring_info_t *ring_info; 336 int base_side, end_side; 337 int r_index, l_index, anchor_index; 338 int found, search_done; 339 uint32_t offset, chunk_size, block_size, page_size_mask; 340 uint32_t chunk_index, block_index, total_index; 341 int max_iterations, iteration; 342 rxbuf_index_info_t *bufinfo; 343 344 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> hxge_rxbuf_pp_to_vp")); 345 346 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 347 "==> hxge_rxbuf_pp_to_vp: buf_pp $%p btype %d", 348 pkt_buf_addr_pp, pktbufsz_type)); 349 350 #if defined(__i386) 351 pktbuf_pp = (uint64_t)(uint32_t)pkt_buf_addr_pp; 352 #else 353 pktbuf_pp = (uint64_t)pkt_buf_addr_pp; 354 #endif 355 356 switch (pktbufsz_type) { 357 case 0: 358 bufsize = rbr_p->pkt_buf_size0; 359 break; 360 case 1: 361 bufsize = rbr_p->pkt_buf_size1; 362 break; 363 case 2: 364 bufsize = rbr_p->pkt_buf_size2; 365 break; 366 case RCR_SINGLE_BLOCK: 367 bufsize = 0; 368 anchor_index = 0; 369 break; 370 default: 371 return (HXGE_ERROR); 372 } 373 374 if (rbr_p->num_blocks == 1) { 375 anchor_index = 0; 376 ring_info = rbr_p->ring_info; 377 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 378 379 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 380 "==> hxge_rxbuf_pp_to_vp: (found, 1 block) " 381 "buf_pp $%p btype %d anchor_index %d bufinfo $%p", 382 pkt_buf_addr_pp, pktbufsz_type, anchor_index, bufinfo)); 383 384 goto found_index; 385 } 386 387 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 388 "==> hxge_rxbuf_pp_to_vp: buf_pp $%p btype %d anchor_index %d", 389 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 390 391 ring_info = rbr_p->ring_info; 392 found = B_FALSE; 393 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 394 iteration = 0; 395 max_iterations = ring_info->max_iterations; 396 397 /* 398 * First check if this block have been seen recently. This is indicated 399 * by a hint which is initialized when the first buffer of the block is 400 * seen. The hint is reset when the last buffer of the block has been 401 * processed. As three block sizes are supported, three hints are kept. 402 * The idea behind the hints is that once the hardware uses a block 403 * for a buffer of that size, it will use it exclusively for that size 404 * and will use it until it is exhausted. It is assumed that there 405 * would a single block being used for the same buffer sizes at any 406 * given time. 407 */ 408 if (ring_info->hint[pktbufsz_type] != NO_HINT) { 409 anchor_index = ring_info->hint[pktbufsz_type]; 410 dvma_addr = bufinfo[anchor_index].dvma_addr; 411 chunk_size = bufinfo[anchor_index].buf_size; 412 if ((pktbuf_pp >= dvma_addr) && 413 (pktbuf_pp < (dvma_addr + chunk_size))) { 414 found = B_TRUE; 415 /* 416 * check if this is the last buffer in the block If so, 417 * then reset the hint for the size; 418 */ 419 420 if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size)) 421 ring_info->hint[pktbufsz_type] = NO_HINT; 422 } 423 } 424 425 if (found == B_FALSE) { 426 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 427 "==> hxge_rxbuf_pp_to_vp: (!found)" 428 "buf_pp $%p btype %d anchor_index %d", 429 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 430 431 /* 432 * This is the first buffer of the block of this size. Need to 433 * search the whole information array. the search algorithm 434 * uses a binary tree search algorithm. It assumes that the 435 * information is already sorted with increasing order info[0] 436 * < info[1] < info[2] .... < info[n-1] where n is the size of 437 * the information array 438 */ 439 r_index = rbr_p->num_blocks - 1; 440 l_index = 0; 441 search_done = B_FALSE; 442 anchor_index = MID_INDEX(r_index, l_index); 443 while (search_done == B_FALSE) { 444 if ((r_index == l_index) || 445 (iteration >= max_iterations)) 446 search_done = B_TRUE; 447 448 end_side = TO_RIGHT; /* to the right */ 449 base_side = TO_LEFT; /* to the left */ 450 /* read the DVMA address information and sort it */ 451 dvma_addr = bufinfo[anchor_index].dvma_addr; 452 chunk_size = bufinfo[anchor_index].buf_size; 453 454 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 455 "==> hxge_rxbuf_pp_to_vp: (searching)" 456 "buf_pp $%p btype %d " 457 "anchor_index %d chunk_size %d dvmaaddr $%p", 458 pkt_buf_addr_pp, pktbufsz_type, anchor_index, 459 chunk_size, dvma_addr)); 460 461 if (pktbuf_pp >= dvma_addr) 462 base_side = TO_RIGHT; /* to the right */ 463 if (pktbuf_pp < (dvma_addr + chunk_size)) 464 end_side = TO_LEFT; /* to the left */ 465 466 switch (base_side + end_side) { 467 case IN_MIDDLE: 468 /* found */ 469 found = B_TRUE; 470 search_done = B_TRUE; 471 if ((pktbuf_pp + bufsize) < 472 (dvma_addr + chunk_size)) 473 ring_info->hint[pktbufsz_type] = 474 bufinfo[anchor_index].buf_index; 475 break; 476 case BOTH_RIGHT: 477 /* not found: go to the right */ 478 l_index = anchor_index + 1; 479 anchor_index = MID_INDEX(r_index, l_index); 480 break; 481 482 case BOTH_LEFT: 483 /* not found: go to the left */ 484 r_index = anchor_index - 1; 485 anchor_index = MID_INDEX(r_index, l_index); 486 break; 487 default: /* should not come here */ 488 return (HXGE_ERROR); 489 } 490 iteration++; 491 } 492 493 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 494 "==> hxge_rxbuf_pp_to_vp: (search done)" 495 "buf_pp $%p btype %d anchor_index %d", 496 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 497 } 498 499 if (found == B_FALSE) { 500 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 501 "==> hxge_rxbuf_pp_to_vp: (search failed)" 502 "buf_pp $%p btype %d anchor_index %d", 503 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 504 return (HXGE_ERROR); 505 } 506 507 found_index: 508 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 509 "==> hxge_rxbuf_pp_to_vp: (FOUND1)" 510 "buf_pp $%p btype %d bufsize %d anchor_index %d", 511 pkt_buf_addr_pp, pktbufsz_type, bufsize, anchor_index)); 512 513 /* index of the first block in this chunk */ 514 chunk_index = bufinfo[anchor_index].start_index; 515 dvma_addr = bufinfo[anchor_index].dvma_addr; 516 page_size_mask = ring_info->block_size_mask; 517 518 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 519 "==> hxge_rxbuf_pp_to_vp: (FOUND3), get chunk)" 520 "buf_pp $%p btype %d bufsize %d " 521 "anchor_index %d chunk_index %d dvma $%p", 522 pkt_buf_addr_pp, pktbufsz_type, bufsize, 523 anchor_index, chunk_index, dvma_addr)); 524 525 offset = pktbuf_pp - dvma_addr; /* offset within the chunk */ 526 block_size = rbr_p->block_size; /* System block(page) size */ 527 528 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 529 "==> hxge_rxbuf_pp_to_vp: (FOUND4), get chunk)" 530 "buf_pp $%p btype %d bufsize %d " 531 "anchor_index %d chunk_index %d dvma $%p " 532 "offset %d block_size %d", 533 pkt_buf_addr_pp, pktbufsz_type, bufsize, anchor_index, 534 chunk_index, dvma_addr, offset, block_size)); 535 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> getting total index")); 536 537 block_index = (offset / block_size); /* index within chunk */ 538 total_index = chunk_index + block_index; 539 540 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 541 "==> hxge_rxbuf_pp_to_vp: " 542 "total_index %d dvma_addr $%p " 543 "offset %d block_size %d " 544 "block_index %d ", 545 total_index, dvma_addr, offset, block_size, block_index)); 546 547 #if defined(__i386) 548 *pkt_buf_addr_p = (uint64_t *)((uint32_t)bufinfo[anchor_index].kaddr + 549 (uint32_t)offset); 550 #else 551 *pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr + 552 offset); 553 #endif 554 555 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 556 "==> hxge_rxbuf_pp_to_vp: " 557 "total_index %d dvma_addr $%p " 558 "offset %d block_size %d " 559 "block_index %d " 560 "*pkt_buf_addr_p $%p", 561 total_index, dvma_addr, offset, block_size, 562 block_index, *pkt_buf_addr_p)); 563 564 *msg_index = total_index; 565 *bufoffset = (offset & page_size_mask); 566 567 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 568 "==> hxge_rxbuf_pp_to_vp: get msg index: " 569 "msg_index %d bufoffset_index %d", 570 *msg_index, *bufoffset)); 571 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "<== hxge_rxbuf_pp_to_vp")); 572 573 return (HXGE_OK); 574 } 575 576 577 /* 578 * used by quick sort (qsort) function 579 * to perform comparison 580 */ 581 static int 582 hxge_sort_compare(const void *p1, const void *p2) 583 { 584 585 rxbuf_index_info_t *a, *b; 586 587 a = (rxbuf_index_info_t *)p1; 588 b = (rxbuf_index_info_t *)p2; 589 590 if (a->dvma_addr > b->dvma_addr) 591 return (1); 592 if (a->dvma_addr < b->dvma_addr) 593 return (-1); 594 return (0); 595 } 596 597 /* 598 * Grabbed this sort implementation from common/syscall/avl.c 599 * 600 * Generic shellsort, from K&R (1st ed, p 58.), somewhat modified. 601 * v = Ptr to array/vector of objs 602 * n = # objs in the array 603 * s = size of each obj (must be multiples of a word size) 604 * f = ptr to function to compare two objs 605 * returns (-1 = less than, 0 = equal, 1 = greater than 606 */ 607 void 608 hxge_ksort(caddr_t v, int n, int s, int (*f) ()) 609 { 610 int g, i, j, ii; 611 unsigned int *p1, *p2; 612 unsigned int tmp; 613 614 /* No work to do */ 615 if (v == NULL || n <= 1) 616 return; 617 /* Sanity check on arguments */ 618 ASSERT(((uintptr_t)v & 0x3) == 0 && (s & 0x3) == 0); 619 ASSERT(s > 0); 620 621 for (g = n / 2; g > 0; g /= 2) { 622 for (i = g; i < n; i++) { 623 for (j = i - g; j >= 0 && 624 (*f) (v + j * s, v + (j + g) * s) == 1; j -= g) { 625 p1 = (unsigned *)(v + j * s); 626 p2 = (unsigned *)(v + (j + g) * s); 627 for (ii = 0; ii < s / 4; ii++) { 628 tmp = *p1; 629 *p1++ = *p2; 630 *p2++ = tmp; 631 } 632 } 633 } 634 } 635 } 636 637 /* 638 * Initialize data structures required for rxdma 639 * buffer dvma->vmem address lookup 640 */ 641 /*ARGSUSED*/ 642 static hxge_status_t 643 hxge_rxbuf_index_info_init(p_hxge_t hxgep, p_rx_rbr_ring_t rbrp) 644 { 645 int index; 646 rxring_info_t *ring_info; 647 int max_iteration = 0, max_index = 0; 648 649 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_rxbuf_index_info_init")); 650 651 ring_info = rbrp->ring_info; 652 ring_info->hint[0] = NO_HINT; 653 ring_info->hint[1] = NO_HINT; 654 ring_info->hint[2] = NO_HINT; 655 max_index = rbrp->num_blocks; 656 657 /* read the DVMA address information and sort it */ 658 /* do init of the information array */ 659 660 HXGE_DEBUG_MSG((hxgep, DMA2_CTL, 661 " hxge_rxbuf_index_info_init Sort ptrs")); 662 663 /* sort the array */ 664 hxge_ksort((void *) ring_info->buffer, max_index, 665 sizeof (rxbuf_index_info_t), hxge_sort_compare); 666 667 for (index = 0; index < max_index; index++) { 668 HXGE_DEBUG_MSG((hxgep, DMA2_CTL, 669 " hxge_rxbuf_index_info_init: sorted chunk %d " 670 " ioaddr $%p kaddr $%p size %x", 671 index, ring_info->buffer[index].dvma_addr, 672 ring_info->buffer[index].kaddr, 673 ring_info->buffer[index].buf_size)); 674 } 675 676 max_iteration = 0; 677 while (max_index >= (1ULL << max_iteration)) 678 max_iteration++; 679 ring_info->max_iterations = max_iteration + 1; 680 681 HXGE_DEBUG_MSG((hxgep, DMA2_CTL, 682 " hxge_rxbuf_index_info_init Find max iter %d", 683 ring_info->max_iterations)); 684 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_rxbuf_index_info_init")); 685 686 return (HXGE_OK); 687 } 688 689 /*ARGSUSED*/ 690 void 691 hxge_dump_rcr_entry(p_hxge_t hxgep, p_rcr_entry_t entry_p) 692 { 693 #ifdef HXGE_DEBUG 694 695 uint32_t bptr; 696 uint64_t pp; 697 698 bptr = entry_p->bits.pkt_buf_addr; 699 700 HXGE_DEBUG_MSG((hxgep, RX_CTL, 701 "\trcr entry $%p " 702 "\trcr entry 0x%0llx " 703 "\trcr entry 0x%08x " 704 "\trcr entry 0x%08x " 705 "\tvalue 0x%0llx\n" 706 "\tmulti = %d\n" 707 "\tpkt_type = 0x%x\n" 708 "\terror = 0x%04x\n" 709 "\tl2_len = %d\n" 710 "\tpktbufsize = %d\n" 711 "\tpkt_buf_addr = $%p\n" 712 "\tpkt_buf_addr (<< 6) = $%p\n", 713 entry_p, 714 *(int64_t *)entry_p, 715 *(int32_t *)entry_p, 716 *(int32_t *)((char *)entry_p + 32), 717 entry_p->value, 718 entry_p->bits.multi, 719 entry_p->bits.pkt_type, 720 entry_p->bits.error, 721 entry_p->bits.l2_len, 722 entry_p->bits.pktbufsz, 723 bptr, 724 entry_p->bits.pkt_buf_addr_l)); 725 726 pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) << 727 RCR_PKT_BUF_ADDR_SHIFT; 728 729 HXGE_DEBUG_MSG((hxgep, RX_CTL, "rcr pp 0x%llx l2 len %d", 730 pp, (*(int64_t *)entry_p >> 40) & 0x3fff)); 731 #endif 732 } 733 734 /*ARGSUSED*/ 735 void 736 hxge_rxdma_stop(p_hxge_t hxgep) 737 { 738 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop")); 739 740 (void) hxge_rx_vmac_disable(hxgep); 741 (void) hxge_rxdma_hw_mode(hxgep, HXGE_DMA_STOP); 742 743 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop")); 744 } 745 746 void 747 hxge_rxdma_stop_reinit(p_hxge_t hxgep) 748 { 749 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_reinit")); 750 751 (void) hxge_rxdma_stop(hxgep); 752 (void) hxge_uninit_rxdma_channels(hxgep); 753 (void) hxge_init_rxdma_channels(hxgep); 754 755 (void) hxge_rx_vmac_enable(hxgep); 756 757 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop_reinit")); 758 } 759 760 hxge_status_t 761 hxge_rxdma_hw_mode(p_hxge_t hxgep, boolean_t enable) 762 { 763 int i, ndmas; 764 uint16_t channel; 765 p_rx_rbr_rings_t rx_rbr_rings; 766 p_rx_rbr_ring_t *rbr_rings; 767 hpi_handle_t handle; 768 hpi_status_t rs = HPI_SUCCESS; 769 hxge_status_t status = HXGE_OK; 770 771 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 772 "==> hxge_rxdma_hw_mode: mode %d", enable)); 773 774 if (!(hxgep->drv_state & STATE_HW_INITIALIZED)) { 775 HXGE_DEBUG_MSG((hxgep, RX_CTL, 776 "<== hxge_rxdma_mode: not initialized")); 777 return (HXGE_ERROR); 778 } 779 780 rx_rbr_rings = hxgep->rx_rbr_rings; 781 if (rx_rbr_rings == NULL) { 782 HXGE_DEBUG_MSG((hxgep, RX_CTL, 783 "<== hxge_rxdma_mode: NULL ring pointer")); 784 return (HXGE_ERROR); 785 } 786 787 if (rx_rbr_rings->rbr_rings == NULL) { 788 HXGE_DEBUG_MSG((hxgep, RX_CTL, 789 "<== hxge_rxdma_mode: NULL rbr rings pointer")); 790 return (HXGE_ERROR); 791 } 792 793 ndmas = rx_rbr_rings->ndmas; 794 if (!ndmas) { 795 HXGE_DEBUG_MSG((hxgep, RX_CTL, 796 "<== hxge_rxdma_mode: no channel")); 797 return (HXGE_ERROR); 798 } 799 800 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 801 "==> hxge_rxdma_mode (ndmas %d)", ndmas)); 802 803 rbr_rings = rx_rbr_rings->rbr_rings; 804 805 handle = HXGE_DEV_HPI_HANDLE(hxgep); 806 807 for (i = 0; i < ndmas; i++) { 808 if (rbr_rings == NULL || rbr_rings[i] == NULL) { 809 continue; 810 } 811 channel = rbr_rings[i]->rdc; 812 if (enable) { 813 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 814 "==> hxge_rxdma_hw_mode: channel %d (enable)", 815 channel)); 816 rs = hpi_rxdma_cfg_rdc_enable(handle, channel); 817 } else { 818 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 819 "==> hxge_rxdma_hw_mode: channel %d (disable)", 820 channel)); 821 rs = hpi_rxdma_cfg_rdc_disable(handle, channel); 822 } 823 } 824 825 status = ((rs == HPI_SUCCESS) ? HXGE_OK : HXGE_ERROR | rs); 826 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 827 "<== hxge_rxdma_hw_mode: status 0x%x", status)); 828 829 return (status); 830 } 831 832 int 833 hxge_rxdma_get_ring_index(p_hxge_t hxgep, uint16_t channel) 834 { 835 int i, ndmas; 836 uint16_t rdc; 837 p_rx_rbr_rings_t rx_rbr_rings; 838 p_rx_rbr_ring_t *rbr_rings; 839 840 HXGE_DEBUG_MSG((hxgep, RX_CTL, 841 "==> hxge_rxdma_get_ring_index: channel %d", channel)); 842 843 rx_rbr_rings = hxgep->rx_rbr_rings; 844 if (rx_rbr_rings == NULL) { 845 HXGE_DEBUG_MSG((hxgep, RX_CTL, 846 "<== hxge_rxdma_get_ring_index: NULL ring pointer")); 847 return (-1); 848 } 849 850 ndmas = rx_rbr_rings->ndmas; 851 if (!ndmas) { 852 HXGE_DEBUG_MSG((hxgep, RX_CTL, 853 "<== hxge_rxdma_get_ring_index: no channel")); 854 return (-1); 855 } 856 857 HXGE_DEBUG_MSG((hxgep, RX_CTL, 858 "==> hxge_rxdma_get_ring_index (ndmas %d)", ndmas)); 859 860 rbr_rings = rx_rbr_rings->rbr_rings; 861 for (i = 0; i < ndmas; i++) { 862 rdc = rbr_rings[i]->rdc; 863 if (channel == rdc) { 864 HXGE_DEBUG_MSG((hxgep, RX_CTL, 865 "==> hxge_rxdma_get_rbr_ring: " 866 "channel %d (index %d) " 867 "ring %d", channel, i, rbr_rings[i])); 868 869 return (i); 870 } 871 } 872 873 HXGE_DEBUG_MSG((hxgep, RX_CTL, 874 "<== hxge_rxdma_get_rbr_ring_index: not found")); 875 876 return (-1); 877 } 878 879 /* 880 * Static functions start here. 881 */ 882 static p_rx_msg_t 883 hxge_allocb(size_t size, uint32_t pri, p_hxge_dma_common_t dmabuf_p) 884 { 885 p_rx_msg_t hxge_mp = NULL; 886 p_hxge_dma_common_t dmamsg_p; 887 uchar_t *buffer; 888 889 hxge_mp = KMEM_ZALLOC(sizeof (rx_msg_t), KM_NOSLEEP); 890 if (hxge_mp == NULL) { 891 HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, 892 "Allocation of a rx msg failed.")); 893 goto hxge_allocb_exit; 894 } 895 896 hxge_mp->use_buf_pool = B_FALSE; 897 if (dmabuf_p) { 898 hxge_mp->use_buf_pool = B_TRUE; 899 900 dmamsg_p = (p_hxge_dma_common_t)&hxge_mp->buf_dma; 901 *dmamsg_p = *dmabuf_p; 902 dmamsg_p->nblocks = 1; 903 dmamsg_p->block_size = size; 904 dmamsg_p->alength = size; 905 buffer = (uchar_t *)dmabuf_p->kaddrp; 906 907 dmabuf_p->kaddrp = (void *)((char *)dmabuf_p->kaddrp + size); 908 dmabuf_p->ioaddr_pp = (void *) 909 ((char *)dmabuf_p->ioaddr_pp + size); 910 911 dmabuf_p->alength -= size; 912 dmabuf_p->offset += size; 913 dmabuf_p->dma_cookie.dmac_laddress += size; 914 dmabuf_p->dma_cookie.dmac_size -= size; 915 } else { 916 buffer = KMEM_ALLOC(size, KM_NOSLEEP); 917 if (buffer == NULL) { 918 HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, 919 "Allocation of a receive page failed.")); 920 goto hxge_allocb_fail1; 921 } 922 } 923 924 hxge_mp->rx_mblk_p = desballoc(buffer, size, pri, &hxge_mp->freeb); 925 if (hxge_mp->rx_mblk_p == NULL) { 926 HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, "desballoc failed.")); 927 goto hxge_allocb_fail2; 928 } 929 hxge_mp->buffer = buffer; 930 hxge_mp->block_size = size; 931 hxge_mp->freeb.free_func = (void (*) ()) hxge_freeb; 932 hxge_mp->freeb.free_arg = (caddr_t)hxge_mp; 933 hxge_mp->ref_cnt = 1; 934 hxge_mp->free = B_TRUE; 935 hxge_mp->rx_use_bcopy = B_FALSE; 936 937 atomic_inc_32(&hxge_mblks_pending); 938 939 goto hxge_allocb_exit; 940 941 hxge_allocb_fail2: 942 if (!hxge_mp->use_buf_pool) { 943 KMEM_FREE(buffer, size); 944 } 945 hxge_allocb_fail1: 946 KMEM_FREE(hxge_mp, sizeof (rx_msg_t)); 947 hxge_mp = NULL; 948 949 hxge_allocb_exit: 950 return (hxge_mp); 951 } 952 953 p_mblk_t 954 hxge_dupb(p_rx_msg_t hxge_mp, uint_t offset, size_t size) 955 { 956 p_mblk_t mp; 957 958 HXGE_DEBUG_MSG((NULL, MEM_CTL, "==> hxge_dupb")); 959 HXGE_DEBUG_MSG((NULL, MEM_CTL, "hxge_mp = $%p " 960 "offset = 0x%08X " "size = 0x%08X", hxge_mp, offset, size)); 961 962 mp = desballoc(&hxge_mp->buffer[offset], size, 0, &hxge_mp->freeb); 963 if (mp == NULL) { 964 HXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 965 goto hxge_dupb_exit; 966 } 967 968 atomic_inc_32(&hxge_mp->ref_cnt); 969 970 hxge_dupb_exit: 971 HXGE_DEBUG_MSG((NULL, MEM_CTL, "<== hxge_dupb mp = $%p", hxge_mp)); 972 return (mp); 973 } 974 975 p_mblk_t 976 hxge_dupb_bcopy(p_rx_msg_t hxge_mp, uint_t offset, size_t size) 977 { 978 p_mblk_t mp; 979 uchar_t *dp; 980 981 mp = allocb(size + HXGE_RXBUF_EXTRA, 0); 982 if (mp == NULL) { 983 HXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 984 goto hxge_dupb_bcopy_exit; 985 } 986 dp = mp->b_rptr = mp->b_rptr + HXGE_RXBUF_EXTRA; 987 bcopy((void *) &hxge_mp->buffer[offset], dp, size); 988 mp->b_wptr = dp + size; 989 990 hxge_dupb_bcopy_exit: 991 992 HXGE_DEBUG_MSG((NULL, MEM_CTL, "<== hxge_dupb mp = $%p", hxge_mp)); 993 994 return (mp); 995 } 996 997 void hxge_post_page(p_hxge_t hxgep, p_rx_rbr_ring_t rx_rbr_p, 998 p_rx_msg_t rx_msg_p); 999 1000 void 1001 hxge_post_page(p_hxge_t hxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p) 1002 { 1003 hpi_status_t hpi_status; 1004 hxge_status_t status; 1005 int i; 1006 1007 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_post_page")); 1008 1009 /* Reuse this buffer */ 1010 rx_msg_p->free = B_FALSE; 1011 rx_msg_p->cur_usage_cnt = 0; 1012 rx_msg_p->max_usage_cnt = 0; 1013 rx_msg_p->pkt_buf_size = 0; 1014 1015 if (rx_rbr_p->rbr_use_bcopy) { 1016 rx_msg_p->rx_use_bcopy = B_FALSE; 1017 atomic_dec_32(&rx_rbr_p->rbr_consumed); 1018 } 1019 1020 /* 1021 * Get the rbr header pointer and its offset index. 1022 */ 1023 rx_rbr_p->rbr_wr_index = ((rx_rbr_p->rbr_wr_index + 1) & 1024 rx_rbr_p->rbr_wrap_mask); 1025 rx_rbr_p->rbr_desc_vp[rx_rbr_p->rbr_wr_index] = rx_msg_p->shifted_addr; 1026 1027 /* 1028 * Accumulate some buffers in the ring before re-enabling the 1029 * DMA channel, if rbr empty was signaled. 1030 */ 1031 if (!rx_rbr_p->rbr_is_empty) { 1032 hpi_rxdma_rdc_rbr_kick(HXGE_DEV_HPI_HANDLE(hxgep), 1033 rx_rbr_p->rdc, 1); 1034 } else { 1035 rx_rbr_p->accumulate++; 1036 if (rx_rbr_p->accumulate >= HXGE_RBR_EMPTY_THRESHOLD) { 1037 rx_rbr_p->rbr_is_empty = B_FALSE; 1038 rx_rbr_p->accumulate = 0; 1039 1040 /* 1041 * Complete the processing for the RBR Empty by: 1042 * 0) kicking back HXGE_RBR_EMPTY_THRESHOLD 1043 * packets. 1044 * 1) Disable the RX vmac. 1045 * 2) Re-enable the affected DMA channel. 1046 * 3) Re-enable the RX vmac. 1047 */ 1048 hpi_rxdma_rdc_rbr_kick(HXGE_DEV_HPI_HANDLE(hxgep), 1049 rx_rbr_p->rdc, HXGE_RBR_EMPTY_THRESHOLD); 1050 1051 /* 1052 * Disable the RX VMAC, but setting the framelength 1053 * to 0, since there is a hardware bug when disabling 1054 * the vmac. 1055 */ 1056 MUTEX_ENTER(hxgep->genlock); 1057 (void) hpi_vmac_rx_set_framesize( 1058 HXGE_DEV_HPI_HANDLE(hxgep), (uint16_t)0); 1059 1060 hpi_status = hpi_rxdma_cfg_rdc_enable( 1061 HXGE_DEV_HPI_HANDLE(hxgep), rx_rbr_p->rdc); 1062 if (hpi_status != HPI_SUCCESS) { 1063 p_hxge_rx_ring_stats_t rdc_stats; 1064 1065 rdc_stats = 1066 &hxgep->statsp->rdc_stats[rx_rbr_p->rdc]; 1067 rdc_stats->rbr_empty_fail++; 1068 1069 status = hxge_rxdma_fatal_err_recover(hxgep, 1070 rx_rbr_p->rdc); 1071 if (status != HXGE_OK) { 1072 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1073 "hxge(%d): channel(%d) is empty.", 1074 hxgep->instance, rx_rbr_p->rdc)); 1075 } 1076 } 1077 1078 for (i = 0; i < 1024; i++) { 1079 uint64_t value; 1080 RXDMA_REG_READ64(HXGE_DEV_HPI_HANDLE(hxgep), 1081 RDC_STAT, i & 3, &value); 1082 } 1083 1084 /* 1085 * Re-enable the RX VMAC. 1086 */ 1087 (void) hpi_vmac_rx_set_framesize( 1088 HXGE_DEV_HPI_HANDLE(hxgep), 1089 (uint16_t)hxgep->vmac.maxframesize); 1090 MUTEX_EXIT(hxgep->genlock); 1091 } 1092 } 1093 1094 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1095 "<== hxge_post_page (channel %d post_next_index %d)", 1096 rx_rbr_p->rdc, rx_rbr_p->rbr_wr_index)); 1097 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_post_page")); 1098 } 1099 1100 void 1101 hxge_freeb(p_rx_msg_t rx_msg_p) 1102 { 1103 size_t size; 1104 uchar_t *buffer = NULL; 1105 int ref_cnt; 1106 boolean_t free_state = B_FALSE; 1107 rx_rbr_ring_t *ring = rx_msg_p->rx_rbr_p; 1108 1109 HXGE_DEBUG_MSG((NULL, MEM2_CTL, "==> hxge_freeb")); 1110 HXGE_DEBUG_MSG((NULL, MEM2_CTL, 1111 "hxge_freeb:rx_msg_p = $%p (block pending %d)", 1112 rx_msg_p, hxge_mblks_pending)); 1113 1114 if (ring == NULL) 1115 return; 1116 1117 /* 1118 * This is to prevent posting activities while we are recovering 1119 * from fatal errors. This should not be a performance drag since 1120 * ref_cnt != 0 most times. 1121 */ 1122 if (ring->rbr_state == RBR_POSTING) 1123 MUTEX_ENTER(&ring->post_lock); 1124 1125 /* 1126 * First we need to get the free state, then 1127 * atomic decrement the reference count to prevent 1128 * the race condition with the interrupt thread that 1129 * is processing a loaned up buffer block. 1130 */ 1131 free_state = rx_msg_p->free; 1132 ref_cnt = atomic_add_32_nv(&rx_msg_p->ref_cnt, -1); 1133 if (!ref_cnt) { 1134 atomic_dec_32(&hxge_mblks_pending); 1135 1136 buffer = rx_msg_p->buffer; 1137 size = rx_msg_p->block_size; 1138 1139 HXGE_DEBUG_MSG((NULL, MEM2_CTL, "hxge_freeb: " 1140 "will free: rx_msg_p = $%p (block pending %d)", 1141 rx_msg_p, hxge_mblks_pending)); 1142 1143 if (!rx_msg_p->use_buf_pool) { 1144 KMEM_FREE(buffer, size); 1145 } 1146 1147 KMEM_FREE(rx_msg_p, sizeof (rx_msg_t)); 1148 /* 1149 * Decrement the receive buffer ring's reference 1150 * count, too. 1151 */ 1152 atomic_dec_32(&ring->rbr_ref_cnt); 1153 1154 /* 1155 * Free the receive buffer ring, iff 1156 * 1. all the receive buffers have been freed 1157 * 2. and we are in the proper state (that is, 1158 * we are not UNMAPPING). 1159 */ 1160 if (ring->rbr_ref_cnt == 0 && 1161 ring->rbr_state == RBR_UNMAPPED) { 1162 KMEM_FREE(ring, sizeof (*ring)); 1163 /* post_lock has been destroyed already */ 1164 return; 1165 } 1166 } 1167 1168 /* 1169 * Repost buffer. 1170 */ 1171 if (free_state && (ref_cnt == 1)) { 1172 HXGE_DEBUG_MSG((NULL, RX_CTL, 1173 "hxge_freeb: post page $%p:", rx_msg_p)); 1174 if (ring->rbr_state == RBR_POSTING) 1175 hxge_post_page(rx_msg_p->hxgep, ring, rx_msg_p); 1176 } 1177 1178 if (ring->rbr_state == RBR_POSTING) 1179 MUTEX_EXIT(&ring->post_lock); 1180 1181 HXGE_DEBUG_MSG((NULL, MEM2_CTL, "<== hxge_freeb")); 1182 } 1183 1184 uint_t 1185 hxge_rx_intr(caddr_t arg1, caddr_t arg2) 1186 { 1187 p_hxge_ldv_t ldvp = (p_hxge_ldv_t)arg1; 1188 p_hxge_t hxgep = (p_hxge_t)arg2; 1189 p_hxge_ldg_t ldgp; 1190 uint8_t channel; 1191 hpi_handle_t handle; 1192 rdc_stat_t cs; 1193 uint_t serviced = DDI_INTR_UNCLAIMED; 1194 1195 if (ldvp == NULL) { 1196 HXGE_DEBUG_MSG((NULL, RX_INT_CTL, 1197 "<== hxge_rx_intr: arg2 $%p arg1 $%p", hxgep, ldvp)); 1198 return (DDI_INTR_UNCLAIMED); 1199 } 1200 1201 if (arg2 == NULL || (void *) ldvp->hxgep != arg2) { 1202 hxgep = ldvp->hxgep; 1203 } 1204 1205 /* 1206 * If the interface is not started, just swallow the interrupt 1207 * for the logical device and don't rearm it. 1208 */ 1209 if (hxgep->hxge_mac_state != HXGE_MAC_STARTED) 1210 return (DDI_INTR_CLAIMED); 1211 1212 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1213 "==> hxge_rx_intr: arg2 $%p arg1 $%p", hxgep, ldvp)); 1214 1215 /* 1216 * This interrupt handler is for a specific receive dma channel. 1217 */ 1218 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1219 1220 /* 1221 * Get the control and status for this channel. 1222 */ 1223 channel = ldvp->channel; 1224 ldgp = ldvp->ldgp; 1225 RXDMA_REG_READ64(handle, RDC_STAT, channel, &cs.value); 1226 1227 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_intr:channel %d " 1228 "cs 0x%016llx rcrto 0x%x rcrthres %x", 1229 channel, cs.value, cs.bits.rcr_to, cs.bits.rcr_thres)); 1230 1231 hxge_rx_pkts_vring(hxgep, ldvp->vdma_index, ldvp, cs); 1232 serviced = DDI_INTR_CLAIMED; 1233 1234 /* error events. */ 1235 if (cs.value & RDC_STAT_ERROR) { 1236 (void) hxge_rx_err_evnts(hxgep, ldvp->vdma_index, ldvp, cs); 1237 } 1238 1239 hxge_intr_exit: 1240 /* 1241 * Enable the mailbox update interrupt if we want to use mailbox. We 1242 * probably don't need to use mailbox as it only saves us one pio read. 1243 * Also write 1 to rcrthres and rcrto to clear these two edge triggered 1244 * bits. 1245 */ 1246 cs.value &= RDC_STAT_WR1C; 1247 cs.bits.mex = 1; 1248 cs.bits.ptrread = 0; 1249 cs.bits.pktread = 0; 1250 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); 1251 1252 /* 1253 * Rearm this logical group if this is a single device group. 1254 */ 1255 if (ldgp->nldvs == 1) { 1256 ld_intr_mgmt_t mgm; 1257 1258 mgm.value = 0; 1259 mgm.bits.arm = 1; 1260 mgm.bits.timer = ldgp->ldg_timer; 1261 HXGE_REG_WR32(handle, 1262 LD_INTR_MGMT + LDSV_OFFSET(ldgp->ldg), mgm.value); 1263 } 1264 1265 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1266 "<== hxge_rx_intr: serviced %d", serviced)); 1267 1268 return (serviced); 1269 } 1270 1271 static void 1272 hxge_rx_pkts_vring(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp, 1273 rdc_stat_t cs) 1274 { 1275 p_mblk_t mp; 1276 p_rx_rcr_ring_t rcrp; 1277 1278 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts_vring")); 1279 if ((mp = hxge_rx_pkts(hxgep, vindex, ldvp, &rcrp, cs)) == NULL) { 1280 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1281 "<== hxge_rx_pkts_vring: no mp")); 1282 return; 1283 } 1284 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_pkts_vring: $%p", mp)); 1285 1286 #ifdef HXGE_DEBUG 1287 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1288 "==> hxge_rx_pkts_vring:calling mac_rx (NEMO) " 1289 "LEN %d mp $%p mp->b_next $%p rcrp $%p " 1290 "mac_handle $%p", 1291 (mp->b_wptr - mp->b_rptr), mp, mp->b_next, 1292 rcrp, rcrp->rcr_mac_handle)); 1293 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1294 "==> hxge_rx_pkts_vring: dump packets " 1295 "(mp $%p b_rptr $%p b_wptr $%p):\n %s", 1296 mp, mp->b_rptr, mp->b_wptr, 1297 hxge_dump_packet((char *)mp->b_rptr, 64))); 1298 1299 if (mp->b_cont) { 1300 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1301 "==> hxge_rx_pkts_vring: dump b_cont packets " 1302 "(mp->b_cont $%p b_rptr $%p b_wptr $%p):\n %s", 1303 mp->b_cont, mp->b_cont->b_rptr, mp->b_cont->b_wptr, 1304 hxge_dump_packet((char *)mp->b_cont->b_rptr, 1305 mp->b_cont->b_wptr - mp->b_cont->b_rptr))); 1306 } 1307 if (mp->b_next) { 1308 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1309 "==> hxge_rx_pkts_vring: dump next packets " 1310 "(b_rptr $%p): %s", 1311 mp->b_next->b_rptr, 1312 hxge_dump_packet((char *)mp->b_next->b_rptr, 64))); 1313 } 1314 #endif 1315 1316 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1317 "==> hxge_rx_pkts_vring: send packet to stack")); 1318 mac_rx(hxgep->mach, rcrp->rcr_mac_handle, mp); 1319 1320 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rx_pkts_vring")); 1321 } 1322 1323 /*ARGSUSED*/ 1324 mblk_t * 1325 hxge_rx_pkts(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp, 1326 p_rx_rcr_ring_t *rcrp, rdc_stat_t cs) 1327 { 1328 hpi_handle_t handle; 1329 uint8_t channel; 1330 p_rx_rcr_rings_t rx_rcr_rings; 1331 p_rx_rcr_ring_t rcr_p; 1332 uint32_t comp_rd_index; 1333 p_rcr_entry_t rcr_desc_rd_head_p; 1334 p_rcr_entry_t rcr_desc_rd_head_pp; 1335 p_mblk_t nmp, mp_cont, head_mp, *tail_mp; 1336 uint16_t qlen, nrcr_read, npkt_read; 1337 uint32_t qlen_hw, qlen_sw; 1338 uint32_t invalid_rcr_entry; 1339 boolean_t multi; 1340 rdc_rcr_cfg_b_t rcr_cfg_b; 1341 p_rx_mbox_t rx_mboxp; 1342 p_rxdma_mailbox_t mboxp; 1343 uint64_t rcr_head_index, rcr_tail_index; 1344 uint64_t rcr_tail; 1345 uint64_t value; 1346 rdc_rcr_tail_t rcr_tail_reg; 1347 p_hxge_rx_ring_stats_t rdc_stats; 1348 1349 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts:vindex %d " 1350 "channel %d", vindex, ldvp->channel)); 1351 1352 if (!(hxgep->drv_state & STATE_HW_INITIALIZED)) { 1353 return (NULL); 1354 } 1355 1356 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1357 rx_rcr_rings = hxgep->rx_rcr_rings; 1358 rcr_p = rx_rcr_rings->rcr_rings[vindex]; 1359 channel = rcr_p->rdc; 1360 if (channel != ldvp->channel) { 1361 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts:index %d " 1362 "channel %d, and rcr channel %d not matched.", 1363 vindex, ldvp->channel, channel)); 1364 return (NULL); 1365 } 1366 1367 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1368 "==> hxge_rx_pkts: START: rcr channel %d " 1369 "head_p $%p head_pp $%p index %d ", 1370 channel, rcr_p->rcr_desc_rd_head_p, 1371 rcr_p->rcr_desc_rd_head_pp, rcr_p->comp_rd_index)); 1372 1373 rx_mboxp = hxgep->rx_mbox_areas_p->rxmbox_areas[channel]; 1374 mboxp = (p_rxdma_mailbox_t)rx_mboxp->rx_mbox.kaddrp; 1375 1376 (void) hpi_rxdma_rdc_rcr_qlen_get(handle, channel, &qlen); 1377 RXDMA_REG_READ64(handle, RDC_RCR_TAIL, channel, &rcr_tail_reg.value); 1378 rcr_tail = rcr_tail_reg.bits.tail; 1379 1380 if (!qlen) { 1381 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1382 "<== hxge_rx_pkts:rcr channel %d qlen %d (no pkts)", 1383 channel, qlen)); 1384 return (NULL); 1385 } 1386 1387 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_pkts:rcr channel %d " 1388 "qlen %d", channel, qlen)); 1389 1390 comp_rd_index = rcr_p->comp_rd_index; 1391 1392 rcr_desc_rd_head_p = rcr_p->rcr_desc_rd_head_p; 1393 rcr_desc_rd_head_pp = rcr_p->rcr_desc_rd_head_pp; 1394 nrcr_read = npkt_read = 0; 1395 1396 /* 1397 * Number of packets queued (The jumbo or multi packet will be counted 1398 * as only one paccket and it may take up more than one completion 1399 * entry). 1400 */ 1401 qlen_hw = (qlen < hxge_max_rx_pkts) ? qlen : hxge_max_rx_pkts; 1402 head_mp = NULL; 1403 tail_mp = &head_mp; 1404 nmp = mp_cont = NULL; 1405 multi = B_FALSE; 1406 1407 rcr_head_index = rcr_p->rcr_desc_rd_head_p - rcr_p->rcr_desc_first_p; 1408 rcr_tail_index = rcr_tail - rcr_p->rcr_tail_begin; 1409 1410 if (rcr_tail_index >= rcr_head_index) { 1411 qlen_sw = rcr_tail_index - rcr_head_index; 1412 } else { 1413 /* rcr_tail has wrapped around */ 1414 qlen_sw = (rcr_p->comp_size - rcr_head_index) + rcr_tail_index; 1415 } 1416 1417 if (qlen_hw > qlen_sw) { 1418 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1419 "Channel %d, rcr_qlen from reg %d and from rcr_tail %d\n", 1420 channel, qlen_hw, qlen_sw)); 1421 qlen_hw = qlen_sw; 1422 } 1423 1424 while (qlen_hw) { 1425 #ifdef HXGE_DEBUG 1426 hxge_dump_rcr_entry(hxgep, rcr_desc_rd_head_p); 1427 #endif 1428 /* 1429 * Process one completion ring entry. 1430 */ 1431 invalid_rcr_entry = 0; 1432 hxge_receive_packet(hxgep, 1433 rcr_p, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont, 1434 &invalid_rcr_entry); 1435 if (invalid_rcr_entry != 0) { 1436 rdc_stats = rcr_p->rdc_stats; 1437 rdc_stats->rcr_invalids++; 1438 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1439 "Channel %d could only read 0x%x packets, " 1440 "but 0x%x pending\n", channel, npkt_read, qlen_hw)); 1441 break; 1442 } 1443 1444 /* 1445 * message chaining modes (nemo msg chaining) 1446 */ 1447 if (nmp) { 1448 nmp->b_next = NULL; 1449 if (!multi && !mp_cont) { /* frame fits a partition */ 1450 *tail_mp = nmp; 1451 tail_mp = &nmp->b_next; 1452 nmp = NULL; 1453 } else if (multi && !mp_cont) { /* first segment */ 1454 *tail_mp = nmp; 1455 tail_mp = &nmp->b_cont; 1456 } else if (multi && mp_cont) { /* mid of multi segs */ 1457 *tail_mp = mp_cont; 1458 tail_mp = &mp_cont->b_cont; 1459 } else if (!multi && mp_cont) { /* last segment */ 1460 *tail_mp = mp_cont; 1461 tail_mp = &nmp->b_next; 1462 nmp = NULL; 1463 } 1464 } 1465 1466 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1467 "==> hxge_rx_pkts: loop: rcr channel %d " 1468 "before updating: multi %d " 1469 "nrcr_read %d " 1470 "npk read %d " 1471 "head_pp $%p index %d ", 1472 channel, multi, 1473 nrcr_read, npkt_read, rcr_desc_rd_head_pp, comp_rd_index)); 1474 1475 if (!multi) { 1476 qlen_hw--; 1477 npkt_read++; 1478 } 1479 1480 /* 1481 * Update the next read entry. 1482 */ 1483 comp_rd_index = NEXT_ENTRY(comp_rd_index, 1484 rcr_p->comp_wrap_mask); 1485 1486 rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p, 1487 rcr_p->rcr_desc_first_p, rcr_p->rcr_desc_last_p); 1488 1489 nrcr_read++; 1490 1491 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1492 "<== hxge_rx_pkts: (SAM, process one packet) " 1493 "nrcr_read %d", nrcr_read)); 1494 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1495 "==> hxge_rx_pkts: loop: rcr channel %d " 1496 "multi %d nrcr_read %d npk read %d head_pp $%p index %d ", 1497 channel, multi, nrcr_read, npkt_read, rcr_desc_rd_head_pp, 1498 comp_rd_index)); 1499 } 1500 1501 rcr_p->rcr_desc_rd_head_pp = rcr_desc_rd_head_pp; 1502 rcr_p->comp_rd_index = comp_rd_index; 1503 rcr_p->rcr_desc_rd_head_p = rcr_desc_rd_head_p; 1504 1505 /* Adjust the mailbox queue length for a hardware bug workaround */ 1506 mboxp->rcrstat_a.bits.qlen -= npkt_read; 1507 1508 if ((hxgep->intr_timeout != rcr_p->intr_timeout) || 1509 (hxgep->intr_threshold != rcr_p->intr_threshold)) { 1510 rcr_p->intr_timeout = hxgep->intr_timeout; 1511 rcr_p->intr_threshold = hxgep->intr_threshold; 1512 rcr_cfg_b.value = 0x0ULL; 1513 if (rcr_p->intr_timeout) 1514 rcr_cfg_b.bits.entout = 1; 1515 rcr_cfg_b.bits.timeout = rcr_p->intr_timeout; 1516 rcr_cfg_b.bits.pthres = rcr_p->intr_threshold; 1517 RXDMA_REG_WRITE64(handle, RDC_RCR_CFG_B, 1518 channel, rcr_cfg_b.value); 1519 } 1520 1521 cs.bits.pktread = npkt_read; 1522 cs.bits.ptrread = nrcr_read; 1523 value = cs.value; 1524 cs.value &= 0xffffffffULL; 1525 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); 1526 1527 cs.value = value & ~0xffffffffULL; 1528 cs.bits.pktread = 0; 1529 cs.bits.ptrread = 0; 1530 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); 1531 1532 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1533 "==> hxge_rx_pkts: EXIT: rcr channel %d " 1534 "head_pp $%p index %016llx ", 1535 channel, rcr_p->rcr_desc_rd_head_pp, rcr_p->comp_rd_index)); 1536 1537 /* 1538 * Update RCR buffer pointer read and number of packets read. 1539 */ 1540 1541 *rcrp = rcr_p; 1542 1543 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "<== hxge_rx_pkts")); 1544 1545 return (head_mp); 1546 } 1547 1548 #define RCR_ENTRY_PATTERN 0x5a5a6b6b7c7c8d8dULL 1549 #define NO_PORT_BIT 0x20 1550 1551 /*ARGSUSED*/ 1552 void 1553 hxge_receive_packet(p_hxge_t hxgep, 1554 p_rx_rcr_ring_t rcr_p, p_rcr_entry_t rcr_desc_rd_head_p, 1555 boolean_t *multi_p, mblk_t **mp, mblk_t **mp_cont, 1556 uint32_t *invalid_rcr_entry) 1557 { 1558 p_mblk_t nmp = NULL; 1559 uint64_t multi; 1560 uint8_t channel; 1561 1562 boolean_t first_entry = B_TRUE; 1563 boolean_t buffer_free = B_FALSE; 1564 boolean_t error_send_up = B_FALSE; 1565 uint8_t error_type; 1566 uint16_t l2_len; 1567 uint16_t skip_len; 1568 uint8_t pktbufsz_type; 1569 uint64_t rcr_entry; 1570 uint64_t *pkt_buf_addr_pp; 1571 uint64_t *pkt_buf_addr_p; 1572 uint32_t buf_offset; 1573 uint32_t bsize; 1574 uint32_t msg_index; 1575 p_rx_rbr_ring_t rx_rbr_p; 1576 p_rx_msg_t *rx_msg_ring_p; 1577 p_rx_msg_t rx_msg_p; 1578 1579 uint16_t sw_offset_bytes = 0, hdr_size = 0; 1580 hxge_status_t status = HXGE_OK; 1581 boolean_t is_valid = B_FALSE; 1582 p_hxge_rx_ring_stats_t rdc_stats; 1583 uint32_t bytes_read; 1584 uint8_t header = 0; 1585 1586 channel = rcr_p->rdc; 1587 1588 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> hxge_receive_packet")); 1589 1590 first_entry = (*mp == NULL) ? B_TRUE : B_FALSE; 1591 rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); 1592 1593 /* Verify the content of the rcr_entry for a hardware bug workaround */ 1594 if ((rcr_entry == 0x0) || (rcr_entry == RCR_ENTRY_PATTERN)) { 1595 *invalid_rcr_entry = 1; 1596 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "hxge_receive_packet " 1597 "Channel %d invalid RCR entry 0x%llx found, returning\n", 1598 channel, (long long) rcr_entry)); 1599 return; 1600 } 1601 *((uint64_t *)rcr_desc_rd_head_p) = RCR_ENTRY_PATTERN; 1602 1603 multi = (rcr_entry & RCR_MULTI_MASK); 1604 1605 error_type = ((rcr_entry & RCR_ERROR_MASK) >> RCR_ERROR_SHIFT); 1606 l2_len = ((rcr_entry & RCR_L2_LEN_MASK) >> RCR_L2_LEN_SHIFT); 1607 1608 /* 1609 * Hardware does not strip the CRC due bug ID 11451 where 1610 * the hardware mis handles minimum size packets. 1611 */ 1612 l2_len -= ETHERFCSL; 1613 1614 pktbufsz_type = ((rcr_entry & RCR_PKTBUFSZ_MASK) >> 1615 RCR_PKTBUFSZ_SHIFT); 1616 #if defined(__i386) 1617 pkt_buf_addr_pp = (uint64_t *)(uint32_t)((rcr_entry & 1618 RCR_PKT_BUF_ADDR_MASK) << RCR_PKT_BUF_ADDR_SHIFT); 1619 #else 1620 pkt_buf_addr_pp = (uint64_t *)((rcr_entry & RCR_PKT_BUF_ADDR_MASK) << 1621 RCR_PKT_BUF_ADDR_SHIFT); 1622 #endif 1623 1624 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1625 "==> hxge_receive_packet: entryp $%p entry 0x%0llx " 1626 "pkt_buf_addr_pp $%p l2_len %d multi %d " 1627 "error_type 0x%x pktbufsz_type %d ", 1628 rcr_desc_rd_head_p, rcr_entry, pkt_buf_addr_pp, l2_len, 1629 multi, error_type, pktbufsz_type)); 1630 1631 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1632 "==> hxge_receive_packet: entryp $%p entry 0x%0llx " 1633 "pkt_buf_addr_pp $%p l2_len %d multi %d " 1634 "error_type 0x%x ", rcr_desc_rd_head_p, 1635 rcr_entry, pkt_buf_addr_pp, l2_len, multi, error_type)); 1636 1637 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1638 "==> (rbr) hxge_receive_packet: entry 0x%0llx " 1639 "full pkt_buf_addr_pp $%p l2_len %d", 1640 rcr_entry, pkt_buf_addr_pp, l2_len)); 1641 1642 /* get the stats ptr */ 1643 rdc_stats = rcr_p->rdc_stats; 1644 1645 if (!l2_len) { 1646 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1647 "<== hxge_receive_packet: failed: l2 length is 0.")); 1648 return; 1649 } 1650 1651 /* shift 6 bits to get the full io address */ 1652 #if defined(__i386) 1653 pkt_buf_addr_pp = (uint64_t *)((uint32_t)pkt_buf_addr_pp << 1654 RCR_PKT_BUF_ADDR_SHIFT_FULL); 1655 #else 1656 pkt_buf_addr_pp = (uint64_t *)((uint64_t)pkt_buf_addr_pp << 1657 RCR_PKT_BUF_ADDR_SHIFT_FULL); 1658 #endif 1659 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1660 "==> (rbr) hxge_receive_packet: entry 0x%0llx " 1661 "full pkt_buf_addr_pp $%p l2_len %d", 1662 rcr_entry, pkt_buf_addr_pp, l2_len)); 1663 1664 rx_rbr_p = rcr_p->rx_rbr_p; 1665 rx_msg_ring_p = rx_rbr_p->rx_msg_ring; 1666 1667 if (first_entry) { 1668 hdr_size = (rcr_p->full_hdr_flag ? RXDMA_HDR_SIZE_FULL : 1669 RXDMA_HDR_SIZE_DEFAULT); 1670 1671 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1672 "==> hxge_receive_packet: first entry 0x%016llx " 1673 "pkt_buf_addr_pp $%p l2_len %d hdr %d", 1674 rcr_entry, pkt_buf_addr_pp, l2_len, hdr_size)); 1675 } 1676 1677 MUTEX_ENTER(&rcr_p->lock); 1678 MUTEX_ENTER(&rx_rbr_p->lock); 1679 1680 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1681 "==> (rbr 1) hxge_receive_packet: entry 0x%0llx " 1682 "full pkt_buf_addr_pp $%p l2_len %d", 1683 rcr_entry, pkt_buf_addr_pp, l2_len)); 1684 1685 /* 1686 * Packet buffer address in the completion entry points to the starting 1687 * buffer address (offset 0). Use the starting buffer address to locate 1688 * the corresponding kernel address. 1689 */ 1690 status = hxge_rxbuf_pp_to_vp(hxgep, rx_rbr_p, 1691 pktbufsz_type, pkt_buf_addr_pp, &pkt_buf_addr_p, 1692 &buf_offset, &msg_index); 1693 1694 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1695 "==> (rbr 2) hxge_receive_packet: entry 0x%0llx " 1696 "full pkt_buf_addr_pp $%p l2_len %d", 1697 rcr_entry, pkt_buf_addr_pp, l2_len)); 1698 1699 if (status != HXGE_OK) { 1700 MUTEX_EXIT(&rx_rbr_p->lock); 1701 MUTEX_EXIT(&rcr_p->lock); 1702 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1703 "<== hxge_receive_packet: found vaddr failed %d", status)); 1704 return; 1705 } 1706 1707 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1708 "==> (rbr 3) hxge_receive_packet: entry 0x%0llx " 1709 "full pkt_buf_addr_pp $%p l2_len %d", 1710 rcr_entry, pkt_buf_addr_pp, l2_len)); 1711 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1712 "==> (rbr 4 msgindex %d) hxge_receive_packet: entry 0x%0llx " 1713 "full pkt_buf_addr_pp $%p l2_len %d", 1714 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 1715 1716 if (msg_index >= rx_rbr_p->tnblocks) { 1717 MUTEX_EXIT(&rx_rbr_p->lock); 1718 MUTEX_EXIT(&rcr_p->lock); 1719 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1720 "==> hxge_receive_packet: FATAL msg_index (%d) " 1721 "should be smaller than tnblocks (%d)\n", 1722 msg_index, rx_rbr_p->tnblocks)); 1723 return; 1724 } 1725 1726 rx_msg_p = rx_msg_ring_p[msg_index]; 1727 1728 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1729 "==> (rbr 4 msgindex %d) hxge_receive_packet: entry 0x%0llx " 1730 "full pkt_buf_addr_pp $%p l2_len %d", 1731 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 1732 1733 switch (pktbufsz_type) { 1734 case RCR_PKTBUFSZ_0: 1735 bsize = rx_rbr_p->pkt_buf_size0_bytes; 1736 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1737 "==> hxge_receive_packet: 0 buf %d", bsize)); 1738 break; 1739 case RCR_PKTBUFSZ_1: 1740 bsize = rx_rbr_p->pkt_buf_size1_bytes; 1741 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1742 "==> hxge_receive_packet: 1 buf %d", bsize)); 1743 break; 1744 case RCR_PKTBUFSZ_2: 1745 bsize = rx_rbr_p->pkt_buf_size2_bytes; 1746 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1747 "==> hxge_receive_packet: 2 buf %d", bsize)); 1748 break; 1749 case RCR_SINGLE_BLOCK: 1750 bsize = rx_msg_p->block_size; 1751 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1752 "==> hxge_receive_packet: single %d", bsize)); 1753 1754 break; 1755 default: 1756 MUTEX_EXIT(&rx_rbr_p->lock); 1757 MUTEX_EXIT(&rcr_p->lock); 1758 return; 1759 } 1760 1761 DMA_COMMON_SYNC_OFFSET(rx_msg_p->buf_dma, 1762 (buf_offset + sw_offset_bytes), (hdr_size + l2_len), 1763 DDI_DMA_SYNC_FORCPU); 1764 1765 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1766 "==> hxge_receive_packet: after first dump:usage count")); 1767 1768 if (rx_msg_p->cur_usage_cnt == 0) { 1769 if (rx_rbr_p->rbr_use_bcopy) { 1770 atomic_inc_32(&rx_rbr_p->rbr_consumed); 1771 if (rx_rbr_p->rbr_consumed > 1772 rx_rbr_p->rbr_threshold_hi) { 1773 rx_msg_p->rx_use_bcopy = B_TRUE; 1774 } 1775 } 1776 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1777 "==> hxge_receive_packet: buf %d (new block) ", bsize)); 1778 1779 rx_msg_p->pkt_buf_size_code = pktbufsz_type; 1780 rx_msg_p->pkt_buf_size = bsize; 1781 rx_msg_p->cur_usage_cnt = 1; 1782 if (pktbufsz_type == RCR_SINGLE_BLOCK) { 1783 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1784 "==> hxge_receive_packet: buf %d (single block) ", 1785 bsize)); 1786 /* 1787 * Buffer can be reused once the free function is 1788 * called. 1789 */ 1790 rx_msg_p->max_usage_cnt = 1; 1791 buffer_free = B_TRUE; 1792 } else { 1793 rx_msg_p->max_usage_cnt = rx_msg_p->block_size / bsize; 1794 if (rx_msg_p->max_usage_cnt == 1) { 1795 buffer_free = B_TRUE; 1796 } 1797 } 1798 } else { 1799 rx_msg_p->cur_usage_cnt++; 1800 if (rx_msg_p->cur_usage_cnt == rx_msg_p->max_usage_cnt) { 1801 buffer_free = B_TRUE; 1802 } 1803 } 1804 1805 if (rx_msg_p->rx_use_bcopy) { 1806 rdc_stats->pkt_drop++; 1807 atomic_inc_32(&rx_msg_p->ref_cnt); 1808 if (buffer_free == B_TRUE) { 1809 rx_msg_p->free = B_TRUE; 1810 } 1811 1812 MUTEX_EXIT(&rx_rbr_p->lock); 1813 MUTEX_EXIT(&rcr_p->lock); 1814 hxge_freeb(rx_msg_p); 1815 return; 1816 } 1817 1818 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1819 "msgbuf index = %d l2len %d bytes usage %d max_usage %d ", 1820 msg_index, l2_len, 1821 rx_msg_p->cur_usage_cnt, rx_msg_p->max_usage_cnt)); 1822 1823 if (error_type) { 1824 rdc_stats->ierrors++; 1825 /* Update error stats */ 1826 rdc_stats->errlog.compl_err_type = error_type; 1827 HXGE_FM_REPORT_ERROR(hxgep, NULL, HXGE_FM_EREPORT_RDMC_RCR_ERR); 1828 1829 if (error_type & RCR_CTRL_FIFO_DED) { 1830 rdc_stats->ctrl_fifo_ecc_err++; 1831 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1832 " hxge_receive_packet: " 1833 " channel %d RCR ctrl_fifo_ded error", channel)); 1834 } else if (error_type & RCR_DATA_FIFO_DED) { 1835 rdc_stats->data_fifo_ecc_err++; 1836 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1837 " hxge_receive_packet: channel %d" 1838 " RCR data_fifo_ded error", channel)); 1839 } 1840 1841 /* 1842 * Update and repost buffer block if max usage count is 1843 * reached. 1844 */ 1845 if (error_send_up == B_FALSE) { 1846 atomic_inc_32(&rx_msg_p->ref_cnt); 1847 if (buffer_free == B_TRUE) { 1848 rx_msg_p->free = B_TRUE; 1849 } 1850 1851 MUTEX_EXIT(&rx_rbr_p->lock); 1852 MUTEX_EXIT(&rcr_p->lock); 1853 hxge_freeb(rx_msg_p); 1854 return; 1855 } 1856 } 1857 1858 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1859 "==> hxge_receive_packet: DMA sync second ")); 1860 1861 bytes_read = rcr_p->rcvd_pkt_bytes; 1862 skip_len = sw_offset_bytes + hdr_size; 1863 1864 if (first_entry) { 1865 header = rx_msg_p->buffer[buf_offset]; 1866 } 1867 1868 if (!rx_msg_p->rx_use_bcopy) { 1869 /* 1870 * For loaned up buffers, the driver reference count 1871 * will be incremented first and then the free state. 1872 */ 1873 if ((nmp = hxge_dupb(rx_msg_p, buf_offset, bsize)) != NULL) { 1874 if (first_entry) { 1875 nmp->b_rptr = &nmp->b_rptr[skip_len]; 1876 if (l2_len < bsize - skip_len) { 1877 nmp->b_wptr = &nmp->b_rptr[l2_len]; 1878 } else { 1879 nmp->b_wptr = &nmp->b_rptr[bsize 1880 - skip_len]; 1881 } 1882 } else { 1883 if (l2_len - bytes_read < bsize) { 1884 nmp->b_wptr = 1885 &nmp->b_rptr[l2_len - bytes_read]; 1886 } else { 1887 nmp->b_wptr = &nmp->b_rptr[bsize]; 1888 } 1889 } 1890 } 1891 } else { 1892 if (first_entry) { 1893 nmp = hxge_dupb_bcopy(rx_msg_p, buf_offset + skip_len, 1894 l2_len < bsize - skip_len ? 1895 l2_len : bsize - skip_len); 1896 } else { 1897 nmp = hxge_dupb_bcopy(rx_msg_p, buf_offset, 1898 l2_len - bytes_read < bsize ? 1899 l2_len - bytes_read : bsize); 1900 } 1901 } 1902 1903 if (nmp != NULL) { 1904 if (first_entry) 1905 bytes_read = nmp->b_wptr - nmp->b_rptr; 1906 else 1907 bytes_read += nmp->b_wptr - nmp->b_rptr; 1908 1909 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1910 "==> hxge_receive_packet after dupb: " 1911 "rbr consumed %d " 1912 "pktbufsz_type %d " 1913 "nmp $%p rptr $%p wptr $%p " 1914 "buf_offset %d bzise %d l2_len %d skip_len %d", 1915 rx_rbr_p->rbr_consumed, 1916 pktbufsz_type, 1917 nmp, nmp->b_rptr, nmp->b_wptr, 1918 buf_offset, bsize, l2_len, skip_len)); 1919 } else { 1920 cmn_err(CE_WARN, "!hxge_receive_packet: update stats (error)"); 1921 1922 atomic_inc_32(&rx_msg_p->ref_cnt); 1923 if (buffer_free == B_TRUE) { 1924 rx_msg_p->free = B_TRUE; 1925 } 1926 1927 MUTEX_EXIT(&rx_rbr_p->lock); 1928 MUTEX_EXIT(&rcr_p->lock); 1929 hxge_freeb(rx_msg_p); 1930 return; 1931 } 1932 1933 if (buffer_free == B_TRUE) { 1934 rx_msg_p->free = B_TRUE; 1935 } 1936 1937 /* 1938 * ERROR, FRAG and PKT_TYPE are only reported in the first entry. If a 1939 * packet is not fragmented and no error bit is set, then L4 checksum 1940 * is OK. 1941 */ 1942 is_valid = (nmp != NULL); 1943 if (first_entry) { 1944 rdc_stats->ipackets++; /* count only 1st seg for jumbo */ 1945 if (l2_len > (STD_FRAME_SIZE - ETHERFCSL)) 1946 rdc_stats->jumbo_pkts++; 1947 rdc_stats->ibytes += skip_len + l2_len < bsize ? 1948 l2_len : bsize; 1949 } else { 1950 /* 1951 * Add the current portion of the packet to the kstats. 1952 * The current portion of the packet is calculated by using 1953 * length of the packet and the previously received portion. 1954 */ 1955 rdc_stats->ibytes += l2_len - rcr_p->rcvd_pkt_bytes < bsize ? 1956 l2_len - rcr_p->rcvd_pkt_bytes : bsize; 1957 } 1958 1959 rcr_p->rcvd_pkt_bytes = bytes_read; 1960 1961 if (rx_msg_p->free && rx_msg_p->rx_use_bcopy) { 1962 atomic_inc_32(&rx_msg_p->ref_cnt); 1963 MUTEX_EXIT(&rx_rbr_p->lock); 1964 MUTEX_EXIT(&rcr_p->lock); 1965 hxge_freeb(rx_msg_p); 1966 } else { 1967 MUTEX_EXIT(&rx_rbr_p->lock); 1968 MUTEX_EXIT(&rcr_p->lock); 1969 } 1970 1971 if (is_valid) { 1972 nmp->b_cont = NULL; 1973 if (first_entry) { 1974 *mp = nmp; 1975 *mp_cont = NULL; 1976 } else { 1977 *mp_cont = nmp; 1978 } 1979 } 1980 1981 /* 1982 * Update stats and hardware checksuming. 1983 */ 1984 if (is_valid && !multi) { 1985 if (!(header & NO_PORT_BIT) && !error_type) { 1986 (void) hcksum_assoc(nmp, NULL, NULL, 0, 0, 0, 0, 1987 HCK_FULLCKSUM_OK | HCK_FULLCKSUM, 0); 1988 1989 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1990 "==> hxge_receive_packet: Full tcp/udp cksum " 1991 "is_valid 0x%x multi %d error %d", 1992 is_valid, multi, error_type)); 1993 } 1994 } 1995 1996 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1997 "==> hxge_receive_packet: *mp 0x%016llx", *mp)); 1998 1999 *multi_p = (multi == RCR_MULTI_MASK); 2000 2001 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_receive_packet: " 2002 "multi %d nmp 0x%016llx *mp 0x%016llx *mp_cont 0x%016llx", 2003 *multi_p, nmp, *mp, *mp_cont)); 2004 } 2005 2006 static void 2007 hxge_rx_rbr_empty_recover(p_hxge_t hxgep, uint8_t channel) 2008 { 2009 hpi_handle_t handle; 2010 p_rx_rcr_ring_t rcrp; 2011 p_rx_rbr_ring_t rbrp; 2012 2013 rcrp = hxgep->rx_rcr_rings->rcr_rings[channel]; 2014 rbrp = rcrp->rx_rbr_p; 2015 handle = HXGE_DEV_HPI_HANDLE(hxgep); 2016 2017 /* 2018 * Wait for the channel to be quiet 2019 */ 2020 (void) hpi_rxdma_cfg_rdc_wait_for_qst(handle, channel); 2021 2022 /* 2023 * Post page will accumulate some buffers before re-enabling 2024 * the DMA channel. 2025 */ 2026 MUTEX_ENTER(&rbrp->post_lock); 2027 rbrp->rbr_is_empty = B_TRUE; 2028 MUTEX_EXIT(&rbrp->post_lock); 2029 } 2030 2031 /*ARGSUSED*/ 2032 static hxge_status_t 2033 hxge_rx_err_evnts(p_hxge_t hxgep, uint_t index, p_hxge_ldv_t ldvp, 2034 rdc_stat_t cs) 2035 { 2036 p_hxge_rx_ring_stats_t rdc_stats; 2037 hpi_handle_t handle; 2038 boolean_t rxchan_fatal = B_FALSE; 2039 uint8_t channel; 2040 hxge_status_t status = HXGE_OK; 2041 uint64_t cs_val; 2042 2043 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_rx_err_evnts")); 2044 2045 handle = HXGE_DEV_HPI_HANDLE(hxgep); 2046 channel = ldvp->channel; 2047 2048 /* Clear the interrupts */ 2049 cs.bits.pktread = 0; 2050 cs.bits.ptrread = 0; 2051 cs_val = cs.value & RDC_STAT_WR1C; 2052 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs_val); 2053 2054 rdc_stats = &hxgep->statsp->rdc_stats[ldvp->vdma_index]; 2055 2056 if (cs.bits.rbr_cpl_to) { 2057 rdc_stats->rbr_tmout++; 2058 HXGE_FM_REPORT_ERROR(hxgep, channel, 2059 HXGE_FM_EREPORT_RDMC_RBR_CPL_TO); 2060 rxchan_fatal = B_TRUE; 2061 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2062 "==> hxge_rx_err_evnts(channel %d): " 2063 "fatal error: rx_rbr_timeout", channel)); 2064 } 2065 2066 if ((cs.bits.rcr_shadow_par_err) || (cs.bits.rbr_prefetch_par_err)) { 2067 (void) hpi_rxdma_ring_perr_stat_get(handle, 2068 &rdc_stats->errlog.pre_par, &rdc_stats->errlog.sha_par); 2069 } 2070 2071 if (cs.bits.rcr_shadow_par_err) { 2072 rdc_stats->rcr_sha_par++; 2073 HXGE_FM_REPORT_ERROR(hxgep, channel, 2074 HXGE_FM_EREPORT_RDMC_RCR_SHA_PAR); 2075 rxchan_fatal = B_TRUE; 2076 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2077 "==> hxge_rx_err_evnts(channel %d): " 2078 "fatal error: rcr_shadow_par_err", channel)); 2079 } 2080 2081 if (cs.bits.rbr_prefetch_par_err) { 2082 rdc_stats->rbr_pre_par++; 2083 HXGE_FM_REPORT_ERROR(hxgep, channel, 2084 HXGE_FM_EREPORT_RDMC_RBR_PRE_PAR); 2085 rxchan_fatal = B_TRUE; 2086 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2087 "==> hxge_rx_err_evnts(channel %d): " 2088 "fatal error: rbr_prefetch_par_err", channel)); 2089 } 2090 2091 if (cs.bits.rbr_pre_empty) { 2092 rdc_stats->rbr_pre_empty++; 2093 HXGE_FM_REPORT_ERROR(hxgep, channel, 2094 HXGE_FM_EREPORT_RDMC_RBR_PRE_EMPTY); 2095 rxchan_fatal = B_TRUE; 2096 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2097 "==> hxge_rx_err_evnts(channel %d): " 2098 "fatal error: rbr_pre_empty", channel)); 2099 } 2100 2101 if (cs.bits.peu_resp_err) { 2102 rdc_stats->peu_resp_err++; 2103 HXGE_FM_REPORT_ERROR(hxgep, channel, 2104 HXGE_FM_EREPORT_RDMC_PEU_RESP_ERR); 2105 rxchan_fatal = B_TRUE; 2106 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2107 "==> hxge_rx_err_evnts(channel %d): " 2108 "fatal error: peu_resp_err", channel)); 2109 } 2110 2111 if (cs.bits.rcr_thres) { 2112 rdc_stats->rcr_thres++; 2113 } 2114 2115 if (cs.bits.rcr_to) { 2116 rdc_stats->rcr_to++; 2117 } 2118 2119 if (cs.bits.rcr_shadow_full) { 2120 rdc_stats->rcr_shadow_full++; 2121 HXGE_FM_REPORT_ERROR(hxgep, channel, 2122 HXGE_FM_EREPORT_RDMC_RCR_SHA_FULL); 2123 rxchan_fatal = B_TRUE; 2124 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2125 "==> hxge_rx_err_evnts(channel %d): " 2126 "fatal error: rcr_shadow_full", channel)); 2127 } 2128 2129 if (cs.bits.rcr_full) { 2130 rdc_stats->rcrfull++; 2131 HXGE_FM_REPORT_ERROR(hxgep, channel, 2132 HXGE_FM_EREPORT_RDMC_RCRFULL); 2133 rxchan_fatal = B_TRUE; 2134 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2135 "==> hxge_rx_err_evnts(channel %d): " 2136 "fatal error: rcrfull error", channel)); 2137 } 2138 2139 if (cs.bits.rbr_empty) { 2140 rdc_stats->rbr_empty++; 2141 hxge_rx_rbr_empty_recover(hxgep, channel); 2142 } 2143 2144 if (cs.bits.rbr_full) { 2145 rdc_stats->rbrfull++; 2146 HXGE_FM_REPORT_ERROR(hxgep, channel, 2147 HXGE_FM_EREPORT_RDMC_RBRFULL); 2148 rxchan_fatal = B_TRUE; 2149 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2150 "==> hxge_rx_err_evnts(channel %d): " 2151 "fatal error: rbr_full error", channel)); 2152 } 2153 2154 if (rxchan_fatal) { 2155 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2156 " hxge_rx_err_evnts: fatal error on Channel #%d\n", 2157 channel)); 2158 status = hxge_rxdma_fatal_err_recover(hxgep, channel); 2159 if (status == HXGE_OK) { 2160 FM_SERVICE_RESTORED(hxgep); 2161 } 2162 } 2163 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_rx_err_evnts")); 2164 2165 return (status); 2166 } 2167 2168 static hxge_status_t 2169 hxge_map_rxdma(p_hxge_t hxgep) 2170 { 2171 int i, ndmas; 2172 uint16_t channel; 2173 p_rx_rbr_rings_t rx_rbr_rings; 2174 p_rx_rbr_ring_t *rbr_rings; 2175 p_rx_rcr_rings_t rx_rcr_rings; 2176 p_rx_rcr_ring_t *rcr_rings; 2177 p_rx_mbox_areas_t rx_mbox_areas_p; 2178 p_rx_mbox_t *rx_mbox_p; 2179 p_hxge_dma_pool_t dma_buf_poolp; 2180 p_hxge_dma_common_t *dma_buf_p; 2181 p_hxge_dma_pool_t dma_rbr_cntl_poolp; 2182 p_hxge_dma_common_t *dma_rbr_cntl_p; 2183 p_hxge_dma_pool_t dma_rcr_cntl_poolp; 2184 p_hxge_dma_common_t *dma_rcr_cntl_p; 2185 p_hxge_dma_pool_t dma_mbox_cntl_poolp; 2186 p_hxge_dma_common_t *dma_mbox_cntl_p; 2187 uint32_t *num_chunks; 2188 hxge_status_t status = HXGE_OK; 2189 2190 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_map_rxdma")); 2191 2192 dma_buf_poolp = hxgep->rx_buf_pool_p; 2193 dma_rbr_cntl_poolp = hxgep->rx_rbr_cntl_pool_p; 2194 dma_rcr_cntl_poolp = hxgep->rx_rcr_cntl_pool_p; 2195 dma_mbox_cntl_poolp = hxgep->rx_mbox_cntl_pool_p; 2196 2197 if (!dma_buf_poolp->buf_allocated || 2198 !dma_rbr_cntl_poolp->buf_allocated || 2199 !dma_rcr_cntl_poolp->buf_allocated || 2200 !dma_mbox_cntl_poolp->buf_allocated) { 2201 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2202 "<== hxge_map_rxdma: buf not allocated")); 2203 return (HXGE_ERROR); 2204 } 2205 2206 ndmas = dma_buf_poolp->ndmas; 2207 if (!ndmas) { 2208 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2209 "<== hxge_map_rxdma: no dma allocated")); 2210 return (HXGE_ERROR); 2211 } 2212 2213 num_chunks = dma_buf_poolp->num_chunks; 2214 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2215 dma_rbr_cntl_p = dma_rbr_cntl_poolp->dma_buf_pool_p; 2216 dma_rcr_cntl_p = dma_rcr_cntl_poolp->dma_buf_pool_p; 2217 dma_mbox_cntl_p = dma_mbox_cntl_poolp->dma_buf_pool_p; 2218 2219 rx_rbr_rings = (p_rx_rbr_rings_t) 2220 KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2221 rbr_rings = (p_rx_rbr_ring_t *)KMEM_ZALLOC( 2222 sizeof (p_rx_rbr_ring_t) * ndmas, KM_SLEEP); 2223 2224 rx_rcr_rings = (p_rx_rcr_rings_t) 2225 KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2226 rcr_rings = (p_rx_rcr_ring_t *)KMEM_ZALLOC( 2227 sizeof (p_rx_rcr_ring_t) * ndmas, KM_SLEEP); 2228 2229 rx_mbox_areas_p = (p_rx_mbox_areas_t) 2230 KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2231 rx_mbox_p = (p_rx_mbox_t *)KMEM_ZALLOC( 2232 sizeof (p_rx_mbox_t) * ndmas, KM_SLEEP); 2233 2234 /* 2235 * Timeout should be set based on the system clock divider. 2236 * The following timeout value of 1 assumes that the 2237 * granularity (1000) is 3 microseconds running at 300MHz. 2238 */ 2239 2240 hxgep->intr_threshold = RXDMA_RCR_PTHRES_DEFAULT; 2241 hxgep->intr_timeout = RXDMA_RCR_TO_DEFAULT; 2242 2243 /* 2244 * Map descriptors from the buffer polls for each dam channel. 2245 */ 2246 for (i = 0; i < ndmas; i++) { 2247 /* 2248 * Set up and prepare buffer blocks, descriptors and mailbox. 2249 */ 2250 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 2251 status = hxge_map_rxdma_channel(hxgep, channel, 2252 (p_hxge_dma_common_t *)&dma_buf_p[i], 2253 (p_rx_rbr_ring_t *)&rbr_rings[i], 2254 num_chunks[i], 2255 (p_hxge_dma_common_t *)&dma_rbr_cntl_p[i], 2256 (p_hxge_dma_common_t *)&dma_rcr_cntl_p[i], 2257 (p_hxge_dma_common_t *)&dma_mbox_cntl_p[i], 2258 (p_rx_rcr_ring_t *)&rcr_rings[i], 2259 (p_rx_mbox_t *)&rx_mbox_p[i]); 2260 if (status != HXGE_OK) { 2261 goto hxge_map_rxdma_fail1; 2262 } 2263 rbr_rings[i]->index = (uint16_t)i; 2264 rcr_rings[i]->index = (uint16_t)i; 2265 rcr_rings[i]->rdc_stats = &hxgep->statsp->rdc_stats[i]; 2266 } 2267 2268 rx_rbr_rings->ndmas = rx_rcr_rings->ndmas = ndmas; 2269 rx_rbr_rings->rbr_rings = rbr_rings; 2270 hxgep->rx_rbr_rings = rx_rbr_rings; 2271 rx_rcr_rings->rcr_rings = rcr_rings; 2272 hxgep->rx_rcr_rings = rx_rcr_rings; 2273 2274 rx_mbox_areas_p->rxmbox_areas = rx_mbox_p; 2275 hxgep->rx_mbox_areas_p = rx_mbox_areas_p; 2276 2277 goto hxge_map_rxdma_exit; 2278 2279 hxge_map_rxdma_fail1: 2280 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2281 "==> hxge_map_rxdma: unmap rbr,rcr (status 0x%x channel %d i %d)", 2282 status, channel, i)); 2283 i--; 2284 for (; i >= 0; i--) { 2285 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 2286 hxge_unmap_rxdma_channel(hxgep, channel, 2287 rbr_rings[i], rcr_rings[i], rx_mbox_p[i]); 2288 } 2289 2290 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2291 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2292 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2293 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2294 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2295 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2296 2297 hxge_map_rxdma_exit: 2298 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2299 "<== hxge_map_rxdma: (status 0x%x channel %d)", status, channel)); 2300 2301 return (status); 2302 } 2303 2304 static void 2305 hxge_unmap_rxdma(p_hxge_t hxgep) 2306 { 2307 int i, ndmas; 2308 uint16_t channel; 2309 p_rx_rbr_rings_t rx_rbr_rings; 2310 p_rx_rbr_ring_t *rbr_rings; 2311 p_rx_rcr_rings_t rx_rcr_rings; 2312 p_rx_rcr_ring_t *rcr_rings; 2313 p_rx_mbox_areas_t rx_mbox_areas_p; 2314 p_rx_mbox_t *rx_mbox_p; 2315 p_hxge_dma_pool_t dma_buf_poolp; 2316 p_hxge_dma_pool_t dma_rbr_cntl_poolp; 2317 p_hxge_dma_pool_t dma_rcr_cntl_poolp; 2318 p_hxge_dma_pool_t dma_mbox_cntl_poolp; 2319 p_hxge_dma_common_t *dma_buf_p; 2320 2321 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_unmap_rxdma")); 2322 2323 dma_buf_poolp = hxgep->rx_buf_pool_p; 2324 dma_rbr_cntl_poolp = hxgep->rx_rbr_cntl_pool_p; 2325 dma_rcr_cntl_poolp = hxgep->rx_rcr_cntl_pool_p; 2326 dma_mbox_cntl_poolp = hxgep->rx_mbox_cntl_pool_p; 2327 2328 if (!dma_buf_poolp->buf_allocated || 2329 !dma_rbr_cntl_poolp->buf_allocated || 2330 !dma_rcr_cntl_poolp->buf_allocated || 2331 !dma_mbox_cntl_poolp->buf_allocated) { 2332 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2333 "<== hxge_unmap_rxdma: NULL buf pointers")); 2334 return; 2335 } 2336 2337 rx_rbr_rings = hxgep->rx_rbr_rings; 2338 rx_rcr_rings = hxgep->rx_rcr_rings; 2339 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 2340 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2341 "<== hxge_unmap_rxdma: NULL pointers")); 2342 return; 2343 } 2344 2345 ndmas = rx_rbr_rings->ndmas; 2346 if (!ndmas) { 2347 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2348 "<== hxge_unmap_rxdma: no channel")); 2349 return; 2350 } 2351 2352 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2353 "==> hxge_unmap_rxdma (ndmas %d)", ndmas)); 2354 2355 rbr_rings = rx_rbr_rings->rbr_rings; 2356 rcr_rings = rx_rcr_rings->rcr_rings; 2357 rx_mbox_areas_p = hxgep->rx_mbox_areas_p; 2358 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 2359 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2360 2361 for (i = 0; i < ndmas; i++) { 2362 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 2363 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2364 "==> hxge_unmap_rxdma (ndmas %d) channel %d", 2365 ndmas, channel)); 2366 (void) hxge_unmap_rxdma_channel(hxgep, channel, 2367 (p_rx_rbr_ring_t)rbr_rings[i], 2368 (p_rx_rcr_ring_t)rcr_rings[i], 2369 (p_rx_mbox_t)rx_mbox_p[i]); 2370 } 2371 2372 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2373 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2374 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2375 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2376 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2377 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2378 2379 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_unmap_rxdma")); 2380 } 2381 2382 hxge_status_t 2383 hxge_map_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 2384 p_hxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 2385 uint32_t num_chunks, p_hxge_dma_common_t *dma_rbr_cntl_p, 2386 p_hxge_dma_common_t *dma_rcr_cntl_p, p_hxge_dma_common_t *dma_mbox_cntl_p, 2387 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 2388 { 2389 int status = HXGE_OK; 2390 2391 /* 2392 * Set up and prepare buffer blocks, descriptors and mailbox. 2393 */ 2394 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2395 "==> hxge_map_rxdma_channel (channel %d)", channel)); 2396 2397 /* 2398 * Receive buffer blocks 2399 */ 2400 status = hxge_map_rxdma_channel_buf_ring(hxgep, channel, 2401 dma_buf_p, rbr_p, num_chunks); 2402 if (status != HXGE_OK) { 2403 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2404 "==> hxge_map_rxdma_channel (channel %d): " 2405 "map buffer failed 0x%x", channel, status)); 2406 goto hxge_map_rxdma_channel_exit; 2407 } 2408 2409 /* 2410 * Receive block ring, completion ring and mailbox. 2411 */ 2412 status = hxge_map_rxdma_channel_cfg_ring(hxgep, channel, 2413 dma_rbr_cntl_p, dma_rcr_cntl_p, dma_mbox_cntl_p, 2414 rbr_p, rcr_p, rx_mbox_p); 2415 if (status != HXGE_OK) { 2416 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2417 "==> hxge_map_rxdma_channel (channel %d): " 2418 "map config failed 0x%x", channel, status)); 2419 goto hxge_map_rxdma_channel_fail2; 2420 } 2421 goto hxge_map_rxdma_channel_exit; 2422 2423 hxge_map_rxdma_channel_fail3: 2424 /* Free rbr, rcr */ 2425 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2426 "==> hxge_map_rxdma_channel: free rbr/rcr (status 0x%x channel %d)", 2427 status, channel)); 2428 hxge_unmap_rxdma_channel_cfg_ring(hxgep, *rcr_p, *rx_mbox_p); 2429 2430 hxge_map_rxdma_channel_fail2: 2431 /* Free buffer blocks */ 2432 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2433 "==> hxge_map_rxdma_channel: free rx buffers" 2434 "(hxgep 0x%x status 0x%x channel %d)", 2435 hxgep, status, channel)); 2436 hxge_unmap_rxdma_channel_buf_ring(hxgep, *rbr_p); 2437 2438 status = HXGE_ERROR; 2439 2440 hxge_map_rxdma_channel_exit: 2441 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2442 "<== hxge_map_rxdma_channel: (hxgep 0x%x status 0x%x channel %d)", 2443 hxgep, status, channel)); 2444 2445 return (status); 2446 } 2447 2448 /*ARGSUSED*/ 2449 static void 2450 hxge_unmap_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 2451 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 2452 { 2453 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2454 "==> hxge_unmap_rxdma_channel (channel %d)", channel)); 2455 2456 /* 2457 * unmap receive block ring, completion ring and mailbox. 2458 */ 2459 (void) hxge_unmap_rxdma_channel_cfg_ring(hxgep, rcr_p, rx_mbox_p); 2460 2461 /* unmap buffer blocks */ 2462 (void) hxge_unmap_rxdma_channel_buf_ring(hxgep, rbr_p); 2463 2464 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_unmap_rxdma_channel")); 2465 } 2466 2467 /*ARGSUSED*/ 2468 static hxge_status_t 2469 hxge_map_rxdma_channel_cfg_ring(p_hxge_t hxgep, uint16_t dma_channel, 2470 p_hxge_dma_common_t *dma_rbr_cntl_p, p_hxge_dma_common_t *dma_rcr_cntl_p, 2471 p_hxge_dma_common_t *dma_mbox_cntl_p, p_rx_rbr_ring_t *rbr_p, 2472 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 2473 { 2474 p_rx_rbr_ring_t rbrp; 2475 p_rx_rcr_ring_t rcrp; 2476 p_rx_mbox_t mboxp; 2477 p_hxge_dma_common_t cntl_dmap; 2478 p_hxge_dma_common_t dmap; 2479 p_rx_msg_t *rx_msg_ring; 2480 p_rx_msg_t rx_msg_p; 2481 rdc_rbr_cfg_a_t *rcfga_p; 2482 rdc_rbr_cfg_b_t *rcfgb_p; 2483 rdc_rcr_cfg_a_t *cfga_p; 2484 rdc_rcr_cfg_b_t *cfgb_p; 2485 rdc_rx_cfg1_t *cfig1_p; 2486 rdc_rx_cfg2_t *cfig2_p; 2487 rdc_rbr_kick_t *kick_p; 2488 uint32_t dmaaddrp; 2489 uint32_t *rbr_vaddrp; 2490 uint32_t bkaddr; 2491 hxge_status_t status = HXGE_OK; 2492 int i; 2493 uint32_t hxge_port_rcr_size; 2494 2495 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2496 "==> hxge_map_rxdma_channel_cfg_ring")); 2497 2498 cntl_dmap = *dma_rbr_cntl_p; 2499 2500 /* 2501 * Map in the receive block ring 2502 */ 2503 rbrp = *rbr_p; 2504 dmap = (p_hxge_dma_common_t)&rbrp->rbr_desc; 2505 hxge_setup_dma_common(dmap, cntl_dmap, rbrp->rbb_max, 4); 2506 2507 /* 2508 * Zero out buffer block ring descriptors. 2509 */ 2510 bzero((caddr_t)dmap->kaddrp, dmap->alength); 2511 2512 rcfga_p = &(rbrp->rbr_cfga); 2513 rcfgb_p = &(rbrp->rbr_cfgb); 2514 kick_p = &(rbrp->rbr_kick); 2515 rcfga_p->value = 0; 2516 rcfgb_p->value = 0; 2517 kick_p->value = 0; 2518 rbrp->rbr_addr = dmap->dma_cookie.dmac_laddress; 2519 rcfga_p->value = (rbrp->rbr_addr & 2520 (RBR_CFIG_A_STDADDR_MASK | RBR_CFIG_A_STDADDR_BASE_MASK)); 2521 rcfga_p->value |= ((uint64_t)rbrp->rbb_max << RBR_CFIG_A_LEN_SHIFT); 2522 2523 /* XXXX: how to choose packet buffer sizes */ 2524 rcfgb_p->bits.bufsz0 = rbrp->pkt_buf_size0; 2525 rcfgb_p->bits.vld0 = 1; 2526 rcfgb_p->bits.bufsz1 = rbrp->pkt_buf_size1; 2527 rcfgb_p->bits.vld1 = 1; 2528 rcfgb_p->bits.bufsz2 = rbrp->pkt_buf_size2; 2529 rcfgb_p->bits.vld2 = 1; 2530 rcfgb_p->bits.bksize = hxgep->rx_bksize_code; 2531 2532 /* 2533 * For each buffer block, enter receive block address to the ring. 2534 */ 2535 rbr_vaddrp = (uint32_t *)dmap->kaddrp; 2536 rbrp->rbr_desc_vp = (uint32_t *)dmap->kaddrp; 2537 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2538 "==> hxge_map_rxdma_channel_cfg_ring: channel %d " 2539 "rbr_vaddrp $%p", dma_channel, rbr_vaddrp)); 2540 2541 rx_msg_ring = rbrp->rx_msg_ring; 2542 for (i = 0; i < rbrp->tnblocks; i++) { 2543 rx_msg_p = rx_msg_ring[i]; 2544 rx_msg_p->hxgep = hxgep; 2545 rx_msg_p->rx_rbr_p = rbrp; 2546 bkaddr = (uint32_t) 2547 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 2548 RBR_BKADDR_SHIFT)); 2549 rx_msg_p->free = B_FALSE; 2550 rx_msg_p->max_usage_cnt = 0xbaddcafe; 2551 2552 *rbr_vaddrp++ = bkaddr; 2553 } 2554 2555 kick_p->bits.bkadd = rbrp->rbb_max; 2556 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 2557 2558 rbrp->rbr_rd_index = 0; 2559 2560 rbrp->rbr_consumed = 0; 2561 rbrp->rbr_use_bcopy = B_TRUE; 2562 rbrp->rbr_bufsize_type = RCR_PKTBUFSZ_0; 2563 2564 /* 2565 * Do bcopy on packets greater than bcopy size once the lo threshold is 2566 * reached. This lo threshold should be less than the hi threshold. 2567 * 2568 * Do bcopy on every packet once the hi threshold is reached. 2569 */ 2570 if (hxge_rx_threshold_lo >= hxge_rx_threshold_hi) { 2571 /* default it to use hi */ 2572 hxge_rx_threshold_lo = hxge_rx_threshold_hi; 2573 } 2574 if (hxge_rx_buf_size_type > HXGE_RBR_TYPE2) { 2575 hxge_rx_buf_size_type = HXGE_RBR_TYPE2; 2576 } 2577 rbrp->rbr_bufsize_type = hxge_rx_buf_size_type; 2578 2579 switch (hxge_rx_threshold_hi) { 2580 default: 2581 case HXGE_RX_COPY_NONE: 2582 /* Do not do bcopy at all */ 2583 rbrp->rbr_use_bcopy = B_FALSE; 2584 rbrp->rbr_threshold_hi = rbrp->rbb_max; 2585 break; 2586 2587 case HXGE_RX_COPY_1: 2588 case HXGE_RX_COPY_2: 2589 case HXGE_RX_COPY_3: 2590 case HXGE_RX_COPY_4: 2591 case HXGE_RX_COPY_5: 2592 case HXGE_RX_COPY_6: 2593 case HXGE_RX_COPY_7: 2594 rbrp->rbr_threshold_hi = 2595 rbrp->rbb_max * (hxge_rx_threshold_hi) / 2596 HXGE_RX_BCOPY_SCALE; 2597 break; 2598 2599 case HXGE_RX_COPY_ALL: 2600 rbrp->rbr_threshold_hi = 0; 2601 break; 2602 } 2603 2604 switch (hxge_rx_threshold_lo) { 2605 default: 2606 case HXGE_RX_COPY_NONE: 2607 /* Do not do bcopy at all */ 2608 if (rbrp->rbr_use_bcopy) { 2609 rbrp->rbr_use_bcopy = B_FALSE; 2610 } 2611 rbrp->rbr_threshold_lo = rbrp->rbb_max; 2612 break; 2613 2614 case HXGE_RX_COPY_1: 2615 case HXGE_RX_COPY_2: 2616 case HXGE_RX_COPY_3: 2617 case HXGE_RX_COPY_4: 2618 case HXGE_RX_COPY_5: 2619 case HXGE_RX_COPY_6: 2620 case HXGE_RX_COPY_7: 2621 rbrp->rbr_threshold_lo = 2622 rbrp->rbb_max * (hxge_rx_threshold_lo) / 2623 HXGE_RX_BCOPY_SCALE; 2624 break; 2625 2626 case HXGE_RX_COPY_ALL: 2627 rbrp->rbr_threshold_lo = 0; 2628 break; 2629 } 2630 2631 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2632 "hxge_map_rxdma_channel_cfg_ring: channel %d rbb_max %d " 2633 "rbrp->rbr_bufsize_type %d rbb_threshold_hi %d " 2634 "rbb_threshold_lo %d", 2635 dma_channel, rbrp->rbb_max, rbrp->rbr_bufsize_type, 2636 rbrp->rbr_threshold_hi, rbrp->rbr_threshold_lo)); 2637 2638 /* Map in the receive completion ring */ 2639 rcrp = (p_rx_rcr_ring_t)KMEM_ZALLOC(sizeof (rx_rcr_ring_t), KM_SLEEP); 2640 rcrp->rdc = dma_channel; 2641 rcrp->hxgep = hxgep; 2642 2643 hxge_port_rcr_size = hxgep->hxge_port_rcr_size; 2644 rcrp->comp_size = hxge_port_rcr_size; 2645 rcrp->comp_wrap_mask = hxge_port_rcr_size - 1; 2646 2647 rcrp->max_receive_pkts = hxge_max_rx_pkts; 2648 2649 cntl_dmap = *dma_rcr_cntl_p; 2650 2651 dmap = (p_hxge_dma_common_t)&rcrp->rcr_desc; 2652 hxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size, 2653 sizeof (rcr_entry_t)); 2654 rcrp->comp_rd_index = 0; 2655 rcrp->comp_wt_index = 0; 2656 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 2657 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 2658 #if defined(__i386) 2659 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 2660 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 2661 #else 2662 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 2663 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 2664 #endif 2665 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 2666 (hxge_port_rcr_size - 1); 2667 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 2668 (hxge_port_rcr_size - 1); 2669 2670 rcrp->rcr_tail_begin = DMA_COMMON_IOADDR(rcrp->rcr_desc); 2671 rcrp->rcr_tail_begin = (rcrp->rcr_tail_begin & 0x7ffffULL) >> 3; 2672 2673 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2674 "==> hxge_map_rxdma_channel_cfg_ring: channel %d " 2675 "rbr_vaddrp $%p rcr_desc_rd_head_p $%p " 2676 "rcr_desc_rd_head_pp $%p rcr_desc_rd_last_p $%p " 2677 "rcr_desc_rd_last_pp $%p ", 2678 dma_channel, rbr_vaddrp, rcrp->rcr_desc_rd_head_p, 2679 rcrp->rcr_desc_rd_head_pp, rcrp->rcr_desc_last_p, 2680 rcrp->rcr_desc_last_pp)); 2681 2682 /* 2683 * Zero out buffer block ring descriptors. 2684 */ 2685 bzero((caddr_t)dmap->kaddrp, dmap->alength); 2686 rcrp->intr_timeout = hxgep->intr_timeout; 2687 rcrp->intr_threshold = hxgep->intr_threshold; 2688 rcrp->full_hdr_flag = B_FALSE; 2689 rcrp->sw_priv_hdr_len = 0; 2690 2691 cfga_p = &(rcrp->rcr_cfga); 2692 cfgb_p = &(rcrp->rcr_cfgb); 2693 cfga_p->value = 0; 2694 cfgb_p->value = 0; 2695 rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress; 2696 2697 cfga_p->value = (rcrp->rcr_addr & 2698 (RCRCFIG_A_STADDR_MASK | RCRCFIG_A_STADDR_BASE_MASK)); 2699 2700 cfga_p->value |= ((uint64_t)rcrp->comp_size << RCRCFIG_A_LEN_SHIF); 2701 2702 /* 2703 * Timeout should be set based on the system clock divider. The 2704 * following timeout value of 1 assumes that the granularity (1000) is 2705 * 3 microseconds running at 300MHz. 2706 */ 2707 cfgb_p->bits.pthres = rcrp->intr_threshold; 2708 cfgb_p->bits.timeout = rcrp->intr_timeout; 2709 cfgb_p->bits.entout = 1; 2710 2711 /* Map in the mailbox */ 2712 cntl_dmap = *dma_mbox_cntl_p; 2713 mboxp = (p_rx_mbox_t)KMEM_ZALLOC(sizeof (rx_mbox_t), KM_SLEEP); 2714 dmap = (p_hxge_dma_common_t)&mboxp->rx_mbox; 2715 hxge_setup_dma_common(dmap, cntl_dmap, 1, sizeof (rxdma_mailbox_t)); 2716 cfig1_p = (rdc_rx_cfg1_t *)&mboxp->rx_cfg1; 2717 cfig2_p = (rdc_rx_cfg2_t *)&mboxp->rx_cfg2; 2718 cfig1_p->value = cfig2_p->value = 0; 2719 2720 mboxp->mbox_addr = dmap->dma_cookie.dmac_laddress; 2721 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2722 "==> hxge_map_rxdma_channel_cfg_ring: " 2723 "channel %d cfg1 0x%016llx cfig2 0x%016llx cookie 0x%016llx", 2724 dma_channel, cfig1_p->value, cfig2_p->value, 2725 mboxp->mbox_addr)); 2726 2727 dmaaddrp = (uint32_t)((dmap->dma_cookie.dmac_laddress >> 32) & 0xfff); 2728 cfig1_p->bits.mbaddr_h = dmaaddrp; 2729 2730 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 0xffffffff); 2731 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 2732 RXDMA_CFIG2_MBADDR_L_MASK); 2733 2734 cfig2_p->bits.mbaddr_l = (dmaaddrp >> RXDMA_CFIG2_MBADDR_L_SHIFT); 2735 2736 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2737 "==> hxge_map_rxdma_channel_cfg_ring: channel %d damaddrp $%p " 2738 "cfg1 0x%016llx cfig2 0x%016llx", 2739 dma_channel, dmaaddrp, cfig1_p->value, cfig2_p->value)); 2740 2741 cfig2_p->bits.full_hdr = rcrp->full_hdr_flag; 2742 cfig2_p->bits.offset = rcrp->sw_priv_hdr_len; 2743 2744 rbrp->rx_rcr_p = rcrp; 2745 rcrp->rx_rbr_p = rbrp; 2746 *rcr_p = rcrp; 2747 *rx_mbox_p = mboxp; 2748 2749 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2750 "<== hxge_map_rxdma_channel_cfg_ring status 0x%08x", status)); 2751 return (status); 2752 } 2753 2754 /*ARGSUSED*/ 2755 static void 2756 hxge_unmap_rxdma_channel_cfg_ring(p_hxge_t hxgep, 2757 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 2758 { 2759 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2760 "==> hxge_unmap_rxdma_channel_cfg_ring: channel %d", rcr_p->rdc)); 2761 2762 KMEM_FREE(rcr_p, sizeof (rx_rcr_ring_t)); 2763 KMEM_FREE(rx_mbox_p, sizeof (rx_mbox_t)); 2764 2765 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2766 "<== hxge_unmap_rxdma_channel_cfg_ring")); 2767 } 2768 2769 static hxge_status_t 2770 hxge_map_rxdma_channel_buf_ring(p_hxge_t hxgep, uint16_t channel, 2771 p_hxge_dma_common_t *dma_buf_p, 2772 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks) 2773 { 2774 p_rx_rbr_ring_t rbrp; 2775 p_hxge_dma_common_t dma_bufp, tmp_bufp; 2776 p_rx_msg_t *rx_msg_ring; 2777 p_rx_msg_t rx_msg_p; 2778 p_mblk_t mblk_p; 2779 2780 rxring_info_t *ring_info; 2781 hxge_status_t status = HXGE_OK; 2782 int i, j, index; 2783 uint32_t size, bsize, nblocks, nmsgs; 2784 2785 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2786 "==> hxge_map_rxdma_channel_buf_ring: channel %d", channel)); 2787 2788 dma_bufp = tmp_bufp = *dma_buf_p; 2789 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2790 " hxge_map_rxdma_channel_buf_ring: channel %d to map %d " 2791 "chunks bufp 0x%016llx", channel, num_chunks, dma_bufp)); 2792 2793 nmsgs = 0; 2794 for (i = 0; i < num_chunks; i++, tmp_bufp++) { 2795 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2796 "==> hxge_map_rxdma_channel_buf_ring: channel %d " 2797 "bufp 0x%016llx nblocks %d nmsgs %d", 2798 channel, tmp_bufp, tmp_bufp->nblocks, nmsgs)); 2799 nmsgs += tmp_bufp->nblocks; 2800 } 2801 if (!nmsgs) { 2802 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2803 "<== hxge_map_rxdma_channel_buf_ring: channel %d " 2804 "no msg blocks", channel)); 2805 status = HXGE_ERROR; 2806 goto hxge_map_rxdma_channel_buf_ring_exit; 2807 } 2808 rbrp = (p_rx_rbr_ring_t)KMEM_ZALLOC(sizeof (rx_rbr_ring_t), KM_SLEEP); 2809 2810 size = nmsgs * sizeof (p_rx_msg_t); 2811 rx_msg_ring = KMEM_ZALLOC(size, KM_SLEEP); 2812 ring_info = (rxring_info_t *)KMEM_ZALLOC(sizeof (rxring_info_t), 2813 KM_SLEEP); 2814 2815 MUTEX_INIT(&rbrp->lock, NULL, MUTEX_DRIVER, 2816 (void *) hxgep->interrupt_cookie); 2817 MUTEX_INIT(&rbrp->post_lock, NULL, MUTEX_DRIVER, 2818 (void *) hxgep->interrupt_cookie); 2819 2820 rbrp->rdc = channel; 2821 rbrp->num_blocks = num_chunks; 2822 rbrp->tnblocks = nmsgs; 2823 rbrp->rbb_max = nmsgs; 2824 rbrp->rbr_max_size = nmsgs; 2825 rbrp->rbr_wrap_mask = (rbrp->rbb_max - 1); 2826 2827 /* 2828 * Buffer sizes suggested by NIU architect. 256, 512 and 2K. 2829 */ 2830 2831 rbrp->pkt_buf_size0 = RBR_BUFSZ0_256B; 2832 rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_256_BYTES; 2833 rbrp->hpi_pkt_buf_size0 = SIZE_256B; 2834 2835 rbrp->pkt_buf_size1 = RBR_BUFSZ1_1K; 2836 rbrp->pkt_buf_size1_bytes = RBR_BUFSZ1_1K_BYTES; 2837 rbrp->hpi_pkt_buf_size1 = SIZE_1KB; 2838 2839 rbrp->block_size = hxgep->rx_default_block_size; 2840 2841 if (!hxgep->param_arr[param_accept_jumbo].value) { 2842 rbrp->pkt_buf_size2 = RBR_BUFSZ2_2K; 2843 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_2K_BYTES; 2844 rbrp->hpi_pkt_buf_size2 = SIZE_2KB; 2845 } else { 2846 rbrp->hpi_pkt_buf_size2 = SIZE_4KB; 2847 rbrp->pkt_buf_size2 = RBR_BUFSZ2_4K; 2848 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_4K_BYTES; 2849 } 2850 2851 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2852 "==> hxge_map_rxdma_channel_buf_ring: channel %d " 2853 "actual rbr max %d rbb_max %d nmsgs %d " 2854 "rbrp->block_size %d default_block_size %d " 2855 "(config hxge_rbr_size %d hxge_rbr_spare_size %d)", 2856 channel, rbrp->rbr_max_size, rbrp->rbb_max, nmsgs, 2857 rbrp->block_size, hxgep->rx_default_block_size, 2858 hxge_rbr_size, hxge_rbr_spare_size)); 2859 2860 /* 2861 * Map in buffers from the buffer pool. 2862 * Note that num_blocks is the num_chunks. For Sparc, there is likely 2863 * only one chunk. For x86, there will be many chunks. 2864 * Loop over chunks. 2865 */ 2866 index = 0; 2867 for (i = 0; i < rbrp->num_blocks; i++, dma_bufp++) { 2868 bsize = dma_bufp->block_size; 2869 nblocks = dma_bufp->nblocks; 2870 #if defined(__i386) 2871 ring_info->buffer[i].dvma_addr = (uint32_t)dma_bufp->ioaddr_pp; 2872 #else 2873 ring_info->buffer[i].dvma_addr = (uint64_t)dma_bufp->ioaddr_pp; 2874 #endif 2875 ring_info->buffer[i].buf_index = i; 2876 ring_info->buffer[i].buf_size = dma_bufp->alength; 2877 ring_info->buffer[i].start_index = index; 2878 #if defined(__i386) 2879 ring_info->buffer[i].kaddr = (uint32_t)dma_bufp->kaddrp; 2880 #else 2881 ring_info->buffer[i].kaddr = (uint64_t)dma_bufp->kaddrp; 2882 #endif 2883 2884 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2885 " hxge_map_rxdma_channel_buf_ring: map channel %d " 2886 "chunk %d nblocks %d chunk_size %x block_size 0x%x " 2887 "dma_bufp $%p dvma_addr $%p", channel, i, 2888 dma_bufp->nblocks, 2889 ring_info->buffer[i].buf_size, bsize, dma_bufp, 2890 ring_info->buffer[i].dvma_addr)); 2891 2892 /* loop over blocks within a chunk */ 2893 for (j = 0; j < nblocks; j++) { 2894 if ((rx_msg_p = hxge_allocb(bsize, BPRI_LO, 2895 dma_bufp)) == NULL) { 2896 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2897 "allocb failed (index %d i %d j %d)", 2898 index, i, j)); 2899 goto hxge_map_rxdma_channel_buf_ring_fail1; 2900 } 2901 rx_msg_ring[index] = rx_msg_p; 2902 rx_msg_p->block_index = index; 2903 rx_msg_p->shifted_addr = (uint32_t) 2904 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 2905 RBR_BKADDR_SHIFT)); 2906 /* 2907 * Too much output 2908 * HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2909 * "index %d j %d rx_msg_p $%p mblk %p", 2910 * index, j, rx_msg_p, rx_msg_p->rx_mblk_p)); 2911 */ 2912 mblk_p = rx_msg_p->rx_mblk_p; 2913 mblk_p->b_wptr = mblk_p->b_rptr + bsize; 2914 2915 rbrp->rbr_ref_cnt++; 2916 index++; 2917 rx_msg_p->buf_dma.dma_channel = channel; 2918 } 2919 } 2920 if (i < rbrp->num_blocks) { 2921 goto hxge_map_rxdma_channel_buf_ring_fail1; 2922 } 2923 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2924 "hxge_map_rxdma_channel_buf_ring: done buf init " 2925 "channel %d msg block entries %d", channel, index)); 2926 ring_info->block_size_mask = bsize - 1; 2927 rbrp->rx_msg_ring = rx_msg_ring; 2928 rbrp->dma_bufp = dma_buf_p; 2929 rbrp->ring_info = ring_info; 2930 2931 status = hxge_rxbuf_index_info_init(hxgep, rbrp); 2932 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, " hxge_map_rxdma_channel_buf_ring: " 2933 "channel %d done buf info init", channel)); 2934 2935 /* 2936 * Finally, permit hxge_freeb() to call hxge_post_page(). 2937 */ 2938 rbrp->rbr_state = RBR_POSTING; 2939 2940 *rbr_p = rbrp; 2941 2942 goto hxge_map_rxdma_channel_buf_ring_exit; 2943 2944 hxge_map_rxdma_channel_buf_ring_fail1: 2945 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2946 " hxge_map_rxdma_channel_buf_ring: failed channel (0x%x)", 2947 channel, status)); 2948 2949 index--; 2950 for (; index >= 0; index--) { 2951 rx_msg_p = rx_msg_ring[index]; 2952 if (rx_msg_p != NULL) { 2953 freeb(rx_msg_p->rx_mblk_p); 2954 rx_msg_ring[index] = NULL; 2955 } 2956 } 2957 2958 hxge_map_rxdma_channel_buf_ring_fail: 2959 MUTEX_DESTROY(&rbrp->post_lock); 2960 MUTEX_DESTROY(&rbrp->lock); 2961 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 2962 KMEM_FREE(rx_msg_ring, size); 2963 KMEM_FREE(rbrp, sizeof (rx_rbr_ring_t)); 2964 2965 status = HXGE_ERROR; 2966 2967 hxge_map_rxdma_channel_buf_ring_exit: 2968 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2969 "<== hxge_map_rxdma_channel_buf_ring status 0x%08x", status)); 2970 2971 return (status); 2972 } 2973 2974 /*ARGSUSED*/ 2975 static void 2976 hxge_unmap_rxdma_channel_buf_ring(p_hxge_t hxgep, 2977 p_rx_rbr_ring_t rbr_p) 2978 { 2979 p_rx_msg_t *rx_msg_ring; 2980 p_rx_msg_t rx_msg_p; 2981 rxring_info_t *ring_info; 2982 int i; 2983 uint32_t size; 2984 2985 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2986 "==> hxge_unmap_rxdma_channel_buf_ring")); 2987 if (rbr_p == NULL) { 2988 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2989 "<== hxge_unmap_rxdma_channel_buf_ring: NULL rbrp")); 2990 return; 2991 } 2992 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2993 "==> hxge_unmap_rxdma_channel_buf_ring: channel %d", rbr_p->rdc)); 2994 2995 rx_msg_ring = rbr_p->rx_msg_ring; 2996 ring_info = rbr_p->ring_info; 2997 2998 if (rx_msg_ring == NULL || ring_info == NULL) { 2999 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3000 "<== hxge_unmap_rxdma_channel_buf_ring: " 3001 "rx_msg_ring $%p ring_info $%p", rx_msg_p, ring_info)); 3002 return; 3003 } 3004 3005 size = rbr_p->tnblocks * sizeof (p_rx_msg_t); 3006 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3007 " hxge_unmap_rxdma_channel_buf_ring: channel %d chunks %d " 3008 "tnblocks %d (max %d) size ptrs %d ", rbr_p->rdc, rbr_p->num_blocks, 3009 rbr_p->tnblocks, rbr_p->rbr_max_size, size)); 3010 3011 for (i = 0; i < rbr_p->tnblocks; i++) { 3012 rx_msg_p = rx_msg_ring[i]; 3013 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3014 " hxge_unmap_rxdma_channel_buf_ring: " 3015 "rx_msg_p $%p", rx_msg_p)); 3016 if (rx_msg_p != NULL) { 3017 freeb(rx_msg_p->rx_mblk_p); 3018 rx_msg_ring[i] = NULL; 3019 } 3020 } 3021 3022 /* 3023 * We no longer may use the mutex <post_lock>. By setting 3024 * <rbr_state> to anything but POSTING, we prevent 3025 * hxge_post_page() from accessing a dead mutex. 3026 */ 3027 rbr_p->rbr_state = RBR_UNMAPPING; 3028 MUTEX_DESTROY(&rbr_p->post_lock); 3029 3030 MUTEX_DESTROY(&rbr_p->lock); 3031 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3032 KMEM_FREE(rx_msg_ring, size); 3033 3034 if (rbr_p->rbr_ref_cnt == 0) { 3035 /* This is the normal state of affairs. */ 3036 KMEM_FREE(rbr_p, sizeof (*rbr_p)); 3037 } else { 3038 /* 3039 * Some of our buffers are still being used. 3040 * Therefore, tell hxge_freeb() this ring is 3041 * unmapped, so it may free <rbr_p> for us. 3042 */ 3043 rbr_p->rbr_state = RBR_UNMAPPED; 3044 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3045 "unmap_rxdma_buf_ring: %d %s outstanding.", 3046 rbr_p->rbr_ref_cnt, 3047 rbr_p->rbr_ref_cnt == 1 ? "msg" : "msgs")); 3048 } 3049 3050 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3051 "<== hxge_unmap_rxdma_channel_buf_ring")); 3052 } 3053 3054 static hxge_status_t 3055 hxge_rxdma_hw_start_common(p_hxge_t hxgep) 3056 { 3057 hxge_status_t status = HXGE_OK; 3058 3059 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start_common")); 3060 3061 /* 3062 * Load the sharable parameters by writing to the function zero control 3063 * registers. These FZC registers should be initialized only once for 3064 * the entire chip. 3065 */ 3066 (void) hxge_init_fzc_rx_common(hxgep); 3067 3068 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start_common")); 3069 3070 return (status); 3071 } 3072 3073 static hxge_status_t 3074 hxge_rxdma_hw_start(p_hxge_t hxgep) 3075 { 3076 int i, ndmas; 3077 uint16_t channel; 3078 p_rx_rbr_rings_t rx_rbr_rings; 3079 p_rx_rbr_ring_t *rbr_rings; 3080 p_rx_rcr_rings_t rx_rcr_rings; 3081 p_rx_rcr_ring_t *rcr_rings; 3082 p_rx_mbox_areas_t rx_mbox_areas_p; 3083 p_rx_mbox_t *rx_mbox_p; 3084 hxge_status_t status = HXGE_OK; 3085 3086 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start")); 3087 3088 rx_rbr_rings = hxgep->rx_rbr_rings; 3089 rx_rcr_rings = hxgep->rx_rcr_rings; 3090 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3091 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3092 "<== hxge_rxdma_hw_start: NULL ring pointers")); 3093 return (HXGE_ERROR); 3094 } 3095 3096 ndmas = rx_rbr_rings->ndmas; 3097 if (ndmas == 0) { 3098 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3099 "<== hxge_rxdma_hw_start: no dma channel allocated")); 3100 return (HXGE_ERROR); 3101 } 3102 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3103 "==> hxge_rxdma_hw_start (ndmas %d)", ndmas)); 3104 3105 /* 3106 * Scrub the RDC Rx DMA Prefetch Buffer Command. 3107 */ 3108 for (i = 0; i < 128; i++) { 3109 HXGE_REG_WR64(hxgep->hpi_handle, RDC_PREF_CMD, i); 3110 } 3111 3112 /* 3113 * Scrub Rx DMA Shadow Tail Command. 3114 */ 3115 for (i = 0; i < 64; i++) { 3116 HXGE_REG_WR64(hxgep->hpi_handle, RDC_SHADOW_CMD, i); 3117 } 3118 3119 /* 3120 * Scrub Rx DMA Control Fifo Command. 3121 */ 3122 for (i = 0; i < 512; i++) { 3123 HXGE_REG_WR64(hxgep->hpi_handle, RDC_CTRL_FIFO_CMD, i); 3124 } 3125 3126 /* 3127 * Scrub Rx DMA Data Fifo Command. 3128 */ 3129 for (i = 0; i < 1536; i++) { 3130 HXGE_REG_WR64(hxgep->hpi_handle, RDC_DATA_FIFO_CMD, i); 3131 } 3132 3133 /* 3134 * Reset the FIFO Error Stat. 3135 */ 3136 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_STAT, 0xFF); 3137 3138 /* Set the error mask to receive interrupts */ 3139 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_INT_MASK, 0x0); 3140 3141 rbr_rings = rx_rbr_rings->rbr_rings; 3142 rcr_rings = rx_rcr_rings->rcr_rings; 3143 rx_mbox_areas_p = hxgep->rx_mbox_areas_p; 3144 if (rx_mbox_areas_p) { 3145 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 3146 } 3147 3148 for (i = 0; i < ndmas; i++) { 3149 channel = rbr_rings[i]->rdc; 3150 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3151 "==> hxge_rxdma_hw_start (ndmas %d) channel %d", 3152 ndmas, channel)); 3153 status = hxge_rxdma_start_channel(hxgep, channel, 3154 (p_rx_rbr_ring_t)rbr_rings[i], 3155 (p_rx_rcr_ring_t)rcr_rings[i], 3156 (p_rx_mbox_t)rx_mbox_p[i], rbr_rings[i]->rbb_max); 3157 if (status != HXGE_OK) { 3158 goto hxge_rxdma_hw_start_fail1; 3159 } 3160 } 3161 3162 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start: " 3163 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3164 rx_rbr_rings, rx_rcr_rings)); 3165 goto hxge_rxdma_hw_start_exit; 3166 3167 hxge_rxdma_hw_start_fail1: 3168 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3169 "==> hxge_rxdma_hw_start: disable " 3170 "(status 0x%x channel %d i %d)", status, channel, i)); 3171 for (; i >= 0; i--) { 3172 channel = rbr_rings[i]->rdc; 3173 (void) hxge_rxdma_stop_channel(hxgep, channel); 3174 } 3175 3176 hxge_rxdma_hw_start_exit: 3177 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3178 "==> hxge_rxdma_hw_start: (status 0x%x)", status)); 3179 return (status); 3180 } 3181 3182 static void 3183 hxge_rxdma_hw_stop(p_hxge_t hxgep) 3184 { 3185 int i, ndmas; 3186 uint16_t channel; 3187 p_rx_rbr_rings_t rx_rbr_rings; 3188 p_rx_rbr_ring_t *rbr_rings; 3189 p_rx_rcr_rings_t rx_rcr_rings; 3190 3191 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_stop")); 3192 3193 rx_rbr_rings = hxgep->rx_rbr_rings; 3194 rx_rcr_rings = hxgep->rx_rcr_rings; 3195 3196 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3197 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3198 "<== hxge_rxdma_hw_stop: NULL ring pointers")); 3199 return; 3200 } 3201 3202 ndmas = rx_rbr_rings->ndmas; 3203 if (!ndmas) { 3204 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3205 "<== hxge_rxdma_hw_stop: no dma channel allocated")); 3206 return; 3207 } 3208 3209 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3210 "==> hxge_rxdma_hw_stop (ndmas %d)", ndmas)); 3211 3212 rbr_rings = rx_rbr_rings->rbr_rings; 3213 for (i = 0; i < ndmas; i++) { 3214 channel = rbr_rings[i]->rdc; 3215 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3216 "==> hxge_rxdma_hw_stop (ndmas %d) channel %d", 3217 ndmas, channel)); 3218 (void) hxge_rxdma_stop_channel(hxgep, channel); 3219 } 3220 3221 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_stop: " 3222 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3223 rx_rbr_rings, rx_rcr_rings)); 3224 3225 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_rxdma_hw_stop")); 3226 } 3227 3228 static hxge_status_t 3229 hxge_rxdma_start_channel(p_hxge_t hxgep, uint16_t channel, 3230 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p, 3231 int n_init_kick) 3232 { 3233 hpi_handle_t handle; 3234 hpi_status_t rs = HPI_SUCCESS; 3235 rdc_stat_t cs; 3236 rdc_int_mask_t ent_mask; 3237 hxge_status_t status = HXGE_OK; 3238 3239 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel")); 3240 3241 handle = HXGE_DEV_HPI_HANDLE(hxgep); 3242 3243 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "hxge_rxdma_start_channel: " 3244 "hpi handle addr $%p acc $%p", 3245 hxgep->hpi_handle.regp, hxgep->hpi_handle.regh)); 3246 3247 /* Reset RXDMA channel */ 3248 rs = hpi_rxdma_cfg_rdc_reset(handle, channel); 3249 if (rs != HPI_SUCCESS) { 3250 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3251 "==> hxge_rxdma_start_channel: " 3252 "reset rxdma failed (0x%08x channel %d)", 3253 status, channel)); 3254 return (HXGE_ERROR | rs); 3255 } 3256 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3257 "==> hxge_rxdma_start_channel: reset done: channel %d", channel)); 3258 3259 /* 3260 * Initialize the RXDMA channel specific FZC control configurations. 3261 * These FZC registers are pertaining to each RX channel (logical 3262 * pages). 3263 */ 3264 status = hxge_init_fzc_rxdma_channel(hxgep, 3265 channel, rbr_p, rcr_p, mbox_p); 3266 if (status != HXGE_OK) { 3267 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3268 "==> hxge_rxdma_start_channel: " 3269 "init fzc rxdma failed (0x%08x channel %d)", 3270 status, channel)); 3271 return (status); 3272 } 3273 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3274 "==> hxge_rxdma_start_channel: fzc done")); 3275 3276 /* 3277 * Zero out the shadow and prefetch ram. 3278 */ 3279 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3280 "==> hxge_rxdma_start_channel: ram done")); 3281 3282 /* Set up the interrupt event masks. */ 3283 ent_mask.value = 0; 3284 rs = hpi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 3285 if (rs != HPI_SUCCESS) { 3286 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3287 "==> hxge_rxdma_start_channel: " 3288 "init rxdma event masks failed (0x%08x channel %d)", 3289 status, channel)); 3290 return (HXGE_ERROR | rs); 3291 } 3292 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3293 "event done: channel %d (mask 0x%016llx)", 3294 channel, ent_mask.value)); 3295 3296 /* 3297 * Load RXDMA descriptors, buffers, mailbox, initialise the receive DMA 3298 * channels and enable each DMA channel. 3299 */ 3300 status = hxge_enable_rxdma_channel(hxgep, 3301 channel, rbr_p, rcr_p, mbox_p, n_init_kick); 3302 if (status != HXGE_OK) { 3303 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3304 " hxge_rxdma_start_channel: " 3305 " init enable rxdma failed (0x%08x channel %d)", 3306 status, channel)); 3307 return (status); 3308 } 3309 3310 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3311 "control done - channel %d cs 0x%016llx", channel, cs.value)); 3312 3313 /* 3314 * Initialize the receive DMA control and status register 3315 * Note that rdc_stat HAS to be set after RBR and RCR rings are set 3316 */ 3317 cs.value = 0; 3318 cs.bits.mex = 1; 3319 cs.bits.rcr_thres = 1; 3320 cs.bits.rcr_to = 1; 3321 cs.bits.rbr_empty = 1; 3322 status = hxge_init_rxdma_channel_cntl_stat(hxgep, channel, &cs); 3323 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3324 "channel %d rx_dma_cntl_stat 0x%0016llx", channel, cs.value)); 3325 if (status != HXGE_OK) { 3326 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3327 "==> hxge_rxdma_start_channel: " 3328 "init rxdma control register failed (0x%08x channel %d", 3329 status, channel)); 3330 return (status); 3331 } 3332 3333 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3334 "control done - channel %d cs 0x%016llx", channel, cs.value)); 3335 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3336 "==> hxge_rxdma_start_channel: enable done")); 3337 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_rxdma_start_channel")); 3338 3339 return (HXGE_OK); 3340 } 3341 3342 static hxge_status_t 3343 hxge_rxdma_stop_channel(p_hxge_t hxgep, uint16_t channel) 3344 { 3345 hpi_handle_t handle; 3346 hpi_status_t rs = HPI_SUCCESS; 3347 rdc_stat_t cs; 3348 rdc_int_mask_t ent_mask; 3349 hxge_status_t status = HXGE_OK; 3350 3351 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_channel")); 3352 3353 handle = HXGE_DEV_HPI_HANDLE(hxgep); 3354 3355 HXGE_DEBUG_MSG((hxgep, RX_CTL, "hxge_rxdma_stop_channel: " 3356 "hpi handle addr $%p acc $%p", 3357 hxgep->hpi_handle.regp, hxgep->hpi_handle.regh)); 3358 3359 /* Reset RXDMA channel */ 3360 rs = hpi_rxdma_cfg_rdc_reset(handle, channel); 3361 if (rs != HPI_SUCCESS) { 3362 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3363 " hxge_rxdma_stop_channel: " 3364 " reset rxdma failed (0x%08x channel %d)", 3365 rs, channel)); 3366 return (HXGE_ERROR | rs); 3367 } 3368 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3369 "==> hxge_rxdma_stop_channel: reset done")); 3370 3371 /* Set up the interrupt event masks. */ 3372 ent_mask.value = RDC_INT_MASK_ALL; 3373 rs = hpi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 3374 if (rs != HPI_SUCCESS) { 3375 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3376 "==> hxge_rxdma_stop_channel: " 3377 "set rxdma event masks failed (0x%08x channel %d)", 3378 rs, channel)); 3379 return (HXGE_ERROR | rs); 3380 } 3381 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3382 "==> hxge_rxdma_stop_channel: event done")); 3383 3384 /* Initialize the receive DMA control and status register */ 3385 cs.value = 0; 3386 status = hxge_init_rxdma_channel_cntl_stat(hxgep, channel, &cs); 3387 3388 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_channel: control " 3389 " to default (all 0s) 0x%08x", cs.value)); 3390 3391 if (status != HXGE_OK) { 3392 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3393 " hxge_rxdma_stop_channel: init rxdma" 3394 " control register failed (0x%08x channel %d", 3395 status, channel)); 3396 return (status); 3397 } 3398 3399 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3400 "==> hxge_rxdma_stop_channel: control done")); 3401 3402 /* disable dma channel */ 3403 status = hxge_disable_rxdma_channel(hxgep, channel); 3404 3405 if (status != HXGE_OK) { 3406 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3407 " hxge_rxdma_stop_channel: " 3408 " init enable rxdma failed (0x%08x channel %d)", 3409 status, channel)); 3410 return (status); 3411 } 3412 3413 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3414 "==> hxge_rxdma_stop_channel: disable done")); 3415 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop_channel")); 3416 3417 return (HXGE_OK); 3418 } 3419 3420 hxge_status_t 3421 hxge_rxdma_handle_sys_errors(p_hxge_t hxgep) 3422 { 3423 hpi_handle_t handle; 3424 p_hxge_rdc_sys_stats_t statsp; 3425 rdc_fifo_err_stat_t stat; 3426 hxge_status_t status = HXGE_OK; 3427 3428 handle = hxgep->hpi_handle; 3429 statsp = (p_hxge_rdc_sys_stats_t)&hxgep->statsp->rdc_sys_stats; 3430 3431 /* Clear the int_dbg register in case it is an injected err */ 3432 HXGE_REG_WR64(handle, RDC_FIFO_ERR_INT_DBG, 0x0); 3433 3434 /* Get the error status and clear the register */ 3435 HXGE_REG_RD64(handle, RDC_FIFO_ERR_STAT, &stat.value); 3436 HXGE_REG_WR64(handle, RDC_FIFO_ERR_STAT, stat.value); 3437 3438 if (stat.bits.rx_ctrl_fifo_sec) { 3439 statsp->ctrl_fifo_sec++; 3440 if (statsp->ctrl_fifo_sec == 1) 3441 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3442 "==> hxge_rxdma_handle_sys_errors: " 3443 "rx_ctrl_fifo_sec")); 3444 } 3445 3446 if (stat.bits.rx_ctrl_fifo_ded) { 3447 /* Global fatal error encountered */ 3448 statsp->ctrl_fifo_ded++; 3449 HXGE_FM_REPORT_ERROR(hxgep, NULL, 3450 HXGE_FM_EREPORT_RDMC_CTRL_FIFO_DED); 3451 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3452 "==> hxge_rxdma_handle_sys_errors: " 3453 "fatal error: rx_ctrl_fifo_ded error")); 3454 } 3455 3456 if (stat.bits.rx_data_fifo_sec) { 3457 statsp->data_fifo_sec++; 3458 if (statsp->data_fifo_sec == 1) 3459 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3460 "==> hxge_rxdma_handle_sys_errors: " 3461 "rx_data_fifo_sec")); 3462 } 3463 3464 if (stat.bits.rx_data_fifo_ded) { 3465 /* Global fatal error encountered */ 3466 statsp->data_fifo_ded++; 3467 HXGE_FM_REPORT_ERROR(hxgep, NULL, 3468 HXGE_FM_EREPORT_RDMC_DATA_FIFO_DED); 3469 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3470 "==> hxge_rxdma_handle_sys_errors: " 3471 "fatal error: rx_data_fifo_ded error")); 3472 } 3473 3474 if (stat.bits.rx_ctrl_fifo_ded || stat.bits.rx_data_fifo_ded) { 3475 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3476 " hxge_rxdma_handle_sys_errors: fatal error\n")); 3477 status = hxge_rx_port_fatal_err_recover(hxgep); 3478 if (status == HXGE_OK) { 3479 FM_SERVICE_RESTORED(hxgep); 3480 } 3481 } 3482 3483 return (HXGE_OK); 3484 } 3485 3486 static hxge_status_t 3487 hxge_rxdma_fatal_err_recover(p_hxge_t hxgep, uint16_t channel) 3488 { 3489 hpi_handle_t handle; 3490 hpi_status_t rs = HPI_SUCCESS; 3491 hxge_status_t status = HXGE_OK; 3492 p_rx_rbr_ring_t rbrp; 3493 p_rx_rcr_ring_t rcrp; 3494 p_rx_mbox_t mboxp; 3495 rdc_int_mask_t ent_mask; 3496 p_hxge_dma_common_t dmap; 3497 int ring_idx; 3498 p_rx_msg_t rx_msg_p; 3499 int i; 3500 uint32_t hxge_port_rcr_size; 3501 uint64_t tmp; 3502 int n_init_kick = 0; 3503 3504 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_fatal_err_recover")); 3505 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3506 "Recovering from RxDMAChannel#%d error...", channel)); 3507 3508 /* 3509 * Stop the dma channel waits for the stop done. If the stop done bit 3510 * is not set, then create an error. 3511 */ 3512 3513 handle = HXGE_DEV_HPI_HANDLE(hxgep); 3514 3515 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Rx DMA stop...")); 3516 3517 ring_idx = hxge_rxdma_get_ring_index(hxgep, channel); 3518 rbrp = (p_rx_rbr_ring_t)hxgep->rx_rbr_rings->rbr_rings[ring_idx]; 3519 rcrp = (p_rx_rcr_ring_t)hxgep->rx_rcr_rings->rcr_rings[ring_idx]; 3520 3521 MUTEX_ENTER(&rcrp->lock); 3522 MUTEX_ENTER(&rbrp->lock); 3523 MUTEX_ENTER(&rbrp->post_lock); 3524 3525 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxDMA channel...")); 3526 3527 rs = hpi_rxdma_cfg_rdc_disable(handle, channel); 3528 if (rs != HPI_SUCCESS) { 3529 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3530 "hxge_disable_rxdma_channel:failed")); 3531 goto fail; 3532 } 3533 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxDMA interrupt...")); 3534 3535 /* Disable interrupt */ 3536 ent_mask.value = RDC_INT_MASK_ALL; 3537 rs = hpi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 3538 if (rs != HPI_SUCCESS) { 3539 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3540 "Set rxdma event masks failed (channel %d)", channel)); 3541 } 3542 HXGE_DEBUG_MSG((hxgep, RX_CTL, "RxDMA channel reset...")); 3543 3544 /* Reset RXDMA channel */ 3545 rs = hpi_rxdma_cfg_rdc_reset(handle, channel); 3546 if (rs != HPI_SUCCESS) { 3547 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3548 "Reset rxdma failed (channel %d)", channel)); 3549 goto fail; 3550 } 3551 hxge_port_rcr_size = hxgep->hxge_port_rcr_size; 3552 mboxp = (p_rx_mbox_t)hxgep->rx_mbox_areas_p->rxmbox_areas[ring_idx]; 3553 3554 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 3555 rbrp->rbr_rd_index = 0; 3556 3557 rcrp->comp_rd_index = 0; 3558 rcrp->comp_wt_index = 0; 3559 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 3560 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 3561 #if defined(__i386) 3562 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3563 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3564 #else 3565 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3566 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3567 #endif 3568 3569 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 3570 (hxge_port_rcr_size - 1); 3571 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 3572 (hxge_port_rcr_size - 1); 3573 3574 rcrp->rcr_tail_begin = DMA_COMMON_IOADDR(rcrp->rcr_desc); 3575 rcrp->rcr_tail_begin = (rcrp->rcr_tail_begin & 0x7ffffULL) >> 3; 3576 3577 dmap = (p_hxge_dma_common_t)&rcrp->rcr_desc; 3578 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3579 3580 HXGE_DEBUG_MSG((hxgep, RX_CTL, "rbr entries = %d\n", 3581 rbrp->rbr_max_size)); 3582 3583 /* Count the number of buffers owned by the hardware at this moment */ 3584 for (i = 0; i < rbrp->rbr_max_size; i++) { 3585 rx_msg_p = rbrp->rx_msg_ring[i]; 3586 if (rx_msg_p->ref_cnt == 1) { 3587 n_init_kick++; 3588 } 3589 } 3590 3591 HXGE_DEBUG_MSG((hxgep, RX_CTL, "RxDMA channel re-start...")); 3592 3593 /* 3594 * This is error recover! Some buffers are owned by the hardware and 3595 * the rest are owned by the apps. We should only kick in those 3596 * owned by the hardware initially. The apps will post theirs 3597 * eventually. 3598 */ 3599 status = hxge_rxdma_start_channel(hxgep, channel, rbrp, rcrp, mboxp, 3600 n_init_kick); 3601 if (status != HXGE_OK) { 3602 goto fail; 3603 } 3604 3605 /* 3606 * The DMA channel may disable itself automatically. 3607 * The following is a work-around. 3608 */ 3609 HXGE_REG_RD64(handle, RDC_RX_CFG1, &tmp); 3610 rs = hpi_rxdma_cfg_rdc_enable(handle, channel); 3611 if (rs != HPI_SUCCESS) { 3612 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3613 "hpi_rxdma_cfg_rdc_enable (channel %d)", channel)); 3614 } 3615 3616 MUTEX_EXIT(&rbrp->post_lock); 3617 MUTEX_EXIT(&rbrp->lock); 3618 MUTEX_EXIT(&rcrp->lock); 3619 3620 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3621 "Recovery Successful, RxDMAChannel#%d Restored", channel)); 3622 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_fatal_err_recover")); 3623 3624 return (HXGE_OK); 3625 3626 fail: 3627 MUTEX_EXIT(&rbrp->post_lock); 3628 MUTEX_EXIT(&rbrp->lock); 3629 MUTEX_EXIT(&rcrp->lock); 3630 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovery failed")); 3631 3632 return (HXGE_ERROR | rs); 3633 } 3634 3635 static hxge_status_t 3636 hxge_rx_port_fatal_err_recover(p_hxge_t hxgep) 3637 { 3638 hxge_status_t status = HXGE_OK; 3639 p_hxge_dma_common_t *dma_buf_p; 3640 uint16_t channel; 3641 int ndmas; 3642 int i; 3643 block_reset_t reset_reg; 3644 3645 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_port_fatal_err_recover")); 3646 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovering from RDC error ...")); 3647 3648 /* Reset RDC block from PEU for this fatal error */ 3649 reset_reg.value = 0; 3650 reset_reg.bits.rdc_rst = 1; 3651 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value); 3652 3653 /* Disable RxMAC */ 3654 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxMAC...\n")); 3655 if (hxge_rx_vmac_disable(hxgep) != HXGE_OK) 3656 goto fail; 3657 3658 HXGE_DELAY(1000); 3659 3660 /* Restore any common settings after PEU reset */ 3661 if (hxge_rxdma_hw_start_common(hxgep) != HXGE_OK) 3662 goto fail; 3663 3664 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Stop all RxDMA channels...")); 3665 3666 ndmas = hxgep->rx_buf_pool_p->ndmas; 3667 dma_buf_p = hxgep->rx_buf_pool_p->dma_buf_pool_p; 3668 3669 for (i = 0; i < ndmas; i++) { 3670 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 3671 if (hxge_rxdma_fatal_err_recover(hxgep, channel) != HXGE_OK) { 3672 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3673 "Could not recover channel %d", channel)); 3674 } 3675 } 3676 3677 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Reset RxMAC...")); 3678 3679 /* Reset RxMAC */ 3680 if (hxge_rx_vmac_reset(hxgep) != HXGE_OK) { 3681 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3682 "hxge_rx_port_fatal_err_recover: Failed to reset RxMAC")); 3683 goto fail; 3684 } 3685 3686 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Re-initialize RxMAC...")); 3687 3688 /* Re-Initialize RxMAC */ 3689 if ((status = hxge_rx_vmac_init(hxgep)) != HXGE_OK) { 3690 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3691 "hxge_rx_port_fatal_err_recover: Failed to reset RxMAC")); 3692 goto fail; 3693 } 3694 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Re-enable RxMAC...")); 3695 3696 /* Re-enable RxMAC */ 3697 if ((status = hxge_rx_vmac_enable(hxgep)) != HXGE_OK) { 3698 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3699 "hxge_rx_port_fatal_err_recover: Failed to enable RxMAC")); 3700 goto fail; 3701 } 3702 3703 /* Reset the error mask since PEU reset cleared it */ 3704 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_INT_MASK, 0x0); 3705 3706 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3707 "Recovery Successful, RxPort Restored")); 3708 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rx_port_fatal_err_recover")); 3709 3710 return (HXGE_OK); 3711 fail: 3712 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovery failed")); 3713 return (status); 3714 } 3715