1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_HXGE_HXGE_H 28 #define _SYS_HXGE_HXGE_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <hxge_vmac.h> 35 #include <hxge_pfc.h> 36 #include <hxge_classify.h> 37 38 /* 39 * HXGE diagnostics IOCTLS. 40 */ 41 #define HXGE_IOC ((((('N' << 8) + 'X') << 8) + 'G') << 8) 42 43 #define HXGE_GET_TX_RING_SZ (HXGE_IOC|1) 44 #define HXGE_GET_TX_DESC (HXGE_IOC|2) 45 #define HXGE_GLOBAL_RESET (HXGE_IOC|3) 46 #define HXGE_TX_SIDE_RESET (HXGE_IOC|4) 47 #define HXGE_RX_SIDE_RESET (HXGE_IOC|5) 48 #define HXGE_RESET_MAC (HXGE_IOC|6) 49 #define HXGE_RTRACE (HXGE_IOC|7) 50 #define HXGE_GET_TCAM (HXGE_IOC|8) 51 #define HXGE_PUT_TCAM (HXGE_IOC|9) 52 53 #define HXGE_OK 0 54 #define HXGE_ERROR 0x40000000 55 #define HXGE_DDI_FAILED 0x20000000 56 57 /* 58 * Definitions for module_info. 59 */ 60 #define HXGE_DRIVER_NAME "hxge" /* module name */ 61 #define HXGE_CHECK_TIMER (5000) 62 63 typedef enum { 64 param_instance, 65 66 param_accept_jumbo, 67 param_rxdma_rbr_size, 68 param_rxdma_rcr_size, 69 param_rxdma_intr_time, 70 param_rxdma_intr_pkts, 71 param_vlan_ids, 72 param_implicit_vlan_id, 73 param_tcam_enable, 74 75 param_hash_init_value, 76 param_class_cfg_ether_usr1, 77 param_class_cfg_ether_usr2, 78 param_class_opt_ipv4_tcp, 79 param_class_opt_ipv4_udp, 80 param_class_opt_ipv4_ah, 81 param_class_opt_ipv4_sctp, 82 param_class_opt_ipv6_tcp, 83 param_class_opt_ipv6_udp, 84 param_class_opt_ipv6_ah, 85 param_class_opt_ipv6_sctp, 86 param_hxge_debug_flag, 87 param_hpi_debug_flag, 88 param_dump_ptrs, 89 param_end 90 } hxge_param_index_t; 91 92 93 #define HXGE_PARAM_READ 0x00000001ULL 94 #define HXGE_PARAM_WRITE 0x00000002ULL 95 #define HXGE_PARAM_SHARED 0x00000004ULL 96 #define HXGE_PARAM_PRIV 0x00000008ULL 97 #define HXGE_PARAM_RW HXGE_PARAM_READ | HXGE_PARAM_WRITE 98 #define HXGE_PARAM_RWS HXGE_PARAM_RW | HXGE_PARAM_SHARED 99 #define HXGE_PARAM_RWP HXGE_PARAM_RW | HXGE_PARAM_PRIV 100 101 #define HXGE_PARAM_RXDMA 0x00000010ULL 102 #define HXGE_PARAM_TXDMA 0x00000020ULL 103 #define HXGE_PARAM_MAC 0x00000040ULL 104 105 #define HXGE_PARAM_CMPLX 0x00010000ULL 106 #define HXGE_PARAM_NDD_WR_OK 0x00020000ULL 107 #define HXGE_PARAM_INIT_ONLY 0x00040000ULL 108 #define HXGE_PARAM_INIT_CONFIG 0x00080000ULL 109 110 #define HXGE_PARAM_READ_PROP 0x00100000ULL 111 #define HXGE_PARAM_PROP_ARR32 0x00200000ULL 112 #define HXGE_PARAM_PROP_ARR64 0x00400000ULL 113 #define HXGE_PARAM_PROP_STR 0x00800000ULL 114 115 #define HXGE_PARAM_DONT_SHOW 0x80000000ULL 116 117 #define HXGE_PARAM_ARRAY_CNT_MASK 0x0000ffff00000000ULL 118 #define HXGE_PARAM_ARRAY_CNT_SHIFT 32ULL 119 #define HXGE_PARAM_ARRAY_ALLOC_MASK 0xffff000000000000ULL 120 #define HXGE_PARAM_ARRAY_ALLOC_SHIFT 48ULL 121 122 typedef struct _hxge_param_t { 123 int (*getf)(); 124 int (*setf)(); /* null for read only */ 125 uint64_t type; /* R/W/ Common/Port/ .... */ 126 uint64_t minimum; 127 uint64_t maximum; 128 uint64_t value; /* for array params, pointer to value array */ 129 uint64_t old_value; /* for array params, pointer to old_value array */ 130 char *fcode_name; 131 char *name; 132 } hxge_param_t, *p_hxge_param_t; 133 134 135 typedef enum { 136 hxge_lb_normal, 137 hxge_lb_mac10g 138 } hxge_lb_t; 139 140 enum hxge_mac_state { 141 HXGE_MAC_STOPPED = 0, 142 HXGE_MAC_STARTED 143 }; 144 145 typedef struct _filter_t { 146 uint32_t all_phys_cnt; 147 uint32_t all_multicast_cnt; 148 uint32_t all_sap_cnt; 149 } filter_t, *p_filter_t; 150 151 typedef struct _hxge_port_stats_t { 152 hxge_lb_t lb_mode; 153 uint32_t poll_mode; 154 } hxge_port_stats_t, *p_hxge_port_stats_t; 155 156 157 typedef struct _hxge_peu_sys_stats { 158 uint32_t spc_acc_err; 159 uint32_t tdc_pioacc_err; 160 uint32_t rdc_pioacc_err; 161 uint32_t pfc_pioacc_err; 162 uint32_t vmac_pioacc_err; 163 uint32_t cpl_hdrq_parerr; 164 uint32_t cpl_dataq_parerr; 165 uint32_t retryram_xdlh_parerr; 166 uint32_t retrysotram_xdlh_parerr; 167 uint32_t p_hdrq_parerr; 168 uint32_t p_dataq_parerr; 169 uint32_t np_hdrq_parerr; 170 uint32_t np_dataq_parerr; 171 uint32_t eic_msix_parerr; 172 uint32_t hcr_parerr; 173 } hxge_peu_sys_stats_t, *p_hxge_peu_sys_stats_t; 174 175 176 typedef struct _hxge_stats_t { 177 /* 178 * Overall structure size 179 */ 180 size_t stats_size; 181 182 kstat_t *ksp; 183 kstat_t *rdc_ksp[HXGE_MAX_RDCS]; 184 kstat_t *tdc_ksp[HXGE_MAX_TDCS]; 185 kstat_t *rdc_sys_ksp; 186 kstat_t *tdc_sys_ksp; 187 kstat_t *pfc_ksp; 188 kstat_t *vmac_ksp; 189 kstat_t *port_ksp; 190 kstat_t *mmac_ksp; 191 kstat_t *peu_sys_ksp; 192 193 hxge_mac_stats_t mac_stats; 194 hxge_vmac_stats_t vmac_stats; /* VMAC Statistics */ 195 196 hxge_rx_ring_stats_t rdc_stats[HXGE_MAX_RDCS]; /* per rdc stats */ 197 hxge_rdc_sys_stats_t rdc_sys_stats; /* RDC system stats */ 198 199 hxge_tx_ring_stats_t tdc_stats[HXGE_MAX_TDCS]; /* per tdc stats */ 200 hxge_tdc_sys_stats_t tdc_sys_stats; /* TDC system stats */ 201 202 hxge_pfc_stats_t pfc_stats; /* pfc stats */ 203 hxge_port_stats_t port_stats; /* port stats */ 204 205 hxge_peu_sys_stats_t peu_sys_stats; /* PEU system stats */ 206 } hxge_stats_t, *p_hxge_stats_t; 207 208 typedef struct _hxge_intr_t { 209 boolean_t intr_registered; /* interrupts are registered */ 210 boolean_t intr_enabled; /* interrupts are enabled */ 211 boolean_t niu_msi_enable; /* debug or configurable? */ 212 uint8_t nldevs; /* # of logical devices */ 213 int intr_types; /* interrupt types supported */ 214 int intr_type; /* interrupt type to add */ 215 int msi_intx_cnt; /* # msi/intx ints returned */ 216 int intr_added; /* # ints actually needed */ 217 int intr_cap; /* interrupt capabilities */ 218 size_t intr_size; /* size of array to allocate */ 219 ddi_intr_handle_t *htable; /* For array of interrupts */ 220 /* Add interrupt number for each interrupt vector */ 221 int pri; 222 } hxge_intr_t, *p_hxge_intr_t; 223 224 typedef struct _hxge_ldgv_t { 225 uint8_t ndma_ldvs; 226 uint8_t nldvs; 227 uint8_t start_ldg; 228 uint8_t maxldgs; 229 uint8_t maxldvs; 230 uint8_t ldg_intrs; 231 uint32_t tmres; 232 p_hxge_ldg_t ldgp; 233 p_hxge_ldv_t ldvp; 234 p_hxge_ldv_t ldvp_syserr; 235 } hxge_ldgv_t, *p_hxge_ldgv_t; 236 237 typedef struct _hxge_timeout { 238 timeout_id_t id; 239 clock_t ticks; 240 kmutex_t lock; 241 uint32_t link_status; 242 boolean_t report_link_status; 243 } hxge_timeout; 244 245 typedef struct _hxge_addr { 246 boolean_t set; 247 boolean_t primary; 248 uint8_t addr[ETHERADDRL]; 249 } hxge_addr_t; 250 251 #define HXGE_MAX_MAC_ADDRS 16 252 253 typedef struct _hxge_mmac { 254 uint8_t total; 255 uint8_t available; 256 hxge_addr_t addrs[HXGE_MAX_MAC_ADDRS]; 257 } hxge_mmac_t; 258 259 /* 260 * Ring Group Strucuture. 261 */ 262 #define HXGE_MAX_RX_GROUPS 1 263 264 typedef struct _hxge_rx_ring_group_t { 265 mac_ring_type_t type; 266 mac_group_handle_t ghandle; 267 struct _hxge_t *hxgep; 268 int index; 269 boolean_t started; 270 } hxge_ring_group_t; 271 272 /* 273 * Ring Handle 274 */ 275 typedef struct _hxge_ring_handle_t { 276 struct _hxge_t *hxgep; 277 int index; /* port-wise */ 278 mac_ring_handle_t ring_handle; 279 boolean_t started; 280 } hxge_ring_handle_t; 281 282 typedef hxge_ring_handle_t *p_hxge_ring_handle_t; 283 284 /* 285 * Hydra Device instance state information. 286 * Each instance is dynamically allocated on first attach. 287 */ 288 struct _hxge_t { 289 dev_info_t *dip; /* device instance */ 290 dev_info_t *p_dip; /* Parent's device instance */ 291 int instance; /* instance number */ 292 uint32_t drv_state; /* driver state bit flags */ 293 uint64_t hxge_debug_level; /* driver state bit flags */ 294 kmutex_t genlock[1]; 295 enum hxge_mac_state hxge_mac_state; 296 297 p_dev_regs_t dev_regs; 298 hpi_handle_t hpi_handle; 299 hpi_handle_t hpi_pci_handle; 300 hpi_handle_t hpi_reg_handle; 301 hpi_handle_t hpi_msi_handle; 302 303 hxge_vmac_t vmac; 304 hxge_classify_t classifier; 305 306 mac_handle_t mach; /* mac module handle */ 307 308 p_hxge_stats_t statsp; 309 uint32_t param_count; 310 p_hxge_param_t param_arr; 311 hxge_hw_list_t *hxge_hw_p; /* pointer to per Hydra */ 312 uint8_t nrdc; 313 uint8_t rdc[HXGE_MAX_RDCS]; 314 boolean_t rdc_first_intr[HXGE_MAX_RDCS]; 315 uint8_t ntdc; 316 uint8_t tdc[HXGE_MAX_TDCS]; 317 318 hxge_ring_handle_t tx_ring_handles[HXGE_MAX_TDCS]; 319 hxge_ring_handle_t rx_ring_handles[HXGE_MAX_RDCS]; 320 hxge_ring_group_t rx_groups[HXGE_MAX_RX_GROUPS]; 321 322 hxge_intr_t hxge_intr_type; 323 hxge_dma_pt_cfg_t pt_config; 324 hxge_class_pt_cfg_t class_config; 325 326 /* Logical device and group data structures. */ 327 p_hxge_ldgv_t ldgvp; 328 329 caddr_t param_list; /* Parameter list */ 330 331 ether_addr_st factaddr; /* factory mac address */ 332 ether_addr_st ouraddr; /* individual address */ 333 kmutex_t ouraddr_lock; /* lock to protect to uradd */ 334 hxge_mmac_t mmac; 335 336 ddi_iblock_cookie_t interrupt_cookie; 337 338 /* 339 * Blocks of memory may be pre-allocated by the 340 * partition manager or the driver. They may include 341 * blocks for configuration and buffers. The idea is 342 * to preallocate big blocks of contiguous areas in 343 * system memory (i.e. with IOMMU). These blocks then 344 * will be broken up to a fixed number of blocks with 345 * each block having the same block size (4K, 8K, 16K or 346 * 32K) in the case of buffer blocks. For systems that 347 * do not support DVMA, more than one big block will be 348 * allocated. 349 */ 350 uint32_t rx_default_block_size; 351 hxge_rx_block_size_t rx_bksize_code; 352 353 p_hxge_dma_pool_t rx_buf_pool_p; 354 p_hxge_dma_pool_t rx_rbr_cntl_pool_p; 355 p_hxge_dma_pool_t rx_rcr_cntl_pool_p; 356 p_hxge_dma_pool_t rx_mbox_cntl_pool_p; 357 358 p_hxge_dma_pool_t tx_buf_pool_p; 359 p_hxge_dma_pool_t tx_cntl_pool_p; 360 361 /* Receive buffer block ring and completion ring. */ 362 p_rx_rbr_rings_t rx_rbr_rings; 363 p_rx_rcr_rings_t rx_rcr_rings; 364 p_rx_mbox_areas_t rx_mbox_areas_p; 365 366 uint32_t start_rdc; 367 uint32_t max_rdcs; 368 369 /* Transmit descriptors rings */ 370 p_tx_rings_t tx_rings; 371 p_tx_mbox_areas_t tx_mbox_areas_p; 372 373 uint32_t start_tdc; 374 uint32_t max_tdcs; 375 uint32_t tdc_mask; 376 377 ddi_dma_handle_t dmasparehandle; 378 379 ulong_t sys_page_sz; 380 ulong_t sys_page_mask; 381 int suspended; 382 383 filter_t filter; /* Current instance filter */ 384 p_hash_filter_t hash_filter; /* Multicast hash filter. */ 385 krwlock_t filter_lock; /* Lock to protect filters. */ 386 387 ulong_t sys_burst_sz; 388 timeout_id_t hxge_timerid; 389 uint8_t msg_min; 390 391 uint16_t intr_timeout; 392 uint16_t intr_threshold; 393 394 rtrace_t rtrace; 395 int fm_capabilities; /* FMA capabilities */ 396 397 uint32_t hxge_port_rbr_size; 398 uint32_t hxge_port_rcr_size; 399 uint32_t hxge_port_tx_ring_size; 400 401 kmutex_t vmac_lock; 402 kmutex_t pio_lock; 403 hxge_timeout timeout; 404 405 int msix_count; 406 int msix_index; 407 uint32_t msix_table[32][3]; 408 uint32_t msix_table_check[1][3]; 409 }; 410 411 /* 412 * Driver state flags. 413 */ 414 #define STATE_REGS_MAPPED 0x000000001 /* device registers mapped */ 415 #define STATE_KSTATS_SETUP 0x000000002 /* kstats allocated */ 416 #define STATE_NODE_CREATED 0x000000004 /* device node created */ 417 #define STATE_HW_CONFIG_CREATED 0x000000008 /* hardware properties */ 418 #define STATE_HW_INITIALIZED 0x000000010 /* hardware initialized */ 419 420 typedef struct _hxge_port_kstat_t { 421 /* 422 * Transciever state informations. 423 */ 424 kstat_named_t cap_autoneg; 425 kstat_named_t cap_10gfdx; 426 427 /* 428 * Link partner capabilities. 429 */ 430 kstat_named_t lp_cap_autoneg; 431 kstat_named_t lp_cap_10gfdx; 432 433 /* 434 * Shared link setup. 435 */ 436 kstat_named_t link_speed; 437 kstat_named_t link_duplex; 438 kstat_named_t link_up; 439 440 /* 441 * Lets the user know the MTU currently in use by 442 * the physical MAC port. 443 */ 444 kstat_named_t lb_mode; 445 446 kstat_named_t tx_max_pend; 447 kstat_named_t rx_jumbo_pkts; 448 449 /* 450 * Misc MAC statistics. 451 */ 452 kstat_named_t ifspeed; 453 kstat_named_t promisc; 454 } hxge_port_kstat_t, *p_hxge_port_kstat_t; 455 456 typedef struct _hxge_rdc_kstat { 457 /* 458 * Receive DMA channel statistics. 459 * This structure needs to be consistent with hxge_rdc_stat_index_t 460 * in hxge_kstat.c 461 */ 462 kstat_named_t ipackets; 463 kstat_named_t rbytes; 464 kstat_named_t errors; 465 kstat_named_t jumbo_pkts; 466 467 kstat_named_t rcr_unknown_err; 468 kstat_named_t rcr_sha_par_err; 469 kstat_named_t rbr_pre_par_err; 470 kstat_named_t rbr_pre_emty; 471 472 kstat_named_t rcr_shadow_full; 473 kstat_named_t rbr_tmout; 474 kstat_named_t peu_resp_err; 475 476 kstat_named_t ctrl_fifo_ecc_err; 477 kstat_named_t data_fifo_ecc_err; 478 479 kstat_named_t rcrfull; 480 kstat_named_t rbr_empty; 481 kstat_named_t rbr_empty_fail; 482 kstat_named_t rbr_empty_restore; 483 kstat_named_t rbrfull; 484 kstat_named_t rcr_invalids; /* Account for invalid RCR entries. */ 485 486 kstat_named_t rcr_to; 487 kstat_named_t rcr_thresh; 488 kstat_named_t pkt_drop; 489 } hxge_rdc_kstat_t, *p_hxge_rdc_kstat_t; 490 491 typedef struct _hxge_rdc_sys_kstat { 492 /* 493 * Receive DMA system statistics. 494 * This structure needs to be consistent with hxge_rdc_sys_stat_idx_t 495 * in hxge_kstat.c 496 */ 497 kstat_named_t ctrl_fifo_sec; 498 kstat_named_t ctrl_fifo_ded; 499 kstat_named_t data_fifo_sec; 500 kstat_named_t data_fifo_ded; 501 } hxge_rdc_sys_kstat_t, *p_hxge_rdc_sys_kstat_t; 502 503 typedef struct _hxge_tdc_kstat { 504 /* 505 * Transmit DMA channel statistics. 506 * This structure needs to be consistent with hxge_tdc_stats_index_t 507 * in hxge_kstat.c 508 */ 509 kstat_named_t opackets; 510 kstat_named_t obytes; 511 kstat_named_t obytes_with_pad; 512 kstat_named_t oerrors; 513 kstat_named_t tx_inits; 514 kstat_named_t tx_no_buf; 515 516 kstat_named_t peu_resp_err; 517 kstat_named_t pkt_size_err; 518 kstat_named_t tx_rng_oflow; 519 kstat_named_t pkt_size_hdr_err; 520 kstat_named_t runt_pkt_drop_err; 521 kstat_named_t pref_par_err; 522 kstat_named_t tdr_pref_cpl_to; 523 kstat_named_t pkt_cpl_to; 524 kstat_named_t invalid_sop; 525 kstat_named_t unexpected_sop; 526 527 kstat_named_t count_hdr_size_err; 528 kstat_named_t count_runt; 529 kstat_named_t count_abort; 530 531 kstat_named_t tx_starts; 532 kstat_named_t tx_no_desc; 533 kstat_named_t tx_dma_bind_fail; 534 kstat_named_t tx_hdr_pkts; 535 kstat_named_t tx_ddi_pkts; 536 kstat_named_t tx_jumbo_pkts; 537 kstat_named_t tx_max_pend; 538 kstat_named_t tx_marks; 539 } hxge_tdc_kstat_t, *p_hxge_tdc_kstat_t; 540 541 typedef struct _hxge_tdc_sys_kstat { 542 /* 543 * Transmit DMA system statistics. 544 * This structure needs to be consistent with hxge_tdc_sys_stat_idx_t 545 * in hxge_kstat.c 546 */ 547 kstat_named_t reord_tbl_par_err; 548 kstat_named_t reord_buf_ded_err; 549 kstat_named_t reord_buf_sec_err; 550 } hxge_tdc_sys_kstat_t, *p_hxge_tdc_sys_kstat_t; 551 552 typedef struct _hxge_vmac_kstat { 553 /* 554 * VMAC statistics. 555 * This structure needs to be consistent with hxge_vmac_stat_index_t 556 * in hxge_kstat.c 557 */ 558 kstat_named_t tx_frame_cnt; 559 kstat_named_t tx_byte_cnt; 560 561 kstat_named_t rx_frame_cnt; 562 kstat_named_t rx_byte_cnt; 563 kstat_named_t rx_drop_frame_cnt; 564 kstat_named_t rx_drop_byte_cnt; 565 kstat_named_t rx_crc_cnt; 566 kstat_named_t rx_pause_cnt; 567 kstat_named_t rx_bcast_fr_cnt; 568 kstat_named_t rx_mcast_fr_cnt; 569 } hxge_vmac_kstat_t, *p_hxge_vmac_kstat_t; 570 571 typedef struct _hxge_pfc_kstat { 572 /* 573 * This structure needs to be consistent with hxge_pfc_stat_index_t 574 * in hxge_kstat.c 575 */ 576 kstat_named_t pfc_pkt_drop; 577 kstat_named_t pfc_tcam_parity_err; 578 kstat_named_t pfc_vlan_parity_err; 579 kstat_named_t pfc_bad_cs_count; 580 kstat_named_t pfc_drop_count; 581 kstat_named_t pfc_tcp_ctrl_drop; 582 kstat_named_t pfc_l2_addr_drop; 583 kstat_named_t pfc_class_code_drop; 584 kstat_named_t pfc_tcam_drop; 585 kstat_named_t pfc_vlan_drop; 586 } hxge_pfc_kstat_t, *p_hxge_pfc_kstat_t; 587 588 typedef struct _hxge_mmac_kstat { 589 /* 590 * This structure needs to be consistent with hxge_mmac_stat_index_t 591 * in hxge_kstat.c 592 */ 593 kstat_named_t mmac_max_addr_cnt; 594 kstat_named_t mmac_avail_addr_cnt; 595 kstat_named_t mmac_addr1; 596 kstat_named_t mmac_addr2; 597 kstat_named_t mmac_addr3; 598 kstat_named_t mmac_addr4; 599 kstat_named_t mmac_addr5; 600 kstat_named_t mmac_addr6; 601 kstat_named_t mmac_addr7; 602 kstat_named_t mmac_addr8; 603 kstat_named_t mmac_addr9; 604 kstat_named_t mmac_addr10; 605 kstat_named_t mmac_addr11; 606 kstat_named_t mmac_addr12; 607 kstat_named_t mmac_addr13; 608 kstat_named_t mmac_addr14; 609 kstat_named_t mmac_addr15; 610 kstat_named_t mmac_addr16; 611 } hxge_mmac_kstat_t, *p_hxge_mmac_kstat_t; 612 613 typedef struct _hxge_peu_sys_kstat { 614 /* 615 * This structure needs to be consistent with hxge_peu_sys_stat_idx_t 616 * in hxge_kstat.c 617 */ 618 kstat_named_t spc_acc_err; 619 kstat_named_t tdc_pioacc_err; 620 kstat_named_t rdc_pioacc_err; 621 kstat_named_t pfc_pioacc_err; 622 kstat_named_t vmac_pioacc_err; 623 kstat_named_t cpl_hdrq_parerr; 624 kstat_named_t cpl_dataq_parerr; 625 kstat_named_t retryram_xdlh_parerr; 626 kstat_named_t retrysotram_xdlh_parerr; 627 kstat_named_t p_hdrq_parerr; 628 kstat_named_t p_dataq_parerr; 629 kstat_named_t np_hdrq_parerr; 630 kstat_named_t np_dataq_parerr; 631 kstat_named_t eic_msix_parerr; 632 kstat_named_t hcr_parerr; 633 } hxge_peu_sys_kstat_t, *p_hxge_peu_sys_kstat_t; 634 635 /* 636 * Prototype definitions. 637 */ 638 hxge_status_t hxge_init(p_hxge_t); 639 void hxge_uninit(p_hxge_t); 640 641 typedef void (*fptrv_t)(); 642 timeout_id_t hxge_start_timer(p_hxge_t hxgep, fptrv_t func, int msec); 643 void hxge_stop_timer(p_hxge_t hxgep, timeout_id_t timerid); 644 645 #ifdef __cplusplus 646 } 647 #endif 648 649 #endif /* _SYS_HXGE_HXGE_H */ 650