1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <hpi_vmac.h> 29 30 #define HXGE_VMAC_RX_STAT_CLEAR 0x1ffULL 31 #define HXGE_VMAC_TX_STAT_CLEAR 0x7ULL 32 #define HXGE_VMAC_RX_MASK_OVERFLOW 0x1fe 33 #define HXGE_VMAC_RX_MASK_FRAME 0x1 34 35 hpi_status_t 36 hpi_tx_vmac_reset(hpi_handle_t handle) 37 { 38 vmac_rst_t reset; 39 40 HXGE_REG_RD64(handle, VMAC_RST, &(reset.value)); 41 42 reset.bits.tx_reset = 1; 43 44 HXGE_REG_WR64(handle, VMAC_RST, reset.value); 45 46 return (HPI_SUCCESS); 47 } 48 49 hpi_status_t 50 hpi_rx_vmac_reset(hpi_handle_t handle) 51 { 52 vmac_rst_t reset; 53 54 HXGE_REG_RD64(handle, VMAC_RST, &(reset.value)); 55 56 reset.bits.rx_reset = 1; 57 58 HXGE_REG_WR64(handle, VMAC_RST, reset.value); 59 60 return (HPI_SUCCESS); 61 } 62 63 64 hpi_status_t 65 hpi_vmac_tx_config(hpi_handle_t handle, config_op_t op, uint64_t config, 66 uint16_t max_frame_length) 67 { 68 vmac_tx_cfg_t cfg; 69 70 if (config == 0) { 71 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 72 " hpi_vmac_tx_config Invalid Input: config <0x%x>", 73 config)); 74 return (HPI_FAILURE); 75 } 76 77 HXGE_REG_RD64(handle, VMAC_TX_CFG, &cfg.value); 78 79 switch (op) { 80 case ENABLE: 81 if (config & CFG_VMAC_TX_EN) 82 cfg.bits.tx_en = 1; 83 if (config & CFG_VMAC_TX_CRC_INSERT) 84 cfg.bits.crc_insert = 1; 85 if (config & CFG_VMAC_TX_PAD) 86 cfg.bits.tx_pad = 1; 87 if (max_frame_length) 88 cfg.bits.tx_max_frame_length = max_frame_length; 89 break; 90 case DISABLE: 91 if (config & CFG_VMAC_TX_EN) 92 cfg.bits.tx_en = 0; 93 if (config & CFG_VMAC_TX_CRC_INSERT) 94 cfg.bits.crc_insert = 0; 95 if (config & CFG_VMAC_TX_PAD) 96 cfg.bits.tx_pad = 0; 97 break; 98 case INIT: 99 if (config & CFG_VMAC_TX_EN) 100 cfg.bits.tx_en = 1; 101 else 102 cfg.bits.tx_en = 0; 103 104 if (config & CFG_VMAC_TX_CRC_INSERT) 105 cfg.bits.crc_insert = 1; 106 else 107 cfg.bits.crc_insert = 0; 108 109 if (config & CFG_VMAC_TX_PAD) 110 cfg.bits.tx_pad = 1; 111 else 112 cfg.bits.tx_pad = 0; 113 114 if (max_frame_length) 115 cfg.bits.tx_max_frame_length = max_frame_length; 116 117 break; 118 default: 119 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 120 " hpi_vmac_tx_config Invalid Input: op <0x%x>", op)); 121 return (HPI_FAILURE); 122 } 123 124 HXGE_REG_WR64(handle, VMAC_TX_CFG, cfg.value); 125 126 return (HPI_SUCCESS); 127 } 128 129 hpi_status_t 130 hpi_vmac_rx_config(hpi_handle_t handle, config_op_t op, uint64_t config, 131 uint16_t max_frame_length) 132 { 133 vmac_rx_cfg_t cfg; 134 135 if (config == 0) { 136 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 137 " hpi_vmac_rx_config Invalid Input: config <0x%x>", 138 config)); 139 return (HPI_FAILURE); 140 } 141 142 HXGE_REG_RD64(handle, VMAC_RX_CFG, &cfg.value); 143 144 switch (op) { 145 case ENABLE: 146 if (config & CFG_VMAC_RX_EN) 147 cfg.bits.rx_en = 1; 148 if (config & CFG_VMAC_RX_CRC_CHECK_DISABLE) 149 cfg.bits.crc_check_disable = 1; 150 if (config & CFG_VMAC_RX_STRIP_CRC) 151 cfg.bits.strip_crc = 1; 152 if (config & CFG_VMAC_RX_PASS_FLOW_CTRL_FR) 153 cfg.bits.pass_flow_ctrl_fr = 1; 154 if (config & CFG_VMAC_RX_PROMIXCUOUS_GROUP) 155 cfg.bits.promiscuous_group = 1; 156 if (config & CFG_VMAC_RX_PROMISCUOUS_MODE) 157 cfg.bits.promiscuous_mode = 1; 158 if (config & CFG_VMAC_RX_LOOP_BACK) 159 cfg.bits.loopback = 1; 160 break; 161 case DISABLE: 162 if (config & CFG_VMAC_RX_EN) 163 cfg.bits.rx_en = 0; 164 if (config & CFG_VMAC_RX_CRC_CHECK_DISABLE) 165 cfg.bits.crc_check_disable = 0; 166 if (config & CFG_VMAC_RX_STRIP_CRC) 167 cfg.bits.strip_crc = 0; 168 if (config & CFG_VMAC_RX_PASS_FLOW_CTRL_FR) 169 cfg.bits.pass_flow_ctrl_fr = 0; 170 if (config & CFG_VMAC_RX_PROMIXCUOUS_GROUP) 171 cfg.bits.promiscuous_group = 0; 172 if (config & CFG_VMAC_RX_PROMISCUOUS_MODE) 173 cfg.bits.promiscuous_mode = 0; 174 if (config & CFG_VMAC_RX_LOOP_BACK) 175 cfg.bits.loopback = 0; 176 break; 177 case INIT: 178 if (config & CFG_VMAC_RX_EN) 179 cfg.bits.rx_en = 1; 180 else 181 cfg.bits.rx_en = 0; 182 if (config & CFG_VMAC_RX_CRC_CHECK_DISABLE) 183 cfg.bits.crc_check_disable = 1; 184 else 185 cfg.bits.crc_check_disable = 0; 186 if (config & CFG_VMAC_RX_STRIP_CRC) 187 cfg.bits.strip_crc = 1; 188 else 189 cfg.bits.strip_crc = 0; 190 if (config & CFG_VMAC_RX_PASS_FLOW_CTRL_FR) 191 cfg.bits.pass_flow_ctrl_fr = 1; 192 else 193 cfg.bits.pass_flow_ctrl_fr = 0; 194 if (config & CFG_VMAC_RX_PROMIXCUOUS_GROUP) 195 cfg.bits.promiscuous_group = 1; 196 else 197 cfg.bits.promiscuous_group = 0; 198 if (config & CFG_VMAC_RX_PROMISCUOUS_MODE) 199 cfg.bits.promiscuous_mode = 1; 200 else 201 cfg.bits.promiscuous_mode = 0; 202 if (config & CFG_VMAC_RX_LOOP_BACK) 203 cfg.bits.loopback = 1; 204 else 205 cfg.bits.loopback = 0; 206 207 break; 208 default: 209 HPI_ERROR_MSG((handle.function, HPI_ERR_CTL, 210 " hpi_vmac_rx_config Invalid Input: op <0x%x>", op)); 211 return (HPI_FAILURE); 212 } 213 214 if (max_frame_length) 215 cfg.bits.rx_max_frame_length = max_frame_length; 216 217 HXGE_REG_WR64(handle, VMAC_RX_CFG, cfg.value); 218 219 return (HPI_SUCCESS); 220 } 221 222 hpi_status_t 223 hpi_vmac_clear_rx_int_stat(hpi_handle_t handle) 224 { 225 uint64_t offset; 226 227 offset = VMAC_RX_STAT; 228 REG_PIO_WRITE64(handle, offset, HXGE_VMAC_RX_STAT_CLEAR); 229 230 return (HPI_SUCCESS); 231 } 232 233 hpi_status_t 234 hpi_vmac_clear_tx_int_stat(hpi_handle_t handle) 235 { 236 uint64_t offset; 237 238 offset = VMAC_TX_STAT; 239 REG_PIO_WRITE64(handle, offset, HXGE_VMAC_TX_STAT_CLEAR); 240 241 return (HPI_SUCCESS); 242 } 243 244 hpi_status_t 245 hpi_pfc_set_rx_int_stat_mask(hpi_handle_t handle, boolean_t overflow_cnt, 246 boolean_t frame_cnt) 247 { 248 uint64_t offset; 249 uint64_t value = 0; 250 251 if (overflow_cnt) 252 value |= HXGE_VMAC_RX_MASK_OVERFLOW; 253 254 if (frame_cnt) 255 value |= HXGE_VMAC_RX_MASK_FRAME; 256 257 offset = VMAC_RX_MSK; 258 REG_PIO_WRITE64(handle, offset, value); 259 260 return (HPI_SUCCESS); 261 } 262 263 hpi_status_t 264 hpi_pfc_set_tx_int_stat_mask(hpi_handle_t handle, boolean_t overflow_cnt, 265 boolean_t frame_cnt) 266 { 267 uint64_t offset; 268 uint64_t value = 0; 269 uint64_t overflow_mask = 0x6; 270 uint64_t frame_mask = 0x1; 271 272 if (overflow_cnt) 273 value |= overflow_mask; 274 275 if (frame_cnt) 276 value |= frame_mask; 277 278 offset = VMAC_TX_MSK; 279 REG_PIO_WRITE64(handle, offset, value); 280 281 return (HPI_SUCCESS); 282 } 283