1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _E1000G_SW_H 27 #define _E1000G_SW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * ********************************************************************** 35 * Module Name: * 36 * e1000g_sw.h * 37 * * 38 * Abstract: * 39 * This header file contains Software-related data structures * 40 * definitions. * 41 * * 42 * ********************************************************************** 43 */ 44 45 #include <sys/types.h> 46 #include <sys/conf.h> 47 #include <sys/debug.h> 48 #include <sys/stropts.h> 49 #include <sys/stream.h> 50 #include <sys/strsun.h> 51 #include <sys/strlog.h> 52 #include <sys/kmem.h> 53 #include <sys/stat.h> 54 #include <sys/kstat.h> 55 #include <sys/modctl.h> 56 #include <sys/errno.h> 57 #include <sys/mac.h> 58 #include <sys/mac_ether.h> 59 #include <sys/vlan.h> 60 #include <sys/ddi.h> 61 #include <sys/sunddi.h> 62 #include <sys/disp.h> 63 #include <sys/pci.h> 64 #include <sys/sdt.h> 65 #include <sys/ethernet.h> 66 #include <sys/pattr.h> 67 #include <sys/strsubr.h> 68 #include <sys/netlb.h> 69 #include <inet/common.h> 70 #include <inet/ip.h> 71 #include <inet/tcp.h> 72 #include <inet/mi.h> 73 #include <inet/nd.h> 74 #include <sys/ddifm.h> 75 #include <sys/fm/protocol.h> 76 #include <sys/fm/util.h> 77 #include <sys/fm/io/ddi.h> 78 #include "e1000_api.h" 79 80 #define JUMBO_FRAG_LENGTH 4096 81 82 #define LAST_RAR_ENTRY (E1000_RAR_ENTRIES - 1) 83 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 84 #define MAX_NUM_MULTICAST_ADDRESSES 256 85 86 /* 87 * MAX_COOKIES = max_LSO_packet_size(65535 + ethernet_header_len)/page_size 88 * + one for cross page split 89 * MAX_TX_DESC_PER_PACKET = MAX_COOKIES + one for the context descriptor + 90 * two for the workaround of the 82546 chip 91 */ 92 #define MAX_COOKIES 18 93 #define MAX_TX_DESC_PER_PACKET 21 94 95 /* 96 * constants used in setting flow control thresholds 97 */ 98 #define E1000_PBA_10K 0x000A 99 #define E1000_PBA_MASK 0xffff 100 #define E1000_PBA_SHIFT 10 101 #define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 102 #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 103 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 104 105 #define MAX_NUM_TX_DESCRIPTOR 4096 106 #define MAX_NUM_RX_DESCRIPTOR 4096 107 #define MAX_NUM_RX_FREELIST 4096 108 #define MAX_NUM_TX_FREELIST 4096 109 #define MAX_RX_LIMIT_ON_INTR 4096 110 #define MAX_RX_INTR_DELAY 65535 111 #define MAX_RX_INTR_ABS_DELAY 65535 112 #define MAX_TX_INTR_DELAY 65535 113 #define MAX_TX_INTR_ABS_DELAY 65535 114 #define MAX_INTR_THROTTLING 65535 115 #define MAX_RX_BCOPY_THRESHOLD E1000_RX_BUFFER_SIZE_2K 116 #define MAX_TX_BCOPY_THRESHOLD E1000_TX_BUFFER_SIZE_2K 117 #define MAX_TX_RECYCLE_THRESHOLD MAX_NUM_TX_DESCRIPTOR 118 #define MAX_TX_RECYCLE_NUM MAX_NUM_TX_DESCRIPTOR 119 120 #define MIN_NUM_TX_DESCRIPTOR 80 121 #define MIN_NUM_RX_DESCRIPTOR 80 122 #define MIN_NUM_RX_FREELIST 64 123 #define MIN_NUM_TX_FREELIST 80 124 #define MIN_RX_LIMIT_ON_INTR 16 125 #define MIN_RX_INTR_DELAY 0 126 #define MIN_RX_INTR_ABS_DELAY 0 127 #define MIN_TX_INTR_DELAY 0 128 #define MIN_TX_INTR_ABS_DELAY 0 129 #define MIN_INTR_THROTTLING 0 130 #define MIN_RX_BCOPY_THRESHOLD 0 131 #define MIN_TX_BCOPY_THRESHOLD ETHERMIN 132 #define MIN_TX_RECYCLE_THRESHOLD 0 133 #define MIN_TX_RECYCLE_NUM MAX_TX_DESC_PER_PACKET 134 135 #define DEFAULT_NUM_RX_DESCRIPTOR 2048 136 #define DEFAULT_NUM_TX_DESCRIPTOR 2048 137 #define DEFAULT_NUM_RX_FREELIST 4096 138 #define DEFAULT_NUM_TX_FREELIST 2304 139 #define DEFAULT_RX_LIMIT_ON_INTR 128 140 141 #ifdef __sparc 142 #define MAX_INTR_PER_SEC 7100 143 #define MIN_INTR_PER_SEC 3000 144 #define DEFAULT_INTR_PACKET_LOW 5 145 #define DEFAULT_INTR_PACKET_HIGH 128 146 #define DEFAULT_TX_RECYCLE_THRESHOLD 512 147 #else 148 #define MAX_INTR_PER_SEC 15000 149 #define MIN_INTR_PER_SEC 4000 150 #define DEFAULT_INTR_PACKET_LOW 10 151 #define DEFAULT_INTR_PACKET_HIGH 48 152 #define DEFAULT_TX_RECYCLE_THRESHOLD DEFAULT_TX_NO_RESOURCE 153 #endif 154 155 #define DEFAULT_RX_INTR_DELAY 0 156 #define DEFAULT_RX_INTR_ABS_DELAY 64 157 #define DEFAULT_TX_INTR_DELAY 64 158 #define DEFAULT_TX_INTR_ABS_DELAY 64 159 #define DEFAULT_INTR_THROTTLING_HIGH 1000000000/(MIN_INTR_PER_SEC*256) 160 #define DEFAULT_INTR_THROTTLING_LOW 1000000000/(MAX_INTR_PER_SEC*256) 161 #define DEFAULT_INTR_THROTTLING DEFAULT_INTR_THROTTLING_LOW 162 163 #define DEFAULT_RX_BCOPY_THRESHOLD 128 164 #define DEFAULT_TX_BCOPY_THRESHOLD 512 165 #define DEFAULT_TX_RECYCLE_NUM 64 166 #define DEFAULT_TX_UPDATE_THRESHOLD 256 167 #define DEFAULT_TX_NO_RESOURCE MAX_TX_DESC_PER_PACKET 168 169 #define DEFAULT_TX_INTR_ENABLE 1 170 #define DEFAULT_FLOW_CONTROL 3 171 #define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */ 172 /* which is normally 0x040 */ 173 #define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */ 174 #define DEFAULT_MSI_ENABLE 1 /* MSI Enable */ 175 #define DEFAULT_TX_HCKSUM_ENABLE 1 /* Hardware checksum enable */ 176 #define DEFAULT_LSO_ENABLE 1 /* LSO enable */ 177 178 #define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */ 179 180 /* 181 * The size of the receive/transmite buffers 182 */ 183 #define E1000_RX_BUFFER_SIZE_2K (2048) 184 #define E1000_RX_BUFFER_SIZE_4K (4096) 185 #define E1000_RX_BUFFER_SIZE_8K (8192) 186 #define E1000_RX_BUFFER_SIZE_16K (16384) 187 188 #define E1000_TX_BUFFER_SIZE_2K (2048) 189 #define E1000_TX_BUFFER_SIZE_4K (4096) 190 #define E1000_TX_BUFFER_SIZE_8K (8192) 191 #define E1000_TX_BUFFER_SIZE_16K (16384) 192 193 #define E1000_TX_BUFFER_OEVRRUN_THRESHOLD (2015) 194 195 #define E1000G_RX_SW_FREE 0x0 196 #define E1000G_RX_SW_SENDUP 0x1 197 #define E1000G_RX_SW_STOP 0x2 198 #define E1000G_RX_SW_DETACH 0x3 199 200 /* 201 * definitions for smartspeed workaround 202 */ 203 #define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */ 204 /* or 30 seconds */ 205 #define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */ 206 /* or 6 seconds */ 207 208 /* 209 * Definitions for module_info. 210 */ 211 #define WSNAME "e1000g" /* module name */ 212 213 /* 214 * Defined for IP header alignment. We also need to preserve space for 215 * VLAN tag (4 bytes) 216 */ 217 #define E1000G_IPALIGNROOM 6 218 #define E1000G_IPALIGNPRESERVEROOM 64 219 220 /* 221 * bit flags for 'attach_progress' which is a member variable in struct e1000g 222 */ 223 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 224 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 225 #define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */ 226 #define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */ 227 #define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */ 228 #define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */ 229 #define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */ 230 #define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */ 231 #define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */ 232 /* 0200 used to be PROGRESS_NDD. Now unused */ 233 #define ATTACH_PROGRESS_MAC 0x0400 /* MAC registered */ 234 #define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */ 235 #define ATTACH_PROGRESS_FMINIT 0x1000 /* FMA initiated */ 236 237 /* 238 * Speed and Duplex Settings 239 */ 240 #define GDIAG_10_HALF 1 241 #define GDIAG_10_FULL 2 242 #define GDIAG_100_HALF 3 243 #define GDIAG_100_FULL 4 244 #define GDIAG_1000_FULL 6 245 #define GDIAG_ANY 7 246 247 /* 248 * Coexist Workaround RP: 07/04/03 249 * 82544 Workaround : Co-existence 250 */ 251 #define MAX_TX_BUF_SIZE (8 * 1024) 252 253 /* 254 * Defines for Jumbo Frame 255 */ 256 #define FRAME_SIZE_UPTO_2K 2048 257 #define FRAME_SIZE_UPTO_4K 4096 258 #define FRAME_SIZE_UPTO_8K 8192 259 #define FRAME_SIZE_UPTO_16K 16384 260 #define FRAME_SIZE_UPTO_9K 9234 261 262 #define MAXIMUM_MTU 9000 263 #define DEFAULT_MTU ETHERMTU 264 265 #define DEFAULT_FRAME_SIZE \ 266 (DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 267 #define MAXIMUM_FRAME_SIZE \ 268 (MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 269 270 #define E1000_LSO_MAXLEN 65535 271 272 /* Defines for Tx stall check */ 273 #define E1000G_STALL_WATCHDOG_COUNT 8 274 275 #define MAX_TX_LINK_DOWN_TIMEOUT 8 276 277 /* Defines for DVMA */ 278 #ifdef __sparc 279 #define E1000G_DEFAULT_DVMA_PAGE_NUM 2 280 #endif 281 282 /* 283 * Loopback definitions 284 */ 285 #define E1000G_LB_NONE 0 286 #define E1000G_LB_EXTERNAL_1000 1 287 #define E1000G_LB_EXTERNAL_100 2 288 #define E1000G_LB_EXTERNAL_10 3 289 #define E1000G_LB_INTERNAL_PHY 4 290 291 /* 292 * Private dip list definitions 293 */ 294 #define E1000G_PRIV_DEVI_ATTACH 0x0 295 #define E1000G_PRIV_DEVI_DETACH 0x1 296 297 /* 298 * Tx descriptor LENGTH field mask 299 */ 300 #define E1000G_TBD_LENGTH_MASK 0x000fffff 301 302 /* 303 * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. 304 */ 305 #define QUEUE_INIT_LIST(_LH) \ 306 (_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0 307 308 /* 309 * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty. 310 */ 311 #define IS_QUEUE_EMPTY(_LH) \ 312 ((_LH)->Flink == (PSINGLE_LIST_LINK)0) 313 314 /* 315 * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does 316 * not remove the head from the queue. 317 */ 318 #define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink)) 319 320 /* 321 * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue. 322 */ 323 #define QUEUE_REMOVE_HEAD(_LH) \ 324 { \ 325 PSINGLE_LIST_LINK ListElem; \ 326 if (ListElem = (_LH)->Flink) \ 327 { \ 328 if (!((_LH)->Flink = ListElem->Flink)) \ 329 (_LH)->Blink = (PSINGLE_LIST_LINK) 0; \ 330 } \ 331 } 332 333 /* 334 * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list), 335 * and return it (this differs from QUEUE_REMOVE_HEAD only in 336 * the 1st line). 337 */ 338 #define QUEUE_POP_HEAD(_LH) \ 339 (PSINGLE_LIST_LINK)(_LH)->Flink; \ 340 { \ 341 PSINGLE_LIST_LINK ListElem; \ 342 ListElem = (_LH)->Flink; \ 343 if (ListElem) \ 344 { \ 345 (_LH)->Flink = ListElem->Flink; \ 346 if (!(_LH)->Flink) \ 347 (_LH)->Blink = (PSINGLE_LIST_LINK)0; \ 348 } \ 349 } 350 351 /* 352 * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not 353 * remove the tail from the queue. 354 */ 355 #define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink)) 356 357 /* 358 * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue 359 */ 360 #define QUEUE_PUSH_TAIL(_LH, _E) \ 361 if ((_LH)->Blink) \ 362 { \ 363 ((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \ 364 (PSINGLE_LIST_LINK)(_E); \ 365 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 366 } else { \ 367 (_LH)->Flink = \ 368 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 369 } \ 370 (_E)->Flink = (PSINGLE_LIST_LINK)0; 371 372 /* 373 * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue. 374 */ 375 #define QUEUE_PUSH_HEAD(_LH, _E) \ 376 if (!((_E)->Flink = (_LH)->Flink)) \ 377 { \ 378 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 379 } \ 380 (_LH)->Flink = (PSINGLE_LIST_LINK)(_E); 381 382 /* 383 * QUEUE_GET_NEXT -- Macro which returns the next element linked to the 384 * current element. 385 */ 386 #define QUEUE_GET_NEXT(_LH, _E) \ 387 (PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \ 388 (0) : ((_E)->Flink)) 389 390 /* 391 * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue 392 */ 393 #define QUEUE_APPEND(_LH1, _LH2) \ 394 if ((_LH2)->Flink) { \ 395 if ((_LH1)->Flink) { \ 396 ((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \ 397 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 398 } else { \ 399 (_LH1)->Flink = \ 400 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 401 } \ 402 (_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \ 403 } 404 405 /* 406 * Property lookups 407 */ 408 #define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 409 DDI_PROP_DONTPASS, (n)) 410 #define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 411 DDI_PROP_DONTPASS, (n), -1) 412 413 #ifdef E1000G_DEBUG 414 /* 415 * E1000G-specific ioctls ... 416 */ 417 #define E1000G_IOC ((((((('E' << 4) + '1') << 4) \ 418 + 'K') << 4) + 'G') << 4) 419 420 /* 421 * These diagnostic IOCTLS are enabled only in DEBUG drivers 422 */ 423 #define E1000G_IOC_REG_PEEK (E1000G_IOC | 1) 424 #define E1000G_IOC_REG_POKE (E1000G_IOC | 2) 425 #define E1000G_IOC_CHIP_RESET (E1000G_IOC | 3) 426 427 #define E1000G_PP_SPACE_REG 0 /* PCI memory space */ 428 #define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */ 429 430 typedef struct { 431 uint64_t pp_acc_size; /* It's 1, 2, 4 or 8 */ 432 uint64_t pp_acc_space; /* See #defines below */ 433 uint64_t pp_acc_offset; /* See regs definition */ 434 uint64_t pp_acc_data; /* output for peek */ 435 /* input for poke */ 436 } e1000g_peekpoke_t; 437 #endif /* E1000G_DEBUG */ 438 439 /* 440 * (Internal) return values from ioctl subroutines 441 */ 442 enum ioc_reply { 443 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 444 IOC_DONE, /* OK, reply sent */ 445 IOC_ACK, /* OK, just send ACK */ 446 IOC_REPLY /* OK, just send reply */ 447 }; 448 449 /* 450 * Named Data (ND) Parameter Management Structure 451 */ 452 typedef struct { 453 uint32_t ndp_info; 454 uint32_t ndp_min; 455 uint32_t ndp_max; 456 uint32_t ndp_val; 457 struct e1000g *ndp_instance; 458 char *ndp_name; 459 } nd_param_t; 460 461 /* 462 * The entry of the private dip list 463 */ 464 typedef struct _private_devi_list { 465 dev_info_t *priv_dip; 466 uint16_t flag; 467 struct _private_devi_list *next; 468 } private_devi_list_t; 469 470 /* 471 * A structure that points to the next entry in the queue. 472 */ 473 typedef struct _SINGLE_LIST_LINK { 474 struct _SINGLE_LIST_LINK *Flink; 475 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK; 476 477 /* 478 * A "ListHead" structure that points to the head and tail of a queue 479 */ 480 typedef struct _LIST_DESCRIBER { 481 struct _SINGLE_LIST_LINK *volatile Flink; 482 struct _SINGLE_LIST_LINK *volatile Blink; 483 } LIST_DESCRIBER, *PLIST_DESCRIBER; 484 485 /* 486 * Address-Length pair structure that stores descriptor info 487 */ 488 typedef struct _sw_desc { 489 uint64_t address; 490 uint32_t length; 491 } sw_desc_t, *p_sw_desc_t; 492 493 typedef struct _desc_array { 494 sw_desc_t descriptor[4]; 495 uint32_t elements; 496 } desc_array_t, *p_desc_array_t; 497 498 typedef enum { 499 USE_NONE, 500 USE_BCOPY, 501 USE_DVMA, 502 USE_DMA 503 } dma_type_t; 504 505 typedef enum { 506 E1000G_STOP, 507 E1000G_START, 508 E1000G_ERROR 509 } chip_state_t; 510 511 typedef struct _dma_buffer { 512 caddr_t address; 513 uint64_t dma_address; 514 ddi_acc_handle_t acc_handle; 515 ddi_dma_handle_t dma_handle; 516 size_t size; 517 size_t len; 518 } dma_buffer_t, *p_dma_buffer_t; 519 520 /* 521 * Transmit Control Block (TCB), Ndis equiv of SWPacket This 522 * structure stores the additional information that is 523 * associated with every packet to be transmitted. It stores the 524 * message block pointer and the TBD addresses associated with 525 * the m_blk and also the link to the next tcb in the chain 526 */ 527 typedef struct _tx_sw_packet { 528 /* Link to the next tx_sw_packet in the list */ 529 SINGLE_LIST_LINK Link; 530 mblk_t *mp; 531 uint32_t num_desc; 532 uint32_t num_mblk_frag; 533 dma_type_t dma_type; 534 dma_type_t data_transfer_type; 535 ddi_dma_handle_t tx_dma_handle; 536 dma_buffer_t tx_buf[1]; 537 sw_desc_t desc[MAX_TX_DESC_PER_PACKET]; 538 } tx_sw_packet_t, *p_tx_sw_packet_t; 539 540 /* 541 * This structure is similar to the rx_sw_packet structure used 542 * for Ndis. This structure stores information about the 2k 543 * aligned receive buffer into which the FX1000 DMA's frames. 544 * This structure is maintained as a linked list of many 545 * receiver buffer pointers. 546 */ 547 typedef struct _rx_sw_packet { 548 /* Link to the next rx_sw_packet_t in the list */ 549 SINGLE_LIST_LINK Link; 550 struct _rx_sw_packet *next; 551 uint16_t flag; 552 mblk_t *mp; 553 caddr_t rx_ring; 554 dma_type_t dma_type; 555 frtn_t free_rtn; 556 dma_buffer_t rx_buf[1]; 557 } rx_sw_packet_t, *p_rx_sw_packet_t; 558 559 typedef struct _mblk_list { 560 mblk_t *head; 561 mblk_t *tail; 562 } mblk_list_t, *p_mblk_list_t; 563 564 typedef struct _context_data { 565 uint32_t ether_header_size; 566 uint32_t cksum_flags; 567 uint32_t cksum_start; 568 uint32_t cksum_stuff; 569 uint16_t mss; 570 uint8_t hdr_len; 571 uint32_t pay_len; 572 boolean_t lso_flag; 573 } context_data_t; 574 575 typedef union _e1000g_ether_addr { 576 struct { 577 uint32_t high; 578 uint32_t low; 579 } reg; 580 struct { 581 uint8_t set; 582 uint8_t redundant; 583 uint8_t addr[ETHERADDRL]; 584 } mac; 585 } e1000g_ether_addr_t; 586 587 typedef struct _e1000g_stat { 588 589 kstat_named_t link_speed; /* Link Speed */ 590 kstat_named_t reset_count; /* Reset Count */ 591 592 kstat_named_t rx_error; /* Rx Error in Packet */ 593 kstat_named_t rx_esballoc_fail; /* Rx Desballoc Failure */ 594 kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ 595 596 kstat_named_t tx_no_desc; /* Tx No Desc */ 597 kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ 598 kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ 599 kstat_named_t tx_over_size; /* Tx Pkt Too Long */ 600 kstat_named_t tx_reschedule; /* Tx Reschedule */ 601 602 #ifdef E1000G_DEBUG 603 kstat_named_t rx_none; /* Rx No Incoming Data */ 604 kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */ 605 kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */ 606 kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */ 607 608 kstat_named_t tx_under_size; /* Tx Packet Under Size */ 609 kstat_named_t tx_empty_frags; /* Tx Empty Frags */ 610 kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */ 611 kstat_named_t tx_recycle; /* Tx Recycle */ 612 kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ 613 kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */ 614 kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */ 615 kstat_named_t tx_copy; /* Tx Send Copy */ 616 kstat_named_t tx_bind; /* Tx Send Bind */ 617 kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */ 618 kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ 619 kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ 620 #endif 621 622 kstat_named_t Crcerrs; /* CRC Error Count */ 623 kstat_named_t Symerrs; /* Symbol Error Count */ 624 kstat_named_t Mpc; /* Missed Packet Count */ 625 kstat_named_t Scc; /* Single Collision Count */ 626 kstat_named_t Ecol; /* Excessive Collision Count */ 627 kstat_named_t Mcc; /* Multiple Collision Count */ 628 kstat_named_t Latecol; /* Late Collision Count */ 629 kstat_named_t Colc; /* Collision Count */ 630 kstat_named_t Dc; /* Defer Count */ 631 kstat_named_t Sec; /* Sequence Error Count */ 632 kstat_named_t Rlec; /* Receive Length Error Count */ 633 kstat_named_t Xonrxc; /* XON Received Count */ 634 kstat_named_t Xontxc; /* XON Xmitted Count */ 635 kstat_named_t Xoffrxc; /* XOFF Received Count */ 636 kstat_named_t Xofftxc; /* Xoff Xmitted Count */ 637 kstat_named_t Fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 638 #ifdef E1000G_DEBUG 639 kstat_named_t Prc64; /* Packets Received - 64b */ 640 kstat_named_t Prc127; /* Packets Received - 65-127b */ 641 kstat_named_t Prc255; /* Packets Received - 127-255b */ 642 kstat_named_t Prc511; /* Packets Received - 256-511b */ 643 kstat_named_t Prc1023; /* Packets Received - 511-1023b */ 644 kstat_named_t Prc1522; /* Packets Received - 1024-1522b */ 645 #endif 646 kstat_named_t Gprc; /* Good Packets Received Count */ 647 kstat_named_t Bprc; /* Broadcasts Pkts Received Count */ 648 kstat_named_t Mprc; /* Multicast Pkts Received Count */ 649 kstat_named_t Gptc; /* Good Packets Xmitted Count */ 650 kstat_named_t Gorl; /* Good Octets Recvd Lo Count */ 651 kstat_named_t Gorh; /* Good Octets Recvd Hi Count */ 652 kstat_named_t Gotl; /* Good Octets Xmitd Lo Count */ 653 kstat_named_t Goth; /* Good Octets Xmitd Hi Count */ 654 kstat_named_t Rnbc; /* Receive No Buffers Count */ 655 kstat_named_t Ruc; /* Receive Undersize Count */ 656 kstat_named_t Rfc; /* Receive Frag Count */ 657 kstat_named_t Roc; /* Receive Oversize Count */ 658 kstat_named_t Rjc; /* Receive Jabber Count */ 659 kstat_named_t Torl; /* Total Octets Recvd Lo Count */ 660 kstat_named_t Torh; /* Total Octets Recvd Hi Count */ 661 kstat_named_t Totl; /* Total Octets Xmted Lo Count */ 662 kstat_named_t Toth; /* Total Octets Xmted Hi Count */ 663 kstat_named_t Tpr; /* Total Packets Received */ 664 kstat_named_t Tpt; /* Total Packets Xmitted */ 665 #ifdef E1000G_DEBUG 666 kstat_named_t Ptc64; /* Packets Xmitted (64b) */ 667 kstat_named_t Ptc127; /* Packets Xmitted (64-127b) */ 668 kstat_named_t Ptc255; /* Packets Xmitted (128-255b) */ 669 kstat_named_t Ptc511; /* Packets Xmitted (255-511b) */ 670 kstat_named_t Ptc1023; /* Packets Xmitted (512-1023b) */ 671 kstat_named_t Ptc1522; /* Packets Xmitted (1024-1522b */ 672 #endif 673 kstat_named_t Mptc; /* Multicast Packets Xmited Count */ 674 kstat_named_t Bptc; /* Broadcast Packets Xmited Count */ 675 kstat_named_t Algnerrc; /* Alignment Error count */ 676 kstat_named_t Tuc; /* Transmit Underrun count */ 677 kstat_named_t Rxerrc; /* Rx Error Count */ 678 kstat_named_t Tncrs; /* Transmit with no CRS */ 679 kstat_named_t Cexterr; /* Carrier Extension Error count */ 680 kstat_named_t Rutec; /* Receive DMA too Early count */ 681 kstat_named_t Tsctc; /* TCP seg contexts xmit count */ 682 kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */ 683 } e1000g_stat_t, *p_e1000g_stat_t; 684 685 typedef struct _e1000g_tx_ring { 686 kmutex_t tx_lock; 687 kmutex_t freelist_lock; 688 kmutex_t usedlist_lock; 689 /* 690 * Descriptor queue definitions 691 */ 692 ddi_dma_handle_t tbd_dma_handle; 693 ddi_acc_handle_t tbd_acc_handle; 694 struct e1000_tx_desc *tbd_area; 695 uint64_t tbd_dma_addr; 696 struct e1000_tx_desc *tbd_first; 697 struct e1000_tx_desc *tbd_last; 698 struct e1000_tx_desc *tbd_oldest; 699 struct e1000_tx_desc *tbd_next; 700 uint32_t tbd_avail; 701 /* 702 * Software packet structures definitions 703 */ 704 p_tx_sw_packet_t packet_area; 705 LIST_DESCRIBER used_list; 706 LIST_DESCRIBER free_list; 707 /* 708 * TCP/UDP Context Data Information 709 */ 710 context_data_t pre_context; 711 /* 712 * Timer definitions for 82547 713 */ 714 timeout_id_t timer_id_82547; 715 boolean_t timer_enable_82547; 716 /* 717 * reschedule when tx resource is available 718 */ 719 boolean_t resched_needed; 720 uint32_t stall_watchdog; 721 uint32_t recycle_fail; 722 mblk_list_t mblks; 723 /* 724 * Statistics 725 */ 726 uint32_t stat_no_swpkt; 727 uint32_t stat_no_desc; 728 uint32_t stat_send_fail; 729 uint32_t stat_reschedule; 730 uint32_t stat_over_size; 731 #ifdef E1000G_DEBUG 732 uint32_t stat_under_size; 733 uint32_t stat_exceed_frags; 734 uint32_t stat_empty_frags; 735 uint32_t stat_recycle; 736 uint32_t stat_recycle_intr; 737 uint32_t stat_recycle_retry; 738 uint32_t stat_recycle_none; 739 uint32_t stat_copy; 740 uint32_t stat_bind; 741 uint32_t stat_multi_copy; 742 uint32_t stat_multi_cookie; 743 uint32_t stat_lack_desc; 744 uint32_t stat_lso_header_fail; 745 #endif 746 /* 747 * Pointer to the adapter 748 */ 749 struct e1000g *adapter; 750 } e1000g_tx_ring_t, *pe1000g_tx_ring_t; 751 752 typedef struct _e1000g_rx_ring { 753 kmutex_t rx_lock; 754 kmutex_t freelist_lock; 755 /* 756 * Descriptor queue definitions 757 */ 758 ddi_dma_handle_t rbd_dma_handle; 759 ddi_acc_handle_t rbd_acc_handle; 760 struct e1000_rx_desc *rbd_area; 761 uint64_t rbd_dma_addr; 762 struct e1000_rx_desc *rbd_first; 763 struct e1000_rx_desc *rbd_last; 764 struct e1000_rx_desc *rbd_next; 765 /* 766 * Software packet structures definitions 767 */ 768 p_rx_sw_packet_t packet_area; 769 LIST_DESCRIBER recv_list; 770 LIST_DESCRIBER free_list; 771 772 p_rx_sw_packet_t pending_list; 773 uint32_t pending_count; 774 uint32_t avail_freepkt; 775 uint32_t rx_mblk_len; 776 mblk_t *rx_mblk; 777 mblk_t *rx_mblk_tail; 778 /* 779 * Statistics 780 */ 781 uint32_t stat_error; 782 uint32_t stat_esballoc_fail; 783 uint32_t stat_allocb_fail; 784 uint32_t stat_exceed_pkt; 785 #ifdef E1000G_DEBUG 786 uint32_t stat_none; 787 uint32_t stat_multi_desc; 788 uint32_t stat_no_freepkt; 789 #endif 790 /* 791 * Pointer to the adapter 792 */ 793 struct e1000g *adapter; 794 } e1000g_rx_ring_t, *pe1000g_rx_ring_t; 795 796 typedef struct e1000g { 797 int instance; 798 dev_info_t *dip; 799 dev_info_t *priv_dip; 800 mac_handle_t mh; 801 mac_resource_handle_t mrh; 802 struct e1000_hw shared; 803 struct e1000g_osdep osdep; 804 805 chip_state_t chip_state; 806 boolean_t e1000g_promisc; 807 boolean_t strip_crc; 808 boolean_t rx_buffer_setup; 809 boolean_t esb2_workaround; 810 link_state_t link_state; 811 uint32_t link_speed; 812 uint32_t link_duplex; 813 uint32_t master_latency_timer; 814 uint32_t smartspeed; /* smartspeed w/a counter */ 815 uint32_t init_count; 816 uint32_t reset_count; 817 uint32_t attach_progress; /* attach tracking */ 818 uint32_t loopback_mode; 819 820 uint32_t tx_desc_num; 821 uint32_t tx_freelist_num; 822 uint32_t rx_desc_num; 823 uint32_t rx_freelist_num; 824 uint32_t tx_buffer_size; 825 uint32_t rx_buffer_size; 826 827 uint32_t tx_link_down_timeout; 828 uint32_t tx_bcopy_thresh; 829 uint32_t rx_limit_onintr; 830 uint32_t rx_bcopy_thresh; 831 uint32_t rx_buf_align; 832 uint32_t desc_align; 833 834 boolean_t intr_adaptive; 835 boolean_t tx_intr_enable; 836 uint32_t tx_recycle_thresh; 837 uint32_t tx_recycle_num; 838 uint32_t tx_intr_delay; 839 uint32_t tx_intr_abs_delay; 840 uint32_t rx_intr_delay; 841 uint32_t rx_intr_abs_delay; 842 uint32_t intr_throttling_rate; 843 844 uint32_t default_mtu; 845 uint32_t max_frame_size; 846 uint32_t min_frame_size; 847 848 boolean_t watchdog_timer_enabled; 849 boolean_t watchdog_timer_started; 850 timeout_id_t watchdog_tid; 851 boolean_t link_complete; 852 timeout_id_t link_tid; 853 854 e1000g_rx_ring_t rx_ring[1]; 855 e1000g_tx_ring_t tx_ring[1]; 856 857 /* 858 * Rx and Tx packet count for interrupt adaptive setting 859 */ 860 uint32_t rx_pkt_cnt; 861 uint32_t tx_pkt_cnt; 862 863 /* 864 * The watchdog_lock must be held when updateing the 865 * timeout fields in struct e1000g, that is, 866 * watchdog_tid, watchdog_timer_started. 867 */ 868 kmutex_t watchdog_lock; 869 /* 870 * The link_lock protects the link fields in struct e1000g, 871 * such as link_state, link_speed, link_duplex, link_complete, and 872 * link_tid. 873 */ 874 kmutex_t link_lock; 875 /* 876 * The chip_lock assures that the Rx/Tx process must be 877 * stopped while other functions change the hardware 878 * configuration of e1000g card, such as e1000g_reset(), 879 * e1000g_reset_hw() etc are executed. 880 */ 881 krwlock_t chip_lock; 882 883 boolean_t unicst_init; 884 uint32_t unicst_avail; 885 uint32_t unicst_total; 886 e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 887 888 uint32_t mcast_count; 889 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 890 891 ulong_t sys_page_sz; 892 #ifdef __sparc 893 uint_t dvma_page_num; 894 #endif 895 896 boolean_t msi_enable; 897 boolean_t tx_hcksum_enable; 898 boolean_t lso_enable; 899 boolean_t lso_premature_issue; 900 int intr_type; 901 int intr_cnt; 902 int intr_cap; 903 size_t intr_size; 904 uint_t intr_pri; 905 ddi_intr_handle_t *htable; 906 907 int tx_softint_pri; 908 ddi_softint_handle_t tx_softint_handle; 909 910 kstat_t *e1000g_ksp; 911 912 uint16_t phy_ctrl; /* contents of PHY_CTRL */ 913 uint16_t phy_status; /* contents of PHY_STATUS */ 914 uint16_t phy_an_adv; /* contents of PHY_AUTONEG_ADV */ 915 uint16_t phy_an_exp; /* contents of PHY_AUTONEG_EXP */ 916 uint16_t phy_ext_status; /* contents of PHY_EXT_STATUS */ 917 uint16_t phy_1000t_ctrl; /* contents of PHY_1000T_CTRL */ 918 uint16_t phy_1000t_status; /* contents of PHY_1000T_STATUS */ 919 uint16_t phy_lp_able; /* contents of PHY_LP_ABILITY */ 920 921 /* 922 * FMA capabilities 923 */ 924 int fm_capabilities; 925 926 uint32_t param_en_1000fdx:1, 927 param_en_1000hdx:1, 928 param_en_100fdx:1, 929 param_en_100hdx:1, 930 param_en_10fdx:1, 931 param_en_10hdx:1, 932 param_autoneg_cap:1, 933 param_pause_cap:1, 934 param_asym_pause_cap:1, 935 param_1000fdx_cap:1, 936 param_1000hdx_cap:1, 937 param_100t4_cap:1, 938 param_100fdx_cap:1, 939 param_100hdx_cap:1, 940 param_10fdx_cap:1, 941 param_10hdx_cap:1, 942 param_adv_autoneg:1, 943 param_adv_pause:1, 944 param_adv_asym_pause:1, 945 param_adv_1000fdx:1, 946 param_adv_1000hdx:1, 947 param_adv_100t4:1, 948 param_adv_100fdx:1, 949 param_adv_100hdx:1, 950 param_adv_10fdx:1, 951 param_adv_10hdx:1, 952 param_lp_autoneg:1, 953 param_lp_pause:1, 954 param_lp_asym_pause:1, 955 param_lp_1000fdx:1, 956 param_lp_1000hdx:1, 957 param_lp_100t4:1; 958 959 uint32_t param_lp_100fdx:1, 960 param_lp_100hdx:1, 961 param_lp_10fdx:1, 962 param_lp_10hdx:1, 963 param_pad_to_32:28; 964 965 } e1000g_t; 966 967 968 /* 969 * Function prototypes 970 */ 971 int e1000g_alloc_dma_resources(struct e1000g *Adapter); 972 void e1000g_release_dma_resources(struct e1000g *Adapter); 973 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet); 974 void e1000g_tx_setup(struct e1000g *Adapter); 975 void e1000g_rx_setup(struct e1000g *Adapter); 976 void e1000g_setup_multicast(struct e1000g *Adapter); 977 978 int e1000g_recycle(e1000g_tx_ring_t *tx_ring); 979 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet); 980 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring); 981 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2); 982 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp); 983 mblk_t *e1000g_receive(struct e1000g *Adapter); 984 void e1000g_rxfree_func(p_rx_sw_packet_t packet); 985 986 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val); 987 int e1000g_init_stats(struct e1000g *Adapter); 988 void e1000_tbi_adjust_stats(struct e1000g *Adapter, 989 uint32_t frame_len, uint8_t *mac_addr); 990 991 void e1000g_clear_interrupt(struct e1000g *Adapter); 992 void e1000g_mask_interrupt(struct e1000g *Adapter); 993 void e1000g_clear_all_interrupts(struct e1000g *Adapter); 994 void e1000g_clear_tx_interrupt(struct e1000g *Adapter); 995 void e1000g_mask_tx_interrupt(struct e1000g *Adapter); 996 void phy_spd_state(struct e1000_hw *hw, boolean_t enable); 997 void e1000_enable_pciex_master(struct e1000_hw *hw); 998 int e1000g_check_acc_handle(ddi_acc_handle_t handle); 999 int e1000g_check_dma_handle(ddi_dma_handle_t handle); 1000 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail); 1001 void e1000g_set_fma_flags(struct e1000g *Adapter, int acc_flag, int dma_flag); 1002 int e1000g_reset_link(struct e1000g *Adapter); 1003 1004 /* 1005 * Global variables 1006 */ 1007 extern boolean_t e1000g_force_detach; 1008 extern uint32_t e1000g_mblks_pending; 1009 extern krwlock_t e1000g_rx_detach_lock; 1010 extern private_devi_list_t *e1000g_private_devi_list; 1011 1012 #ifdef __cplusplus 1013 } 1014 #endif 1015 1016 #endif /* _E1000G_SW_H */ 1017