1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _E1000G_SW_H 27 #define _E1000G_SW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * ********************************************************************** 35 * Module Name: * 36 * e1000g_sw.h * 37 * * 38 * Abstract: * 39 * This header file contains Software-related data structures * 40 * definitions. * 41 * * 42 * ********************************************************************** 43 */ 44 45 #include <sys/types.h> 46 #include <sys/conf.h> 47 #include <sys/debug.h> 48 #include <sys/stropts.h> 49 #include <sys/stream.h> 50 #include <sys/strsun.h> 51 #include <sys/strlog.h> 52 #include <sys/kmem.h> 53 #include <sys/stat.h> 54 #include <sys/kstat.h> 55 #include <sys/modctl.h> 56 #include <sys/errno.h> 57 #include <sys/mac_provider.h> 58 #include <sys/mac_ether.h> 59 #include <sys/vlan.h> 60 #include <sys/ddi.h> 61 #include <sys/sunddi.h> 62 #include <sys/disp.h> 63 #include <sys/pci.h> 64 #include <sys/sdt.h> 65 #include <sys/ethernet.h> 66 #include <sys/pattr.h> 67 #include <sys/strsubr.h> 68 #include <sys/netlb.h> 69 #include <inet/common.h> 70 #include <inet/ip.h> 71 #include <inet/tcp.h> 72 #include <inet/mi.h> 73 #include <inet/nd.h> 74 #include <sys/ddifm.h> 75 #include <sys/fm/protocol.h> 76 #include <sys/fm/util.h> 77 #include <sys/fm/io/ddi.h> 78 #include "e1000_api.h" 79 80 #define JUMBO_FRAG_LENGTH 4096 81 82 #define LAST_RAR_ENTRY (E1000_RAR_ENTRIES - 1) 83 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 84 #define MAX_NUM_MULTICAST_ADDRESSES 256 85 86 /* 87 * MAX_COOKIES = max_LSO_packet_size(65535 + ethernet_header_len)/page_size 88 * + one for cross page split 89 * MAX_TX_DESC_PER_PACKET = MAX_COOKIES + one for the context descriptor + 90 * two for the workaround of the 82546 chip 91 */ 92 #define MAX_COOKIES 18 93 #define MAX_TX_DESC_PER_PACKET 21 94 95 /* 96 * constants used in setting flow control thresholds 97 */ 98 #define E1000_PBA_10K 0x000A 99 #define E1000_PBA_MASK 0xffff 100 #define E1000_PBA_SHIFT 10 101 #define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 102 #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 103 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 104 105 #define MAX_NUM_TX_DESCRIPTOR 4096 106 #define MAX_NUM_RX_DESCRIPTOR 4096 107 #define MAX_NUM_RX_FREELIST 4096 108 #define MAX_NUM_TX_FREELIST 4096 109 #define MAX_RX_LIMIT_ON_INTR 4096 110 #define MAX_RX_INTR_DELAY 65535 111 #define MAX_RX_INTR_ABS_DELAY 65535 112 #define MAX_TX_INTR_DELAY 65535 113 #define MAX_TX_INTR_ABS_DELAY 65535 114 #define MAX_INTR_THROTTLING 65535 115 #define MAX_RX_BCOPY_THRESHOLD E1000_RX_BUFFER_SIZE_2K 116 #define MAX_TX_BCOPY_THRESHOLD E1000_TX_BUFFER_SIZE_2K 117 118 #define MIN_NUM_TX_DESCRIPTOR 80 119 #define MIN_NUM_RX_DESCRIPTOR 80 120 #define MIN_NUM_RX_FREELIST 64 121 #define MIN_NUM_TX_FREELIST 80 122 #define MIN_RX_LIMIT_ON_INTR 16 123 #define MIN_RX_INTR_DELAY 0 124 #define MIN_RX_INTR_ABS_DELAY 0 125 #define MIN_TX_INTR_DELAY 0 126 #define MIN_TX_INTR_ABS_DELAY 0 127 #define MIN_INTR_THROTTLING 0 128 #define MIN_RX_BCOPY_THRESHOLD 0 129 #define MIN_TX_BCOPY_THRESHOLD ETHERMIN 130 131 #define DEFAULT_NUM_RX_DESCRIPTOR 2048 132 #define DEFAULT_NUM_TX_DESCRIPTOR 2048 133 #define DEFAULT_NUM_RX_FREELIST 4096 134 #define DEFAULT_NUM_TX_FREELIST 2304 135 #define DEFAULT_RX_LIMIT_ON_INTR 128 136 137 #ifdef __sparc 138 #define MAX_INTR_PER_SEC 7100 139 #define MIN_INTR_PER_SEC 3000 140 #define DEFAULT_INTR_PACKET_LOW 5 141 #define DEFAULT_INTR_PACKET_HIGH 128 142 #else 143 #define MAX_INTR_PER_SEC 15000 144 #define MIN_INTR_PER_SEC 4000 145 #define DEFAULT_INTR_PACKET_LOW 10 146 #define DEFAULT_INTR_PACKET_HIGH 48 147 #endif 148 149 #define DEFAULT_RX_INTR_DELAY 0 150 #define DEFAULT_RX_INTR_ABS_DELAY 64 151 #define DEFAULT_TX_INTR_DELAY 64 152 #define DEFAULT_TX_INTR_ABS_DELAY 64 153 #define DEFAULT_INTR_THROTTLING_HIGH 1000000000/(MIN_INTR_PER_SEC*256) 154 #define DEFAULT_INTR_THROTTLING_LOW 1000000000/(MAX_INTR_PER_SEC*256) 155 #define DEFAULT_INTR_THROTTLING DEFAULT_INTR_THROTTLING_LOW 156 157 #define DEFAULT_RX_BCOPY_THRESHOLD 128 158 #define DEFAULT_TX_BCOPY_THRESHOLD 512 159 #define DEFAULT_TX_UPDATE_THRESHOLD 256 160 #define DEFAULT_TX_NO_RESOURCE MAX_TX_DESC_PER_PACKET 161 162 #define DEFAULT_TX_INTR_ENABLE 1 163 #define DEFAULT_FLOW_CONTROL 3 164 #define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */ 165 /* which is normally 0x040 */ 166 #define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */ 167 #define DEFAULT_MSI_ENABLE 1 /* MSI Enable */ 168 #define DEFAULT_TX_HCKSUM_ENABLE 1 /* Hardware checksum enable */ 169 #define DEFAULT_LSO_ENABLE 1 /* LSO enable */ 170 #define DEFAULT_MEM_WORKAROUND_82546 1 /* 82546 memory workaround */ 171 172 #define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */ 173 174 /* 175 * The size of the receive/transmite buffers 176 */ 177 #define E1000_RX_BUFFER_SIZE_2K (2048) 178 #define E1000_RX_BUFFER_SIZE_4K (4096) 179 #define E1000_RX_BUFFER_SIZE_8K (8192) 180 #define E1000_RX_BUFFER_SIZE_16K (16384) 181 182 #define E1000_TX_BUFFER_SIZE_2K (2048) 183 #define E1000_TX_BUFFER_SIZE_4K (4096) 184 #define E1000_TX_BUFFER_SIZE_8K (8192) 185 #define E1000_TX_BUFFER_SIZE_16K (16384) 186 187 #define E1000_TX_BUFFER_OEVRRUN_THRESHOLD (2015) 188 189 #define E1000G_RX_SW_FREE 0x0 190 #define E1000G_RX_SW_SENDUP 0x1 191 #define E1000G_RX_SW_STOP 0x2 192 #define E1000G_RX_SW_DETACH 0x3 193 194 /* 195 * definitions for smartspeed workaround 196 */ 197 #define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */ 198 /* or 30 seconds */ 199 #define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */ 200 /* or 6 seconds */ 201 202 /* 203 * Definitions for module_info. 204 */ 205 #define WSNAME "e1000g" /* module name */ 206 207 /* 208 * Defined for IP header alignment. We also need to preserve space for 209 * VLAN tag (4 bytes) 210 */ 211 #define E1000G_IPALIGNROOM 6 212 #define E1000G_IPALIGNPRESERVEROOM 64 213 214 /* 215 * bit flags for 'attach_progress' which is a member variable in struct e1000g 216 */ 217 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 218 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 219 #define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */ 220 #define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */ 221 #define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */ 222 #define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */ 223 #define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */ 224 #define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */ 225 #define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */ 226 /* 0200 used to be PROGRESS_NDD. Now unused */ 227 #define ATTACH_PROGRESS_MAC 0x0400 /* MAC registered */ 228 #define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */ 229 #define ATTACH_PROGRESS_FMINIT 0x1000 /* FMA initiated */ 230 231 /* 232 * Speed and Duplex Settings 233 */ 234 #define GDIAG_10_HALF 1 235 #define GDIAG_10_FULL 2 236 #define GDIAG_100_HALF 3 237 #define GDIAG_100_FULL 4 238 #define GDIAG_1000_FULL 6 239 #define GDIAG_ANY 7 240 241 /* 242 * Coexist Workaround RP: 07/04/03 243 * 82544 Workaround : Co-existence 244 */ 245 #define MAX_TX_BUF_SIZE (8 * 1024) 246 247 /* 248 * Defines for Jumbo Frame 249 */ 250 #define FRAME_SIZE_UPTO_2K 2048 251 #define FRAME_SIZE_UPTO_4K 4096 252 #define FRAME_SIZE_UPTO_8K 8192 253 #define FRAME_SIZE_UPTO_16K 16384 254 #define FRAME_SIZE_UPTO_9K 9234 255 256 #define MAXIMUM_MTU 9000 257 #define DEFAULT_MTU ETHERMTU 258 259 #define DEFAULT_FRAME_SIZE \ 260 (DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 261 #define MAXIMUM_FRAME_SIZE \ 262 (MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 263 264 #define E1000_LSO_MAXLEN 65535 265 266 /* Defines for Tx stall check */ 267 #define E1000G_STALL_WATCHDOG_COUNT 8 268 269 #define MAX_TX_LINK_DOWN_TIMEOUT 8 270 271 /* Defines for DVMA */ 272 #ifdef __sparc 273 #define E1000G_DEFAULT_DVMA_PAGE_NUM 2 274 #endif 275 276 /* 277 * Loopback definitions 278 */ 279 #define E1000G_LB_NONE 0 280 #define E1000G_LB_EXTERNAL_1000 1 281 #define E1000G_LB_EXTERNAL_100 2 282 #define E1000G_LB_EXTERNAL_10 3 283 #define E1000G_LB_INTERNAL_PHY 4 284 285 /* 286 * Private dip list definitions 287 */ 288 #define E1000G_PRIV_DEVI_ATTACH 0x0 289 #define E1000G_PRIV_DEVI_DETACH 0x1 290 291 /* 292 * Tx descriptor LENGTH field mask 293 */ 294 #define E1000G_TBD_LENGTH_MASK 0x000fffff 295 296 /* 297 * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. 298 */ 299 #define QUEUE_INIT_LIST(_LH) \ 300 (_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0 301 302 /* 303 * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty. 304 */ 305 #define IS_QUEUE_EMPTY(_LH) \ 306 ((_LH)->Flink == (PSINGLE_LIST_LINK)0) 307 308 /* 309 * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does 310 * not remove the head from the queue. 311 */ 312 #define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink)) 313 314 /* 315 * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue. 316 */ 317 #define QUEUE_REMOVE_HEAD(_LH) \ 318 { \ 319 PSINGLE_LIST_LINK ListElem; \ 320 if (ListElem = (_LH)->Flink) \ 321 { \ 322 if (!((_LH)->Flink = ListElem->Flink)) \ 323 (_LH)->Blink = (PSINGLE_LIST_LINK) 0; \ 324 } \ 325 } 326 327 /* 328 * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list), 329 * and return it (this differs from QUEUE_REMOVE_HEAD only in 330 * the 1st line). 331 */ 332 #define QUEUE_POP_HEAD(_LH) \ 333 (PSINGLE_LIST_LINK)(_LH)->Flink; \ 334 { \ 335 PSINGLE_LIST_LINK ListElem; \ 336 ListElem = (_LH)->Flink; \ 337 if (ListElem) \ 338 { \ 339 (_LH)->Flink = ListElem->Flink; \ 340 if (!(_LH)->Flink) \ 341 (_LH)->Blink = (PSINGLE_LIST_LINK)0; \ 342 } \ 343 } 344 345 /* 346 * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not 347 * remove the tail from the queue. 348 */ 349 #define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink)) 350 351 /* 352 * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue 353 */ 354 #define QUEUE_PUSH_TAIL(_LH, _E) \ 355 if ((_LH)->Blink) \ 356 { \ 357 ((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \ 358 (PSINGLE_LIST_LINK)(_E); \ 359 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 360 } else { \ 361 (_LH)->Flink = \ 362 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 363 } \ 364 (_E)->Flink = (PSINGLE_LIST_LINK)0; 365 366 /* 367 * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue. 368 */ 369 #define QUEUE_PUSH_HEAD(_LH, _E) \ 370 if (!((_E)->Flink = (_LH)->Flink)) \ 371 { \ 372 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 373 } \ 374 (_LH)->Flink = (PSINGLE_LIST_LINK)(_E); 375 376 /* 377 * QUEUE_GET_NEXT -- Macro which returns the next element linked to the 378 * current element. 379 */ 380 #define QUEUE_GET_NEXT(_LH, _E) \ 381 (PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \ 382 (0) : ((_E)->Flink)) 383 384 /* 385 * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue 386 */ 387 #define QUEUE_APPEND(_LH1, _LH2) \ 388 if ((_LH2)->Flink) { \ 389 if ((_LH1)->Flink) { \ 390 ((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \ 391 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 392 } else { \ 393 (_LH1)->Flink = \ 394 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 395 } \ 396 (_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \ 397 } 398 399 400 #define QUEUE_SWITCH(_LH1, _LH2) \ 401 if ((_LH2)->Flink) { \ 402 (_LH1)->Flink = (_LH2)->Flink; \ 403 (_LH1)->Blink = (_LH2)->Blink; \ 404 (_LH2)->Flink = (_LH2)->Blink = (PSINGLE_LIST_LINK)0; \ 405 } 406 407 /* 408 * Property lookups 409 */ 410 #define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 411 DDI_PROP_DONTPASS, (n)) 412 #define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 413 DDI_PROP_DONTPASS, (n), -1) 414 415 #ifdef E1000G_DEBUG 416 /* 417 * E1000G-specific ioctls ... 418 */ 419 #define E1000G_IOC ((((((('E' << 4) + '1') << 4) \ 420 + 'K') << 4) + 'G') << 4) 421 422 /* 423 * These diagnostic IOCTLS are enabled only in DEBUG drivers 424 */ 425 #define E1000G_IOC_REG_PEEK (E1000G_IOC | 1) 426 #define E1000G_IOC_REG_POKE (E1000G_IOC | 2) 427 #define E1000G_IOC_CHIP_RESET (E1000G_IOC | 3) 428 429 #define E1000G_PP_SPACE_REG 0 /* PCI memory space */ 430 #define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */ 431 432 typedef struct { 433 uint64_t pp_acc_size; /* It's 1, 2, 4 or 8 */ 434 uint64_t pp_acc_space; /* See #defines below */ 435 uint64_t pp_acc_offset; /* See regs definition */ 436 uint64_t pp_acc_data; /* output for peek */ 437 /* input for poke */ 438 } e1000g_peekpoke_t; 439 #endif /* E1000G_DEBUG */ 440 441 /* 442 * (Internal) return values from ioctl subroutines 443 */ 444 enum ioc_reply { 445 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 446 IOC_DONE, /* OK, reply sent */ 447 IOC_ACK, /* OK, just send ACK */ 448 IOC_REPLY /* OK, just send reply */ 449 }; 450 451 /* 452 * Named Data (ND) Parameter Management Structure 453 */ 454 typedef struct { 455 uint32_t ndp_info; 456 uint32_t ndp_min; 457 uint32_t ndp_max; 458 uint32_t ndp_val; 459 struct e1000g *ndp_instance; 460 char *ndp_name; 461 } nd_param_t; 462 463 /* 464 * The entry of the private dip list 465 */ 466 typedef struct _private_devi_list { 467 dev_info_t *priv_dip; 468 uint16_t flag; 469 struct _private_devi_list *next; 470 } private_devi_list_t; 471 472 /* 473 * A structure that points to the next entry in the queue. 474 */ 475 typedef struct _SINGLE_LIST_LINK { 476 struct _SINGLE_LIST_LINK *Flink; 477 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK; 478 479 /* 480 * A "ListHead" structure that points to the head and tail of a queue 481 */ 482 typedef struct _LIST_DESCRIBER { 483 struct _SINGLE_LIST_LINK *volatile Flink; 484 struct _SINGLE_LIST_LINK *volatile Blink; 485 } LIST_DESCRIBER, *PLIST_DESCRIBER; 486 487 /* 488 * Address-Length pair structure that stores descriptor info 489 */ 490 typedef struct _sw_desc { 491 uint64_t address; 492 uint32_t length; 493 } sw_desc_t, *p_sw_desc_t; 494 495 typedef struct _desc_array { 496 sw_desc_t descriptor[4]; 497 uint32_t elements; 498 } desc_array_t, *p_desc_array_t; 499 500 typedef enum { 501 USE_NONE, 502 USE_BCOPY, 503 USE_DVMA, 504 USE_DMA 505 } dma_type_t; 506 507 typedef enum { 508 E1000G_STOP, 509 E1000G_START, 510 E1000G_ERROR 511 } chip_state_t; 512 513 typedef struct _dma_buffer { 514 caddr_t address; 515 uint64_t dma_address; 516 ddi_acc_handle_t acc_handle; 517 ddi_dma_handle_t dma_handle; 518 size_t size; 519 size_t len; 520 } dma_buffer_t, *p_dma_buffer_t; 521 522 /* 523 * Transmit Control Block (TCB), Ndis equiv of SWPacket This 524 * structure stores the additional information that is 525 * associated with every packet to be transmitted. It stores the 526 * message block pointer and the TBD addresses associated with 527 * the m_blk and also the link to the next tcb in the chain 528 */ 529 typedef struct _tx_sw_packet { 530 /* Link to the next tx_sw_packet in the list */ 531 SINGLE_LIST_LINK Link; 532 mblk_t *mp; 533 uint32_t num_desc; 534 uint32_t num_mblk_frag; 535 dma_type_t dma_type; 536 dma_type_t data_transfer_type; 537 ddi_dma_handle_t tx_dma_handle; 538 dma_buffer_t tx_buf[1]; 539 sw_desc_t desc[MAX_TX_DESC_PER_PACKET]; 540 } tx_sw_packet_t, *p_tx_sw_packet_t; 541 542 /* 543 * This structure is similar to the rx_sw_packet structure used 544 * for Ndis. This structure stores information about the 2k 545 * aligned receive buffer into which the FX1000 DMA's frames. 546 * This structure is maintained as a linked list of many 547 * receiver buffer pointers. 548 */ 549 typedef struct _rx_sw_packet { 550 /* Link to the next rx_sw_packet_t in the list */ 551 SINGLE_LIST_LINK Link; 552 struct _rx_sw_packet *next; 553 uint16_t flag; 554 mblk_t *mp; 555 caddr_t rx_ring; 556 dma_type_t dma_type; 557 frtn_t free_rtn; 558 dma_buffer_t rx_buf[1]; 559 } rx_sw_packet_t, *p_rx_sw_packet_t; 560 561 typedef struct _mblk_list { 562 mblk_t *head; 563 mblk_t *tail; 564 } mblk_list_t, *p_mblk_list_t; 565 566 typedef struct _context_data { 567 uint32_t ether_header_size; 568 uint32_t cksum_flags; 569 uint32_t cksum_start; 570 uint32_t cksum_stuff; 571 uint16_t mss; 572 uint8_t hdr_len; 573 uint32_t pay_len; 574 boolean_t lso_flag; 575 } context_data_t; 576 577 typedef union _e1000g_ether_addr { 578 struct { 579 uint32_t high; 580 uint32_t low; 581 } reg; 582 struct { 583 uint8_t set; 584 uint8_t redundant; 585 uint8_t addr[ETHERADDRL]; 586 } mac; 587 } e1000g_ether_addr_t; 588 589 typedef struct _e1000g_stat { 590 591 kstat_named_t link_speed; /* Link Speed */ 592 kstat_named_t reset_count; /* Reset Count */ 593 594 kstat_named_t rx_error; /* Rx Error in Packet */ 595 kstat_named_t rx_esballoc_fail; /* Rx Desballoc Failure */ 596 kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ 597 598 kstat_named_t tx_no_desc; /* Tx No Desc */ 599 kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ 600 kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ 601 kstat_named_t tx_over_size; /* Tx Pkt Too Long */ 602 kstat_named_t tx_reschedule; /* Tx Reschedule */ 603 604 #ifdef E1000G_DEBUG 605 kstat_named_t rx_none; /* Rx No Incoming Data */ 606 kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */ 607 kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */ 608 kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */ 609 610 kstat_named_t tx_under_size; /* Tx Packet Under Size */ 611 kstat_named_t tx_empty_frags; /* Tx Empty Frags */ 612 kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */ 613 kstat_named_t tx_recycle; /* Tx Recycle */ 614 kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ 615 kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */ 616 kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */ 617 kstat_named_t tx_copy; /* Tx Send Copy */ 618 kstat_named_t tx_bind; /* Tx Send Bind */ 619 kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */ 620 kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ 621 kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ 622 #endif 623 624 kstat_named_t Crcerrs; /* CRC Error Count */ 625 kstat_named_t Symerrs; /* Symbol Error Count */ 626 kstat_named_t Mpc; /* Missed Packet Count */ 627 kstat_named_t Scc; /* Single Collision Count */ 628 kstat_named_t Ecol; /* Excessive Collision Count */ 629 kstat_named_t Mcc; /* Multiple Collision Count */ 630 kstat_named_t Latecol; /* Late Collision Count */ 631 kstat_named_t Colc; /* Collision Count */ 632 kstat_named_t Dc; /* Defer Count */ 633 kstat_named_t Sec; /* Sequence Error Count */ 634 kstat_named_t Rlec; /* Receive Length Error Count */ 635 kstat_named_t Xonrxc; /* XON Received Count */ 636 kstat_named_t Xontxc; /* XON Xmitted Count */ 637 kstat_named_t Xoffrxc; /* XOFF Received Count */ 638 kstat_named_t Xofftxc; /* Xoff Xmitted Count */ 639 kstat_named_t Fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 640 #ifdef E1000G_DEBUG 641 kstat_named_t Prc64; /* Packets Received - 64b */ 642 kstat_named_t Prc127; /* Packets Received - 65-127b */ 643 kstat_named_t Prc255; /* Packets Received - 127-255b */ 644 kstat_named_t Prc511; /* Packets Received - 256-511b */ 645 kstat_named_t Prc1023; /* Packets Received - 511-1023b */ 646 kstat_named_t Prc1522; /* Packets Received - 1024-1522b */ 647 #endif 648 kstat_named_t Gprc; /* Good Packets Received Count */ 649 kstat_named_t Bprc; /* Broadcasts Pkts Received Count */ 650 kstat_named_t Mprc; /* Multicast Pkts Received Count */ 651 kstat_named_t Gptc; /* Good Packets Xmitted Count */ 652 kstat_named_t Gorl; /* Good Octets Recvd Lo Count */ 653 kstat_named_t Gorh; /* Good Octets Recvd Hi Count */ 654 kstat_named_t Gotl; /* Good Octets Xmitd Lo Count */ 655 kstat_named_t Goth; /* Good Octets Xmitd Hi Count */ 656 kstat_named_t Rnbc; /* Receive No Buffers Count */ 657 kstat_named_t Ruc; /* Receive Undersize Count */ 658 kstat_named_t Rfc; /* Receive Frag Count */ 659 kstat_named_t Roc; /* Receive Oversize Count */ 660 kstat_named_t Rjc; /* Receive Jabber Count */ 661 kstat_named_t Torl; /* Total Octets Recvd Lo Count */ 662 kstat_named_t Torh; /* Total Octets Recvd Hi Count */ 663 kstat_named_t Totl; /* Total Octets Xmted Lo Count */ 664 kstat_named_t Toth; /* Total Octets Xmted Hi Count */ 665 kstat_named_t Tpr; /* Total Packets Received */ 666 kstat_named_t Tpt; /* Total Packets Xmitted */ 667 #ifdef E1000G_DEBUG 668 kstat_named_t Ptc64; /* Packets Xmitted (64b) */ 669 kstat_named_t Ptc127; /* Packets Xmitted (64-127b) */ 670 kstat_named_t Ptc255; /* Packets Xmitted (128-255b) */ 671 kstat_named_t Ptc511; /* Packets Xmitted (255-511b) */ 672 kstat_named_t Ptc1023; /* Packets Xmitted (512-1023b) */ 673 kstat_named_t Ptc1522; /* Packets Xmitted (1024-1522b */ 674 #endif 675 kstat_named_t Mptc; /* Multicast Packets Xmited Count */ 676 kstat_named_t Bptc; /* Broadcast Packets Xmited Count */ 677 kstat_named_t Algnerrc; /* Alignment Error count */ 678 kstat_named_t Tuc; /* Transmit Underrun count */ 679 kstat_named_t Rxerrc; /* Rx Error Count */ 680 kstat_named_t Tncrs; /* Transmit with no CRS */ 681 kstat_named_t Cexterr; /* Carrier Extension Error count */ 682 kstat_named_t Rutec; /* Receive DMA too Early count */ 683 kstat_named_t Tsctc; /* TCP seg contexts xmit count */ 684 kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */ 685 } e1000g_stat_t, *p_e1000g_stat_t; 686 687 typedef struct _e1000g_tx_ring { 688 kmutex_t tx_lock; 689 kmutex_t freelist_lock; 690 kmutex_t usedlist_lock; 691 /* 692 * Descriptor queue definitions 693 */ 694 ddi_dma_handle_t tbd_dma_handle; 695 ddi_acc_handle_t tbd_acc_handle; 696 struct e1000_tx_desc *tbd_area; 697 uint64_t tbd_dma_addr; 698 struct e1000_tx_desc *tbd_first; 699 struct e1000_tx_desc *tbd_last; 700 struct e1000_tx_desc *tbd_oldest; 701 struct e1000_tx_desc *tbd_next; 702 uint32_t tbd_avail; 703 /* 704 * Software packet structures definitions 705 */ 706 p_tx_sw_packet_t packet_area; 707 LIST_DESCRIBER used_list; 708 LIST_DESCRIBER free_list; 709 /* 710 * TCP/UDP Context Data Information 711 */ 712 context_data_t pre_context; 713 /* 714 * Timer definitions for 82547 715 */ 716 timeout_id_t timer_id_82547; 717 boolean_t timer_enable_82547; 718 /* 719 * reschedule when tx resource is available 720 */ 721 boolean_t resched_needed; 722 clock_t resched_timestamp; 723 uint32_t stall_watchdog; 724 uint32_t recycle_fail; 725 mblk_list_t mblks; 726 /* 727 * Statistics 728 */ 729 uint32_t stat_no_swpkt; 730 uint32_t stat_no_desc; 731 uint32_t stat_send_fail; 732 uint32_t stat_reschedule; 733 uint32_t stat_timer_reschedule; 734 uint32_t stat_over_size; 735 #ifdef E1000G_DEBUG 736 uint32_t stat_under_size; 737 uint32_t stat_exceed_frags; 738 uint32_t stat_empty_frags; 739 uint32_t stat_recycle; 740 uint32_t stat_recycle_intr; 741 uint32_t stat_recycle_retry; 742 uint32_t stat_recycle_none; 743 uint32_t stat_copy; 744 uint32_t stat_bind; 745 uint32_t stat_multi_copy; 746 uint32_t stat_multi_cookie; 747 uint32_t stat_lack_desc; 748 uint32_t stat_lso_header_fail; 749 #endif 750 /* 751 * Pointer to the adapter 752 */ 753 struct e1000g *adapter; 754 } e1000g_tx_ring_t, *pe1000g_tx_ring_t; 755 756 typedef struct _e1000g_rx_ring { 757 kmutex_t rx_lock; 758 kmutex_t freelist_lock; 759 kmutex_t recycle_lock; 760 /* 761 * Descriptor queue definitions 762 */ 763 ddi_dma_handle_t rbd_dma_handle; 764 ddi_acc_handle_t rbd_acc_handle; 765 struct e1000_rx_desc *rbd_area; 766 uint64_t rbd_dma_addr; 767 struct e1000_rx_desc *rbd_first; 768 struct e1000_rx_desc *rbd_last; 769 struct e1000_rx_desc *rbd_next; 770 /* 771 * Software packet structures definitions 772 */ 773 p_rx_sw_packet_t packet_area; 774 LIST_DESCRIBER recv_list; 775 LIST_DESCRIBER free_list; 776 LIST_DESCRIBER recycle_list; 777 778 p_rx_sw_packet_t pending_list; 779 uint32_t pending_count; 780 uint32_t avail_freepkt; 781 uint32_t recycle_freepkt; 782 uint32_t rx_mblk_len; 783 mblk_t *rx_mblk; 784 mblk_t *rx_mblk_tail; 785 mac_ring_handle_t mrh; 786 mac_ring_handle_t mrh_init; 787 uint64_t ring_gen_num; 788 mblk_t *poll_list_head; 789 mblk_t *poll_list_tail; 790 uint_t poll_list_sz; 791 boolean_t poll_flag; 792 793 /* 794 * Statistics 795 */ 796 uint32_t stat_error; 797 uint32_t stat_esballoc_fail; 798 uint32_t stat_allocb_fail; 799 uint32_t stat_exceed_pkt; 800 #ifdef E1000G_DEBUG 801 uint32_t stat_none; 802 uint32_t stat_multi_desc; 803 uint32_t stat_no_freepkt; 804 #endif 805 /* 806 * Pointer to the adapter 807 */ 808 struct e1000g *adapter; 809 } e1000g_rx_ring_t, *pe1000g_rx_ring_t; 810 811 typedef struct e1000g { 812 int instance; 813 dev_info_t *dip; 814 dev_info_t *priv_dip; 815 mac_handle_t mh; 816 mac_resource_handle_t mrh; 817 struct e1000_hw shared; 818 struct e1000g_osdep osdep; 819 820 chip_state_t chip_state; 821 boolean_t e1000g_promisc; 822 boolean_t strip_crc; 823 boolean_t rx_buffer_setup; 824 boolean_t esb2_workaround; 825 link_state_t link_state; 826 uint32_t link_speed; 827 uint32_t link_duplex; 828 uint32_t master_latency_timer; 829 uint32_t smartspeed; /* smartspeed w/a counter */ 830 uint32_t init_count; 831 uint32_t reset_count; 832 uint32_t attach_progress; /* attach tracking */ 833 uint32_t loopback_mode; 834 835 uint32_t tx_desc_num; 836 uint32_t tx_freelist_num; 837 uint32_t rx_desc_num; 838 uint32_t rx_freelist_num; 839 uint32_t tx_buffer_size; 840 uint32_t rx_buffer_size; 841 842 uint32_t tx_link_down_timeout; 843 uint32_t tx_bcopy_thresh; 844 uint32_t rx_limit_onintr; 845 uint32_t rx_bcopy_thresh; 846 uint32_t rx_buf_align; 847 uint32_t desc_align; 848 849 boolean_t intr_adaptive; 850 boolean_t tx_intr_enable; 851 uint32_t tx_intr_delay; 852 uint32_t tx_intr_abs_delay; 853 uint32_t rx_intr_delay; 854 uint32_t rx_intr_abs_delay; 855 uint32_t intr_throttling_rate; 856 857 uint32_t default_mtu; 858 uint32_t max_frame_size; 859 uint32_t min_frame_size; 860 861 boolean_t watchdog_timer_enabled; 862 boolean_t watchdog_timer_started; 863 timeout_id_t watchdog_tid; 864 boolean_t link_complete; 865 timeout_id_t link_tid; 866 867 e1000g_rx_ring_t rx_ring[1]; 868 e1000g_tx_ring_t tx_ring[1]; 869 mac_group_handle_t rx_group; 870 871 kmutex_t gen_lock; /* General lock for the whole struct e1000g */ 872 873 /* 874 * Rx and Tx packet count for interrupt adaptive setting 875 */ 876 uint32_t rx_pkt_cnt; 877 uint32_t tx_pkt_cnt; 878 879 /* 880 * The watchdog_lock must be held when updateing the 881 * timeout fields in struct e1000g, that is, 882 * watchdog_tid, watchdog_timer_started. 883 */ 884 kmutex_t watchdog_lock; 885 /* 886 * The link_lock protects the link fields in struct e1000g, 887 * such as link_state, link_speed, link_duplex, link_complete, and 888 * link_tid. 889 */ 890 kmutex_t link_lock; 891 /* 892 * The chip_lock assures that the Rx/Tx process must be 893 * stopped while other functions change the hardware 894 * configuration of e1000g card, such as e1000g_reset(), 895 * e1000g_reset_hw() etc are executed. 896 */ 897 krwlock_t chip_lock; 898 899 boolean_t unicst_init; 900 uint32_t unicst_avail; 901 uint32_t unicst_total; 902 e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 903 904 uint32_t mcast_count; 905 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 906 907 ulong_t sys_page_sz; 908 #ifdef __sparc 909 uint_t dvma_page_num; 910 #endif 911 912 boolean_t msi_enable; 913 boolean_t tx_hcksum_enable; 914 boolean_t lso_enable; 915 boolean_t lso_premature_issue; 916 boolean_t mem_workaround_82546; 917 int intr_type; 918 int intr_cnt; 919 int intr_cap; 920 size_t intr_size; 921 uint_t intr_pri; 922 ddi_intr_handle_t *htable; 923 924 int tx_softint_pri; 925 ddi_softint_handle_t tx_softint_handle; 926 927 kstat_t *e1000g_ksp; 928 929 boolean_t poll_mode; 930 931 uint16_t phy_ctrl; /* contents of PHY_CTRL */ 932 uint16_t phy_status; /* contents of PHY_STATUS */ 933 uint16_t phy_an_adv; /* contents of PHY_AUTONEG_ADV */ 934 uint16_t phy_an_exp; /* contents of PHY_AUTONEG_EXP */ 935 uint16_t phy_ext_status; /* contents of PHY_EXT_STATUS */ 936 uint16_t phy_1000t_ctrl; /* contents of PHY_1000T_CTRL */ 937 uint16_t phy_1000t_status; /* contents of PHY_1000T_STATUS */ 938 uint16_t phy_lp_able; /* contents of PHY_LP_ABILITY */ 939 940 /* 941 * FMA capabilities 942 */ 943 int fm_capabilities; 944 945 uint32_t param_en_1000fdx:1, 946 param_en_1000hdx:1, 947 param_en_100fdx:1, 948 param_en_100hdx:1, 949 param_en_10fdx:1, 950 param_en_10hdx:1, 951 param_autoneg_cap:1, 952 param_pause_cap:1, 953 param_asym_pause_cap:1, 954 param_1000fdx_cap:1, 955 param_1000hdx_cap:1, 956 param_100t4_cap:1, 957 param_100fdx_cap:1, 958 param_100hdx_cap:1, 959 param_10fdx_cap:1, 960 param_10hdx_cap:1, 961 param_adv_autoneg:1, 962 param_adv_pause:1, 963 param_adv_asym_pause:1, 964 param_adv_1000fdx:1, 965 param_adv_1000hdx:1, 966 param_adv_100t4:1, 967 param_adv_100fdx:1, 968 param_adv_100hdx:1, 969 param_adv_10fdx:1, 970 param_adv_10hdx:1, 971 param_lp_autoneg:1, 972 param_lp_pause:1, 973 param_lp_asym_pause:1, 974 param_lp_1000fdx:1, 975 param_lp_1000hdx:1, 976 param_lp_100t4:1; 977 978 uint32_t param_lp_100fdx:1, 979 param_lp_100hdx:1, 980 param_lp_10fdx:1, 981 param_lp_10hdx:1, 982 param_pad_to_32:28; 983 984 } e1000g_t; 985 986 987 /* 988 * Function prototypes 989 */ 990 int e1000g_alloc_dma_resources(struct e1000g *Adapter); 991 void e1000g_release_dma_resources(struct e1000g *Adapter); 992 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet); 993 void e1000g_tx_setup(struct e1000g *Adapter); 994 void e1000g_rx_setup(struct e1000g *Adapter); 995 void e1000g_setup_multicast(struct e1000g *Adapter); 996 997 int e1000g_recycle(e1000g_tx_ring_t *tx_ring); 998 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet); 999 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring); 1000 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2); 1001 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp); 1002 mblk_t *e1000g_receive(e1000g_rx_ring_t *rx_ring, mblk_t **tail, uint_t *sz); 1003 void e1000g_rxfree_func(p_rx_sw_packet_t packet); 1004 1005 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val); 1006 int e1000g_init_stats(struct e1000g *Adapter); 1007 void e1000_tbi_adjust_stats(struct e1000g *Adapter, 1008 uint32_t frame_len, uint8_t *mac_addr); 1009 1010 void e1000g_clear_interrupt(struct e1000g *Adapter); 1011 void e1000g_mask_interrupt(struct e1000g *Adapter); 1012 void e1000g_clear_all_interrupts(struct e1000g *Adapter); 1013 void e1000g_clear_tx_interrupt(struct e1000g *Adapter); 1014 void e1000g_mask_tx_interrupt(struct e1000g *Adapter); 1015 void phy_spd_state(struct e1000_hw *hw, boolean_t enable); 1016 void e1000_enable_pciex_master(struct e1000_hw *hw); 1017 int e1000g_check_acc_handle(ddi_acc_handle_t handle); 1018 int e1000g_check_dma_handle(ddi_dma_handle_t handle); 1019 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail); 1020 void e1000g_set_fma_flags(struct e1000g *Adapter, int acc_flag, int dma_flag); 1021 int e1000g_reset_link(struct e1000g *Adapter); 1022 1023 /* 1024 * Global variables 1025 */ 1026 extern boolean_t e1000g_force_detach; 1027 extern uint32_t e1000g_mblks_pending; 1028 extern krwlock_t e1000g_rx_detach_lock; 1029 extern private_devi_list_t *e1000g_private_devi_list; 1030 extern int e1000g_poll_mode; 1031 1032 #ifdef __cplusplus 1033 } 1034 #endif 1035 1036 #endif /* _E1000G_SW_H */ 1037