1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet"; 48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 49 static char e1000g_version[] = "Driver Ver. 5.3.19"; 50 51 /* 52 * Proto types for DDI entry points 53 */ 54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 56 static int e1000g_quiesce(dev_info_t *); 57 58 /* 59 * init and intr routines prototype 60 */ 61 static int e1000g_resume(dev_info_t *); 62 static int e1000g_suspend(dev_info_t *); 63 static uint_t e1000g_intr_pciexpress(caddr_t); 64 static uint_t e1000g_intr(caddr_t); 65 static void e1000g_intr_work(struct e1000g *, uint32_t); 66 #pragma inline(e1000g_intr_work) 67 static int e1000g_init(struct e1000g *); 68 static int e1000g_start(struct e1000g *, boolean_t); 69 static void e1000g_stop(struct e1000g *, boolean_t); 70 static int e1000g_m_start(void *); 71 static void e1000g_m_stop(void *); 72 static int e1000g_m_promisc(void *, boolean_t); 73 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 74 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 75 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 76 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 77 uint_t, const void *); 78 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 79 uint_t, uint_t, void *, uint_t *); 80 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 81 const void *); 82 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 83 uint_t, void *, uint_t *); 84 static void e1000g_init_locks(struct e1000g *); 85 static void e1000g_destroy_locks(struct e1000g *); 86 static int e1000g_identify_hardware(struct e1000g *); 87 static int e1000g_regs_map(struct e1000g *); 88 static int e1000g_set_driver_params(struct e1000g *); 89 static void e1000g_set_bufsize(struct e1000g *); 90 static int e1000g_register_mac(struct e1000g *); 91 static boolean_t e1000g_rx_drain(struct e1000g *); 92 static boolean_t e1000g_tx_drain(struct e1000g *); 93 static void e1000g_init_unicst(struct e1000g *); 94 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int); 95 static int e1000g_alloc_rx_data(struct e1000g *); 96 static void e1000g_release_multicast(struct e1000g *); 97 static void e1000g_pch_limits(struct e1000g *); 98 static uint32_t e1000g_mtu2maxframe(uint32_t); 99 100 /* 101 * Local routines 102 */ 103 static boolean_t e1000g_reset_adapter(struct e1000g *); 104 static void e1000g_tx_clean(struct e1000g *); 105 static void e1000g_rx_clean(struct e1000g *); 106 static void e1000g_link_timer(void *); 107 static void e1000g_local_timer(void *); 108 static boolean_t e1000g_link_check(struct e1000g *); 109 static boolean_t e1000g_stall_check(struct e1000g *); 110 static void e1000g_smartspeed(struct e1000g *); 111 static void e1000g_get_conf(struct e1000g *); 112 static boolean_t e1000g_get_prop(struct e1000g *, char *, int, int, int, 113 int *); 114 static void enable_watchdog_timer(struct e1000g *); 115 static void disable_watchdog_timer(struct e1000g *); 116 static void start_watchdog_timer(struct e1000g *); 117 static void restart_watchdog_timer(struct e1000g *); 118 static void stop_watchdog_timer(struct e1000g *); 119 static void stop_link_timer(struct e1000g *); 120 static void stop_82547_timer(e1000g_tx_ring_t *); 121 static void e1000g_force_speed_duplex(struct e1000g *); 122 static void e1000g_setup_max_mtu(struct e1000g *); 123 static void e1000g_get_max_frame_size(struct e1000g *); 124 static boolean_t is_valid_mac_addr(uint8_t *); 125 static void e1000g_unattach(dev_info_t *, struct e1000g *); 126 #ifdef E1000G_DEBUG 127 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 128 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 129 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 130 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 131 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 132 struct iocblk *, mblk_t *); 133 #endif 134 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 135 struct iocblk *, mblk_t *); 136 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 137 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 138 static void e1000g_set_internal_loopback(struct e1000g *); 139 static void e1000g_set_external_loopback_1000(struct e1000g *); 140 static void e1000g_set_external_loopback_100(struct e1000g *); 141 static void e1000g_set_external_loopback_10(struct e1000g *); 142 static int e1000g_add_intrs(struct e1000g *); 143 static int e1000g_intr_add(struct e1000g *, int); 144 static int e1000g_rem_intrs(struct e1000g *); 145 static int e1000g_enable_intrs(struct e1000g *); 146 static int e1000g_disable_intrs(struct e1000g *); 147 static boolean_t e1000g_link_up(struct e1000g *); 148 #ifdef __sparc 149 static boolean_t e1000g_find_mac_address(struct e1000g *); 150 #endif 151 static void e1000g_get_phy_state(struct e1000g *); 152 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 153 const void *impl_data); 154 static void e1000g_fm_init(struct e1000g *Adapter); 155 static void e1000g_fm_fini(struct e1000g *Adapter); 156 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 157 static void e1000g_param_sync(struct e1000g *); 158 static void e1000g_get_driver_control(struct e1000_hw *); 159 static void e1000g_release_driver_control(struct e1000_hw *); 160 static void e1000g_restore_promisc(struct e1000g *Adapter); 161 162 mac_priv_prop_t e1000g_priv_props[] = { 163 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 164 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 165 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 166 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 167 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 168 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 169 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 170 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 171 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 172 {"_intr_adaptive", MAC_PROP_PERM_RW}, 173 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 174 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 175 }; 176 #define E1000G_MAX_PRIV_PROPS \ 177 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 178 179 180 static struct cb_ops cb_ws_ops = { 181 nulldev, /* cb_open */ 182 nulldev, /* cb_close */ 183 nodev, /* cb_strategy */ 184 nodev, /* cb_print */ 185 nodev, /* cb_dump */ 186 nodev, /* cb_read */ 187 nodev, /* cb_write */ 188 nodev, /* cb_ioctl */ 189 nodev, /* cb_devmap */ 190 nodev, /* cb_mmap */ 191 nodev, /* cb_segmap */ 192 nochpoll, /* cb_chpoll */ 193 ddi_prop_op, /* cb_prop_op */ 194 NULL, /* cb_stream */ 195 D_MP | D_HOTPLUG, /* cb_flag */ 196 CB_REV, /* cb_rev */ 197 nodev, /* cb_aread */ 198 nodev /* cb_awrite */ 199 }; 200 201 static struct dev_ops ws_ops = { 202 DEVO_REV, /* devo_rev */ 203 0, /* devo_refcnt */ 204 NULL, /* devo_getinfo */ 205 nulldev, /* devo_identify */ 206 nulldev, /* devo_probe */ 207 e1000g_attach, /* devo_attach */ 208 e1000g_detach, /* devo_detach */ 209 nodev, /* devo_reset */ 210 &cb_ws_ops, /* devo_cb_ops */ 211 NULL, /* devo_bus_ops */ 212 ddi_power, /* devo_power */ 213 e1000g_quiesce /* devo_quiesce */ 214 }; 215 216 static struct modldrv modldrv = { 217 &mod_driverops, /* Type of module. This one is a driver */ 218 ident, /* Discription string */ 219 &ws_ops, /* driver ops */ 220 }; 221 222 static struct modlinkage modlinkage = { 223 MODREV_1, &modldrv, NULL 224 }; 225 226 /* Access attributes for register mapping */ 227 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 228 DDI_DEVICE_ATTR_V1, 229 DDI_STRUCTURE_LE_ACC, 230 DDI_STRICTORDER_ACC, 231 DDI_FLAGERR_ACC 232 }; 233 234 #define E1000G_M_CALLBACK_FLAGS \ 235 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 236 237 static mac_callbacks_t e1000g_m_callbacks = { 238 E1000G_M_CALLBACK_FLAGS, 239 e1000g_m_stat, 240 e1000g_m_start, 241 e1000g_m_stop, 242 e1000g_m_promisc, 243 e1000g_m_multicst, 244 NULL, 245 e1000g_m_tx, 246 e1000g_m_ioctl, 247 e1000g_m_getcapab, 248 NULL, 249 NULL, 250 e1000g_m_setprop, 251 e1000g_m_getprop 252 }; 253 254 /* 255 * Global variables 256 */ 257 uint32_t e1000g_mblks_pending = 0; 258 /* 259 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 260 * Here we maintain a private dev_info list if e1000g_force_detach is 261 * enabled. If we force the driver to detach while there are still some 262 * rx buffers retained in the upper layer, we have to keep a copy of the 263 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 264 * structure will be freed after the driver is detached. However when we 265 * finally free those rx buffers released by the upper layer, we need to 266 * refer to the dev_info to free the dma buffers. So we save a copy of 267 * the dev_info for this purpose. On x86 platform, we assume this copy 268 * of dev_info is always valid, but on SPARC platform, it could be invalid 269 * after the system board level DR operation. For this reason, the global 270 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 271 */ 272 #ifdef __sparc 273 boolean_t e1000g_force_detach = B_FALSE; 274 #else 275 boolean_t e1000g_force_detach = B_TRUE; 276 #endif 277 private_devi_list_t *e1000g_private_devi_list = NULL; 278 279 /* 280 * The mutex e1000g_rx_detach_lock is defined to protect the processing of 281 * the private dev_info list, and to serialize the processing of rx buffer 282 * freeing and rx buffer recycling. 283 */ 284 kmutex_t e1000g_rx_detach_lock; 285 /* 286 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 287 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 288 * If there are many e1000g instances, the system may run out of DVMA 289 * resources during the initialization of the instances, then the flag will 290 * be changed to "USE_DMA". Because different e1000g instances are initialized 291 * in parallel, we need to use this lock to protect the flag. 292 */ 293 krwlock_t e1000g_dma_type_lock; 294 295 /* 296 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 297 * Based on the information from Intel, the 82546 chipset has some hardware 298 * problem. When one port is being reset and the other port is trying to 299 * access the eeprom, it could cause system hang or panic. To workaround this 300 * hardware problem, we use a global mutex to prevent such operations from 301 * happening simultaneously on different instances. This workaround is applied 302 * to all the devices supported by this driver. 303 */ 304 kmutex_t e1000g_nvm_lock; 305 306 /* 307 * Loadable module configuration entry points for the driver 308 */ 309 310 /* 311 * _init - module initialization 312 */ 313 int 314 _init(void) 315 { 316 int status; 317 318 mac_init_ops(&ws_ops, WSNAME); 319 status = mod_install(&modlinkage); 320 if (status != DDI_SUCCESS) 321 mac_fini_ops(&ws_ops); 322 else { 323 mutex_init(&e1000g_rx_detach_lock, NULL, MUTEX_DRIVER, NULL); 324 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 325 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 326 } 327 328 return (status); 329 } 330 331 /* 332 * _fini - module finalization 333 */ 334 int 335 _fini(void) 336 { 337 int status; 338 339 if (e1000g_mblks_pending != 0) 340 return (EBUSY); 341 342 status = mod_remove(&modlinkage); 343 if (status == DDI_SUCCESS) { 344 mac_fini_ops(&ws_ops); 345 346 if (e1000g_force_detach) { 347 private_devi_list_t *devi_node; 348 349 mutex_enter(&e1000g_rx_detach_lock); 350 while (e1000g_private_devi_list != NULL) { 351 devi_node = e1000g_private_devi_list; 352 e1000g_private_devi_list = 353 e1000g_private_devi_list->next; 354 355 kmem_free(devi_node->priv_dip, 356 sizeof (struct dev_info)); 357 kmem_free(devi_node, 358 sizeof (private_devi_list_t)); 359 } 360 mutex_exit(&e1000g_rx_detach_lock); 361 } 362 363 mutex_destroy(&e1000g_rx_detach_lock); 364 rw_destroy(&e1000g_dma_type_lock); 365 mutex_destroy(&e1000g_nvm_lock); 366 } 367 368 return (status); 369 } 370 371 /* 372 * _info - module information 373 */ 374 int 375 _info(struct modinfo *modinfop) 376 { 377 return (mod_info(&modlinkage, modinfop)); 378 } 379 380 /* 381 * e1000g_attach - driver attach 382 * 383 * This function is the device-specific initialization entry 384 * point. This entry point is required and must be written. 385 * The DDI_ATTACH command must be provided in the attach entry 386 * point. When attach() is called with cmd set to DDI_ATTACH, 387 * all normal kernel services (such as kmem_alloc(9F)) are 388 * available for use by the driver. 389 * 390 * The attach() function will be called once for each instance 391 * of the device on the system with cmd set to DDI_ATTACH. 392 * Until attach() succeeds, the only driver entry points which 393 * may be called are open(9E) and getinfo(9E). 394 */ 395 static int 396 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 397 { 398 struct e1000g *Adapter; 399 struct e1000_hw *hw; 400 struct e1000g_osdep *osdep; 401 int instance; 402 403 switch (cmd) { 404 default: 405 e1000g_log(NULL, CE_WARN, 406 "Unsupported command send to e1000g_attach... "); 407 return (DDI_FAILURE); 408 409 case DDI_RESUME: 410 return (e1000g_resume(devinfo)); 411 412 case DDI_ATTACH: 413 break; 414 } 415 416 /* 417 * get device instance number 418 */ 419 instance = ddi_get_instance(devinfo); 420 421 /* 422 * Allocate soft data structure 423 */ 424 Adapter = 425 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 426 427 Adapter->dip = devinfo; 428 Adapter->instance = instance; 429 Adapter->tx_ring->adapter = Adapter; 430 Adapter->rx_ring->adapter = Adapter; 431 432 hw = &Adapter->shared; 433 osdep = &Adapter->osdep; 434 hw->back = osdep; 435 osdep->adapter = Adapter; 436 437 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 438 439 /* 440 * Initialize for fma support 441 */ 442 (void) e1000g_get_prop(Adapter, "fm-capable", 443 0, 0x0f, 444 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 445 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE, 446 &Adapter->fm_capabilities); 447 e1000g_fm_init(Adapter); 448 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 449 450 /* 451 * PCI Configure 452 */ 453 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 454 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 455 goto attach_fail; 456 } 457 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 458 459 /* 460 * Setup hardware 461 */ 462 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 463 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 464 goto attach_fail; 465 } 466 467 /* 468 * Map in the device registers. 469 */ 470 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 471 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 472 goto attach_fail; 473 } 474 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 475 476 /* 477 * Initialize driver parameters 478 */ 479 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 480 goto attach_fail; 481 } 482 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 483 484 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 485 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 486 goto attach_fail; 487 } 488 489 /* 490 * Initialize interrupts 491 */ 492 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 493 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 494 goto attach_fail; 495 } 496 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 497 498 /* 499 * Initialize mutex's for this device. 500 * Do this before enabling the interrupt handler and 501 * register the softint to avoid the condition where 502 * interrupt handler can try using uninitialized mutex 503 */ 504 e1000g_init_locks(Adapter); 505 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 506 507 /* 508 * Initialize Driver Counters 509 */ 510 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 511 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 512 goto attach_fail; 513 } 514 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 515 516 /* 517 * Initialize chip hardware and software structures 518 */ 519 rw_enter(&Adapter->chip_lock, RW_WRITER); 520 if (e1000g_init(Adapter) != DDI_SUCCESS) { 521 rw_exit(&Adapter->chip_lock); 522 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 523 goto attach_fail; 524 } 525 rw_exit(&Adapter->chip_lock); 526 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 527 528 /* 529 * Register the driver to the MAC 530 */ 531 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 532 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 533 goto attach_fail; 534 } 535 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 536 537 /* 538 * Now that mutex locks are initialized, and the chip is also 539 * initialized, enable interrupts. 540 */ 541 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 542 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 543 goto attach_fail; 544 } 545 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 546 547 /* 548 * If e1000g_force_detach is enabled, in global private dip list, 549 * we will create a new entry, which maintains the priv_dip for DR 550 * supports after driver detached. 551 */ 552 if (e1000g_force_detach) { 553 private_devi_list_t *devi_node; 554 555 Adapter->priv_dip = 556 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 557 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 558 sizeof (struct dev_info)); 559 560 devi_node = 561 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 562 563 mutex_enter(&e1000g_rx_detach_lock); 564 devi_node->priv_dip = Adapter->priv_dip; 565 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 566 devi_node->pending_rx_count = 0; 567 568 Adapter->priv_devi_node = devi_node; 569 570 if (e1000g_private_devi_list == NULL) { 571 devi_node->prev = NULL; 572 devi_node->next = NULL; 573 e1000g_private_devi_list = devi_node; 574 } else { 575 devi_node->prev = NULL; 576 devi_node->next = e1000g_private_devi_list; 577 e1000g_private_devi_list->prev = devi_node; 578 e1000g_private_devi_list = devi_node; 579 } 580 mutex_exit(&e1000g_rx_detach_lock); 581 } 582 583 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 584 Adapter->e1000g_state = E1000G_INITIALIZED; 585 586 return (DDI_SUCCESS); 587 588 attach_fail: 589 e1000g_unattach(devinfo, Adapter); 590 return (DDI_FAILURE); 591 } 592 593 static int 594 e1000g_register_mac(struct e1000g *Adapter) 595 { 596 struct e1000_hw *hw = &Adapter->shared; 597 mac_register_t *mac; 598 int err; 599 600 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 601 return (DDI_FAILURE); 602 603 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 604 mac->m_driver = Adapter; 605 mac->m_dip = Adapter->dip; 606 mac->m_src_addr = hw->mac.addr; 607 mac->m_callbacks = &e1000g_m_callbacks; 608 mac->m_min_sdu = 0; 609 mac->m_max_sdu = Adapter->default_mtu; 610 mac->m_margin = VLAN_TAGSZ; 611 mac->m_priv_props = e1000g_priv_props; 612 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 613 mac->m_v12n = MAC_VIRT_LEVEL1; 614 615 err = mac_register(mac, &Adapter->mh); 616 mac_free(mac); 617 618 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 619 } 620 621 static int 622 e1000g_identify_hardware(struct e1000g *Adapter) 623 { 624 struct e1000_hw *hw = &Adapter->shared; 625 struct e1000g_osdep *osdep = &Adapter->osdep; 626 627 /* Get the device id */ 628 hw->vendor_id = 629 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 630 hw->device_id = 631 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 632 hw->revision_id = 633 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 634 hw->subsystem_device_id = 635 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 636 hw->subsystem_vendor_id = 637 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 638 639 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 640 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 641 "MAC type could not be set properly."); 642 return (DDI_FAILURE); 643 } 644 645 return (DDI_SUCCESS); 646 } 647 648 static int 649 e1000g_regs_map(struct e1000g *Adapter) 650 { 651 dev_info_t *devinfo = Adapter->dip; 652 struct e1000_hw *hw = &Adapter->shared; 653 struct e1000g_osdep *osdep = &Adapter->osdep; 654 off_t mem_size; 655 656 /* Get size of adapter register memory */ 657 if (ddi_dev_regsize(devinfo, ADAPTER_REG_SET, &mem_size) != 658 DDI_SUCCESS) { 659 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 660 "ddi_dev_regsize for registers failed"); 661 return (DDI_FAILURE); 662 } 663 664 /* Map adapter register memory */ 665 if ((ddi_regs_map_setup(devinfo, ADAPTER_REG_SET, 666 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 667 &osdep->reg_handle)) != DDI_SUCCESS) { 668 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 669 "ddi_regs_map_setup for registers failed"); 670 goto regs_map_fail; 671 } 672 673 /* ICH needs to map flash memory */ 674 if (hw->mac.type == e1000_ich8lan || 675 hw->mac.type == e1000_ich9lan || 676 hw->mac.type == e1000_ich10lan || 677 hw->mac.type == e1000_pchlan) { 678 /* get flash size */ 679 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 680 &mem_size) != DDI_SUCCESS) { 681 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 682 "ddi_dev_regsize for ICH flash failed"); 683 goto regs_map_fail; 684 } 685 686 /* map flash in */ 687 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 688 (caddr_t *)&hw->flash_address, 0, 689 mem_size, &e1000g_regs_acc_attr, 690 &osdep->ich_flash_handle) != DDI_SUCCESS) { 691 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 692 "ddi_regs_map_setup for ICH flash failed"); 693 goto regs_map_fail; 694 } 695 } 696 697 return (DDI_SUCCESS); 698 699 regs_map_fail: 700 if (osdep->reg_handle != NULL) 701 ddi_regs_map_free(&osdep->reg_handle); 702 703 return (DDI_FAILURE); 704 } 705 706 static int 707 e1000g_set_driver_params(struct e1000g *Adapter) 708 { 709 struct e1000_hw *hw; 710 uint32_t mem_bar, io_bar, bar64; 711 712 hw = &Adapter->shared; 713 714 /* Set MAC type and initialize hardware functions */ 715 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 716 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 717 "Could not setup hardware functions"); 718 return (DDI_FAILURE); 719 } 720 721 /* Get bus information */ 722 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 723 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 724 "Could not get bus information"); 725 return (DDI_FAILURE); 726 } 727 728 /* get mem_base addr */ 729 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 730 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 731 732 /* get io_base addr */ 733 if (hw->mac.type >= e1000_82544) { 734 if (bar64) { 735 /* IO BAR is different for 64 bit BAR mode */ 736 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 737 PCI_CONF_BASE4); 738 } else { 739 /* normal 32-bit BAR mode */ 740 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 741 PCI_CONF_BASE2); 742 } 743 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 744 } else { 745 /* no I/O access for adapters prior to 82544 */ 746 hw->io_base = 0x0; 747 } 748 749 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 750 751 hw->mac.autoneg_failed = B_TRUE; 752 753 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 754 hw->phy.autoneg_wait_to_complete = B_FALSE; 755 756 /* Adaptive IFS related changes */ 757 hw->mac.adaptive_ifs = B_TRUE; 758 759 /* Enable phy init script for IGP phy of 82541/82547 */ 760 if ((hw->mac.type == e1000_82547) || 761 (hw->mac.type == e1000_82541) || 762 (hw->mac.type == e1000_82547_rev_2) || 763 (hw->mac.type == e1000_82541_rev_2)) 764 e1000_init_script_state_82541(hw, B_TRUE); 765 766 /* Enable the TTL workaround for 82541/82547 */ 767 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 768 769 #ifdef __sparc 770 Adapter->strip_crc = B_TRUE; 771 #else 772 Adapter->strip_crc = B_FALSE; 773 #endif 774 775 /* setup the maximum MTU size of the chip */ 776 e1000g_setup_max_mtu(Adapter); 777 778 /* Get speed/duplex settings in conf file */ 779 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 780 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 781 e1000g_force_speed_duplex(Adapter); 782 783 /* Get Jumbo Frames settings in conf file */ 784 e1000g_get_max_frame_size(Adapter); 785 786 /* Get conf file properties */ 787 e1000g_get_conf(Adapter); 788 789 /* enforce PCH limits */ 790 e1000g_pch_limits(Adapter); 791 792 /* Set Rx/Tx buffer size */ 793 e1000g_set_bufsize(Adapter); 794 795 /* Master Latency Timer */ 796 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 797 798 /* copper options */ 799 if (hw->phy.media_type == e1000_media_type_copper) { 800 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 801 hw->phy.disable_polarity_correction = B_FALSE; 802 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 803 } 804 805 /* The initial link state should be "unknown" */ 806 Adapter->link_state = LINK_STATE_UNKNOWN; 807 808 /* Initialize rx parameters */ 809 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 810 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 811 812 /* Initialize tx parameters */ 813 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 814 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 815 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 816 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 817 818 /* Initialize rx parameters */ 819 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 820 821 return (DDI_SUCCESS); 822 } 823 824 static void 825 e1000g_setup_max_mtu(struct e1000g *Adapter) 826 { 827 struct e1000_mac_info *mac = &Adapter->shared.mac; 828 struct e1000_phy_info *phy = &Adapter->shared.phy; 829 830 switch (mac->type) { 831 /* types that do not support jumbo frames */ 832 case e1000_ich8lan: 833 case e1000_82573: 834 case e1000_82583: 835 Adapter->max_mtu = ETHERMTU; 836 break; 837 /* ich9 supports jumbo frames except on one phy type */ 838 case e1000_ich9lan: 839 if (phy->type == e1000_phy_ife) 840 Adapter->max_mtu = ETHERMTU; 841 else 842 Adapter->max_mtu = MAXIMUM_MTU_9K; 843 break; 844 /* pch can do jumbo frames up to 4K */ 845 case e1000_pchlan: 846 Adapter->max_mtu = MAXIMUM_MTU_4K; 847 break; 848 /* types with a special limit */ 849 case e1000_82571: 850 case e1000_82572: 851 case e1000_82574: 852 case e1000_80003es2lan: 853 case e1000_ich10lan: 854 Adapter->max_mtu = MAXIMUM_MTU_9K; 855 break; 856 /* default limit is 16K */ 857 default: 858 Adapter->max_mtu = FRAME_SIZE_UPTO_16K - 859 sizeof (struct ether_vlan_header) - ETHERFCSL - 860 E1000G_IPALIGNPRESERVEROOM; 861 break; 862 } 863 } 864 865 static void 866 e1000g_set_bufsize(struct e1000g *Adapter) 867 { 868 struct e1000_mac_info *mac = &Adapter->shared.mac; 869 uint64_t rx_size; 870 uint64_t tx_size; 871 872 dev_info_t *devinfo = Adapter->dip; 873 #ifdef __sparc 874 ulong_t iommu_pagesize; 875 #endif 876 /* Get the system page size */ 877 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 878 879 #ifdef __sparc 880 iommu_pagesize = dvma_pagesize(devinfo); 881 if (iommu_pagesize != 0) { 882 if (Adapter->sys_page_sz == iommu_pagesize) { 883 if (iommu_pagesize > 0x4000) 884 Adapter->sys_page_sz = 0x4000; 885 } else { 886 if (Adapter->sys_page_sz > iommu_pagesize) 887 Adapter->sys_page_sz = iommu_pagesize; 888 } 889 } 890 if (Adapter->lso_enable) { 891 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 892 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 893 } else { 894 Adapter->dvma_page_num = Adapter->max_frame_size / 895 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 896 } 897 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 898 #endif 899 900 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 901 902 if (Adapter->mem_workaround_82546 && 903 ((mac->type == e1000_82545) || 904 (mac->type == e1000_82546) || 905 (mac->type == e1000_82546_rev_3))) { 906 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 907 } else { 908 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 909 if ((rx_size > FRAME_SIZE_UPTO_2K) && 910 (rx_size <= FRAME_SIZE_UPTO_4K)) 911 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 912 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 913 (rx_size <= FRAME_SIZE_UPTO_8K)) 914 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 915 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 916 (rx_size <= FRAME_SIZE_UPTO_16K)) 917 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 918 else 919 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 920 } 921 922 tx_size = Adapter->max_frame_size; 923 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 924 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 925 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 926 (tx_size <= FRAME_SIZE_UPTO_8K)) 927 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 928 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 929 (tx_size <= FRAME_SIZE_UPTO_16K)) 930 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 931 else 932 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 933 934 /* 935 * For Wiseman adapters we have an requirement of having receive 936 * buffers aligned at 256 byte boundary. Since Livengood does not 937 * require this and forcing it for all hardwares will have 938 * performance implications, I am making it applicable only for 939 * Wiseman and for Jumbo frames enabled mode as rest of the time, 940 * it is okay to have normal frames...but it does involve a 941 * potential risk where we may loose data if buffer is not 942 * aligned...so all wiseman boards to have 256 byte aligned 943 * buffers 944 */ 945 if (mac->type < e1000_82543) 946 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 947 else 948 Adapter->rx_buf_align = 1; 949 } 950 951 /* 952 * e1000g_detach - driver detach 953 * 954 * The detach() function is the complement of the attach routine. 955 * If cmd is set to DDI_DETACH, detach() is used to remove the 956 * state associated with a given instance of a device node 957 * prior to the removal of that instance from the system. 958 * 959 * The detach() function will be called once for each instance 960 * of the device for which there has been a successful attach() 961 * once there are no longer any opens on the device. 962 * 963 * Interrupts routine are disabled, All memory allocated by this 964 * driver are freed. 965 */ 966 static int 967 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 968 { 969 struct e1000g *Adapter; 970 boolean_t rx_drain; 971 972 switch (cmd) { 973 default: 974 return (DDI_FAILURE); 975 976 case DDI_SUSPEND: 977 return (e1000g_suspend(devinfo)); 978 979 case DDI_DETACH: 980 break; 981 } 982 983 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 984 if (Adapter == NULL) 985 return (DDI_FAILURE); 986 987 rx_drain = e1000g_rx_drain(Adapter); 988 if (!rx_drain && !e1000g_force_detach) 989 return (DDI_FAILURE); 990 991 if (mac_unregister(Adapter->mh) != 0) { 992 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 993 return (DDI_FAILURE); 994 } 995 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 996 997 ASSERT(!(Adapter->e1000g_state & E1000G_STARTED)); 998 999 if (!e1000g_force_detach && !rx_drain) 1000 return (DDI_FAILURE); 1001 1002 e1000g_unattach(devinfo, Adapter); 1003 1004 return (DDI_SUCCESS); 1005 } 1006 1007 /* 1008 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 1009 */ 1010 void 1011 e1000g_free_priv_devi_node(private_devi_list_t *devi_node) 1012 { 1013 ASSERT(e1000g_private_devi_list != NULL); 1014 ASSERT(devi_node != NULL); 1015 1016 if (devi_node->prev != NULL) 1017 devi_node->prev->next = devi_node->next; 1018 if (devi_node->next != NULL) 1019 devi_node->next->prev = devi_node->prev; 1020 if (devi_node == e1000g_private_devi_list) 1021 e1000g_private_devi_list = devi_node->next; 1022 1023 kmem_free(devi_node->priv_dip, 1024 sizeof (struct dev_info)); 1025 kmem_free(devi_node, 1026 sizeof (private_devi_list_t)); 1027 } 1028 1029 static void 1030 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1031 { 1032 private_devi_list_t *devi_node; 1033 int result; 1034 1035 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1036 (void) e1000g_disable_intrs(Adapter); 1037 } 1038 1039 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1040 (void) mac_unregister(Adapter->mh); 1041 } 1042 1043 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1044 (void) e1000g_rem_intrs(Adapter); 1045 } 1046 1047 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1048 (void) ddi_prop_remove_all(devinfo); 1049 } 1050 1051 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1052 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1053 } 1054 1055 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1056 stop_link_timer(Adapter); 1057 1058 mutex_enter(&e1000g_nvm_lock); 1059 result = e1000_reset_hw(&Adapter->shared); 1060 mutex_exit(&e1000g_nvm_lock); 1061 1062 if (result != E1000_SUCCESS) { 1063 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1064 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1065 } 1066 } 1067 1068 e1000g_release_multicast(Adapter); 1069 1070 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1071 if (Adapter->osdep.reg_handle != NULL) 1072 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1073 if (Adapter->osdep.ich_flash_handle != NULL) 1074 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1075 } 1076 1077 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1078 if (Adapter->osdep.cfg_handle != NULL) 1079 pci_config_teardown(&Adapter->osdep.cfg_handle); 1080 } 1081 1082 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1083 e1000g_destroy_locks(Adapter); 1084 } 1085 1086 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1087 e1000g_fm_fini(Adapter); 1088 } 1089 1090 mutex_enter(&e1000g_rx_detach_lock); 1091 if (e1000g_force_detach && (Adapter->priv_devi_node != NULL)) { 1092 devi_node = Adapter->priv_devi_node; 1093 devi_node->flag |= E1000G_PRIV_DEVI_DETACH; 1094 1095 if (devi_node->pending_rx_count == 0) { 1096 e1000g_free_priv_devi_node(devi_node); 1097 } 1098 } 1099 mutex_exit(&e1000g_rx_detach_lock); 1100 1101 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1102 1103 /* 1104 * Another hotplug spec requirement, 1105 * run ddi_set_driver_private(devinfo, null); 1106 */ 1107 ddi_set_driver_private(devinfo, NULL); 1108 } 1109 1110 static void 1111 e1000g_init_locks(struct e1000g *Adapter) 1112 { 1113 e1000g_tx_ring_t *tx_ring; 1114 e1000g_rx_ring_t *rx_ring; 1115 1116 rw_init(&Adapter->chip_lock, NULL, 1117 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1118 mutex_init(&Adapter->link_lock, NULL, 1119 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1120 mutex_init(&Adapter->watchdog_lock, NULL, 1121 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1122 1123 tx_ring = Adapter->tx_ring; 1124 1125 mutex_init(&tx_ring->tx_lock, NULL, 1126 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1127 mutex_init(&tx_ring->usedlist_lock, NULL, 1128 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1129 mutex_init(&tx_ring->freelist_lock, NULL, 1130 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1131 1132 rx_ring = Adapter->rx_ring; 1133 1134 mutex_init(&rx_ring->rx_lock, NULL, 1135 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1136 } 1137 1138 static void 1139 e1000g_destroy_locks(struct e1000g *Adapter) 1140 { 1141 e1000g_tx_ring_t *tx_ring; 1142 e1000g_rx_ring_t *rx_ring; 1143 1144 tx_ring = Adapter->tx_ring; 1145 mutex_destroy(&tx_ring->tx_lock); 1146 mutex_destroy(&tx_ring->usedlist_lock); 1147 mutex_destroy(&tx_ring->freelist_lock); 1148 1149 rx_ring = Adapter->rx_ring; 1150 mutex_destroy(&rx_ring->rx_lock); 1151 1152 mutex_destroy(&Adapter->link_lock); 1153 mutex_destroy(&Adapter->watchdog_lock); 1154 rw_destroy(&Adapter->chip_lock); 1155 1156 /* destory mutex initialized in shared code */ 1157 e1000_destroy_hw_mutex(&Adapter->shared); 1158 } 1159 1160 static int 1161 e1000g_resume(dev_info_t *devinfo) 1162 { 1163 struct e1000g *Adapter; 1164 1165 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1166 if (Adapter == NULL) 1167 e1000g_log(Adapter, CE_PANIC, 1168 "Instance pointer is null\n"); 1169 1170 if (Adapter->dip != devinfo) 1171 e1000g_log(Adapter, CE_PANIC, 1172 "Devinfo is not the same as saved devinfo\n"); 1173 1174 rw_enter(&Adapter->chip_lock, RW_WRITER); 1175 1176 if (Adapter->e1000g_state & E1000G_STARTED) { 1177 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1178 rw_exit(&Adapter->chip_lock); 1179 /* 1180 * We note the failure, but return success, as the 1181 * system is still usable without this controller. 1182 */ 1183 e1000g_log(Adapter, CE_WARN, 1184 "e1000g_resume: failed to restart controller\n"); 1185 return (DDI_SUCCESS); 1186 } 1187 /* Enable and start the watchdog timer */ 1188 enable_watchdog_timer(Adapter); 1189 } 1190 1191 Adapter->e1000g_state &= ~E1000G_SUSPENDED; 1192 1193 rw_exit(&Adapter->chip_lock); 1194 1195 return (DDI_SUCCESS); 1196 } 1197 1198 static int 1199 e1000g_suspend(dev_info_t *devinfo) 1200 { 1201 struct e1000g *Adapter; 1202 1203 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1204 if (Adapter == NULL) 1205 return (DDI_FAILURE); 1206 1207 rw_enter(&Adapter->chip_lock, RW_WRITER); 1208 1209 Adapter->e1000g_state |= E1000G_SUSPENDED; 1210 1211 /* if the port isn't plumbed, we can simply return */ 1212 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 1213 rw_exit(&Adapter->chip_lock); 1214 return (DDI_SUCCESS); 1215 } 1216 1217 e1000g_stop(Adapter, B_FALSE); 1218 1219 rw_exit(&Adapter->chip_lock); 1220 1221 /* Disable and stop all the timers */ 1222 disable_watchdog_timer(Adapter); 1223 stop_link_timer(Adapter); 1224 stop_82547_timer(Adapter->tx_ring); 1225 1226 return (DDI_SUCCESS); 1227 } 1228 1229 static int 1230 e1000g_init(struct e1000g *Adapter) 1231 { 1232 uint32_t pba; 1233 uint32_t high_water; 1234 struct e1000_hw *hw; 1235 clock_t link_timeout; 1236 int result; 1237 1238 hw = &Adapter->shared; 1239 1240 /* 1241 * reset to put the hardware in a known state 1242 * before we try to do anything with the eeprom 1243 */ 1244 mutex_enter(&e1000g_nvm_lock); 1245 result = e1000_reset_hw(hw); 1246 mutex_exit(&e1000g_nvm_lock); 1247 1248 if (result != E1000_SUCCESS) { 1249 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1250 goto init_fail; 1251 } 1252 1253 mutex_enter(&e1000g_nvm_lock); 1254 result = e1000_validate_nvm_checksum(hw); 1255 if (result < E1000_SUCCESS) { 1256 /* 1257 * Some PCI-E parts fail the first check due to 1258 * the link being in sleep state. Call it again, 1259 * if it fails a second time its a real issue. 1260 */ 1261 result = e1000_validate_nvm_checksum(hw); 1262 } 1263 mutex_exit(&e1000g_nvm_lock); 1264 1265 if (result < E1000_SUCCESS) { 1266 e1000g_log(Adapter, CE_WARN, 1267 "Invalid NVM checksum. Please contact " 1268 "the vendor to update the NVM."); 1269 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1270 goto init_fail; 1271 } 1272 1273 result = 0; 1274 #ifdef __sparc 1275 /* 1276 * First, we try to get the local ethernet address from OBP. If 1277 * failed, then we get it from the EEPROM of NIC card. 1278 */ 1279 result = e1000g_find_mac_address(Adapter); 1280 #endif 1281 /* Get the local ethernet address. */ 1282 if (!result) { 1283 mutex_enter(&e1000g_nvm_lock); 1284 result = e1000_read_mac_addr(hw); 1285 mutex_exit(&e1000g_nvm_lock); 1286 } 1287 1288 if (result < E1000_SUCCESS) { 1289 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1290 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1291 goto init_fail; 1292 } 1293 1294 /* check for valid mac address */ 1295 if (!is_valid_mac_addr(hw->mac.addr)) { 1296 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1297 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1298 goto init_fail; 1299 } 1300 1301 /* Set LAA state for 82571 chipset */ 1302 e1000_set_laa_state_82571(hw, B_TRUE); 1303 1304 /* Master Latency Timer implementation */ 1305 if (Adapter->master_latency_timer) { 1306 pci_config_put8(Adapter->osdep.cfg_handle, 1307 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1308 } 1309 1310 if (hw->mac.type < e1000_82547) { 1311 /* 1312 * Total FIFO is 64K 1313 */ 1314 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1315 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1316 else 1317 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1318 } else if ((hw->mac.type == e1000_82571) || 1319 (hw->mac.type == e1000_82572) || 1320 (hw->mac.type == e1000_80003es2lan)) { 1321 /* 1322 * Total FIFO is 48K 1323 */ 1324 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1325 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1326 else 1327 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1328 } else if (hw->mac.type == e1000_82573) { 1329 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1330 } else if (hw->mac.type == e1000_82574) { 1331 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1332 pba = E1000_READ_REG(hw, E1000_PBA); 1333 } else if (hw->mac.type == e1000_ich8lan) { 1334 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1335 } else if (hw->mac.type == e1000_ich9lan) { 1336 pba = E1000_PBA_10K; 1337 } else if (hw->mac.type == e1000_ich10lan) { 1338 pba = E1000_PBA_10K; 1339 } else if (hw->mac.type == e1000_pchlan) { 1340 pba = E1000_PBA_26K; 1341 } else { 1342 /* 1343 * Total FIFO is 40K 1344 */ 1345 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1346 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1347 else 1348 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1349 } 1350 E1000_WRITE_REG(hw, E1000_PBA, pba); 1351 1352 /* 1353 * These parameters set thresholds for the adapter's generation(Tx) 1354 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1355 * settings. Flow control is enabled or disabled in the configuration 1356 * file. 1357 * High-water mark is set down from the top of the rx fifo (not 1358 * sensitive to max_frame_size) and low-water is set just below 1359 * high-water mark. 1360 * The high water mark must be low enough to fit one full frame above 1361 * it in the rx FIFO. Should be the lower of: 1362 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1363 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1364 * Rx FIFO size minus one full frame. 1365 */ 1366 high_water = min(((pba << 10) * 9 / 10), 1367 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 || 1368 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ? 1369 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1370 ((pba << 10) - Adapter->max_frame_size))); 1371 1372 hw->fc.high_water = high_water & 0xFFF8; 1373 hw->fc.low_water = hw->fc.high_water - 8; 1374 1375 if (hw->mac.type == e1000_80003es2lan) 1376 hw->fc.pause_time = 0xFFFF; 1377 else 1378 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1379 hw->fc.send_xon = B_TRUE; 1380 1381 /* 1382 * Reset the adapter hardware the second time. 1383 */ 1384 mutex_enter(&e1000g_nvm_lock); 1385 result = e1000_reset_hw(hw); 1386 mutex_exit(&e1000g_nvm_lock); 1387 1388 if (result != E1000_SUCCESS) { 1389 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1390 goto init_fail; 1391 } 1392 1393 /* disable wakeup control by default */ 1394 if (hw->mac.type >= e1000_82544) 1395 E1000_WRITE_REG(hw, E1000_WUC, 0); 1396 1397 /* 1398 * MWI should be disabled on 82546. 1399 */ 1400 if (hw->mac.type == e1000_82546) 1401 e1000_pci_clear_mwi(hw); 1402 else 1403 e1000_pci_set_mwi(hw); 1404 1405 /* 1406 * Configure/Initialize hardware 1407 */ 1408 mutex_enter(&e1000g_nvm_lock); 1409 result = e1000_init_hw(hw); 1410 mutex_exit(&e1000g_nvm_lock); 1411 1412 if (result < E1000_SUCCESS) { 1413 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1414 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1415 goto init_fail; 1416 } 1417 1418 /* 1419 * Restore LED settings to the default from EEPROM 1420 * to meet the standard for Sun platforms. 1421 */ 1422 (void) e1000_cleanup_led(hw); 1423 1424 /* Disable Smart Power Down */ 1425 phy_spd_state(hw, B_FALSE); 1426 1427 /* Make sure driver has control */ 1428 e1000g_get_driver_control(hw); 1429 1430 /* 1431 * Initialize unicast addresses. 1432 */ 1433 e1000g_init_unicst(Adapter); 1434 1435 /* 1436 * Setup and initialize the mctable structures. After this routine 1437 * completes Multicast table will be set 1438 */ 1439 e1000_update_mc_addr_list(hw, 1440 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 1441 msec_delay(5); 1442 1443 /* 1444 * Implement Adaptive IFS 1445 */ 1446 e1000_reset_adaptive(hw); 1447 1448 /* Setup Interrupt Throttling Register */ 1449 if (hw->mac.type >= e1000_82540) { 1450 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1451 } else 1452 Adapter->intr_adaptive = B_FALSE; 1453 1454 /* Start the timer for link setup */ 1455 if (hw->mac.autoneg) 1456 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1457 else 1458 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1459 1460 mutex_enter(&Adapter->link_lock); 1461 if (hw->phy.autoneg_wait_to_complete) { 1462 Adapter->link_complete = B_TRUE; 1463 } else { 1464 Adapter->link_complete = B_FALSE; 1465 Adapter->link_tid = timeout(e1000g_link_timer, 1466 (void *)Adapter, link_timeout); 1467 } 1468 mutex_exit(&Adapter->link_lock); 1469 1470 /* Save the state of the phy */ 1471 e1000g_get_phy_state(Adapter); 1472 1473 e1000g_param_sync(Adapter); 1474 1475 Adapter->init_count++; 1476 1477 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1478 goto init_fail; 1479 } 1480 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1481 goto init_fail; 1482 } 1483 1484 Adapter->poll_mode = e1000g_poll_mode; 1485 1486 return (DDI_SUCCESS); 1487 1488 init_fail: 1489 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1490 return (DDI_FAILURE); 1491 } 1492 1493 static int 1494 e1000g_alloc_rx_data(struct e1000g *Adapter) 1495 { 1496 e1000g_rx_ring_t *rx_ring; 1497 e1000g_rx_data_t *rx_data; 1498 1499 rx_ring = Adapter->rx_ring; 1500 1501 rx_data = kmem_zalloc(sizeof (e1000g_rx_data_t), KM_NOSLEEP); 1502 1503 if (rx_data == NULL) 1504 return (DDI_FAILURE); 1505 1506 rx_data->priv_devi_node = Adapter->priv_devi_node; 1507 rx_data->rx_ring = rx_ring; 1508 1509 mutex_init(&rx_data->freelist_lock, NULL, 1510 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1511 mutex_init(&rx_data->recycle_lock, NULL, 1512 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1513 1514 rx_ring->rx_data = rx_data; 1515 1516 return (DDI_SUCCESS); 1517 } 1518 1519 void 1520 e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data) 1521 { 1522 rx_sw_packet_t *packet, *next_packet; 1523 1524 if (rx_data == NULL) 1525 return; 1526 1527 packet = rx_data->packet_area; 1528 while (packet != NULL) { 1529 next_packet = packet->next; 1530 e1000g_free_rx_sw_packet(packet, B_TRUE); 1531 packet = next_packet; 1532 } 1533 rx_data->packet_area = NULL; 1534 } 1535 1536 void 1537 e1000g_free_rx_data(e1000g_rx_data_t *rx_data) 1538 { 1539 if (rx_data == NULL) 1540 return; 1541 1542 mutex_destroy(&rx_data->freelist_lock); 1543 mutex_destroy(&rx_data->recycle_lock); 1544 1545 kmem_free(rx_data, sizeof (e1000g_rx_data_t)); 1546 } 1547 1548 /* 1549 * Check if the link is up 1550 */ 1551 static boolean_t 1552 e1000g_link_up(struct e1000g *Adapter) 1553 { 1554 struct e1000_hw *hw = &Adapter->shared; 1555 boolean_t link_up = B_FALSE; 1556 1557 /* 1558 * get_link_status is set in the interrupt handler on link-status-change 1559 * or rx sequence error interrupt. get_link_status will stay 1560 * false until the e1000_check_for_link establishes link only 1561 * for copper adapters. 1562 */ 1563 switch (hw->phy.media_type) { 1564 case e1000_media_type_copper: 1565 if (hw->mac.get_link_status) { 1566 (void) e1000_check_for_link(hw); 1567 link_up = !hw->mac.get_link_status; 1568 } else { 1569 link_up = B_TRUE; 1570 } 1571 break; 1572 case e1000_media_type_fiber: 1573 (void) e1000_check_for_link(hw); 1574 link_up = (E1000_READ_REG(hw, E1000_STATUS) & 1575 E1000_STATUS_LU); 1576 break; 1577 case e1000_media_type_internal_serdes: 1578 (void) e1000_check_for_link(hw); 1579 link_up = hw->mac.serdes_has_link; 1580 break; 1581 } 1582 1583 return (link_up); 1584 } 1585 1586 static void 1587 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1588 { 1589 struct iocblk *iocp; 1590 struct e1000g *e1000gp; 1591 enum ioc_reply status; 1592 1593 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1594 iocp->ioc_error = 0; 1595 e1000gp = (struct e1000g *)arg; 1596 1597 ASSERT(e1000gp); 1598 if (e1000gp == NULL) { 1599 miocnak(q, mp, 0, EINVAL); 1600 return; 1601 } 1602 1603 rw_enter(&e1000gp->chip_lock, RW_READER); 1604 if (e1000gp->e1000g_state & E1000G_SUSPENDED) { 1605 rw_exit(&e1000gp->chip_lock); 1606 miocnak(q, mp, 0, EINVAL); 1607 return; 1608 } 1609 rw_exit(&e1000gp->chip_lock); 1610 1611 switch (iocp->ioc_cmd) { 1612 1613 case LB_GET_INFO_SIZE: 1614 case LB_GET_INFO: 1615 case LB_GET_MODE: 1616 case LB_SET_MODE: 1617 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1618 break; 1619 1620 1621 #ifdef E1000G_DEBUG 1622 case E1000G_IOC_REG_PEEK: 1623 case E1000G_IOC_REG_POKE: 1624 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1625 break; 1626 case E1000G_IOC_CHIP_RESET: 1627 e1000gp->reset_count++; 1628 if (e1000g_reset_adapter(e1000gp)) 1629 status = IOC_ACK; 1630 else 1631 status = IOC_INVAL; 1632 break; 1633 #endif 1634 default: 1635 status = IOC_INVAL; 1636 break; 1637 } 1638 1639 /* 1640 * Decide how to reply 1641 */ 1642 switch (status) { 1643 default: 1644 case IOC_INVAL: 1645 /* 1646 * Error, reply with a NAK and EINVAL or the specified error 1647 */ 1648 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1649 EINVAL : iocp->ioc_error); 1650 break; 1651 1652 case IOC_DONE: 1653 /* 1654 * OK, reply already sent 1655 */ 1656 break; 1657 1658 case IOC_ACK: 1659 /* 1660 * OK, reply with an ACK 1661 */ 1662 miocack(q, mp, 0, 0); 1663 break; 1664 1665 case IOC_REPLY: 1666 /* 1667 * OK, send prepared reply as ACK or NAK 1668 */ 1669 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1670 M_IOCACK : M_IOCNAK; 1671 qreply(q, mp); 1672 break; 1673 } 1674 } 1675 1676 /* 1677 * The default value of e1000g_poll_mode == 0 assumes that the NIC is 1678 * capable of supporting only one interrupt and we shouldn't disable 1679 * the physical interrupt. In this case we let the interrupt come and 1680 * we queue the packets in the rx ring itself in case we are in polling 1681 * mode (better latency but slightly lower performance and a very 1682 * high intrrupt count in mpstat which is harmless). 1683 * 1684 * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt 1685 * which can be disabled in poll mode. This gives better overall 1686 * throughput (compared to the mode above), shows very low interrupt 1687 * count but has slightly higher latency since we pick the packets when 1688 * the poll thread does polling. 1689 * 1690 * Currently, this flag should be enabled only while doing performance 1691 * measurement or when it can be guaranteed that entire NIC going 1692 * in poll mode will not harm any traffic like cluster heartbeat etc. 1693 */ 1694 int e1000g_poll_mode = 0; 1695 1696 /* 1697 * Called from the upper layers when driver is in polling mode to 1698 * pick up any queued packets. Care should be taken to not block 1699 * this thread. 1700 */ 1701 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup) 1702 { 1703 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)arg; 1704 mblk_t *mp = NULL; 1705 mblk_t *tail; 1706 struct e1000g *adapter; 1707 1708 adapter = rx_ring->adapter; 1709 1710 rw_enter(&adapter->chip_lock, RW_READER); 1711 1712 if (adapter->e1000g_state & E1000G_SUSPENDED) { 1713 rw_exit(&adapter->chip_lock); 1714 return (NULL); 1715 } 1716 1717 mutex_enter(&rx_ring->rx_lock); 1718 mp = e1000g_receive(rx_ring, &tail, bytes_to_pickup); 1719 mutex_exit(&rx_ring->rx_lock); 1720 rw_exit(&adapter->chip_lock); 1721 return (mp); 1722 } 1723 1724 static int 1725 e1000g_m_start(void *arg) 1726 { 1727 struct e1000g *Adapter = (struct e1000g *)arg; 1728 1729 rw_enter(&Adapter->chip_lock, RW_WRITER); 1730 1731 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1732 rw_exit(&Adapter->chip_lock); 1733 return (ECANCELED); 1734 } 1735 1736 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1737 rw_exit(&Adapter->chip_lock); 1738 return (ENOTACTIVE); 1739 } 1740 1741 Adapter->e1000g_state |= E1000G_STARTED; 1742 1743 rw_exit(&Adapter->chip_lock); 1744 1745 /* Enable and start the watchdog timer */ 1746 enable_watchdog_timer(Adapter); 1747 1748 return (0); 1749 } 1750 1751 static int 1752 e1000g_start(struct e1000g *Adapter, boolean_t global) 1753 { 1754 e1000g_rx_data_t *rx_data; 1755 1756 if (global) { 1757 if (e1000g_alloc_rx_data(Adapter) != DDI_SUCCESS) { 1758 e1000g_log(Adapter, CE_WARN, "Allocate rx data failed"); 1759 goto start_fail; 1760 } 1761 1762 /* Allocate dma resources for descriptors and buffers */ 1763 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1764 e1000g_log(Adapter, CE_WARN, 1765 "Alloc DMA resources failed"); 1766 goto start_fail; 1767 } 1768 Adapter->rx_buffer_setup = B_FALSE; 1769 } 1770 1771 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1772 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1773 e1000g_log(Adapter, CE_WARN, 1774 "Adapter initialization failed"); 1775 goto start_fail; 1776 } 1777 } 1778 1779 /* Setup and initialize the transmit structures */ 1780 e1000g_tx_setup(Adapter); 1781 msec_delay(5); 1782 1783 /* Setup and initialize the receive structures */ 1784 e1000g_rx_setup(Adapter); 1785 msec_delay(5); 1786 1787 /* Restore the e1000g promiscuous mode */ 1788 e1000g_restore_promisc(Adapter); 1789 1790 e1000g_mask_interrupt(Adapter); 1791 1792 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1793 1794 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1795 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1796 goto start_fail; 1797 } 1798 1799 return (DDI_SUCCESS); 1800 1801 start_fail: 1802 rx_data = Adapter->rx_ring->rx_data; 1803 1804 if (global) { 1805 e1000g_release_dma_resources(Adapter); 1806 e1000g_free_rx_pending_buffers(rx_data); 1807 e1000g_free_rx_data(rx_data); 1808 } 1809 1810 mutex_enter(&e1000g_nvm_lock); 1811 (void) e1000_reset_hw(&Adapter->shared); 1812 mutex_exit(&e1000g_nvm_lock); 1813 1814 return (DDI_FAILURE); 1815 } 1816 1817 static void 1818 e1000g_m_stop(void *arg) 1819 { 1820 struct e1000g *Adapter = (struct e1000g *)arg; 1821 1822 /* Drain tx sessions */ 1823 (void) e1000g_tx_drain(Adapter); 1824 1825 rw_enter(&Adapter->chip_lock, RW_WRITER); 1826 1827 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1828 rw_exit(&Adapter->chip_lock); 1829 return; 1830 } 1831 Adapter->e1000g_state &= ~E1000G_STARTED; 1832 e1000g_stop(Adapter, B_TRUE); 1833 1834 rw_exit(&Adapter->chip_lock); 1835 1836 /* Disable and stop all the timers */ 1837 disable_watchdog_timer(Adapter); 1838 stop_link_timer(Adapter); 1839 stop_82547_timer(Adapter->tx_ring); 1840 } 1841 1842 static void 1843 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1844 { 1845 private_devi_list_t *devi_node; 1846 e1000g_rx_data_t *rx_data; 1847 int result; 1848 1849 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1850 1851 /* Stop the chip and release pending resources */ 1852 1853 /* Tell firmware driver is no longer in control */ 1854 e1000g_release_driver_control(&Adapter->shared); 1855 1856 e1000g_clear_all_interrupts(Adapter); 1857 1858 mutex_enter(&e1000g_nvm_lock); 1859 result = e1000_reset_hw(&Adapter->shared); 1860 mutex_exit(&e1000g_nvm_lock); 1861 1862 if (result != E1000_SUCCESS) { 1863 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1864 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1865 } 1866 1867 /* Release resources still held by the TX descriptors */ 1868 e1000g_tx_clean(Adapter); 1869 1870 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1871 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1872 1873 /* Clean the pending rx jumbo packet fragment */ 1874 e1000g_rx_clean(Adapter); 1875 1876 if (global) { 1877 e1000g_release_dma_resources(Adapter); 1878 1879 mutex_enter(&e1000g_rx_detach_lock); 1880 rx_data = Adapter->rx_ring->rx_data; 1881 rx_data->flag |= E1000G_RX_STOPPED; 1882 1883 if (rx_data->pending_count == 0) { 1884 e1000g_free_rx_pending_buffers(rx_data); 1885 e1000g_free_rx_data(rx_data); 1886 } else { 1887 devi_node = rx_data->priv_devi_node; 1888 if (devi_node != NULL) 1889 atomic_inc_32(&devi_node->pending_rx_count); 1890 else 1891 atomic_inc_32(&Adapter->pending_rx_count); 1892 } 1893 mutex_exit(&e1000g_rx_detach_lock); 1894 } 1895 1896 if (Adapter->link_state == LINK_STATE_UP) { 1897 Adapter->link_state = LINK_STATE_UNKNOWN; 1898 mac_link_update(Adapter->mh, Adapter->link_state); 1899 } 1900 } 1901 1902 static void 1903 e1000g_rx_clean(struct e1000g *Adapter) 1904 { 1905 e1000g_rx_data_t *rx_data = Adapter->rx_ring->rx_data; 1906 1907 if (rx_data == NULL) 1908 return; 1909 1910 if (rx_data->rx_mblk != NULL) { 1911 freemsg(rx_data->rx_mblk); 1912 rx_data->rx_mblk = NULL; 1913 rx_data->rx_mblk_tail = NULL; 1914 rx_data->rx_mblk_len = 0; 1915 } 1916 } 1917 1918 static void 1919 e1000g_tx_clean(struct e1000g *Adapter) 1920 { 1921 e1000g_tx_ring_t *tx_ring; 1922 p_tx_sw_packet_t packet; 1923 mblk_t *mp; 1924 mblk_t *nmp; 1925 uint32_t packet_count; 1926 1927 tx_ring = Adapter->tx_ring; 1928 1929 /* 1930 * Here we don't need to protect the lists using 1931 * the usedlist_lock and freelist_lock, for they 1932 * have been protected by the chip_lock. 1933 */ 1934 mp = NULL; 1935 nmp = NULL; 1936 packet_count = 0; 1937 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1938 while (packet != NULL) { 1939 if (packet->mp != NULL) { 1940 /* Assemble the message chain */ 1941 if (mp == NULL) { 1942 mp = packet->mp; 1943 nmp = packet->mp; 1944 } else { 1945 nmp->b_next = packet->mp; 1946 nmp = packet->mp; 1947 } 1948 /* Disconnect the message from the sw packet */ 1949 packet->mp = NULL; 1950 } 1951 1952 e1000g_free_tx_swpkt(packet); 1953 packet_count++; 1954 1955 packet = (p_tx_sw_packet_t) 1956 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1957 } 1958 1959 if (mp != NULL) 1960 freemsgchain(mp); 1961 1962 if (packet_count > 0) { 1963 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1964 QUEUE_INIT_LIST(&tx_ring->used_list); 1965 1966 /* Setup TX descriptor pointers */ 1967 tx_ring->tbd_next = tx_ring->tbd_first; 1968 tx_ring->tbd_oldest = tx_ring->tbd_first; 1969 1970 /* Setup our HW Tx Head & Tail descriptor pointers */ 1971 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1972 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1973 } 1974 } 1975 1976 static boolean_t 1977 e1000g_tx_drain(struct e1000g *Adapter) 1978 { 1979 int i; 1980 boolean_t done; 1981 e1000g_tx_ring_t *tx_ring; 1982 1983 tx_ring = Adapter->tx_ring; 1984 1985 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1986 for (i = 0; i < TX_DRAIN_TIME; i++) { 1987 mutex_enter(&tx_ring->usedlist_lock); 1988 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1989 mutex_exit(&tx_ring->usedlist_lock); 1990 1991 if (done) 1992 break; 1993 1994 msec_delay(1); 1995 } 1996 1997 return (done); 1998 } 1999 2000 static boolean_t 2001 e1000g_rx_drain(struct e1000g *Adapter) 2002 { 2003 int i; 2004 boolean_t done; 2005 2006 /* 2007 * Allow up to RX_DRAIN_TIME for pending received packets to complete. 2008 */ 2009 for (i = 0; i < RX_DRAIN_TIME; i++) { 2010 done = (Adapter->pending_rx_count == 0); 2011 2012 if (done) 2013 break; 2014 2015 msec_delay(1); 2016 } 2017 2018 return (done); 2019 } 2020 2021 static boolean_t 2022 e1000g_reset_adapter(struct e1000g *Adapter) 2023 { 2024 /* Disable and stop all the timers */ 2025 disable_watchdog_timer(Adapter); 2026 stop_link_timer(Adapter); 2027 stop_82547_timer(Adapter->tx_ring); 2028 2029 rw_enter(&Adapter->chip_lock, RW_WRITER); 2030 2031 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2032 rw_exit(&Adapter->chip_lock); 2033 return (B_TRUE); 2034 } 2035 2036 e1000g_stop(Adapter, B_FALSE); 2037 2038 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 2039 rw_exit(&Adapter->chip_lock); 2040 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2041 return (B_FALSE); 2042 } 2043 2044 rw_exit(&Adapter->chip_lock); 2045 2046 /* Enable and start the watchdog timer */ 2047 enable_watchdog_timer(Adapter); 2048 2049 return (B_TRUE); 2050 } 2051 2052 boolean_t 2053 e1000g_global_reset(struct e1000g *Adapter) 2054 { 2055 /* Disable and stop all the timers */ 2056 disable_watchdog_timer(Adapter); 2057 stop_link_timer(Adapter); 2058 stop_82547_timer(Adapter->tx_ring); 2059 2060 rw_enter(&Adapter->chip_lock, RW_WRITER); 2061 2062 e1000g_stop(Adapter, B_TRUE); 2063 2064 Adapter->init_count = 0; 2065 2066 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 2067 rw_exit(&Adapter->chip_lock); 2068 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2069 return (B_FALSE); 2070 } 2071 2072 rw_exit(&Adapter->chip_lock); 2073 2074 /* Enable and start the watchdog timer */ 2075 enable_watchdog_timer(Adapter); 2076 2077 return (B_TRUE); 2078 } 2079 2080 /* 2081 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 2082 * 2083 * This interrupt service routine is for PCI-Express adapters. 2084 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 2085 * bit is set. 2086 */ 2087 static uint_t 2088 e1000g_intr_pciexpress(caddr_t arg) 2089 { 2090 struct e1000g *Adapter; 2091 uint32_t icr; 2092 2093 Adapter = (struct e1000g *)(uintptr_t)arg; 2094 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2095 2096 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2097 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2098 return (DDI_INTR_CLAIMED); 2099 } 2100 2101 if (icr & E1000_ICR_INT_ASSERTED) { 2102 /* 2103 * E1000_ICR_INT_ASSERTED bit was set: 2104 * Read(Clear) the ICR, claim this interrupt, 2105 * look for work to do. 2106 */ 2107 e1000g_intr_work(Adapter, icr); 2108 return (DDI_INTR_CLAIMED); 2109 } else { 2110 /* 2111 * E1000_ICR_INT_ASSERTED bit was not set: 2112 * Don't claim this interrupt, return immediately. 2113 */ 2114 return (DDI_INTR_UNCLAIMED); 2115 } 2116 } 2117 2118 /* 2119 * e1000g_intr - ISR for PCI/PCI-X chipsets 2120 * 2121 * This interrupt service routine is for PCI/PCI-X adapters. 2122 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 2123 * bit is set or not. 2124 */ 2125 static uint_t 2126 e1000g_intr(caddr_t arg) 2127 { 2128 struct e1000g *Adapter; 2129 uint32_t icr; 2130 2131 Adapter = (struct e1000g *)(uintptr_t)arg; 2132 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2133 2134 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2135 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2136 return (DDI_INTR_CLAIMED); 2137 } 2138 2139 if (icr) { 2140 /* 2141 * Any bit was set in ICR: 2142 * Read(Clear) the ICR, claim this interrupt, 2143 * look for work to do. 2144 */ 2145 e1000g_intr_work(Adapter, icr); 2146 return (DDI_INTR_CLAIMED); 2147 } else { 2148 /* 2149 * No bit was set in ICR: 2150 * Don't claim this interrupt, return immediately. 2151 */ 2152 return (DDI_INTR_UNCLAIMED); 2153 } 2154 } 2155 2156 /* 2157 * e1000g_intr_work - actual processing of ISR 2158 * 2159 * Read(clear) the ICR contents and call appropriate interrupt 2160 * processing routines. 2161 */ 2162 static void 2163 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 2164 { 2165 struct e1000_hw *hw; 2166 hw = &Adapter->shared; 2167 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2168 2169 Adapter->rx_pkt_cnt = 0; 2170 Adapter->tx_pkt_cnt = 0; 2171 2172 rw_enter(&Adapter->chip_lock, RW_READER); 2173 2174 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2175 rw_exit(&Adapter->chip_lock); 2176 return; 2177 } 2178 /* 2179 * Here we need to check the "e1000g_state" flag within the chip_lock to 2180 * ensure the receive routine will not execute when the adapter is 2181 * being reset. 2182 */ 2183 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2184 rw_exit(&Adapter->chip_lock); 2185 return; 2186 } 2187 2188 if (icr & E1000_ICR_RXT0) { 2189 mblk_t *mp = NULL; 2190 mblk_t *tail = NULL; 2191 e1000g_rx_ring_t *rx_ring; 2192 2193 rx_ring = Adapter->rx_ring; 2194 mutex_enter(&rx_ring->rx_lock); 2195 /* 2196 * Sometimes with legacy interrupts, it possible that 2197 * there is a single interrupt for Rx/Tx. In which 2198 * case, if poll flag is set, we shouldn't really 2199 * be doing Rx processing. 2200 */ 2201 if (!rx_ring->poll_flag) 2202 mp = e1000g_receive(rx_ring, &tail, 2203 E1000G_CHAIN_NO_LIMIT); 2204 mutex_exit(&rx_ring->rx_lock); 2205 rw_exit(&Adapter->chip_lock); 2206 if (mp != NULL) 2207 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2208 mp, rx_ring->ring_gen_num); 2209 } else 2210 rw_exit(&Adapter->chip_lock); 2211 2212 if (icr & E1000_ICR_TXDW) { 2213 if (!Adapter->tx_intr_enable) 2214 e1000g_clear_tx_interrupt(Adapter); 2215 2216 /* Recycle the tx descriptors */ 2217 rw_enter(&Adapter->chip_lock, RW_READER); 2218 (void) e1000g_recycle(tx_ring); 2219 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 2220 rw_exit(&Adapter->chip_lock); 2221 2222 if (tx_ring->resched_needed && 2223 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 2224 tx_ring->resched_needed = B_FALSE; 2225 mac_tx_update(Adapter->mh); 2226 E1000G_STAT(tx_ring->stat_reschedule); 2227 } 2228 } 2229 2230 /* 2231 * The Receive Sequence errors RXSEQ and the link status change LSC 2232 * are checked to detect that the cable has been pulled out. For 2233 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 2234 * are an indication that cable is not connected. 2235 */ 2236 if ((icr & E1000_ICR_RXSEQ) || 2237 (icr & E1000_ICR_LSC) || 2238 (icr & E1000_ICR_GPI_EN1)) { 2239 boolean_t link_changed; 2240 timeout_id_t tid = 0; 2241 2242 stop_watchdog_timer(Adapter); 2243 2244 rw_enter(&Adapter->chip_lock, RW_WRITER); 2245 2246 /* 2247 * Because we got a link-status-change interrupt, force 2248 * e1000_check_for_link() to look at phy 2249 */ 2250 Adapter->shared.mac.get_link_status = B_TRUE; 2251 2252 /* e1000g_link_check takes care of link status change */ 2253 link_changed = e1000g_link_check(Adapter); 2254 2255 /* Get new phy state */ 2256 e1000g_get_phy_state(Adapter); 2257 2258 /* 2259 * If the link timer has not timed out, we'll not notify 2260 * the upper layer with any link state until the link is up. 2261 */ 2262 if (link_changed && !Adapter->link_complete) { 2263 if (Adapter->link_state == LINK_STATE_UP) { 2264 mutex_enter(&Adapter->link_lock); 2265 Adapter->link_complete = B_TRUE; 2266 tid = Adapter->link_tid; 2267 Adapter->link_tid = 0; 2268 mutex_exit(&Adapter->link_lock); 2269 } else { 2270 link_changed = B_FALSE; 2271 } 2272 } 2273 rw_exit(&Adapter->chip_lock); 2274 2275 if (link_changed) { 2276 if (tid != 0) 2277 (void) untimeout(tid); 2278 2279 /* 2280 * Workaround for esb2. Data stuck in fifo on a link 2281 * down event. Stop receiver here and reset in watchdog. 2282 */ 2283 if ((Adapter->link_state == LINK_STATE_DOWN) && 2284 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2285 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2286 E1000_WRITE_REG(hw, E1000_RCTL, 2287 rctl & ~E1000_RCTL_EN); 2288 e1000g_log(Adapter, CE_WARN, 2289 "ESB2 receiver disabled"); 2290 Adapter->esb2_workaround = B_TRUE; 2291 } 2292 if (!Adapter->reset_flag) 2293 mac_link_update(Adapter->mh, 2294 Adapter->link_state); 2295 if (Adapter->link_state == LINK_STATE_UP) 2296 Adapter->reset_flag = B_FALSE; 2297 } 2298 2299 start_watchdog_timer(Adapter); 2300 } 2301 } 2302 2303 static void 2304 e1000g_init_unicst(struct e1000g *Adapter) 2305 { 2306 struct e1000_hw *hw; 2307 int slot; 2308 2309 hw = &Adapter->shared; 2310 2311 if (Adapter->init_count == 0) { 2312 /* Initialize the multiple unicast addresses */ 2313 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2314 2315 /* Workaround for an erratum of 82571 chipst */ 2316 if ((hw->mac.type == e1000_82571) && 2317 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2318 Adapter->unicst_total--; 2319 2320 Adapter->unicst_avail = Adapter->unicst_total; 2321 2322 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2323 /* Clear both the flag and MAC address */ 2324 Adapter->unicst_addr[slot].reg.high = 0; 2325 Adapter->unicst_addr[slot].reg.low = 0; 2326 } 2327 } else { 2328 /* Workaround for an erratum of 82571 chipst */ 2329 if ((hw->mac.type == e1000_82571) && 2330 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2331 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2332 2333 /* Re-configure the RAR registers */ 2334 for (slot = 0; slot < Adapter->unicst_total; slot++) 2335 if (Adapter->unicst_addr[slot].mac.set == 1) 2336 e1000_rar_set(hw, 2337 Adapter->unicst_addr[slot].mac.addr, slot); 2338 } 2339 2340 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2341 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2342 } 2343 2344 static int 2345 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2346 int slot) 2347 { 2348 struct e1000_hw *hw; 2349 2350 hw = &Adapter->shared; 2351 2352 /* 2353 * The first revision of Wiseman silicon (rev 2.0) has an errata 2354 * that requires the receiver to be in reset when any of the 2355 * receive address registers (RAR regs) are accessed. The first 2356 * rev of Wiseman silicon also requires MWI to be disabled when 2357 * a global reset or a receive reset is issued. So before we 2358 * initialize the RARs, we check the rev of the Wiseman controller 2359 * and work around any necessary HW errata. 2360 */ 2361 if ((hw->mac.type == e1000_82542) && 2362 (hw->revision_id == E1000_REVISION_2)) { 2363 e1000_pci_clear_mwi(hw); 2364 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2365 msec_delay(5); 2366 } 2367 if (mac_addr == NULL) { 2368 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0); 2369 E1000_WRITE_FLUSH(hw); 2370 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0); 2371 E1000_WRITE_FLUSH(hw); 2372 /* Clear both the flag and MAC address */ 2373 Adapter->unicst_addr[slot].reg.high = 0; 2374 Adapter->unicst_addr[slot].reg.low = 0; 2375 } else { 2376 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, 2377 ETHERADDRL); 2378 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2379 Adapter->unicst_addr[slot].mac.set = 1; 2380 } 2381 2382 /* Workaround for an erratum of 82571 chipst */ 2383 if (slot == 0) { 2384 if ((hw->mac.type == e1000_82571) && 2385 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2386 if (mac_addr == NULL) { 2387 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2388 slot << 1, 0); 2389 E1000_WRITE_FLUSH(hw); 2390 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2391 (slot << 1) + 1, 0); 2392 E1000_WRITE_FLUSH(hw); 2393 } else { 2394 e1000_rar_set(hw, (uint8_t *)mac_addr, 2395 LAST_RAR_ENTRY); 2396 } 2397 } 2398 2399 /* 2400 * If we are using Wiseman rev 2.0 silicon, we will have previously 2401 * put the receive in reset, and disabled MWI, to work around some 2402 * HW errata. Now we should take the receiver out of reset, and 2403 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2404 */ 2405 if ((hw->mac.type == e1000_82542) && 2406 (hw->revision_id == E1000_REVISION_2)) { 2407 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2408 msec_delay(1); 2409 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2410 e1000_pci_set_mwi(hw); 2411 e1000g_rx_setup(Adapter); 2412 } 2413 2414 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2415 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2416 return (EIO); 2417 } 2418 2419 return (0); 2420 } 2421 2422 static int 2423 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2424 { 2425 struct e1000_hw *hw = &Adapter->shared; 2426 struct ether_addr *newtable; 2427 size_t new_len; 2428 size_t old_len; 2429 int res = 0; 2430 2431 if ((multiaddr[0] & 01) == 0) { 2432 res = EINVAL; 2433 e1000g_log(Adapter, CE_WARN, "Illegal multicast address"); 2434 goto done; 2435 } 2436 2437 if (Adapter->mcast_count >= Adapter->mcast_max_num) { 2438 res = ENOENT; 2439 e1000g_log(Adapter, CE_WARN, 2440 "Adapter requested more than %d mcast addresses", 2441 Adapter->mcast_max_num); 2442 goto done; 2443 } 2444 2445 2446 if (Adapter->mcast_count == Adapter->mcast_alloc_count) { 2447 old_len = Adapter->mcast_alloc_count * 2448 sizeof (struct ether_addr); 2449 new_len = (Adapter->mcast_alloc_count + MCAST_ALLOC_SIZE) * 2450 sizeof (struct ether_addr); 2451 2452 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2453 if (newtable == NULL) { 2454 res = ENOMEM; 2455 e1000g_log(Adapter, CE_WARN, 2456 "Not enough memory to alloc mcast table"); 2457 goto done; 2458 } 2459 2460 if (Adapter->mcast_table != NULL) { 2461 bcopy(Adapter->mcast_table, newtable, old_len); 2462 kmem_free(Adapter->mcast_table, old_len); 2463 } 2464 Adapter->mcast_alloc_count += MCAST_ALLOC_SIZE; 2465 Adapter->mcast_table = newtable; 2466 } 2467 2468 bcopy(multiaddr, 2469 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2470 Adapter->mcast_count++; 2471 2472 /* 2473 * Update the MC table in the hardware 2474 */ 2475 e1000g_clear_interrupt(Adapter); 2476 2477 e1000_update_mc_addr_list(hw, 2478 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2479 2480 e1000g_mask_interrupt(Adapter); 2481 2482 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2483 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2484 res = EIO; 2485 } 2486 2487 done: 2488 return (res); 2489 } 2490 2491 static int 2492 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2493 { 2494 struct e1000_hw *hw = &Adapter->shared; 2495 struct ether_addr *newtable; 2496 size_t new_len; 2497 size_t old_len; 2498 unsigned i; 2499 2500 for (i = 0; i < Adapter->mcast_count; i++) { 2501 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2502 ETHERADDRL) == 0) { 2503 for (i++; i < Adapter->mcast_count; i++) { 2504 Adapter->mcast_table[i - 1] = 2505 Adapter->mcast_table[i]; 2506 } 2507 Adapter->mcast_count--; 2508 break; 2509 } 2510 } 2511 2512 if ((Adapter->mcast_alloc_count - Adapter->mcast_count) > 2513 MCAST_ALLOC_SIZE) { 2514 old_len = Adapter->mcast_alloc_count * 2515 sizeof (struct ether_addr); 2516 new_len = (Adapter->mcast_alloc_count - MCAST_ALLOC_SIZE) * 2517 sizeof (struct ether_addr); 2518 2519 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2520 if (newtable != NULL) { 2521 bcopy(Adapter->mcast_table, newtable, new_len); 2522 kmem_free(Adapter->mcast_table, old_len); 2523 2524 Adapter->mcast_alloc_count -= MCAST_ALLOC_SIZE; 2525 Adapter->mcast_table = newtable; 2526 } 2527 } 2528 2529 /* 2530 * Update the MC table in the hardware 2531 */ 2532 e1000g_clear_interrupt(Adapter); 2533 2534 e1000_update_mc_addr_list(hw, 2535 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2536 2537 e1000g_mask_interrupt(Adapter); 2538 2539 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2540 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2541 return (EIO); 2542 } 2543 2544 return (0); 2545 } 2546 2547 static void 2548 e1000g_release_multicast(struct e1000g *Adapter) 2549 { 2550 if (Adapter->mcast_table != NULL) { 2551 kmem_free(Adapter->mcast_table, 2552 Adapter->mcast_alloc_count * sizeof (struct ether_addr)); 2553 Adapter->mcast_table = NULL; 2554 } 2555 } 2556 2557 int 2558 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2559 { 2560 struct e1000g *Adapter = (struct e1000g *)arg; 2561 int result; 2562 2563 rw_enter(&Adapter->chip_lock, RW_WRITER); 2564 2565 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2566 result = ECANCELED; 2567 goto done; 2568 } 2569 2570 result = (add) ? multicst_add(Adapter, addr) 2571 : multicst_remove(Adapter, addr); 2572 2573 done: 2574 rw_exit(&Adapter->chip_lock); 2575 return (result); 2576 2577 } 2578 2579 int 2580 e1000g_m_promisc(void *arg, boolean_t on) 2581 { 2582 struct e1000g *Adapter = (struct e1000g *)arg; 2583 uint32_t rctl; 2584 2585 rw_enter(&Adapter->chip_lock, RW_WRITER); 2586 2587 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2588 rw_exit(&Adapter->chip_lock); 2589 return (ECANCELED); 2590 } 2591 2592 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2593 2594 if (on) 2595 rctl |= 2596 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2597 else 2598 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2599 2600 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2601 2602 Adapter->e1000g_promisc = on; 2603 2604 rw_exit(&Adapter->chip_lock); 2605 2606 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2607 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2608 return (EIO); 2609 } 2610 2611 return (0); 2612 } 2613 2614 /* 2615 * Entry points to enable and disable interrupts at the granularity of 2616 * a group. 2617 * Turns the poll_mode for the whole adapter on and off to enable or 2618 * override the ring level polling control over the hardware interrupts. 2619 */ 2620 static int 2621 e1000g_rx_group_intr_enable(mac_intr_handle_t arg) 2622 { 2623 struct e1000g *adapter = (struct e1000g *)arg; 2624 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2625 2626 /* 2627 * Later interrupts at the granularity of the this ring will 2628 * invoke mac_rx() with NULL, indicating the need for another 2629 * software classification. 2630 * We have a single ring usable per adapter now, so we only need to 2631 * reset the rx handle for that one. 2632 * When more RX rings can be used, we should update each one of them. 2633 */ 2634 mutex_enter(&rx_ring->rx_lock); 2635 rx_ring->mrh = NULL; 2636 adapter->poll_mode = B_FALSE; 2637 mutex_exit(&rx_ring->rx_lock); 2638 return (0); 2639 } 2640 2641 static int 2642 e1000g_rx_group_intr_disable(mac_intr_handle_t arg) 2643 { 2644 struct e1000g *adapter = (struct e1000g *)arg; 2645 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2646 2647 mutex_enter(&rx_ring->rx_lock); 2648 2649 /* 2650 * Later interrupts at the granularity of the this ring will 2651 * invoke mac_rx() with the handle for this ring; 2652 */ 2653 adapter->poll_mode = B_TRUE; 2654 rx_ring->mrh = rx_ring->mrh_init; 2655 mutex_exit(&rx_ring->rx_lock); 2656 return (0); 2657 } 2658 2659 /* 2660 * Entry points to enable and disable interrupts at the granularity of 2661 * a ring. 2662 * adapter poll_mode controls whether we actually proceed with hardware 2663 * interrupt toggling. 2664 */ 2665 static int 2666 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh) 2667 { 2668 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2669 struct e1000g *adapter = rx_ring->adapter; 2670 struct e1000_hw *hw = &adapter->shared; 2671 uint32_t intr_mask; 2672 2673 rw_enter(&adapter->chip_lock, RW_READER); 2674 2675 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2676 rw_exit(&adapter->chip_lock); 2677 return (0); 2678 } 2679 2680 mutex_enter(&rx_ring->rx_lock); 2681 rx_ring->poll_flag = 0; 2682 mutex_exit(&rx_ring->rx_lock); 2683 2684 /* Rx interrupt enabling for MSI and legacy */ 2685 intr_mask = E1000_READ_REG(hw, E1000_IMS); 2686 intr_mask |= E1000_IMS_RXT0; 2687 E1000_WRITE_REG(hw, E1000_IMS, intr_mask); 2688 E1000_WRITE_FLUSH(hw); 2689 2690 /* Trigger a Rx interrupt to check Rx ring */ 2691 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2692 E1000_WRITE_FLUSH(hw); 2693 2694 rw_exit(&adapter->chip_lock); 2695 return (0); 2696 } 2697 2698 static int 2699 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh) 2700 { 2701 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2702 struct e1000g *adapter = rx_ring->adapter; 2703 struct e1000_hw *hw = &adapter->shared; 2704 2705 rw_enter(&adapter->chip_lock, RW_READER); 2706 2707 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2708 rw_exit(&adapter->chip_lock); 2709 return (0); 2710 } 2711 mutex_enter(&rx_ring->rx_lock); 2712 rx_ring->poll_flag = 1; 2713 mutex_exit(&rx_ring->rx_lock); 2714 2715 /* Rx interrupt disabling for MSI and legacy */ 2716 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0); 2717 E1000_WRITE_FLUSH(hw); 2718 2719 rw_exit(&adapter->chip_lock); 2720 return (0); 2721 } 2722 2723 /* 2724 * e1000g_unicst_find - Find the slot for the specified unicast address 2725 */ 2726 static int 2727 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr) 2728 { 2729 int slot; 2730 2731 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2732 if ((Adapter->unicst_addr[slot].mac.set == 1) && 2733 (bcmp(Adapter->unicst_addr[slot].mac.addr, 2734 mac_addr, ETHERADDRL) == 0)) 2735 return (slot); 2736 } 2737 2738 return (-1); 2739 } 2740 2741 /* 2742 * Entry points to add and remove a MAC address to a ring group. 2743 * The caller takes care of adding and removing the MAC addresses 2744 * to the filter via these two routines. 2745 */ 2746 2747 static int 2748 e1000g_addmac(void *arg, const uint8_t *mac_addr) 2749 { 2750 struct e1000g *Adapter = (struct e1000g *)arg; 2751 int slot, err; 2752 2753 rw_enter(&Adapter->chip_lock, RW_WRITER); 2754 2755 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2756 rw_exit(&Adapter->chip_lock); 2757 return (ECANCELED); 2758 } 2759 2760 if (e1000g_unicst_find(Adapter, mac_addr) != -1) { 2761 /* The same address is already in slot */ 2762 rw_exit(&Adapter->chip_lock); 2763 return (0); 2764 } 2765 2766 if (Adapter->unicst_avail == 0) { 2767 /* no slots available */ 2768 rw_exit(&Adapter->chip_lock); 2769 return (ENOSPC); 2770 } 2771 2772 /* Search for a free slot */ 2773 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2774 if (Adapter->unicst_addr[slot].mac.set == 0) 2775 break; 2776 } 2777 ASSERT(slot < Adapter->unicst_total); 2778 2779 err = e1000g_unicst_set(Adapter, mac_addr, slot); 2780 if (err == 0) 2781 Adapter->unicst_avail--; 2782 2783 rw_exit(&Adapter->chip_lock); 2784 2785 return (err); 2786 } 2787 2788 static int 2789 e1000g_remmac(void *arg, const uint8_t *mac_addr) 2790 { 2791 struct e1000g *Adapter = (struct e1000g *)arg; 2792 int slot, err; 2793 2794 rw_enter(&Adapter->chip_lock, RW_WRITER); 2795 2796 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2797 rw_exit(&Adapter->chip_lock); 2798 return (ECANCELED); 2799 } 2800 2801 slot = e1000g_unicst_find(Adapter, mac_addr); 2802 if (slot == -1) { 2803 rw_exit(&Adapter->chip_lock); 2804 return (EINVAL); 2805 } 2806 2807 ASSERT(Adapter->unicst_addr[slot].mac.set); 2808 2809 /* Clear this slot */ 2810 err = e1000g_unicst_set(Adapter, NULL, slot); 2811 if (err == 0) 2812 Adapter->unicst_avail++; 2813 2814 rw_exit(&Adapter->chip_lock); 2815 2816 return (err); 2817 } 2818 2819 static int 2820 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num) 2821 { 2822 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh; 2823 2824 mutex_enter(&rx_ring->rx_lock); 2825 rx_ring->ring_gen_num = mr_gen_num; 2826 mutex_exit(&rx_ring->rx_lock); 2827 return (0); 2828 } 2829 2830 /* 2831 * Callback funtion for MAC layer to register all rings. 2832 * 2833 * The hardware supports a single group with currently only one ring 2834 * available. 2835 * Though not offering virtualization ability per se, exposing the 2836 * group/ring still enables the polling and interrupt toggling. 2837 */ 2838 /* ARGSUSED */ 2839 void 2840 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index, 2841 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh) 2842 { 2843 struct e1000g *Adapter = (struct e1000g *)arg; 2844 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 2845 mac_intr_t *mintr; 2846 2847 /* 2848 * We advertised only RX group/rings, so the MAC framework shouldn't 2849 * ask for any thing else. 2850 */ 2851 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0); 2852 2853 rx_ring->mrh = rx_ring->mrh_init = rh; 2854 infop->mri_driver = (mac_ring_driver_t)rx_ring; 2855 infop->mri_start = e1000g_ring_start; 2856 infop->mri_stop = NULL; 2857 infop->mri_poll = e1000g_poll_ring; 2858 2859 /* Ring level interrupts */ 2860 mintr = &infop->mri_intr; 2861 mintr->mi_handle = (mac_intr_handle_t)rx_ring; 2862 mintr->mi_enable = e1000g_rx_ring_intr_enable; 2863 mintr->mi_disable = e1000g_rx_ring_intr_disable; 2864 } 2865 2866 /* ARGSUSED */ 2867 static void 2868 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index, 2869 mac_group_info_t *infop, mac_group_handle_t gh) 2870 { 2871 struct e1000g *Adapter = (struct e1000g *)arg; 2872 mac_intr_t *mintr; 2873 2874 /* 2875 * We advertised a single RX ring. Getting a request for anything else 2876 * signifies a bug in the MAC framework. 2877 */ 2878 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0); 2879 2880 Adapter->rx_group = gh; 2881 2882 infop->mgi_driver = (mac_group_driver_t)Adapter; 2883 infop->mgi_start = NULL; 2884 infop->mgi_stop = NULL; 2885 infop->mgi_addmac = e1000g_addmac; 2886 infop->mgi_remmac = e1000g_remmac; 2887 infop->mgi_count = 1; 2888 2889 /* Group level interrupts */ 2890 mintr = &infop->mgi_intr; 2891 mintr->mi_handle = (mac_intr_handle_t)Adapter; 2892 mintr->mi_enable = e1000g_rx_group_intr_enable; 2893 mintr->mi_disable = e1000g_rx_group_intr_disable; 2894 } 2895 2896 static boolean_t 2897 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2898 { 2899 struct e1000g *Adapter = (struct e1000g *)arg; 2900 2901 switch (cap) { 2902 case MAC_CAPAB_HCKSUM: { 2903 uint32_t *txflags = cap_data; 2904 2905 if (Adapter->tx_hcksum_enable) 2906 *txflags = HCKSUM_IPHDRCKSUM | 2907 HCKSUM_INET_PARTIAL; 2908 else 2909 return (B_FALSE); 2910 break; 2911 } 2912 2913 case MAC_CAPAB_LSO: { 2914 mac_capab_lso_t *cap_lso = cap_data; 2915 2916 if (Adapter->lso_enable) { 2917 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2918 cap_lso->lso_basic_tcp_ipv4.lso_max = 2919 E1000_LSO_MAXLEN; 2920 } else 2921 return (B_FALSE); 2922 break; 2923 } 2924 case MAC_CAPAB_RINGS: { 2925 mac_capab_rings_t *cap_rings = cap_data; 2926 2927 /* No TX rings exposed yet */ 2928 if (cap_rings->mr_type != MAC_RING_TYPE_RX) 2929 return (B_FALSE); 2930 2931 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC; 2932 cap_rings->mr_rnum = 1; 2933 cap_rings->mr_gnum = 1; 2934 cap_rings->mr_rget = e1000g_fill_ring; 2935 cap_rings->mr_gget = e1000g_fill_group; 2936 break; 2937 } 2938 default: 2939 return (B_FALSE); 2940 } 2941 return (B_TRUE); 2942 } 2943 2944 static boolean_t 2945 e1000g_param_locked(mac_prop_id_t pr_num) 2946 { 2947 /* 2948 * All en_* parameters are locked (read-only) while 2949 * the device is in any sort of loopback mode ... 2950 */ 2951 switch (pr_num) { 2952 case MAC_PROP_EN_1000FDX_CAP: 2953 case MAC_PROP_EN_1000HDX_CAP: 2954 case MAC_PROP_EN_100FDX_CAP: 2955 case MAC_PROP_EN_100HDX_CAP: 2956 case MAC_PROP_EN_10FDX_CAP: 2957 case MAC_PROP_EN_10HDX_CAP: 2958 case MAC_PROP_AUTONEG: 2959 case MAC_PROP_FLOWCTRL: 2960 return (B_TRUE); 2961 } 2962 return (B_FALSE); 2963 } 2964 2965 /* 2966 * callback function for set/get of properties 2967 */ 2968 static int 2969 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2970 uint_t pr_valsize, const void *pr_val) 2971 { 2972 struct e1000g *Adapter = arg; 2973 struct e1000_hw *hw = &Adapter->shared; 2974 struct e1000_fc_info *fc = &Adapter->shared.fc; 2975 int err = 0; 2976 link_flowctrl_t flowctrl; 2977 uint32_t cur_mtu, new_mtu; 2978 2979 rw_enter(&Adapter->chip_lock, RW_WRITER); 2980 2981 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2982 rw_exit(&Adapter->chip_lock); 2983 return (ECANCELED); 2984 } 2985 2986 if (Adapter->loopback_mode != E1000G_LB_NONE && 2987 e1000g_param_locked(pr_num)) { 2988 /* 2989 * All en_* parameters are locked (read-only) 2990 * while the device is in any sort of loopback mode. 2991 */ 2992 rw_exit(&Adapter->chip_lock); 2993 return (EBUSY); 2994 } 2995 2996 switch (pr_num) { 2997 case MAC_PROP_EN_1000FDX_CAP: 2998 if (hw->phy.media_type != e1000_media_type_copper) { 2999 err = ENOTSUP; 3000 break; 3001 } 3002 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 3003 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 3004 goto reset; 3005 case MAC_PROP_EN_100FDX_CAP: 3006 if (hw->phy.media_type != e1000_media_type_copper) { 3007 err = ENOTSUP; 3008 break; 3009 } 3010 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 3011 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 3012 goto reset; 3013 case MAC_PROP_EN_100HDX_CAP: 3014 if (hw->phy.media_type != e1000_media_type_copper) { 3015 err = ENOTSUP; 3016 break; 3017 } 3018 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 3019 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 3020 goto reset; 3021 case MAC_PROP_EN_10FDX_CAP: 3022 if (hw->phy.media_type != e1000_media_type_copper) { 3023 err = ENOTSUP; 3024 break; 3025 } 3026 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 3027 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 3028 goto reset; 3029 case MAC_PROP_EN_10HDX_CAP: 3030 if (hw->phy.media_type != e1000_media_type_copper) { 3031 err = ENOTSUP; 3032 break; 3033 } 3034 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 3035 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 3036 goto reset; 3037 case MAC_PROP_AUTONEG: 3038 if (hw->phy.media_type != e1000_media_type_copper) { 3039 err = ENOTSUP; 3040 break; 3041 } 3042 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 3043 goto reset; 3044 case MAC_PROP_FLOWCTRL: 3045 fc->send_xon = B_TRUE; 3046 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 3047 3048 switch (flowctrl) { 3049 default: 3050 err = EINVAL; 3051 break; 3052 case LINK_FLOWCTRL_NONE: 3053 fc->requested_mode = e1000_fc_none; 3054 break; 3055 case LINK_FLOWCTRL_RX: 3056 fc->requested_mode = e1000_fc_rx_pause; 3057 break; 3058 case LINK_FLOWCTRL_TX: 3059 fc->requested_mode = e1000_fc_tx_pause; 3060 break; 3061 case LINK_FLOWCTRL_BI: 3062 fc->requested_mode = e1000_fc_full; 3063 break; 3064 } 3065 reset: 3066 if (err == 0) { 3067 /* check PCH limits & reset the link */ 3068 e1000g_pch_limits(Adapter); 3069 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 3070 err = EINVAL; 3071 } 3072 break; 3073 case MAC_PROP_ADV_1000FDX_CAP: 3074 case MAC_PROP_ADV_1000HDX_CAP: 3075 case MAC_PROP_ADV_100FDX_CAP: 3076 case MAC_PROP_ADV_100HDX_CAP: 3077 case MAC_PROP_ADV_10FDX_CAP: 3078 case MAC_PROP_ADV_10HDX_CAP: 3079 case MAC_PROP_EN_1000HDX_CAP: 3080 case MAC_PROP_STATUS: 3081 case MAC_PROP_SPEED: 3082 case MAC_PROP_DUPLEX: 3083 err = ENOTSUP; /* read-only prop. Can't set this. */ 3084 break; 3085 case MAC_PROP_MTU: 3086 /* adapter must be stopped for an MTU change */ 3087 if (Adapter->e1000g_state & E1000G_STARTED) { 3088 err = EBUSY; 3089 break; 3090 } 3091 3092 cur_mtu = Adapter->default_mtu; 3093 3094 /* get new requested MTU */ 3095 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 3096 if (new_mtu == cur_mtu) { 3097 err = 0; 3098 break; 3099 } 3100 3101 if ((new_mtu < DEFAULT_MTU) || 3102 (new_mtu > Adapter->max_mtu)) { 3103 err = EINVAL; 3104 break; 3105 } 3106 3107 /* inform MAC framework of new MTU */ 3108 err = mac_maxsdu_update(Adapter->mh, new_mtu); 3109 3110 if (err == 0) { 3111 Adapter->default_mtu = new_mtu; 3112 Adapter->max_frame_size = 3113 e1000g_mtu2maxframe(new_mtu); 3114 3115 /* 3116 * check PCH limits & set buffer sizes to 3117 * match new MTU 3118 */ 3119 e1000g_pch_limits(Adapter); 3120 e1000g_set_bufsize(Adapter); 3121 3122 /* 3123 * decrease the number of descriptors and free 3124 * packets for jumbo frames to reduce tx/rx 3125 * resource consumption 3126 */ 3127 if (Adapter->max_frame_size >= 3128 (FRAME_SIZE_UPTO_4K - 3129 E1000G_IPALIGNPRESERVEROOM)) { 3130 3131 if (Adapter->tx_desc_num_flag == 0) 3132 Adapter->tx_desc_num = 3133 DEFAULT_JUMBO_NUM_TX_DESC; 3134 3135 if (Adapter->rx_desc_num_flag == 0) 3136 Adapter->rx_desc_num = 3137 DEFAULT_JUMBO_NUM_RX_DESC; 3138 3139 if (Adapter->tx_buf_num_flag == 0) 3140 Adapter->tx_freelist_num = 3141 DEFAULT_JUMBO_NUM_TX_BUF; 3142 3143 if (Adapter->rx_buf_num_flag == 0) 3144 Adapter->rx_freelist_num = 3145 DEFAULT_JUMBO_NUM_RX_BUF; 3146 } else { 3147 if (Adapter->tx_desc_num_flag == 0) 3148 Adapter->tx_desc_num = 3149 DEFAULT_NUM_TX_DESCRIPTOR; 3150 3151 if (Adapter->rx_desc_num_flag == 0) 3152 Adapter->rx_desc_num = 3153 DEFAULT_NUM_RX_DESCRIPTOR; 3154 3155 if (Adapter->tx_buf_num_flag == 0) 3156 Adapter->tx_freelist_num = 3157 DEFAULT_NUM_TX_FREELIST; 3158 3159 if (Adapter->rx_buf_num_flag == 0) 3160 Adapter->rx_freelist_num = 3161 DEFAULT_NUM_RX_FREELIST; 3162 } 3163 } 3164 break; 3165 case MAC_PROP_PRIVATE: 3166 err = e1000g_set_priv_prop(Adapter, pr_name, 3167 pr_valsize, pr_val); 3168 break; 3169 default: 3170 err = ENOTSUP; 3171 break; 3172 } 3173 rw_exit(&Adapter->chip_lock); 3174 return (err); 3175 } 3176 3177 static int 3178 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3179 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3180 { 3181 struct e1000g *Adapter = arg; 3182 struct e1000_fc_info *fc = &Adapter->shared.fc; 3183 struct e1000_hw *hw = &Adapter->shared; 3184 int err = 0; 3185 link_flowctrl_t flowctrl; 3186 uint64_t tmp = 0; 3187 3188 if (pr_valsize == 0) 3189 return (EINVAL); 3190 3191 *perm = MAC_PROP_PERM_RW; 3192 3193 bzero(pr_val, pr_valsize); 3194 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 3195 return (e1000g_get_def_val(Adapter, pr_num, 3196 pr_valsize, pr_val)); 3197 } 3198 3199 switch (pr_num) { 3200 case MAC_PROP_DUPLEX: 3201 *perm = MAC_PROP_PERM_READ; 3202 if (pr_valsize >= sizeof (link_duplex_t)) { 3203 bcopy(&Adapter->link_duplex, pr_val, 3204 sizeof (link_duplex_t)); 3205 } else 3206 err = EINVAL; 3207 break; 3208 case MAC_PROP_SPEED: 3209 *perm = MAC_PROP_PERM_READ; 3210 if (pr_valsize >= sizeof (uint64_t)) { 3211 tmp = Adapter->link_speed * 1000000ull; 3212 bcopy(&tmp, pr_val, sizeof (tmp)); 3213 } else 3214 err = EINVAL; 3215 break; 3216 case MAC_PROP_AUTONEG: 3217 if (hw->phy.media_type != e1000_media_type_copper) 3218 *perm = MAC_PROP_PERM_READ; 3219 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 3220 break; 3221 case MAC_PROP_FLOWCTRL: 3222 if (pr_valsize >= sizeof (link_flowctrl_t)) { 3223 switch (fc->current_mode) { 3224 case e1000_fc_none: 3225 flowctrl = LINK_FLOWCTRL_NONE; 3226 break; 3227 case e1000_fc_rx_pause: 3228 flowctrl = LINK_FLOWCTRL_RX; 3229 break; 3230 case e1000_fc_tx_pause: 3231 flowctrl = LINK_FLOWCTRL_TX; 3232 break; 3233 case e1000_fc_full: 3234 flowctrl = LINK_FLOWCTRL_BI; 3235 break; 3236 } 3237 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 3238 } else 3239 err = EINVAL; 3240 break; 3241 case MAC_PROP_ADV_1000FDX_CAP: 3242 *perm = MAC_PROP_PERM_READ; 3243 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 3244 break; 3245 case MAC_PROP_EN_1000FDX_CAP: 3246 if (hw->phy.media_type != e1000_media_type_copper) 3247 *perm = MAC_PROP_PERM_READ; 3248 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 3249 break; 3250 case MAC_PROP_ADV_1000HDX_CAP: 3251 *perm = MAC_PROP_PERM_READ; 3252 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 3253 break; 3254 case MAC_PROP_EN_1000HDX_CAP: 3255 *perm = MAC_PROP_PERM_READ; 3256 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 3257 break; 3258 case MAC_PROP_ADV_100FDX_CAP: 3259 *perm = MAC_PROP_PERM_READ; 3260 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 3261 break; 3262 case MAC_PROP_EN_100FDX_CAP: 3263 if (hw->phy.media_type != e1000_media_type_copper) 3264 *perm = MAC_PROP_PERM_READ; 3265 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 3266 break; 3267 case MAC_PROP_ADV_100HDX_CAP: 3268 *perm = MAC_PROP_PERM_READ; 3269 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 3270 break; 3271 case MAC_PROP_EN_100HDX_CAP: 3272 if (hw->phy.media_type != e1000_media_type_copper) 3273 *perm = MAC_PROP_PERM_READ; 3274 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 3275 break; 3276 case MAC_PROP_ADV_10FDX_CAP: 3277 *perm = MAC_PROP_PERM_READ; 3278 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 3279 break; 3280 case MAC_PROP_EN_10FDX_CAP: 3281 if (hw->phy.media_type != e1000_media_type_copper) 3282 *perm = MAC_PROP_PERM_READ; 3283 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 3284 break; 3285 case MAC_PROP_ADV_10HDX_CAP: 3286 *perm = MAC_PROP_PERM_READ; 3287 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 3288 break; 3289 case MAC_PROP_EN_10HDX_CAP: 3290 if (hw->phy.media_type != e1000_media_type_copper) 3291 *perm = MAC_PROP_PERM_READ; 3292 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 3293 break; 3294 case MAC_PROP_ADV_100T4_CAP: 3295 case MAC_PROP_EN_100T4_CAP: 3296 *perm = MAC_PROP_PERM_READ; 3297 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 3298 break; 3299 case MAC_PROP_PRIVATE: 3300 err = e1000g_get_priv_prop(Adapter, pr_name, 3301 pr_flags, pr_valsize, pr_val, perm); 3302 break; 3303 case MAC_PROP_MTU: { 3304 struct e1000_mac_info *mac = &Adapter->shared.mac; 3305 struct e1000_phy_info *phy = &Adapter->shared.phy; 3306 mac_propval_range_t range; 3307 3308 if (!(pr_flags & MAC_PROP_POSSIBLE)) 3309 return (ENOTSUP); 3310 if (pr_valsize < sizeof (mac_propval_range_t)) 3311 return (EINVAL); 3312 range.mpr_count = 1; 3313 range.mpr_type = MAC_PROPVAL_UINT32; 3314 range.range_uint32[0].mpur_min = DEFAULT_MTU; 3315 range.range_uint32[0].mpur_max = Adapter->max_mtu; 3316 /* following MAC type do not support jumbo frames */ 3317 if ((mac->type == e1000_ich8lan) || 3318 ((mac->type == e1000_ich9lan) && (phy->type == 3319 e1000_phy_ife))) { 3320 range.range_uint32[0].mpur_max = DEFAULT_MTU; 3321 } 3322 bcopy(&range, pr_val, sizeof (range)); 3323 break; 3324 } 3325 default: 3326 err = ENOTSUP; 3327 break; 3328 } 3329 return (err); 3330 } 3331 3332 /* ARGSUSED2 */ 3333 static int 3334 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 3335 uint_t pr_valsize, const void *pr_val) 3336 { 3337 int err = 0; 3338 long result; 3339 struct e1000_hw *hw = &Adapter->shared; 3340 3341 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3342 if (pr_val == NULL) { 3343 err = EINVAL; 3344 return (err); 3345 } 3346 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3347 if (result < MIN_TX_BCOPY_THRESHOLD || 3348 result > MAX_TX_BCOPY_THRESHOLD) 3349 err = EINVAL; 3350 else { 3351 Adapter->tx_bcopy_thresh = (uint32_t)result; 3352 } 3353 return (err); 3354 } 3355 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3356 if (pr_val == NULL) { 3357 err = EINVAL; 3358 return (err); 3359 } 3360 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3361 if (result < 0 || result > 1) 3362 err = EINVAL; 3363 else { 3364 Adapter->tx_intr_enable = (result == 1) ? 3365 B_TRUE: B_FALSE; 3366 if (Adapter->tx_intr_enable) 3367 e1000g_mask_tx_interrupt(Adapter); 3368 else 3369 e1000g_clear_tx_interrupt(Adapter); 3370 if (e1000g_check_acc_handle( 3371 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3372 ddi_fm_service_impact(Adapter->dip, 3373 DDI_SERVICE_DEGRADED); 3374 err = EIO; 3375 } 3376 } 3377 return (err); 3378 } 3379 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3380 if (pr_val == NULL) { 3381 err = EINVAL; 3382 return (err); 3383 } 3384 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3385 if (result < MIN_TX_INTR_DELAY || 3386 result > MAX_TX_INTR_DELAY) 3387 err = EINVAL; 3388 else { 3389 Adapter->tx_intr_delay = (uint32_t)result; 3390 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 3391 if (e1000g_check_acc_handle( 3392 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3393 ddi_fm_service_impact(Adapter->dip, 3394 DDI_SERVICE_DEGRADED); 3395 err = EIO; 3396 } 3397 } 3398 return (err); 3399 } 3400 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3401 if (pr_val == NULL) { 3402 err = EINVAL; 3403 return (err); 3404 } 3405 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3406 if (result < MIN_TX_INTR_ABS_DELAY || 3407 result > MAX_TX_INTR_ABS_DELAY) 3408 err = EINVAL; 3409 else { 3410 Adapter->tx_intr_abs_delay = (uint32_t)result; 3411 E1000_WRITE_REG(hw, E1000_TADV, 3412 Adapter->tx_intr_abs_delay); 3413 if (e1000g_check_acc_handle( 3414 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3415 ddi_fm_service_impact(Adapter->dip, 3416 DDI_SERVICE_DEGRADED); 3417 err = EIO; 3418 } 3419 } 3420 return (err); 3421 } 3422 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3423 if (pr_val == NULL) { 3424 err = EINVAL; 3425 return (err); 3426 } 3427 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3428 if (result < MIN_RX_BCOPY_THRESHOLD || 3429 result > MAX_RX_BCOPY_THRESHOLD) 3430 err = EINVAL; 3431 else 3432 Adapter->rx_bcopy_thresh = (uint32_t)result; 3433 return (err); 3434 } 3435 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3436 if (pr_val == NULL) { 3437 err = EINVAL; 3438 return (err); 3439 } 3440 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3441 if (result < MIN_RX_LIMIT_ON_INTR || 3442 result > MAX_RX_LIMIT_ON_INTR) 3443 err = EINVAL; 3444 else 3445 Adapter->rx_limit_onintr = (uint32_t)result; 3446 return (err); 3447 } 3448 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3449 if (pr_val == NULL) { 3450 err = EINVAL; 3451 return (err); 3452 } 3453 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3454 if (result < MIN_RX_INTR_DELAY || 3455 result > MAX_RX_INTR_DELAY) 3456 err = EINVAL; 3457 else { 3458 Adapter->rx_intr_delay = (uint32_t)result; 3459 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3460 if (e1000g_check_acc_handle( 3461 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3462 ddi_fm_service_impact(Adapter->dip, 3463 DDI_SERVICE_DEGRADED); 3464 err = EIO; 3465 } 3466 } 3467 return (err); 3468 } 3469 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3470 if (pr_val == NULL) { 3471 err = EINVAL; 3472 return (err); 3473 } 3474 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3475 if (result < MIN_RX_INTR_ABS_DELAY || 3476 result > MAX_RX_INTR_ABS_DELAY) 3477 err = EINVAL; 3478 else { 3479 Adapter->rx_intr_abs_delay = (uint32_t)result; 3480 E1000_WRITE_REG(hw, E1000_RADV, 3481 Adapter->rx_intr_abs_delay); 3482 if (e1000g_check_acc_handle( 3483 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3484 ddi_fm_service_impact(Adapter->dip, 3485 DDI_SERVICE_DEGRADED); 3486 err = EIO; 3487 } 3488 } 3489 return (err); 3490 } 3491 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3492 if (pr_val == NULL) { 3493 err = EINVAL; 3494 return (err); 3495 } 3496 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3497 if (result < MIN_INTR_THROTTLING || 3498 result > MAX_INTR_THROTTLING) 3499 err = EINVAL; 3500 else { 3501 if (hw->mac.type >= e1000_82540) { 3502 Adapter->intr_throttling_rate = 3503 (uint32_t)result; 3504 E1000_WRITE_REG(hw, E1000_ITR, 3505 Adapter->intr_throttling_rate); 3506 if (e1000g_check_acc_handle( 3507 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3508 ddi_fm_service_impact(Adapter->dip, 3509 DDI_SERVICE_DEGRADED); 3510 err = EIO; 3511 } 3512 } else 3513 err = EINVAL; 3514 } 3515 return (err); 3516 } 3517 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3518 if (pr_val == NULL) { 3519 err = EINVAL; 3520 return (err); 3521 } 3522 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3523 if (result < 0 || result > 1) 3524 err = EINVAL; 3525 else { 3526 if (hw->mac.type >= e1000_82540) { 3527 Adapter->intr_adaptive = (result == 1) ? 3528 B_TRUE : B_FALSE; 3529 } else { 3530 err = EINVAL; 3531 } 3532 } 3533 return (err); 3534 } 3535 return (ENOTSUP); 3536 } 3537 3538 static int 3539 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3540 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3541 { 3542 int err = ENOTSUP; 3543 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3544 int value; 3545 3546 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3547 *perm = MAC_PROP_PERM_READ; 3548 if (is_default) 3549 goto done; 3550 value = Adapter->param_adv_pause; 3551 err = 0; 3552 goto done; 3553 } 3554 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3555 *perm = MAC_PROP_PERM_READ; 3556 if (is_default) 3557 goto done; 3558 value = Adapter->param_adv_asym_pause; 3559 err = 0; 3560 goto done; 3561 } 3562 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3563 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3564 Adapter->tx_bcopy_thresh); 3565 err = 0; 3566 goto done; 3567 } 3568 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3569 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3570 Adapter->tx_intr_enable); 3571 err = 0; 3572 goto done; 3573 } 3574 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3575 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3576 Adapter->tx_intr_delay); 3577 err = 0; 3578 goto done; 3579 } 3580 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3581 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3582 Adapter->tx_intr_abs_delay); 3583 err = 0; 3584 goto done; 3585 } 3586 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3587 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3588 Adapter->rx_bcopy_thresh); 3589 err = 0; 3590 goto done; 3591 } 3592 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3593 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3594 Adapter->rx_limit_onintr); 3595 err = 0; 3596 goto done; 3597 } 3598 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3599 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3600 Adapter->rx_intr_delay); 3601 err = 0; 3602 goto done; 3603 } 3604 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3605 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3606 Adapter->rx_intr_abs_delay); 3607 err = 0; 3608 goto done; 3609 } 3610 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3611 value = (is_default ? DEFAULT_INTR_THROTTLING : 3612 Adapter->intr_throttling_rate); 3613 err = 0; 3614 goto done; 3615 } 3616 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3617 value = (is_default ? 1 : Adapter->intr_adaptive); 3618 err = 0; 3619 goto done; 3620 } 3621 done: 3622 if (err == 0) { 3623 (void) snprintf(pr_val, pr_valsize, "%d", value); 3624 } 3625 return (err); 3626 } 3627 3628 /* 3629 * e1000g_get_conf - get configurations set in e1000g.conf 3630 * This routine gets user-configured values out of the configuration 3631 * file e1000g.conf. 3632 * 3633 * For each configurable value, there is a minimum, a maximum, and a 3634 * default. 3635 * If user does not configure a value, use the default. 3636 * If user configures below the minimum, use the minumum. 3637 * If user configures above the maximum, use the maxumum. 3638 */ 3639 static void 3640 e1000g_get_conf(struct e1000g *Adapter) 3641 { 3642 struct e1000_hw *hw = &Adapter->shared; 3643 boolean_t tbi_compatibility = B_FALSE; 3644 boolean_t is_jumbo = B_FALSE; 3645 int propval; 3646 /* 3647 * decrease the number of descriptors and free packets 3648 * for jumbo frames to reduce tx/rx resource consumption 3649 */ 3650 if (Adapter->max_frame_size >= 3651 (FRAME_SIZE_UPTO_4K - 3652 E1000G_IPALIGNPRESERVEROOM)) { 3653 is_jumbo = B_TRUE; 3654 } 3655 3656 /* 3657 * get each configurable property from e1000g.conf 3658 */ 3659 3660 /* 3661 * NumTxDescriptors 3662 */ 3663 Adapter->tx_desc_num_flag = 3664 e1000g_get_prop(Adapter, "NumTxDescriptors", 3665 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3666 is_jumbo ? DEFAULT_JUMBO_NUM_TX_DESC 3667 : DEFAULT_NUM_TX_DESCRIPTOR, &propval); 3668 Adapter->tx_desc_num = propval; 3669 3670 /* 3671 * NumRxDescriptors 3672 */ 3673 Adapter->rx_desc_num_flag = 3674 e1000g_get_prop(Adapter, "NumRxDescriptors", 3675 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3676 is_jumbo ? DEFAULT_JUMBO_NUM_RX_DESC 3677 : DEFAULT_NUM_RX_DESCRIPTOR, &propval); 3678 Adapter->rx_desc_num = propval; 3679 3680 /* 3681 * NumRxFreeList 3682 */ 3683 Adapter->rx_buf_num_flag = 3684 e1000g_get_prop(Adapter, "NumRxFreeList", 3685 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3686 is_jumbo ? DEFAULT_JUMBO_NUM_RX_BUF 3687 : DEFAULT_NUM_RX_FREELIST, &propval); 3688 Adapter->rx_freelist_num = propval; 3689 3690 /* 3691 * NumTxPacketList 3692 */ 3693 Adapter->tx_buf_num_flag = 3694 e1000g_get_prop(Adapter, "NumTxPacketList", 3695 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3696 is_jumbo ? DEFAULT_JUMBO_NUM_TX_BUF 3697 : DEFAULT_NUM_TX_FREELIST, &propval); 3698 Adapter->tx_freelist_num = propval; 3699 3700 /* 3701 * FlowControl 3702 */ 3703 hw->fc.send_xon = B_TRUE; 3704 (void) e1000g_get_prop(Adapter, "FlowControl", 3705 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL, &propval); 3706 hw->fc.requested_mode = propval; 3707 /* 4 is the setting that says "let the eeprom decide" */ 3708 if (hw->fc.requested_mode == 4) 3709 hw->fc.requested_mode = e1000_fc_default; 3710 3711 /* 3712 * Max Num Receive Packets on Interrupt 3713 */ 3714 (void) e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3715 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3716 DEFAULT_RX_LIMIT_ON_INTR, &propval); 3717 Adapter->rx_limit_onintr = propval; 3718 3719 /* 3720 * PHY master slave setting 3721 */ 3722 (void) e1000g_get_prop(Adapter, "SetMasterSlave", 3723 e1000_ms_hw_default, e1000_ms_auto, 3724 e1000_ms_hw_default, &propval); 3725 hw->phy.ms_type = propval; 3726 3727 /* 3728 * Parameter which controls TBI mode workaround, which is only 3729 * needed on certain switches such as Cisco 6500/Foundry 3730 */ 3731 (void) e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3732 0, 1, DEFAULT_TBI_COMPAT_ENABLE, &propval); 3733 tbi_compatibility = (propval == 1); 3734 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3735 3736 /* 3737 * MSI Enable 3738 */ 3739 (void) e1000g_get_prop(Adapter, "MSIEnable", 3740 0, 1, DEFAULT_MSI_ENABLE, &propval); 3741 Adapter->msi_enable = (propval == 1); 3742 3743 /* 3744 * Interrupt Throttling Rate 3745 */ 3746 (void) e1000g_get_prop(Adapter, "intr_throttling_rate", 3747 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3748 DEFAULT_INTR_THROTTLING, &propval); 3749 Adapter->intr_throttling_rate = propval; 3750 3751 /* 3752 * Adaptive Interrupt Blanking Enable/Disable 3753 * It is enabled by default 3754 */ 3755 (void) e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1, 3756 &propval); 3757 Adapter->intr_adaptive = (propval == 1); 3758 3759 /* 3760 * Hardware checksum enable/disable parameter 3761 */ 3762 (void) e1000g_get_prop(Adapter, "tx_hcksum_enable", 3763 0, 1, DEFAULT_TX_HCKSUM_ENABLE, &propval); 3764 Adapter->tx_hcksum_enable = (propval == 1); 3765 /* 3766 * Checksum on/off selection via global parameters. 3767 * 3768 * If the chip is flagged as not capable of (correctly) 3769 * handling checksumming, we don't enable it on either 3770 * Rx or Tx side. Otherwise, we take this chip's settings 3771 * from the patchable global defaults. 3772 * 3773 * We advertise our capabilities only if TX offload is 3774 * enabled. On receive, the stack will accept checksummed 3775 * packets anyway, even if we haven't said we can deliver 3776 * them. 3777 */ 3778 switch (hw->mac.type) { 3779 case e1000_82540: 3780 case e1000_82544: 3781 case e1000_82545: 3782 case e1000_82545_rev_3: 3783 case e1000_82546: 3784 case e1000_82546_rev_3: 3785 case e1000_82571: 3786 case e1000_82572: 3787 case e1000_82573: 3788 case e1000_80003es2lan: 3789 break; 3790 /* 3791 * For the following Intel PRO/1000 chipsets, we have not 3792 * tested the hardware checksum offload capability, so we 3793 * disable the capability for them. 3794 * e1000_82542, 3795 * e1000_82543, 3796 * e1000_82541, 3797 * e1000_82541_rev_2, 3798 * e1000_82547, 3799 * e1000_82547_rev_2, 3800 */ 3801 default: 3802 Adapter->tx_hcksum_enable = B_FALSE; 3803 } 3804 3805 /* 3806 * Large Send Offloading(LSO) Enable/Disable 3807 * If the tx hardware checksum is not enabled, LSO should be 3808 * disabled. 3809 */ 3810 (void) e1000g_get_prop(Adapter, "lso_enable", 3811 0, 1, DEFAULT_LSO_ENABLE, &propval); 3812 Adapter->lso_enable = (propval == 1); 3813 3814 switch (hw->mac.type) { 3815 case e1000_82546: 3816 case e1000_82546_rev_3: 3817 if (Adapter->lso_enable) 3818 Adapter->lso_premature_issue = B_TRUE; 3819 /* FALLTHRU */ 3820 case e1000_82571: 3821 case e1000_82572: 3822 case e1000_82573: 3823 case e1000_80003es2lan: 3824 break; 3825 default: 3826 Adapter->lso_enable = B_FALSE; 3827 } 3828 3829 if (!Adapter->tx_hcksum_enable) { 3830 Adapter->lso_premature_issue = B_FALSE; 3831 Adapter->lso_enable = B_FALSE; 3832 } 3833 3834 /* 3835 * If mem_workaround_82546 is enabled, the rx buffer allocated by 3836 * e1000_82545, e1000_82546 and e1000_82546_rev_3 3837 * will not cross 64k boundary. 3838 */ 3839 (void) e1000g_get_prop(Adapter, "mem_workaround_82546", 3840 0, 1, DEFAULT_MEM_WORKAROUND_82546, &propval); 3841 Adapter->mem_workaround_82546 = (propval == 1); 3842 3843 /* 3844 * Max number of multicast addresses 3845 */ 3846 (void) e1000g_get_prop(Adapter, "mcast_max_num", 3847 MIN_MCAST_NUM, MAX_MCAST_NUM, hw->mac.mta_reg_count * 32, 3848 &propval); 3849 Adapter->mcast_max_num = propval; 3850 } 3851 3852 /* 3853 * e1000g_get_prop - routine to read properties 3854 * 3855 * Get a user-configure property value out of the configuration 3856 * file e1000g.conf. 3857 * 3858 * Caller provides name of the property, a default value, a minimum 3859 * value, a maximum value and a pointer to the returned property 3860 * value. 3861 * 3862 * Return B_TRUE if the configured value of the property is not a default 3863 * value, otherwise return B_FALSE. 3864 */ 3865 static boolean_t 3866 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3867 char *propname, /* name of the property */ 3868 int minval, /* minimum acceptable value */ 3869 int maxval, /* maximim acceptable value */ 3870 int defval, /* default value */ 3871 int *propvalue) /* property value return to caller */ 3872 { 3873 int propval; /* value returned for requested property */ 3874 int *props; /* point to array of properties returned */ 3875 uint_t nprops; /* number of property value returned */ 3876 boolean_t ret = B_TRUE; 3877 3878 /* 3879 * get the array of properties from the config file 3880 */ 3881 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3882 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3883 /* got some properties, test if we got enough */ 3884 if (Adapter->instance < nprops) { 3885 propval = props[Adapter->instance]; 3886 } else { 3887 /* not enough properties configured */ 3888 propval = defval; 3889 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3890 "Not Enough %s values found in e1000g.conf" 3891 " - set to %d\n", 3892 propname, propval); 3893 ret = B_FALSE; 3894 } 3895 3896 /* free memory allocated for properties */ 3897 ddi_prop_free(props); 3898 3899 } else { 3900 propval = defval; 3901 ret = B_FALSE; 3902 } 3903 3904 /* 3905 * enforce limits 3906 */ 3907 if (propval > maxval) { 3908 propval = maxval; 3909 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3910 "Too High %s value in e1000g.conf - set to %d\n", 3911 propname, propval); 3912 } 3913 3914 if (propval < minval) { 3915 propval = minval; 3916 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3917 "Too Low %s value in e1000g.conf - set to %d\n", 3918 propname, propval); 3919 } 3920 3921 *propvalue = propval; 3922 return (ret); 3923 } 3924 3925 static boolean_t 3926 e1000g_link_check(struct e1000g *Adapter) 3927 { 3928 uint16_t speed, duplex, phydata; 3929 boolean_t link_changed = B_FALSE; 3930 struct e1000_hw *hw; 3931 uint32_t reg_tarc; 3932 3933 hw = &Adapter->shared; 3934 3935 if (e1000g_link_up(Adapter)) { 3936 /* 3937 * The Link is up, check whether it was marked as down earlier 3938 */ 3939 if (Adapter->link_state != LINK_STATE_UP) { 3940 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3941 Adapter->link_speed = speed; 3942 Adapter->link_duplex = duplex; 3943 Adapter->link_state = LINK_STATE_UP; 3944 link_changed = B_TRUE; 3945 3946 if (Adapter->link_speed == SPEED_1000) 3947 Adapter->stall_threshold = TX_STALL_TIME_2S; 3948 else 3949 Adapter->stall_threshold = TX_STALL_TIME_8S; 3950 3951 Adapter->tx_link_down_timeout = 0; 3952 3953 if ((hw->mac.type == e1000_82571) || 3954 (hw->mac.type == e1000_82572)) { 3955 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3956 if (speed == SPEED_1000) 3957 reg_tarc |= (1 << 21); 3958 else 3959 reg_tarc &= ~(1 << 21); 3960 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3961 } 3962 } 3963 Adapter->smartspeed = 0; 3964 } else { 3965 if (Adapter->link_state != LINK_STATE_DOWN) { 3966 Adapter->link_speed = 0; 3967 Adapter->link_duplex = 0; 3968 Adapter->link_state = LINK_STATE_DOWN; 3969 link_changed = B_TRUE; 3970 3971 /* 3972 * SmartSpeed workaround for Tabor/TanaX, When the 3973 * driver loses link disable auto master/slave 3974 * resolution. 3975 */ 3976 if (hw->phy.type == e1000_phy_igp) { 3977 (void) e1000_read_phy_reg(hw, 3978 PHY_1000T_CTRL, &phydata); 3979 phydata |= CR_1000T_MS_ENABLE; 3980 (void) e1000_write_phy_reg(hw, 3981 PHY_1000T_CTRL, phydata); 3982 } 3983 } else { 3984 e1000g_smartspeed(Adapter); 3985 } 3986 3987 if (Adapter->e1000g_state & E1000G_STARTED) { 3988 if (Adapter->tx_link_down_timeout < 3989 MAX_TX_LINK_DOWN_TIMEOUT) { 3990 Adapter->tx_link_down_timeout++; 3991 } else if (Adapter->tx_link_down_timeout == 3992 MAX_TX_LINK_DOWN_TIMEOUT) { 3993 e1000g_tx_clean(Adapter); 3994 Adapter->tx_link_down_timeout++; 3995 } 3996 } 3997 } 3998 3999 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4000 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4001 4002 return (link_changed); 4003 } 4004 4005 /* 4006 * e1000g_reset_link - Using the link properties to setup the link 4007 */ 4008 int 4009 e1000g_reset_link(struct e1000g *Adapter) 4010 { 4011 struct e1000_mac_info *mac; 4012 struct e1000_phy_info *phy; 4013 struct e1000_hw *hw; 4014 boolean_t invalid; 4015 4016 mac = &Adapter->shared.mac; 4017 phy = &Adapter->shared.phy; 4018 hw = &Adapter->shared; 4019 invalid = B_FALSE; 4020 4021 if (hw->phy.media_type != e1000_media_type_copper) 4022 goto out; 4023 4024 if (Adapter->param_adv_autoneg == 1) { 4025 mac->autoneg = B_TRUE; 4026 phy->autoneg_advertised = 0; 4027 4028 /* 4029 * 1000hdx is not supported for autonegotiation 4030 */ 4031 if (Adapter->param_adv_1000fdx == 1) 4032 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 4033 4034 if (Adapter->param_adv_100fdx == 1) 4035 phy->autoneg_advertised |= ADVERTISE_100_FULL; 4036 4037 if (Adapter->param_adv_100hdx == 1) 4038 phy->autoneg_advertised |= ADVERTISE_100_HALF; 4039 4040 if (Adapter->param_adv_10fdx == 1) 4041 phy->autoneg_advertised |= ADVERTISE_10_FULL; 4042 4043 if (Adapter->param_adv_10hdx == 1) 4044 phy->autoneg_advertised |= ADVERTISE_10_HALF; 4045 4046 if (phy->autoneg_advertised == 0) 4047 invalid = B_TRUE; 4048 } else { 4049 mac->autoneg = B_FALSE; 4050 4051 /* 4052 * For Intel copper cards, 1000fdx and 1000hdx are not 4053 * supported for forced link 4054 */ 4055 if (Adapter->param_adv_100fdx == 1) 4056 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4057 else if (Adapter->param_adv_100hdx == 1) 4058 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4059 else if (Adapter->param_adv_10fdx == 1) 4060 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4061 else if (Adapter->param_adv_10hdx == 1) 4062 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4063 else 4064 invalid = B_TRUE; 4065 4066 } 4067 4068 if (invalid) { 4069 e1000g_log(Adapter, CE_WARN, 4070 "Invalid link settings. Setup link to " 4071 "support autonegotiation with all link capabilities."); 4072 mac->autoneg = B_TRUE; 4073 phy->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 4074 } 4075 4076 out: 4077 return (e1000_setup_link(&Adapter->shared)); 4078 } 4079 4080 static void 4081 e1000g_timer_tx_resched(struct e1000g *Adapter) 4082 { 4083 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 4084 4085 rw_enter(&Adapter->chip_lock, RW_READER); 4086 4087 if (tx_ring->resched_needed && 4088 ((ddi_get_lbolt() - tx_ring->resched_timestamp) > 4089 drv_usectohz(1000000)) && 4090 (Adapter->e1000g_state & E1000G_STARTED) && 4091 (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) { 4092 tx_ring->resched_needed = B_FALSE; 4093 mac_tx_update(Adapter->mh); 4094 E1000G_STAT(tx_ring->stat_reschedule); 4095 E1000G_STAT(tx_ring->stat_timer_reschedule); 4096 } 4097 4098 rw_exit(&Adapter->chip_lock); 4099 } 4100 4101 static void 4102 e1000g_local_timer(void *ws) 4103 { 4104 struct e1000g *Adapter = (struct e1000g *)ws; 4105 struct e1000_hw *hw; 4106 e1000g_ether_addr_t ether_addr; 4107 boolean_t link_changed; 4108 4109 hw = &Adapter->shared; 4110 4111 if (Adapter->e1000g_state & E1000G_ERROR) { 4112 rw_enter(&Adapter->chip_lock, RW_WRITER); 4113 Adapter->e1000g_state &= ~E1000G_ERROR; 4114 rw_exit(&Adapter->chip_lock); 4115 4116 Adapter->reset_count++; 4117 if (e1000g_global_reset(Adapter)) { 4118 ddi_fm_service_impact(Adapter->dip, 4119 DDI_SERVICE_RESTORED); 4120 e1000g_timer_tx_resched(Adapter); 4121 } else 4122 ddi_fm_service_impact(Adapter->dip, 4123 DDI_SERVICE_LOST); 4124 return; 4125 } 4126 4127 if (e1000g_stall_check(Adapter)) { 4128 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4129 "Tx stall detected. Activate automatic recovery.\n"); 4130 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 4131 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 4132 Adapter->reset_count++; 4133 if (e1000g_reset_adapter(Adapter)) { 4134 ddi_fm_service_impact(Adapter->dip, 4135 DDI_SERVICE_RESTORED); 4136 e1000g_timer_tx_resched(Adapter); 4137 } 4138 return; 4139 } 4140 4141 link_changed = B_FALSE; 4142 rw_enter(&Adapter->chip_lock, RW_READER); 4143 if (Adapter->link_complete) 4144 link_changed = e1000g_link_check(Adapter); 4145 rw_exit(&Adapter->chip_lock); 4146 4147 if (link_changed) { 4148 if (!Adapter->reset_flag) 4149 mac_link_update(Adapter->mh, Adapter->link_state); 4150 if (Adapter->link_state == LINK_STATE_UP) 4151 Adapter->reset_flag = B_FALSE; 4152 } 4153 /* 4154 * Workaround for esb2. Data stuck in fifo on a link 4155 * down event. Reset the adapter to recover it. 4156 */ 4157 if (Adapter->esb2_workaround) { 4158 Adapter->esb2_workaround = B_FALSE; 4159 (void) e1000g_reset_adapter(Adapter); 4160 return; 4161 } 4162 4163 /* 4164 * With 82571 controllers, any locally administered address will 4165 * be overwritten when there is a reset on the other port. 4166 * Detect this circumstance and correct it. 4167 */ 4168 if ((hw->mac.type == e1000_82571) && 4169 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 4170 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 4171 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 4172 4173 ether_addr.reg.low = ntohl(ether_addr.reg.low); 4174 ether_addr.reg.high = ntohl(ether_addr.reg.high); 4175 4176 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 4177 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 4178 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 4179 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 4180 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 4181 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 4182 e1000_rar_set(hw, hw->mac.addr, 0); 4183 } 4184 } 4185 4186 /* 4187 * Long TTL workaround for 82541/82547 4188 */ 4189 (void) e1000_igp_ttl_workaround_82547(hw); 4190 4191 /* 4192 * Check for Adaptive IFS settings If there are lots of collisions 4193 * change the value in steps... 4194 * These properties should only be set for 10/100 4195 */ 4196 if ((hw->phy.media_type == e1000_media_type_copper) && 4197 ((Adapter->link_speed == SPEED_100) || 4198 (Adapter->link_speed == SPEED_10))) { 4199 e1000_update_adaptive(hw); 4200 } 4201 /* 4202 * Set Timer Interrupts 4203 */ 4204 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 4205 4206 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4207 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4208 else 4209 e1000g_timer_tx_resched(Adapter); 4210 4211 restart_watchdog_timer(Adapter); 4212 } 4213 4214 /* 4215 * The function e1000g_link_timer() is called when the timer for link setup 4216 * is expired, which indicates the completion of the link setup. The link 4217 * state will not be updated until the link setup is completed. And the 4218 * link state will not be sent to the upper layer through mac_link_update() 4219 * in this function. It will be updated in the local timer routine or the 4220 * interrupt service routine after the interface is started (plumbed). 4221 */ 4222 static void 4223 e1000g_link_timer(void *arg) 4224 { 4225 struct e1000g *Adapter = (struct e1000g *)arg; 4226 4227 mutex_enter(&Adapter->link_lock); 4228 Adapter->link_complete = B_TRUE; 4229 Adapter->link_tid = 0; 4230 mutex_exit(&Adapter->link_lock); 4231 } 4232 4233 /* 4234 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 4235 * 4236 * This function read the forced speed and duplex for 10/100 Mbps speeds 4237 * and also for 1000 Mbps speeds from the e1000g.conf file 4238 */ 4239 static void 4240 e1000g_force_speed_duplex(struct e1000g *Adapter) 4241 { 4242 int forced; 4243 int propval; 4244 struct e1000_mac_info *mac = &Adapter->shared.mac; 4245 struct e1000_phy_info *phy = &Adapter->shared.phy; 4246 4247 /* 4248 * get value out of config file 4249 */ 4250 (void) e1000g_get_prop(Adapter, "ForceSpeedDuplex", 4251 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY, &forced); 4252 4253 switch (forced) { 4254 case GDIAG_10_HALF: 4255 /* 4256 * Disable Auto Negotiation 4257 */ 4258 mac->autoneg = B_FALSE; 4259 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4260 break; 4261 case GDIAG_10_FULL: 4262 /* 4263 * Disable Auto Negotiation 4264 */ 4265 mac->autoneg = B_FALSE; 4266 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4267 break; 4268 case GDIAG_100_HALF: 4269 /* 4270 * Disable Auto Negotiation 4271 */ 4272 mac->autoneg = B_FALSE; 4273 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4274 break; 4275 case GDIAG_100_FULL: 4276 /* 4277 * Disable Auto Negotiation 4278 */ 4279 mac->autoneg = B_FALSE; 4280 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4281 break; 4282 case GDIAG_1000_FULL: 4283 /* 4284 * The gigabit spec requires autonegotiation. Therefore, 4285 * when the user wants to force the speed to 1000Mbps, we 4286 * enable AutoNeg, but only allow the harware to advertise 4287 * 1000Mbps. This is different from 10/100 operation, where 4288 * we are allowed to link without any negotiation. 4289 */ 4290 mac->autoneg = B_TRUE; 4291 phy->autoneg_advertised = ADVERTISE_1000_FULL; 4292 break; 4293 default: /* obey the setting of AutoNegAdvertised */ 4294 mac->autoneg = B_TRUE; 4295 (void) e1000g_get_prop(Adapter, "AutoNegAdvertised", 4296 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 4297 AUTONEG_ADVERTISE_SPEED_DEFAULT, &propval); 4298 phy->autoneg_advertised = (uint16_t)propval; 4299 break; 4300 } /* switch */ 4301 } 4302 4303 /* 4304 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 4305 * 4306 * This function reads MaxFrameSize from e1000g.conf 4307 */ 4308 static void 4309 e1000g_get_max_frame_size(struct e1000g *Adapter) 4310 { 4311 int max_frame; 4312 4313 /* 4314 * get value out of config file 4315 */ 4316 (void) e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0, 4317 &max_frame); 4318 4319 switch (max_frame) { 4320 case 0: 4321 Adapter->default_mtu = ETHERMTU; 4322 break; 4323 /* 4324 * To avoid excessive memory allocation for rx buffers, 4325 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 4326 */ 4327 case 1: 4328 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 4329 sizeof (struct ether_vlan_header) - ETHERFCSL - 4330 E1000G_IPALIGNPRESERVEROOM; 4331 break; 4332 case 2: 4333 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 4334 sizeof (struct ether_vlan_header) - ETHERFCSL - 4335 E1000G_IPALIGNPRESERVEROOM; 4336 break; 4337 case 3: 4338 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 4339 sizeof (struct ether_vlan_header) - ETHERFCSL - 4340 E1000G_IPALIGNPRESERVEROOM; 4341 break; 4342 default: 4343 Adapter->default_mtu = ETHERMTU; 4344 break; 4345 } /* switch */ 4346 4347 /* 4348 * If the user configed MTU is larger than the deivce's maximum MTU, 4349 * the MTU is set to the deivce's maximum value. 4350 */ 4351 if (Adapter->default_mtu > Adapter->max_mtu) 4352 Adapter->default_mtu = Adapter->max_mtu; 4353 4354 Adapter->max_frame_size = e1000g_mtu2maxframe(Adapter->default_mtu); 4355 } 4356 4357 /* 4358 * e1000g_pch_limits - Apply limits of the PCH silicon type 4359 * 4360 * At any frame size larger than the ethernet default, 4361 * prevent linking at 10/100 speeds. 4362 */ 4363 static void 4364 e1000g_pch_limits(struct e1000g *Adapter) 4365 { 4366 struct e1000_hw *hw = &Adapter->shared; 4367 4368 /* only applies to PCH silicon type */ 4369 if (hw->mac.type != e1000_pchlan) 4370 return; 4371 4372 /* only applies to frames larger than ethernet default */ 4373 if (Adapter->max_frame_size > DEFAULT_FRAME_SIZE) { 4374 hw->mac.autoneg = B_TRUE; 4375 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL; 4376 4377 Adapter->param_adv_autoneg = 1; 4378 Adapter->param_adv_1000fdx = 1; 4379 4380 Adapter->param_adv_100fdx = 0; 4381 Adapter->param_adv_100hdx = 0; 4382 Adapter->param_adv_10fdx = 0; 4383 Adapter->param_adv_10hdx = 0; 4384 4385 e1000g_param_sync(Adapter); 4386 } 4387 } 4388 4389 /* 4390 * e1000g_mtu2maxframe - convert given MTU to maximum frame size 4391 */ 4392 static uint32_t 4393 e1000g_mtu2maxframe(uint32_t mtu) 4394 { 4395 uint32_t maxframe; 4396 4397 maxframe = mtu + sizeof (struct ether_vlan_header) + ETHERFCSL; 4398 4399 return (maxframe); 4400 } 4401 4402 static void 4403 arm_watchdog_timer(struct e1000g *Adapter) 4404 { 4405 Adapter->watchdog_tid = 4406 timeout(e1000g_local_timer, 4407 (void *)Adapter, 1 * drv_usectohz(1000000)); 4408 } 4409 #pragma inline(arm_watchdog_timer) 4410 4411 static void 4412 enable_watchdog_timer(struct e1000g *Adapter) 4413 { 4414 mutex_enter(&Adapter->watchdog_lock); 4415 4416 if (!Adapter->watchdog_timer_enabled) { 4417 Adapter->watchdog_timer_enabled = B_TRUE; 4418 Adapter->watchdog_timer_started = B_TRUE; 4419 arm_watchdog_timer(Adapter); 4420 } 4421 4422 mutex_exit(&Adapter->watchdog_lock); 4423 } 4424 4425 static void 4426 disable_watchdog_timer(struct e1000g *Adapter) 4427 { 4428 timeout_id_t tid; 4429 4430 mutex_enter(&Adapter->watchdog_lock); 4431 4432 Adapter->watchdog_timer_enabled = B_FALSE; 4433 Adapter->watchdog_timer_started = B_FALSE; 4434 tid = Adapter->watchdog_tid; 4435 Adapter->watchdog_tid = 0; 4436 4437 mutex_exit(&Adapter->watchdog_lock); 4438 4439 if (tid != 0) 4440 (void) untimeout(tid); 4441 } 4442 4443 static void 4444 start_watchdog_timer(struct e1000g *Adapter) 4445 { 4446 mutex_enter(&Adapter->watchdog_lock); 4447 4448 if (Adapter->watchdog_timer_enabled) { 4449 if (!Adapter->watchdog_timer_started) { 4450 Adapter->watchdog_timer_started = B_TRUE; 4451 arm_watchdog_timer(Adapter); 4452 } 4453 } 4454 4455 mutex_exit(&Adapter->watchdog_lock); 4456 } 4457 4458 static void 4459 restart_watchdog_timer(struct e1000g *Adapter) 4460 { 4461 mutex_enter(&Adapter->watchdog_lock); 4462 4463 if (Adapter->watchdog_timer_started) 4464 arm_watchdog_timer(Adapter); 4465 4466 mutex_exit(&Adapter->watchdog_lock); 4467 } 4468 4469 static void 4470 stop_watchdog_timer(struct e1000g *Adapter) 4471 { 4472 timeout_id_t tid; 4473 4474 mutex_enter(&Adapter->watchdog_lock); 4475 4476 Adapter->watchdog_timer_started = B_FALSE; 4477 tid = Adapter->watchdog_tid; 4478 Adapter->watchdog_tid = 0; 4479 4480 mutex_exit(&Adapter->watchdog_lock); 4481 4482 if (tid != 0) 4483 (void) untimeout(tid); 4484 } 4485 4486 static void 4487 stop_link_timer(struct e1000g *Adapter) 4488 { 4489 timeout_id_t tid; 4490 4491 /* Disable the link timer */ 4492 mutex_enter(&Adapter->link_lock); 4493 4494 tid = Adapter->link_tid; 4495 Adapter->link_tid = 0; 4496 4497 mutex_exit(&Adapter->link_lock); 4498 4499 if (tid != 0) 4500 (void) untimeout(tid); 4501 } 4502 4503 static void 4504 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4505 { 4506 timeout_id_t tid; 4507 4508 /* Disable the tx timer for 82547 chipset */ 4509 mutex_enter(&tx_ring->tx_lock); 4510 4511 tx_ring->timer_enable_82547 = B_FALSE; 4512 tid = tx_ring->timer_id_82547; 4513 tx_ring->timer_id_82547 = 0; 4514 4515 mutex_exit(&tx_ring->tx_lock); 4516 4517 if (tid != 0) 4518 (void) untimeout(tid); 4519 } 4520 4521 void 4522 e1000g_clear_interrupt(struct e1000g *Adapter) 4523 { 4524 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4525 0xffffffff & ~E1000_IMS_RXSEQ); 4526 } 4527 4528 void 4529 e1000g_mask_interrupt(struct e1000g *Adapter) 4530 { 4531 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4532 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4533 4534 if (Adapter->tx_intr_enable) 4535 e1000g_mask_tx_interrupt(Adapter); 4536 } 4537 4538 /* 4539 * This routine is called by e1000g_quiesce(), therefore must not block. 4540 */ 4541 void 4542 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4543 { 4544 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4545 } 4546 4547 void 4548 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4549 { 4550 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4551 } 4552 4553 void 4554 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4555 { 4556 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4557 } 4558 4559 static void 4560 e1000g_smartspeed(struct e1000g *Adapter) 4561 { 4562 struct e1000_hw *hw = &Adapter->shared; 4563 uint16_t phy_status; 4564 uint16_t phy_ctrl; 4565 4566 /* 4567 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4568 * advertising 1000Full, we don't even use the workaround 4569 */ 4570 if ((hw->phy.type != e1000_phy_igp) || 4571 !hw->mac.autoneg || 4572 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4573 return; 4574 4575 /* 4576 * True if this is the first call of this function or after every 4577 * 30 seconds of not having link 4578 */ 4579 if (Adapter->smartspeed == 0) { 4580 /* 4581 * If Master/Slave config fault is asserted twice, we 4582 * assume back-to-back 4583 */ 4584 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4585 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4586 return; 4587 4588 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4589 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4590 return; 4591 /* 4592 * We're assuming back-2-back because our status register 4593 * insists! there's a fault in the master/slave 4594 * relationship that was "negotiated" 4595 */ 4596 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4597 /* 4598 * Is the phy configured for manual configuration of 4599 * master/slave? 4600 */ 4601 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4602 /* 4603 * Yes. Then disable manual configuration (enable 4604 * auto configuration) of master/slave 4605 */ 4606 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4607 (void) e1000_write_phy_reg(hw, 4608 PHY_1000T_CTRL, phy_ctrl); 4609 /* 4610 * Effectively starting the clock 4611 */ 4612 Adapter->smartspeed++; 4613 /* 4614 * Restart autonegotiation 4615 */ 4616 if (!e1000_phy_setup_autoneg(hw) && 4617 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4618 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4619 MII_CR_RESTART_AUTO_NEG); 4620 (void) e1000_write_phy_reg(hw, 4621 PHY_CONTROL, phy_ctrl); 4622 } 4623 } 4624 return; 4625 /* 4626 * Has 6 seconds transpired still without link? Remember, 4627 * you should reset the smartspeed counter once you obtain 4628 * link 4629 */ 4630 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4631 /* 4632 * Yes. Remember, we did at the start determine that 4633 * there's a master/slave configuration fault, so we're 4634 * still assuming there's someone on the other end, but we 4635 * just haven't yet been able to talk to it. We then 4636 * re-enable auto configuration of master/slave to see if 4637 * we're running 2/3 pair cables. 4638 */ 4639 /* 4640 * If still no link, perhaps using 2/3 pair cable 4641 */ 4642 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4643 phy_ctrl |= CR_1000T_MS_ENABLE; 4644 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4645 /* 4646 * Restart autoneg with phy enabled for manual 4647 * configuration of master/slave 4648 */ 4649 if (!e1000_phy_setup_autoneg(hw) && 4650 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4651 phy_ctrl |= 4652 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4653 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4654 } 4655 /* 4656 * Hopefully, there are no more faults and we've obtained 4657 * link as a result. 4658 */ 4659 } 4660 /* 4661 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4662 * seconds) 4663 */ 4664 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4665 Adapter->smartspeed = 0; 4666 } 4667 4668 static boolean_t 4669 is_valid_mac_addr(uint8_t *mac_addr) 4670 { 4671 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4672 const uint8_t addr_test2[6] = 4673 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4674 4675 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4676 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4677 return (B_FALSE); 4678 4679 return (B_TRUE); 4680 } 4681 4682 /* 4683 * e1000g_stall_check - check for tx stall 4684 * 4685 * This function checks if the adapter is stalled (in transmit). 4686 * 4687 * It is called each time the watchdog timeout is invoked. 4688 * If the transmit descriptor reclaim continuously fails, 4689 * the watchdog value will increment by 1. If the watchdog 4690 * value exceeds the threshold, the adapter is assumed to 4691 * have stalled and need to be reset. 4692 */ 4693 static boolean_t 4694 e1000g_stall_check(struct e1000g *Adapter) 4695 { 4696 e1000g_tx_ring_t *tx_ring; 4697 4698 tx_ring = Adapter->tx_ring; 4699 4700 if (Adapter->link_state != LINK_STATE_UP) 4701 return (B_FALSE); 4702 4703 (void) e1000g_recycle(tx_ring); 4704 4705 if (Adapter->stall_flag) { 4706 Adapter->stall_flag = B_FALSE; 4707 Adapter->reset_flag = B_TRUE; 4708 return (B_TRUE); 4709 } 4710 4711 return (B_FALSE); 4712 } 4713 4714 #ifdef E1000G_DEBUG 4715 static enum ioc_reply 4716 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4717 { 4718 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4719 e1000g_peekpoke_t *ppd; 4720 uint64_t mem_va; 4721 uint64_t maxoff; 4722 boolean_t peek; 4723 4724 switch (iocp->ioc_cmd) { 4725 4726 case E1000G_IOC_REG_PEEK: 4727 peek = B_TRUE; 4728 break; 4729 4730 case E1000G_IOC_REG_POKE: 4731 peek = B_FALSE; 4732 break; 4733 4734 deault: 4735 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4736 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4737 iocp->ioc_cmd); 4738 return (IOC_INVAL); 4739 } 4740 4741 /* 4742 * Validate format of ioctl 4743 */ 4744 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4745 return (IOC_INVAL); 4746 if (mp->b_cont == NULL) 4747 return (IOC_INVAL); 4748 4749 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4750 4751 /* 4752 * Validate request parameters 4753 */ 4754 switch (ppd->pp_acc_space) { 4755 4756 default: 4757 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4758 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4759 ppd->pp_acc_space); 4760 return (IOC_INVAL); 4761 4762 case E1000G_PP_SPACE_REG: 4763 /* 4764 * Memory-mapped I/O space 4765 */ 4766 ASSERT(ppd->pp_acc_size == 4); 4767 if (ppd->pp_acc_size != 4) 4768 return (IOC_INVAL); 4769 4770 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4771 return (IOC_INVAL); 4772 4773 mem_va = 0; 4774 maxoff = 0x10000; 4775 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4776 break; 4777 4778 case E1000G_PP_SPACE_E1000G: 4779 /* 4780 * E1000g data structure! 4781 */ 4782 mem_va = (uintptr_t)e1000gp; 4783 maxoff = sizeof (struct e1000g); 4784 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4785 break; 4786 4787 } 4788 4789 if (ppd->pp_acc_offset >= maxoff) 4790 return (IOC_INVAL); 4791 4792 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4793 return (IOC_INVAL); 4794 4795 /* 4796 * All OK - go! 4797 */ 4798 ppd->pp_acc_offset += mem_va; 4799 (*ppfn)(e1000gp, ppd); 4800 return (peek ? IOC_REPLY : IOC_ACK); 4801 } 4802 4803 static void 4804 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4805 { 4806 ddi_acc_handle_t handle; 4807 uint32_t *regaddr; 4808 4809 handle = e1000gp->osdep.reg_handle; 4810 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4811 (uintptr_t)ppd->pp_acc_offset); 4812 4813 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4814 } 4815 4816 static void 4817 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4818 { 4819 ddi_acc_handle_t handle; 4820 uint32_t *regaddr; 4821 uint32_t value; 4822 4823 handle = e1000gp->osdep.reg_handle; 4824 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4825 (uintptr_t)ppd->pp_acc_offset); 4826 value = (uint32_t)ppd->pp_acc_data; 4827 4828 ddi_put32(handle, regaddr, value); 4829 } 4830 4831 static void 4832 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4833 { 4834 uint64_t value; 4835 void *vaddr; 4836 4837 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4838 4839 switch (ppd->pp_acc_size) { 4840 case 1: 4841 value = *(uint8_t *)vaddr; 4842 break; 4843 4844 case 2: 4845 value = *(uint16_t *)vaddr; 4846 break; 4847 4848 case 4: 4849 value = *(uint32_t *)vaddr; 4850 break; 4851 4852 case 8: 4853 value = *(uint64_t *)vaddr; 4854 break; 4855 } 4856 4857 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4858 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4859 (void *)e1000gp, (void *)ppd, value, vaddr); 4860 4861 ppd->pp_acc_data = value; 4862 } 4863 4864 static void 4865 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4866 { 4867 uint64_t value; 4868 void *vaddr; 4869 4870 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4871 value = ppd->pp_acc_data; 4872 4873 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4874 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4875 (void *)e1000gp, (void *)ppd, value, vaddr); 4876 4877 switch (ppd->pp_acc_size) { 4878 case 1: 4879 *(uint8_t *)vaddr = (uint8_t)value; 4880 break; 4881 4882 case 2: 4883 *(uint16_t *)vaddr = (uint16_t)value; 4884 break; 4885 4886 case 4: 4887 *(uint32_t *)vaddr = (uint32_t)value; 4888 break; 4889 4890 case 8: 4891 *(uint64_t *)vaddr = (uint64_t)value; 4892 break; 4893 } 4894 } 4895 #endif 4896 4897 /* 4898 * Loopback Support 4899 */ 4900 static lb_property_t lb_normal = 4901 { normal, "normal", E1000G_LB_NONE }; 4902 static lb_property_t lb_external1000 = 4903 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4904 static lb_property_t lb_external100 = 4905 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4906 static lb_property_t lb_external10 = 4907 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4908 static lb_property_t lb_phy = 4909 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4910 4911 static enum ioc_reply 4912 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4913 { 4914 lb_info_sz_t *lbsp; 4915 lb_property_t *lbpp; 4916 struct e1000_hw *hw; 4917 uint32_t *lbmp; 4918 uint32_t size; 4919 uint32_t value; 4920 4921 hw = &Adapter->shared; 4922 4923 if (mp->b_cont == NULL) 4924 return (IOC_INVAL); 4925 4926 if (!e1000g_check_loopback_support(hw)) { 4927 e1000g_log(NULL, CE_WARN, 4928 "Loopback is not supported on e1000g%d", Adapter->instance); 4929 return (IOC_INVAL); 4930 } 4931 4932 switch (iocp->ioc_cmd) { 4933 default: 4934 return (IOC_INVAL); 4935 4936 case LB_GET_INFO_SIZE: 4937 size = sizeof (lb_info_sz_t); 4938 if (iocp->ioc_count != size) 4939 return (IOC_INVAL); 4940 4941 rw_enter(&Adapter->chip_lock, RW_WRITER); 4942 e1000g_get_phy_state(Adapter); 4943 4944 /* 4945 * Workaround for hardware faults. In order to get a stable 4946 * state of phy, we will wait for a specific interval and 4947 * try again. The time delay is an experiential value based 4948 * on our testing. 4949 */ 4950 msec_delay(100); 4951 e1000g_get_phy_state(Adapter); 4952 rw_exit(&Adapter->chip_lock); 4953 4954 value = sizeof (lb_normal); 4955 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4956 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4957 (hw->phy.media_type == e1000_media_type_fiber) || 4958 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4959 value += sizeof (lb_phy); 4960 switch (hw->mac.type) { 4961 case e1000_82571: 4962 case e1000_82572: 4963 case e1000_80003es2lan: 4964 value += sizeof (lb_external1000); 4965 break; 4966 } 4967 } 4968 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4969 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4970 value += sizeof (lb_external100); 4971 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4972 value += sizeof (lb_external10); 4973 4974 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 4975 *lbsp = value; 4976 break; 4977 4978 case LB_GET_INFO: 4979 value = sizeof (lb_normal); 4980 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4981 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4982 (hw->phy.media_type == e1000_media_type_fiber) || 4983 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4984 value += sizeof (lb_phy); 4985 switch (hw->mac.type) { 4986 case e1000_82571: 4987 case e1000_82572: 4988 case e1000_80003es2lan: 4989 value += sizeof (lb_external1000); 4990 break; 4991 } 4992 } 4993 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4994 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4995 value += sizeof (lb_external100); 4996 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4997 value += sizeof (lb_external10); 4998 4999 size = value; 5000 if (iocp->ioc_count != size) 5001 return (IOC_INVAL); 5002 5003 value = 0; 5004 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 5005 lbpp[value++] = lb_normal; 5006 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5007 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5008 (hw->phy.media_type == e1000_media_type_fiber) || 5009 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5010 lbpp[value++] = lb_phy; 5011 switch (hw->mac.type) { 5012 case e1000_82571: 5013 case e1000_82572: 5014 case e1000_80003es2lan: 5015 lbpp[value++] = lb_external1000; 5016 break; 5017 } 5018 } 5019 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5020 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5021 lbpp[value++] = lb_external100; 5022 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5023 lbpp[value++] = lb_external10; 5024 break; 5025 5026 case LB_GET_MODE: 5027 size = sizeof (uint32_t); 5028 if (iocp->ioc_count != size) 5029 return (IOC_INVAL); 5030 5031 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 5032 *lbmp = Adapter->loopback_mode; 5033 break; 5034 5035 case LB_SET_MODE: 5036 size = 0; 5037 if (iocp->ioc_count != sizeof (uint32_t)) 5038 return (IOC_INVAL); 5039 5040 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 5041 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 5042 return (IOC_INVAL); 5043 break; 5044 } 5045 5046 iocp->ioc_count = size; 5047 iocp->ioc_error = 0; 5048 5049 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 5050 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 5051 return (IOC_INVAL); 5052 } 5053 5054 return (IOC_REPLY); 5055 } 5056 5057 static boolean_t 5058 e1000g_check_loopback_support(struct e1000_hw *hw) 5059 { 5060 switch (hw->mac.type) { 5061 case e1000_82540: 5062 case e1000_82545: 5063 case e1000_82545_rev_3: 5064 case e1000_82546: 5065 case e1000_82546_rev_3: 5066 case e1000_82541: 5067 case e1000_82541_rev_2: 5068 case e1000_82547: 5069 case e1000_82547_rev_2: 5070 case e1000_82571: 5071 case e1000_82572: 5072 case e1000_82573: 5073 case e1000_82574: 5074 case e1000_80003es2lan: 5075 case e1000_ich9lan: 5076 case e1000_ich10lan: 5077 return (B_TRUE); 5078 } 5079 return (B_FALSE); 5080 } 5081 5082 static boolean_t 5083 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 5084 { 5085 struct e1000_hw *hw; 5086 int i, times; 5087 boolean_t link_up; 5088 5089 if (mode == Adapter->loopback_mode) 5090 return (B_TRUE); 5091 5092 hw = &Adapter->shared; 5093 times = 0; 5094 5095 Adapter->loopback_mode = mode; 5096 5097 if (mode == E1000G_LB_NONE) { 5098 /* Reset the chip */ 5099 hw->phy.autoneg_wait_to_complete = B_TRUE; 5100 (void) e1000g_reset_adapter(Adapter); 5101 hw->phy.autoneg_wait_to_complete = B_FALSE; 5102 return (B_TRUE); 5103 } 5104 5105 again: 5106 5107 rw_enter(&Adapter->chip_lock, RW_WRITER); 5108 5109 switch (mode) { 5110 default: 5111 rw_exit(&Adapter->chip_lock); 5112 return (B_FALSE); 5113 5114 case E1000G_LB_EXTERNAL_1000: 5115 e1000g_set_external_loopback_1000(Adapter); 5116 break; 5117 5118 case E1000G_LB_EXTERNAL_100: 5119 e1000g_set_external_loopback_100(Adapter); 5120 break; 5121 5122 case E1000G_LB_EXTERNAL_10: 5123 e1000g_set_external_loopback_10(Adapter); 5124 break; 5125 5126 case E1000G_LB_INTERNAL_PHY: 5127 e1000g_set_internal_loopback(Adapter); 5128 break; 5129 } 5130 5131 times++; 5132 5133 rw_exit(&Adapter->chip_lock); 5134 5135 /* Wait for link up */ 5136 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 5137 msec_delay(100); 5138 5139 rw_enter(&Adapter->chip_lock, RW_WRITER); 5140 5141 link_up = e1000g_link_up(Adapter); 5142 5143 rw_exit(&Adapter->chip_lock); 5144 5145 if (!link_up) { 5146 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5147 "Failed to get the link up"); 5148 if (times < 2) { 5149 /* Reset the link */ 5150 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5151 "Reset the link ..."); 5152 (void) e1000g_reset_adapter(Adapter); 5153 goto again; 5154 } 5155 } 5156 5157 return (B_TRUE); 5158 } 5159 5160 /* 5161 * The following loopback settings are from Intel's technical 5162 * document - "How To Loopback". All the register settings and 5163 * time delay values are directly inherited from the document 5164 * without more explanations available. 5165 */ 5166 static void 5167 e1000g_set_internal_loopback(struct e1000g *Adapter) 5168 { 5169 struct e1000_hw *hw; 5170 uint32_t ctrl; 5171 uint32_t status; 5172 uint16_t phy_ctrl; 5173 uint16_t phy_reg; 5174 uint32_t txcw; 5175 5176 hw = &Adapter->shared; 5177 5178 /* Disable Smart Power Down */ 5179 phy_spd_state(hw, B_FALSE); 5180 5181 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 5182 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 5183 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 5184 5185 switch (hw->mac.type) { 5186 case e1000_82540: 5187 case e1000_82545: 5188 case e1000_82545_rev_3: 5189 case e1000_82546: 5190 case e1000_82546_rev_3: 5191 case e1000_82573: 5192 /* Auto-MDI/MDIX off */ 5193 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 5194 /* Reset PHY to update Auto-MDI/MDIX */ 5195 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5196 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 5197 /* Reset PHY to auto-neg off and force 1000 */ 5198 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5199 phy_ctrl | MII_CR_RESET); 5200 /* 5201 * Disable PHY receiver for 82540/545/546 and 82573 Family. 5202 * See comments above e1000g_set_internal_loopback() for the 5203 * background. 5204 */ 5205 (void) e1000_write_phy_reg(hw, 29, 0x001F); 5206 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 5207 (void) e1000_write_phy_reg(hw, 29, 0x001A); 5208 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 5209 break; 5210 case e1000_80003es2lan: 5211 /* Force Link Up */ 5212 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 5213 0x1CC); 5214 /* Sets PCS loopback at 1Gbs */ 5215 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 5216 0x1046); 5217 break; 5218 } 5219 5220 /* 5221 * The following registers should be set for e1000_phy_bm phy type. 5222 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy. 5223 * For others, we do not need to set these registers. 5224 */ 5225 if (hw->phy.type == e1000_phy_bm) { 5226 /* Set Default MAC Interface speed to 1GB */ 5227 (void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg); 5228 phy_reg &= ~0x0007; 5229 phy_reg |= 0x006; 5230 (void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg); 5231 /* Assert SW reset for above settings to take effect */ 5232 (void) e1000_phy_commit(hw); 5233 msec_delay(1); 5234 /* Force Full Duplex */ 5235 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5236 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5237 phy_reg | 0x000C); 5238 /* Set Link Up (in force link) */ 5239 (void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg); 5240 (void) e1000_write_phy_reg(hw, PHY_REG(776, 16), 5241 phy_reg | 0x0040); 5242 /* Force Link */ 5243 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5244 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5245 phy_reg | 0x0040); 5246 /* Set Early Link Enable */ 5247 (void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg); 5248 (void) e1000_write_phy_reg(hw, PHY_REG(769, 20), 5249 phy_reg | 0x0400); 5250 } 5251 5252 /* Set loopback */ 5253 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 5254 5255 msec_delay(250); 5256 5257 /* Now set up the MAC to the same speed/duplex as the PHY. */ 5258 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5259 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5260 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5261 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5262 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 5263 E1000_CTRL_FD); /* Force Duplex to FULL */ 5264 5265 switch (hw->mac.type) { 5266 case e1000_82540: 5267 case e1000_82545: 5268 case e1000_82545_rev_3: 5269 case e1000_82546: 5270 case e1000_82546_rev_3: 5271 /* 5272 * For some serdes we'll need to commit the writes now 5273 * so that the status is updated on link 5274 */ 5275 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 5276 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5277 msec_delay(100); 5278 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5279 } 5280 5281 if (hw->phy.media_type == e1000_media_type_copper) { 5282 /* Invert Loss of Signal */ 5283 ctrl |= E1000_CTRL_ILOS; 5284 } else { 5285 /* Set ILOS on fiber nic if half duplex is detected */ 5286 status = E1000_READ_REG(hw, E1000_STATUS); 5287 if ((status & E1000_STATUS_FD) == 0) 5288 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5289 } 5290 break; 5291 5292 case e1000_82571: 5293 case e1000_82572: 5294 /* 5295 * The fiber/SerDes versions of this adapter do not contain an 5296 * accessible PHY. Therefore, loopback beyond MAC must be done 5297 * using SerDes analog loopback. 5298 */ 5299 if (hw->phy.media_type != e1000_media_type_copper) { 5300 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5301 txcw = E1000_READ_REG(hw, E1000_TXCW); 5302 txcw &= ~((uint32_t)1 << 31); 5303 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5304 5305 /* 5306 * Write 0x410 to Serdes Control register 5307 * to enable Serdes analog loopback 5308 */ 5309 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5310 msec_delay(10); 5311 } 5312 5313 status = E1000_READ_REG(hw, E1000_STATUS); 5314 /* Set ILOS on fiber nic if half duplex is detected */ 5315 if ((hw->phy.media_type == e1000_media_type_fiber) && 5316 ((status & E1000_STATUS_FD) == 0 || 5317 (status & E1000_STATUS_LU) == 0)) 5318 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5319 else if (hw->phy.media_type == e1000_media_type_internal_serdes) 5320 ctrl |= E1000_CTRL_SLU; 5321 break; 5322 5323 case e1000_82573: 5324 ctrl |= E1000_CTRL_ILOS; 5325 break; 5326 case e1000_ich9lan: 5327 case e1000_ich10lan: 5328 ctrl |= E1000_CTRL_SLU; 5329 break; 5330 } 5331 if (hw->phy.type == e1000_phy_bm) 5332 ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS; 5333 5334 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5335 } 5336 5337 static void 5338 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 5339 { 5340 struct e1000_hw *hw; 5341 uint32_t rctl; 5342 uint32_t ctrl_ext; 5343 uint32_t ctrl; 5344 uint32_t status; 5345 uint32_t txcw; 5346 uint16_t phydata; 5347 5348 hw = &Adapter->shared; 5349 5350 /* Disable Smart Power Down */ 5351 phy_spd_state(hw, B_FALSE); 5352 5353 switch (hw->mac.type) { 5354 case e1000_82571: 5355 case e1000_82572: 5356 switch (hw->phy.media_type) { 5357 case e1000_media_type_copper: 5358 /* Force link up (Must be done before the PHY writes) */ 5359 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5360 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 5361 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5362 5363 rctl = E1000_READ_REG(hw, E1000_RCTL); 5364 rctl |= (E1000_RCTL_EN | 5365 E1000_RCTL_SBP | 5366 E1000_RCTL_UPE | 5367 E1000_RCTL_MPE | 5368 E1000_RCTL_LPE | 5369 E1000_RCTL_BAM); /* 0x803E */ 5370 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 5371 5372 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5373 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 5374 E1000_CTRL_EXT_SDP6_DATA | 5375 E1000_CTRL_EXT_SDP3_DATA | 5376 E1000_CTRL_EXT_SDP4_DIR | 5377 E1000_CTRL_EXT_SDP6_DIR | 5378 E1000_CTRL_EXT_SDP3_DIR); /* 0x0DD0 */ 5379 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5380 5381 /* 5382 * This sequence tunes the PHY's SDP and no customer 5383 * settable values. For background, see comments above 5384 * e1000g_set_internal_loopback(). 5385 */ 5386 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 5387 msec_delay(10); 5388 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 5389 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 5390 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 5391 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 5392 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 5393 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 5394 5395 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 5396 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 5397 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 5398 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 5399 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 5400 5401 msec_delay(50); 5402 break; 5403 case e1000_media_type_fiber: 5404 case e1000_media_type_internal_serdes: 5405 status = E1000_READ_REG(hw, E1000_STATUS); 5406 if (((status & E1000_STATUS_LU) == 0) || 5407 (hw->phy.media_type == 5408 e1000_media_type_internal_serdes)) { 5409 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5410 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5411 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5412 } 5413 5414 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5415 txcw = E1000_READ_REG(hw, E1000_TXCW); 5416 txcw &= ~((uint32_t)1 << 31); 5417 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5418 5419 /* 5420 * Write 0x410 to Serdes Control register 5421 * to enable Serdes analog loopback 5422 */ 5423 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5424 msec_delay(10); 5425 break; 5426 default: 5427 break; 5428 } 5429 break; 5430 case e1000_82574: 5431 case e1000_80003es2lan: 5432 case e1000_ich9lan: 5433 case e1000_ich10lan: 5434 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 5435 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 5436 phydata | (1 << 5)); 5437 Adapter->param_adv_autoneg = 1; 5438 Adapter->param_adv_1000fdx = 1; 5439 (void) e1000g_reset_link(Adapter); 5440 break; 5441 } 5442 } 5443 5444 static void 5445 e1000g_set_external_loopback_100(struct e1000g *Adapter) 5446 { 5447 struct e1000_hw *hw; 5448 uint32_t ctrl; 5449 uint16_t phy_ctrl; 5450 5451 hw = &Adapter->shared; 5452 5453 /* Disable Smart Power Down */ 5454 phy_spd_state(hw, B_FALSE); 5455 5456 phy_ctrl = (MII_CR_FULL_DUPLEX | 5457 MII_CR_SPEED_100); 5458 5459 /* Force 100/FD, reset PHY */ 5460 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5461 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 5462 msec_delay(10); 5463 5464 /* Force 100/FD */ 5465 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5466 phy_ctrl); /* 0x2100 */ 5467 msec_delay(10); 5468 5469 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5470 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5471 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5472 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5473 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5474 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5475 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 5476 E1000_CTRL_FD); /* Force Duplex to FULL */ 5477 5478 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5479 } 5480 5481 static void 5482 e1000g_set_external_loopback_10(struct e1000g *Adapter) 5483 { 5484 struct e1000_hw *hw; 5485 uint32_t ctrl; 5486 uint16_t phy_ctrl; 5487 5488 hw = &Adapter->shared; 5489 5490 /* Disable Smart Power Down */ 5491 phy_spd_state(hw, B_FALSE); 5492 5493 phy_ctrl = (MII_CR_FULL_DUPLEX | 5494 MII_CR_SPEED_10); 5495 5496 /* Force 10/FD, reset PHY */ 5497 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5498 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 5499 msec_delay(10); 5500 5501 /* Force 10/FD */ 5502 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5503 phy_ctrl); /* 0x0100 */ 5504 msec_delay(10); 5505 5506 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5507 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5508 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5509 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5510 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5511 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5512 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 5513 E1000_CTRL_FD); /* Force Duplex to FULL */ 5514 5515 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5516 } 5517 5518 #ifdef __sparc 5519 static boolean_t 5520 e1000g_find_mac_address(struct e1000g *Adapter) 5521 { 5522 struct e1000_hw *hw = &Adapter->shared; 5523 uchar_t *bytes; 5524 struct ether_addr sysaddr; 5525 uint_t nelts; 5526 int err; 5527 boolean_t found = B_FALSE; 5528 5529 /* 5530 * The "vendor's factory-set address" may already have 5531 * been extracted from the chip, but if the property 5532 * "local-mac-address" is set we use that instead. 5533 * 5534 * We check whether it looks like an array of 6 5535 * bytes (which it should, if OBP set it). If we can't 5536 * make sense of it this way, we'll ignore it. 5537 */ 5538 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5539 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 5540 if (err == DDI_PROP_SUCCESS) { 5541 if (nelts == ETHERADDRL) { 5542 while (nelts--) 5543 hw->mac.addr[nelts] = bytes[nelts]; 5544 found = B_TRUE; 5545 } 5546 ddi_prop_free(bytes); 5547 } 5548 5549 /* 5550 * Look up the OBP property "local-mac-address?". If the user has set 5551 * 'local-mac-address? = false', use "the system address" instead. 5552 */ 5553 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5554 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5555 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5556 if (localetheraddr(NULL, &sysaddr) != 0) { 5557 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5558 found = B_TRUE; 5559 } 5560 } 5561 ddi_prop_free(bytes); 5562 } 5563 5564 /* 5565 * Finally(!), if there's a valid "mac-address" property (created 5566 * if we netbooted from this interface), we must use this instead 5567 * of any of the above to ensure that the NFS/install server doesn't 5568 * get confused by the address changing as Solaris takes over! 5569 */ 5570 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5571 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5572 if (err == DDI_PROP_SUCCESS) { 5573 if (nelts == ETHERADDRL) { 5574 while (nelts--) 5575 hw->mac.addr[nelts] = bytes[nelts]; 5576 found = B_TRUE; 5577 } 5578 ddi_prop_free(bytes); 5579 } 5580 5581 if (found) { 5582 bcopy(hw->mac.addr, hw->mac.perm_addr, 5583 ETHERADDRL); 5584 } 5585 5586 return (found); 5587 } 5588 #endif 5589 5590 static int 5591 e1000g_add_intrs(struct e1000g *Adapter) 5592 { 5593 dev_info_t *devinfo; 5594 int intr_types; 5595 int rc; 5596 5597 devinfo = Adapter->dip; 5598 5599 /* Get supported interrupt types */ 5600 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5601 5602 if (rc != DDI_SUCCESS) { 5603 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5604 "Get supported interrupt types failed: %d\n", rc); 5605 return (DDI_FAILURE); 5606 } 5607 5608 /* 5609 * Based on Intel Technical Advisory document (TA-160), there are some 5610 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5611 * that it supports MSI, but in fact has problems. 5612 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5613 * PCI/PCI-X NICs. 5614 */ 5615 if (Adapter->shared.mac.type < e1000_82571) 5616 Adapter->msi_enable = B_FALSE; 5617 5618 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5619 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5620 5621 if (rc != DDI_SUCCESS) { 5622 /* EMPTY */ 5623 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5624 "Add MSI failed, trying Legacy interrupts\n"); 5625 } else { 5626 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5627 } 5628 } 5629 5630 if ((Adapter->intr_type == 0) && 5631 (intr_types & DDI_INTR_TYPE_FIXED)) { 5632 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5633 5634 if (rc != DDI_SUCCESS) { 5635 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5636 "Add Legacy interrupts failed\n"); 5637 return (DDI_FAILURE); 5638 } 5639 5640 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5641 } 5642 5643 if (Adapter->intr_type == 0) { 5644 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5645 "No interrupts registered\n"); 5646 return (DDI_FAILURE); 5647 } 5648 5649 return (DDI_SUCCESS); 5650 } 5651 5652 /* 5653 * e1000g_intr_add() handles MSI/Legacy interrupts 5654 */ 5655 static int 5656 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5657 { 5658 dev_info_t *devinfo; 5659 int count, avail, actual; 5660 int x, y, rc, inum = 0; 5661 int flag; 5662 ddi_intr_handler_t *intr_handler; 5663 5664 devinfo = Adapter->dip; 5665 5666 /* get number of interrupts */ 5667 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5668 if ((rc != DDI_SUCCESS) || (count == 0)) { 5669 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5670 "Get interrupt number failed. Return: %d, count: %d\n", 5671 rc, count); 5672 return (DDI_FAILURE); 5673 } 5674 5675 /* get number of available interrupts */ 5676 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5677 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5678 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5679 "Get interrupt available number failed. " 5680 "Return: %d, available: %d\n", rc, avail); 5681 return (DDI_FAILURE); 5682 } 5683 5684 if (avail < count) { 5685 /* EMPTY */ 5686 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5687 "Interrupts count: %d, available: %d\n", 5688 count, avail); 5689 } 5690 5691 /* Allocate an array of interrupt handles */ 5692 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5693 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5694 5695 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5696 flag = DDI_INTR_ALLOC_NORMAL; 5697 5698 /* call ddi_intr_alloc() */ 5699 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5700 count, &actual, flag); 5701 5702 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5703 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5704 "Allocate interrupts failed: %d\n", rc); 5705 5706 kmem_free(Adapter->htable, Adapter->intr_size); 5707 return (DDI_FAILURE); 5708 } 5709 5710 if (actual < count) { 5711 /* EMPTY */ 5712 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5713 "Interrupts requested: %d, received: %d\n", 5714 count, actual); 5715 } 5716 5717 Adapter->intr_cnt = actual; 5718 5719 /* Get priority for first msi, assume remaining are all the same */ 5720 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5721 5722 if (rc != DDI_SUCCESS) { 5723 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5724 "Get interrupt priority failed: %d\n", rc); 5725 5726 /* Free already allocated intr */ 5727 for (y = 0; y < actual; y++) 5728 (void) ddi_intr_free(Adapter->htable[y]); 5729 5730 kmem_free(Adapter->htable, Adapter->intr_size); 5731 return (DDI_FAILURE); 5732 } 5733 5734 /* 5735 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5736 * use the interrupt service routine e1000g_intr_pciexpress() 5737 * to avoid interrupt stealing when sharing interrupt with other 5738 * devices. 5739 */ 5740 if (Adapter->shared.mac.type < e1000_82571) 5741 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5742 else 5743 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5744 5745 /* Call ddi_intr_add_handler() */ 5746 for (x = 0; x < actual; x++) { 5747 rc = ddi_intr_add_handler(Adapter->htable[x], 5748 intr_handler, (caddr_t)Adapter, NULL); 5749 5750 if (rc != DDI_SUCCESS) { 5751 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5752 "Add interrupt handler failed: %d\n", rc); 5753 5754 /* Remove already added handler */ 5755 for (y = 0; y < x; y++) 5756 (void) ddi_intr_remove_handler( 5757 Adapter->htable[y]); 5758 5759 /* Free already allocated intr */ 5760 for (y = 0; y < actual; y++) 5761 (void) ddi_intr_free(Adapter->htable[y]); 5762 5763 kmem_free(Adapter->htable, Adapter->intr_size); 5764 return (DDI_FAILURE); 5765 } 5766 } 5767 5768 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5769 5770 if (rc != DDI_SUCCESS) { 5771 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5772 "Get interrupt cap failed: %d\n", rc); 5773 5774 /* Free already allocated intr */ 5775 for (y = 0; y < actual; y++) { 5776 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5777 (void) ddi_intr_free(Adapter->htable[y]); 5778 } 5779 5780 kmem_free(Adapter->htable, Adapter->intr_size); 5781 return (DDI_FAILURE); 5782 } 5783 5784 return (DDI_SUCCESS); 5785 } 5786 5787 static int 5788 e1000g_rem_intrs(struct e1000g *Adapter) 5789 { 5790 int x; 5791 int rc; 5792 5793 for (x = 0; x < Adapter->intr_cnt; x++) { 5794 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5795 if (rc != DDI_SUCCESS) { 5796 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5797 "Remove intr handler failed: %d\n", rc); 5798 return (DDI_FAILURE); 5799 } 5800 5801 rc = ddi_intr_free(Adapter->htable[x]); 5802 if (rc != DDI_SUCCESS) { 5803 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5804 "Free intr failed: %d\n", rc); 5805 return (DDI_FAILURE); 5806 } 5807 } 5808 5809 kmem_free(Adapter->htable, Adapter->intr_size); 5810 5811 return (DDI_SUCCESS); 5812 } 5813 5814 static int 5815 e1000g_enable_intrs(struct e1000g *Adapter) 5816 { 5817 int x; 5818 int rc; 5819 5820 /* Enable interrupts */ 5821 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5822 /* Call ddi_intr_block_enable() for MSI */ 5823 rc = ddi_intr_block_enable(Adapter->htable, 5824 Adapter->intr_cnt); 5825 if (rc != DDI_SUCCESS) { 5826 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5827 "Enable block intr failed: %d\n", rc); 5828 return (DDI_FAILURE); 5829 } 5830 } else { 5831 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5832 for (x = 0; x < Adapter->intr_cnt; x++) { 5833 rc = ddi_intr_enable(Adapter->htable[x]); 5834 if (rc != DDI_SUCCESS) { 5835 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5836 "Enable intr failed: %d\n", rc); 5837 return (DDI_FAILURE); 5838 } 5839 } 5840 } 5841 5842 return (DDI_SUCCESS); 5843 } 5844 5845 static int 5846 e1000g_disable_intrs(struct e1000g *Adapter) 5847 { 5848 int x; 5849 int rc; 5850 5851 /* Disable all interrupts */ 5852 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5853 rc = ddi_intr_block_disable(Adapter->htable, 5854 Adapter->intr_cnt); 5855 if (rc != DDI_SUCCESS) { 5856 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5857 "Disable block intr failed: %d\n", rc); 5858 return (DDI_FAILURE); 5859 } 5860 } else { 5861 for (x = 0; x < Adapter->intr_cnt; x++) { 5862 rc = ddi_intr_disable(Adapter->htable[x]); 5863 if (rc != DDI_SUCCESS) { 5864 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5865 "Disable intr failed: %d\n", rc); 5866 return (DDI_FAILURE); 5867 } 5868 } 5869 } 5870 5871 return (DDI_SUCCESS); 5872 } 5873 5874 /* 5875 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5876 */ 5877 static void 5878 e1000g_get_phy_state(struct e1000g *Adapter) 5879 { 5880 struct e1000_hw *hw = &Adapter->shared; 5881 5882 if (hw->phy.media_type == e1000_media_type_copper) { 5883 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5884 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5885 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 5886 &Adapter->phy_an_adv); 5887 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, 5888 &Adapter->phy_an_exp); 5889 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, 5890 &Adapter->phy_ext_status); 5891 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, 5892 &Adapter->phy_1000t_ctrl); 5893 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5894 &Adapter->phy_1000t_status); 5895 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, 5896 &Adapter->phy_lp_able); 5897 5898 Adapter->param_autoneg_cap = 5899 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5900 Adapter->param_pause_cap = 5901 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5902 Adapter->param_asym_pause_cap = 5903 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5904 Adapter->param_1000fdx_cap = 5905 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5906 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5907 Adapter->param_1000hdx_cap = 5908 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5909 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5910 Adapter->param_100t4_cap = 5911 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5912 Adapter->param_100fdx_cap = 5913 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5914 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5915 Adapter->param_100hdx_cap = 5916 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5917 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5918 Adapter->param_10fdx_cap = 5919 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5920 Adapter->param_10hdx_cap = 5921 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5922 5923 Adapter->param_adv_autoneg = hw->mac.autoneg; 5924 Adapter->param_adv_pause = 5925 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5926 Adapter->param_adv_asym_pause = 5927 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5928 Adapter->param_adv_1000hdx = 5929 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5930 Adapter->param_adv_100t4 = 5931 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5932 if (Adapter->param_adv_autoneg == 1) { 5933 Adapter->param_adv_1000fdx = 5934 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) 5935 ? 1 : 0; 5936 Adapter->param_adv_100fdx = 5937 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) 5938 ? 1 : 0; 5939 Adapter->param_adv_100hdx = 5940 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) 5941 ? 1 : 0; 5942 Adapter->param_adv_10fdx = 5943 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5944 Adapter->param_adv_10hdx = 5945 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5946 } 5947 5948 Adapter->param_lp_autoneg = 5949 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5950 Adapter->param_lp_pause = 5951 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5952 Adapter->param_lp_asym_pause = 5953 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5954 Adapter->param_lp_1000fdx = 5955 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5956 Adapter->param_lp_1000hdx = 5957 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5958 Adapter->param_lp_100t4 = 5959 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5960 Adapter->param_lp_100fdx = 5961 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5962 Adapter->param_lp_100hdx = 5963 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5964 Adapter->param_lp_10fdx = 5965 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5966 Adapter->param_lp_10hdx = 5967 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5968 } else { 5969 /* 5970 * 1Gig Fiber adapter only offers 1Gig Full Duplex. Meaning, 5971 * it can only work with 1Gig Full Duplex Link Partner. 5972 */ 5973 Adapter->param_autoneg_cap = 0; 5974 Adapter->param_pause_cap = 1; 5975 Adapter->param_asym_pause_cap = 1; 5976 Adapter->param_1000fdx_cap = 1; 5977 Adapter->param_1000hdx_cap = 0; 5978 Adapter->param_100t4_cap = 0; 5979 Adapter->param_100fdx_cap = 0; 5980 Adapter->param_100hdx_cap = 0; 5981 Adapter->param_10fdx_cap = 0; 5982 Adapter->param_10hdx_cap = 0; 5983 5984 Adapter->param_adv_autoneg = 0; 5985 Adapter->param_adv_pause = 1; 5986 Adapter->param_adv_asym_pause = 1; 5987 Adapter->param_adv_1000fdx = 1; 5988 Adapter->param_adv_1000hdx = 0; 5989 Adapter->param_adv_100t4 = 0; 5990 Adapter->param_adv_100fdx = 0; 5991 Adapter->param_adv_100hdx = 0; 5992 Adapter->param_adv_10fdx = 0; 5993 Adapter->param_adv_10hdx = 0; 5994 5995 Adapter->param_lp_autoneg = 0; 5996 Adapter->param_lp_pause = 0; 5997 Adapter->param_lp_asym_pause = 0; 5998 Adapter->param_lp_1000fdx = 0; 5999 Adapter->param_lp_1000hdx = 0; 6000 Adapter->param_lp_100t4 = 0; 6001 Adapter->param_lp_100fdx = 0; 6002 Adapter->param_lp_100hdx = 0; 6003 Adapter->param_lp_10fdx = 0; 6004 Adapter->param_lp_10hdx = 0; 6005 } 6006 } 6007 6008 /* 6009 * FMA support 6010 */ 6011 6012 int 6013 e1000g_check_acc_handle(ddi_acc_handle_t handle) 6014 { 6015 ddi_fm_error_t de; 6016 6017 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 6018 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 6019 return (de.fme_status); 6020 } 6021 6022 int 6023 e1000g_check_dma_handle(ddi_dma_handle_t handle) 6024 { 6025 ddi_fm_error_t de; 6026 6027 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 6028 return (de.fme_status); 6029 } 6030 6031 /* 6032 * The IO fault service error handling callback function 6033 */ 6034 /* ARGSUSED2 */ 6035 static int 6036 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 6037 { 6038 /* 6039 * as the driver can always deal with an error in any dma or 6040 * access handle, we can just return the fme_status value. 6041 */ 6042 pci_ereport_post(dip, err, NULL); 6043 return (err->fme_status); 6044 } 6045 6046 static void 6047 e1000g_fm_init(struct e1000g *Adapter) 6048 { 6049 ddi_iblock_cookie_t iblk; 6050 int fma_dma_flag; 6051 6052 /* Only register with IO Fault Services if we have some capability */ 6053 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 6054 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 6055 } else { 6056 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 6057 } 6058 6059 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 6060 fma_dma_flag = 1; 6061 } else { 6062 fma_dma_flag = 0; 6063 } 6064 6065 (void) e1000g_set_fma_flags(fma_dma_flag); 6066 6067 if (Adapter->fm_capabilities) { 6068 6069 /* Register capabilities with IO Fault Services */ 6070 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 6071 6072 /* 6073 * Initialize pci ereport capabilities if ereport capable 6074 */ 6075 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6076 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6077 pci_ereport_setup(Adapter->dip); 6078 6079 /* 6080 * Register error callback if error callback capable 6081 */ 6082 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6083 ddi_fm_handler_register(Adapter->dip, 6084 e1000g_fm_error_cb, (void*) Adapter); 6085 } 6086 } 6087 6088 static void 6089 e1000g_fm_fini(struct e1000g *Adapter) 6090 { 6091 /* Only unregister FMA capabilities if we registered some */ 6092 if (Adapter->fm_capabilities) { 6093 6094 /* 6095 * Release any resources allocated by pci_ereport_setup() 6096 */ 6097 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6098 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6099 pci_ereport_teardown(Adapter->dip); 6100 6101 /* 6102 * Un-register error callback if error callback capable 6103 */ 6104 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6105 ddi_fm_handler_unregister(Adapter->dip); 6106 6107 /* Unregister from IO Fault Services */ 6108 mutex_enter(&e1000g_rx_detach_lock); 6109 ddi_fm_fini(Adapter->dip); 6110 if (Adapter->priv_dip != NULL) { 6111 DEVI(Adapter->priv_dip)->devi_fmhdl = NULL; 6112 } 6113 mutex_exit(&e1000g_rx_detach_lock); 6114 } 6115 } 6116 6117 void 6118 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 6119 { 6120 uint64_t ena; 6121 char buf[FM_MAX_CLASS]; 6122 6123 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 6124 ena = fm_ena_generate(0, FM_ENA_FMT1); 6125 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 6126 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 6127 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 6128 } 6129 } 6130 6131 /* 6132 * quiesce(9E) entry point. 6133 * 6134 * This function is called when the system is single-threaded at high 6135 * PIL with preemption disabled. Therefore, this function must not be 6136 * blocked. 6137 * 6138 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 6139 * DDI_FAILURE indicates an error condition and should almost never happen. 6140 */ 6141 static int 6142 e1000g_quiesce(dev_info_t *devinfo) 6143 { 6144 struct e1000g *Adapter; 6145 6146 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 6147 6148 if (Adapter == NULL) 6149 return (DDI_FAILURE); 6150 6151 e1000g_clear_all_interrupts(Adapter); 6152 6153 (void) e1000_reset_hw(&Adapter->shared); 6154 6155 /* Setup our HW Tx Head & Tail descriptor pointers */ 6156 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 6157 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 6158 6159 /* Setup our HW Rx Head & Tail descriptor pointers */ 6160 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 6161 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 6162 6163 return (DDI_SUCCESS); 6164 } 6165 6166 static int 6167 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 6168 uint_t pr_valsize, void *pr_val) 6169 { 6170 link_flowctrl_t fl; 6171 struct e1000_hw *hw = &Adapter->shared; 6172 int err = 0; 6173 6174 ASSERT(pr_valsize > 0); 6175 switch (pr_num) { 6176 case MAC_PROP_AUTONEG: 6177 if (hw->phy.media_type != e1000_media_type_copper) 6178 *(uint8_t *)pr_val = 0; 6179 else 6180 *(uint8_t *)pr_val = 6181 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) 6182 ? 1 : 0); 6183 break; 6184 case MAC_PROP_FLOWCTRL: 6185 if (pr_valsize < sizeof (link_flowctrl_t)) 6186 return (EINVAL); 6187 fl = LINK_FLOWCTRL_BI; 6188 bcopy(&fl, pr_val, sizeof (fl)); 6189 break; 6190 case MAC_PROP_ADV_1000FDX_CAP: 6191 case MAC_PROP_EN_1000FDX_CAP: 6192 if (hw->phy.media_type != e1000_media_type_copper) 6193 *(uint8_t *)pr_val = 1; 6194 else 6195 *(uint8_t *)pr_val = 6196 ((Adapter->phy_ext_status & 6197 IEEE_ESR_1000T_FD_CAPS) || 6198 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) 6199 ? 1 : 0; 6200 break; 6201 case MAC_PROP_ADV_1000HDX_CAP: 6202 case MAC_PROP_EN_1000HDX_CAP: 6203 *(uint8_t *)pr_val = 0; 6204 break; 6205 case MAC_PROP_ADV_100FDX_CAP: 6206 case MAC_PROP_EN_100FDX_CAP: 6207 if (hw->phy.media_type != e1000_media_type_copper) 6208 *(uint8_t *)pr_val = 0; 6209 else 6210 *(uint8_t *)pr_val = 6211 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 6212 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 6213 ? 1 : 0; 6214 break; 6215 case MAC_PROP_ADV_100HDX_CAP: 6216 case MAC_PROP_EN_100HDX_CAP: 6217 if (hw->phy.media_type != e1000_media_type_copper) 6218 *(uint8_t *)pr_val = 0; 6219 else 6220 *(uint8_t *)pr_val = 6221 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 6222 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) 6223 ? 1 : 0; 6224 break; 6225 case MAC_PROP_ADV_10FDX_CAP: 6226 case MAC_PROP_EN_10FDX_CAP: 6227 if (hw->phy.media_type != e1000_media_type_copper) 6228 *(uint8_t *)pr_val = 0; 6229 else 6230 *(uint8_t *)pr_val = 6231 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 6232 break; 6233 case MAC_PROP_ADV_10HDX_CAP: 6234 case MAC_PROP_EN_10HDX_CAP: 6235 if (hw->phy.media_type != e1000_media_type_copper) 6236 *(uint8_t *)pr_val = 0; 6237 else 6238 *(uint8_t *)pr_val = 6239 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 6240 break; 6241 default: 6242 err = ENOTSUP; 6243 break; 6244 } 6245 return (err); 6246 } 6247 6248 /* 6249 * synchronize the adv* and en* parameters. 6250 * 6251 * See comments in <sys/dld.h> for details of the *_en_* 6252 * parameters. The usage of ndd for setting adv parameters will 6253 * synchronize all the en parameters with the e1000g parameters, 6254 * implicitly disabling any settings made via dladm. 6255 */ 6256 static void 6257 e1000g_param_sync(struct e1000g *Adapter) 6258 { 6259 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 6260 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 6261 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 6262 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 6263 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 6264 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 6265 } 6266 6267 /* 6268 * e1000g_get_driver_control - tell manageability firmware that the driver 6269 * has control. 6270 */ 6271 static void 6272 e1000g_get_driver_control(struct e1000_hw *hw) 6273 { 6274 uint32_t ctrl_ext; 6275 uint32_t swsm; 6276 6277 /* tell manageability firmware the driver has taken over */ 6278 switch (hw->mac.type) { 6279 case e1000_82573: 6280 swsm = E1000_READ_REG(hw, E1000_SWSM); 6281 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 6282 break; 6283 case e1000_82571: 6284 case e1000_82572: 6285 case e1000_82574: 6286 case e1000_80003es2lan: 6287 case e1000_ich8lan: 6288 case e1000_ich9lan: 6289 case e1000_ich10lan: 6290 case e1000_pchlan: 6291 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6292 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6293 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 6294 break; 6295 default: 6296 /* no manageability firmware: do nothing */ 6297 break; 6298 } 6299 } 6300 6301 /* 6302 * e1000g_release_driver_control - tell manageability firmware that the driver 6303 * has released control. 6304 */ 6305 static void 6306 e1000g_release_driver_control(struct e1000_hw *hw) 6307 { 6308 uint32_t ctrl_ext; 6309 uint32_t swsm; 6310 6311 /* tell manageability firmware the driver has released control */ 6312 switch (hw->mac.type) { 6313 case e1000_82573: 6314 swsm = E1000_READ_REG(hw, E1000_SWSM); 6315 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 6316 break; 6317 case e1000_82571: 6318 case e1000_82572: 6319 case e1000_82574: 6320 case e1000_80003es2lan: 6321 case e1000_ich8lan: 6322 case e1000_ich9lan: 6323 case e1000_ich10lan: 6324 case e1000_pchlan: 6325 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6326 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6327 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 6328 break; 6329 default: 6330 /* no manageability firmware: do nothing */ 6331 break; 6332 } 6333 } 6334 6335 /* 6336 * Restore e1000g promiscuous mode. 6337 */ 6338 static void 6339 e1000g_restore_promisc(struct e1000g *Adapter) 6340 { 6341 if (Adapter->e1000g_promisc) { 6342 uint32_t rctl; 6343 6344 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 6345 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 6346 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 6347 } 6348 } 6349