1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet"; 48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 49 static char e1000g_version[] = "Driver Ver. 5.3.4"; 50 51 /* 52 * Proto types for DDI entry points 53 */ 54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 56 static int e1000g_quiesce(dev_info_t *); 57 58 /* 59 * init and intr routines prototype 60 */ 61 static int e1000g_resume(dev_info_t *); 62 static int e1000g_suspend(dev_info_t *); 63 static uint_t e1000g_intr_pciexpress(caddr_t); 64 static uint_t e1000g_intr(caddr_t); 65 static void e1000g_intr_work(struct e1000g *, uint32_t); 66 #pragma inline(e1000g_intr_work) 67 static int e1000g_init(struct e1000g *); 68 static int e1000g_start(struct e1000g *, boolean_t); 69 static void e1000g_stop(struct e1000g *, boolean_t); 70 static int e1000g_m_start(void *); 71 static void e1000g_m_stop(void *); 72 static int e1000g_m_promisc(void *, boolean_t); 73 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 74 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 75 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 76 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 77 uint_t, const void *); 78 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 79 uint_t, uint_t, void *, uint_t *); 80 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 81 const void *); 82 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 83 uint_t, void *, uint_t *); 84 static void e1000g_init_locks(struct e1000g *); 85 static void e1000g_destroy_locks(struct e1000g *); 86 static int e1000g_identify_hardware(struct e1000g *); 87 static int e1000g_regs_map(struct e1000g *); 88 static int e1000g_set_driver_params(struct e1000g *); 89 static void e1000g_set_bufsize(struct e1000g *); 90 static int e1000g_register_mac(struct e1000g *); 91 static boolean_t e1000g_rx_drain(struct e1000g *); 92 static boolean_t e1000g_tx_drain(struct e1000g *); 93 static void e1000g_init_unicst(struct e1000g *); 94 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int); 95 static int e1000g_alloc_rx_data(struct e1000g *); 96 97 /* 98 * Local routines 99 */ 100 static boolean_t e1000g_reset_adapter(struct e1000g *); 101 static void e1000g_tx_clean(struct e1000g *); 102 static void e1000g_rx_clean(struct e1000g *); 103 static void e1000g_link_timer(void *); 104 static void e1000g_local_timer(void *); 105 static boolean_t e1000g_link_check(struct e1000g *); 106 static boolean_t e1000g_stall_check(struct e1000g *); 107 static void e1000g_smartspeed(struct e1000g *); 108 static void e1000g_get_conf(struct e1000g *); 109 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 110 static void enable_watchdog_timer(struct e1000g *); 111 static void disable_watchdog_timer(struct e1000g *); 112 static void start_watchdog_timer(struct e1000g *); 113 static void restart_watchdog_timer(struct e1000g *); 114 static void stop_watchdog_timer(struct e1000g *); 115 static void stop_link_timer(struct e1000g *); 116 static void stop_82547_timer(e1000g_tx_ring_t *); 117 static void e1000g_force_speed_duplex(struct e1000g *); 118 static void e1000g_get_max_frame_size(struct e1000g *); 119 static boolean_t is_valid_mac_addr(uint8_t *); 120 static void e1000g_unattach(dev_info_t *, struct e1000g *); 121 #ifdef E1000G_DEBUG 122 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 123 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 124 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 125 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 126 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 127 struct iocblk *, mblk_t *); 128 #endif 129 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 130 struct iocblk *, mblk_t *); 131 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 132 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 133 static void e1000g_set_internal_loopback(struct e1000g *); 134 static void e1000g_set_external_loopback_1000(struct e1000g *); 135 static void e1000g_set_external_loopback_100(struct e1000g *); 136 static void e1000g_set_external_loopback_10(struct e1000g *); 137 static int e1000g_add_intrs(struct e1000g *); 138 static int e1000g_intr_add(struct e1000g *, int); 139 static int e1000g_rem_intrs(struct e1000g *); 140 static int e1000g_enable_intrs(struct e1000g *); 141 static int e1000g_disable_intrs(struct e1000g *); 142 static boolean_t e1000g_link_up(struct e1000g *); 143 #ifdef __sparc 144 static boolean_t e1000g_find_mac_address(struct e1000g *); 145 #endif 146 static void e1000g_get_phy_state(struct e1000g *); 147 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 148 const void *impl_data); 149 static void e1000g_fm_init(struct e1000g *Adapter); 150 static void e1000g_fm_fini(struct e1000g *Adapter); 151 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 152 static void e1000g_param_sync(struct e1000g *); 153 static void e1000g_get_driver_control(struct e1000_hw *); 154 static void e1000g_release_driver_control(struct e1000_hw *); 155 static void e1000g_restore_promisc(struct e1000g *Adapter); 156 157 mac_priv_prop_t e1000g_priv_props[] = { 158 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 159 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 160 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 161 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 162 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 163 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 164 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 165 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 166 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 167 {"_intr_adaptive", MAC_PROP_PERM_RW}, 168 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 169 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 170 }; 171 #define E1000G_MAX_PRIV_PROPS \ 172 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 173 174 175 static struct cb_ops cb_ws_ops = { 176 nulldev, /* cb_open */ 177 nulldev, /* cb_close */ 178 nodev, /* cb_strategy */ 179 nodev, /* cb_print */ 180 nodev, /* cb_dump */ 181 nodev, /* cb_read */ 182 nodev, /* cb_write */ 183 nodev, /* cb_ioctl */ 184 nodev, /* cb_devmap */ 185 nodev, /* cb_mmap */ 186 nodev, /* cb_segmap */ 187 nochpoll, /* cb_chpoll */ 188 ddi_prop_op, /* cb_prop_op */ 189 NULL, /* cb_stream */ 190 D_MP | D_HOTPLUG, /* cb_flag */ 191 CB_REV, /* cb_rev */ 192 nodev, /* cb_aread */ 193 nodev /* cb_awrite */ 194 }; 195 196 static struct dev_ops ws_ops = { 197 DEVO_REV, /* devo_rev */ 198 0, /* devo_refcnt */ 199 NULL, /* devo_getinfo */ 200 nulldev, /* devo_identify */ 201 nulldev, /* devo_probe */ 202 e1000g_attach, /* devo_attach */ 203 e1000g_detach, /* devo_detach */ 204 nodev, /* devo_reset */ 205 &cb_ws_ops, /* devo_cb_ops */ 206 NULL, /* devo_bus_ops */ 207 ddi_power, /* devo_power */ 208 e1000g_quiesce /* devo_quiesce */ 209 }; 210 211 static struct modldrv modldrv = { 212 &mod_driverops, /* Type of module. This one is a driver */ 213 ident, /* Discription string */ 214 &ws_ops, /* driver ops */ 215 }; 216 217 static struct modlinkage modlinkage = { 218 MODREV_1, &modldrv, NULL 219 }; 220 221 /* Access attributes for register mapping */ 222 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 223 DDI_DEVICE_ATTR_V0, 224 DDI_STRUCTURE_LE_ACC, 225 DDI_STRICTORDER_ACC, 226 DDI_FLAGERR_ACC 227 }; 228 229 #define E1000G_M_CALLBACK_FLAGS \ 230 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 231 232 static mac_callbacks_t e1000g_m_callbacks = { 233 E1000G_M_CALLBACK_FLAGS, 234 e1000g_m_stat, 235 e1000g_m_start, 236 e1000g_m_stop, 237 e1000g_m_promisc, 238 e1000g_m_multicst, 239 NULL, 240 e1000g_m_tx, 241 e1000g_m_ioctl, 242 e1000g_m_getcapab, 243 NULL, 244 NULL, 245 e1000g_m_setprop, 246 e1000g_m_getprop 247 }; 248 249 /* 250 * Global variables 251 */ 252 uint32_t e1000g_mblks_pending = 0; 253 /* 254 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 255 * Here we maintain a private dev_info list if e1000g_force_detach is 256 * enabled. If we force the driver to detach while there are still some 257 * rx buffers retained in the upper layer, we have to keep a copy of the 258 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 259 * structure will be freed after the driver is detached. However when we 260 * finally free those rx buffers released by the upper layer, we need to 261 * refer to the dev_info to free the dma buffers. So we save a copy of 262 * the dev_info for this purpose. On x86 platform, we assume this copy 263 * of dev_info is always valid, but on SPARC platform, it could be invalid 264 * after the system board level DR operation. For this reason, the global 265 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 266 */ 267 #ifdef __sparc 268 boolean_t e1000g_force_detach = B_FALSE; 269 #else 270 boolean_t e1000g_force_detach = B_TRUE; 271 #endif 272 private_devi_list_t *e1000g_private_devi_list = NULL; 273 274 /* 275 * The mutex e1000g_rx_detach_lock is defined to protect the processing of 276 * the private dev_info list, and to serialize the processing of rx buffer 277 * freeing and rx buffer recycling. 278 */ 279 kmutex_t e1000g_rx_detach_lock; 280 /* 281 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 282 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 283 * If there are many e1000g instances, the system may run out of DVMA 284 * resources during the initialization of the instances, then the flag will 285 * be changed to "USE_DMA". Because different e1000g instances are initialized 286 * in parallel, we need to use this lock to protect the flag. 287 */ 288 krwlock_t e1000g_dma_type_lock; 289 290 /* 291 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 292 * Based on the information from Intel, the 82546 chipset has some hardware 293 * problem. When one port is being reset and the other port is trying to 294 * access the eeprom, it could cause system hang or panic. To workaround this 295 * hardware problem, we use a global mutex to prevent such operations from 296 * happening simultaneously on different instances. This workaround is applied 297 * to all the devices supported by this driver. 298 */ 299 kmutex_t e1000g_nvm_lock; 300 301 /* 302 * Loadable module configuration entry points for the driver 303 */ 304 305 /* 306 * _init - module initialization 307 */ 308 int 309 _init(void) 310 { 311 int status; 312 313 mac_init_ops(&ws_ops, WSNAME); 314 status = mod_install(&modlinkage); 315 if (status != DDI_SUCCESS) 316 mac_fini_ops(&ws_ops); 317 else { 318 mutex_init(&e1000g_rx_detach_lock, NULL, MUTEX_DRIVER, NULL); 319 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 320 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 321 } 322 323 return (status); 324 } 325 326 /* 327 * _fini - module finalization 328 */ 329 int 330 _fini(void) 331 { 332 int status; 333 334 if (e1000g_mblks_pending != 0) 335 return (EBUSY); 336 337 status = mod_remove(&modlinkage); 338 if (status == DDI_SUCCESS) { 339 mac_fini_ops(&ws_ops); 340 341 if (e1000g_force_detach) { 342 private_devi_list_t *devi_node; 343 344 mutex_enter(&e1000g_rx_detach_lock); 345 while (e1000g_private_devi_list != NULL) { 346 devi_node = e1000g_private_devi_list; 347 e1000g_private_devi_list = 348 e1000g_private_devi_list->next; 349 350 kmem_free(devi_node->priv_dip, 351 sizeof (struct dev_info)); 352 kmem_free(devi_node, 353 sizeof (private_devi_list_t)); 354 } 355 mutex_exit(&e1000g_rx_detach_lock); 356 } 357 358 mutex_destroy(&e1000g_rx_detach_lock); 359 rw_destroy(&e1000g_dma_type_lock); 360 mutex_destroy(&e1000g_nvm_lock); 361 } 362 363 return (status); 364 } 365 366 /* 367 * _info - module information 368 */ 369 int 370 _info(struct modinfo *modinfop) 371 { 372 return (mod_info(&modlinkage, modinfop)); 373 } 374 375 /* 376 * e1000g_attach - driver attach 377 * 378 * This function is the device-specific initialization entry 379 * point. This entry point is required and must be written. 380 * The DDI_ATTACH command must be provided in the attach entry 381 * point. When attach() is called with cmd set to DDI_ATTACH, 382 * all normal kernel services (such as kmem_alloc(9F)) are 383 * available for use by the driver. 384 * 385 * The attach() function will be called once for each instance 386 * of the device on the system with cmd set to DDI_ATTACH. 387 * Until attach() succeeds, the only driver entry points which 388 * may be called are open(9E) and getinfo(9E). 389 */ 390 static int 391 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 392 { 393 struct e1000g *Adapter; 394 struct e1000_hw *hw; 395 struct e1000g_osdep *osdep; 396 int instance; 397 398 switch (cmd) { 399 default: 400 e1000g_log(NULL, CE_WARN, 401 "Unsupported command send to e1000g_attach... "); 402 return (DDI_FAILURE); 403 404 case DDI_RESUME: 405 return (e1000g_resume(devinfo)); 406 407 case DDI_ATTACH: 408 break; 409 } 410 411 /* 412 * get device instance number 413 */ 414 instance = ddi_get_instance(devinfo); 415 416 /* 417 * Allocate soft data structure 418 */ 419 Adapter = 420 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 421 422 Adapter->dip = devinfo; 423 Adapter->instance = instance; 424 Adapter->tx_ring->adapter = Adapter; 425 Adapter->rx_ring->adapter = Adapter; 426 427 hw = &Adapter->shared; 428 osdep = &Adapter->osdep; 429 hw->back = osdep; 430 osdep->adapter = Adapter; 431 432 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 433 434 /* 435 * Initialize for fma support 436 */ 437 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 438 0, 0x0f, 439 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 440 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 441 e1000g_fm_init(Adapter); 442 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 443 444 /* 445 * PCI Configure 446 */ 447 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 448 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 449 goto attach_fail; 450 } 451 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 452 453 /* 454 * Setup hardware 455 */ 456 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 457 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 458 goto attach_fail; 459 } 460 461 /* 462 * Map in the device registers. 463 */ 464 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 465 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 466 goto attach_fail; 467 } 468 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 469 470 /* 471 * Initialize driver parameters 472 */ 473 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 474 goto attach_fail; 475 } 476 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 477 478 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 479 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 480 goto attach_fail; 481 } 482 483 /* 484 * Initialize interrupts 485 */ 486 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 487 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 488 goto attach_fail; 489 } 490 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 491 492 /* 493 * Initialize mutex's for this device. 494 * Do this before enabling the interrupt handler and 495 * register the softint to avoid the condition where 496 * interrupt handler can try using uninitialized mutex 497 */ 498 e1000g_init_locks(Adapter); 499 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 500 501 /* 502 * Initialize Driver Counters 503 */ 504 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 505 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 506 goto attach_fail; 507 } 508 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 509 510 /* 511 * Initialize chip hardware and software structures 512 */ 513 rw_enter(&Adapter->chip_lock, RW_WRITER); 514 if (e1000g_init(Adapter) != DDI_SUCCESS) { 515 rw_exit(&Adapter->chip_lock); 516 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 517 goto attach_fail; 518 } 519 rw_exit(&Adapter->chip_lock); 520 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 521 522 /* 523 * Register the driver to the MAC 524 */ 525 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 526 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 527 goto attach_fail; 528 } 529 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 530 531 /* 532 * Now that mutex locks are initialized, and the chip is also 533 * initialized, enable interrupts. 534 */ 535 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 536 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 537 goto attach_fail; 538 } 539 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 540 541 /* 542 * If e1000g_force_detach is enabled, in global private dip list, 543 * we will create a new entry, which maintains the priv_dip for DR 544 * supports after driver detached. 545 */ 546 if (e1000g_force_detach) { 547 private_devi_list_t *devi_node; 548 549 Adapter->priv_dip = 550 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 551 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 552 sizeof (struct dev_info)); 553 554 devi_node = 555 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 556 557 mutex_enter(&e1000g_rx_detach_lock); 558 devi_node->priv_dip = Adapter->priv_dip; 559 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 560 devi_node->pending_rx_count = 0; 561 562 Adapter->priv_devi_node = devi_node; 563 564 if (e1000g_private_devi_list == NULL) { 565 devi_node->prev = NULL; 566 devi_node->next = NULL; 567 e1000g_private_devi_list = devi_node; 568 } else { 569 devi_node->prev = NULL; 570 devi_node->next = e1000g_private_devi_list; 571 e1000g_private_devi_list->prev = devi_node; 572 e1000g_private_devi_list = devi_node; 573 } 574 mutex_exit(&e1000g_rx_detach_lock); 575 } 576 577 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 578 Adapter->e1000g_state = E1000G_INITIALIZED; 579 580 return (DDI_SUCCESS); 581 582 attach_fail: 583 e1000g_unattach(devinfo, Adapter); 584 return (DDI_FAILURE); 585 } 586 587 static int 588 e1000g_register_mac(struct e1000g *Adapter) 589 { 590 struct e1000_hw *hw = &Adapter->shared; 591 mac_register_t *mac; 592 int err; 593 594 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 595 return (DDI_FAILURE); 596 597 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 598 mac->m_driver = Adapter; 599 mac->m_dip = Adapter->dip; 600 mac->m_src_addr = hw->mac.addr; 601 mac->m_callbacks = &e1000g_m_callbacks; 602 mac->m_min_sdu = 0; 603 mac->m_max_sdu = Adapter->default_mtu; 604 mac->m_margin = VLAN_TAGSZ; 605 mac->m_priv_props = e1000g_priv_props; 606 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 607 mac->m_v12n = MAC_VIRT_LEVEL1; 608 609 err = mac_register(mac, &Adapter->mh); 610 mac_free(mac); 611 612 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 613 } 614 615 static int 616 e1000g_identify_hardware(struct e1000g *Adapter) 617 { 618 struct e1000_hw *hw = &Adapter->shared; 619 struct e1000g_osdep *osdep = &Adapter->osdep; 620 621 /* Get the device id */ 622 hw->vendor_id = 623 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 624 hw->device_id = 625 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 626 hw->revision_id = 627 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 628 hw->subsystem_device_id = 629 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 630 hw->subsystem_vendor_id = 631 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 632 633 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 634 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 635 "MAC type could not be set properly."); 636 return (DDI_FAILURE); 637 } 638 639 return (DDI_SUCCESS); 640 } 641 642 static int 643 e1000g_regs_map(struct e1000g *Adapter) 644 { 645 dev_info_t *devinfo = Adapter->dip; 646 struct e1000_hw *hw = &Adapter->shared; 647 struct e1000g_osdep *osdep = &Adapter->osdep; 648 off_t mem_size; 649 650 /* Get size of adapter register memory */ 651 if (ddi_dev_regsize(devinfo, ADAPTER_REG_SET, &mem_size) != 652 DDI_SUCCESS) { 653 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 654 "ddi_dev_regsize for registers failed"); 655 return (DDI_FAILURE); 656 } 657 658 /* Map adapter register memory */ 659 if ((ddi_regs_map_setup(devinfo, ADAPTER_REG_SET, 660 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 661 &osdep->reg_handle)) != DDI_SUCCESS) { 662 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 663 "ddi_regs_map_setup for registers failed"); 664 goto regs_map_fail; 665 } 666 667 /* ICH needs to map flash memory */ 668 if (hw->mac.type == e1000_ich8lan || 669 hw->mac.type == e1000_ich9lan || 670 hw->mac.type == e1000_ich10lan) { 671 /* get flash size */ 672 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 673 &mem_size) != DDI_SUCCESS) { 674 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 675 "ddi_dev_regsize for ICH flash failed"); 676 goto regs_map_fail; 677 } 678 679 /* map flash in */ 680 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 681 (caddr_t *)&hw->flash_address, 0, 682 mem_size, &e1000g_regs_acc_attr, 683 &osdep->ich_flash_handle) != DDI_SUCCESS) { 684 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 685 "ddi_regs_map_setup for ICH flash failed"); 686 goto regs_map_fail; 687 } 688 } 689 690 return (DDI_SUCCESS); 691 692 regs_map_fail: 693 if (osdep->reg_handle != NULL) 694 ddi_regs_map_free(&osdep->reg_handle); 695 696 return (DDI_FAILURE); 697 } 698 699 static int 700 e1000g_set_driver_params(struct e1000g *Adapter) 701 { 702 struct e1000_hw *hw; 703 uint32_t mem_bar, io_bar, bar64; 704 705 hw = &Adapter->shared; 706 707 /* Set MAC type and initialize hardware functions */ 708 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 709 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 710 "Could not setup hardware functions"); 711 return (DDI_FAILURE); 712 } 713 714 /* Get bus information */ 715 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 716 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 717 "Could not get bus information"); 718 return (DDI_FAILURE); 719 } 720 721 /* get mem_base addr */ 722 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 723 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 724 725 /* get io_base addr */ 726 if (hw->mac.type >= e1000_82544) { 727 if (bar64) { 728 /* IO BAR is different for 64 bit BAR mode */ 729 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 730 PCI_CONF_BASE4); 731 } else { 732 /* normal 32-bit BAR mode */ 733 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 734 PCI_CONF_BASE2); 735 } 736 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 737 } else { 738 /* no I/O access for adapters prior to 82544 */ 739 hw->io_base = 0x0; 740 } 741 742 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 743 744 hw->mac.autoneg_failed = B_TRUE; 745 746 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 747 hw->phy.autoneg_wait_to_complete = B_FALSE; 748 749 /* Adaptive IFS related changes */ 750 hw->mac.adaptive_ifs = B_TRUE; 751 752 /* Enable phy init script for IGP phy of 82541/82547 */ 753 if ((hw->mac.type == e1000_82547) || 754 (hw->mac.type == e1000_82541) || 755 (hw->mac.type == e1000_82547_rev_2) || 756 (hw->mac.type == e1000_82541_rev_2)) 757 e1000_init_script_state_82541(hw, B_TRUE); 758 759 /* Enable the TTL workaround for 82541/82547 */ 760 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 761 762 #ifdef __sparc 763 Adapter->strip_crc = B_TRUE; 764 #else 765 Adapter->strip_crc = B_FALSE; 766 #endif 767 768 /* Get conf file properties */ 769 e1000g_get_conf(Adapter); 770 771 /* Get speed/duplex settings in conf file */ 772 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 773 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 774 e1000g_force_speed_duplex(Adapter); 775 776 /* Get Jumbo Frames settings in conf file */ 777 e1000g_get_max_frame_size(Adapter); 778 779 /* Set Rx/Tx buffer size */ 780 e1000g_set_bufsize(Adapter); 781 782 /* Master Latency Timer */ 783 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 784 785 /* copper options */ 786 if (hw->phy.media_type == e1000_media_type_copper) { 787 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 788 hw->phy.disable_polarity_correction = B_FALSE; 789 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 790 } 791 792 /* The initial link state should be "unknown" */ 793 Adapter->link_state = LINK_STATE_UNKNOWN; 794 795 /* Initialize rx parameters */ 796 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 797 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 798 799 /* Initialize tx parameters */ 800 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 801 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 802 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 803 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 804 805 /* Initialize rx parameters */ 806 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 807 808 return (DDI_SUCCESS); 809 } 810 811 static void 812 e1000g_set_bufsize(struct e1000g *Adapter) 813 { 814 struct e1000_mac_info *mac = &Adapter->shared.mac; 815 uint64_t rx_size; 816 uint64_t tx_size; 817 818 dev_info_t *devinfo = Adapter->dip; 819 #ifdef __sparc 820 ulong_t iommu_pagesize; 821 #endif 822 /* Get the system page size */ 823 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 824 825 #ifdef __sparc 826 iommu_pagesize = dvma_pagesize(devinfo); 827 if (iommu_pagesize != 0) { 828 if (Adapter->sys_page_sz == iommu_pagesize) { 829 if (iommu_pagesize > 0x4000) 830 Adapter->sys_page_sz = 0x4000; 831 } else { 832 if (Adapter->sys_page_sz > iommu_pagesize) 833 Adapter->sys_page_sz = iommu_pagesize; 834 } 835 } 836 if (Adapter->lso_enable) { 837 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 838 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 839 } else { 840 Adapter->dvma_page_num = Adapter->max_frame_size / 841 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 842 } 843 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 844 #endif 845 846 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 847 848 if (Adapter->mem_workaround_82546 && 849 ((mac->type == e1000_82545) || 850 (mac->type == e1000_82546) || 851 (mac->type == e1000_82546_rev_3))) { 852 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 853 } else { 854 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 855 if ((rx_size > FRAME_SIZE_UPTO_2K) && 856 (rx_size <= FRAME_SIZE_UPTO_4K)) 857 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 858 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 859 (rx_size <= FRAME_SIZE_UPTO_8K)) 860 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 861 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 862 (rx_size <= FRAME_SIZE_UPTO_16K)) 863 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 864 else 865 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 866 } 867 868 tx_size = Adapter->max_frame_size; 869 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 870 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 871 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 872 (tx_size <= FRAME_SIZE_UPTO_8K)) 873 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 874 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 875 (tx_size <= FRAME_SIZE_UPTO_16K)) 876 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 877 else 878 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 879 880 /* 881 * For Wiseman adapters we have an requirement of having receive 882 * buffers aligned at 256 byte boundary. Since Livengood does not 883 * require this and forcing it for all hardwares will have 884 * performance implications, I am making it applicable only for 885 * Wiseman and for Jumbo frames enabled mode as rest of the time, 886 * it is okay to have normal frames...but it does involve a 887 * potential risk where we may loose data if buffer is not 888 * aligned...so all wiseman boards to have 256 byte aligned 889 * buffers 890 */ 891 if (mac->type < e1000_82543) 892 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 893 else 894 Adapter->rx_buf_align = 1; 895 } 896 897 /* 898 * e1000g_detach - driver detach 899 * 900 * The detach() function is the complement of the attach routine. 901 * If cmd is set to DDI_DETACH, detach() is used to remove the 902 * state associated with a given instance of a device node 903 * prior to the removal of that instance from the system. 904 * 905 * The detach() function will be called once for each instance 906 * of the device for which there has been a successful attach() 907 * once there are no longer any opens on the device. 908 * 909 * Interrupts routine are disabled, All memory allocated by this 910 * driver are freed. 911 */ 912 static int 913 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 914 { 915 struct e1000g *Adapter; 916 boolean_t rx_drain; 917 918 switch (cmd) { 919 default: 920 return (DDI_FAILURE); 921 922 case DDI_SUSPEND: 923 return (e1000g_suspend(devinfo)); 924 925 case DDI_DETACH: 926 break; 927 } 928 929 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 930 if (Adapter == NULL) 931 return (DDI_FAILURE); 932 933 rx_drain = e1000g_rx_drain(Adapter); 934 if (!rx_drain && !e1000g_force_detach) 935 return (DDI_FAILURE); 936 937 if (mac_unregister(Adapter->mh) != 0) { 938 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 939 return (DDI_FAILURE); 940 } 941 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 942 943 ASSERT(!(Adapter->e1000g_state & E1000G_STARTED)); 944 945 if (!e1000g_force_detach && !rx_drain) 946 return (DDI_FAILURE); 947 948 e1000g_unattach(devinfo, Adapter); 949 950 return (DDI_SUCCESS); 951 } 952 953 /* 954 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 955 */ 956 void 957 e1000g_free_priv_devi_node(private_devi_list_t *devi_node) 958 { 959 ASSERT(e1000g_private_devi_list != NULL); 960 ASSERT(devi_node != NULL); 961 962 if (devi_node->prev != NULL) 963 devi_node->prev->next = devi_node->next; 964 if (devi_node->next != NULL) 965 devi_node->next->prev = devi_node->prev; 966 if (devi_node == e1000g_private_devi_list) 967 e1000g_private_devi_list = devi_node->next; 968 969 kmem_free(devi_node->priv_dip, 970 sizeof (struct dev_info)); 971 kmem_free(devi_node, 972 sizeof (private_devi_list_t)); 973 } 974 975 static void 976 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 977 { 978 private_devi_list_t *devi_node; 979 int result; 980 981 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 982 (void) e1000g_disable_intrs(Adapter); 983 } 984 985 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 986 (void) mac_unregister(Adapter->mh); 987 } 988 989 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 990 (void) e1000g_rem_intrs(Adapter); 991 } 992 993 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 994 (void) ddi_prop_remove_all(devinfo); 995 } 996 997 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 998 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 999 } 1000 1001 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1002 stop_link_timer(Adapter); 1003 1004 mutex_enter(&e1000g_nvm_lock); 1005 result = e1000_reset_hw(&Adapter->shared); 1006 mutex_exit(&e1000g_nvm_lock); 1007 1008 if (result != E1000_SUCCESS) { 1009 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1010 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1011 } 1012 } 1013 1014 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1015 if (Adapter->osdep.reg_handle != NULL) 1016 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1017 if (Adapter->osdep.ich_flash_handle != NULL) 1018 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1019 } 1020 1021 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1022 if (Adapter->osdep.cfg_handle != NULL) 1023 pci_config_teardown(&Adapter->osdep.cfg_handle); 1024 } 1025 1026 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1027 e1000g_destroy_locks(Adapter); 1028 } 1029 1030 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1031 e1000g_fm_fini(Adapter); 1032 } 1033 1034 mutex_enter(&e1000g_rx_detach_lock); 1035 if (e1000g_force_detach) { 1036 devi_node = Adapter->priv_devi_node; 1037 devi_node->flag |= E1000G_PRIV_DEVI_DETACH; 1038 1039 if (devi_node->pending_rx_count == 0) { 1040 e1000g_free_priv_devi_node(devi_node); 1041 } 1042 } 1043 mutex_exit(&e1000g_rx_detach_lock); 1044 1045 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1046 1047 /* 1048 * Another hotplug spec requirement, 1049 * run ddi_set_driver_private(devinfo, null); 1050 */ 1051 ddi_set_driver_private(devinfo, NULL); 1052 } 1053 1054 static void 1055 e1000g_init_locks(struct e1000g *Adapter) 1056 { 1057 e1000g_tx_ring_t *tx_ring; 1058 e1000g_rx_ring_t *rx_ring; 1059 1060 rw_init(&Adapter->chip_lock, NULL, 1061 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1062 mutex_init(&Adapter->link_lock, NULL, 1063 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1064 mutex_init(&Adapter->watchdog_lock, NULL, 1065 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1066 1067 tx_ring = Adapter->tx_ring; 1068 1069 mutex_init(&tx_ring->tx_lock, NULL, 1070 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1071 mutex_init(&tx_ring->usedlist_lock, NULL, 1072 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1073 mutex_init(&tx_ring->freelist_lock, NULL, 1074 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1075 1076 rx_ring = Adapter->rx_ring; 1077 1078 mutex_init(&rx_ring->rx_lock, NULL, 1079 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1080 } 1081 1082 static void 1083 e1000g_destroy_locks(struct e1000g *Adapter) 1084 { 1085 e1000g_tx_ring_t *tx_ring; 1086 e1000g_rx_ring_t *rx_ring; 1087 1088 tx_ring = Adapter->tx_ring; 1089 mutex_destroy(&tx_ring->tx_lock); 1090 mutex_destroy(&tx_ring->usedlist_lock); 1091 mutex_destroy(&tx_ring->freelist_lock); 1092 1093 rx_ring = Adapter->rx_ring; 1094 mutex_destroy(&rx_ring->rx_lock); 1095 1096 mutex_destroy(&Adapter->link_lock); 1097 mutex_destroy(&Adapter->watchdog_lock); 1098 rw_destroy(&Adapter->chip_lock); 1099 } 1100 1101 static int 1102 e1000g_resume(dev_info_t *devinfo) 1103 { 1104 struct e1000g *Adapter; 1105 1106 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1107 if (Adapter == NULL) 1108 e1000g_log(Adapter, CE_PANIC, 1109 "Instance pointer is null\n"); 1110 1111 if (Adapter->dip != devinfo) 1112 e1000g_log(Adapter, CE_PANIC, 1113 "Devinfo is not the same as saved devinfo\n"); 1114 1115 rw_enter(&Adapter->chip_lock, RW_WRITER); 1116 1117 if (Adapter->e1000g_state & E1000G_STARTED) { 1118 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1119 rw_exit(&Adapter->chip_lock); 1120 /* 1121 * We note the failure, but return success, as the 1122 * system is still usable without this controller. 1123 */ 1124 e1000g_log(Adapter, CE_WARN, 1125 "e1000g_resume: failed to restart controller\n"); 1126 return (DDI_SUCCESS); 1127 } 1128 /* Enable and start the watchdog timer */ 1129 enable_watchdog_timer(Adapter); 1130 } 1131 1132 Adapter->e1000g_state &= ~E1000G_SUSPENDED; 1133 1134 rw_exit(&Adapter->chip_lock); 1135 1136 return (DDI_SUCCESS); 1137 } 1138 1139 static int 1140 e1000g_suspend(dev_info_t *devinfo) 1141 { 1142 struct e1000g *Adapter; 1143 1144 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1145 if (Adapter == NULL) 1146 return (DDI_FAILURE); 1147 1148 rw_enter(&Adapter->chip_lock, RW_WRITER); 1149 1150 Adapter->e1000g_state |= E1000G_SUSPENDED; 1151 1152 /* if the port isn't plumbed, we can simply return */ 1153 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 1154 rw_exit(&Adapter->chip_lock); 1155 return (DDI_SUCCESS); 1156 } 1157 1158 e1000g_stop(Adapter, B_FALSE); 1159 1160 rw_exit(&Adapter->chip_lock); 1161 1162 /* Disable and stop all the timers */ 1163 disable_watchdog_timer(Adapter); 1164 stop_link_timer(Adapter); 1165 stop_82547_timer(Adapter->tx_ring); 1166 1167 return (DDI_SUCCESS); 1168 } 1169 1170 static int 1171 e1000g_init(struct e1000g *Adapter) 1172 { 1173 uint32_t pba; 1174 uint32_t high_water; 1175 struct e1000_hw *hw; 1176 clock_t link_timeout; 1177 int result; 1178 1179 hw = &Adapter->shared; 1180 1181 /* 1182 * reset to put the hardware in a known state 1183 * before we try to do anything with the eeprom 1184 */ 1185 mutex_enter(&e1000g_nvm_lock); 1186 result = e1000_reset_hw(hw); 1187 mutex_exit(&e1000g_nvm_lock); 1188 1189 if (result != E1000_SUCCESS) { 1190 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1191 goto init_fail; 1192 } 1193 1194 mutex_enter(&e1000g_nvm_lock); 1195 result = e1000_validate_nvm_checksum(hw); 1196 if (result < E1000_SUCCESS) { 1197 /* 1198 * Some PCI-E parts fail the first check due to 1199 * the link being in sleep state. Call it again, 1200 * if it fails a second time its a real issue. 1201 */ 1202 result = e1000_validate_nvm_checksum(hw); 1203 } 1204 mutex_exit(&e1000g_nvm_lock); 1205 1206 if (result < E1000_SUCCESS) { 1207 e1000g_log(Adapter, CE_WARN, 1208 "Invalid NVM checksum. Please contact " 1209 "the vendor to update the NVM."); 1210 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1211 goto init_fail; 1212 } 1213 1214 result = 0; 1215 #ifdef __sparc 1216 /* 1217 * First, we try to get the local ethernet address from OBP. If 1218 * failed, then we get it from the EEPROM of NIC card. 1219 */ 1220 result = e1000g_find_mac_address(Adapter); 1221 #endif 1222 /* Get the local ethernet address. */ 1223 if (!result) { 1224 mutex_enter(&e1000g_nvm_lock); 1225 result = e1000_read_mac_addr(hw); 1226 mutex_exit(&e1000g_nvm_lock); 1227 } 1228 1229 if (result < E1000_SUCCESS) { 1230 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1231 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1232 goto init_fail; 1233 } 1234 1235 /* check for valid mac address */ 1236 if (!is_valid_mac_addr(hw->mac.addr)) { 1237 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1238 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1239 goto init_fail; 1240 } 1241 1242 /* Set LAA state for 82571 chipset */ 1243 e1000_set_laa_state_82571(hw, B_TRUE); 1244 1245 /* Master Latency Timer implementation */ 1246 if (Adapter->master_latency_timer) { 1247 pci_config_put8(Adapter->osdep.cfg_handle, 1248 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1249 } 1250 1251 if (hw->mac.type < e1000_82547) { 1252 /* 1253 * Total FIFO is 64K 1254 */ 1255 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1256 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1257 else 1258 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1259 } else if ((hw->mac.type == e1000_82571) || 1260 (hw->mac.type == e1000_82572) || 1261 (hw->mac.type == e1000_80003es2lan)) { 1262 /* 1263 * Total FIFO is 48K 1264 */ 1265 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1266 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1267 else 1268 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1269 } else if (hw->mac.type == e1000_82573) { 1270 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1271 } else if (hw->mac.type == e1000_82574) { 1272 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1273 pba = E1000_READ_REG(hw, E1000_PBA); 1274 } else if (hw->mac.type == e1000_ich8lan) { 1275 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1276 } else if (hw->mac.type == e1000_ich9lan) { 1277 pba = E1000_PBA_10K; 1278 } else if (hw->mac.type == e1000_ich10lan) { 1279 pba = E1000_PBA_10K; 1280 } else { 1281 /* 1282 * Total FIFO is 40K 1283 */ 1284 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1285 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1286 else 1287 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1288 } 1289 E1000_WRITE_REG(hw, E1000_PBA, pba); 1290 1291 /* 1292 * These parameters set thresholds for the adapter's generation(Tx) 1293 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1294 * settings. Flow control is enabled or disabled in the configuration 1295 * file. 1296 * High-water mark is set down from the top of the rx fifo (not 1297 * sensitive to max_frame_size) and low-water is set just below 1298 * high-water mark. 1299 * The high water mark must be low enough to fit one full frame above 1300 * it in the rx FIFO. Should be the lower of: 1301 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1302 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1303 * Rx FIFO size minus one full frame. 1304 */ 1305 high_water = min(((pba << 10) * 9 / 10), 1306 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 || 1307 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ? 1308 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1309 ((pba << 10) - Adapter->max_frame_size))); 1310 1311 hw->fc.high_water = high_water & 0xFFF8; 1312 hw->fc.low_water = hw->fc.high_water - 8; 1313 1314 if (hw->mac.type == e1000_80003es2lan) 1315 hw->fc.pause_time = 0xFFFF; 1316 else 1317 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1318 hw->fc.send_xon = B_TRUE; 1319 1320 /* 1321 * Reset the adapter hardware the second time. 1322 */ 1323 mutex_enter(&e1000g_nvm_lock); 1324 result = e1000_reset_hw(hw); 1325 mutex_exit(&e1000g_nvm_lock); 1326 1327 if (result != E1000_SUCCESS) { 1328 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1329 goto init_fail; 1330 } 1331 1332 /* disable wakeup control by default */ 1333 if (hw->mac.type >= e1000_82544) 1334 E1000_WRITE_REG(hw, E1000_WUC, 0); 1335 1336 /* 1337 * MWI should be disabled on 82546. 1338 */ 1339 if (hw->mac.type == e1000_82546) 1340 e1000_pci_clear_mwi(hw); 1341 else 1342 e1000_pci_set_mwi(hw); 1343 1344 /* 1345 * Configure/Initialize hardware 1346 */ 1347 mutex_enter(&e1000g_nvm_lock); 1348 result = e1000_init_hw(hw); 1349 mutex_exit(&e1000g_nvm_lock); 1350 1351 if (result < E1000_SUCCESS) { 1352 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1353 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1354 goto init_fail; 1355 } 1356 1357 /* 1358 * Restore LED settings to the default from EEPROM 1359 * to meet the standard for Sun platforms. 1360 */ 1361 if ((hw->mac.type != e1000_82541) && 1362 (hw->mac.type != e1000_82541_rev_2) && 1363 (hw->mac.type != e1000_82547) && 1364 (hw->mac.type != e1000_82547_rev_2)) 1365 (void) e1000_cleanup_led(hw); 1366 1367 /* Disable Smart Power Down */ 1368 phy_spd_state(hw, B_FALSE); 1369 1370 /* Make sure driver has control */ 1371 e1000g_get_driver_control(hw); 1372 1373 /* 1374 * Initialize unicast addresses. 1375 */ 1376 e1000g_init_unicst(Adapter); 1377 1378 /* 1379 * Setup and initialize the mctable structures. After this routine 1380 * completes Multicast table will be set 1381 */ 1382 e1000g_setup_multicast(Adapter); 1383 msec_delay(5); 1384 1385 /* 1386 * Implement Adaptive IFS 1387 */ 1388 e1000_reset_adaptive(hw); 1389 1390 /* Setup Interrupt Throttling Register */ 1391 if (hw->mac.type >= e1000_82540) { 1392 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1393 } else 1394 Adapter->intr_adaptive = B_FALSE; 1395 1396 /* Start the timer for link setup */ 1397 if (hw->mac.autoneg) 1398 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1399 else 1400 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1401 1402 mutex_enter(&Adapter->link_lock); 1403 if (hw->phy.autoneg_wait_to_complete) { 1404 Adapter->link_complete = B_TRUE; 1405 } else { 1406 Adapter->link_complete = B_FALSE; 1407 Adapter->link_tid = timeout(e1000g_link_timer, 1408 (void *)Adapter, link_timeout); 1409 } 1410 mutex_exit(&Adapter->link_lock); 1411 1412 /* Enable PCI-Ex master */ 1413 if (hw->bus.type == e1000_bus_type_pci_express) { 1414 e1000_enable_pciex_master(hw); 1415 } 1416 1417 /* Save the state of the phy */ 1418 e1000g_get_phy_state(Adapter); 1419 1420 e1000g_param_sync(Adapter); 1421 1422 Adapter->init_count++; 1423 1424 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1425 goto init_fail; 1426 } 1427 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1428 goto init_fail; 1429 } 1430 1431 Adapter->poll_mode = e1000g_poll_mode; 1432 1433 return (DDI_SUCCESS); 1434 1435 init_fail: 1436 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1437 return (DDI_FAILURE); 1438 } 1439 1440 static int 1441 e1000g_alloc_rx_data(struct e1000g *Adapter) 1442 { 1443 e1000g_rx_ring_t *rx_ring; 1444 e1000g_rx_data_t *rx_data; 1445 1446 rx_ring = Adapter->rx_ring; 1447 1448 rx_data = kmem_zalloc(sizeof (e1000g_rx_data_t), KM_NOSLEEP); 1449 1450 if (rx_data == NULL) 1451 return (DDI_FAILURE); 1452 1453 rx_data->priv_devi_node = Adapter->priv_devi_node; 1454 rx_data->rx_ring = rx_ring; 1455 1456 mutex_init(&rx_data->freelist_lock, NULL, 1457 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1458 mutex_init(&rx_data->recycle_lock, NULL, 1459 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1460 1461 rx_ring->rx_data = rx_data; 1462 1463 return (DDI_SUCCESS); 1464 } 1465 1466 void 1467 e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data) 1468 { 1469 rx_sw_packet_t *packet, *next_packet; 1470 1471 if (rx_data == NULL) 1472 return; 1473 1474 packet = rx_data->packet_area; 1475 while (packet != NULL) { 1476 next_packet = packet->next; 1477 e1000g_free_rx_sw_packet(packet, B_TRUE); 1478 packet = next_packet; 1479 } 1480 rx_data->packet_area = NULL; 1481 } 1482 1483 void 1484 e1000g_free_rx_data(e1000g_rx_data_t *rx_data) 1485 { 1486 if (rx_data == NULL) 1487 return; 1488 1489 mutex_destroy(&rx_data->freelist_lock); 1490 mutex_destroy(&rx_data->recycle_lock); 1491 1492 kmem_free(rx_data, sizeof (e1000g_rx_data_t)); 1493 } 1494 1495 /* 1496 * Check if the link is up 1497 */ 1498 static boolean_t 1499 e1000g_link_up(struct e1000g *Adapter) 1500 { 1501 struct e1000_hw *hw; 1502 boolean_t link_up; 1503 1504 hw = &Adapter->shared; 1505 1506 (void) e1000_check_for_link(hw); 1507 1508 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1509 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1510 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1511 (hw->mac.serdes_has_link))) { 1512 link_up = B_TRUE; 1513 } else { 1514 link_up = B_FALSE; 1515 } 1516 1517 return (link_up); 1518 } 1519 1520 static void 1521 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1522 { 1523 struct iocblk *iocp; 1524 struct e1000g *e1000gp; 1525 enum ioc_reply status; 1526 1527 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1528 iocp->ioc_error = 0; 1529 e1000gp = (struct e1000g *)arg; 1530 1531 ASSERT(e1000gp); 1532 if (e1000gp == NULL) { 1533 miocnak(q, mp, 0, EINVAL); 1534 return; 1535 } 1536 1537 rw_enter(&e1000gp->chip_lock, RW_READER); 1538 if (e1000gp->e1000g_state & E1000G_SUSPENDED) { 1539 rw_exit(&e1000gp->chip_lock); 1540 miocnak(q, mp, 0, EINVAL); 1541 return; 1542 } 1543 rw_exit(&e1000gp->chip_lock); 1544 1545 switch (iocp->ioc_cmd) { 1546 1547 case LB_GET_INFO_SIZE: 1548 case LB_GET_INFO: 1549 case LB_GET_MODE: 1550 case LB_SET_MODE: 1551 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1552 break; 1553 1554 1555 #ifdef E1000G_DEBUG 1556 case E1000G_IOC_REG_PEEK: 1557 case E1000G_IOC_REG_POKE: 1558 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1559 break; 1560 case E1000G_IOC_CHIP_RESET: 1561 e1000gp->reset_count++; 1562 if (e1000g_reset_adapter(e1000gp)) 1563 status = IOC_ACK; 1564 else 1565 status = IOC_INVAL; 1566 break; 1567 #endif 1568 default: 1569 status = IOC_INVAL; 1570 break; 1571 } 1572 1573 /* 1574 * Decide how to reply 1575 */ 1576 switch (status) { 1577 default: 1578 case IOC_INVAL: 1579 /* 1580 * Error, reply with a NAK and EINVAL or the specified error 1581 */ 1582 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1583 EINVAL : iocp->ioc_error); 1584 break; 1585 1586 case IOC_DONE: 1587 /* 1588 * OK, reply already sent 1589 */ 1590 break; 1591 1592 case IOC_ACK: 1593 /* 1594 * OK, reply with an ACK 1595 */ 1596 miocack(q, mp, 0, 0); 1597 break; 1598 1599 case IOC_REPLY: 1600 /* 1601 * OK, send prepared reply as ACK or NAK 1602 */ 1603 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1604 M_IOCACK : M_IOCNAK; 1605 qreply(q, mp); 1606 break; 1607 } 1608 } 1609 1610 /* 1611 * The default value of e1000g_poll_mode == 0 assumes that the NIC is 1612 * capable of supporting only one interrupt and we shouldn't disable 1613 * the physical interrupt. In this case we let the interrupt come and 1614 * we queue the packets in the rx ring itself in case we are in polling 1615 * mode (better latency but slightly lower performance and a very 1616 * high intrrupt count in mpstat which is harmless). 1617 * 1618 * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt 1619 * which can be disabled in poll mode. This gives better overall 1620 * throughput (compared to the mode above), shows very low interrupt 1621 * count but has slightly higher latency since we pick the packets when 1622 * the poll thread does polling. 1623 * 1624 * Currently, this flag should be enabled only while doing performance 1625 * measurement or when it can be guaranteed that entire NIC going 1626 * in poll mode will not harm any traffic like cluster heartbeat etc. 1627 */ 1628 int e1000g_poll_mode = 0; 1629 1630 /* 1631 * Called from the upper layers when driver is in polling mode to 1632 * pick up any queued packets. Care should be taken to not block 1633 * this thread. 1634 */ 1635 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup) 1636 { 1637 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)arg; 1638 mblk_t *mp = NULL; 1639 mblk_t *tail; 1640 struct e1000g *adapter; 1641 1642 adapter = rx_ring->adapter; 1643 1644 rw_enter(&adapter->chip_lock, RW_READER); 1645 1646 if (adapter->e1000g_state & E1000G_SUSPENDED) { 1647 rw_exit(&adapter->chip_lock); 1648 return (NULL); 1649 } 1650 1651 mutex_enter(&rx_ring->rx_lock); 1652 mp = e1000g_receive(rx_ring, &tail, bytes_to_pickup); 1653 mutex_exit(&rx_ring->rx_lock); 1654 rw_exit(&adapter->chip_lock); 1655 return (mp); 1656 } 1657 1658 static int 1659 e1000g_m_start(void *arg) 1660 { 1661 struct e1000g *Adapter = (struct e1000g *)arg; 1662 1663 rw_enter(&Adapter->chip_lock, RW_WRITER); 1664 1665 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1666 rw_exit(&Adapter->chip_lock); 1667 return (ECANCELED); 1668 } 1669 1670 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1671 rw_exit(&Adapter->chip_lock); 1672 return (ENOTACTIVE); 1673 } 1674 1675 Adapter->e1000g_state |= E1000G_STARTED; 1676 1677 rw_exit(&Adapter->chip_lock); 1678 1679 /* Enable and start the watchdog timer */ 1680 enable_watchdog_timer(Adapter); 1681 1682 return (0); 1683 } 1684 1685 static int 1686 e1000g_start(struct e1000g *Adapter, boolean_t global) 1687 { 1688 e1000g_rx_data_t *rx_data; 1689 1690 if (global) { 1691 if (e1000g_alloc_rx_data(Adapter) != DDI_SUCCESS) { 1692 e1000g_log(Adapter, CE_WARN, "Allocate rx data failed"); 1693 goto start_fail; 1694 } 1695 1696 /* Allocate dma resources for descriptors and buffers */ 1697 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1698 e1000g_log(Adapter, CE_WARN, 1699 "Alloc DMA resources failed"); 1700 goto start_fail; 1701 } 1702 Adapter->rx_buffer_setup = B_FALSE; 1703 } 1704 1705 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1706 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1707 e1000g_log(Adapter, CE_WARN, 1708 "Adapter initialization failed"); 1709 goto start_fail; 1710 } 1711 } 1712 1713 /* Setup and initialize the transmit structures */ 1714 e1000g_tx_setup(Adapter); 1715 msec_delay(5); 1716 1717 /* Setup and initialize the receive structures */ 1718 e1000g_rx_setup(Adapter); 1719 msec_delay(5); 1720 1721 /* Restore the e1000g promiscuous mode */ 1722 e1000g_restore_promisc(Adapter); 1723 1724 e1000g_mask_interrupt(Adapter); 1725 1726 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1727 1728 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1729 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1730 goto start_fail; 1731 } 1732 1733 return (DDI_SUCCESS); 1734 1735 start_fail: 1736 rx_data = Adapter->rx_ring->rx_data; 1737 1738 if (global) { 1739 e1000g_release_dma_resources(Adapter); 1740 e1000g_free_rx_pending_buffers(rx_data); 1741 e1000g_free_rx_data(rx_data); 1742 } 1743 1744 mutex_enter(&e1000g_nvm_lock); 1745 (void) e1000_reset_hw(&Adapter->shared); 1746 mutex_exit(&e1000g_nvm_lock); 1747 1748 return (DDI_FAILURE); 1749 } 1750 1751 static void 1752 e1000g_m_stop(void *arg) 1753 { 1754 struct e1000g *Adapter = (struct e1000g *)arg; 1755 1756 /* Drain tx sessions */ 1757 (void) e1000g_tx_drain(Adapter); 1758 1759 rw_enter(&Adapter->chip_lock, RW_WRITER); 1760 1761 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1762 rw_exit(&Adapter->chip_lock); 1763 return; 1764 } 1765 Adapter->e1000g_state &= ~E1000G_STARTED; 1766 e1000g_stop(Adapter, B_TRUE); 1767 1768 rw_exit(&Adapter->chip_lock); 1769 1770 /* Disable and stop all the timers */ 1771 disable_watchdog_timer(Adapter); 1772 stop_link_timer(Adapter); 1773 stop_82547_timer(Adapter->tx_ring); 1774 } 1775 1776 static void 1777 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1778 { 1779 private_devi_list_t *devi_node; 1780 e1000g_rx_data_t *rx_data; 1781 int result; 1782 1783 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1784 1785 /* Stop the chip and release pending resources */ 1786 1787 /* Tell firmware driver is no longer in control */ 1788 e1000g_release_driver_control(&Adapter->shared); 1789 1790 e1000g_clear_all_interrupts(Adapter); 1791 1792 mutex_enter(&e1000g_nvm_lock); 1793 result = e1000_reset_hw(&Adapter->shared); 1794 mutex_exit(&e1000g_nvm_lock); 1795 1796 if (result != E1000_SUCCESS) { 1797 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1798 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1799 } 1800 1801 /* Release resources still held by the TX descriptors */ 1802 e1000g_tx_clean(Adapter); 1803 1804 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1805 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1806 1807 /* Clean the pending rx jumbo packet fragment */ 1808 e1000g_rx_clean(Adapter); 1809 1810 if (global) { 1811 e1000g_release_dma_resources(Adapter); 1812 1813 mutex_enter(&e1000g_rx_detach_lock); 1814 rx_data = Adapter->rx_ring->rx_data; 1815 rx_data->flag |= E1000G_RX_STOPPED; 1816 1817 if (rx_data->pending_count == 0) { 1818 e1000g_free_rx_pending_buffers(rx_data); 1819 e1000g_free_rx_data(rx_data); 1820 } else { 1821 devi_node = rx_data->priv_devi_node; 1822 if (devi_node != NULL) 1823 atomic_inc_32(&devi_node->pending_rx_count); 1824 else 1825 atomic_inc_32(&Adapter->pending_rx_count); 1826 } 1827 mutex_exit(&e1000g_rx_detach_lock); 1828 } 1829 } 1830 1831 static void 1832 e1000g_rx_clean(struct e1000g *Adapter) 1833 { 1834 e1000g_rx_data_t *rx_data = Adapter->rx_ring->rx_data; 1835 1836 if (rx_data == NULL) 1837 return; 1838 1839 if (rx_data->rx_mblk != NULL) { 1840 freemsg(rx_data->rx_mblk); 1841 rx_data->rx_mblk = NULL; 1842 rx_data->rx_mblk_tail = NULL; 1843 rx_data->rx_mblk_len = 0; 1844 } 1845 } 1846 1847 static void 1848 e1000g_tx_clean(struct e1000g *Adapter) 1849 { 1850 e1000g_tx_ring_t *tx_ring; 1851 p_tx_sw_packet_t packet; 1852 mblk_t *mp; 1853 mblk_t *nmp; 1854 uint32_t packet_count; 1855 1856 tx_ring = Adapter->tx_ring; 1857 1858 /* 1859 * Here we don't need to protect the lists using 1860 * the usedlist_lock and freelist_lock, for they 1861 * have been protected by the chip_lock. 1862 */ 1863 mp = NULL; 1864 nmp = NULL; 1865 packet_count = 0; 1866 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1867 while (packet != NULL) { 1868 if (packet->mp != NULL) { 1869 /* Assemble the message chain */ 1870 if (mp == NULL) { 1871 mp = packet->mp; 1872 nmp = packet->mp; 1873 } else { 1874 nmp->b_next = packet->mp; 1875 nmp = packet->mp; 1876 } 1877 /* Disconnect the message from the sw packet */ 1878 packet->mp = NULL; 1879 } 1880 1881 e1000g_free_tx_swpkt(packet); 1882 packet_count++; 1883 1884 packet = (p_tx_sw_packet_t) 1885 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1886 } 1887 1888 if (mp != NULL) 1889 freemsgchain(mp); 1890 1891 if (packet_count > 0) { 1892 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1893 QUEUE_INIT_LIST(&tx_ring->used_list); 1894 1895 /* Setup TX descriptor pointers */ 1896 tx_ring->tbd_next = tx_ring->tbd_first; 1897 tx_ring->tbd_oldest = tx_ring->tbd_first; 1898 1899 /* Setup our HW Tx Head & Tail descriptor pointers */ 1900 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1901 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1902 } 1903 } 1904 1905 static boolean_t 1906 e1000g_tx_drain(struct e1000g *Adapter) 1907 { 1908 int i; 1909 boolean_t done; 1910 e1000g_tx_ring_t *tx_ring; 1911 1912 tx_ring = Adapter->tx_ring; 1913 1914 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1915 for (i = 0; i < TX_DRAIN_TIME; i++) { 1916 mutex_enter(&tx_ring->usedlist_lock); 1917 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1918 mutex_exit(&tx_ring->usedlist_lock); 1919 1920 if (done) 1921 break; 1922 1923 msec_delay(1); 1924 } 1925 1926 return (done); 1927 } 1928 1929 static boolean_t 1930 e1000g_rx_drain(struct e1000g *Adapter) 1931 { 1932 int i; 1933 boolean_t done; 1934 1935 /* 1936 * Allow up to RX_DRAIN_TIME for pending received packets to complete. 1937 */ 1938 for (i = 0; i < RX_DRAIN_TIME; i++) { 1939 done = (Adapter->pending_rx_count == 0); 1940 1941 if (done) 1942 break; 1943 1944 msec_delay(1); 1945 } 1946 1947 return (done); 1948 } 1949 1950 static boolean_t 1951 e1000g_reset_adapter(struct e1000g *Adapter) 1952 { 1953 /* Disable and stop all the timers */ 1954 disable_watchdog_timer(Adapter); 1955 stop_link_timer(Adapter); 1956 stop_82547_timer(Adapter->tx_ring); 1957 1958 rw_enter(&Adapter->chip_lock, RW_WRITER); 1959 1960 e1000g_stop(Adapter, B_FALSE); 1961 1962 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1963 rw_exit(&Adapter->chip_lock); 1964 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1965 return (B_FALSE); 1966 } 1967 1968 rw_exit(&Adapter->chip_lock); 1969 1970 /* Enable and start the watchdog timer */ 1971 enable_watchdog_timer(Adapter); 1972 1973 return (B_TRUE); 1974 } 1975 1976 boolean_t 1977 e1000g_global_reset(struct e1000g *Adapter) 1978 { 1979 /* Disable and stop all the timers */ 1980 disable_watchdog_timer(Adapter); 1981 stop_link_timer(Adapter); 1982 stop_82547_timer(Adapter->tx_ring); 1983 1984 rw_enter(&Adapter->chip_lock, RW_WRITER); 1985 1986 e1000g_stop(Adapter, B_TRUE); 1987 1988 Adapter->init_count = 0; 1989 1990 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1991 rw_exit(&Adapter->chip_lock); 1992 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1993 return (B_FALSE); 1994 } 1995 1996 rw_exit(&Adapter->chip_lock); 1997 1998 /* Enable and start the watchdog timer */ 1999 enable_watchdog_timer(Adapter); 2000 2001 return (B_TRUE); 2002 } 2003 2004 /* 2005 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 2006 * 2007 * This interrupt service routine is for PCI-Express adapters. 2008 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 2009 * bit is set. 2010 */ 2011 static uint_t 2012 e1000g_intr_pciexpress(caddr_t arg) 2013 { 2014 struct e1000g *Adapter; 2015 uint32_t icr; 2016 2017 Adapter = (struct e1000g *)(uintptr_t)arg; 2018 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2019 2020 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2021 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2022 2023 if (icr & E1000_ICR_INT_ASSERTED) { 2024 /* 2025 * E1000_ICR_INT_ASSERTED bit was set: 2026 * Read(Clear) the ICR, claim this interrupt, 2027 * look for work to do. 2028 */ 2029 e1000g_intr_work(Adapter, icr); 2030 return (DDI_INTR_CLAIMED); 2031 } else { 2032 /* 2033 * E1000_ICR_INT_ASSERTED bit was not set: 2034 * Don't claim this interrupt, return immediately. 2035 */ 2036 return (DDI_INTR_UNCLAIMED); 2037 } 2038 } 2039 2040 /* 2041 * e1000g_intr - ISR for PCI/PCI-X chipsets 2042 * 2043 * This interrupt service routine is for PCI/PCI-X adapters. 2044 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 2045 * bit is set or not. 2046 */ 2047 static uint_t 2048 e1000g_intr(caddr_t arg) 2049 { 2050 struct e1000g *Adapter; 2051 uint32_t icr; 2052 2053 Adapter = (struct e1000g *)(uintptr_t)arg; 2054 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2055 2056 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2057 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2058 2059 if (icr) { 2060 /* 2061 * Any bit was set in ICR: 2062 * Read(Clear) the ICR, claim this interrupt, 2063 * look for work to do. 2064 */ 2065 e1000g_intr_work(Adapter, icr); 2066 return (DDI_INTR_CLAIMED); 2067 } else { 2068 /* 2069 * No bit was set in ICR: 2070 * Don't claim this interrupt, return immediately. 2071 */ 2072 return (DDI_INTR_UNCLAIMED); 2073 } 2074 } 2075 2076 /* 2077 * e1000g_intr_work - actual processing of ISR 2078 * 2079 * Read(clear) the ICR contents and call appropriate interrupt 2080 * processing routines. 2081 */ 2082 static void 2083 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 2084 { 2085 struct e1000_hw *hw; 2086 hw = &Adapter->shared; 2087 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2088 2089 Adapter->rx_pkt_cnt = 0; 2090 Adapter->tx_pkt_cnt = 0; 2091 2092 rw_enter(&Adapter->chip_lock, RW_READER); 2093 2094 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2095 rw_exit(&Adapter->chip_lock); 2096 return; 2097 } 2098 /* 2099 * Here we need to check the "e1000g_state" flag within the chip_lock to 2100 * ensure the receive routine will not execute when the adapter is 2101 * being reset. 2102 */ 2103 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2104 rw_exit(&Adapter->chip_lock); 2105 return; 2106 } 2107 2108 if (icr & E1000_ICR_RXT0) { 2109 mblk_t *mp = NULL; 2110 mblk_t *tail = NULL; 2111 e1000g_rx_ring_t *rx_ring; 2112 2113 rx_ring = Adapter->rx_ring; 2114 mutex_enter(&rx_ring->rx_lock); 2115 /* 2116 * Sometimes with legacy interrupts, it possible that 2117 * there is a single interrupt for Rx/Tx. In which 2118 * case, if poll flag is set, we shouldn't really 2119 * be doing Rx processing. 2120 */ 2121 if (!rx_ring->poll_flag) 2122 mp = e1000g_receive(rx_ring, &tail, 2123 E1000G_CHAIN_NO_LIMIT); 2124 mutex_exit(&rx_ring->rx_lock); 2125 rw_exit(&Adapter->chip_lock); 2126 if (mp != NULL) 2127 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2128 mp, rx_ring->ring_gen_num); 2129 } else 2130 rw_exit(&Adapter->chip_lock); 2131 2132 if (icr & E1000_ICR_TXDW) { 2133 if (!Adapter->tx_intr_enable) 2134 e1000g_clear_tx_interrupt(Adapter); 2135 2136 /* Recycle the tx descriptors */ 2137 rw_enter(&Adapter->chip_lock, RW_READER); 2138 (void) e1000g_recycle(tx_ring); 2139 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 2140 rw_exit(&Adapter->chip_lock); 2141 2142 if (tx_ring->resched_needed && 2143 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 2144 tx_ring->resched_needed = B_FALSE; 2145 mac_tx_update(Adapter->mh); 2146 E1000G_STAT(tx_ring->stat_reschedule); 2147 } 2148 } 2149 2150 /* 2151 * The Receive Sequence errors RXSEQ and the link status change LSC 2152 * are checked to detect that the cable has been pulled out. For 2153 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 2154 * are an indication that cable is not connected. 2155 */ 2156 if ((icr & E1000_ICR_RXSEQ) || 2157 (icr & E1000_ICR_LSC) || 2158 (icr & E1000_ICR_GPI_EN1)) { 2159 boolean_t link_changed; 2160 timeout_id_t tid = 0; 2161 2162 stop_watchdog_timer(Adapter); 2163 2164 rw_enter(&Adapter->chip_lock, RW_WRITER); 2165 2166 /* 2167 * Because we got a link-status-change interrupt, force 2168 * e1000_check_for_link() to look at phy 2169 */ 2170 Adapter->shared.mac.get_link_status = B_TRUE; 2171 2172 /* e1000g_link_check takes care of link status change */ 2173 link_changed = e1000g_link_check(Adapter); 2174 2175 /* Get new phy state */ 2176 e1000g_get_phy_state(Adapter); 2177 2178 /* 2179 * If the link timer has not timed out, we'll not notify 2180 * the upper layer with any link state until the link is up. 2181 */ 2182 if (link_changed && !Adapter->link_complete) { 2183 if (Adapter->link_state == LINK_STATE_UP) { 2184 mutex_enter(&Adapter->link_lock); 2185 Adapter->link_complete = B_TRUE; 2186 tid = Adapter->link_tid; 2187 Adapter->link_tid = 0; 2188 mutex_exit(&Adapter->link_lock); 2189 } else { 2190 link_changed = B_FALSE; 2191 } 2192 } 2193 rw_exit(&Adapter->chip_lock); 2194 2195 if (link_changed) { 2196 if (tid != 0) 2197 (void) untimeout(tid); 2198 2199 /* 2200 * Workaround for esb2. Data stuck in fifo on a link 2201 * down event. Stop receiver here and reset in watchdog. 2202 */ 2203 if ((Adapter->link_state == LINK_STATE_DOWN) && 2204 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2205 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2206 E1000_WRITE_REG(hw, E1000_RCTL, 2207 rctl & ~E1000_RCTL_EN); 2208 e1000g_log(Adapter, CE_WARN, 2209 "ESB2 receiver disabled"); 2210 Adapter->esb2_workaround = B_TRUE; 2211 } 2212 if (!Adapter->reset_flag) 2213 mac_link_update(Adapter->mh, 2214 Adapter->link_state); 2215 if (Adapter->link_state == LINK_STATE_UP) 2216 Adapter->reset_flag = B_FALSE; 2217 } 2218 2219 start_watchdog_timer(Adapter); 2220 } 2221 } 2222 2223 static void 2224 e1000g_init_unicst(struct e1000g *Adapter) 2225 { 2226 struct e1000_hw *hw; 2227 int slot; 2228 2229 hw = &Adapter->shared; 2230 2231 if (Adapter->init_count == 0) { 2232 /* Initialize the multiple unicast addresses */ 2233 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2234 2235 /* Workaround for an erratum of 82571 chipst */ 2236 if ((hw->mac.type == e1000_82571) && 2237 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2238 Adapter->unicst_total--; 2239 2240 Adapter->unicst_avail = Adapter->unicst_total; 2241 2242 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2243 /* Clear both the flag and MAC address */ 2244 Adapter->unicst_addr[slot].reg.high = 0; 2245 Adapter->unicst_addr[slot].reg.low = 0; 2246 } 2247 } else { 2248 /* Workaround for an erratum of 82571 chipst */ 2249 if ((hw->mac.type == e1000_82571) && 2250 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2251 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2252 2253 /* Re-configure the RAR registers */ 2254 for (slot = 0; slot < Adapter->unicst_total; slot++) 2255 if (Adapter->unicst_addr[slot].mac.set == 1) 2256 e1000_rar_set(hw, 2257 Adapter->unicst_addr[slot].mac.addr, slot); 2258 } 2259 2260 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2261 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2262 } 2263 2264 static int 2265 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2266 int slot) 2267 { 2268 struct e1000_hw *hw; 2269 2270 hw = &Adapter->shared; 2271 2272 /* 2273 * The first revision of Wiseman silicon (rev 2.0) has an errata 2274 * that requires the receiver to be in reset when any of the 2275 * receive address registers (RAR regs) are accessed. The first 2276 * rev of Wiseman silicon also requires MWI to be disabled when 2277 * a global reset or a receive reset is issued. So before we 2278 * initialize the RARs, we check the rev of the Wiseman controller 2279 * and work around any necessary HW errata. 2280 */ 2281 if ((hw->mac.type == e1000_82542) && 2282 (hw->revision_id == E1000_REVISION_2)) { 2283 e1000_pci_clear_mwi(hw); 2284 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2285 msec_delay(5); 2286 } 2287 if (mac_addr == NULL) { 2288 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0); 2289 E1000_WRITE_FLUSH(hw); 2290 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0); 2291 E1000_WRITE_FLUSH(hw); 2292 /* Clear both the flag and MAC address */ 2293 Adapter->unicst_addr[slot].reg.high = 0; 2294 Adapter->unicst_addr[slot].reg.low = 0; 2295 } else { 2296 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, 2297 ETHERADDRL); 2298 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2299 Adapter->unicst_addr[slot].mac.set = 1; 2300 } 2301 2302 /* Workaround for an erratum of 82571 chipst */ 2303 if (slot == 0) { 2304 if ((hw->mac.type == e1000_82571) && 2305 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2306 if (mac_addr == NULL) { 2307 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2308 slot << 1, 0); 2309 E1000_WRITE_FLUSH(hw); 2310 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2311 (slot << 1) + 1, 0); 2312 E1000_WRITE_FLUSH(hw); 2313 } else { 2314 e1000_rar_set(hw, (uint8_t *)mac_addr, 2315 LAST_RAR_ENTRY); 2316 } 2317 } 2318 2319 /* 2320 * If we are using Wiseman rev 2.0 silicon, we will have previously 2321 * put the receive in reset, and disabled MWI, to work around some 2322 * HW errata. Now we should take the receiver out of reset, and 2323 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2324 */ 2325 if ((hw->mac.type == e1000_82542) && 2326 (hw->revision_id == E1000_REVISION_2)) { 2327 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2328 msec_delay(1); 2329 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2330 e1000_pci_set_mwi(hw); 2331 e1000g_rx_setup(Adapter); 2332 } 2333 2334 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2335 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2336 return (EIO); 2337 } 2338 2339 return (0); 2340 } 2341 2342 static int 2343 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2344 { 2345 struct e1000_hw *hw = &Adapter->shared; 2346 int res = 0; 2347 2348 if ((multiaddr[0] & 01) == 0) { 2349 res = EINVAL; 2350 goto done; 2351 } 2352 2353 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2354 res = ENOENT; 2355 goto done; 2356 } 2357 2358 bcopy(multiaddr, 2359 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2360 Adapter->mcast_count++; 2361 2362 /* 2363 * Update the MC table in the hardware 2364 */ 2365 e1000g_clear_interrupt(Adapter); 2366 2367 e1000g_setup_multicast(Adapter); 2368 2369 if ((hw->mac.type == e1000_82542) && 2370 (hw->revision_id == E1000_REVISION_2)) 2371 e1000g_rx_setup(Adapter); 2372 2373 e1000g_mask_interrupt(Adapter); 2374 2375 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2376 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2377 res = EIO; 2378 } 2379 2380 done: 2381 return (res); 2382 } 2383 2384 static int 2385 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2386 { 2387 struct e1000_hw *hw = &Adapter->shared; 2388 unsigned i; 2389 2390 for (i = 0; i < Adapter->mcast_count; i++) { 2391 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2392 ETHERADDRL) == 0) { 2393 for (i++; i < Adapter->mcast_count; i++) { 2394 Adapter->mcast_table[i - 1] = 2395 Adapter->mcast_table[i]; 2396 } 2397 Adapter->mcast_count--; 2398 break; 2399 } 2400 } 2401 2402 /* 2403 * Update the MC table in the hardware 2404 */ 2405 e1000g_clear_interrupt(Adapter); 2406 2407 e1000g_setup_multicast(Adapter); 2408 2409 if ((hw->mac.type == e1000_82542) && 2410 (hw->revision_id == E1000_REVISION_2)) 2411 e1000g_rx_setup(Adapter); 2412 2413 e1000g_mask_interrupt(Adapter); 2414 2415 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2416 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2417 return (EIO); 2418 } 2419 2420 return (0); 2421 } 2422 2423 /* 2424 * e1000g_setup_multicast - setup multicast data structures 2425 * 2426 * This routine initializes all of the multicast related structures. 2427 */ 2428 void 2429 e1000g_setup_multicast(struct e1000g *Adapter) 2430 { 2431 uint8_t *mc_addr_list; 2432 uint32_t mc_addr_count; 2433 uint32_t rctl; 2434 struct e1000_hw *hw; 2435 2436 hw = &Adapter->shared; 2437 2438 /* 2439 * The e1000g has the ability to do perfect filtering of 16 2440 * addresses. The driver uses one of the e1000g's 16 receive 2441 * address registers for its node/network/mac/individual address. 2442 * So, we have room for up to 15 multicast addresses in the CAM, 2443 * additional MC addresses are handled by the MTA (Multicast Table 2444 * Array) 2445 */ 2446 2447 rctl = E1000_READ_REG(hw, E1000_RCTL); 2448 2449 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2450 2451 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2452 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2453 "Adapter requested more than %d MC Addresses.\n", 2454 MAX_NUM_MULTICAST_ADDRESSES); 2455 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2456 } else { 2457 /* 2458 * Set the number of MC addresses that we are being 2459 * requested to use 2460 */ 2461 mc_addr_count = Adapter->mcast_count; 2462 } 2463 /* 2464 * The Wiseman 2.0 silicon has an errata by which the receiver will 2465 * hang while writing to the receive address registers if the receiver 2466 * is not in reset before writing to the registers. Updating the RAR 2467 * is done during the setting up of the multicast table, hence the 2468 * receiver has to be put in reset before updating the multicast table 2469 * and then taken out of reset at the end 2470 */ 2471 /* 2472 * if WMI was enabled then dis able it before issueing the global 2473 * reset to the hardware. 2474 */ 2475 /* 2476 * Only required for WISEMAN_2_0 2477 */ 2478 if ((hw->mac.type == e1000_82542) && 2479 (hw->revision_id == E1000_REVISION_2)) { 2480 e1000_pci_clear_mwi(hw); 2481 /* 2482 * The e1000g must be in reset before changing any RA 2483 * registers. Reset receive unit. The chip will remain in 2484 * the reset state until software explicitly restarts it. 2485 */ 2486 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2487 /* Allow receiver time to go in to reset */ 2488 msec_delay(5); 2489 } 2490 2491 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2492 Adapter->unicst_total, hw->mac.rar_entry_count); 2493 2494 /* 2495 * Only for Wiseman_2_0 2496 * If MWI was enabled then re-enable it after issueing (as we 2497 * disabled it up there) the receive reset command. 2498 * Wainwright does not have a receive reset command and only thing 2499 * close to it is global reset which will require tx setup also 2500 */ 2501 if ((hw->mac.type == e1000_82542) && 2502 (hw->revision_id == E1000_REVISION_2)) { 2503 /* 2504 * if WMI was enabled then reenable it after issueing the 2505 * global or receive reset to the hardware. 2506 */ 2507 2508 /* 2509 * Take receiver out of reset 2510 * clear E1000_RCTL_RST bit (and all others) 2511 */ 2512 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2513 msec_delay(5); 2514 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2515 e1000_pci_set_mwi(hw); 2516 } 2517 2518 /* 2519 * Restore original value 2520 */ 2521 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2522 } 2523 2524 int 2525 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2526 { 2527 struct e1000g *Adapter = (struct e1000g *)arg; 2528 int result; 2529 2530 rw_enter(&Adapter->chip_lock, RW_WRITER); 2531 2532 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2533 result = ECANCELED; 2534 goto done; 2535 } 2536 2537 result = (add) ? multicst_add(Adapter, addr) 2538 : multicst_remove(Adapter, addr); 2539 2540 done: 2541 rw_exit(&Adapter->chip_lock); 2542 return (result); 2543 2544 } 2545 2546 int 2547 e1000g_m_promisc(void *arg, boolean_t on) 2548 { 2549 struct e1000g *Adapter = (struct e1000g *)arg; 2550 uint32_t rctl; 2551 2552 rw_enter(&Adapter->chip_lock, RW_WRITER); 2553 2554 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2555 rw_exit(&Adapter->chip_lock); 2556 return (ECANCELED); 2557 } 2558 2559 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2560 2561 if (on) 2562 rctl |= 2563 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2564 else 2565 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2566 2567 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2568 2569 Adapter->e1000g_promisc = on; 2570 2571 rw_exit(&Adapter->chip_lock); 2572 2573 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2574 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2575 return (EIO); 2576 } 2577 2578 return (0); 2579 } 2580 2581 /* 2582 * Entry points to enable and disable interrupts at the granularity of 2583 * a group. 2584 * Turns the poll_mode for the whole adapter on and off to enable or 2585 * override the ring level polling control over the hardware interrupts. 2586 */ 2587 static int 2588 e1000g_rx_group_intr_enable(mac_intr_handle_t arg) 2589 { 2590 struct e1000g *adapter = (struct e1000g *)arg; 2591 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2592 2593 /* 2594 * Later interrupts at the granularity of the this ring will 2595 * invoke mac_rx() with NULL, indicating the need for another 2596 * software classification. 2597 * We have a single ring usable per adapter now, so we only need to 2598 * reset the rx handle for that one. 2599 * When more RX rings can be used, we should update each one of them. 2600 */ 2601 mutex_enter(&rx_ring->rx_lock); 2602 rx_ring->mrh = NULL; 2603 adapter->poll_mode = B_FALSE; 2604 mutex_exit(&rx_ring->rx_lock); 2605 return (0); 2606 } 2607 2608 static int 2609 e1000g_rx_group_intr_disable(mac_intr_handle_t arg) 2610 { 2611 struct e1000g *adapter = (struct e1000g *)arg; 2612 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2613 2614 mutex_enter(&rx_ring->rx_lock); 2615 2616 /* 2617 * Later interrupts at the granularity of the this ring will 2618 * invoke mac_rx() with the handle for this ring; 2619 */ 2620 adapter->poll_mode = B_TRUE; 2621 rx_ring->mrh = rx_ring->mrh_init; 2622 mutex_exit(&rx_ring->rx_lock); 2623 return (0); 2624 } 2625 2626 /* 2627 * Entry points to enable and disable interrupts at the granularity of 2628 * a ring. 2629 * adapter poll_mode controls whether we actually proceed with hardware 2630 * interrupt toggling. 2631 */ 2632 static int 2633 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh) 2634 { 2635 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2636 struct e1000g *adapter = rx_ring->adapter; 2637 struct e1000_hw *hw = &adapter->shared; 2638 uint32_t intr_mask; 2639 2640 rw_enter(&adapter->chip_lock, RW_READER); 2641 2642 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2643 rw_exit(&adapter->chip_lock); 2644 return (0); 2645 } 2646 2647 mutex_enter(&rx_ring->rx_lock); 2648 rx_ring->poll_flag = 0; 2649 mutex_exit(&rx_ring->rx_lock); 2650 2651 /* Rx interrupt enabling for MSI and legacy */ 2652 intr_mask = E1000_READ_REG(hw, E1000_IMS); 2653 intr_mask |= E1000_IMS_RXT0; 2654 E1000_WRITE_REG(hw, E1000_IMS, intr_mask); 2655 E1000_WRITE_FLUSH(hw); 2656 2657 /* Trigger a Rx interrupt to check Rx ring */ 2658 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2659 E1000_WRITE_FLUSH(hw); 2660 2661 rw_exit(&adapter->chip_lock); 2662 return (0); 2663 } 2664 2665 static int 2666 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh) 2667 { 2668 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2669 struct e1000g *adapter = rx_ring->adapter; 2670 struct e1000_hw *hw = &adapter->shared; 2671 2672 rw_enter(&adapter->chip_lock, RW_READER); 2673 2674 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2675 rw_exit(&adapter->chip_lock); 2676 return (0); 2677 } 2678 mutex_enter(&rx_ring->rx_lock); 2679 rx_ring->poll_flag = 1; 2680 mutex_exit(&rx_ring->rx_lock); 2681 2682 /* Rx interrupt disabling for MSI and legacy */ 2683 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0); 2684 E1000_WRITE_FLUSH(hw); 2685 2686 rw_exit(&adapter->chip_lock); 2687 return (0); 2688 } 2689 2690 /* 2691 * e1000g_unicst_find - Find the slot for the specified unicast address 2692 */ 2693 static int 2694 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr) 2695 { 2696 int slot; 2697 2698 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2699 if ((Adapter->unicst_addr[slot].mac.set == 1) && 2700 (bcmp(Adapter->unicst_addr[slot].mac.addr, 2701 mac_addr, ETHERADDRL) == 0)) 2702 return (slot); 2703 } 2704 2705 return (-1); 2706 } 2707 2708 /* 2709 * Entry points to add and remove a MAC address to a ring group. 2710 * The caller takes care of adding and removing the MAC addresses 2711 * to the filter via these two routines. 2712 */ 2713 2714 static int 2715 e1000g_addmac(void *arg, const uint8_t *mac_addr) 2716 { 2717 struct e1000g *Adapter = (struct e1000g *)arg; 2718 int slot, err; 2719 2720 rw_enter(&Adapter->chip_lock, RW_WRITER); 2721 2722 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2723 rw_exit(&Adapter->chip_lock); 2724 return (ECANCELED); 2725 } 2726 2727 if (e1000g_unicst_find(Adapter, mac_addr) != -1) { 2728 /* The same address is already in slot */ 2729 rw_exit(&Adapter->chip_lock); 2730 return (0); 2731 } 2732 2733 if (Adapter->unicst_avail == 0) { 2734 /* no slots available */ 2735 rw_exit(&Adapter->chip_lock); 2736 return (ENOSPC); 2737 } 2738 2739 /* Search for a free slot */ 2740 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2741 if (Adapter->unicst_addr[slot].mac.set == 0) 2742 break; 2743 } 2744 ASSERT(slot < Adapter->unicst_total); 2745 2746 err = e1000g_unicst_set(Adapter, mac_addr, slot); 2747 if (err == 0) 2748 Adapter->unicst_avail--; 2749 2750 rw_exit(&Adapter->chip_lock); 2751 2752 return (err); 2753 } 2754 2755 static int 2756 e1000g_remmac(void *arg, const uint8_t *mac_addr) 2757 { 2758 struct e1000g *Adapter = (struct e1000g *)arg; 2759 int slot, err; 2760 2761 rw_enter(&Adapter->chip_lock, RW_WRITER); 2762 2763 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2764 rw_exit(&Adapter->chip_lock); 2765 return (ECANCELED); 2766 } 2767 2768 slot = e1000g_unicst_find(Adapter, mac_addr); 2769 if (slot == -1) { 2770 rw_exit(&Adapter->chip_lock); 2771 return (EINVAL); 2772 } 2773 2774 ASSERT(Adapter->unicst_addr[slot].mac.set); 2775 2776 /* Clear this slot */ 2777 err = e1000g_unicst_set(Adapter, NULL, slot); 2778 if (err == 0) 2779 Adapter->unicst_avail++; 2780 2781 rw_exit(&Adapter->chip_lock); 2782 2783 return (err); 2784 } 2785 2786 static int 2787 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num) 2788 { 2789 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh; 2790 2791 mutex_enter(&rx_ring->rx_lock); 2792 rx_ring->ring_gen_num = mr_gen_num; 2793 mutex_exit(&rx_ring->rx_lock); 2794 return (0); 2795 } 2796 2797 /* 2798 * Callback funtion for MAC layer to register all rings. 2799 * 2800 * The hardware supports a single group with currently only one ring 2801 * available. 2802 * Though not offering virtualization ability per se, exposing the 2803 * group/ring still enables the polling and interrupt toggling. 2804 */ 2805 void 2806 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index, 2807 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh) 2808 { 2809 struct e1000g *Adapter = (struct e1000g *)arg; 2810 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 2811 mac_intr_t *mintr; 2812 2813 /* 2814 * We advertised only RX group/rings, so the MAC framework shouldn't 2815 * ask for any thing else. 2816 */ 2817 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0); 2818 2819 rx_ring->mrh = rx_ring->mrh_init = rh; 2820 infop->mri_driver = (mac_ring_driver_t)rx_ring; 2821 infop->mri_start = e1000g_ring_start; 2822 infop->mri_stop = NULL; 2823 infop->mri_poll = e1000g_poll_ring; 2824 2825 /* Ring level interrupts */ 2826 mintr = &infop->mri_intr; 2827 mintr->mi_handle = (mac_intr_handle_t)rx_ring; 2828 mintr->mi_enable = e1000g_rx_ring_intr_enable; 2829 mintr->mi_disable = e1000g_rx_ring_intr_disable; 2830 } 2831 2832 static void 2833 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index, 2834 mac_group_info_t *infop, mac_group_handle_t gh) 2835 { 2836 struct e1000g *Adapter = (struct e1000g *)arg; 2837 mac_intr_t *mintr; 2838 2839 /* 2840 * We advertised a single RX ring. Getting a request for anything else 2841 * signifies a bug in the MAC framework. 2842 */ 2843 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0); 2844 2845 Adapter->rx_group = gh; 2846 2847 infop->mgi_driver = (mac_group_driver_t)Adapter; 2848 infop->mgi_start = NULL; 2849 infop->mgi_stop = NULL; 2850 infop->mgi_addmac = e1000g_addmac; 2851 infop->mgi_remmac = e1000g_remmac; 2852 infop->mgi_count = 1; 2853 2854 /* Group level interrupts */ 2855 mintr = &infop->mgi_intr; 2856 mintr->mi_handle = (mac_intr_handle_t)Adapter; 2857 mintr->mi_enable = e1000g_rx_group_intr_enable; 2858 mintr->mi_disable = e1000g_rx_group_intr_disable; 2859 } 2860 2861 static boolean_t 2862 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2863 { 2864 struct e1000g *Adapter = (struct e1000g *)arg; 2865 2866 switch (cap) { 2867 case MAC_CAPAB_HCKSUM: { 2868 uint32_t *txflags = cap_data; 2869 2870 if (Adapter->tx_hcksum_enable) 2871 *txflags = HCKSUM_IPHDRCKSUM | 2872 HCKSUM_INET_PARTIAL; 2873 else 2874 return (B_FALSE); 2875 break; 2876 } 2877 2878 case MAC_CAPAB_LSO: { 2879 mac_capab_lso_t *cap_lso = cap_data; 2880 2881 if (Adapter->lso_enable) { 2882 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2883 cap_lso->lso_basic_tcp_ipv4.lso_max = 2884 E1000_LSO_MAXLEN; 2885 } else 2886 return (B_FALSE); 2887 break; 2888 } 2889 case MAC_CAPAB_RINGS: { 2890 mac_capab_rings_t *cap_rings = cap_data; 2891 2892 /* No TX rings exposed yet */ 2893 if (cap_rings->mr_type != MAC_RING_TYPE_RX) 2894 return (B_FALSE); 2895 2896 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC; 2897 cap_rings->mr_rnum = 1; 2898 cap_rings->mr_gnum = 1; 2899 cap_rings->mr_rget = e1000g_fill_ring; 2900 cap_rings->mr_gget = e1000g_fill_group; 2901 break; 2902 } 2903 default: 2904 return (B_FALSE); 2905 } 2906 return (B_TRUE); 2907 } 2908 2909 static boolean_t 2910 e1000g_param_locked(mac_prop_id_t pr_num) 2911 { 2912 /* 2913 * All en_* parameters are locked (read-only) while 2914 * the device is in any sort of loopback mode ... 2915 */ 2916 switch (pr_num) { 2917 case MAC_PROP_EN_1000FDX_CAP: 2918 case MAC_PROP_EN_1000HDX_CAP: 2919 case MAC_PROP_EN_100FDX_CAP: 2920 case MAC_PROP_EN_100HDX_CAP: 2921 case MAC_PROP_EN_10FDX_CAP: 2922 case MAC_PROP_EN_10HDX_CAP: 2923 case MAC_PROP_AUTONEG: 2924 case MAC_PROP_FLOWCTRL: 2925 return (B_TRUE); 2926 } 2927 return (B_FALSE); 2928 } 2929 2930 /* 2931 * callback function for set/get of properties 2932 */ 2933 static int 2934 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2935 uint_t pr_valsize, const void *pr_val) 2936 { 2937 struct e1000g *Adapter = arg; 2938 struct e1000_mac_info *mac = &Adapter->shared.mac; 2939 struct e1000_phy_info *phy = &Adapter->shared.phy; 2940 struct e1000_fc_info *fc = &Adapter->shared.fc; 2941 int err = 0; 2942 link_flowctrl_t flowctrl; 2943 uint32_t cur_mtu, new_mtu; 2944 uint64_t tmp = 0; 2945 2946 rw_enter(&Adapter->chip_lock, RW_WRITER); 2947 2948 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2949 rw_exit(&Adapter->chip_lock); 2950 return (ECANCELED); 2951 } 2952 2953 if (Adapter->loopback_mode != E1000G_LB_NONE && 2954 e1000g_param_locked(pr_num)) { 2955 /* 2956 * All en_* parameters are locked (read-only) 2957 * while the device is in any sort of loopback mode. 2958 */ 2959 rw_exit(&Adapter->chip_lock); 2960 return (EBUSY); 2961 } 2962 2963 switch (pr_num) { 2964 case MAC_PROP_EN_1000FDX_CAP: 2965 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 2966 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 2967 goto reset; 2968 case MAC_PROP_EN_100FDX_CAP: 2969 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 2970 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 2971 goto reset; 2972 case MAC_PROP_EN_100HDX_CAP: 2973 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 2974 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 2975 goto reset; 2976 case MAC_PROP_EN_10FDX_CAP: 2977 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 2978 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 2979 goto reset; 2980 case MAC_PROP_EN_10HDX_CAP: 2981 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 2982 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 2983 goto reset; 2984 case MAC_PROP_AUTONEG: 2985 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 2986 goto reset; 2987 case MAC_PROP_FLOWCTRL: 2988 fc->send_xon = B_TRUE; 2989 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 2990 2991 switch (flowctrl) { 2992 default: 2993 err = EINVAL; 2994 break; 2995 case LINK_FLOWCTRL_NONE: 2996 fc->requested_mode = e1000_fc_none; 2997 break; 2998 case LINK_FLOWCTRL_RX: 2999 fc->requested_mode = e1000_fc_rx_pause; 3000 break; 3001 case LINK_FLOWCTRL_TX: 3002 fc->requested_mode = e1000_fc_tx_pause; 3003 break; 3004 case LINK_FLOWCTRL_BI: 3005 fc->requested_mode = e1000_fc_full; 3006 break; 3007 } 3008 reset: 3009 if (err == 0) { 3010 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 3011 err = EINVAL; 3012 } 3013 break; 3014 case MAC_PROP_ADV_1000FDX_CAP: 3015 case MAC_PROP_ADV_1000HDX_CAP: 3016 case MAC_PROP_ADV_100FDX_CAP: 3017 case MAC_PROP_ADV_100HDX_CAP: 3018 case MAC_PROP_ADV_10FDX_CAP: 3019 case MAC_PROP_ADV_10HDX_CAP: 3020 case MAC_PROP_EN_1000HDX_CAP: 3021 case MAC_PROP_STATUS: 3022 case MAC_PROP_SPEED: 3023 case MAC_PROP_DUPLEX: 3024 err = ENOTSUP; /* read-only prop. Can't set this. */ 3025 break; 3026 case MAC_PROP_MTU: 3027 cur_mtu = Adapter->default_mtu; 3028 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 3029 if (new_mtu == cur_mtu) { 3030 err = 0; 3031 break; 3032 } 3033 3034 tmp = new_mtu + sizeof (struct ether_vlan_header) + 3035 ETHERFCSL; 3036 if ((tmp < DEFAULT_FRAME_SIZE) || 3037 (tmp > MAXIMUM_FRAME_SIZE)) { 3038 err = EINVAL; 3039 break; 3040 } 3041 3042 /* ich8 does not support jumbo frames */ 3043 if ((mac->type == e1000_ich8lan) && 3044 (tmp > DEFAULT_FRAME_SIZE)) { 3045 err = EINVAL; 3046 break; 3047 } 3048 /* ich9 does not do jumbo frames on one phy type */ 3049 if ((mac->type == e1000_ich9lan) && 3050 (phy->type == e1000_phy_ife) && 3051 (tmp > DEFAULT_FRAME_SIZE)) { 3052 err = EINVAL; 3053 break; 3054 } 3055 if (Adapter->e1000g_state & E1000G_STARTED) { 3056 err = EBUSY; 3057 break; 3058 } 3059 3060 err = mac_maxsdu_update(Adapter->mh, new_mtu); 3061 if (err == 0) { 3062 Adapter->max_frame_size = (uint32_t)tmp; 3063 Adapter->default_mtu = new_mtu; 3064 e1000g_set_bufsize(Adapter); 3065 } 3066 break; 3067 case MAC_PROP_PRIVATE: 3068 err = e1000g_set_priv_prop(Adapter, pr_name, 3069 pr_valsize, pr_val); 3070 break; 3071 default: 3072 err = ENOTSUP; 3073 break; 3074 } 3075 rw_exit(&Adapter->chip_lock); 3076 return (err); 3077 } 3078 3079 static int 3080 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3081 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3082 { 3083 struct e1000g *Adapter = arg; 3084 struct e1000_fc_info *fc = &Adapter->shared.fc; 3085 int err = 0; 3086 link_flowctrl_t flowctrl; 3087 uint64_t tmp = 0; 3088 3089 if (pr_valsize == 0) 3090 return (EINVAL); 3091 3092 *perm = MAC_PROP_PERM_RW; 3093 3094 bzero(pr_val, pr_valsize); 3095 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 3096 return (e1000g_get_def_val(Adapter, pr_num, 3097 pr_valsize, pr_val)); 3098 } 3099 3100 switch (pr_num) { 3101 case MAC_PROP_DUPLEX: 3102 *perm = MAC_PROP_PERM_READ; 3103 if (pr_valsize >= sizeof (link_duplex_t)) { 3104 bcopy(&Adapter->link_duplex, pr_val, 3105 sizeof (link_duplex_t)); 3106 } else 3107 err = EINVAL; 3108 break; 3109 case MAC_PROP_SPEED: 3110 *perm = MAC_PROP_PERM_READ; 3111 if (pr_valsize >= sizeof (uint64_t)) { 3112 tmp = Adapter->link_speed * 1000000ull; 3113 bcopy(&tmp, pr_val, sizeof (tmp)); 3114 } else 3115 err = EINVAL; 3116 break; 3117 case MAC_PROP_AUTONEG: 3118 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 3119 break; 3120 case MAC_PROP_FLOWCTRL: 3121 if (pr_valsize >= sizeof (link_flowctrl_t)) { 3122 switch (fc->current_mode) { 3123 case e1000_fc_none: 3124 flowctrl = LINK_FLOWCTRL_NONE; 3125 break; 3126 case e1000_fc_rx_pause: 3127 flowctrl = LINK_FLOWCTRL_RX; 3128 break; 3129 case e1000_fc_tx_pause: 3130 flowctrl = LINK_FLOWCTRL_TX; 3131 break; 3132 case e1000_fc_full: 3133 flowctrl = LINK_FLOWCTRL_BI; 3134 break; 3135 } 3136 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 3137 } else 3138 err = EINVAL; 3139 break; 3140 case MAC_PROP_ADV_1000FDX_CAP: 3141 *perm = MAC_PROP_PERM_READ; 3142 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 3143 break; 3144 case MAC_PROP_EN_1000FDX_CAP: 3145 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 3146 break; 3147 case MAC_PROP_ADV_1000HDX_CAP: 3148 *perm = MAC_PROP_PERM_READ; 3149 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 3150 break; 3151 case MAC_PROP_EN_1000HDX_CAP: 3152 *perm = MAC_PROP_PERM_READ; 3153 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 3154 break; 3155 case MAC_PROP_ADV_100FDX_CAP: 3156 *perm = MAC_PROP_PERM_READ; 3157 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 3158 break; 3159 case MAC_PROP_EN_100FDX_CAP: 3160 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 3161 break; 3162 case MAC_PROP_ADV_100HDX_CAP: 3163 *perm = MAC_PROP_PERM_READ; 3164 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 3165 break; 3166 case MAC_PROP_EN_100HDX_CAP: 3167 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 3168 break; 3169 case MAC_PROP_ADV_10FDX_CAP: 3170 *perm = MAC_PROP_PERM_READ; 3171 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 3172 break; 3173 case MAC_PROP_EN_10FDX_CAP: 3174 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 3175 break; 3176 case MAC_PROP_ADV_10HDX_CAP: 3177 *perm = MAC_PROP_PERM_READ; 3178 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 3179 break; 3180 case MAC_PROP_EN_10HDX_CAP: 3181 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 3182 break; 3183 case MAC_PROP_ADV_100T4_CAP: 3184 case MAC_PROP_EN_100T4_CAP: 3185 *perm = MAC_PROP_PERM_READ; 3186 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 3187 break; 3188 case MAC_PROP_PRIVATE: 3189 err = e1000g_get_priv_prop(Adapter, pr_name, 3190 pr_flags, pr_valsize, pr_val, perm); 3191 break; 3192 default: 3193 err = ENOTSUP; 3194 break; 3195 } 3196 return (err); 3197 } 3198 3199 /* ARGSUSED2 */ 3200 static int 3201 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 3202 uint_t pr_valsize, const void *pr_val) 3203 { 3204 int err = 0; 3205 long result; 3206 struct e1000_hw *hw = &Adapter->shared; 3207 3208 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3209 if (pr_val == NULL) { 3210 err = EINVAL; 3211 return (err); 3212 } 3213 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3214 if (result < MIN_TX_BCOPY_THRESHOLD || 3215 result > MAX_TX_BCOPY_THRESHOLD) 3216 err = EINVAL; 3217 else { 3218 Adapter->tx_bcopy_thresh = (uint32_t)result; 3219 } 3220 return (err); 3221 } 3222 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3223 if (pr_val == NULL) { 3224 err = EINVAL; 3225 return (err); 3226 } 3227 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3228 if (result < 0 || result > 1) 3229 err = EINVAL; 3230 else { 3231 Adapter->tx_intr_enable = (result == 1) ? 3232 B_TRUE: B_FALSE; 3233 if (Adapter->tx_intr_enable) 3234 e1000g_mask_tx_interrupt(Adapter); 3235 else 3236 e1000g_clear_tx_interrupt(Adapter); 3237 if (e1000g_check_acc_handle( 3238 Adapter->osdep.reg_handle) != DDI_FM_OK) 3239 ddi_fm_service_impact(Adapter->dip, 3240 DDI_SERVICE_DEGRADED); 3241 } 3242 return (err); 3243 } 3244 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3245 if (pr_val == NULL) { 3246 err = EINVAL; 3247 return (err); 3248 } 3249 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3250 if (result < MIN_TX_INTR_DELAY || 3251 result > MAX_TX_INTR_DELAY) 3252 err = EINVAL; 3253 else { 3254 Adapter->tx_intr_delay = (uint32_t)result; 3255 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 3256 if (e1000g_check_acc_handle( 3257 Adapter->osdep.reg_handle) != DDI_FM_OK) 3258 ddi_fm_service_impact(Adapter->dip, 3259 DDI_SERVICE_DEGRADED); 3260 } 3261 return (err); 3262 } 3263 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3264 if (pr_val == NULL) { 3265 err = EINVAL; 3266 return (err); 3267 } 3268 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3269 if (result < MIN_TX_INTR_ABS_DELAY || 3270 result > MAX_TX_INTR_ABS_DELAY) 3271 err = EINVAL; 3272 else { 3273 Adapter->tx_intr_abs_delay = (uint32_t)result; 3274 E1000_WRITE_REG(hw, E1000_TADV, 3275 Adapter->tx_intr_abs_delay); 3276 if (e1000g_check_acc_handle( 3277 Adapter->osdep.reg_handle) != DDI_FM_OK) 3278 ddi_fm_service_impact(Adapter->dip, 3279 DDI_SERVICE_DEGRADED); 3280 } 3281 return (err); 3282 } 3283 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3284 if (pr_val == NULL) { 3285 err = EINVAL; 3286 return (err); 3287 } 3288 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3289 if (result < MIN_RX_BCOPY_THRESHOLD || 3290 result > MAX_RX_BCOPY_THRESHOLD) 3291 err = EINVAL; 3292 else 3293 Adapter->rx_bcopy_thresh = (uint32_t)result; 3294 return (err); 3295 } 3296 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3297 if (pr_val == NULL) { 3298 err = EINVAL; 3299 return (err); 3300 } 3301 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3302 if (result < MIN_RX_LIMIT_ON_INTR || 3303 result > MAX_RX_LIMIT_ON_INTR) 3304 err = EINVAL; 3305 else 3306 Adapter->rx_limit_onintr = (uint32_t)result; 3307 return (err); 3308 } 3309 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3310 if (pr_val == NULL) { 3311 err = EINVAL; 3312 return (err); 3313 } 3314 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3315 if (result < MIN_RX_INTR_DELAY || 3316 result > MAX_RX_INTR_DELAY) 3317 err = EINVAL; 3318 else { 3319 Adapter->rx_intr_delay = (uint32_t)result; 3320 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3321 if (e1000g_check_acc_handle( 3322 Adapter->osdep.reg_handle) != DDI_FM_OK) 3323 ddi_fm_service_impact(Adapter->dip, 3324 DDI_SERVICE_DEGRADED); 3325 } 3326 return (err); 3327 } 3328 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3329 if (pr_val == NULL) { 3330 err = EINVAL; 3331 return (err); 3332 } 3333 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3334 if (result < MIN_RX_INTR_ABS_DELAY || 3335 result > MAX_RX_INTR_ABS_DELAY) 3336 err = EINVAL; 3337 else { 3338 Adapter->rx_intr_abs_delay = (uint32_t)result; 3339 E1000_WRITE_REG(hw, E1000_RADV, 3340 Adapter->rx_intr_abs_delay); 3341 if (e1000g_check_acc_handle( 3342 Adapter->osdep.reg_handle) != DDI_FM_OK) 3343 ddi_fm_service_impact(Adapter->dip, 3344 DDI_SERVICE_DEGRADED); 3345 } 3346 return (err); 3347 } 3348 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3349 if (pr_val == NULL) { 3350 err = EINVAL; 3351 return (err); 3352 } 3353 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3354 if (result < MIN_INTR_THROTTLING || 3355 result > MAX_INTR_THROTTLING) 3356 err = EINVAL; 3357 else { 3358 if (hw->mac.type >= e1000_82540) { 3359 Adapter->intr_throttling_rate = 3360 (uint32_t)result; 3361 E1000_WRITE_REG(hw, E1000_ITR, 3362 Adapter->intr_throttling_rate); 3363 if (e1000g_check_acc_handle( 3364 Adapter->osdep.reg_handle) != DDI_FM_OK) 3365 ddi_fm_service_impact(Adapter->dip, 3366 DDI_SERVICE_DEGRADED); 3367 } else 3368 err = EINVAL; 3369 } 3370 return (err); 3371 } 3372 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3373 if (pr_val == NULL) { 3374 err = EINVAL; 3375 return (err); 3376 } 3377 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3378 if (result < 0 || result > 1) 3379 err = EINVAL; 3380 else { 3381 if (hw->mac.type >= e1000_82540) { 3382 Adapter->intr_adaptive = (result == 1) ? 3383 B_TRUE : B_FALSE; 3384 } else { 3385 err = EINVAL; 3386 } 3387 } 3388 return (err); 3389 } 3390 return (ENOTSUP); 3391 } 3392 3393 static int 3394 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3395 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3396 { 3397 int err = ENOTSUP; 3398 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3399 int value; 3400 3401 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3402 *perm = MAC_PROP_PERM_READ; 3403 if (is_default) 3404 goto done; 3405 value = Adapter->param_adv_pause; 3406 err = 0; 3407 goto done; 3408 } 3409 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3410 *perm = MAC_PROP_PERM_READ; 3411 if (is_default) 3412 goto done; 3413 value = Adapter->param_adv_asym_pause; 3414 err = 0; 3415 goto done; 3416 } 3417 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3418 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3419 Adapter->tx_bcopy_thresh); 3420 err = 0; 3421 goto done; 3422 } 3423 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3424 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3425 Adapter->tx_intr_enable); 3426 err = 0; 3427 goto done; 3428 } 3429 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3430 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3431 Adapter->tx_intr_delay); 3432 err = 0; 3433 goto done; 3434 } 3435 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3436 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3437 Adapter->tx_intr_abs_delay); 3438 err = 0; 3439 goto done; 3440 } 3441 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3442 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3443 Adapter->rx_bcopy_thresh); 3444 err = 0; 3445 goto done; 3446 } 3447 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3448 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3449 Adapter->rx_limit_onintr); 3450 err = 0; 3451 goto done; 3452 } 3453 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3454 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3455 Adapter->rx_intr_delay); 3456 err = 0; 3457 goto done; 3458 } 3459 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3460 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3461 Adapter->rx_intr_abs_delay); 3462 err = 0; 3463 goto done; 3464 } 3465 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3466 value = (is_default ? DEFAULT_INTR_THROTTLING : 3467 Adapter->intr_throttling_rate); 3468 err = 0; 3469 goto done; 3470 } 3471 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3472 value = (is_default ? 1 : Adapter->intr_adaptive); 3473 err = 0; 3474 goto done; 3475 } 3476 done: 3477 if (err == 0) { 3478 (void) snprintf(pr_val, pr_valsize, "%d", value); 3479 } 3480 return (err); 3481 } 3482 3483 /* 3484 * e1000g_get_conf - get configurations set in e1000g.conf 3485 * This routine gets user-configured values out of the configuration 3486 * file e1000g.conf. 3487 * 3488 * For each configurable value, there is a minimum, a maximum, and a 3489 * default. 3490 * If user does not configure a value, use the default. 3491 * If user configures below the minimum, use the minumum. 3492 * If user configures above the maximum, use the maxumum. 3493 */ 3494 static void 3495 e1000g_get_conf(struct e1000g *Adapter) 3496 { 3497 struct e1000_hw *hw = &Adapter->shared; 3498 boolean_t tbi_compatibility = B_FALSE; 3499 3500 /* 3501 * get each configurable property from e1000g.conf 3502 */ 3503 3504 /* 3505 * NumTxDescriptors 3506 */ 3507 Adapter->tx_desc_num = 3508 e1000g_get_prop(Adapter, "NumTxDescriptors", 3509 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3510 DEFAULT_NUM_TX_DESCRIPTOR); 3511 3512 /* 3513 * NumRxDescriptors 3514 */ 3515 Adapter->rx_desc_num = 3516 e1000g_get_prop(Adapter, "NumRxDescriptors", 3517 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3518 DEFAULT_NUM_RX_DESCRIPTOR); 3519 3520 /* 3521 * NumRxFreeList 3522 */ 3523 Adapter->rx_freelist_num = 3524 e1000g_get_prop(Adapter, "NumRxFreeList", 3525 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3526 DEFAULT_NUM_RX_FREELIST); 3527 3528 /* 3529 * NumTxPacketList 3530 */ 3531 Adapter->tx_freelist_num = 3532 e1000g_get_prop(Adapter, "NumTxPacketList", 3533 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3534 DEFAULT_NUM_TX_FREELIST); 3535 3536 /* 3537 * FlowControl 3538 */ 3539 hw->fc.send_xon = B_TRUE; 3540 hw->fc.requested_mode = 3541 e1000g_get_prop(Adapter, "FlowControl", 3542 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3543 /* 4 is the setting that says "let the eeprom decide" */ 3544 if (hw->fc.requested_mode == 4) 3545 hw->fc.requested_mode = e1000_fc_default; 3546 3547 /* 3548 * Max Num Receive Packets on Interrupt 3549 */ 3550 Adapter->rx_limit_onintr = 3551 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3552 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3553 DEFAULT_RX_LIMIT_ON_INTR); 3554 3555 /* 3556 * PHY master slave setting 3557 */ 3558 hw->phy.ms_type = 3559 e1000g_get_prop(Adapter, "SetMasterSlave", 3560 e1000_ms_hw_default, e1000_ms_auto, 3561 e1000_ms_hw_default); 3562 3563 /* 3564 * Parameter which controls TBI mode workaround, which is only 3565 * needed on certain switches such as Cisco 6500/Foundry 3566 */ 3567 tbi_compatibility = 3568 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3569 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3570 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3571 3572 /* 3573 * MSI Enable 3574 */ 3575 Adapter->msi_enable = 3576 e1000g_get_prop(Adapter, "MSIEnable", 3577 0, 1, DEFAULT_MSI_ENABLE); 3578 3579 /* 3580 * Interrupt Throttling Rate 3581 */ 3582 Adapter->intr_throttling_rate = 3583 e1000g_get_prop(Adapter, "intr_throttling_rate", 3584 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3585 DEFAULT_INTR_THROTTLING); 3586 3587 /* 3588 * Adaptive Interrupt Blanking Enable/Disable 3589 * It is enabled by default 3590 */ 3591 Adapter->intr_adaptive = 3592 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3593 B_TRUE : B_FALSE; 3594 3595 /* 3596 * Hardware checksum enable/disable parameter 3597 */ 3598 Adapter->tx_hcksum_enable = 3599 e1000g_get_prop(Adapter, "tx_hcksum_enable", 3600 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3601 /* 3602 * Checksum on/off selection via global parameters. 3603 * 3604 * If the chip is flagged as not capable of (correctly) 3605 * handling checksumming, we don't enable it on either 3606 * Rx or Tx side. Otherwise, we take this chip's settings 3607 * from the patchable global defaults. 3608 * 3609 * We advertise our capabilities only if TX offload is 3610 * enabled. On receive, the stack will accept checksummed 3611 * packets anyway, even if we haven't said we can deliver 3612 * them. 3613 */ 3614 switch (hw->mac.type) { 3615 case e1000_82540: 3616 case e1000_82544: 3617 case e1000_82545: 3618 case e1000_82545_rev_3: 3619 case e1000_82546: 3620 case e1000_82546_rev_3: 3621 case e1000_82571: 3622 case e1000_82572: 3623 case e1000_82573: 3624 case e1000_80003es2lan: 3625 break; 3626 /* 3627 * For the following Intel PRO/1000 chipsets, we have not 3628 * tested the hardware checksum offload capability, so we 3629 * disable the capability for them. 3630 * e1000_82542, 3631 * e1000_82543, 3632 * e1000_82541, 3633 * e1000_82541_rev_2, 3634 * e1000_82547, 3635 * e1000_82547_rev_2, 3636 */ 3637 default: 3638 Adapter->tx_hcksum_enable = B_FALSE; 3639 } 3640 3641 /* 3642 * Large Send Offloading(LSO) Enable/Disable 3643 * If the tx hardware checksum is not enabled, LSO should be 3644 * disabled. 3645 */ 3646 Adapter->lso_enable = 3647 e1000g_get_prop(Adapter, "lso_enable", 3648 0, 1, DEFAULT_LSO_ENABLE); 3649 3650 switch (hw->mac.type) { 3651 case e1000_82546: 3652 case e1000_82546_rev_3: 3653 if (Adapter->lso_enable) 3654 Adapter->lso_premature_issue = B_TRUE; 3655 /* FALLTHRU */ 3656 case e1000_82571: 3657 case e1000_82572: 3658 case e1000_82573: 3659 case e1000_80003es2lan: 3660 break; 3661 default: 3662 Adapter->lso_enable = B_FALSE; 3663 } 3664 3665 if (!Adapter->tx_hcksum_enable) { 3666 Adapter->lso_premature_issue = B_FALSE; 3667 Adapter->lso_enable = B_FALSE; 3668 } 3669 3670 /* 3671 * If mem_workaround_82546 is enabled, the rx buffer allocated by 3672 * e1000_82545, e1000_82546 and e1000_82546_rev_3 3673 * will not cross 64k boundary. 3674 */ 3675 Adapter->mem_workaround_82546 = 3676 e1000g_get_prop(Adapter, "mem_workaround_82546", 3677 0, 1, DEFAULT_MEM_WORKAROUND_82546); 3678 } 3679 3680 /* 3681 * e1000g_get_prop - routine to read properties 3682 * 3683 * Get a user-configure property value out of the configuration 3684 * file e1000g.conf. 3685 * 3686 * Caller provides name of the property, a default value, a minimum 3687 * value, and a maximum value. 3688 * 3689 * Return configured value of the property, with default, minimum and 3690 * maximum properly applied. 3691 */ 3692 static int 3693 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3694 char *propname, /* name of the property */ 3695 int minval, /* minimum acceptable value */ 3696 int maxval, /* maximim acceptable value */ 3697 int defval) /* default value */ 3698 { 3699 int propval; /* value returned for requested property */ 3700 int *props; /* point to array of properties returned */ 3701 uint_t nprops; /* number of property value returned */ 3702 3703 /* 3704 * get the array of properties from the config file 3705 */ 3706 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3707 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3708 /* got some properties, test if we got enough */ 3709 if (Adapter->instance < nprops) { 3710 propval = props[Adapter->instance]; 3711 } else { 3712 /* not enough properties configured */ 3713 propval = defval; 3714 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3715 "Not Enough %s values found in e1000g.conf" 3716 " - set to %d\n", 3717 propname, propval); 3718 } 3719 3720 /* free memory allocated for properties */ 3721 ddi_prop_free(props); 3722 3723 } else { 3724 propval = defval; 3725 } 3726 3727 /* 3728 * enforce limits 3729 */ 3730 if (propval > maxval) { 3731 propval = maxval; 3732 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3733 "Too High %s value in e1000g.conf - set to %d\n", 3734 propname, propval); 3735 } 3736 3737 if (propval < minval) { 3738 propval = minval; 3739 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3740 "Too Low %s value in e1000g.conf - set to %d\n", 3741 propname, propval); 3742 } 3743 3744 return (propval); 3745 } 3746 3747 static boolean_t 3748 e1000g_link_check(struct e1000g *Adapter) 3749 { 3750 uint16_t speed, duplex, phydata; 3751 boolean_t link_changed = B_FALSE; 3752 struct e1000_hw *hw; 3753 uint32_t reg_tarc; 3754 3755 hw = &Adapter->shared; 3756 3757 if (e1000g_link_up(Adapter)) { 3758 /* 3759 * The Link is up, check whether it was marked as down earlier 3760 */ 3761 if (Adapter->link_state != LINK_STATE_UP) { 3762 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3763 Adapter->link_speed = speed; 3764 Adapter->link_duplex = duplex; 3765 Adapter->link_state = LINK_STATE_UP; 3766 link_changed = B_TRUE; 3767 3768 if (Adapter->link_speed == SPEED_1000) 3769 Adapter->stall_threshold = TX_STALL_TIME_2S; 3770 else 3771 Adapter->stall_threshold = TX_STALL_TIME_8S; 3772 3773 Adapter->tx_link_down_timeout = 0; 3774 3775 if ((hw->mac.type == e1000_82571) || 3776 (hw->mac.type == e1000_82572)) { 3777 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3778 if (speed == SPEED_1000) 3779 reg_tarc |= (1 << 21); 3780 else 3781 reg_tarc &= ~(1 << 21); 3782 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3783 } 3784 } 3785 Adapter->smartspeed = 0; 3786 } else { 3787 if (Adapter->link_state != LINK_STATE_DOWN) { 3788 Adapter->link_speed = 0; 3789 Adapter->link_duplex = 0; 3790 Adapter->link_state = LINK_STATE_DOWN; 3791 link_changed = B_TRUE; 3792 3793 /* 3794 * SmartSpeed workaround for Tabor/TanaX, When the 3795 * driver loses link disable auto master/slave 3796 * resolution. 3797 */ 3798 if (hw->phy.type == e1000_phy_igp) { 3799 (void) e1000_read_phy_reg(hw, 3800 PHY_1000T_CTRL, &phydata); 3801 phydata |= CR_1000T_MS_ENABLE; 3802 (void) e1000_write_phy_reg(hw, 3803 PHY_1000T_CTRL, phydata); 3804 } 3805 } else { 3806 e1000g_smartspeed(Adapter); 3807 } 3808 3809 if (Adapter->e1000g_state & E1000G_STARTED) { 3810 if (Adapter->tx_link_down_timeout < 3811 MAX_TX_LINK_DOWN_TIMEOUT) { 3812 Adapter->tx_link_down_timeout++; 3813 } else if (Adapter->tx_link_down_timeout == 3814 MAX_TX_LINK_DOWN_TIMEOUT) { 3815 e1000g_tx_clean(Adapter); 3816 Adapter->tx_link_down_timeout++; 3817 } 3818 } 3819 } 3820 3821 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3822 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3823 3824 return (link_changed); 3825 } 3826 3827 /* 3828 * e1000g_reset_link - Using the link properties to setup the link 3829 */ 3830 int 3831 e1000g_reset_link(struct e1000g *Adapter) 3832 { 3833 struct e1000_mac_info *mac; 3834 struct e1000_phy_info *phy; 3835 boolean_t invalid; 3836 3837 mac = &Adapter->shared.mac; 3838 phy = &Adapter->shared.phy; 3839 invalid = B_FALSE; 3840 3841 if (Adapter->param_adv_autoneg == 1) { 3842 mac->autoneg = B_TRUE; 3843 phy->autoneg_advertised = 0; 3844 3845 /* 3846 * 1000hdx is not supported for autonegotiation 3847 */ 3848 if (Adapter->param_adv_1000fdx == 1) 3849 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3850 3851 if (Adapter->param_adv_100fdx == 1) 3852 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3853 3854 if (Adapter->param_adv_100hdx == 1) 3855 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3856 3857 if (Adapter->param_adv_10fdx == 1) 3858 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3859 3860 if (Adapter->param_adv_10hdx == 1) 3861 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3862 3863 if (phy->autoneg_advertised == 0) 3864 invalid = B_TRUE; 3865 } else { 3866 mac->autoneg = B_FALSE; 3867 3868 /* 3869 * 1000fdx and 1000hdx are not supported for forced link 3870 */ 3871 if (Adapter->param_adv_100fdx == 1) 3872 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3873 else if (Adapter->param_adv_100hdx == 1) 3874 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3875 else if (Adapter->param_adv_10fdx == 1) 3876 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3877 else if (Adapter->param_adv_10hdx == 1) 3878 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3879 else 3880 invalid = B_TRUE; 3881 3882 } 3883 3884 if (invalid) { 3885 e1000g_log(Adapter, CE_WARN, 3886 "Invalid link sets. Setup link to" 3887 "support autonegotiation with all link capabilities."); 3888 mac->autoneg = B_TRUE; 3889 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3890 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3891 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3892 } 3893 3894 return (e1000_setup_link(&Adapter->shared)); 3895 } 3896 3897 static void 3898 e1000g_timer_tx_resched(struct e1000g *Adapter) 3899 { 3900 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 3901 3902 rw_enter(&Adapter->chip_lock, RW_READER); 3903 3904 if (tx_ring->resched_needed && 3905 ((ddi_get_lbolt() - tx_ring->resched_timestamp) > 3906 drv_usectohz(1000000)) && 3907 (Adapter->e1000g_state & E1000G_STARTED) && 3908 (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) { 3909 tx_ring->resched_needed = B_FALSE; 3910 mac_tx_update(Adapter->mh); 3911 E1000G_STAT(tx_ring->stat_reschedule); 3912 E1000G_STAT(tx_ring->stat_timer_reschedule); 3913 } 3914 3915 rw_exit(&Adapter->chip_lock); 3916 } 3917 3918 static void 3919 e1000g_local_timer(void *ws) 3920 { 3921 struct e1000g *Adapter = (struct e1000g *)ws; 3922 struct e1000_hw *hw; 3923 e1000g_ether_addr_t ether_addr; 3924 boolean_t link_changed; 3925 3926 hw = &Adapter->shared; 3927 3928 if (Adapter->e1000g_state & E1000G_ERROR) { 3929 rw_enter(&Adapter->chip_lock, RW_WRITER); 3930 Adapter->e1000g_state &= ~E1000G_ERROR; 3931 rw_exit(&Adapter->chip_lock); 3932 3933 Adapter->reset_count++; 3934 if (e1000g_global_reset(Adapter)) { 3935 ddi_fm_service_impact(Adapter->dip, 3936 DDI_SERVICE_RESTORED); 3937 e1000g_timer_tx_resched(Adapter); 3938 } else 3939 ddi_fm_service_impact(Adapter->dip, 3940 DDI_SERVICE_LOST); 3941 return; 3942 } 3943 3944 if (e1000g_stall_check(Adapter)) { 3945 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3946 "Tx stall detected. Activate automatic recovery.\n"); 3947 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 3948 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 3949 Adapter->reset_count++; 3950 if (e1000g_reset_adapter(Adapter)) { 3951 ddi_fm_service_impact(Adapter->dip, 3952 DDI_SERVICE_RESTORED); 3953 e1000g_timer_tx_resched(Adapter); 3954 } 3955 return; 3956 } 3957 3958 link_changed = B_FALSE; 3959 rw_enter(&Adapter->chip_lock, RW_READER); 3960 if (Adapter->link_complete) 3961 link_changed = e1000g_link_check(Adapter); 3962 rw_exit(&Adapter->chip_lock); 3963 3964 if (link_changed) { 3965 if (!Adapter->reset_flag) 3966 mac_link_update(Adapter->mh, Adapter->link_state); 3967 if (Adapter->link_state == LINK_STATE_UP) 3968 Adapter->reset_flag = B_FALSE; 3969 } 3970 /* 3971 * Workaround for esb2. Data stuck in fifo on a link 3972 * down event. Reset the adapter to recover it. 3973 */ 3974 if (Adapter->esb2_workaround) { 3975 Adapter->esb2_workaround = B_FALSE; 3976 (void) e1000g_reset_adapter(Adapter); 3977 return; 3978 } 3979 3980 /* 3981 * With 82571 controllers, any locally administered address will 3982 * be overwritten when there is a reset on the other port. 3983 * Detect this circumstance and correct it. 3984 */ 3985 if ((hw->mac.type == e1000_82571) && 3986 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 3987 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 3988 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 3989 3990 ether_addr.reg.low = ntohl(ether_addr.reg.low); 3991 ether_addr.reg.high = ntohl(ether_addr.reg.high); 3992 3993 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 3994 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 3995 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 3996 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 3997 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 3998 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 3999 e1000_rar_set(hw, hw->mac.addr, 0); 4000 } 4001 } 4002 4003 /* 4004 * Long TTL workaround for 82541/82547 4005 */ 4006 (void) e1000_igp_ttl_workaround_82547(hw); 4007 4008 /* 4009 * Check for Adaptive IFS settings If there are lots of collisions 4010 * change the value in steps... 4011 * These properties should only be set for 10/100 4012 */ 4013 if ((hw->phy.media_type == e1000_media_type_copper) && 4014 ((Adapter->link_speed == SPEED_100) || 4015 (Adapter->link_speed == SPEED_10))) { 4016 e1000_update_adaptive(hw); 4017 } 4018 /* 4019 * Set Timer Interrupts 4020 */ 4021 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 4022 4023 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4024 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4025 else 4026 e1000g_timer_tx_resched(Adapter); 4027 4028 restart_watchdog_timer(Adapter); 4029 } 4030 4031 /* 4032 * The function e1000g_link_timer() is called when the timer for link setup 4033 * is expired, which indicates the completion of the link setup. The link 4034 * state will not be updated until the link setup is completed. And the 4035 * link state will not be sent to the upper layer through mac_link_update() 4036 * in this function. It will be updated in the local timer routine or the 4037 * interrupt service routine after the interface is started (plumbed). 4038 */ 4039 static void 4040 e1000g_link_timer(void *arg) 4041 { 4042 struct e1000g *Adapter = (struct e1000g *)arg; 4043 4044 mutex_enter(&Adapter->link_lock); 4045 Adapter->link_complete = B_TRUE; 4046 Adapter->link_tid = 0; 4047 mutex_exit(&Adapter->link_lock); 4048 } 4049 4050 /* 4051 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 4052 * 4053 * This function read the forced speed and duplex for 10/100 Mbps speeds 4054 * and also for 1000 Mbps speeds from the e1000g.conf file 4055 */ 4056 static void 4057 e1000g_force_speed_duplex(struct e1000g *Adapter) 4058 { 4059 int forced; 4060 struct e1000_mac_info *mac = &Adapter->shared.mac; 4061 struct e1000_phy_info *phy = &Adapter->shared.phy; 4062 4063 /* 4064 * get value out of config file 4065 */ 4066 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 4067 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 4068 4069 switch (forced) { 4070 case GDIAG_10_HALF: 4071 /* 4072 * Disable Auto Negotiation 4073 */ 4074 mac->autoneg = B_FALSE; 4075 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4076 break; 4077 case GDIAG_10_FULL: 4078 /* 4079 * Disable Auto Negotiation 4080 */ 4081 mac->autoneg = B_FALSE; 4082 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4083 break; 4084 case GDIAG_100_HALF: 4085 /* 4086 * Disable Auto Negotiation 4087 */ 4088 mac->autoneg = B_FALSE; 4089 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4090 break; 4091 case GDIAG_100_FULL: 4092 /* 4093 * Disable Auto Negotiation 4094 */ 4095 mac->autoneg = B_FALSE; 4096 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4097 break; 4098 case GDIAG_1000_FULL: 4099 /* 4100 * The gigabit spec requires autonegotiation. Therefore, 4101 * when the user wants to force the speed to 1000Mbps, we 4102 * enable AutoNeg, but only allow the harware to advertise 4103 * 1000Mbps. This is different from 10/100 operation, where 4104 * we are allowed to link without any negotiation. 4105 */ 4106 mac->autoneg = B_TRUE; 4107 phy->autoneg_advertised = ADVERTISE_1000_FULL; 4108 break; 4109 default: /* obey the setting of AutoNegAdvertised */ 4110 mac->autoneg = B_TRUE; 4111 phy->autoneg_advertised = 4112 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 4113 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 4114 AUTONEG_ADVERTISE_SPEED_DEFAULT); 4115 break; 4116 } /* switch */ 4117 } 4118 4119 /* 4120 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 4121 * 4122 * This function reads MaxFrameSize from e1000g.conf 4123 */ 4124 static void 4125 e1000g_get_max_frame_size(struct e1000g *Adapter) 4126 { 4127 int max_frame; 4128 struct e1000_mac_info *mac = &Adapter->shared.mac; 4129 struct e1000_phy_info *phy = &Adapter->shared.phy; 4130 4131 /* 4132 * get value out of config file 4133 */ 4134 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 4135 4136 switch (max_frame) { 4137 case 0: 4138 Adapter->default_mtu = ETHERMTU; 4139 break; 4140 /* 4141 * To avoid excessive memory allocation for rx buffers, 4142 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 4143 */ 4144 case 1: 4145 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 4146 sizeof (struct ether_vlan_header) - ETHERFCSL - 4147 E1000G_IPALIGNPRESERVEROOM; 4148 break; 4149 case 2: 4150 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 4151 sizeof (struct ether_vlan_header) - ETHERFCSL - 4152 E1000G_IPALIGNPRESERVEROOM; 4153 break; 4154 case 3: 4155 if (mac->type >= e1000_82571) 4156 Adapter->default_mtu = MAXIMUM_MTU; 4157 else 4158 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 4159 sizeof (struct ether_vlan_header) - ETHERFCSL - 4160 E1000G_IPALIGNPRESERVEROOM; 4161 break; 4162 default: 4163 Adapter->default_mtu = ETHERMTU; 4164 break; 4165 } /* switch */ 4166 4167 Adapter->max_frame_size = Adapter->default_mtu + 4168 sizeof (struct ether_vlan_header) + ETHERFCSL; 4169 4170 /* ich8 does not do jumbo frames */ 4171 if (mac->type == e1000_ich8lan) { 4172 Adapter->default_mtu = ETHERMTU; 4173 Adapter->max_frame_size = ETHERMTU + 4174 sizeof (struct ether_vlan_header) + ETHERFCSL; 4175 } 4176 4177 /* ich9 does not do jumbo frames on one phy type */ 4178 if ((mac->type == e1000_ich9lan) && 4179 (phy->type == e1000_phy_ife)) { 4180 Adapter->default_mtu = ETHERMTU; 4181 Adapter->max_frame_size = ETHERMTU + 4182 sizeof (struct ether_vlan_header) + ETHERFCSL; 4183 } 4184 } 4185 4186 static void 4187 arm_watchdog_timer(struct e1000g *Adapter) 4188 { 4189 Adapter->watchdog_tid = 4190 timeout(e1000g_local_timer, 4191 (void *)Adapter, 1 * drv_usectohz(1000000)); 4192 } 4193 #pragma inline(arm_watchdog_timer) 4194 4195 static void 4196 enable_watchdog_timer(struct e1000g *Adapter) 4197 { 4198 mutex_enter(&Adapter->watchdog_lock); 4199 4200 if (!Adapter->watchdog_timer_enabled) { 4201 Adapter->watchdog_timer_enabled = B_TRUE; 4202 Adapter->watchdog_timer_started = B_TRUE; 4203 arm_watchdog_timer(Adapter); 4204 } 4205 4206 mutex_exit(&Adapter->watchdog_lock); 4207 } 4208 4209 static void 4210 disable_watchdog_timer(struct e1000g *Adapter) 4211 { 4212 timeout_id_t tid; 4213 4214 mutex_enter(&Adapter->watchdog_lock); 4215 4216 Adapter->watchdog_timer_enabled = B_FALSE; 4217 Adapter->watchdog_timer_started = B_FALSE; 4218 tid = Adapter->watchdog_tid; 4219 Adapter->watchdog_tid = 0; 4220 4221 mutex_exit(&Adapter->watchdog_lock); 4222 4223 if (tid != 0) 4224 (void) untimeout(tid); 4225 } 4226 4227 static void 4228 start_watchdog_timer(struct e1000g *Adapter) 4229 { 4230 mutex_enter(&Adapter->watchdog_lock); 4231 4232 if (Adapter->watchdog_timer_enabled) { 4233 if (!Adapter->watchdog_timer_started) { 4234 Adapter->watchdog_timer_started = B_TRUE; 4235 arm_watchdog_timer(Adapter); 4236 } 4237 } 4238 4239 mutex_exit(&Adapter->watchdog_lock); 4240 } 4241 4242 static void 4243 restart_watchdog_timer(struct e1000g *Adapter) 4244 { 4245 mutex_enter(&Adapter->watchdog_lock); 4246 4247 if (Adapter->watchdog_timer_started) 4248 arm_watchdog_timer(Adapter); 4249 4250 mutex_exit(&Adapter->watchdog_lock); 4251 } 4252 4253 static void 4254 stop_watchdog_timer(struct e1000g *Adapter) 4255 { 4256 timeout_id_t tid; 4257 4258 mutex_enter(&Adapter->watchdog_lock); 4259 4260 Adapter->watchdog_timer_started = B_FALSE; 4261 tid = Adapter->watchdog_tid; 4262 Adapter->watchdog_tid = 0; 4263 4264 mutex_exit(&Adapter->watchdog_lock); 4265 4266 if (tid != 0) 4267 (void) untimeout(tid); 4268 } 4269 4270 static void 4271 stop_link_timer(struct e1000g *Adapter) 4272 { 4273 timeout_id_t tid; 4274 4275 /* Disable the link timer */ 4276 mutex_enter(&Adapter->link_lock); 4277 4278 tid = Adapter->link_tid; 4279 Adapter->link_tid = 0; 4280 4281 mutex_exit(&Adapter->link_lock); 4282 4283 if (tid != 0) 4284 (void) untimeout(tid); 4285 } 4286 4287 static void 4288 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4289 { 4290 timeout_id_t tid; 4291 4292 /* Disable the tx timer for 82547 chipset */ 4293 mutex_enter(&tx_ring->tx_lock); 4294 4295 tx_ring->timer_enable_82547 = B_FALSE; 4296 tid = tx_ring->timer_id_82547; 4297 tx_ring->timer_id_82547 = 0; 4298 4299 mutex_exit(&tx_ring->tx_lock); 4300 4301 if (tid != 0) 4302 (void) untimeout(tid); 4303 } 4304 4305 void 4306 e1000g_clear_interrupt(struct e1000g *Adapter) 4307 { 4308 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4309 0xffffffff & ~E1000_IMS_RXSEQ); 4310 } 4311 4312 void 4313 e1000g_mask_interrupt(struct e1000g *Adapter) 4314 { 4315 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4316 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4317 4318 if (Adapter->tx_intr_enable) 4319 e1000g_mask_tx_interrupt(Adapter); 4320 } 4321 4322 /* 4323 * This routine is called by e1000g_quiesce(), therefore must not block. 4324 */ 4325 void 4326 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4327 { 4328 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4329 } 4330 4331 void 4332 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4333 { 4334 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4335 } 4336 4337 void 4338 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4339 { 4340 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4341 } 4342 4343 static void 4344 e1000g_smartspeed(struct e1000g *Adapter) 4345 { 4346 struct e1000_hw *hw = &Adapter->shared; 4347 uint16_t phy_status; 4348 uint16_t phy_ctrl; 4349 4350 /* 4351 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4352 * advertising 1000Full, we don't even use the workaround 4353 */ 4354 if ((hw->phy.type != e1000_phy_igp) || 4355 !hw->mac.autoneg || 4356 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4357 return; 4358 4359 /* 4360 * True if this is the first call of this function or after every 4361 * 30 seconds of not having link 4362 */ 4363 if (Adapter->smartspeed == 0) { 4364 /* 4365 * If Master/Slave config fault is asserted twice, we 4366 * assume back-to-back 4367 */ 4368 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4369 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4370 return; 4371 4372 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4373 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4374 return; 4375 /* 4376 * We're assuming back-2-back because our status register 4377 * insists! there's a fault in the master/slave 4378 * relationship that was "negotiated" 4379 */ 4380 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4381 /* 4382 * Is the phy configured for manual configuration of 4383 * master/slave? 4384 */ 4385 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4386 /* 4387 * Yes. Then disable manual configuration (enable 4388 * auto configuration) of master/slave 4389 */ 4390 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4391 (void) e1000_write_phy_reg(hw, 4392 PHY_1000T_CTRL, phy_ctrl); 4393 /* 4394 * Effectively starting the clock 4395 */ 4396 Adapter->smartspeed++; 4397 /* 4398 * Restart autonegotiation 4399 */ 4400 if (!e1000_phy_setup_autoneg(hw) && 4401 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4402 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4403 MII_CR_RESTART_AUTO_NEG); 4404 (void) e1000_write_phy_reg(hw, 4405 PHY_CONTROL, phy_ctrl); 4406 } 4407 } 4408 return; 4409 /* 4410 * Has 6 seconds transpired still without link? Remember, 4411 * you should reset the smartspeed counter once you obtain 4412 * link 4413 */ 4414 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4415 /* 4416 * Yes. Remember, we did at the start determine that 4417 * there's a master/slave configuration fault, so we're 4418 * still assuming there's someone on the other end, but we 4419 * just haven't yet been able to talk to it. We then 4420 * re-enable auto configuration of master/slave to see if 4421 * we're running 2/3 pair cables. 4422 */ 4423 /* 4424 * If still no link, perhaps using 2/3 pair cable 4425 */ 4426 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4427 phy_ctrl |= CR_1000T_MS_ENABLE; 4428 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4429 /* 4430 * Restart autoneg with phy enabled for manual 4431 * configuration of master/slave 4432 */ 4433 if (!e1000_phy_setup_autoneg(hw) && 4434 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4435 phy_ctrl |= 4436 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4437 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4438 } 4439 /* 4440 * Hopefully, there are no more faults and we've obtained 4441 * link as a result. 4442 */ 4443 } 4444 /* 4445 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4446 * seconds) 4447 */ 4448 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4449 Adapter->smartspeed = 0; 4450 } 4451 4452 static boolean_t 4453 is_valid_mac_addr(uint8_t *mac_addr) 4454 { 4455 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4456 const uint8_t addr_test2[6] = 4457 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4458 4459 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4460 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4461 return (B_FALSE); 4462 4463 return (B_TRUE); 4464 } 4465 4466 /* 4467 * e1000g_stall_check - check for tx stall 4468 * 4469 * This function checks if the adapter is stalled (in transmit). 4470 * 4471 * It is called each time the watchdog timeout is invoked. 4472 * If the transmit descriptor reclaim continuously fails, 4473 * the watchdog value will increment by 1. If the watchdog 4474 * value exceeds the threshold, the adapter is assumed to 4475 * have stalled and need to be reset. 4476 */ 4477 static boolean_t 4478 e1000g_stall_check(struct e1000g *Adapter) 4479 { 4480 e1000g_tx_ring_t *tx_ring; 4481 4482 tx_ring = Adapter->tx_ring; 4483 4484 if (Adapter->link_state != LINK_STATE_UP) 4485 return (B_FALSE); 4486 4487 (void) e1000g_recycle(tx_ring); 4488 4489 if (Adapter->stall_flag) { 4490 Adapter->stall_flag = B_FALSE; 4491 Adapter->reset_flag = B_TRUE; 4492 return (B_TRUE); 4493 } 4494 4495 return (B_FALSE); 4496 } 4497 4498 #ifdef E1000G_DEBUG 4499 static enum ioc_reply 4500 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4501 { 4502 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4503 e1000g_peekpoke_t *ppd; 4504 uint64_t mem_va; 4505 uint64_t maxoff; 4506 boolean_t peek; 4507 4508 switch (iocp->ioc_cmd) { 4509 4510 case E1000G_IOC_REG_PEEK: 4511 peek = B_TRUE; 4512 break; 4513 4514 case E1000G_IOC_REG_POKE: 4515 peek = B_FALSE; 4516 break; 4517 4518 deault: 4519 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4520 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4521 iocp->ioc_cmd); 4522 return (IOC_INVAL); 4523 } 4524 4525 /* 4526 * Validate format of ioctl 4527 */ 4528 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4529 return (IOC_INVAL); 4530 if (mp->b_cont == NULL) 4531 return (IOC_INVAL); 4532 4533 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4534 4535 /* 4536 * Validate request parameters 4537 */ 4538 switch (ppd->pp_acc_space) { 4539 4540 default: 4541 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4542 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4543 ppd->pp_acc_space); 4544 return (IOC_INVAL); 4545 4546 case E1000G_PP_SPACE_REG: 4547 /* 4548 * Memory-mapped I/O space 4549 */ 4550 ASSERT(ppd->pp_acc_size == 4); 4551 if (ppd->pp_acc_size != 4) 4552 return (IOC_INVAL); 4553 4554 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4555 return (IOC_INVAL); 4556 4557 mem_va = 0; 4558 maxoff = 0x10000; 4559 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4560 break; 4561 4562 case E1000G_PP_SPACE_E1000G: 4563 /* 4564 * E1000g data structure! 4565 */ 4566 mem_va = (uintptr_t)e1000gp; 4567 maxoff = sizeof (struct e1000g); 4568 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4569 break; 4570 4571 } 4572 4573 if (ppd->pp_acc_offset >= maxoff) 4574 return (IOC_INVAL); 4575 4576 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4577 return (IOC_INVAL); 4578 4579 /* 4580 * All OK - go! 4581 */ 4582 ppd->pp_acc_offset += mem_va; 4583 (*ppfn)(e1000gp, ppd); 4584 return (peek ? IOC_REPLY : IOC_ACK); 4585 } 4586 4587 static void 4588 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4589 { 4590 ddi_acc_handle_t handle; 4591 uint32_t *regaddr; 4592 4593 handle = e1000gp->osdep.reg_handle; 4594 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4595 (uintptr_t)ppd->pp_acc_offset); 4596 4597 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4598 } 4599 4600 static void 4601 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4602 { 4603 ddi_acc_handle_t handle; 4604 uint32_t *regaddr; 4605 uint32_t value; 4606 4607 handle = e1000gp->osdep.reg_handle; 4608 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4609 (uintptr_t)ppd->pp_acc_offset); 4610 value = (uint32_t)ppd->pp_acc_data; 4611 4612 ddi_put32(handle, regaddr, value); 4613 } 4614 4615 static void 4616 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4617 { 4618 uint64_t value; 4619 void *vaddr; 4620 4621 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4622 4623 switch (ppd->pp_acc_size) { 4624 case 1: 4625 value = *(uint8_t *)vaddr; 4626 break; 4627 4628 case 2: 4629 value = *(uint16_t *)vaddr; 4630 break; 4631 4632 case 4: 4633 value = *(uint32_t *)vaddr; 4634 break; 4635 4636 case 8: 4637 value = *(uint64_t *)vaddr; 4638 break; 4639 } 4640 4641 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4642 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4643 (void *)e1000gp, (void *)ppd, value, vaddr); 4644 4645 ppd->pp_acc_data = value; 4646 } 4647 4648 static void 4649 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4650 { 4651 uint64_t value; 4652 void *vaddr; 4653 4654 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4655 value = ppd->pp_acc_data; 4656 4657 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4658 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4659 (void *)e1000gp, (void *)ppd, value, vaddr); 4660 4661 switch (ppd->pp_acc_size) { 4662 case 1: 4663 *(uint8_t *)vaddr = (uint8_t)value; 4664 break; 4665 4666 case 2: 4667 *(uint16_t *)vaddr = (uint16_t)value; 4668 break; 4669 4670 case 4: 4671 *(uint32_t *)vaddr = (uint32_t)value; 4672 break; 4673 4674 case 8: 4675 *(uint64_t *)vaddr = (uint64_t)value; 4676 break; 4677 } 4678 } 4679 #endif 4680 4681 /* 4682 * Loopback Support 4683 */ 4684 static lb_property_t lb_normal = 4685 { normal, "normal", E1000G_LB_NONE }; 4686 static lb_property_t lb_external1000 = 4687 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4688 static lb_property_t lb_external100 = 4689 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4690 static lb_property_t lb_external10 = 4691 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4692 static lb_property_t lb_phy = 4693 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4694 4695 static enum ioc_reply 4696 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4697 { 4698 lb_info_sz_t *lbsp; 4699 lb_property_t *lbpp; 4700 struct e1000_hw *hw; 4701 uint32_t *lbmp; 4702 uint32_t size; 4703 uint32_t value; 4704 4705 hw = &Adapter->shared; 4706 4707 if (mp->b_cont == NULL) 4708 return (IOC_INVAL); 4709 4710 if (!e1000g_check_loopback_support(hw)) { 4711 e1000g_log(NULL, CE_WARN, 4712 "Loopback is not supported on e1000g%d", Adapter->instance); 4713 return (IOC_INVAL); 4714 } 4715 4716 switch (iocp->ioc_cmd) { 4717 default: 4718 return (IOC_INVAL); 4719 4720 case LB_GET_INFO_SIZE: 4721 size = sizeof (lb_info_sz_t); 4722 if (iocp->ioc_count != size) 4723 return (IOC_INVAL); 4724 4725 rw_enter(&Adapter->chip_lock, RW_WRITER); 4726 e1000g_get_phy_state(Adapter); 4727 4728 /* 4729 * Workaround for hardware faults. In order to get a stable 4730 * state of phy, we will wait for a specific interval and 4731 * try again. The time delay is an experiential value based 4732 * on our testing. 4733 */ 4734 msec_delay(100); 4735 e1000g_get_phy_state(Adapter); 4736 rw_exit(&Adapter->chip_lock); 4737 4738 value = sizeof (lb_normal); 4739 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4740 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4741 (hw->phy.media_type == e1000_media_type_fiber) || 4742 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4743 value += sizeof (lb_phy); 4744 switch (hw->mac.type) { 4745 case e1000_82571: 4746 case e1000_82572: 4747 case e1000_80003es2lan: 4748 value += sizeof (lb_external1000); 4749 break; 4750 } 4751 } 4752 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4753 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4754 value += sizeof (lb_external100); 4755 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4756 value += sizeof (lb_external10); 4757 4758 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 4759 *lbsp = value; 4760 break; 4761 4762 case LB_GET_INFO: 4763 value = sizeof (lb_normal); 4764 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4765 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4766 (hw->phy.media_type == e1000_media_type_fiber) || 4767 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4768 value += sizeof (lb_phy); 4769 switch (hw->mac.type) { 4770 case e1000_82571: 4771 case e1000_82572: 4772 case e1000_80003es2lan: 4773 value += sizeof (lb_external1000); 4774 break; 4775 } 4776 } 4777 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4778 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4779 value += sizeof (lb_external100); 4780 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4781 value += sizeof (lb_external10); 4782 4783 size = value; 4784 if (iocp->ioc_count != size) 4785 return (IOC_INVAL); 4786 4787 value = 0; 4788 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 4789 lbpp[value++] = lb_normal; 4790 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4791 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4792 (hw->phy.media_type == e1000_media_type_fiber) || 4793 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4794 lbpp[value++] = lb_phy; 4795 switch (hw->mac.type) { 4796 case e1000_82571: 4797 case e1000_82572: 4798 case e1000_80003es2lan: 4799 lbpp[value++] = lb_external1000; 4800 break; 4801 } 4802 } 4803 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4804 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4805 lbpp[value++] = lb_external100; 4806 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4807 lbpp[value++] = lb_external10; 4808 break; 4809 4810 case LB_GET_MODE: 4811 size = sizeof (uint32_t); 4812 if (iocp->ioc_count != size) 4813 return (IOC_INVAL); 4814 4815 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4816 *lbmp = Adapter->loopback_mode; 4817 break; 4818 4819 case LB_SET_MODE: 4820 size = 0; 4821 if (iocp->ioc_count != sizeof (uint32_t)) 4822 return (IOC_INVAL); 4823 4824 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4825 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4826 return (IOC_INVAL); 4827 break; 4828 } 4829 4830 iocp->ioc_count = size; 4831 iocp->ioc_error = 0; 4832 4833 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4834 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4835 return (IOC_INVAL); 4836 } 4837 4838 return (IOC_REPLY); 4839 } 4840 4841 static boolean_t 4842 e1000g_check_loopback_support(struct e1000_hw *hw) 4843 { 4844 switch (hw->mac.type) { 4845 case e1000_82540: 4846 case e1000_82545: 4847 case e1000_82545_rev_3: 4848 case e1000_82546: 4849 case e1000_82546_rev_3: 4850 case e1000_82541: 4851 case e1000_82541_rev_2: 4852 case e1000_82547: 4853 case e1000_82547_rev_2: 4854 case e1000_82571: 4855 case e1000_82572: 4856 case e1000_82573: 4857 case e1000_82574: 4858 case e1000_80003es2lan: 4859 case e1000_ich9lan: 4860 case e1000_ich10lan: 4861 return (B_TRUE); 4862 } 4863 return (B_FALSE); 4864 } 4865 4866 static boolean_t 4867 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 4868 { 4869 struct e1000_hw *hw; 4870 int i, times; 4871 boolean_t link_up; 4872 4873 if (mode == Adapter->loopback_mode) 4874 return (B_TRUE); 4875 4876 hw = &Adapter->shared; 4877 times = 0; 4878 4879 Adapter->loopback_mode = mode; 4880 4881 if (mode == E1000G_LB_NONE) { 4882 /* Reset the chip */ 4883 hw->phy.autoneg_wait_to_complete = B_TRUE; 4884 (void) e1000g_reset_adapter(Adapter); 4885 hw->phy.autoneg_wait_to_complete = B_FALSE; 4886 return (B_TRUE); 4887 } 4888 4889 again: 4890 4891 rw_enter(&Adapter->chip_lock, RW_WRITER); 4892 4893 switch (mode) { 4894 default: 4895 rw_exit(&Adapter->chip_lock); 4896 return (B_FALSE); 4897 4898 case E1000G_LB_EXTERNAL_1000: 4899 e1000g_set_external_loopback_1000(Adapter); 4900 break; 4901 4902 case E1000G_LB_EXTERNAL_100: 4903 e1000g_set_external_loopback_100(Adapter); 4904 break; 4905 4906 case E1000G_LB_EXTERNAL_10: 4907 e1000g_set_external_loopback_10(Adapter); 4908 break; 4909 4910 case E1000G_LB_INTERNAL_PHY: 4911 e1000g_set_internal_loopback(Adapter); 4912 break; 4913 } 4914 4915 times++; 4916 4917 rw_exit(&Adapter->chip_lock); 4918 4919 /* Wait for link up */ 4920 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 4921 msec_delay(100); 4922 4923 rw_enter(&Adapter->chip_lock, RW_WRITER); 4924 4925 link_up = e1000g_link_up(Adapter); 4926 4927 rw_exit(&Adapter->chip_lock); 4928 4929 if (!link_up) { 4930 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4931 "Failed to get the link up"); 4932 if (times < 2) { 4933 /* Reset the link */ 4934 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4935 "Reset the link ..."); 4936 (void) e1000g_reset_adapter(Adapter); 4937 goto again; 4938 } 4939 } 4940 4941 return (B_TRUE); 4942 } 4943 4944 /* 4945 * The following loopback settings are from Intel's technical 4946 * document - "How To Loopback". All the register settings and 4947 * time delay values are directly inherited from the document 4948 * without more explanations available. 4949 */ 4950 static void 4951 e1000g_set_internal_loopback(struct e1000g *Adapter) 4952 { 4953 struct e1000_hw *hw; 4954 uint32_t ctrl; 4955 uint32_t status; 4956 uint16_t phy_ctrl; 4957 uint16_t phy_reg; 4958 uint32_t txcw; 4959 4960 hw = &Adapter->shared; 4961 4962 /* Disable Smart Power Down */ 4963 phy_spd_state(hw, B_FALSE); 4964 4965 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4966 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 4967 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 4968 4969 switch (hw->mac.type) { 4970 case e1000_82540: 4971 case e1000_82545: 4972 case e1000_82545_rev_3: 4973 case e1000_82546: 4974 case e1000_82546_rev_3: 4975 case e1000_82573: 4976 /* Auto-MDI/MDIX off */ 4977 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 4978 /* Reset PHY to update Auto-MDI/MDIX */ 4979 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4980 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 4981 /* Reset PHY to auto-neg off and force 1000 */ 4982 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4983 phy_ctrl | MII_CR_RESET); 4984 /* 4985 * Disable PHY receiver for 82540/545/546 and 82573 Family. 4986 * See comments above e1000g_set_internal_loopback() for the 4987 * background. 4988 */ 4989 (void) e1000_write_phy_reg(hw, 29, 0x001F); 4990 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 4991 (void) e1000_write_phy_reg(hw, 29, 0x001A); 4992 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 4993 break; 4994 case e1000_80003es2lan: 4995 /* Force Link Up */ 4996 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 4997 0x1CC); 4998 /* Sets PCS loopback at 1Gbs */ 4999 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 5000 0x1046); 5001 break; 5002 } 5003 5004 /* 5005 * The following registers should be set for e1000_phy_bm phy type. 5006 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy. 5007 * For others, we do not need to set these registers. 5008 */ 5009 if (hw->phy.type == e1000_phy_bm) { 5010 /* Set Default MAC Interface speed to 1GB */ 5011 (void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg); 5012 phy_reg &= ~0x0007; 5013 phy_reg |= 0x006; 5014 (void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg); 5015 /* Assert SW reset for above settings to take effect */ 5016 (void) e1000_phy_commit(hw); 5017 msec_delay(1); 5018 /* Force Full Duplex */ 5019 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5020 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5021 phy_reg | 0x000C); 5022 /* Set Link Up (in force link) */ 5023 (void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg); 5024 (void) e1000_write_phy_reg(hw, PHY_REG(776, 16), 5025 phy_reg | 0x0040); 5026 /* Force Link */ 5027 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5028 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5029 phy_reg | 0x0040); 5030 /* Set Early Link Enable */ 5031 (void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg); 5032 (void) e1000_write_phy_reg(hw, PHY_REG(769, 20), 5033 phy_reg | 0x0400); 5034 } 5035 5036 /* Set loopback */ 5037 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 5038 5039 msec_delay(250); 5040 5041 /* Now set up the MAC to the same speed/duplex as the PHY. */ 5042 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5043 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5044 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5045 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5046 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 5047 E1000_CTRL_FD); /* Force Duplex to FULL */ 5048 5049 switch (hw->mac.type) { 5050 case e1000_82540: 5051 case e1000_82545: 5052 case e1000_82545_rev_3: 5053 case e1000_82546: 5054 case e1000_82546_rev_3: 5055 /* 5056 * For some serdes we'll need to commit the writes now 5057 * so that the status is updated on link 5058 */ 5059 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 5060 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5061 msec_delay(100); 5062 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5063 } 5064 5065 if (hw->phy.media_type == e1000_media_type_copper) { 5066 /* Invert Loss of Signal */ 5067 ctrl |= E1000_CTRL_ILOS; 5068 } else { 5069 /* Set ILOS on fiber nic if half duplex is detected */ 5070 status = E1000_READ_REG(hw, E1000_STATUS); 5071 if ((status & E1000_STATUS_FD) == 0) 5072 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5073 } 5074 break; 5075 5076 case e1000_82571: 5077 case e1000_82572: 5078 /* 5079 * The fiber/SerDes versions of this adapter do not contain an 5080 * accessible PHY. Therefore, loopback beyond MAC must be done 5081 * using SerDes analog loopback. 5082 */ 5083 if (hw->phy.media_type != e1000_media_type_copper) { 5084 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5085 txcw = E1000_READ_REG(hw, E1000_TXCW); 5086 txcw &= ~((uint32_t)1 << 31); 5087 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5088 5089 /* 5090 * Write 0x410 to Serdes Control register 5091 * to enable Serdes analog loopback 5092 */ 5093 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5094 msec_delay(10); 5095 } 5096 5097 status = E1000_READ_REG(hw, E1000_STATUS); 5098 /* Set ILOS on fiber nic if half duplex is detected */ 5099 if ((hw->phy.media_type == e1000_media_type_fiber) && 5100 ((status & E1000_STATUS_FD) == 0 || 5101 (status & E1000_STATUS_LU) == 0)) 5102 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5103 else if (hw->phy.media_type == e1000_media_type_internal_serdes) 5104 ctrl |= E1000_CTRL_SLU; 5105 break; 5106 5107 case e1000_82573: 5108 ctrl |= E1000_CTRL_ILOS; 5109 break; 5110 case e1000_ich9lan: 5111 case e1000_ich10lan: 5112 ctrl |= E1000_CTRL_SLU; 5113 break; 5114 } 5115 if (hw->phy.type == e1000_phy_bm) 5116 ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS; 5117 5118 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5119 } 5120 5121 static void 5122 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 5123 { 5124 struct e1000_hw *hw; 5125 uint32_t rctl; 5126 uint32_t ctrl_ext; 5127 uint32_t ctrl; 5128 uint32_t status; 5129 uint32_t txcw; 5130 uint16_t phydata; 5131 5132 hw = &Adapter->shared; 5133 5134 /* Disable Smart Power Down */ 5135 phy_spd_state(hw, B_FALSE); 5136 5137 switch (hw->mac.type) { 5138 case e1000_82571: 5139 case e1000_82572: 5140 switch (hw->phy.media_type) { 5141 case e1000_media_type_copper: 5142 /* Force link up (Must be done before the PHY writes) */ 5143 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5144 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 5145 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5146 5147 rctl = E1000_READ_REG(hw, E1000_RCTL); 5148 rctl |= (E1000_RCTL_EN | 5149 E1000_RCTL_SBP | 5150 E1000_RCTL_UPE | 5151 E1000_RCTL_MPE | 5152 E1000_RCTL_LPE | 5153 E1000_RCTL_BAM); /* 0x803E */ 5154 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 5155 5156 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5157 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 5158 E1000_CTRL_EXT_SDP6_DATA | 5159 E1000_CTRL_EXT_SDP7_DATA | 5160 E1000_CTRL_EXT_SDP4_DIR | 5161 E1000_CTRL_EXT_SDP6_DIR | 5162 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 5163 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5164 5165 /* 5166 * This sequence tunes the PHY's SDP and no customer 5167 * settable values. For background, see comments above 5168 * e1000g_set_internal_loopback(). 5169 */ 5170 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 5171 msec_delay(10); 5172 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 5173 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 5174 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 5175 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 5176 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 5177 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 5178 5179 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 5180 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 5181 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 5182 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 5183 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 5184 5185 msec_delay(50); 5186 break; 5187 case e1000_media_type_fiber: 5188 case e1000_media_type_internal_serdes: 5189 status = E1000_READ_REG(hw, E1000_STATUS); 5190 if (((status & E1000_STATUS_LU) == 0) || 5191 (hw->phy.media_type == 5192 e1000_media_type_internal_serdes)) { 5193 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5194 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5195 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5196 } 5197 5198 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5199 txcw = E1000_READ_REG(hw, E1000_TXCW); 5200 txcw &= ~((uint32_t)1 << 31); 5201 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5202 5203 /* 5204 * Write 0x410 to Serdes Control register 5205 * to enable Serdes analog loopback 5206 */ 5207 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5208 msec_delay(10); 5209 break; 5210 default: 5211 break; 5212 } 5213 break; 5214 case e1000_82574: 5215 case e1000_80003es2lan: 5216 case e1000_ich9lan: 5217 case e1000_ich10lan: 5218 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 5219 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 5220 phydata | (1 << 5)); 5221 Adapter->param_adv_autoneg = 1; 5222 Adapter->param_adv_1000fdx = 1; 5223 (void) e1000g_reset_link(Adapter); 5224 break; 5225 } 5226 } 5227 5228 static void 5229 e1000g_set_external_loopback_100(struct e1000g *Adapter) 5230 { 5231 struct e1000_hw *hw; 5232 uint32_t ctrl; 5233 uint16_t phy_ctrl; 5234 5235 hw = &Adapter->shared; 5236 5237 /* Disable Smart Power Down */ 5238 phy_spd_state(hw, B_FALSE); 5239 5240 phy_ctrl = (MII_CR_FULL_DUPLEX | 5241 MII_CR_SPEED_100); 5242 5243 /* Force 100/FD, reset PHY */ 5244 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5245 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 5246 msec_delay(10); 5247 5248 /* Force 100/FD */ 5249 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5250 phy_ctrl); /* 0x2100 */ 5251 msec_delay(10); 5252 5253 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5254 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5255 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5256 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5257 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5258 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5259 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 5260 E1000_CTRL_FD); /* Force Duplex to FULL */ 5261 5262 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5263 } 5264 5265 static void 5266 e1000g_set_external_loopback_10(struct e1000g *Adapter) 5267 { 5268 struct e1000_hw *hw; 5269 uint32_t ctrl; 5270 uint16_t phy_ctrl; 5271 5272 hw = &Adapter->shared; 5273 5274 /* Disable Smart Power Down */ 5275 phy_spd_state(hw, B_FALSE); 5276 5277 phy_ctrl = (MII_CR_FULL_DUPLEX | 5278 MII_CR_SPEED_10); 5279 5280 /* Force 10/FD, reset PHY */ 5281 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5282 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 5283 msec_delay(10); 5284 5285 /* Force 10/FD */ 5286 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5287 phy_ctrl); /* 0x0100 */ 5288 msec_delay(10); 5289 5290 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5291 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5292 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5293 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5294 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5295 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5296 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 5297 E1000_CTRL_FD); /* Force Duplex to FULL */ 5298 5299 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5300 } 5301 5302 #ifdef __sparc 5303 static boolean_t 5304 e1000g_find_mac_address(struct e1000g *Adapter) 5305 { 5306 struct e1000_hw *hw = &Adapter->shared; 5307 uchar_t *bytes; 5308 struct ether_addr sysaddr; 5309 uint_t nelts; 5310 int err; 5311 boolean_t found = B_FALSE; 5312 5313 /* 5314 * The "vendor's factory-set address" may already have 5315 * been extracted from the chip, but if the property 5316 * "local-mac-address" is set we use that instead. 5317 * 5318 * We check whether it looks like an array of 6 5319 * bytes (which it should, if OBP set it). If we can't 5320 * make sense of it this way, we'll ignore it. 5321 */ 5322 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5323 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 5324 if (err == DDI_PROP_SUCCESS) { 5325 if (nelts == ETHERADDRL) { 5326 while (nelts--) 5327 hw->mac.addr[nelts] = bytes[nelts]; 5328 found = B_TRUE; 5329 } 5330 ddi_prop_free(bytes); 5331 } 5332 5333 /* 5334 * Look up the OBP property "local-mac-address?". If the user has set 5335 * 'local-mac-address? = false', use "the system address" instead. 5336 */ 5337 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5338 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5339 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5340 if (localetheraddr(NULL, &sysaddr) != 0) { 5341 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5342 found = B_TRUE; 5343 } 5344 } 5345 ddi_prop_free(bytes); 5346 } 5347 5348 /* 5349 * Finally(!), if there's a valid "mac-address" property (created 5350 * if we netbooted from this interface), we must use this instead 5351 * of any of the above to ensure that the NFS/install server doesn't 5352 * get confused by the address changing as Solaris takes over! 5353 */ 5354 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5355 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5356 if (err == DDI_PROP_SUCCESS) { 5357 if (nelts == ETHERADDRL) { 5358 while (nelts--) 5359 hw->mac.addr[nelts] = bytes[nelts]; 5360 found = B_TRUE; 5361 } 5362 ddi_prop_free(bytes); 5363 } 5364 5365 if (found) { 5366 bcopy(hw->mac.addr, hw->mac.perm_addr, 5367 ETHERADDRL); 5368 } 5369 5370 return (found); 5371 } 5372 #endif 5373 5374 static int 5375 e1000g_add_intrs(struct e1000g *Adapter) 5376 { 5377 dev_info_t *devinfo; 5378 int intr_types; 5379 int rc; 5380 5381 devinfo = Adapter->dip; 5382 5383 /* Get supported interrupt types */ 5384 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5385 5386 if (rc != DDI_SUCCESS) { 5387 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5388 "Get supported interrupt types failed: %d\n", rc); 5389 return (DDI_FAILURE); 5390 } 5391 5392 /* 5393 * Based on Intel Technical Advisory document (TA-160), there are some 5394 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5395 * that it supports MSI, but in fact has problems. 5396 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5397 * PCI/PCI-X NICs. 5398 */ 5399 if (Adapter->shared.mac.type < e1000_82571) 5400 Adapter->msi_enable = B_FALSE; 5401 5402 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5403 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5404 5405 if (rc != DDI_SUCCESS) { 5406 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5407 "Add MSI failed, trying Legacy interrupts\n"); 5408 } else { 5409 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5410 } 5411 } 5412 5413 if ((Adapter->intr_type == 0) && 5414 (intr_types & DDI_INTR_TYPE_FIXED)) { 5415 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5416 5417 if (rc != DDI_SUCCESS) { 5418 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5419 "Add Legacy interrupts failed\n"); 5420 return (DDI_FAILURE); 5421 } 5422 5423 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5424 } 5425 5426 if (Adapter->intr_type == 0) { 5427 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5428 "No interrupts registered\n"); 5429 return (DDI_FAILURE); 5430 } 5431 5432 return (DDI_SUCCESS); 5433 } 5434 5435 /* 5436 * e1000g_intr_add() handles MSI/Legacy interrupts 5437 */ 5438 static int 5439 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5440 { 5441 dev_info_t *devinfo; 5442 int count, avail, actual; 5443 int x, y, rc, inum = 0; 5444 int flag; 5445 ddi_intr_handler_t *intr_handler; 5446 5447 devinfo = Adapter->dip; 5448 5449 /* get number of interrupts */ 5450 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5451 if ((rc != DDI_SUCCESS) || (count == 0)) { 5452 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5453 "Get interrupt number failed. Return: %d, count: %d\n", 5454 rc, count); 5455 return (DDI_FAILURE); 5456 } 5457 5458 /* get number of available interrupts */ 5459 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5460 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5461 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5462 "Get interrupt available number failed. " 5463 "Return: %d, available: %d\n", rc, avail); 5464 return (DDI_FAILURE); 5465 } 5466 5467 if (avail < count) { 5468 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5469 "Interrupts count: %d, available: %d\n", 5470 count, avail); 5471 } 5472 5473 /* Allocate an array of interrupt handles */ 5474 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5475 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5476 5477 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5478 flag = DDI_INTR_ALLOC_NORMAL; 5479 5480 /* call ddi_intr_alloc() */ 5481 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5482 count, &actual, flag); 5483 5484 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5485 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5486 "Allocate interrupts failed: %d\n", rc); 5487 5488 kmem_free(Adapter->htable, Adapter->intr_size); 5489 return (DDI_FAILURE); 5490 } 5491 5492 if (actual < count) { 5493 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5494 "Interrupts requested: %d, received: %d\n", 5495 count, actual); 5496 } 5497 5498 Adapter->intr_cnt = actual; 5499 5500 /* Get priority for first msi, assume remaining are all the same */ 5501 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5502 5503 if (rc != DDI_SUCCESS) { 5504 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5505 "Get interrupt priority failed: %d\n", rc); 5506 5507 /* Free already allocated intr */ 5508 for (y = 0; y < actual; y++) 5509 (void) ddi_intr_free(Adapter->htable[y]); 5510 5511 kmem_free(Adapter->htable, Adapter->intr_size); 5512 return (DDI_FAILURE); 5513 } 5514 5515 /* 5516 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5517 * use the interrupt service routine e1000g_intr_pciexpress() 5518 * to avoid interrupt stealing when sharing interrupt with other 5519 * devices. 5520 */ 5521 if (Adapter->shared.mac.type < e1000_82571) 5522 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5523 else 5524 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5525 5526 /* Call ddi_intr_add_handler() */ 5527 for (x = 0; x < actual; x++) { 5528 rc = ddi_intr_add_handler(Adapter->htable[x], 5529 intr_handler, (caddr_t)Adapter, NULL); 5530 5531 if (rc != DDI_SUCCESS) { 5532 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5533 "Add interrupt handler failed: %d\n", rc); 5534 5535 /* Remove already added handler */ 5536 for (y = 0; y < x; y++) 5537 (void) ddi_intr_remove_handler( 5538 Adapter->htable[y]); 5539 5540 /* Free already allocated intr */ 5541 for (y = 0; y < actual; y++) 5542 (void) ddi_intr_free(Adapter->htable[y]); 5543 5544 kmem_free(Adapter->htable, Adapter->intr_size); 5545 return (DDI_FAILURE); 5546 } 5547 } 5548 5549 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5550 5551 if (rc != DDI_SUCCESS) { 5552 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5553 "Get interrupt cap failed: %d\n", rc); 5554 5555 /* Free already allocated intr */ 5556 for (y = 0; y < actual; y++) { 5557 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5558 (void) ddi_intr_free(Adapter->htable[y]); 5559 } 5560 5561 kmem_free(Adapter->htable, Adapter->intr_size); 5562 return (DDI_FAILURE); 5563 } 5564 5565 return (DDI_SUCCESS); 5566 } 5567 5568 static int 5569 e1000g_rem_intrs(struct e1000g *Adapter) 5570 { 5571 int x; 5572 int rc; 5573 5574 for (x = 0; x < Adapter->intr_cnt; x++) { 5575 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5576 if (rc != DDI_SUCCESS) { 5577 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5578 "Remove intr handler failed: %d\n", rc); 5579 return (DDI_FAILURE); 5580 } 5581 5582 rc = ddi_intr_free(Adapter->htable[x]); 5583 if (rc != DDI_SUCCESS) { 5584 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5585 "Free intr failed: %d\n", rc); 5586 return (DDI_FAILURE); 5587 } 5588 } 5589 5590 kmem_free(Adapter->htable, Adapter->intr_size); 5591 5592 return (DDI_SUCCESS); 5593 } 5594 5595 static int 5596 e1000g_enable_intrs(struct e1000g *Adapter) 5597 { 5598 int x; 5599 int rc; 5600 5601 /* Enable interrupts */ 5602 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5603 /* Call ddi_intr_block_enable() for MSI */ 5604 rc = ddi_intr_block_enable(Adapter->htable, 5605 Adapter->intr_cnt); 5606 if (rc != DDI_SUCCESS) { 5607 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5608 "Enable block intr failed: %d\n", rc); 5609 return (DDI_FAILURE); 5610 } 5611 } else { 5612 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5613 for (x = 0; x < Adapter->intr_cnt; x++) { 5614 rc = ddi_intr_enable(Adapter->htable[x]); 5615 if (rc != DDI_SUCCESS) { 5616 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5617 "Enable intr failed: %d\n", rc); 5618 return (DDI_FAILURE); 5619 } 5620 } 5621 } 5622 5623 return (DDI_SUCCESS); 5624 } 5625 5626 static int 5627 e1000g_disable_intrs(struct e1000g *Adapter) 5628 { 5629 int x; 5630 int rc; 5631 5632 /* Disable all interrupts */ 5633 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5634 rc = ddi_intr_block_disable(Adapter->htable, 5635 Adapter->intr_cnt); 5636 if (rc != DDI_SUCCESS) { 5637 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5638 "Disable block intr failed: %d\n", rc); 5639 return (DDI_FAILURE); 5640 } 5641 } else { 5642 for (x = 0; x < Adapter->intr_cnt; x++) { 5643 rc = ddi_intr_disable(Adapter->htable[x]); 5644 if (rc != DDI_SUCCESS) { 5645 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5646 "Disable intr failed: %d\n", rc); 5647 return (DDI_FAILURE); 5648 } 5649 } 5650 } 5651 5652 return (DDI_SUCCESS); 5653 } 5654 5655 /* 5656 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5657 */ 5658 static void 5659 e1000g_get_phy_state(struct e1000g *Adapter) 5660 { 5661 struct e1000_hw *hw = &Adapter->shared; 5662 5663 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5664 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5665 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 5666 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 5667 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 5668 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 5669 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5670 &Adapter->phy_1000t_status); 5671 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 5672 5673 Adapter->param_autoneg_cap = 5674 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5675 Adapter->param_pause_cap = 5676 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5677 Adapter->param_asym_pause_cap = 5678 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5679 Adapter->param_1000fdx_cap = 5680 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5681 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5682 Adapter->param_1000hdx_cap = 5683 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5684 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5685 Adapter->param_100t4_cap = 5686 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5687 Adapter->param_100fdx_cap = 5688 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5689 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5690 Adapter->param_100hdx_cap = 5691 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5692 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5693 Adapter->param_10fdx_cap = 5694 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5695 Adapter->param_10hdx_cap = 5696 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5697 5698 Adapter->param_adv_autoneg = hw->mac.autoneg; 5699 Adapter->param_adv_pause = 5700 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5701 Adapter->param_adv_asym_pause = 5702 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5703 Adapter->param_adv_1000hdx = 5704 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5705 Adapter->param_adv_100t4 = 5706 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5707 if (Adapter->param_adv_autoneg == 1) { 5708 Adapter->param_adv_1000fdx = 5709 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5710 Adapter->param_adv_100fdx = 5711 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5712 Adapter->param_adv_100hdx = 5713 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5714 Adapter->param_adv_10fdx = 5715 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5716 Adapter->param_adv_10hdx = 5717 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5718 } 5719 5720 Adapter->param_lp_autoneg = 5721 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5722 Adapter->param_lp_pause = 5723 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5724 Adapter->param_lp_asym_pause = 5725 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5726 Adapter->param_lp_1000fdx = 5727 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5728 Adapter->param_lp_1000hdx = 5729 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5730 Adapter->param_lp_100t4 = 5731 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5732 Adapter->param_lp_100fdx = 5733 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5734 Adapter->param_lp_100hdx = 5735 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5736 Adapter->param_lp_10fdx = 5737 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5738 Adapter->param_lp_10hdx = 5739 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5740 } 5741 5742 /* 5743 * FMA support 5744 */ 5745 5746 int 5747 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5748 { 5749 ddi_fm_error_t de; 5750 5751 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5752 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5753 return (de.fme_status); 5754 } 5755 5756 int 5757 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5758 { 5759 ddi_fm_error_t de; 5760 5761 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5762 return (de.fme_status); 5763 } 5764 5765 /* 5766 * The IO fault service error handling callback function 5767 */ 5768 /* ARGSUSED2 */ 5769 static int 5770 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5771 { 5772 /* 5773 * as the driver can always deal with an error in any dma or 5774 * access handle, we can just return the fme_status value. 5775 */ 5776 pci_ereport_post(dip, err, NULL); 5777 return (err->fme_status); 5778 } 5779 5780 static void 5781 e1000g_fm_init(struct e1000g *Adapter) 5782 { 5783 ddi_iblock_cookie_t iblk; 5784 int fma_acc_flag, fma_dma_flag; 5785 5786 /* Only register with IO Fault Services if we have some capability */ 5787 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5788 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5789 fma_acc_flag = 1; 5790 } else { 5791 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5792 fma_acc_flag = 0; 5793 } 5794 5795 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5796 fma_dma_flag = 1; 5797 } else { 5798 fma_dma_flag = 0; 5799 } 5800 5801 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5802 5803 if (Adapter->fm_capabilities) { 5804 5805 /* Register capabilities with IO Fault Services */ 5806 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5807 5808 /* 5809 * Initialize pci ereport capabilities if ereport capable 5810 */ 5811 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5812 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5813 pci_ereport_setup(Adapter->dip); 5814 5815 /* 5816 * Register error callback if error callback capable 5817 */ 5818 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5819 ddi_fm_handler_register(Adapter->dip, 5820 e1000g_fm_error_cb, (void*) Adapter); 5821 } 5822 } 5823 5824 static void 5825 e1000g_fm_fini(struct e1000g *Adapter) 5826 { 5827 /* Only unregister FMA capabilities if we registered some */ 5828 if (Adapter->fm_capabilities) { 5829 5830 /* 5831 * Release any resources allocated by pci_ereport_setup() 5832 */ 5833 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5834 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5835 pci_ereport_teardown(Adapter->dip); 5836 5837 /* 5838 * Un-register error callback if error callback capable 5839 */ 5840 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5841 ddi_fm_handler_unregister(Adapter->dip); 5842 5843 /* Unregister from IO Fault Services */ 5844 ddi_fm_fini(Adapter->dip); 5845 } 5846 } 5847 5848 void 5849 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 5850 { 5851 uint64_t ena; 5852 char buf[FM_MAX_CLASS]; 5853 5854 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5855 ena = fm_ena_generate(0, FM_ENA_FMT1); 5856 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 5857 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 5858 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5859 } 5860 } 5861 5862 /* 5863 * quiesce(9E) entry point. 5864 * 5865 * This function is called when the system is single-threaded at high 5866 * PIL with preemption disabled. Therefore, this function must not be 5867 * blocked. 5868 * 5869 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 5870 * DDI_FAILURE indicates an error condition and should almost never happen. 5871 */ 5872 static int 5873 e1000g_quiesce(dev_info_t *devinfo) 5874 { 5875 struct e1000g *Adapter; 5876 5877 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 5878 5879 if (Adapter == NULL) 5880 return (DDI_FAILURE); 5881 5882 e1000g_clear_all_interrupts(Adapter); 5883 5884 (void) e1000_reset_hw(&Adapter->shared); 5885 5886 /* Setup our HW Tx Head & Tail descriptor pointers */ 5887 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 5888 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 5889 5890 /* Setup our HW Rx Head & Tail descriptor pointers */ 5891 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 5892 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 5893 5894 return (DDI_SUCCESS); 5895 } 5896 5897 static int 5898 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 5899 uint_t pr_valsize, void *pr_val) 5900 { 5901 link_flowctrl_t fl; 5902 int err = 0; 5903 5904 ASSERT(pr_valsize > 0); 5905 switch (pr_num) { 5906 case MAC_PROP_AUTONEG: 5907 *(uint8_t *)pr_val = 5908 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0); 5909 break; 5910 case MAC_PROP_FLOWCTRL: 5911 if (pr_valsize < sizeof (link_flowctrl_t)) 5912 return (EINVAL); 5913 fl = LINK_FLOWCTRL_BI; 5914 bcopy(&fl, pr_val, sizeof (fl)); 5915 break; 5916 case MAC_PROP_ADV_1000FDX_CAP: 5917 case MAC_PROP_EN_1000FDX_CAP: 5918 *(uint8_t *)pr_val = 5919 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5920 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5921 break; 5922 case MAC_PROP_ADV_1000HDX_CAP: 5923 case MAC_PROP_EN_1000HDX_CAP: 5924 *(uint8_t *)pr_val = 5925 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5926 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5927 break; 5928 case MAC_PROP_ADV_100FDX_CAP: 5929 case MAC_PROP_EN_100FDX_CAP: 5930 *(uint8_t *)pr_val = 5931 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5932 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5933 break; 5934 case MAC_PROP_ADV_100HDX_CAP: 5935 case MAC_PROP_EN_100HDX_CAP: 5936 *(uint8_t *)pr_val = 5937 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5938 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5939 break; 5940 case MAC_PROP_ADV_10FDX_CAP: 5941 case MAC_PROP_EN_10FDX_CAP: 5942 *(uint8_t *)pr_val = 5943 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5944 break; 5945 case MAC_PROP_ADV_10HDX_CAP: 5946 case MAC_PROP_EN_10HDX_CAP: 5947 *(uint8_t *)pr_val = 5948 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5949 break; 5950 default: 5951 err = ENOTSUP; 5952 break; 5953 } 5954 return (err); 5955 } 5956 5957 /* 5958 * synchronize the adv* and en* parameters. 5959 * 5960 * See comments in <sys/dld.h> for details of the *_en_* 5961 * parameters. The usage of ndd for setting adv parameters will 5962 * synchronize all the en parameters with the e1000g parameters, 5963 * implicitly disabling any settings made via dladm. 5964 */ 5965 static void 5966 e1000g_param_sync(struct e1000g *Adapter) 5967 { 5968 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 5969 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 5970 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 5971 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 5972 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 5973 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 5974 } 5975 5976 /* 5977 * e1000g_get_driver_control - tell manageability firmware that the driver 5978 * has control. 5979 */ 5980 static void 5981 e1000g_get_driver_control(struct e1000_hw *hw) 5982 { 5983 uint32_t ctrl_ext; 5984 uint32_t swsm; 5985 5986 /* tell manageability firmware the driver has taken over */ 5987 switch (hw->mac.type) { 5988 case e1000_82573: 5989 swsm = E1000_READ_REG(hw, E1000_SWSM); 5990 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 5991 break; 5992 case e1000_82571: 5993 case e1000_82572: 5994 case e1000_82574: 5995 case e1000_80003es2lan: 5996 case e1000_ich8lan: 5997 case e1000_ich9lan: 5998 case e1000_ich10lan: 5999 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6000 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6001 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 6002 break; 6003 default: 6004 /* no manageability firmware: do nothing */ 6005 break; 6006 } 6007 } 6008 6009 /* 6010 * e1000g_release_driver_control - tell manageability firmware that the driver 6011 * has released control. 6012 */ 6013 static void 6014 e1000g_release_driver_control(struct e1000_hw *hw) 6015 { 6016 uint32_t ctrl_ext; 6017 uint32_t swsm; 6018 6019 /* tell manageability firmware the driver has released control */ 6020 switch (hw->mac.type) { 6021 case e1000_82573: 6022 swsm = E1000_READ_REG(hw, E1000_SWSM); 6023 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 6024 break; 6025 case e1000_82571: 6026 case e1000_82572: 6027 case e1000_82574: 6028 case e1000_80003es2lan: 6029 case e1000_ich8lan: 6030 case e1000_ich9lan: 6031 case e1000_ich10lan: 6032 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6033 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6034 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 6035 break; 6036 default: 6037 /* no manageability firmware: do nothing */ 6038 break; 6039 } 6040 } 6041 6042 /* 6043 * Restore e1000g promiscuous mode. 6044 */ 6045 static void 6046 e1000g_restore_promisc(struct e1000g *Adapter) 6047 { 6048 if (Adapter->e1000g_promisc) { 6049 uint32_t rctl; 6050 6051 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 6052 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 6053 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 6054 } 6055 } 6056