1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet"; 48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 49 static char e1000g_version[] = "Driver Ver. 5.2.13"; 50 51 /* 52 * Proto types for DDI entry points 53 */ 54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 56 static int e1000g_quiesce(dev_info_t *); 57 58 /* 59 * init and intr routines prototype 60 */ 61 static int e1000g_resume(dev_info_t *); 62 static int e1000g_suspend(dev_info_t *); 63 static uint_t e1000g_intr_pciexpress(caddr_t); 64 static uint_t e1000g_intr(caddr_t); 65 static void e1000g_intr_work(struct e1000g *, uint32_t); 66 #pragma inline(e1000g_intr_work) 67 static uint32_t e1000g_get_itr(uint32_t, uint32_t, uint32_t); 68 #pragma inline(e1000g_get_itr) 69 static int e1000g_init(struct e1000g *); 70 static int e1000g_start(struct e1000g *, boolean_t); 71 static void e1000g_stop(struct e1000g *, boolean_t); 72 static int e1000g_m_start(void *); 73 static void e1000g_m_stop(void *); 74 static int e1000g_m_promisc(void *, boolean_t); 75 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 76 static int e1000g_m_unicst(void *, const uint8_t *); 77 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 78 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 79 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 80 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 81 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 82 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 83 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 84 uint_t, const void *); 85 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 86 uint_t, uint_t, void *); 87 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 88 const void *); 89 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 90 uint_t, void *); 91 static void e1000g_init_locks(struct e1000g *); 92 static void e1000g_destroy_locks(struct e1000g *); 93 static int e1000g_identify_hardware(struct e1000g *); 94 static int e1000g_regs_map(struct e1000g *); 95 static int e1000g_set_driver_params(struct e1000g *); 96 static void e1000g_set_bufsize(struct e1000g *); 97 static int e1000g_register_mac(struct e1000g *); 98 static boolean_t e1000g_rx_drain(struct e1000g *); 99 static boolean_t e1000g_tx_drain(struct e1000g *); 100 static void e1000g_init_unicst(struct e1000g *); 101 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 102 103 /* 104 * Local routines 105 */ 106 static boolean_t e1000g_reset_adapter(struct e1000g *); 107 static void e1000g_tx_clean(struct e1000g *); 108 static void e1000g_rx_clean(struct e1000g *); 109 static void e1000g_link_timer(void *); 110 static void e1000g_local_timer(void *); 111 static boolean_t e1000g_link_check(struct e1000g *); 112 static boolean_t e1000g_stall_check(struct e1000g *); 113 static void e1000g_smartspeed(struct e1000g *); 114 static void e1000g_get_conf(struct e1000g *); 115 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 116 static void enable_watchdog_timer(struct e1000g *); 117 static void disable_watchdog_timer(struct e1000g *); 118 static void start_watchdog_timer(struct e1000g *); 119 static void restart_watchdog_timer(struct e1000g *); 120 static void stop_watchdog_timer(struct e1000g *); 121 static void stop_link_timer(struct e1000g *); 122 static void stop_82547_timer(e1000g_tx_ring_t *); 123 static void e1000g_force_speed_duplex(struct e1000g *); 124 static void e1000g_get_max_frame_size(struct e1000g *); 125 static boolean_t is_valid_mac_addr(uint8_t *); 126 static void e1000g_unattach(dev_info_t *, struct e1000g *); 127 #ifdef E1000G_DEBUG 128 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 129 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 130 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 131 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 132 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 133 struct iocblk *, mblk_t *); 134 #endif 135 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 136 struct iocblk *, mblk_t *); 137 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 138 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 139 static void e1000g_set_internal_loopback(struct e1000g *); 140 static void e1000g_set_external_loopback_1000(struct e1000g *); 141 static void e1000g_set_external_loopback_100(struct e1000g *); 142 static void e1000g_set_external_loopback_10(struct e1000g *); 143 static int e1000g_add_intrs(struct e1000g *); 144 static int e1000g_intr_add(struct e1000g *, int); 145 static int e1000g_rem_intrs(struct e1000g *); 146 static int e1000g_enable_intrs(struct e1000g *); 147 static int e1000g_disable_intrs(struct e1000g *); 148 static boolean_t e1000g_link_up(struct e1000g *); 149 #ifdef __sparc 150 static boolean_t e1000g_find_mac_address(struct e1000g *); 151 #endif 152 static void e1000g_get_phy_state(struct e1000g *); 153 static void e1000g_free_priv_devi_node(struct e1000g *, boolean_t); 154 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 155 const void *impl_data); 156 static void e1000g_fm_init(struct e1000g *Adapter); 157 static void e1000g_fm_fini(struct e1000g *Adapter); 158 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 159 static void e1000g_param_sync(struct e1000g *); 160 static void e1000g_get_driver_control(struct e1000_hw *); 161 static void e1000g_release_driver_control(struct e1000_hw *); 162 static void e1000g_restore_promisc(struct e1000g *Adapter); 163 164 mac_priv_prop_t e1000g_priv_props[] = { 165 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 166 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 167 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 168 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 169 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 170 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 171 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 172 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 173 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 174 {"_intr_adaptive", MAC_PROP_PERM_RW}, 175 {"_tx_recycle_thresh", MAC_PROP_PERM_RW}, 176 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 177 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 178 {"_tx_recycle_num", MAC_PROP_PERM_RW} 179 }; 180 #define E1000G_MAX_PRIV_PROPS \ 181 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 182 183 184 static struct cb_ops cb_ws_ops = { 185 nulldev, /* cb_open */ 186 nulldev, /* cb_close */ 187 nodev, /* cb_strategy */ 188 nodev, /* cb_print */ 189 nodev, /* cb_dump */ 190 nodev, /* cb_read */ 191 nodev, /* cb_write */ 192 nodev, /* cb_ioctl */ 193 nodev, /* cb_devmap */ 194 nodev, /* cb_mmap */ 195 nodev, /* cb_segmap */ 196 nochpoll, /* cb_chpoll */ 197 ddi_prop_op, /* cb_prop_op */ 198 NULL, /* cb_stream */ 199 D_MP | D_HOTPLUG, /* cb_flag */ 200 CB_REV, /* cb_rev */ 201 nodev, /* cb_aread */ 202 nodev /* cb_awrite */ 203 }; 204 205 static struct dev_ops ws_ops = { 206 DEVO_REV, /* devo_rev */ 207 0, /* devo_refcnt */ 208 NULL, /* devo_getinfo */ 209 nulldev, /* devo_identify */ 210 nulldev, /* devo_probe */ 211 e1000g_attach, /* devo_attach */ 212 e1000g_detach, /* devo_detach */ 213 nodev, /* devo_reset */ 214 &cb_ws_ops, /* devo_cb_ops */ 215 NULL, /* devo_bus_ops */ 216 ddi_power, /* devo_power */ 217 e1000g_quiesce /* devo_quiesce */ 218 }; 219 220 static struct modldrv modldrv = { 221 &mod_driverops, /* Type of module. This one is a driver */ 222 ident, /* Discription string */ 223 &ws_ops, /* driver ops */ 224 }; 225 226 static struct modlinkage modlinkage = { 227 MODREV_1, &modldrv, NULL 228 }; 229 230 /* Access attributes for register mapping */ 231 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 232 DDI_DEVICE_ATTR_V0, 233 DDI_STRUCTURE_LE_ACC, 234 DDI_STRICTORDER_ACC, 235 DDI_FLAGERR_ACC 236 }; 237 238 #define E1000G_M_CALLBACK_FLAGS \ 239 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 240 241 static mac_callbacks_t e1000g_m_callbacks = { 242 E1000G_M_CALLBACK_FLAGS, 243 e1000g_m_stat, 244 e1000g_m_start, 245 e1000g_m_stop, 246 e1000g_m_promisc, 247 e1000g_m_multicst, 248 e1000g_m_unicst, 249 e1000g_m_tx, 250 NULL, 251 e1000g_m_ioctl, 252 e1000g_m_getcapab, 253 NULL, 254 NULL, 255 e1000g_m_setprop, 256 e1000g_m_getprop 257 }; 258 259 /* 260 * Global variables 261 */ 262 uint32_t e1000g_mblks_pending = 0; 263 /* 264 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 265 * Here we maintain a private dev_info list if e1000g_force_detach is 266 * enabled. If we force the driver to detach while there are still some 267 * rx buffers retained in the upper layer, we have to keep a copy of the 268 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 269 * structure will be freed after the driver is detached. However when we 270 * finally free those rx buffers released by the upper layer, we need to 271 * refer to the dev_info to free the dma buffers. So we save a copy of 272 * the dev_info for this purpose. On x86 platform, we assume this copy 273 * of dev_info is always valid, but on SPARC platform, it could be invalid 274 * after the system board level DR operation. For this reason, the global 275 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 276 */ 277 #ifdef __sparc 278 boolean_t e1000g_force_detach = B_FALSE; 279 #else 280 boolean_t e1000g_force_detach = B_TRUE; 281 #endif 282 private_devi_list_t *e1000g_private_devi_list = NULL; 283 284 /* 285 * The rwlock is defined to protect the whole processing of rx recycling 286 * and the rx packets release in detach processing to make them mutually 287 * exclusive. 288 * The rx recycling processes different rx packets in different threads, 289 * so it will be protected with RW_READER and it won't block any other rx 290 * recycling threads. 291 * While the detach processing will be protected with RW_WRITER to make 292 * it mutually exclusive with the rx recycling. 293 */ 294 krwlock_t e1000g_rx_detach_lock; 295 /* 296 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 297 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 298 * If there are many e1000g instances, the system may run out of DVMA 299 * resources during the initialization of the instances, then the flag will 300 * be changed to "USE_DMA". Because different e1000g instances are initialized 301 * in parallel, we need to use this lock to protect the flag. 302 */ 303 krwlock_t e1000g_dma_type_lock; 304 305 /* 306 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 307 * Based on the information from Intel, the 82546 chipset has some hardware 308 * problem. When one port is being reset and the other port is trying to 309 * access the eeprom, it could cause system hang or panic. To workaround this 310 * hardware problem, we use a global mutex to prevent such operations from 311 * happening simultaneously on different instances. This workaround is applied 312 * to all the devices supported by this driver. 313 */ 314 kmutex_t e1000g_nvm_lock; 315 316 /* 317 * Loadable module configuration entry points for the driver 318 */ 319 320 /* 321 * _init - module initialization 322 */ 323 int 324 _init(void) 325 { 326 int status; 327 328 mac_init_ops(&ws_ops, WSNAME); 329 status = mod_install(&modlinkage); 330 if (status != DDI_SUCCESS) 331 mac_fini_ops(&ws_ops); 332 else { 333 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 334 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 335 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 336 } 337 338 return (status); 339 } 340 341 /* 342 * _fini - module finalization 343 */ 344 int 345 _fini(void) 346 { 347 int status; 348 349 rw_enter(&e1000g_rx_detach_lock, RW_READER); 350 if (e1000g_mblks_pending != 0) { 351 rw_exit(&e1000g_rx_detach_lock); 352 return (EBUSY); 353 } 354 rw_exit(&e1000g_rx_detach_lock); 355 356 status = mod_remove(&modlinkage); 357 if (status == DDI_SUCCESS) { 358 mac_fini_ops(&ws_ops); 359 360 if (e1000g_force_detach) { 361 private_devi_list_t *devi_node; 362 363 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 364 while (e1000g_private_devi_list != NULL) { 365 devi_node = e1000g_private_devi_list; 366 e1000g_private_devi_list = 367 e1000g_private_devi_list->next; 368 369 kmem_free(devi_node->priv_dip, 370 sizeof (struct dev_info)); 371 kmem_free(devi_node, 372 sizeof (private_devi_list_t)); 373 } 374 rw_exit(&e1000g_rx_detach_lock); 375 } 376 377 rw_destroy(&e1000g_rx_detach_lock); 378 rw_destroy(&e1000g_dma_type_lock); 379 mutex_destroy(&e1000g_nvm_lock); 380 } 381 382 return (status); 383 } 384 385 /* 386 * _info - module information 387 */ 388 int 389 _info(struct modinfo *modinfop) 390 { 391 return (mod_info(&modlinkage, modinfop)); 392 } 393 394 /* 395 * e1000g_attach - driver attach 396 * 397 * This function is the device-specific initialization entry 398 * point. This entry point is required and must be written. 399 * The DDI_ATTACH command must be provided in the attach entry 400 * point. When attach() is called with cmd set to DDI_ATTACH, 401 * all normal kernel services (such as kmem_alloc(9F)) are 402 * available for use by the driver. 403 * 404 * The attach() function will be called once for each instance 405 * of the device on the system with cmd set to DDI_ATTACH. 406 * Until attach() succeeds, the only driver entry points which 407 * may be called are open(9E) and getinfo(9E). 408 */ 409 static int 410 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 411 { 412 struct e1000g *Adapter; 413 struct e1000_hw *hw; 414 struct e1000g_osdep *osdep; 415 int instance; 416 417 switch (cmd) { 418 default: 419 e1000g_log(NULL, CE_WARN, 420 "Unsupported command send to e1000g_attach... "); 421 return (DDI_FAILURE); 422 423 case DDI_RESUME: 424 return (e1000g_resume(devinfo)); 425 426 case DDI_ATTACH: 427 break; 428 } 429 430 /* 431 * get device instance number 432 */ 433 instance = ddi_get_instance(devinfo); 434 435 /* 436 * Allocate soft data structure 437 */ 438 Adapter = 439 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 440 441 Adapter->dip = devinfo; 442 Adapter->instance = instance; 443 Adapter->tx_ring->adapter = Adapter; 444 Adapter->rx_ring->adapter = Adapter; 445 446 hw = &Adapter->shared; 447 osdep = &Adapter->osdep; 448 hw->back = osdep; 449 osdep->adapter = Adapter; 450 451 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 452 453 /* 454 * Initialize for fma support 455 */ 456 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 457 0, 0x0f, 458 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 459 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 460 e1000g_fm_init(Adapter); 461 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 462 463 /* 464 * PCI Configure 465 */ 466 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 467 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 468 goto attach_fail; 469 } 470 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 471 472 /* 473 * Setup hardware 474 */ 475 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 476 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 477 goto attach_fail; 478 } 479 480 /* 481 * Map in the device registers. 482 */ 483 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 484 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 485 goto attach_fail; 486 } 487 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 488 489 /* 490 * Initialize driver parameters 491 */ 492 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 493 goto attach_fail; 494 } 495 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 496 497 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 498 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 499 goto attach_fail; 500 } 501 502 /* 503 * Initialize interrupts 504 */ 505 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 506 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 507 goto attach_fail; 508 } 509 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 510 511 /* 512 * Initialize mutex's for this device. 513 * Do this before enabling the interrupt handler and 514 * register the softint to avoid the condition where 515 * interrupt handler can try using uninitialized mutex 516 */ 517 e1000g_init_locks(Adapter); 518 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 519 520 /* 521 * Initialize Driver Counters 522 */ 523 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 524 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 525 goto attach_fail; 526 } 527 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 528 529 /* 530 * Initialize chip hardware and software structures 531 */ 532 if (e1000g_init(Adapter) != DDI_SUCCESS) { 533 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 534 goto attach_fail; 535 } 536 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 537 538 /* 539 * Register the driver to the MAC 540 */ 541 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 542 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 543 goto attach_fail; 544 } 545 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 546 547 /* 548 * Now that mutex locks are initialized, and the chip is also 549 * initialized, enable interrupts. 550 */ 551 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 552 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 553 goto attach_fail; 554 } 555 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 556 557 /* 558 * If e1000g_force_detach is enabled, in global private dip list, 559 * we will create a new entry, which maintains the priv_dip for DR 560 * supports after driver detached. 561 */ 562 if (e1000g_force_detach) { 563 private_devi_list_t *devi_node; 564 565 Adapter->priv_dip = 566 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 567 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 568 sizeof (struct dev_info)); 569 570 devi_node = 571 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 572 573 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 574 devi_node->priv_dip = Adapter->priv_dip; 575 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 576 devi_node->next = e1000g_private_devi_list; 577 e1000g_private_devi_list = devi_node; 578 rw_exit(&e1000g_rx_detach_lock); 579 } 580 581 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 582 583 return (DDI_SUCCESS); 584 585 attach_fail: 586 e1000g_unattach(devinfo, Adapter); 587 return (DDI_FAILURE); 588 } 589 590 static int 591 e1000g_register_mac(struct e1000g *Adapter) 592 { 593 struct e1000_hw *hw = &Adapter->shared; 594 mac_register_t *mac; 595 int err; 596 597 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 598 return (DDI_FAILURE); 599 600 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 601 mac->m_driver = Adapter; 602 mac->m_dip = Adapter->dip; 603 mac->m_src_addr = hw->mac.addr; 604 mac->m_callbacks = &e1000g_m_callbacks; 605 mac->m_min_sdu = 0; 606 mac->m_max_sdu = Adapter->default_mtu; 607 mac->m_margin = VLAN_TAGSZ; 608 mac->m_priv_props = e1000g_priv_props; 609 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 610 611 err = mac_register(mac, &Adapter->mh); 612 mac_free(mac); 613 614 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 615 } 616 617 static int 618 e1000g_identify_hardware(struct e1000g *Adapter) 619 { 620 struct e1000_hw *hw = &Adapter->shared; 621 struct e1000g_osdep *osdep = &Adapter->osdep; 622 623 /* Get the device id */ 624 hw->vendor_id = 625 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 626 hw->device_id = 627 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 628 hw->revision_id = 629 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 630 hw->subsystem_device_id = 631 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 632 hw->subsystem_vendor_id = 633 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 634 635 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 636 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 637 "MAC type could not be set properly."); 638 return (DDI_FAILURE); 639 } 640 641 return (DDI_SUCCESS); 642 } 643 644 static int 645 e1000g_regs_map(struct e1000g *Adapter) 646 { 647 dev_info_t *devinfo = Adapter->dip; 648 struct e1000_hw *hw = &Adapter->shared; 649 struct e1000g_osdep *osdep = &Adapter->osdep; 650 off_t mem_size; 651 652 /* Get size of adapter register memory */ 653 if (ddi_dev_regsize(devinfo, ADAPTER_REG_SET, &mem_size) != 654 DDI_SUCCESS) { 655 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 656 "ddi_dev_regsize for registers failed"); 657 return (DDI_FAILURE); 658 } 659 660 /* Map adapter register memory */ 661 if ((ddi_regs_map_setup(devinfo, ADAPTER_REG_SET, 662 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 663 &osdep->reg_handle)) != DDI_SUCCESS) { 664 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 665 "ddi_regs_map_setup for registers failed"); 666 goto regs_map_fail; 667 } 668 669 /* ICH needs to map flash memory */ 670 if (hw->mac.type == e1000_ich8lan || 671 hw->mac.type == e1000_ich9lan || 672 hw->mac.type == e1000_ich10lan) { 673 /* get flash size */ 674 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 675 &mem_size) != DDI_SUCCESS) { 676 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 677 "ddi_dev_regsize for ICH flash failed"); 678 goto regs_map_fail; 679 } 680 681 /* map flash in */ 682 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 683 (caddr_t *)&hw->flash_address, 0, 684 mem_size, &e1000g_regs_acc_attr, 685 &osdep->ich_flash_handle) != DDI_SUCCESS) { 686 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 687 "ddi_regs_map_setup for ICH flash failed"); 688 goto regs_map_fail; 689 } 690 } 691 692 return (DDI_SUCCESS); 693 694 regs_map_fail: 695 if (osdep->reg_handle != NULL) 696 ddi_regs_map_free(&osdep->reg_handle); 697 698 return (DDI_FAILURE); 699 } 700 701 static int 702 e1000g_set_driver_params(struct e1000g *Adapter) 703 { 704 struct e1000_hw *hw; 705 uint32_t mem_bar, io_bar, bar64; 706 707 hw = &Adapter->shared; 708 709 /* Set MAC type and initialize hardware functions */ 710 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 711 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 712 "Could not setup hardware functions"); 713 return (DDI_FAILURE); 714 } 715 716 /* Get bus information */ 717 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 718 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 719 "Could not get bus information"); 720 return (DDI_FAILURE); 721 } 722 723 /* get mem_base addr */ 724 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 725 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 726 727 /* get io_base addr */ 728 if (hw->mac.type >= e1000_82544) { 729 if (bar64) { 730 /* IO BAR is different for 64 bit BAR mode */ 731 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 732 PCI_CONF_BASE4); 733 } else { 734 /* normal 32-bit BAR mode */ 735 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 736 PCI_CONF_BASE2); 737 } 738 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 739 } else { 740 /* no I/O access for adapters prior to 82544 */ 741 hw->io_base = 0x0; 742 } 743 744 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 745 746 hw->mac.autoneg_failed = B_TRUE; 747 748 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 749 hw->phy.autoneg_wait_to_complete = B_FALSE; 750 751 /* Adaptive IFS related changes */ 752 hw->mac.adaptive_ifs = B_TRUE; 753 754 /* Enable phy init script for IGP phy of 82541/82547 */ 755 if ((hw->mac.type == e1000_82547) || 756 (hw->mac.type == e1000_82541) || 757 (hw->mac.type == e1000_82547_rev_2) || 758 (hw->mac.type == e1000_82541_rev_2)) 759 e1000_init_script_state_82541(hw, B_TRUE); 760 761 /* Enable the TTL workaround for 82541/82547 */ 762 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 763 764 #ifdef __sparc 765 Adapter->strip_crc = B_TRUE; 766 #else 767 Adapter->strip_crc = B_FALSE; 768 #endif 769 770 /* Get conf file properties */ 771 e1000g_get_conf(Adapter); 772 773 /* Get speed/duplex settings in conf file */ 774 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 775 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 776 e1000g_force_speed_duplex(Adapter); 777 778 /* Get Jumbo Frames settings in conf file */ 779 e1000g_get_max_frame_size(Adapter); 780 781 /* Set Rx/Tx buffer size */ 782 e1000g_set_bufsize(Adapter); 783 784 /* Master Latency Timer */ 785 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 786 787 /* copper options */ 788 if (hw->phy.media_type == e1000_media_type_copper) { 789 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 790 hw->phy.disable_polarity_correction = B_FALSE; 791 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 792 } 793 794 /* The initial link state should be "unknown" */ 795 Adapter->link_state = LINK_STATE_UNKNOWN; 796 797 /* Initialize rx parameters */ 798 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 799 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 800 801 /* Initialize tx parameters */ 802 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 803 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 804 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 805 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 806 807 /* Initialize rx parameters */ 808 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 809 810 return (DDI_SUCCESS); 811 } 812 813 static void 814 e1000g_set_bufsize(struct e1000g *Adapter) 815 { 816 struct e1000_mac_info *mac = &Adapter->shared.mac; 817 uint64_t rx_size; 818 uint64_t tx_size; 819 820 dev_info_t *devinfo = Adapter->dip; 821 #ifdef __sparc 822 ulong_t iommu_pagesize; 823 #endif 824 /* Get the system page size */ 825 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 826 827 #ifdef __sparc 828 iommu_pagesize = dvma_pagesize(devinfo); 829 if (iommu_pagesize != 0) { 830 if (Adapter->sys_page_sz == iommu_pagesize) { 831 if (iommu_pagesize > 0x4000) 832 Adapter->sys_page_sz = 0x4000; 833 } else { 834 if (Adapter->sys_page_sz > iommu_pagesize) 835 Adapter->sys_page_sz = iommu_pagesize; 836 } 837 } 838 if (Adapter->lso_enable) { 839 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 840 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 841 } else { 842 Adapter->dvma_page_num = Adapter->max_frame_size / 843 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 844 } 845 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 846 #endif 847 848 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 849 850 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 851 if ((rx_size > FRAME_SIZE_UPTO_2K) && (rx_size <= FRAME_SIZE_UPTO_4K)) 852 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 853 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 854 (rx_size <= FRAME_SIZE_UPTO_8K)) 855 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 856 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 857 (rx_size <= FRAME_SIZE_UPTO_16K)) 858 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 859 else 860 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 861 862 tx_size = Adapter->max_frame_size; 863 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 864 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 865 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 866 (tx_size <= FRAME_SIZE_UPTO_8K)) 867 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 868 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 869 (tx_size <= FRAME_SIZE_UPTO_16K)) 870 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 871 else 872 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 873 874 /* 875 * For Wiseman adapters we have an requirement of having receive 876 * buffers aligned at 256 byte boundary. Since Livengood does not 877 * require this and forcing it for all hardwares will have 878 * performance implications, I am making it applicable only for 879 * Wiseman and for Jumbo frames enabled mode as rest of the time, 880 * it is okay to have normal frames...but it does involve a 881 * potential risk where we may loose data if buffer is not 882 * aligned...so all wiseman boards to have 256 byte aligned 883 * buffers 884 */ 885 if (mac->type < e1000_82543) 886 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 887 else 888 Adapter->rx_buf_align = 1; 889 } 890 891 /* 892 * e1000g_detach - driver detach 893 * 894 * The detach() function is the complement of the attach routine. 895 * If cmd is set to DDI_DETACH, detach() is used to remove the 896 * state associated with a given instance of a device node 897 * prior to the removal of that instance from the system. 898 * 899 * The detach() function will be called once for each instance 900 * of the device for which there has been a successful attach() 901 * once there are no longer any opens on the device. 902 * 903 * Interrupts routine are disabled, All memory allocated by this 904 * driver are freed. 905 */ 906 static int 907 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 908 { 909 struct e1000g *Adapter; 910 boolean_t rx_drain; 911 912 switch (cmd) { 913 default: 914 return (DDI_FAILURE); 915 916 case DDI_SUSPEND: 917 return (e1000g_suspend(devinfo)); 918 919 case DDI_DETACH: 920 break; 921 } 922 923 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 924 if (Adapter == NULL) 925 return (DDI_FAILURE); 926 927 if (mac_unregister(Adapter->mh) != 0) { 928 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 929 return (DDI_FAILURE); 930 } 931 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 932 933 934 if (Adapter->chip_state != E1000G_STOP) 935 e1000g_stop(Adapter, B_TRUE); 936 937 rx_drain = e1000g_rx_drain(Adapter); 938 939 /* 940 * If e1000g_force_detach is enabled, driver detach is safe. 941 * We will let e1000g_free_priv_devi_node routine determine 942 * whether we need to free the priv_dip entry for current 943 * driver instance. 944 */ 945 if (e1000g_force_detach) { 946 e1000g_free_priv_devi_node(Adapter, rx_drain); 947 } else { 948 if (!rx_drain) 949 return (DDI_FAILURE); 950 } 951 952 e1000g_unattach(devinfo, Adapter); 953 954 return (DDI_SUCCESS); 955 } 956 957 /* 958 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 959 * 960 * If free_flag is true, that indicates the upper layer is not holding 961 * the rx buffers, we could free the priv_dip entry safely. 962 * 963 * Otherwise, we have to keep this entry even after driver detached, 964 * and we also need to mark this entry with E1000G_PRIV_DEVI_DETACH flag, 965 * so that driver could free it while all of rx buffers are returned 966 * by upper layer later. 967 */ 968 static void 969 e1000g_free_priv_devi_node(struct e1000g *Adapter, boolean_t free_flag) 970 { 971 private_devi_list_t *devi_node, *devi_del; 972 973 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 974 ASSERT(e1000g_private_devi_list != NULL); 975 ASSERT(Adapter->priv_dip != NULL); 976 977 devi_node = e1000g_private_devi_list; 978 if (devi_node->priv_dip == Adapter->priv_dip) { 979 if (free_flag) { 980 e1000g_private_devi_list = 981 devi_node->next; 982 kmem_free(devi_node->priv_dip, 983 sizeof (struct dev_info)); 984 kmem_free(devi_node, 985 sizeof (private_devi_list_t)); 986 } else { 987 ASSERT(e1000g_mblks_pending != 0); 988 devi_node->flag = 989 E1000G_PRIV_DEVI_DETACH; 990 } 991 rw_exit(&e1000g_rx_detach_lock); 992 return; 993 } 994 995 devi_node = e1000g_private_devi_list; 996 while (devi_node->next != NULL) { 997 if (devi_node->next->priv_dip == Adapter->priv_dip) { 998 if (free_flag) { 999 devi_del = devi_node->next; 1000 devi_node->next = devi_del->next; 1001 kmem_free(devi_del->priv_dip, 1002 sizeof (struct dev_info)); 1003 kmem_free(devi_del, 1004 sizeof (private_devi_list_t)); 1005 } else { 1006 ASSERT(e1000g_mblks_pending != 0); 1007 devi_node->next->flag = 1008 E1000G_PRIV_DEVI_DETACH; 1009 } 1010 break; 1011 } 1012 devi_node = devi_node->next; 1013 } 1014 rw_exit(&e1000g_rx_detach_lock); 1015 } 1016 1017 static void 1018 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1019 { 1020 int result; 1021 1022 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1023 (void) e1000g_disable_intrs(Adapter); 1024 } 1025 1026 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1027 (void) mac_unregister(Adapter->mh); 1028 } 1029 1030 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1031 (void) e1000g_rem_intrs(Adapter); 1032 } 1033 1034 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1035 (void) ddi_prop_remove_all(devinfo); 1036 } 1037 1038 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1039 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1040 } 1041 1042 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1043 stop_link_timer(Adapter); 1044 1045 mutex_enter(&e1000g_nvm_lock); 1046 result = e1000_reset_hw(&Adapter->shared); 1047 mutex_exit(&e1000g_nvm_lock); 1048 1049 if (result != E1000_SUCCESS) { 1050 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1051 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1052 } 1053 } 1054 1055 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1056 if (Adapter->osdep.reg_handle != NULL) 1057 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1058 if (Adapter->osdep.ich_flash_handle != NULL) 1059 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1060 } 1061 1062 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1063 if (Adapter->osdep.cfg_handle != NULL) 1064 pci_config_teardown(&Adapter->osdep.cfg_handle); 1065 } 1066 1067 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1068 e1000g_destroy_locks(Adapter); 1069 } 1070 1071 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1072 e1000g_fm_fini(Adapter); 1073 } 1074 1075 e1000_remove_device(&Adapter->shared); 1076 1077 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1078 1079 /* 1080 * Another hotplug spec requirement, 1081 * run ddi_set_driver_private(devinfo, null); 1082 */ 1083 ddi_set_driver_private(devinfo, NULL); 1084 } 1085 1086 static void 1087 e1000g_init_locks(struct e1000g *Adapter) 1088 { 1089 e1000g_tx_ring_t *tx_ring; 1090 e1000g_rx_ring_t *rx_ring; 1091 1092 rw_init(&Adapter->chip_lock, NULL, 1093 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1094 mutex_init(&Adapter->link_lock, NULL, 1095 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1096 mutex_init(&Adapter->watchdog_lock, NULL, 1097 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1098 1099 tx_ring = Adapter->tx_ring; 1100 1101 mutex_init(&tx_ring->tx_lock, NULL, 1102 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1103 mutex_init(&tx_ring->usedlist_lock, NULL, 1104 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1105 mutex_init(&tx_ring->freelist_lock, NULL, 1106 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1107 1108 rx_ring = Adapter->rx_ring; 1109 1110 mutex_init(&rx_ring->rx_lock, NULL, 1111 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1112 mutex_init(&rx_ring->freelist_lock, NULL, 1113 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1114 } 1115 1116 static void 1117 e1000g_destroy_locks(struct e1000g *Adapter) 1118 { 1119 e1000g_tx_ring_t *tx_ring; 1120 e1000g_rx_ring_t *rx_ring; 1121 1122 tx_ring = Adapter->tx_ring; 1123 mutex_destroy(&tx_ring->tx_lock); 1124 mutex_destroy(&tx_ring->usedlist_lock); 1125 mutex_destroy(&tx_ring->freelist_lock); 1126 1127 rx_ring = Adapter->rx_ring; 1128 mutex_destroy(&rx_ring->rx_lock); 1129 mutex_destroy(&rx_ring->freelist_lock); 1130 1131 mutex_destroy(&Adapter->link_lock); 1132 mutex_destroy(&Adapter->watchdog_lock); 1133 rw_destroy(&Adapter->chip_lock); 1134 } 1135 1136 static int 1137 e1000g_resume(dev_info_t *devinfo) 1138 { 1139 struct e1000g *Adapter; 1140 1141 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1142 if (Adapter == NULL) 1143 return (DDI_FAILURE); 1144 1145 if (e1000g_start(Adapter, B_TRUE)) 1146 return (DDI_FAILURE); 1147 1148 return (DDI_SUCCESS); 1149 } 1150 1151 static int 1152 e1000g_suspend(dev_info_t *devinfo) 1153 { 1154 struct e1000g *Adapter; 1155 1156 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1157 if (Adapter == NULL) 1158 return (DDI_FAILURE); 1159 1160 e1000g_stop(Adapter, B_TRUE); 1161 1162 return (DDI_SUCCESS); 1163 } 1164 1165 static int 1166 e1000g_init(struct e1000g *Adapter) 1167 { 1168 uint32_t pba; 1169 uint32_t high_water; 1170 struct e1000_hw *hw; 1171 clock_t link_timeout; 1172 int result; 1173 1174 hw = &Adapter->shared; 1175 1176 rw_enter(&Adapter->chip_lock, RW_WRITER); 1177 1178 /* 1179 * reset to put the hardware in a known state 1180 * before we try to do anything with the eeprom 1181 */ 1182 mutex_enter(&e1000g_nvm_lock); 1183 result = e1000_reset_hw(hw); 1184 mutex_exit(&e1000g_nvm_lock); 1185 1186 if (result != E1000_SUCCESS) { 1187 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1188 goto init_fail; 1189 } 1190 1191 mutex_enter(&e1000g_nvm_lock); 1192 result = e1000_validate_nvm_checksum(hw); 1193 if (result < E1000_SUCCESS) { 1194 /* 1195 * Some PCI-E parts fail the first check due to 1196 * the link being in sleep state. Call it again, 1197 * if it fails a second time its a real issue. 1198 */ 1199 result = e1000_validate_nvm_checksum(hw); 1200 } 1201 mutex_exit(&e1000g_nvm_lock); 1202 1203 if (result < E1000_SUCCESS) { 1204 e1000g_log(Adapter, CE_WARN, 1205 "Invalid NVM checksum. Please contact " 1206 "the vendor to update the NVM."); 1207 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1208 goto init_fail; 1209 } 1210 1211 result = 0; 1212 #ifdef __sparc 1213 /* 1214 * First, we try to get the local ethernet address from OBP. If 1215 * failed, then we get it from the EEPROM of NIC card. 1216 */ 1217 result = e1000g_find_mac_address(Adapter); 1218 #endif 1219 /* Get the local ethernet address. */ 1220 if (!result) { 1221 mutex_enter(&e1000g_nvm_lock); 1222 result = e1000_read_mac_addr(hw); 1223 mutex_exit(&e1000g_nvm_lock); 1224 } 1225 1226 if (result < E1000_SUCCESS) { 1227 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1228 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1229 goto init_fail; 1230 } 1231 1232 /* check for valid mac address */ 1233 if (!is_valid_mac_addr(hw->mac.addr)) { 1234 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1235 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1236 goto init_fail; 1237 } 1238 1239 /* Set LAA state for 82571 chipset */ 1240 e1000_set_laa_state_82571(hw, B_TRUE); 1241 1242 /* Master Latency Timer implementation */ 1243 if (Adapter->master_latency_timer) { 1244 pci_config_put8(Adapter->osdep.cfg_handle, 1245 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1246 } 1247 1248 if (hw->mac.type < e1000_82547) { 1249 /* 1250 * Total FIFO is 64K 1251 */ 1252 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1253 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1254 else 1255 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1256 } else if ((hw->mac.type == e1000_82571) || 1257 (hw->mac.type == e1000_82572) || 1258 (hw->mac.type == e1000_80003es2lan)) { 1259 /* 1260 * Total FIFO is 48K 1261 */ 1262 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1263 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1264 else 1265 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1266 } else if (hw->mac.type == e1000_82573) { 1267 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1268 } else if (hw->mac.type == e1000_82574) { 1269 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1270 pba = E1000_READ_REG(hw, E1000_PBA); 1271 } else if (hw->mac.type == e1000_ich8lan) { 1272 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1273 } else if (hw->mac.type == e1000_ich9lan) { 1274 pba = E1000_PBA_10K; 1275 } else if (hw->mac.type == e1000_ich10lan) { 1276 pba = E1000_PBA_10K; 1277 } else { 1278 /* 1279 * Total FIFO is 40K 1280 */ 1281 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1282 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1283 else 1284 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1285 } 1286 E1000_WRITE_REG(hw, E1000_PBA, pba); 1287 1288 /* 1289 * These parameters set thresholds for the adapter's generation(Tx) 1290 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1291 * settings. Flow control is enabled or disabled in the configuration 1292 * file. 1293 * High-water mark is set down from the top of the rx fifo (not 1294 * sensitive to max_frame_size) and low-water is set just below 1295 * high-water mark. 1296 * The high water mark must be low enough to fit one full frame above 1297 * it in the rx FIFO. Should be the lower of: 1298 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1299 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1300 * Rx FIFO size minus one full frame. 1301 */ 1302 high_water = min(((pba << 10) * 9 / 10), 1303 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_ich9lan || 1304 hw->mac.type == e1000_ich10lan) ? 1305 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1306 ((pba << 10) - Adapter->max_frame_size))); 1307 1308 hw->fc.high_water = high_water & 0xFFF8; 1309 hw->fc.low_water = hw->fc.high_water - 8; 1310 1311 if (hw->mac.type == e1000_80003es2lan) 1312 hw->fc.pause_time = 0xFFFF; 1313 else 1314 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1315 hw->fc.send_xon = B_TRUE; 1316 1317 /* 1318 * Reset the adapter hardware the second time. 1319 */ 1320 mutex_enter(&e1000g_nvm_lock); 1321 result = e1000_reset_hw(hw); 1322 mutex_exit(&e1000g_nvm_lock); 1323 1324 if (result != E1000_SUCCESS) { 1325 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1326 goto init_fail; 1327 } 1328 1329 /* disable wakeup control by default */ 1330 if (hw->mac.type >= e1000_82544) 1331 E1000_WRITE_REG(hw, E1000_WUC, 0); 1332 1333 /* MWI setup */ 1334 e1000_pci_set_mwi(hw); 1335 1336 /* 1337 * Configure/Initialize hardware 1338 */ 1339 mutex_enter(&e1000g_nvm_lock); 1340 result = e1000_init_hw(hw); 1341 mutex_exit(&e1000g_nvm_lock); 1342 1343 if (result < E1000_SUCCESS) { 1344 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1345 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1346 goto init_fail; 1347 } 1348 1349 /* 1350 * Restore LED settings to the default from EEPROM 1351 * to meet the standard for Sun platforms. 1352 */ 1353 (void) e1000_cleanup_led(hw); 1354 1355 /* Disable Smart Power Down */ 1356 phy_spd_state(hw, B_FALSE); 1357 1358 /* Make sure driver has control */ 1359 e1000g_get_driver_control(hw); 1360 1361 /* 1362 * Initialize unicast addresses. 1363 */ 1364 e1000g_init_unicst(Adapter); 1365 1366 /* 1367 * Setup and initialize the mctable structures. After this routine 1368 * completes Multicast table will be set 1369 */ 1370 e1000g_setup_multicast(Adapter); 1371 msec_delay(5); 1372 1373 /* 1374 * Implement Adaptive IFS 1375 */ 1376 e1000_reset_adaptive(hw); 1377 1378 /* Setup Interrupt Throttling Register */ 1379 if (hw->mac.type >= e1000_82540) { 1380 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1381 } else 1382 Adapter->intr_adaptive = B_FALSE; 1383 1384 /* Start the timer for link setup */ 1385 if (hw->mac.autoneg) 1386 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1387 else 1388 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1389 1390 mutex_enter(&Adapter->link_lock); 1391 if (hw->phy.autoneg_wait_to_complete) { 1392 Adapter->link_complete = B_TRUE; 1393 } else { 1394 Adapter->link_complete = B_FALSE; 1395 Adapter->link_tid = timeout(e1000g_link_timer, 1396 (void *)Adapter, link_timeout); 1397 } 1398 mutex_exit(&Adapter->link_lock); 1399 1400 /* Enable PCI-Ex master */ 1401 if (hw->bus.type == e1000_bus_type_pci_express) { 1402 e1000_enable_pciex_master(hw); 1403 } 1404 1405 /* Save the state of the phy */ 1406 e1000g_get_phy_state(Adapter); 1407 1408 e1000g_param_sync(Adapter); 1409 1410 Adapter->init_count++; 1411 1412 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1413 goto init_fail; 1414 } 1415 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1416 goto init_fail; 1417 } 1418 1419 rw_exit(&Adapter->chip_lock); 1420 1421 return (DDI_SUCCESS); 1422 1423 init_fail: 1424 rw_exit(&Adapter->chip_lock); 1425 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1426 return (DDI_FAILURE); 1427 } 1428 1429 /* 1430 * Check if the link is up 1431 */ 1432 static boolean_t 1433 e1000g_link_up(struct e1000g *Adapter) 1434 { 1435 struct e1000_hw *hw; 1436 boolean_t link_up; 1437 1438 hw = &Adapter->shared; 1439 1440 (void) e1000_check_for_link(hw); 1441 1442 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1443 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1444 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1445 (hw->mac.serdes_has_link))) { 1446 link_up = B_TRUE; 1447 } else { 1448 link_up = B_FALSE; 1449 } 1450 1451 return (link_up); 1452 } 1453 1454 static void 1455 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1456 { 1457 struct iocblk *iocp; 1458 struct e1000g *e1000gp; 1459 enum ioc_reply status; 1460 1461 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1462 iocp->ioc_error = 0; 1463 e1000gp = (struct e1000g *)arg; 1464 1465 ASSERT(e1000gp); 1466 if (e1000gp == NULL) { 1467 miocnak(q, mp, 0, EINVAL); 1468 return; 1469 } 1470 1471 switch (iocp->ioc_cmd) { 1472 1473 case LB_GET_INFO_SIZE: 1474 case LB_GET_INFO: 1475 case LB_GET_MODE: 1476 case LB_SET_MODE: 1477 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1478 break; 1479 1480 1481 #ifdef E1000G_DEBUG 1482 case E1000G_IOC_REG_PEEK: 1483 case E1000G_IOC_REG_POKE: 1484 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1485 break; 1486 case E1000G_IOC_CHIP_RESET: 1487 e1000gp->reset_count++; 1488 if (e1000g_reset_adapter(e1000gp)) 1489 status = IOC_ACK; 1490 else 1491 status = IOC_INVAL; 1492 break; 1493 #endif 1494 default: 1495 status = IOC_INVAL; 1496 break; 1497 } 1498 1499 /* 1500 * Decide how to reply 1501 */ 1502 switch (status) { 1503 default: 1504 case IOC_INVAL: 1505 /* 1506 * Error, reply with a NAK and EINVAL or the specified error 1507 */ 1508 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1509 EINVAL : iocp->ioc_error); 1510 break; 1511 1512 case IOC_DONE: 1513 /* 1514 * OK, reply already sent 1515 */ 1516 break; 1517 1518 case IOC_ACK: 1519 /* 1520 * OK, reply with an ACK 1521 */ 1522 miocack(q, mp, 0, 0); 1523 break; 1524 1525 case IOC_REPLY: 1526 /* 1527 * OK, send prepared reply as ACK or NAK 1528 */ 1529 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1530 M_IOCACK : M_IOCNAK; 1531 qreply(q, mp); 1532 break; 1533 } 1534 } 1535 1536 static int 1537 e1000g_m_start(void *arg) 1538 { 1539 struct e1000g *Adapter = (struct e1000g *)arg; 1540 1541 return (e1000g_start(Adapter, B_TRUE)); 1542 } 1543 1544 static int 1545 e1000g_start(struct e1000g *Adapter, boolean_t global) 1546 { 1547 if (global) { 1548 /* Allocate dma resources for descriptors and buffers */ 1549 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1550 e1000g_log(Adapter, CE_WARN, 1551 "Alloc DMA resources failed"); 1552 return (ENOTACTIVE); 1553 } 1554 Adapter->rx_buffer_setup = B_FALSE; 1555 } 1556 1557 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1558 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1559 e1000g_log(Adapter, CE_WARN, 1560 "Adapter initialization failed"); 1561 if (global) 1562 e1000g_release_dma_resources(Adapter); 1563 return (ENOTACTIVE); 1564 } 1565 } 1566 1567 rw_enter(&Adapter->chip_lock, RW_WRITER); 1568 1569 /* Setup and initialize the transmit structures */ 1570 e1000g_tx_setup(Adapter); 1571 msec_delay(5); 1572 1573 /* Setup and initialize the receive structures */ 1574 e1000g_rx_setup(Adapter); 1575 msec_delay(5); 1576 1577 /* Restore the e1000g promiscuous mode */ 1578 e1000g_restore_promisc(Adapter); 1579 1580 e1000g_mask_interrupt(Adapter); 1581 1582 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1583 rw_exit(&Adapter->chip_lock); 1584 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1585 return (ENOTACTIVE); 1586 } 1587 1588 Adapter->chip_state = E1000G_START; 1589 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1590 1591 rw_exit(&Adapter->chip_lock); 1592 1593 /* Enable and start the watchdog timer */ 1594 enable_watchdog_timer(Adapter); 1595 1596 return (0); 1597 } 1598 1599 static void 1600 e1000g_m_stop(void *arg) 1601 { 1602 struct e1000g *Adapter = (struct e1000g *)arg; 1603 1604 e1000g_stop(Adapter, B_TRUE); 1605 } 1606 1607 static void 1608 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1609 { 1610 int result; 1611 1612 /* Set stop flags */ 1613 rw_enter(&Adapter->chip_lock, RW_WRITER); 1614 1615 Adapter->chip_state = E1000G_STOP; 1616 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1617 1618 rw_exit(&Adapter->chip_lock); 1619 1620 /* Drain tx sessions */ 1621 (void) e1000g_tx_drain(Adapter); 1622 1623 /* Disable and stop all the timers */ 1624 disable_watchdog_timer(Adapter); 1625 stop_link_timer(Adapter); 1626 stop_82547_timer(Adapter->tx_ring); 1627 1628 /* Stop the chip and release pending resources */ 1629 rw_enter(&Adapter->chip_lock, RW_WRITER); 1630 1631 /* Tell firmware driver is no longer in control */ 1632 e1000g_release_driver_control(&Adapter->shared); 1633 1634 e1000g_clear_all_interrupts(Adapter); 1635 1636 mutex_enter(&e1000g_nvm_lock); 1637 result = e1000_reset_hw(&Adapter->shared); 1638 mutex_exit(&e1000g_nvm_lock); 1639 1640 if (result != E1000_SUCCESS) { 1641 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1642 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1643 } 1644 1645 /* Release resources still held by the TX descriptors */ 1646 e1000g_tx_clean(Adapter); 1647 1648 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1649 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1650 1651 /* Clean the pending rx jumbo packet fragment */ 1652 e1000g_rx_clean(Adapter); 1653 1654 rw_exit(&Adapter->chip_lock); 1655 1656 if (global) 1657 e1000g_release_dma_resources(Adapter); 1658 } 1659 1660 static void 1661 e1000g_rx_clean(struct e1000g *Adapter) 1662 { 1663 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 1664 1665 if (rx_ring->rx_mblk != NULL) { 1666 freemsg(rx_ring->rx_mblk); 1667 rx_ring->rx_mblk = NULL; 1668 rx_ring->rx_mblk_tail = NULL; 1669 rx_ring->rx_mblk_len = 0; 1670 } 1671 } 1672 1673 static void 1674 e1000g_tx_clean(struct e1000g *Adapter) 1675 { 1676 e1000g_tx_ring_t *tx_ring; 1677 p_tx_sw_packet_t packet; 1678 mblk_t *mp; 1679 mblk_t *nmp; 1680 uint32_t packet_count; 1681 1682 tx_ring = Adapter->tx_ring; 1683 1684 /* 1685 * Here we don't need to protect the lists using 1686 * the usedlist_lock and freelist_lock, for they 1687 * have been protected by the chip_lock. 1688 */ 1689 mp = NULL; 1690 nmp = NULL; 1691 packet_count = 0; 1692 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1693 while (packet != NULL) { 1694 if (packet->mp != NULL) { 1695 /* Assemble the message chain */ 1696 if (mp == NULL) { 1697 mp = packet->mp; 1698 nmp = packet->mp; 1699 } else { 1700 nmp->b_next = packet->mp; 1701 nmp = packet->mp; 1702 } 1703 /* Disconnect the message from the sw packet */ 1704 packet->mp = NULL; 1705 } 1706 1707 e1000g_free_tx_swpkt(packet); 1708 packet_count++; 1709 1710 packet = (p_tx_sw_packet_t) 1711 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1712 } 1713 1714 if (mp != NULL) 1715 freemsgchain(mp); 1716 1717 if (packet_count > 0) { 1718 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1719 QUEUE_INIT_LIST(&tx_ring->used_list); 1720 1721 /* Setup TX descriptor pointers */ 1722 tx_ring->tbd_next = tx_ring->tbd_first; 1723 tx_ring->tbd_oldest = tx_ring->tbd_first; 1724 1725 /* Setup our HW Tx Head & Tail descriptor pointers */ 1726 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1727 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1728 } 1729 } 1730 1731 static boolean_t 1732 e1000g_tx_drain(struct e1000g *Adapter) 1733 { 1734 int i; 1735 boolean_t done; 1736 e1000g_tx_ring_t *tx_ring; 1737 1738 tx_ring = Adapter->tx_ring; 1739 1740 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1741 for (i = 0; i < TX_DRAIN_TIME; i++) { 1742 mutex_enter(&tx_ring->usedlist_lock); 1743 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1744 mutex_exit(&tx_ring->usedlist_lock); 1745 1746 if (done) 1747 break; 1748 1749 msec_delay(1); 1750 } 1751 1752 return (done); 1753 } 1754 1755 static boolean_t 1756 e1000g_rx_drain(struct e1000g *Adapter) 1757 { 1758 e1000g_rx_ring_t *rx_ring; 1759 p_rx_sw_packet_t packet; 1760 boolean_t done; 1761 1762 rx_ring = Adapter->rx_ring; 1763 done = B_TRUE; 1764 1765 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 1766 1767 while (rx_ring->pending_list != NULL) { 1768 packet = rx_ring->pending_list; 1769 rx_ring->pending_list = 1770 rx_ring->pending_list->next; 1771 1772 if (packet->flag == E1000G_RX_SW_STOP) { 1773 packet->flag = E1000G_RX_SW_DETACH; 1774 done = B_FALSE; 1775 } else { 1776 ASSERT(packet->flag == E1000G_RX_SW_FREE); 1777 ASSERT(packet->mp == NULL); 1778 e1000g_free_rx_sw_packet(packet); 1779 } 1780 } 1781 1782 rw_exit(&e1000g_rx_detach_lock); 1783 1784 return (done); 1785 } 1786 1787 static boolean_t 1788 e1000g_reset_adapter(struct e1000g *Adapter) 1789 { 1790 e1000g_stop(Adapter, B_FALSE); 1791 1792 if (e1000g_start(Adapter, B_FALSE)) { 1793 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1794 return (B_FALSE); 1795 } 1796 1797 return (B_TRUE); 1798 } 1799 1800 boolean_t 1801 e1000g_global_reset(struct e1000g *Adapter) 1802 { 1803 e1000g_stop(Adapter, B_TRUE); 1804 1805 Adapter->init_count = 0; 1806 1807 if (e1000g_start(Adapter, B_TRUE)) { 1808 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1809 return (B_FALSE); 1810 } 1811 1812 return (B_TRUE); 1813 } 1814 1815 /* 1816 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 1817 * 1818 * This interrupt service routine is for PCI-Express adapters. 1819 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 1820 * bit is set. 1821 */ 1822 static uint_t 1823 e1000g_intr_pciexpress(caddr_t arg) 1824 { 1825 struct e1000g *Adapter; 1826 uint32_t icr; 1827 1828 Adapter = (struct e1000g *)(uintptr_t)arg; 1829 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1830 1831 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1832 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1833 1834 if (icr & E1000_ICR_INT_ASSERTED) { 1835 /* 1836 * E1000_ICR_INT_ASSERTED bit was set: 1837 * Read(Clear) the ICR, claim this interrupt, 1838 * look for work to do. 1839 */ 1840 e1000g_intr_work(Adapter, icr); 1841 return (DDI_INTR_CLAIMED); 1842 } else { 1843 /* 1844 * E1000_ICR_INT_ASSERTED bit was not set: 1845 * Don't claim this interrupt, return immediately. 1846 */ 1847 return (DDI_INTR_UNCLAIMED); 1848 } 1849 } 1850 1851 /* 1852 * e1000g_intr - ISR for PCI/PCI-X chipsets 1853 * 1854 * This interrupt service routine is for PCI/PCI-X adapters. 1855 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 1856 * bit is set or not. 1857 */ 1858 static uint_t 1859 e1000g_intr(caddr_t arg) 1860 { 1861 struct e1000g *Adapter; 1862 uint32_t icr; 1863 1864 Adapter = (struct e1000g *)(uintptr_t)arg; 1865 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1866 1867 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1868 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1869 1870 if (icr) { 1871 /* 1872 * Any bit was set in ICR: 1873 * Read(Clear) the ICR, claim this interrupt, 1874 * look for work to do. 1875 */ 1876 e1000g_intr_work(Adapter, icr); 1877 return (DDI_INTR_CLAIMED); 1878 } else { 1879 /* 1880 * No bit was set in ICR: 1881 * Don't claim this interrupt, return immediately. 1882 */ 1883 return (DDI_INTR_UNCLAIMED); 1884 } 1885 } 1886 1887 /* 1888 * e1000g_intr_work - actual processing of ISR 1889 * 1890 * Read(clear) the ICR contents and call appropriate interrupt 1891 * processing routines. 1892 */ 1893 static void 1894 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 1895 { 1896 struct e1000_hw *hw; 1897 hw = &Adapter->shared; 1898 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 1899 uint32_t itr; 1900 1901 Adapter->rx_pkt_cnt = 0; 1902 Adapter->tx_pkt_cnt = 0; 1903 1904 rw_enter(&Adapter->chip_lock, RW_READER); 1905 /* 1906 * Here we need to check the "chip_state" flag within the chip_lock to 1907 * ensure the receive routine will not execute when the adapter is 1908 * being reset. 1909 */ 1910 if (Adapter->chip_state != E1000G_START) { 1911 rw_exit(&Adapter->chip_lock); 1912 return; 1913 } 1914 1915 if (icr & E1000_ICR_RXT0) { 1916 mblk_t *mp; 1917 1918 mutex_enter(&Adapter->rx_ring->rx_lock); 1919 mp = e1000g_receive(Adapter); 1920 mutex_exit(&Adapter->rx_ring->rx_lock); 1921 1922 rw_exit(&Adapter->chip_lock); 1923 1924 if (mp != NULL) 1925 mac_rx(Adapter->mh, Adapter->mrh, mp); 1926 } else 1927 rw_exit(&Adapter->chip_lock); 1928 1929 if (icr & E1000_ICR_TXDW) { 1930 if (!Adapter->tx_intr_enable) 1931 e1000g_clear_tx_interrupt(Adapter); 1932 1933 /* Recycle the tx descriptors */ 1934 rw_enter(&Adapter->chip_lock, RW_READER); 1935 (void) e1000g_recycle(tx_ring); 1936 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 1937 rw_exit(&Adapter->chip_lock); 1938 1939 /* Schedule the re-transmit */ 1940 if (tx_ring->resched_needed && 1941 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 1942 tx_ring->resched_needed = B_FALSE; 1943 mac_tx_update(Adapter->mh); 1944 E1000G_STAT(tx_ring->stat_reschedule); 1945 } 1946 } 1947 1948 if (Adapter->intr_adaptive) { 1949 itr = e1000g_get_itr(Adapter->rx_pkt_cnt, Adapter->tx_pkt_cnt, 1950 Adapter->intr_throttling_rate); 1951 if (itr) { 1952 E1000_WRITE_REG(hw, E1000_ITR, itr); 1953 Adapter->intr_throttling_rate = itr; 1954 } 1955 } 1956 1957 /* 1958 * The Receive Sequence errors RXSEQ and the link status change LSC 1959 * are checked to detect that the cable has been pulled out. For 1960 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1961 * are an indication that cable is not connected. 1962 */ 1963 if ((icr & E1000_ICR_RXSEQ) || 1964 (icr & E1000_ICR_LSC) || 1965 (icr & E1000_ICR_GPI_EN1)) { 1966 boolean_t link_changed; 1967 timeout_id_t tid = 0; 1968 1969 stop_watchdog_timer(Adapter); 1970 1971 rw_enter(&Adapter->chip_lock, RW_WRITER); 1972 1973 /* 1974 * Because we got a link-status-change interrupt, force 1975 * e1000_check_for_link() to look at phy 1976 */ 1977 Adapter->shared.mac.get_link_status = B_TRUE; 1978 1979 /* e1000g_link_check takes care of link status change */ 1980 link_changed = e1000g_link_check(Adapter); 1981 1982 /* Get new phy state */ 1983 e1000g_get_phy_state(Adapter); 1984 1985 /* 1986 * If the link timer has not timed out, we'll not notify 1987 * the upper layer with any link state until the link is up. 1988 */ 1989 if (link_changed && !Adapter->link_complete) { 1990 if (Adapter->link_state == LINK_STATE_UP) { 1991 mutex_enter(&Adapter->link_lock); 1992 Adapter->link_complete = B_TRUE; 1993 tid = Adapter->link_tid; 1994 Adapter->link_tid = 0; 1995 mutex_exit(&Adapter->link_lock); 1996 } else { 1997 link_changed = B_FALSE; 1998 } 1999 } 2000 rw_exit(&Adapter->chip_lock); 2001 2002 if (link_changed) { 2003 if (tid != 0) 2004 (void) untimeout(tid); 2005 2006 /* 2007 * Workaround for esb2. Data stuck in fifo on a link 2008 * down event. Stop receiver here and reset in watchdog. 2009 */ 2010 if ((Adapter->link_state == LINK_STATE_DOWN) && 2011 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2012 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2013 E1000_WRITE_REG(hw, E1000_RCTL, 2014 rctl & ~E1000_RCTL_EN); 2015 e1000g_log(Adapter, CE_WARN, 2016 "ESB2 receiver disabled"); 2017 Adapter->esb2_workaround = B_TRUE; 2018 } 2019 2020 mac_link_update(Adapter->mh, Adapter->link_state); 2021 } 2022 2023 start_watchdog_timer(Adapter); 2024 } 2025 } 2026 2027 static uint32_t 2028 e1000g_get_itr(uint32_t rx_packet, uint32_t tx_packet, uint32_t cur_itr) 2029 { 2030 uint32_t new_itr; 2031 2032 /* 2033 * Determine a propper itr according to rx/tx packet count 2034 * per interrupt, the value of itr are based on document 2035 * and testing. 2036 */ 2037 if ((rx_packet < DEFAULT_INTR_PACKET_LOW) || 2038 (tx_packet < DEFAULT_INTR_PACKET_LOW)) { 2039 new_itr = DEFAULT_INTR_THROTTLING_LOW; 2040 goto itr_done; 2041 } 2042 if ((rx_packet > DEFAULT_INTR_PACKET_HIGH) || 2043 (tx_packet > DEFAULT_INTR_PACKET_HIGH)) { 2044 new_itr = DEFAULT_INTR_THROTTLING_LOW; 2045 goto itr_done; 2046 } 2047 if (cur_itr < DEFAULT_INTR_THROTTLING_HIGH) { 2048 new_itr = cur_itr + (DEFAULT_INTR_THROTTLING_HIGH >> 2); 2049 if (new_itr > DEFAULT_INTR_THROTTLING_HIGH) 2050 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 2051 } else 2052 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 2053 2054 itr_done: 2055 if (cur_itr == new_itr) 2056 return (0); 2057 else 2058 return (new_itr); 2059 } 2060 2061 static void 2062 e1000g_init_unicst(struct e1000g *Adapter) 2063 { 2064 struct e1000_hw *hw; 2065 int slot; 2066 2067 hw = &Adapter->shared; 2068 2069 if (!Adapter->unicst_init) { 2070 /* Initialize the multiple unicast addresses */ 2071 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2072 2073 if ((hw->mac.type == e1000_82571) && 2074 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2075 Adapter->unicst_total--; 2076 2077 Adapter->unicst_avail = Adapter->unicst_total - 1; 2078 2079 /* Store the default mac address */ 2080 e1000_rar_set(hw, hw->mac.addr, 0); 2081 if ((hw->mac.type == e1000_82571) && 2082 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2083 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2084 2085 bcopy(hw->mac.addr, Adapter->unicst_addr[0].mac.addr, 2086 ETHERADDRL); 2087 Adapter->unicst_addr[0].mac.set = 1; 2088 2089 for (slot = 1; slot < Adapter->unicst_total; slot++) 2090 Adapter->unicst_addr[slot].mac.set = 0; 2091 2092 Adapter->unicst_init = B_TRUE; 2093 } else { 2094 /* Recover the default mac address */ 2095 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac.addr, 2096 ETHERADDRL); 2097 2098 /* Store the default mac address */ 2099 e1000_rar_set(hw, hw->mac.addr, 0); 2100 if ((hw->mac.type == e1000_82571) && 2101 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2102 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2103 2104 /* Re-configure the RAR registers */ 2105 for (slot = 1; slot < Adapter->unicst_total; slot++) 2106 e1000_rar_set(hw, 2107 Adapter->unicst_addr[slot].mac.addr, slot); 2108 } 2109 2110 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2111 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2112 } 2113 2114 static int 2115 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 2116 { 2117 struct e1000g *Adapter; 2118 2119 Adapter = (struct e1000g *)arg; 2120 2121 /* Store the default MAC address */ 2122 bcopy(mac_addr, Adapter->shared.mac.addr, ETHERADDRL); 2123 2124 /* Set MAC address in address slot 0, which is the default address */ 2125 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 2126 } 2127 2128 static int 2129 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2130 mac_addr_slot_t slot) 2131 { 2132 struct e1000_hw *hw; 2133 2134 hw = &Adapter->shared; 2135 2136 rw_enter(&Adapter->chip_lock, RW_WRITER); 2137 2138 /* 2139 * The first revision of Wiseman silicon (rev 2.0) has an errata 2140 * that requires the receiver to be in reset when any of the 2141 * receive address registers (RAR regs) are accessed. The first 2142 * rev of Wiseman silicon also requires MWI to be disabled when 2143 * a global reset or a receive reset is issued. So before we 2144 * initialize the RARs, we check the rev of the Wiseman controller 2145 * and work around any necessary HW errata. 2146 */ 2147 if ((hw->mac.type == e1000_82542) && 2148 (hw->revision_id == E1000_REVISION_2)) { 2149 e1000_pci_clear_mwi(hw); 2150 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2151 msec_delay(5); 2152 } 2153 2154 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 2155 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2156 2157 if (slot == 0) { 2158 if ((hw->mac.type == e1000_82571) && 2159 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2160 e1000_rar_set(hw, (uint8_t *)mac_addr, LAST_RAR_ENTRY); 2161 } 2162 2163 /* 2164 * If we are using Wiseman rev 2.0 silicon, we will have previously 2165 * put the receive in reset, and disabled MWI, to work around some 2166 * HW errata. Now we should take the receiver out of reset, and 2167 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2168 */ 2169 if ((hw->mac.type == e1000_82542) && 2170 (hw->revision_id == E1000_REVISION_2)) { 2171 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2172 msec_delay(1); 2173 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2174 e1000_pci_set_mwi(hw); 2175 e1000g_rx_setup(Adapter); 2176 } 2177 2178 rw_exit(&Adapter->chip_lock); 2179 2180 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2181 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2182 return (EIO); 2183 } 2184 2185 return (0); 2186 } 2187 2188 /* 2189 * e1000g_m_unicst_add() - will find an unused address slot, set the 2190 * address value to the one specified, reserve that slot and enable 2191 * the NIC to start filtering on the new MAC address. 2192 * Returns 0 on success. 2193 */ 2194 static int 2195 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 2196 { 2197 struct e1000g *Adapter = (struct e1000g *)arg; 2198 mac_addr_slot_t slot; 2199 int err; 2200 2201 if (mac_unicst_verify(Adapter->mh, 2202 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2203 return (EINVAL); 2204 2205 rw_enter(&Adapter->chip_lock, RW_WRITER); 2206 if (Adapter->unicst_avail == 0) { 2207 /* no slots available */ 2208 rw_exit(&Adapter->chip_lock); 2209 return (ENOSPC); 2210 } 2211 2212 /* 2213 * Primary/default address is in slot 0. The next addresses 2214 * are the multiple MAC addresses. So multiple MAC address 0 2215 * is in slot 1, 1 in slot 2, and so on. So the first multiple 2216 * MAC address resides in slot 1. 2217 */ 2218 for (slot = 1; slot < Adapter->unicst_total; slot++) { 2219 if (Adapter->unicst_addr[slot].mac.set == 0) { 2220 Adapter->unicst_addr[slot].mac.set = 1; 2221 break; 2222 } 2223 } 2224 2225 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 2226 2227 Adapter->unicst_avail--; 2228 rw_exit(&Adapter->chip_lock); 2229 2230 maddr->mma_slot = slot; 2231 2232 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 2233 rw_enter(&Adapter->chip_lock, RW_WRITER); 2234 Adapter->unicst_addr[slot].mac.set = 0; 2235 Adapter->unicst_avail++; 2236 rw_exit(&Adapter->chip_lock); 2237 } 2238 2239 return (err); 2240 } 2241 2242 /* 2243 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 2244 * call to e1000g_m_unicst_add(). The slot number that was returned in 2245 * e1000g_m_unicst_add() is passed in the call to remove the address. 2246 * Returns 0 on success. 2247 */ 2248 static int 2249 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 2250 { 2251 struct e1000g *Adapter = (struct e1000g *)arg; 2252 int err; 2253 2254 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2255 return (EINVAL); 2256 2257 rw_enter(&Adapter->chip_lock, RW_WRITER); 2258 if (Adapter->unicst_addr[slot].mac.set == 1) { 2259 Adapter->unicst_addr[slot].mac.set = 0; 2260 Adapter->unicst_avail++; 2261 rw_exit(&Adapter->chip_lock); 2262 2263 /* Copy the default address to the passed slot */ 2264 if ((err = e1000g_unicst_set(Adapter, 2265 Adapter->unicst_addr[0].mac.addr, slot)) != 0) { 2266 rw_enter(&Adapter->chip_lock, RW_WRITER); 2267 Adapter->unicst_addr[slot].mac.set = 1; 2268 Adapter->unicst_avail--; 2269 rw_exit(&Adapter->chip_lock); 2270 } 2271 return (err); 2272 } 2273 rw_exit(&Adapter->chip_lock); 2274 2275 return (EINVAL); 2276 } 2277 2278 /* 2279 * e1000g_m_unicst_modify() - modifies the value of an address that 2280 * has been added by e1000g_m_unicst_add(). The new address, address 2281 * length and the slot number that was returned in the call to add 2282 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2283 * set to 0. Returns 0 on success. 2284 */ 2285 static int 2286 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2287 { 2288 struct e1000g *Adapter = (struct e1000g *)arg; 2289 mac_addr_slot_t slot; 2290 2291 if (mac_unicst_verify(Adapter->mh, 2292 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2293 return (EINVAL); 2294 2295 slot = maddr->mma_slot; 2296 2297 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2298 return (EINVAL); 2299 2300 rw_enter(&Adapter->chip_lock, RW_WRITER); 2301 if (Adapter->unicst_addr[slot].mac.set == 1) { 2302 rw_exit(&Adapter->chip_lock); 2303 2304 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2305 } 2306 rw_exit(&Adapter->chip_lock); 2307 2308 return (EINVAL); 2309 } 2310 2311 /* 2312 * e1000g_m_unicst_get() - will get the MAC address and all other 2313 * information related to the address slot passed in mac_multi_addr_t. 2314 * mma_flags should be set to 0 in the call. 2315 * On return, mma_flags can take the following values: 2316 * 1) MMAC_SLOT_UNUSED 2317 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2318 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2319 * 4) MMAC_SLOT_USED 2320 */ 2321 static int 2322 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2323 { 2324 struct e1000g *Adapter = (struct e1000g *)arg; 2325 mac_addr_slot_t slot; 2326 2327 slot = maddr->mma_slot; 2328 2329 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2330 return (EINVAL); 2331 2332 rw_enter(&Adapter->chip_lock, RW_WRITER); 2333 if (Adapter->unicst_addr[slot].mac.set == 1) { 2334 bcopy(Adapter->unicst_addr[slot].mac.addr, 2335 maddr->mma_addr, ETHERADDRL); 2336 maddr->mma_flags = MMAC_SLOT_USED; 2337 } else { 2338 maddr->mma_flags = MMAC_SLOT_UNUSED; 2339 } 2340 rw_exit(&Adapter->chip_lock); 2341 2342 return (0); 2343 } 2344 2345 static int 2346 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2347 { 2348 struct e1000_hw *hw = &Adapter->shared; 2349 int res = 0; 2350 2351 rw_enter(&Adapter->chip_lock, RW_WRITER); 2352 2353 if ((multiaddr[0] & 01) == 0) { 2354 res = EINVAL; 2355 goto done; 2356 } 2357 2358 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2359 res = ENOENT; 2360 goto done; 2361 } 2362 2363 bcopy(multiaddr, 2364 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2365 Adapter->mcast_count++; 2366 2367 /* 2368 * Update the MC table in the hardware 2369 */ 2370 e1000g_clear_interrupt(Adapter); 2371 2372 e1000g_setup_multicast(Adapter); 2373 2374 if ((hw->mac.type == e1000_82542) && 2375 (hw->revision_id == E1000_REVISION_2)) 2376 e1000g_rx_setup(Adapter); 2377 2378 e1000g_mask_interrupt(Adapter); 2379 2380 done: 2381 rw_exit(&Adapter->chip_lock); 2382 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2383 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2384 res = EIO; 2385 } 2386 2387 return (res); 2388 } 2389 2390 static int 2391 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2392 { 2393 struct e1000_hw *hw = &Adapter->shared; 2394 unsigned i; 2395 2396 rw_enter(&Adapter->chip_lock, RW_WRITER); 2397 2398 for (i = 0; i < Adapter->mcast_count; i++) { 2399 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2400 ETHERADDRL) == 0) { 2401 for (i++; i < Adapter->mcast_count; i++) { 2402 Adapter->mcast_table[i - 1] = 2403 Adapter->mcast_table[i]; 2404 } 2405 Adapter->mcast_count--; 2406 break; 2407 } 2408 } 2409 2410 /* 2411 * Update the MC table in the hardware 2412 */ 2413 e1000g_clear_interrupt(Adapter); 2414 2415 e1000g_setup_multicast(Adapter); 2416 2417 if ((hw->mac.type == e1000_82542) && 2418 (hw->revision_id == E1000_REVISION_2)) 2419 e1000g_rx_setup(Adapter); 2420 2421 e1000g_mask_interrupt(Adapter); 2422 2423 done: 2424 rw_exit(&Adapter->chip_lock); 2425 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2426 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2427 return (EIO); 2428 } 2429 2430 return (0); 2431 } 2432 2433 /* 2434 * e1000g_setup_multicast - setup multicast data structures 2435 * 2436 * This routine initializes all of the multicast related structures. 2437 */ 2438 void 2439 e1000g_setup_multicast(struct e1000g *Adapter) 2440 { 2441 uint8_t *mc_addr_list; 2442 uint32_t mc_addr_count; 2443 uint32_t rctl; 2444 struct e1000_hw *hw; 2445 2446 hw = &Adapter->shared; 2447 2448 /* 2449 * The e1000g has the ability to do perfect filtering of 16 2450 * addresses. The driver uses one of the e1000g's 16 receive 2451 * address registers for its node/network/mac/individual address. 2452 * So, we have room for up to 15 multicast addresses in the CAM, 2453 * additional MC addresses are handled by the MTA (Multicast Table 2454 * Array) 2455 */ 2456 2457 rctl = E1000_READ_REG(hw, E1000_RCTL); 2458 2459 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2460 2461 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2462 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2463 "Adapter requested more than %d MC Addresses.\n", 2464 MAX_NUM_MULTICAST_ADDRESSES); 2465 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2466 } else { 2467 /* 2468 * Set the number of MC addresses that we are being 2469 * requested to use 2470 */ 2471 mc_addr_count = Adapter->mcast_count; 2472 } 2473 /* 2474 * The Wiseman 2.0 silicon has an errata by which the receiver will 2475 * hang while writing to the receive address registers if the receiver 2476 * is not in reset before writing to the registers. Updating the RAR 2477 * is done during the setting up of the multicast table, hence the 2478 * receiver has to be put in reset before updating the multicast table 2479 * and then taken out of reset at the end 2480 */ 2481 /* 2482 * if WMI was enabled then dis able it before issueing the global 2483 * reset to the hardware. 2484 */ 2485 /* 2486 * Only required for WISEMAN_2_0 2487 */ 2488 if ((hw->mac.type == e1000_82542) && 2489 (hw->revision_id == E1000_REVISION_2)) { 2490 e1000_pci_clear_mwi(hw); 2491 /* 2492 * The e1000g must be in reset before changing any RA 2493 * registers. Reset receive unit. The chip will remain in 2494 * the reset state until software explicitly restarts it. 2495 */ 2496 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2497 /* Allow receiver time to go in to reset */ 2498 msec_delay(5); 2499 } 2500 2501 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2502 Adapter->unicst_total, hw->mac.rar_entry_count); 2503 2504 /* 2505 * Only for Wiseman_2_0 2506 * If MWI was enabled then re-enable it after issueing (as we 2507 * disabled it up there) the receive reset command. 2508 * Wainwright does not have a receive reset command and only thing 2509 * close to it is global reset which will require tx setup also 2510 */ 2511 if ((hw->mac.type == e1000_82542) && 2512 (hw->revision_id == E1000_REVISION_2)) { 2513 /* 2514 * if WMI was enabled then reenable it after issueing the 2515 * global or receive reset to the hardware. 2516 */ 2517 2518 /* 2519 * Take receiver out of reset 2520 * clear E1000_RCTL_RST bit (and all others) 2521 */ 2522 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2523 msec_delay(5); 2524 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2525 e1000_pci_set_mwi(hw); 2526 } 2527 2528 /* 2529 * Restore original value 2530 */ 2531 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2532 } 2533 2534 int 2535 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2536 { 2537 struct e1000g *Adapter = (struct e1000g *)arg; 2538 2539 return ((add) ? multicst_add(Adapter, addr) 2540 : multicst_remove(Adapter, addr)); 2541 } 2542 2543 int 2544 e1000g_m_promisc(void *arg, boolean_t on) 2545 { 2546 struct e1000g *Adapter = (struct e1000g *)arg; 2547 uint32_t rctl; 2548 2549 rw_enter(&Adapter->chip_lock, RW_WRITER); 2550 2551 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2552 2553 if (on) 2554 rctl |= 2555 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2556 else 2557 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2558 2559 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2560 2561 Adapter->e1000g_promisc = on; 2562 2563 rw_exit(&Adapter->chip_lock); 2564 2565 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2566 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2567 return (EIO); 2568 } 2569 2570 return (0); 2571 } 2572 2573 static boolean_t 2574 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2575 { 2576 struct e1000g *Adapter = (struct e1000g *)arg; 2577 2578 switch (cap) { 2579 case MAC_CAPAB_HCKSUM: { 2580 uint32_t *txflags = cap_data; 2581 2582 if (Adapter->tx_hcksum_enable) 2583 *txflags = HCKSUM_IPHDRCKSUM | 2584 HCKSUM_INET_PARTIAL; 2585 else 2586 return (B_FALSE); 2587 break; 2588 } 2589 case MAC_CAPAB_POLL: 2590 /* 2591 * There's nothing for us to fill in, simply returning 2592 * B_TRUE stating that we support polling is sufficient. 2593 */ 2594 break; 2595 2596 case MAC_CAPAB_MULTIADDRESS: { 2597 multiaddress_capab_t *mmacp = cap_data; 2598 2599 /* 2600 * The number of MAC addresses made available by 2601 * this capability is one less than the total as 2602 * the primary address in slot 0 is counted in 2603 * the total. 2604 */ 2605 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2606 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2607 /* No multiple factory addresses, set mma_flag to 0 */ 2608 mmacp->maddr_flag = 0; 2609 mmacp->maddr_handle = Adapter; 2610 mmacp->maddr_add = e1000g_m_unicst_add; 2611 mmacp->maddr_remove = e1000g_m_unicst_remove; 2612 mmacp->maddr_modify = e1000g_m_unicst_modify; 2613 mmacp->maddr_get = e1000g_m_unicst_get; 2614 mmacp->maddr_reserve = NULL; 2615 break; 2616 } 2617 2618 case MAC_CAPAB_LSO: { 2619 mac_capab_lso_t *cap_lso = cap_data; 2620 2621 if (Adapter->lso_enable) { 2622 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2623 cap_lso->lso_basic_tcp_ipv4.lso_max = 2624 E1000_LSO_MAXLEN; 2625 } else 2626 return (B_FALSE); 2627 break; 2628 } 2629 2630 default: 2631 return (B_FALSE); 2632 } 2633 return (B_TRUE); 2634 } 2635 2636 static boolean_t 2637 e1000g_param_locked(mac_prop_id_t pr_num) 2638 { 2639 /* 2640 * All en_* parameters are locked (read-only) while 2641 * the device is in any sort of loopback mode ... 2642 */ 2643 switch (pr_num) { 2644 case MAC_PROP_EN_1000FDX_CAP: 2645 case MAC_PROP_EN_1000HDX_CAP: 2646 case MAC_PROP_EN_100FDX_CAP: 2647 case MAC_PROP_EN_100HDX_CAP: 2648 case MAC_PROP_EN_10FDX_CAP: 2649 case MAC_PROP_EN_10HDX_CAP: 2650 case MAC_PROP_AUTONEG: 2651 case MAC_PROP_FLOWCTRL: 2652 return (B_TRUE); 2653 } 2654 return (B_FALSE); 2655 } 2656 2657 /* 2658 * callback function for set/get of properties 2659 */ 2660 static int 2661 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2662 uint_t pr_valsize, const void *pr_val) 2663 { 2664 struct e1000g *Adapter = arg; 2665 struct e1000_mac_info *mac = &Adapter->shared.mac; 2666 struct e1000_phy_info *phy = &Adapter->shared.phy; 2667 struct e1000_fc_info *fc = &Adapter->shared.fc; 2668 int err = 0; 2669 link_flowctrl_t flowctrl; 2670 uint32_t cur_mtu, new_mtu; 2671 uint64_t tmp = 0; 2672 2673 rw_enter(&Adapter->chip_lock, RW_WRITER); 2674 if (Adapter->loopback_mode != E1000G_LB_NONE && 2675 e1000g_param_locked(pr_num)) { 2676 /* 2677 * All en_* parameters are locked (read-only) 2678 * while the device is in any sort of loopback mode. 2679 */ 2680 rw_exit(&Adapter->chip_lock); 2681 return (EBUSY); 2682 } 2683 2684 switch (pr_num) { 2685 case MAC_PROP_EN_1000FDX_CAP: 2686 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 2687 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 2688 goto reset; 2689 case MAC_PROP_EN_1000HDX_CAP: 2690 Adapter->param_en_1000hdx = *(uint8_t *)pr_val; 2691 Adapter->param_adv_1000hdx = *(uint8_t *)pr_val; 2692 goto reset; 2693 case MAC_PROP_EN_100FDX_CAP: 2694 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 2695 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 2696 goto reset; 2697 case MAC_PROP_EN_100HDX_CAP: 2698 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 2699 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 2700 goto reset; 2701 case MAC_PROP_EN_10FDX_CAP: 2702 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 2703 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 2704 goto reset; 2705 case MAC_PROP_EN_10HDX_CAP: 2706 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 2707 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 2708 goto reset; 2709 case MAC_PROP_AUTONEG: 2710 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 2711 goto reset; 2712 case MAC_PROP_FLOWCTRL: 2713 fc->send_xon = B_TRUE; 2714 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 2715 2716 switch (flowctrl) { 2717 default: 2718 err = EINVAL; 2719 break; 2720 case LINK_FLOWCTRL_NONE: 2721 fc->type = e1000_fc_none; 2722 break; 2723 case LINK_FLOWCTRL_RX: 2724 fc->type = e1000_fc_rx_pause; 2725 break; 2726 case LINK_FLOWCTRL_TX: 2727 fc->type = e1000_fc_tx_pause; 2728 break; 2729 case LINK_FLOWCTRL_BI: 2730 fc->type = e1000_fc_full; 2731 break; 2732 } 2733 reset: 2734 if (err == 0) { 2735 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 2736 err = EINVAL; 2737 } 2738 break; 2739 case MAC_PROP_ADV_1000FDX_CAP: 2740 case MAC_PROP_ADV_1000HDX_CAP: 2741 case MAC_PROP_ADV_100FDX_CAP: 2742 case MAC_PROP_ADV_100HDX_CAP: 2743 case MAC_PROP_ADV_10FDX_CAP: 2744 case MAC_PROP_ADV_10HDX_CAP: 2745 case MAC_PROP_STATUS: 2746 case MAC_PROP_SPEED: 2747 case MAC_PROP_DUPLEX: 2748 err = ENOTSUP; /* read-only prop. Can't set this. */ 2749 break; 2750 case MAC_PROP_MTU: 2751 cur_mtu = Adapter->default_mtu; 2752 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 2753 if (new_mtu == cur_mtu) { 2754 err = 0; 2755 break; 2756 } 2757 2758 tmp = new_mtu + sizeof (struct ether_vlan_header) + 2759 ETHERFCSL; 2760 if ((tmp < DEFAULT_FRAME_SIZE) || 2761 (tmp > MAXIMUM_FRAME_SIZE)) { 2762 err = EINVAL; 2763 break; 2764 } 2765 2766 /* ich8 does not support jumbo frames */ 2767 if ((mac->type == e1000_ich8lan) && 2768 (tmp > DEFAULT_FRAME_SIZE)) { 2769 err = EINVAL; 2770 break; 2771 } 2772 /* ich9 does not do jumbo frames on one phy type */ 2773 if ((mac->type == e1000_ich9lan) && 2774 (phy->type == e1000_phy_ife) && 2775 (tmp > DEFAULT_FRAME_SIZE)) { 2776 err = EINVAL; 2777 break; 2778 } 2779 if (Adapter->chip_state != E1000G_STOP) { 2780 err = EBUSY; 2781 break; 2782 } 2783 2784 err = mac_maxsdu_update(Adapter->mh, new_mtu); 2785 if (err == 0) { 2786 Adapter->max_frame_size = (uint32_t)tmp; 2787 Adapter->default_mtu = new_mtu; 2788 e1000g_set_bufsize(Adapter); 2789 } 2790 break; 2791 case MAC_PROP_PRIVATE: 2792 err = e1000g_set_priv_prop(Adapter, pr_name, 2793 pr_valsize, pr_val); 2794 break; 2795 default: 2796 err = ENOTSUP; 2797 break; 2798 } 2799 rw_exit(&Adapter->chip_lock); 2800 return (err); 2801 } 2802 2803 static int 2804 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2805 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 2806 { 2807 struct e1000g *Adapter = arg; 2808 struct e1000_fc_info *fc = &Adapter->shared.fc; 2809 int err = 0; 2810 link_flowctrl_t flowctrl; 2811 uint64_t tmp = 0; 2812 2813 if (pr_valsize == 0) 2814 return (EINVAL); 2815 2816 bzero(pr_val, pr_valsize); 2817 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 2818 return (e1000g_get_def_val(Adapter, pr_num, 2819 pr_valsize, pr_val)); 2820 } 2821 2822 switch (pr_num) { 2823 case MAC_PROP_DUPLEX: 2824 if (pr_valsize >= sizeof (link_duplex_t)) { 2825 bcopy(&Adapter->link_duplex, pr_val, 2826 sizeof (link_duplex_t)); 2827 } else 2828 err = EINVAL; 2829 break; 2830 case MAC_PROP_SPEED: 2831 if (pr_valsize >= sizeof (uint64_t)) { 2832 tmp = Adapter->link_speed * 1000000ull; 2833 bcopy(&tmp, pr_val, sizeof (tmp)); 2834 } else 2835 err = EINVAL; 2836 break; 2837 case MAC_PROP_AUTONEG: 2838 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 2839 break; 2840 case MAC_PROP_FLOWCTRL: 2841 if (pr_valsize >= sizeof (link_flowctrl_t)) { 2842 switch (fc->type) { 2843 case e1000_fc_none: 2844 flowctrl = LINK_FLOWCTRL_NONE; 2845 break; 2846 case e1000_fc_rx_pause: 2847 flowctrl = LINK_FLOWCTRL_RX; 2848 break; 2849 case e1000_fc_tx_pause: 2850 flowctrl = LINK_FLOWCTRL_TX; 2851 break; 2852 case e1000_fc_full: 2853 flowctrl = LINK_FLOWCTRL_BI; 2854 break; 2855 } 2856 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 2857 } else 2858 err = EINVAL; 2859 break; 2860 case MAC_PROP_ADV_1000FDX_CAP: 2861 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 2862 break; 2863 case MAC_PROP_EN_1000FDX_CAP: 2864 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 2865 break; 2866 case MAC_PROP_ADV_1000HDX_CAP: 2867 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 2868 break; 2869 case MAC_PROP_EN_1000HDX_CAP: 2870 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 2871 break; 2872 case MAC_PROP_ADV_100FDX_CAP: 2873 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 2874 break; 2875 case MAC_PROP_EN_100FDX_CAP: 2876 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 2877 break; 2878 case MAC_PROP_ADV_100HDX_CAP: 2879 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 2880 break; 2881 case MAC_PROP_EN_100HDX_CAP: 2882 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 2883 break; 2884 case MAC_PROP_ADV_10FDX_CAP: 2885 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 2886 break; 2887 case MAC_PROP_EN_10FDX_CAP: 2888 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 2889 break; 2890 case MAC_PROP_ADV_10HDX_CAP: 2891 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 2892 break; 2893 case MAC_PROP_EN_10HDX_CAP: 2894 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 2895 break; 2896 case MAC_PROP_ADV_100T4_CAP: 2897 case MAC_PROP_EN_100T4_CAP: 2898 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 2899 break; 2900 case MAC_PROP_PRIVATE: 2901 err = e1000g_get_priv_prop(Adapter, pr_name, 2902 pr_flags, pr_valsize, pr_val); 2903 break; 2904 default: 2905 err = ENOTSUP; 2906 break; 2907 } 2908 return (err); 2909 } 2910 2911 /* ARGSUSED2 */ 2912 static int 2913 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 2914 uint_t pr_valsize, const void *pr_val) 2915 { 2916 int err = 0; 2917 long result; 2918 struct e1000_hw *hw = &Adapter->shared; 2919 2920 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 2921 if (pr_val == NULL) { 2922 err = EINVAL; 2923 return (err); 2924 } 2925 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2926 if (result < MIN_TX_BCOPY_THRESHOLD || 2927 result > MAX_TX_BCOPY_THRESHOLD) 2928 err = EINVAL; 2929 else { 2930 Adapter->tx_bcopy_thresh = (uint32_t)result; 2931 } 2932 return (err); 2933 } 2934 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 2935 if (pr_val == NULL) { 2936 err = EINVAL; 2937 return (err); 2938 } 2939 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2940 if (result < 0 || result > 1) 2941 err = EINVAL; 2942 else { 2943 Adapter->tx_intr_enable = (result == 1) ? 2944 B_TRUE: B_FALSE; 2945 if (Adapter->tx_intr_enable) 2946 e1000g_mask_tx_interrupt(Adapter); 2947 else 2948 e1000g_clear_tx_interrupt(Adapter); 2949 if (e1000g_check_acc_handle( 2950 Adapter->osdep.reg_handle) != DDI_FM_OK) 2951 ddi_fm_service_impact(Adapter->dip, 2952 DDI_SERVICE_DEGRADED); 2953 } 2954 return (err); 2955 } 2956 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 2957 if (pr_val == NULL) { 2958 err = EINVAL; 2959 return (err); 2960 } 2961 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2962 if (result < MIN_TX_INTR_DELAY || 2963 result > MAX_TX_INTR_DELAY) 2964 err = EINVAL; 2965 else { 2966 Adapter->tx_intr_delay = (uint32_t)result; 2967 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 2968 if (e1000g_check_acc_handle( 2969 Adapter->osdep.reg_handle) != DDI_FM_OK) 2970 ddi_fm_service_impact(Adapter->dip, 2971 DDI_SERVICE_DEGRADED); 2972 } 2973 return (err); 2974 } 2975 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 2976 if (pr_val == NULL) { 2977 err = EINVAL; 2978 return (err); 2979 } 2980 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2981 if (result < MIN_TX_INTR_ABS_DELAY || 2982 result > MAX_TX_INTR_ABS_DELAY) 2983 err = EINVAL; 2984 else { 2985 Adapter->tx_intr_abs_delay = (uint32_t)result; 2986 E1000_WRITE_REG(hw, E1000_TADV, 2987 Adapter->tx_intr_abs_delay); 2988 if (e1000g_check_acc_handle( 2989 Adapter->osdep.reg_handle) != DDI_FM_OK) 2990 ddi_fm_service_impact(Adapter->dip, 2991 DDI_SERVICE_DEGRADED); 2992 } 2993 return (err); 2994 } 2995 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 2996 if (pr_val == NULL) { 2997 err = EINVAL; 2998 return (err); 2999 } 3000 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3001 if (result < MIN_RX_BCOPY_THRESHOLD || 3002 result > MAX_RX_BCOPY_THRESHOLD) 3003 err = EINVAL; 3004 else 3005 Adapter->rx_bcopy_thresh = (uint32_t)result; 3006 return (err); 3007 } 3008 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3009 if (pr_val == NULL) { 3010 err = EINVAL; 3011 return (err); 3012 } 3013 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3014 if (result < MIN_RX_LIMIT_ON_INTR || 3015 result > MAX_RX_LIMIT_ON_INTR) 3016 err = EINVAL; 3017 else 3018 Adapter->rx_limit_onintr = (uint32_t)result; 3019 return (err); 3020 } 3021 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3022 if (pr_val == NULL) { 3023 err = EINVAL; 3024 return (err); 3025 } 3026 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3027 if (result < MIN_RX_INTR_DELAY || 3028 result > MAX_RX_INTR_DELAY) 3029 err = EINVAL; 3030 else { 3031 Adapter->rx_intr_delay = (uint32_t)result; 3032 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3033 if (e1000g_check_acc_handle( 3034 Adapter->osdep.reg_handle) != DDI_FM_OK) 3035 ddi_fm_service_impact(Adapter->dip, 3036 DDI_SERVICE_DEGRADED); 3037 } 3038 return (err); 3039 } 3040 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3041 if (pr_val == NULL) { 3042 err = EINVAL; 3043 return (err); 3044 } 3045 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3046 if (result < MIN_RX_INTR_ABS_DELAY || 3047 result > MAX_RX_INTR_ABS_DELAY) 3048 err = EINVAL; 3049 else { 3050 Adapter->rx_intr_abs_delay = (uint32_t)result; 3051 E1000_WRITE_REG(hw, E1000_RADV, 3052 Adapter->rx_intr_abs_delay); 3053 if (e1000g_check_acc_handle( 3054 Adapter->osdep.reg_handle) != DDI_FM_OK) 3055 ddi_fm_service_impact(Adapter->dip, 3056 DDI_SERVICE_DEGRADED); 3057 } 3058 return (err); 3059 } 3060 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3061 if (pr_val == NULL) { 3062 err = EINVAL; 3063 return (err); 3064 } 3065 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3066 if (result < MIN_INTR_THROTTLING || 3067 result > MAX_INTR_THROTTLING) 3068 err = EINVAL; 3069 else { 3070 if (hw->mac.type >= e1000_82540) { 3071 Adapter->intr_throttling_rate = 3072 (uint32_t)result; 3073 E1000_WRITE_REG(hw, E1000_ITR, 3074 Adapter->intr_throttling_rate); 3075 if (e1000g_check_acc_handle( 3076 Adapter->osdep.reg_handle) != DDI_FM_OK) 3077 ddi_fm_service_impact(Adapter->dip, 3078 DDI_SERVICE_DEGRADED); 3079 } else 3080 err = EINVAL; 3081 } 3082 return (err); 3083 } 3084 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3085 if (pr_val == NULL) { 3086 err = EINVAL; 3087 return (err); 3088 } 3089 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3090 if (result < 0 || result > 1) 3091 err = EINVAL; 3092 else { 3093 if (hw->mac.type >= e1000_82540) { 3094 Adapter->intr_adaptive = (result == 1) ? 3095 B_TRUE : B_FALSE; 3096 } else { 3097 err = EINVAL; 3098 } 3099 } 3100 return (err); 3101 } 3102 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3103 if (pr_val == NULL) { 3104 err = EINVAL; 3105 return (err); 3106 } 3107 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3108 if (result < MIN_TX_RECYCLE_THRESHOLD || 3109 result > MAX_TX_RECYCLE_THRESHOLD) 3110 err = EINVAL; 3111 else 3112 Adapter->tx_recycle_thresh = (uint32_t)result; 3113 return (err); 3114 } 3115 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3116 if (pr_val == NULL) { 3117 err = EINVAL; 3118 return (err); 3119 } 3120 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3121 if (result < MIN_TX_RECYCLE_NUM || 3122 result > MAX_TX_RECYCLE_NUM) 3123 err = EINVAL; 3124 else 3125 Adapter->tx_recycle_num = (uint32_t)result; 3126 return (err); 3127 } 3128 return (ENOTSUP); 3129 } 3130 3131 static int 3132 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3133 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 3134 { 3135 int err = ENOTSUP; 3136 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3137 int value; 3138 3139 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3140 if (is_default) 3141 goto done; 3142 value = Adapter->param_adv_pause; 3143 err = 0; 3144 goto done; 3145 } 3146 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3147 if (is_default) 3148 goto done; 3149 value = Adapter->param_adv_asym_pause; 3150 err = 0; 3151 goto done; 3152 } 3153 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3154 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3155 Adapter->tx_bcopy_thresh); 3156 err = 0; 3157 goto done; 3158 } 3159 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3160 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3161 Adapter->tx_intr_enable); 3162 err = 0; 3163 goto done; 3164 } 3165 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3166 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3167 Adapter->tx_intr_delay); 3168 err = 0; 3169 goto done; 3170 } 3171 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3172 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3173 Adapter->tx_intr_abs_delay); 3174 err = 0; 3175 goto done; 3176 } 3177 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3178 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3179 Adapter->rx_bcopy_thresh); 3180 err = 0; 3181 goto done; 3182 } 3183 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3184 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3185 Adapter->rx_limit_onintr); 3186 err = 0; 3187 goto done; 3188 } 3189 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3190 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3191 Adapter->rx_intr_delay); 3192 err = 0; 3193 goto done; 3194 } 3195 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3196 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3197 Adapter->rx_intr_abs_delay); 3198 err = 0; 3199 goto done; 3200 } 3201 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3202 value = (is_default ? DEFAULT_INTR_THROTTLING : 3203 Adapter->intr_throttling_rate); 3204 err = 0; 3205 goto done; 3206 } 3207 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3208 value = (is_default ? 1 : Adapter->intr_adaptive); 3209 err = 0; 3210 goto done; 3211 } 3212 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3213 value = (is_default ? DEFAULT_TX_RECYCLE_THRESHOLD : 3214 Adapter->tx_recycle_thresh); 3215 err = 0; 3216 goto done; 3217 } 3218 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3219 value = (is_default ? DEFAULT_TX_RECYCLE_NUM : 3220 Adapter->tx_recycle_num); 3221 err = 0; 3222 goto done; 3223 } 3224 done: 3225 if (err == 0) { 3226 (void) snprintf(pr_val, pr_valsize, "%d", value); 3227 } 3228 return (err); 3229 } 3230 3231 /* 3232 * e1000g_get_conf - get configurations set in e1000g.conf 3233 * This routine gets user-configured values out of the configuration 3234 * file e1000g.conf. 3235 * 3236 * For each configurable value, there is a minimum, a maximum, and a 3237 * default. 3238 * If user does not configure a value, use the default. 3239 * If user configures below the minimum, use the minumum. 3240 * If user configures above the maximum, use the maxumum. 3241 */ 3242 static void 3243 e1000g_get_conf(struct e1000g *Adapter) 3244 { 3245 struct e1000_hw *hw = &Adapter->shared; 3246 boolean_t tbi_compatibility = B_FALSE; 3247 3248 /* 3249 * get each configurable property from e1000g.conf 3250 */ 3251 3252 /* 3253 * NumTxDescriptors 3254 */ 3255 Adapter->tx_desc_num = 3256 e1000g_get_prop(Adapter, "NumTxDescriptors", 3257 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3258 DEFAULT_NUM_TX_DESCRIPTOR); 3259 3260 /* 3261 * NumRxDescriptors 3262 */ 3263 Adapter->rx_desc_num = 3264 e1000g_get_prop(Adapter, "NumRxDescriptors", 3265 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3266 DEFAULT_NUM_RX_DESCRIPTOR); 3267 3268 /* 3269 * NumRxFreeList 3270 */ 3271 Adapter->rx_freelist_num = 3272 e1000g_get_prop(Adapter, "NumRxFreeList", 3273 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3274 DEFAULT_NUM_RX_FREELIST); 3275 3276 /* 3277 * NumTxPacketList 3278 */ 3279 Adapter->tx_freelist_num = 3280 e1000g_get_prop(Adapter, "NumTxPacketList", 3281 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3282 DEFAULT_NUM_TX_FREELIST); 3283 3284 /* 3285 * FlowControl 3286 */ 3287 hw->fc.send_xon = B_TRUE; 3288 hw->fc.type = 3289 e1000g_get_prop(Adapter, "FlowControl", 3290 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3291 /* 4 is the setting that says "let the eeprom decide" */ 3292 if (hw->fc.type == 4) 3293 hw->fc.type = e1000_fc_default; 3294 3295 /* 3296 * Max Num Receive Packets on Interrupt 3297 */ 3298 Adapter->rx_limit_onintr = 3299 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3300 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3301 DEFAULT_RX_LIMIT_ON_INTR); 3302 3303 /* 3304 * PHY master slave setting 3305 */ 3306 hw->phy.ms_type = 3307 e1000g_get_prop(Adapter, "SetMasterSlave", 3308 e1000_ms_hw_default, e1000_ms_auto, 3309 e1000_ms_hw_default); 3310 3311 /* 3312 * Parameter which controls TBI mode workaround, which is only 3313 * needed on certain switches such as Cisco 6500/Foundry 3314 */ 3315 tbi_compatibility = 3316 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3317 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3318 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3319 3320 /* 3321 * MSI Enable 3322 */ 3323 Adapter->msi_enable = 3324 e1000g_get_prop(Adapter, "MSIEnable", 3325 0, 1, DEFAULT_MSI_ENABLE); 3326 3327 /* 3328 * Interrupt Throttling Rate 3329 */ 3330 Adapter->intr_throttling_rate = 3331 e1000g_get_prop(Adapter, "intr_throttling_rate", 3332 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3333 DEFAULT_INTR_THROTTLING); 3334 3335 /* 3336 * Adaptive Interrupt Blanking Enable/Disable 3337 * It is enabled by default 3338 */ 3339 Adapter->intr_adaptive = 3340 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3341 B_TRUE : B_FALSE; 3342 3343 /* 3344 * Tx recycle threshold 3345 */ 3346 Adapter->tx_recycle_thresh = 3347 e1000g_get_prop(Adapter, "tx_recycle_thresh", 3348 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 3349 DEFAULT_TX_RECYCLE_THRESHOLD); 3350 3351 /* 3352 * Tx recycle descriptor number 3353 */ 3354 Adapter->tx_recycle_num = 3355 e1000g_get_prop(Adapter, "tx_recycle_num", 3356 MIN_TX_RECYCLE_NUM, MAX_TX_RECYCLE_NUM, 3357 DEFAULT_TX_RECYCLE_NUM); 3358 3359 /* 3360 * Hardware checksum enable/disable parameter 3361 */ 3362 Adapter->tx_hcksum_enable = 3363 e1000g_get_prop(Adapter, "tx_hcksum_enable", 3364 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3365 /* 3366 * Checksum on/off selection via global parameters. 3367 * 3368 * If the chip is flagged as not capable of (correctly) 3369 * handling checksumming, we don't enable it on either 3370 * Rx or Tx side. Otherwise, we take this chip's settings 3371 * from the patchable global defaults. 3372 * 3373 * We advertise our capabilities only if TX offload is 3374 * enabled. On receive, the stack will accept checksummed 3375 * packets anyway, even if we haven't said we can deliver 3376 * them. 3377 */ 3378 switch (hw->mac.type) { 3379 case e1000_82540: 3380 case e1000_82544: 3381 case e1000_82545: 3382 case e1000_82545_rev_3: 3383 case e1000_82546: 3384 case e1000_82546_rev_3: 3385 case e1000_82571: 3386 case e1000_82572: 3387 case e1000_82573: 3388 case e1000_80003es2lan: 3389 break; 3390 /* 3391 * For the following Intel PRO/1000 chipsets, we have not 3392 * tested the hardware checksum offload capability, so we 3393 * disable the capability for them. 3394 * e1000_82542, 3395 * e1000_82543, 3396 * e1000_82541, 3397 * e1000_82541_rev_2, 3398 * e1000_82547, 3399 * e1000_82547_rev_2, 3400 */ 3401 default: 3402 Adapter->tx_hcksum_enable = B_FALSE; 3403 } 3404 3405 /* 3406 * Large Send Offloading(LSO) Enable/Disable 3407 * If the tx hardware checksum is not enabled, LSO should be 3408 * disabled. 3409 */ 3410 Adapter->lso_enable = 3411 e1000g_get_prop(Adapter, "lso_enable", 3412 0, 1, DEFAULT_LSO_ENABLE); 3413 3414 switch (hw->mac.type) { 3415 case e1000_82546: 3416 case e1000_82546_rev_3: 3417 if (Adapter->lso_enable) 3418 Adapter->lso_premature_issue = B_TRUE; 3419 /* FALLTHRU */ 3420 case e1000_82571: 3421 case e1000_82572: 3422 case e1000_82573: 3423 case e1000_80003es2lan: 3424 break; 3425 default: 3426 Adapter->lso_enable = B_FALSE; 3427 } 3428 3429 if (!Adapter->tx_hcksum_enable) { 3430 Adapter->lso_premature_issue = B_FALSE; 3431 Adapter->lso_enable = B_FALSE; 3432 } 3433 } 3434 3435 /* 3436 * e1000g_get_prop - routine to read properties 3437 * 3438 * Get a user-configure property value out of the configuration 3439 * file e1000g.conf. 3440 * 3441 * Caller provides name of the property, a default value, a minimum 3442 * value, and a maximum value. 3443 * 3444 * Return configured value of the property, with default, minimum and 3445 * maximum properly applied. 3446 */ 3447 static int 3448 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3449 char *propname, /* name of the property */ 3450 int minval, /* minimum acceptable value */ 3451 int maxval, /* maximim acceptable value */ 3452 int defval) /* default value */ 3453 { 3454 int propval; /* value returned for requested property */ 3455 int *props; /* point to array of properties returned */ 3456 uint_t nprops; /* number of property value returned */ 3457 3458 /* 3459 * get the array of properties from the config file 3460 */ 3461 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3462 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3463 /* got some properties, test if we got enough */ 3464 if (Adapter->instance < nprops) { 3465 propval = props[Adapter->instance]; 3466 } else { 3467 /* not enough properties configured */ 3468 propval = defval; 3469 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3470 "Not Enough %s values found in e1000g.conf" 3471 " - set to %d\n", 3472 propname, propval); 3473 } 3474 3475 /* free memory allocated for properties */ 3476 ddi_prop_free(props); 3477 3478 } else { 3479 propval = defval; 3480 } 3481 3482 /* 3483 * enforce limits 3484 */ 3485 if (propval > maxval) { 3486 propval = maxval; 3487 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3488 "Too High %s value in e1000g.conf - set to %d\n", 3489 propname, propval); 3490 } 3491 3492 if (propval < minval) { 3493 propval = minval; 3494 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3495 "Too Low %s value in e1000g.conf - set to %d\n", 3496 propname, propval); 3497 } 3498 3499 return (propval); 3500 } 3501 3502 static boolean_t 3503 e1000g_link_check(struct e1000g *Adapter) 3504 { 3505 uint16_t speed, duplex, phydata; 3506 boolean_t link_changed = B_FALSE; 3507 struct e1000_hw *hw; 3508 uint32_t reg_tarc; 3509 3510 hw = &Adapter->shared; 3511 3512 if (e1000g_link_up(Adapter)) { 3513 /* 3514 * The Link is up, check whether it was marked as down earlier 3515 */ 3516 if (Adapter->link_state != LINK_STATE_UP) { 3517 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3518 Adapter->link_speed = speed; 3519 Adapter->link_duplex = duplex; 3520 Adapter->link_state = LINK_STATE_UP; 3521 link_changed = B_TRUE; 3522 3523 Adapter->tx_link_down_timeout = 0; 3524 3525 if ((hw->mac.type == e1000_82571) || 3526 (hw->mac.type == e1000_82572)) { 3527 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3528 if (speed == SPEED_1000) 3529 reg_tarc |= (1 << 21); 3530 else 3531 reg_tarc &= ~(1 << 21); 3532 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3533 } 3534 } 3535 Adapter->smartspeed = 0; 3536 } else { 3537 if (Adapter->link_state != LINK_STATE_DOWN) { 3538 Adapter->link_speed = 0; 3539 Adapter->link_duplex = 0; 3540 Adapter->link_state = LINK_STATE_DOWN; 3541 link_changed = B_TRUE; 3542 3543 /* 3544 * SmartSpeed workaround for Tabor/TanaX, When the 3545 * driver loses link disable auto master/slave 3546 * resolution. 3547 */ 3548 if (hw->phy.type == e1000_phy_igp) { 3549 (void) e1000_read_phy_reg(hw, 3550 PHY_1000T_CTRL, &phydata); 3551 phydata |= CR_1000T_MS_ENABLE; 3552 (void) e1000_write_phy_reg(hw, 3553 PHY_1000T_CTRL, phydata); 3554 } 3555 } else { 3556 e1000g_smartspeed(Adapter); 3557 } 3558 3559 if (Adapter->chip_state == E1000G_START) { 3560 if (Adapter->tx_link_down_timeout < 3561 MAX_TX_LINK_DOWN_TIMEOUT) { 3562 Adapter->tx_link_down_timeout++; 3563 } else if (Adapter->tx_link_down_timeout == 3564 MAX_TX_LINK_DOWN_TIMEOUT) { 3565 e1000g_tx_clean(Adapter); 3566 Adapter->tx_link_down_timeout++; 3567 } 3568 } 3569 } 3570 3571 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3572 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3573 3574 return (link_changed); 3575 } 3576 3577 /* 3578 * e1000g_reset_link - Using the link properties to setup the link 3579 */ 3580 int 3581 e1000g_reset_link(struct e1000g *Adapter) 3582 { 3583 struct e1000_mac_info *mac; 3584 struct e1000_phy_info *phy; 3585 boolean_t invalid; 3586 3587 mac = &Adapter->shared.mac; 3588 phy = &Adapter->shared.phy; 3589 invalid = B_FALSE; 3590 3591 if (Adapter->param_adv_autoneg == 1) { 3592 mac->autoneg = B_TRUE; 3593 phy->autoneg_advertised = 0; 3594 3595 /* 3596 * 1000hdx is not supported for autonegotiation 3597 */ 3598 if (Adapter->param_adv_1000fdx == 1) 3599 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3600 3601 if (Adapter->param_adv_100fdx == 1) 3602 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3603 3604 if (Adapter->param_adv_100hdx == 1) 3605 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3606 3607 if (Adapter->param_adv_10fdx == 1) 3608 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3609 3610 if (Adapter->param_adv_10hdx == 1) 3611 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3612 3613 if (phy->autoneg_advertised == 0) 3614 invalid = B_TRUE; 3615 } else { 3616 mac->autoneg = B_FALSE; 3617 3618 /* 3619 * 1000fdx and 1000hdx are not supported for forced link 3620 */ 3621 if (Adapter->param_adv_100fdx == 1) 3622 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3623 else if (Adapter->param_adv_100hdx == 1) 3624 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3625 else if (Adapter->param_adv_10fdx == 1) 3626 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3627 else if (Adapter->param_adv_10hdx == 1) 3628 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3629 else 3630 invalid = B_TRUE; 3631 3632 } 3633 3634 if (invalid) { 3635 e1000g_log(Adapter, CE_WARN, 3636 "Invalid link sets. Setup link to" 3637 "support autonegotiation with all link capabilities."); 3638 mac->autoneg = B_TRUE; 3639 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3640 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3641 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3642 } 3643 3644 return (e1000_setup_link(&Adapter->shared)); 3645 } 3646 3647 static void 3648 e1000g_local_timer(void *ws) 3649 { 3650 struct e1000g *Adapter = (struct e1000g *)ws; 3651 struct e1000_hw *hw; 3652 e1000g_ether_addr_t ether_addr; 3653 boolean_t link_changed; 3654 3655 hw = &Adapter->shared; 3656 3657 if (Adapter->chip_state == E1000G_ERROR) { 3658 Adapter->reset_count++; 3659 if (e1000g_global_reset(Adapter)) 3660 ddi_fm_service_impact(Adapter->dip, 3661 DDI_SERVICE_RESTORED); 3662 else 3663 ddi_fm_service_impact(Adapter->dip, 3664 DDI_SERVICE_LOST); 3665 return; 3666 } 3667 3668 if (e1000g_stall_check(Adapter)) { 3669 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3670 "Tx stall detected. Activate automatic recovery.\n"); 3671 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 3672 Adapter->reset_count++; 3673 if (e1000g_reset_adapter(Adapter)) 3674 ddi_fm_service_impact(Adapter->dip, 3675 DDI_SERVICE_RESTORED); 3676 else 3677 ddi_fm_service_impact(Adapter->dip, 3678 DDI_SERVICE_LOST); 3679 return; 3680 } 3681 3682 link_changed = B_FALSE; 3683 rw_enter(&Adapter->chip_lock, RW_READER); 3684 if (Adapter->link_complete) 3685 link_changed = e1000g_link_check(Adapter); 3686 rw_exit(&Adapter->chip_lock); 3687 3688 if (link_changed) 3689 mac_link_update(Adapter->mh, Adapter->link_state); 3690 3691 /* 3692 * Workaround for esb2. Data stuck in fifo on a link 3693 * down event. Reset the adapter to recover it. 3694 */ 3695 if (Adapter->esb2_workaround) { 3696 Adapter->esb2_workaround = B_FALSE; 3697 (void) e1000g_reset_adapter(Adapter); 3698 } 3699 3700 /* 3701 * With 82571 controllers, any locally administered address will 3702 * be overwritten when there is a reset on the other port. 3703 * Detect this circumstance and correct it. 3704 */ 3705 if ((hw->mac.type == e1000_82571) && 3706 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 3707 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 3708 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 3709 3710 ether_addr.reg.low = ntohl(ether_addr.reg.low); 3711 ether_addr.reg.high = ntohl(ether_addr.reg.high); 3712 3713 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 3714 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 3715 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 3716 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 3717 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 3718 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 3719 e1000_rar_set(hw, hw->mac.addr, 0); 3720 } 3721 } 3722 3723 /* 3724 * Long TTL workaround for 82541/82547 3725 */ 3726 (void) e1000_igp_ttl_workaround_82547(hw); 3727 3728 /* 3729 * Check for Adaptive IFS settings If there are lots of collisions 3730 * change the value in steps... 3731 * These properties should only be set for 10/100 3732 */ 3733 if ((hw->phy.media_type == e1000_media_type_copper) && 3734 ((Adapter->link_speed == SPEED_100) || 3735 (Adapter->link_speed == SPEED_10))) { 3736 e1000_update_adaptive(hw); 3737 } 3738 /* 3739 * Set Timer Interrupts 3740 */ 3741 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 3742 3743 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3744 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3745 3746 restart_watchdog_timer(Adapter); 3747 } 3748 3749 /* 3750 * The function e1000g_link_timer() is called when the timer for link setup 3751 * is expired, which indicates the completion of the link setup. The link 3752 * state will not be updated until the link setup is completed. And the 3753 * link state will not be sent to the upper layer through mac_link_update() 3754 * in this function. It will be updated in the local timer routine or the 3755 * interrupt service routine after the interface is started (plumbed). 3756 */ 3757 static void 3758 e1000g_link_timer(void *arg) 3759 { 3760 struct e1000g *Adapter = (struct e1000g *)arg; 3761 3762 mutex_enter(&Adapter->link_lock); 3763 Adapter->link_complete = B_TRUE; 3764 Adapter->link_tid = 0; 3765 mutex_exit(&Adapter->link_lock); 3766 } 3767 3768 /* 3769 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 3770 * 3771 * This function read the forced speed and duplex for 10/100 Mbps speeds 3772 * and also for 1000 Mbps speeds from the e1000g.conf file 3773 */ 3774 static void 3775 e1000g_force_speed_duplex(struct e1000g *Adapter) 3776 { 3777 int forced; 3778 struct e1000_mac_info *mac = &Adapter->shared.mac; 3779 struct e1000_phy_info *phy = &Adapter->shared.phy; 3780 3781 /* 3782 * get value out of config file 3783 */ 3784 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 3785 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 3786 3787 switch (forced) { 3788 case GDIAG_10_HALF: 3789 /* 3790 * Disable Auto Negotiation 3791 */ 3792 mac->autoneg = B_FALSE; 3793 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3794 break; 3795 case GDIAG_10_FULL: 3796 /* 3797 * Disable Auto Negotiation 3798 */ 3799 mac->autoneg = B_FALSE; 3800 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3801 break; 3802 case GDIAG_100_HALF: 3803 /* 3804 * Disable Auto Negotiation 3805 */ 3806 mac->autoneg = B_FALSE; 3807 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3808 break; 3809 case GDIAG_100_FULL: 3810 /* 3811 * Disable Auto Negotiation 3812 */ 3813 mac->autoneg = B_FALSE; 3814 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3815 break; 3816 case GDIAG_1000_FULL: 3817 /* 3818 * The gigabit spec requires autonegotiation. Therefore, 3819 * when the user wants to force the speed to 1000Mbps, we 3820 * enable AutoNeg, but only allow the harware to advertise 3821 * 1000Mbps. This is different from 10/100 operation, where 3822 * we are allowed to link without any negotiation. 3823 */ 3824 mac->autoneg = B_TRUE; 3825 phy->autoneg_advertised = ADVERTISE_1000_FULL; 3826 break; 3827 default: /* obey the setting of AutoNegAdvertised */ 3828 mac->autoneg = B_TRUE; 3829 phy->autoneg_advertised = 3830 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 3831 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 3832 AUTONEG_ADVERTISE_SPEED_DEFAULT); 3833 break; 3834 } /* switch */ 3835 } 3836 3837 /* 3838 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 3839 * 3840 * This function reads MaxFrameSize from e1000g.conf 3841 */ 3842 static void 3843 e1000g_get_max_frame_size(struct e1000g *Adapter) 3844 { 3845 int max_frame; 3846 struct e1000_mac_info *mac = &Adapter->shared.mac; 3847 struct e1000_phy_info *phy = &Adapter->shared.phy; 3848 3849 /* 3850 * get value out of config file 3851 */ 3852 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 3853 3854 switch (max_frame) { 3855 case 0: 3856 Adapter->default_mtu = ETHERMTU; 3857 break; 3858 /* 3859 * To avoid excessive memory allocation for rx buffers, 3860 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 3861 */ 3862 case 1: 3863 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 3864 sizeof (struct ether_vlan_header) - ETHERFCSL - 3865 E1000G_IPALIGNPRESERVEROOM; 3866 break; 3867 case 2: 3868 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 3869 sizeof (struct ether_vlan_header) - ETHERFCSL - 3870 E1000G_IPALIGNPRESERVEROOM; 3871 break; 3872 case 3: 3873 if (mac->type >= e1000_82571) 3874 Adapter->default_mtu = MAXIMUM_MTU; 3875 else 3876 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 3877 sizeof (struct ether_vlan_header) - ETHERFCSL - 3878 E1000G_IPALIGNPRESERVEROOM; 3879 break; 3880 default: 3881 Adapter->default_mtu = ETHERMTU; 3882 break; 3883 } /* switch */ 3884 3885 Adapter->max_frame_size = Adapter->default_mtu + 3886 sizeof (struct ether_vlan_header) + ETHERFCSL; 3887 3888 /* ich8 does not do jumbo frames */ 3889 if (mac->type == e1000_ich8lan) { 3890 Adapter->max_frame_size = ETHERMTU + 3891 sizeof (struct ether_vlan_header) + ETHERFCSL; 3892 } 3893 3894 /* ich9 does not do jumbo frames on one phy type */ 3895 if ((mac->type == e1000_ich9lan) && 3896 (phy->type == e1000_phy_ife)) { 3897 Adapter->max_frame_size = ETHERMTU + 3898 sizeof (struct ether_vlan_header) + ETHERFCSL; 3899 } 3900 } 3901 3902 static void 3903 arm_watchdog_timer(struct e1000g *Adapter) 3904 { 3905 Adapter->watchdog_tid = 3906 timeout(e1000g_local_timer, 3907 (void *)Adapter, 1 * drv_usectohz(1000000)); 3908 } 3909 #pragma inline(arm_watchdog_timer) 3910 3911 static void 3912 enable_watchdog_timer(struct e1000g *Adapter) 3913 { 3914 mutex_enter(&Adapter->watchdog_lock); 3915 3916 if (!Adapter->watchdog_timer_enabled) { 3917 Adapter->watchdog_timer_enabled = B_TRUE; 3918 Adapter->watchdog_timer_started = B_TRUE; 3919 arm_watchdog_timer(Adapter); 3920 } 3921 3922 mutex_exit(&Adapter->watchdog_lock); 3923 } 3924 3925 static void 3926 disable_watchdog_timer(struct e1000g *Adapter) 3927 { 3928 timeout_id_t tid; 3929 3930 mutex_enter(&Adapter->watchdog_lock); 3931 3932 Adapter->watchdog_timer_enabled = B_FALSE; 3933 Adapter->watchdog_timer_started = B_FALSE; 3934 tid = Adapter->watchdog_tid; 3935 Adapter->watchdog_tid = 0; 3936 3937 mutex_exit(&Adapter->watchdog_lock); 3938 3939 if (tid != 0) 3940 (void) untimeout(tid); 3941 } 3942 3943 static void 3944 start_watchdog_timer(struct e1000g *Adapter) 3945 { 3946 mutex_enter(&Adapter->watchdog_lock); 3947 3948 if (Adapter->watchdog_timer_enabled) { 3949 if (!Adapter->watchdog_timer_started) { 3950 Adapter->watchdog_timer_started = B_TRUE; 3951 arm_watchdog_timer(Adapter); 3952 } 3953 } 3954 3955 mutex_exit(&Adapter->watchdog_lock); 3956 } 3957 3958 static void 3959 restart_watchdog_timer(struct e1000g *Adapter) 3960 { 3961 mutex_enter(&Adapter->watchdog_lock); 3962 3963 if (Adapter->watchdog_timer_started) 3964 arm_watchdog_timer(Adapter); 3965 3966 mutex_exit(&Adapter->watchdog_lock); 3967 } 3968 3969 static void 3970 stop_watchdog_timer(struct e1000g *Adapter) 3971 { 3972 timeout_id_t tid; 3973 3974 mutex_enter(&Adapter->watchdog_lock); 3975 3976 Adapter->watchdog_timer_started = B_FALSE; 3977 tid = Adapter->watchdog_tid; 3978 Adapter->watchdog_tid = 0; 3979 3980 mutex_exit(&Adapter->watchdog_lock); 3981 3982 if (tid != 0) 3983 (void) untimeout(tid); 3984 } 3985 3986 static void 3987 stop_link_timer(struct e1000g *Adapter) 3988 { 3989 timeout_id_t tid; 3990 3991 /* Disable the link timer */ 3992 mutex_enter(&Adapter->link_lock); 3993 3994 tid = Adapter->link_tid; 3995 Adapter->link_tid = 0; 3996 3997 mutex_exit(&Adapter->link_lock); 3998 3999 if (tid != 0) 4000 (void) untimeout(tid); 4001 } 4002 4003 static void 4004 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4005 { 4006 timeout_id_t tid; 4007 4008 /* Disable the tx timer for 82547 chipset */ 4009 mutex_enter(&tx_ring->tx_lock); 4010 4011 tx_ring->timer_enable_82547 = B_FALSE; 4012 tid = tx_ring->timer_id_82547; 4013 tx_ring->timer_id_82547 = 0; 4014 4015 mutex_exit(&tx_ring->tx_lock); 4016 4017 if (tid != 0) 4018 (void) untimeout(tid); 4019 } 4020 4021 void 4022 e1000g_clear_interrupt(struct e1000g *Adapter) 4023 { 4024 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4025 0xffffffff & ~E1000_IMS_RXSEQ); 4026 } 4027 4028 void 4029 e1000g_mask_interrupt(struct e1000g *Adapter) 4030 { 4031 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4032 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4033 4034 if (Adapter->tx_intr_enable) 4035 e1000g_mask_tx_interrupt(Adapter); 4036 } 4037 4038 /* 4039 * This routine is called by e1000g_quiesce(), therefore must not block. 4040 */ 4041 void 4042 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4043 { 4044 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4045 } 4046 4047 void 4048 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4049 { 4050 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4051 } 4052 4053 void 4054 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4055 { 4056 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4057 } 4058 4059 static void 4060 e1000g_smartspeed(struct e1000g *Adapter) 4061 { 4062 struct e1000_hw *hw = &Adapter->shared; 4063 uint16_t phy_status; 4064 uint16_t phy_ctrl; 4065 4066 /* 4067 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4068 * advertising 1000Full, we don't even use the workaround 4069 */ 4070 if ((hw->phy.type != e1000_phy_igp) || 4071 !hw->mac.autoneg || 4072 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4073 return; 4074 4075 /* 4076 * True if this is the first call of this function or after every 4077 * 30 seconds of not having link 4078 */ 4079 if (Adapter->smartspeed == 0) { 4080 /* 4081 * If Master/Slave config fault is asserted twice, we 4082 * assume back-to-back 4083 */ 4084 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4085 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4086 return; 4087 4088 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4089 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4090 return; 4091 /* 4092 * We're assuming back-2-back because our status register 4093 * insists! there's a fault in the master/slave 4094 * relationship that was "negotiated" 4095 */ 4096 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4097 /* 4098 * Is the phy configured for manual configuration of 4099 * master/slave? 4100 */ 4101 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4102 /* 4103 * Yes. Then disable manual configuration (enable 4104 * auto configuration) of master/slave 4105 */ 4106 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4107 (void) e1000_write_phy_reg(hw, 4108 PHY_1000T_CTRL, phy_ctrl); 4109 /* 4110 * Effectively starting the clock 4111 */ 4112 Adapter->smartspeed++; 4113 /* 4114 * Restart autonegotiation 4115 */ 4116 if (!e1000_phy_setup_autoneg(hw) && 4117 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4118 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4119 MII_CR_RESTART_AUTO_NEG); 4120 (void) e1000_write_phy_reg(hw, 4121 PHY_CONTROL, phy_ctrl); 4122 } 4123 } 4124 return; 4125 /* 4126 * Has 6 seconds transpired still without link? Remember, 4127 * you should reset the smartspeed counter once you obtain 4128 * link 4129 */ 4130 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4131 /* 4132 * Yes. Remember, we did at the start determine that 4133 * there's a master/slave configuration fault, so we're 4134 * still assuming there's someone on the other end, but we 4135 * just haven't yet been able to talk to it. We then 4136 * re-enable auto configuration of master/slave to see if 4137 * we're running 2/3 pair cables. 4138 */ 4139 /* 4140 * If still no link, perhaps using 2/3 pair cable 4141 */ 4142 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4143 phy_ctrl |= CR_1000T_MS_ENABLE; 4144 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4145 /* 4146 * Restart autoneg with phy enabled for manual 4147 * configuration of master/slave 4148 */ 4149 if (!e1000_phy_setup_autoneg(hw) && 4150 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4151 phy_ctrl |= 4152 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4153 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4154 } 4155 /* 4156 * Hopefully, there are no more faults and we've obtained 4157 * link as a result. 4158 */ 4159 } 4160 /* 4161 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4162 * seconds) 4163 */ 4164 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4165 Adapter->smartspeed = 0; 4166 } 4167 4168 static boolean_t 4169 is_valid_mac_addr(uint8_t *mac_addr) 4170 { 4171 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4172 const uint8_t addr_test2[6] = 4173 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4174 4175 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4176 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4177 return (B_FALSE); 4178 4179 return (B_TRUE); 4180 } 4181 4182 /* 4183 * e1000g_stall_check - check for tx stall 4184 * 4185 * This function checks if the adapter is stalled (in transmit). 4186 * 4187 * It is called each time the watchdog timeout is invoked. 4188 * If the transmit descriptor reclaim continuously fails, 4189 * the watchdog value will increment by 1. If the watchdog 4190 * value exceeds the threshold, the adapter is assumed to 4191 * have stalled and need to be reset. 4192 */ 4193 static boolean_t 4194 e1000g_stall_check(struct e1000g *Adapter) 4195 { 4196 e1000g_tx_ring_t *tx_ring; 4197 4198 tx_ring = Adapter->tx_ring; 4199 4200 if (Adapter->link_state != LINK_STATE_UP) 4201 return (B_FALSE); 4202 4203 if (tx_ring->recycle_fail > 0) 4204 tx_ring->stall_watchdog++; 4205 else 4206 tx_ring->stall_watchdog = 0; 4207 4208 if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) 4209 return (B_FALSE); 4210 4211 tx_ring->stall_watchdog = 0; 4212 tx_ring->recycle_fail = 0; 4213 4214 return (B_TRUE); 4215 } 4216 4217 #ifdef E1000G_DEBUG 4218 static enum ioc_reply 4219 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4220 { 4221 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4222 e1000g_peekpoke_t *ppd; 4223 uint64_t mem_va; 4224 uint64_t maxoff; 4225 boolean_t peek; 4226 4227 switch (iocp->ioc_cmd) { 4228 4229 case E1000G_IOC_REG_PEEK: 4230 peek = B_TRUE; 4231 break; 4232 4233 case E1000G_IOC_REG_POKE: 4234 peek = B_FALSE; 4235 break; 4236 4237 deault: 4238 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4239 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4240 iocp->ioc_cmd); 4241 return (IOC_INVAL); 4242 } 4243 4244 /* 4245 * Validate format of ioctl 4246 */ 4247 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4248 return (IOC_INVAL); 4249 if (mp->b_cont == NULL) 4250 return (IOC_INVAL); 4251 4252 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4253 4254 /* 4255 * Validate request parameters 4256 */ 4257 switch (ppd->pp_acc_space) { 4258 4259 default: 4260 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4261 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4262 ppd->pp_acc_space); 4263 return (IOC_INVAL); 4264 4265 case E1000G_PP_SPACE_REG: 4266 /* 4267 * Memory-mapped I/O space 4268 */ 4269 ASSERT(ppd->pp_acc_size == 4); 4270 if (ppd->pp_acc_size != 4) 4271 return (IOC_INVAL); 4272 4273 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4274 return (IOC_INVAL); 4275 4276 mem_va = 0; 4277 maxoff = 0x10000; 4278 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4279 break; 4280 4281 case E1000G_PP_SPACE_E1000G: 4282 /* 4283 * E1000g data structure! 4284 */ 4285 mem_va = (uintptr_t)e1000gp; 4286 maxoff = sizeof (struct e1000g); 4287 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4288 break; 4289 4290 } 4291 4292 if (ppd->pp_acc_offset >= maxoff) 4293 return (IOC_INVAL); 4294 4295 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4296 return (IOC_INVAL); 4297 4298 /* 4299 * All OK - go! 4300 */ 4301 ppd->pp_acc_offset += mem_va; 4302 (*ppfn)(e1000gp, ppd); 4303 return (peek ? IOC_REPLY : IOC_ACK); 4304 } 4305 4306 static void 4307 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4308 { 4309 ddi_acc_handle_t handle; 4310 uint32_t *regaddr; 4311 4312 handle = e1000gp->osdep.reg_handle; 4313 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4314 (uintptr_t)ppd->pp_acc_offset); 4315 4316 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4317 } 4318 4319 static void 4320 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4321 { 4322 ddi_acc_handle_t handle; 4323 uint32_t *regaddr; 4324 uint32_t value; 4325 4326 handle = e1000gp->osdep.reg_handle; 4327 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4328 (uintptr_t)ppd->pp_acc_offset); 4329 value = (uint32_t)ppd->pp_acc_data; 4330 4331 ddi_put32(handle, regaddr, value); 4332 } 4333 4334 static void 4335 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4336 { 4337 uint64_t value; 4338 void *vaddr; 4339 4340 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4341 4342 switch (ppd->pp_acc_size) { 4343 case 1: 4344 value = *(uint8_t *)vaddr; 4345 break; 4346 4347 case 2: 4348 value = *(uint16_t *)vaddr; 4349 break; 4350 4351 case 4: 4352 value = *(uint32_t *)vaddr; 4353 break; 4354 4355 case 8: 4356 value = *(uint64_t *)vaddr; 4357 break; 4358 } 4359 4360 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4361 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4362 (void *)e1000gp, (void *)ppd, value, vaddr); 4363 4364 ppd->pp_acc_data = value; 4365 } 4366 4367 static void 4368 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4369 { 4370 uint64_t value; 4371 void *vaddr; 4372 4373 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4374 value = ppd->pp_acc_data; 4375 4376 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4377 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4378 (void *)e1000gp, (void *)ppd, value, vaddr); 4379 4380 switch (ppd->pp_acc_size) { 4381 case 1: 4382 *(uint8_t *)vaddr = (uint8_t)value; 4383 break; 4384 4385 case 2: 4386 *(uint16_t *)vaddr = (uint16_t)value; 4387 break; 4388 4389 case 4: 4390 *(uint32_t *)vaddr = (uint32_t)value; 4391 break; 4392 4393 case 8: 4394 *(uint64_t *)vaddr = (uint64_t)value; 4395 break; 4396 } 4397 } 4398 #endif 4399 4400 /* 4401 * Loopback Support 4402 */ 4403 static lb_property_t lb_normal = 4404 { normal, "normal", E1000G_LB_NONE }; 4405 static lb_property_t lb_external1000 = 4406 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4407 static lb_property_t lb_external100 = 4408 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4409 static lb_property_t lb_external10 = 4410 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4411 static lb_property_t lb_phy = 4412 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4413 4414 static enum ioc_reply 4415 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4416 { 4417 lb_info_sz_t *lbsp; 4418 lb_property_t *lbpp; 4419 struct e1000_hw *hw; 4420 uint32_t *lbmp; 4421 uint32_t size; 4422 uint32_t value; 4423 4424 hw = &Adapter->shared; 4425 4426 if (mp->b_cont == NULL) 4427 return (IOC_INVAL); 4428 4429 if (!e1000g_check_loopback_support(hw)) { 4430 e1000g_log(NULL, CE_WARN, 4431 "Loopback is not supported on e1000g%d", Adapter->instance); 4432 return (IOC_INVAL); 4433 } 4434 4435 switch (iocp->ioc_cmd) { 4436 default: 4437 return (IOC_INVAL); 4438 4439 case LB_GET_INFO_SIZE: 4440 size = sizeof (lb_info_sz_t); 4441 if (iocp->ioc_count != size) 4442 return (IOC_INVAL); 4443 4444 rw_enter(&Adapter->chip_lock, RW_WRITER); 4445 e1000g_get_phy_state(Adapter); 4446 4447 /* 4448 * Workaround for hardware faults. In order to get a stable 4449 * state of phy, we will wait for a specific interval and 4450 * try again. The time delay is an experiential value based 4451 * on our testing. 4452 */ 4453 msec_delay(100); 4454 e1000g_get_phy_state(Adapter); 4455 rw_exit(&Adapter->chip_lock); 4456 4457 value = sizeof (lb_normal); 4458 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4459 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4460 (hw->phy.media_type == e1000_media_type_fiber) || 4461 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4462 value += sizeof (lb_phy); 4463 switch (hw->mac.type) { 4464 case e1000_82571: 4465 case e1000_82572: 4466 case e1000_80003es2lan: 4467 value += sizeof (lb_external1000); 4468 break; 4469 } 4470 } 4471 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4472 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4473 value += sizeof (lb_external100); 4474 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4475 value += sizeof (lb_external10); 4476 4477 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 4478 *lbsp = value; 4479 break; 4480 4481 case LB_GET_INFO: 4482 value = sizeof (lb_normal); 4483 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4484 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4485 (hw->phy.media_type == e1000_media_type_fiber) || 4486 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4487 value += sizeof (lb_phy); 4488 switch (hw->mac.type) { 4489 case e1000_82571: 4490 case e1000_82572: 4491 case e1000_80003es2lan: 4492 value += sizeof (lb_external1000); 4493 break; 4494 } 4495 } 4496 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4497 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4498 value += sizeof (lb_external100); 4499 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4500 value += sizeof (lb_external10); 4501 4502 size = value; 4503 if (iocp->ioc_count != size) 4504 return (IOC_INVAL); 4505 4506 value = 0; 4507 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 4508 lbpp[value++] = lb_normal; 4509 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4510 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4511 (hw->phy.media_type == e1000_media_type_fiber) || 4512 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4513 lbpp[value++] = lb_phy; 4514 switch (hw->mac.type) { 4515 case e1000_82571: 4516 case e1000_82572: 4517 case e1000_80003es2lan: 4518 lbpp[value++] = lb_external1000; 4519 break; 4520 } 4521 } 4522 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4523 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4524 lbpp[value++] = lb_external100; 4525 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4526 lbpp[value++] = lb_external10; 4527 break; 4528 4529 case LB_GET_MODE: 4530 size = sizeof (uint32_t); 4531 if (iocp->ioc_count != size) 4532 return (IOC_INVAL); 4533 4534 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4535 *lbmp = Adapter->loopback_mode; 4536 break; 4537 4538 case LB_SET_MODE: 4539 size = 0; 4540 if (iocp->ioc_count != sizeof (uint32_t)) 4541 return (IOC_INVAL); 4542 4543 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4544 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4545 return (IOC_INVAL); 4546 break; 4547 } 4548 4549 iocp->ioc_count = size; 4550 iocp->ioc_error = 0; 4551 4552 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4553 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4554 return (IOC_INVAL); 4555 } 4556 4557 return (IOC_REPLY); 4558 } 4559 4560 static boolean_t 4561 e1000g_check_loopback_support(struct e1000_hw *hw) 4562 { 4563 switch (hw->mac.type) { 4564 case e1000_82540: 4565 case e1000_82545: 4566 case e1000_82545_rev_3: 4567 case e1000_82546: 4568 case e1000_82546_rev_3: 4569 case e1000_82541: 4570 case e1000_82541_rev_2: 4571 case e1000_82547: 4572 case e1000_82547_rev_2: 4573 case e1000_82571: 4574 case e1000_82572: 4575 case e1000_82573: 4576 case e1000_80003es2lan: 4577 return (B_TRUE); 4578 } 4579 return (B_FALSE); 4580 } 4581 4582 static boolean_t 4583 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 4584 { 4585 struct e1000_hw *hw; 4586 int i, times; 4587 boolean_t link_up; 4588 4589 if (mode == Adapter->loopback_mode) 4590 return (B_TRUE); 4591 4592 hw = &Adapter->shared; 4593 times = 0; 4594 4595 Adapter->loopback_mode = mode; 4596 4597 if (mode == E1000G_LB_NONE) { 4598 /* Reset the chip */ 4599 hw->phy.autoneg_wait_to_complete = B_TRUE; 4600 (void) e1000g_reset_adapter(Adapter); 4601 hw->phy.autoneg_wait_to_complete = B_FALSE; 4602 return (B_TRUE); 4603 } 4604 4605 again: 4606 4607 rw_enter(&Adapter->chip_lock, RW_WRITER); 4608 4609 switch (mode) { 4610 default: 4611 rw_exit(&Adapter->chip_lock); 4612 return (B_FALSE); 4613 4614 case E1000G_LB_EXTERNAL_1000: 4615 e1000g_set_external_loopback_1000(Adapter); 4616 break; 4617 4618 case E1000G_LB_EXTERNAL_100: 4619 e1000g_set_external_loopback_100(Adapter); 4620 break; 4621 4622 case E1000G_LB_EXTERNAL_10: 4623 e1000g_set_external_loopback_10(Adapter); 4624 break; 4625 4626 case E1000G_LB_INTERNAL_PHY: 4627 e1000g_set_internal_loopback(Adapter); 4628 break; 4629 } 4630 4631 times++; 4632 4633 rw_exit(&Adapter->chip_lock); 4634 4635 /* Wait for link up */ 4636 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 4637 msec_delay(100); 4638 4639 rw_enter(&Adapter->chip_lock, RW_WRITER); 4640 4641 link_up = e1000g_link_up(Adapter); 4642 4643 rw_exit(&Adapter->chip_lock); 4644 4645 if (!link_up) { 4646 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4647 "Failed to get the link up"); 4648 if (times < 2) { 4649 /* Reset the link */ 4650 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4651 "Reset the link ..."); 4652 (void) e1000g_reset_adapter(Adapter); 4653 goto again; 4654 } 4655 } 4656 4657 return (B_TRUE); 4658 } 4659 4660 /* 4661 * The following loopback settings are from Intel's technical 4662 * document - "How To Loopback". All the register settings and 4663 * time delay values are directly inherited from the document 4664 * without more explanations available. 4665 */ 4666 static void 4667 e1000g_set_internal_loopback(struct e1000g *Adapter) 4668 { 4669 struct e1000_hw *hw; 4670 uint32_t ctrl; 4671 uint32_t status; 4672 uint16_t phy_ctrl; 4673 uint32_t txcw; 4674 4675 hw = &Adapter->shared; 4676 4677 /* Disable Smart Power Down */ 4678 phy_spd_state(hw, B_FALSE); 4679 4680 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4681 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 4682 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 4683 4684 switch (hw->mac.type) { 4685 case e1000_82540: 4686 case e1000_82545: 4687 case e1000_82545_rev_3: 4688 case e1000_82546: 4689 case e1000_82546_rev_3: 4690 case e1000_82573: 4691 /* Auto-MDI/MDIX off */ 4692 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 4693 /* Reset PHY to update Auto-MDI/MDIX */ 4694 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4695 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 4696 /* Reset PHY to auto-neg off and force 1000 */ 4697 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4698 phy_ctrl | MII_CR_RESET); 4699 /* 4700 * Disable PHY receiver for 82540/545/546 and 82573 Family. 4701 * See comments above e1000g_set_internal_loopback() for the 4702 * background. 4703 */ 4704 (void) e1000_write_phy_reg(hw, 29, 0x001F); 4705 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 4706 (void) e1000_write_phy_reg(hw, 29, 0x001A); 4707 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 4708 break; 4709 case e1000_80003es2lan: 4710 /* Force Link Up */ 4711 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 4712 0x1CC); 4713 /* Sets PCS loopback at 1Gbs */ 4714 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 4715 0x1046); 4716 break; 4717 } 4718 4719 /* Set loopback */ 4720 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 4721 4722 msec_delay(250); 4723 4724 /* Now set up the MAC to the same speed/duplex as the PHY. */ 4725 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4726 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4727 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4728 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4729 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 4730 E1000_CTRL_FD); /* Force Duplex to FULL */ 4731 4732 switch (hw->mac.type) { 4733 case e1000_82540: 4734 case e1000_82545: 4735 case e1000_82545_rev_3: 4736 case e1000_82546: 4737 case e1000_82546_rev_3: 4738 /* 4739 * For some serdes we'll need to commit the writes now 4740 * so that the status is updated on link 4741 */ 4742 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 4743 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4744 msec_delay(100); 4745 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4746 } 4747 4748 if (hw->phy.media_type == e1000_media_type_copper) { 4749 /* Invert Loss of Signal */ 4750 ctrl |= E1000_CTRL_ILOS; 4751 } else { 4752 /* Set ILOS on fiber nic if half duplex is detected */ 4753 status = E1000_READ_REG(hw, E1000_STATUS); 4754 if ((status & E1000_STATUS_FD) == 0) 4755 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4756 } 4757 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4758 break; 4759 4760 case e1000_82571: 4761 case e1000_82572: 4762 /* 4763 * The fiber/SerDes versions of this adapter do not contain an 4764 * accessible PHY. Therefore, loopback beyond MAC must be done 4765 * using SerDes analog loopback. 4766 */ 4767 if (hw->phy.media_type != e1000_media_type_copper) { 4768 status = E1000_READ_REG(hw, E1000_STATUS); 4769 /* Set ILOS on fiber nic if half duplex is detected */ 4770 if (((status & E1000_STATUS_LU) == 0) || 4771 ((status & E1000_STATUS_FD) == 0) || 4772 (hw->phy.media_type == 4773 e1000_media_type_internal_serdes)) 4774 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4775 4776 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4777 txcw = E1000_READ_REG(hw, E1000_TXCW); 4778 txcw &= ~((uint32_t)1 << 31); 4779 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4780 4781 /* 4782 * Write 0x410 to Serdes Control register 4783 * to enable Serdes analog loopback 4784 */ 4785 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4786 msec_delay(10); 4787 } 4788 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4789 break; 4790 4791 case e1000_82573: 4792 ctrl |= E1000_CTRL_ILOS; 4793 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4794 break; 4795 } 4796 } 4797 4798 static void 4799 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 4800 { 4801 struct e1000_hw *hw; 4802 uint32_t rctl; 4803 uint32_t ctrl_ext; 4804 uint32_t ctrl; 4805 uint32_t status; 4806 uint32_t txcw; 4807 uint16_t phydata; 4808 4809 hw = &Adapter->shared; 4810 4811 /* Disable Smart Power Down */ 4812 phy_spd_state(hw, B_FALSE); 4813 4814 switch (hw->mac.type) { 4815 case e1000_82571: 4816 case e1000_82572: 4817 switch (hw->phy.media_type) { 4818 case e1000_media_type_copper: 4819 /* Force link up (Must be done before the PHY writes) */ 4820 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4821 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 4822 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4823 4824 rctl = E1000_READ_REG(hw, E1000_RCTL); 4825 rctl |= (E1000_RCTL_EN | 4826 E1000_RCTL_SBP | 4827 E1000_RCTL_UPE | 4828 E1000_RCTL_MPE | 4829 E1000_RCTL_LPE | 4830 E1000_RCTL_BAM); /* 0x803E */ 4831 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4832 4833 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4834 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 4835 E1000_CTRL_EXT_SDP6_DATA | 4836 E1000_CTRL_EXT_SDP7_DATA | 4837 E1000_CTRL_EXT_SDP4_DIR | 4838 E1000_CTRL_EXT_SDP6_DIR | 4839 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 4840 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4841 4842 /* 4843 * This sequence tunes the PHY's SDP and no customer 4844 * settable values. For background, see comments above 4845 * e1000g_set_internal_loopback(). 4846 */ 4847 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 4848 msec_delay(10); 4849 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 4850 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 4851 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 4852 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 4853 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 4854 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 4855 4856 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 4857 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 4858 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 4859 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 4860 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 4861 4862 msec_delay(50); 4863 break; 4864 case e1000_media_type_fiber: 4865 case e1000_media_type_internal_serdes: 4866 status = E1000_READ_REG(hw, E1000_STATUS); 4867 if (((status & E1000_STATUS_LU) == 0) || 4868 (hw->phy.media_type == 4869 e1000_media_type_internal_serdes)) { 4870 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4871 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4872 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4873 } 4874 4875 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4876 txcw = E1000_READ_REG(hw, E1000_TXCW); 4877 txcw &= ~((uint32_t)1 << 31); 4878 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4879 4880 /* 4881 * Write 0x410 to Serdes Control register 4882 * to enable Serdes analog loopback 4883 */ 4884 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4885 msec_delay(10); 4886 break; 4887 default: 4888 break; 4889 } 4890 break; 4891 case e1000_80003es2lan: 4892 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 4893 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 4894 phydata | (1 << 5)); 4895 Adapter->param_adv_autoneg = 1; 4896 Adapter->param_adv_1000fdx = 1; 4897 (void) e1000g_reset_link(Adapter); 4898 break; 4899 } 4900 } 4901 4902 static void 4903 e1000g_set_external_loopback_100(struct e1000g *Adapter) 4904 { 4905 struct e1000_hw *hw; 4906 uint32_t ctrl; 4907 uint16_t phy_ctrl; 4908 4909 hw = &Adapter->shared; 4910 4911 /* Disable Smart Power Down */ 4912 phy_spd_state(hw, B_FALSE); 4913 4914 phy_ctrl = (MII_CR_FULL_DUPLEX | 4915 MII_CR_SPEED_100); 4916 4917 /* Force 100/FD, reset PHY */ 4918 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4919 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 4920 msec_delay(10); 4921 4922 /* Force 100/FD */ 4923 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4924 phy_ctrl); /* 0x2100 */ 4925 msec_delay(10); 4926 4927 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4928 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4929 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4930 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4931 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4932 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4933 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 4934 E1000_CTRL_FD); /* Force Duplex to FULL */ 4935 4936 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4937 } 4938 4939 static void 4940 e1000g_set_external_loopback_10(struct e1000g *Adapter) 4941 { 4942 struct e1000_hw *hw; 4943 uint32_t ctrl; 4944 uint16_t phy_ctrl; 4945 4946 hw = &Adapter->shared; 4947 4948 /* Disable Smart Power Down */ 4949 phy_spd_state(hw, B_FALSE); 4950 4951 phy_ctrl = (MII_CR_FULL_DUPLEX | 4952 MII_CR_SPEED_10); 4953 4954 /* Force 10/FD, reset PHY */ 4955 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4956 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 4957 msec_delay(10); 4958 4959 /* Force 10/FD */ 4960 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4961 phy_ctrl); /* 0x0100 */ 4962 msec_delay(10); 4963 4964 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4965 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4966 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4967 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4968 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4969 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4970 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 4971 E1000_CTRL_FD); /* Force Duplex to FULL */ 4972 4973 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4974 } 4975 4976 #ifdef __sparc 4977 static boolean_t 4978 e1000g_find_mac_address(struct e1000g *Adapter) 4979 { 4980 struct e1000_hw *hw = &Adapter->shared; 4981 uchar_t *bytes; 4982 struct ether_addr sysaddr; 4983 uint_t nelts; 4984 int err; 4985 boolean_t found = B_FALSE; 4986 4987 /* 4988 * The "vendor's factory-set address" may already have 4989 * been extracted from the chip, but if the property 4990 * "local-mac-address" is set we use that instead. 4991 * 4992 * We check whether it looks like an array of 6 4993 * bytes (which it should, if OBP set it). If we can't 4994 * make sense of it this way, we'll ignore it. 4995 */ 4996 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4997 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 4998 if (err == DDI_PROP_SUCCESS) { 4999 if (nelts == ETHERADDRL) { 5000 while (nelts--) 5001 hw->mac.addr[nelts] = bytes[nelts]; 5002 found = B_TRUE; 5003 } 5004 ddi_prop_free(bytes); 5005 } 5006 5007 /* 5008 * Look up the OBP property "local-mac-address?". If the user has set 5009 * 'local-mac-address? = false', use "the system address" instead. 5010 */ 5011 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5012 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5013 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5014 if (localetheraddr(NULL, &sysaddr) != 0) { 5015 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5016 found = B_TRUE; 5017 } 5018 } 5019 ddi_prop_free(bytes); 5020 } 5021 5022 /* 5023 * Finally(!), if there's a valid "mac-address" property (created 5024 * if we netbooted from this interface), we must use this instead 5025 * of any of the above to ensure that the NFS/install server doesn't 5026 * get confused by the address changing as Solaris takes over! 5027 */ 5028 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5029 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5030 if (err == DDI_PROP_SUCCESS) { 5031 if (nelts == ETHERADDRL) { 5032 while (nelts--) 5033 hw->mac.addr[nelts] = bytes[nelts]; 5034 found = B_TRUE; 5035 } 5036 ddi_prop_free(bytes); 5037 } 5038 5039 if (found) { 5040 bcopy(hw->mac.addr, hw->mac.perm_addr, 5041 ETHERADDRL); 5042 } 5043 5044 return (found); 5045 } 5046 #endif 5047 5048 static int 5049 e1000g_add_intrs(struct e1000g *Adapter) 5050 { 5051 dev_info_t *devinfo; 5052 int intr_types; 5053 int rc; 5054 5055 devinfo = Adapter->dip; 5056 5057 /* Get supported interrupt types */ 5058 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5059 5060 if (rc != DDI_SUCCESS) { 5061 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5062 "Get supported interrupt types failed: %d\n", rc); 5063 return (DDI_FAILURE); 5064 } 5065 5066 /* 5067 * Based on Intel Technical Advisory document (TA-160), there are some 5068 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5069 * that it supports MSI, but in fact has problems. 5070 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5071 * PCI/PCI-X NICs. 5072 */ 5073 if (Adapter->shared.mac.type < e1000_82571) 5074 Adapter->msi_enable = B_FALSE; 5075 5076 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5077 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5078 5079 if (rc != DDI_SUCCESS) { 5080 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5081 "Add MSI failed, trying Legacy interrupts\n"); 5082 } else { 5083 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5084 } 5085 } 5086 5087 if ((Adapter->intr_type == 0) && 5088 (intr_types & DDI_INTR_TYPE_FIXED)) { 5089 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5090 5091 if (rc != DDI_SUCCESS) { 5092 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5093 "Add Legacy interrupts failed\n"); 5094 return (DDI_FAILURE); 5095 } 5096 5097 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5098 } 5099 5100 if (Adapter->intr_type == 0) { 5101 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5102 "No interrupts registered\n"); 5103 return (DDI_FAILURE); 5104 } 5105 5106 return (DDI_SUCCESS); 5107 } 5108 5109 /* 5110 * e1000g_intr_add() handles MSI/Legacy interrupts 5111 */ 5112 static int 5113 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5114 { 5115 dev_info_t *devinfo; 5116 int count, avail, actual; 5117 int x, y, rc, inum = 0; 5118 int flag; 5119 ddi_intr_handler_t *intr_handler; 5120 5121 devinfo = Adapter->dip; 5122 5123 /* get number of interrupts */ 5124 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5125 if ((rc != DDI_SUCCESS) || (count == 0)) { 5126 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5127 "Get interrupt number failed. Return: %d, count: %d\n", 5128 rc, count); 5129 return (DDI_FAILURE); 5130 } 5131 5132 /* get number of available interrupts */ 5133 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5134 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5135 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5136 "Get interrupt available number failed. " 5137 "Return: %d, available: %d\n", rc, avail); 5138 return (DDI_FAILURE); 5139 } 5140 5141 if (avail < count) { 5142 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5143 "Interrupts count: %d, available: %d\n", 5144 count, avail); 5145 } 5146 5147 /* Allocate an array of interrupt handles */ 5148 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5149 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5150 5151 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5152 flag = DDI_INTR_ALLOC_NORMAL; 5153 5154 /* call ddi_intr_alloc() */ 5155 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5156 count, &actual, flag); 5157 5158 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5159 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5160 "Allocate interrupts failed: %d\n", rc); 5161 5162 kmem_free(Adapter->htable, Adapter->intr_size); 5163 return (DDI_FAILURE); 5164 } 5165 5166 if (actual < count) { 5167 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5168 "Interrupts requested: %d, received: %d\n", 5169 count, actual); 5170 } 5171 5172 Adapter->intr_cnt = actual; 5173 5174 /* Get priority for first msi, assume remaining are all the same */ 5175 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5176 5177 if (rc != DDI_SUCCESS) { 5178 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5179 "Get interrupt priority failed: %d\n", rc); 5180 5181 /* Free already allocated intr */ 5182 for (y = 0; y < actual; y++) 5183 (void) ddi_intr_free(Adapter->htable[y]); 5184 5185 kmem_free(Adapter->htable, Adapter->intr_size); 5186 return (DDI_FAILURE); 5187 } 5188 5189 /* 5190 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5191 * use the interrupt service routine e1000g_intr_pciexpress() 5192 * to avoid interrupt stealing when sharing interrupt with other 5193 * devices. 5194 */ 5195 if (Adapter->shared.mac.type < e1000_82571) 5196 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5197 else 5198 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5199 5200 /* Call ddi_intr_add_handler() */ 5201 for (x = 0; x < actual; x++) { 5202 rc = ddi_intr_add_handler(Adapter->htable[x], 5203 intr_handler, (caddr_t)Adapter, NULL); 5204 5205 if (rc != DDI_SUCCESS) { 5206 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5207 "Add interrupt handler failed: %d\n", rc); 5208 5209 /* Remove already added handler */ 5210 for (y = 0; y < x; y++) 5211 (void) ddi_intr_remove_handler( 5212 Adapter->htable[y]); 5213 5214 /* Free already allocated intr */ 5215 for (y = 0; y < actual; y++) 5216 (void) ddi_intr_free(Adapter->htable[y]); 5217 5218 kmem_free(Adapter->htable, Adapter->intr_size); 5219 return (DDI_FAILURE); 5220 } 5221 } 5222 5223 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5224 5225 if (rc != DDI_SUCCESS) { 5226 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5227 "Get interrupt cap failed: %d\n", rc); 5228 5229 /* Free already allocated intr */ 5230 for (y = 0; y < actual; y++) { 5231 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5232 (void) ddi_intr_free(Adapter->htable[y]); 5233 } 5234 5235 kmem_free(Adapter->htable, Adapter->intr_size); 5236 return (DDI_FAILURE); 5237 } 5238 5239 return (DDI_SUCCESS); 5240 } 5241 5242 static int 5243 e1000g_rem_intrs(struct e1000g *Adapter) 5244 { 5245 int x; 5246 int rc; 5247 5248 for (x = 0; x < Adapter->intr_cnt; x++) { 5249 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5250 if (rc != DDI_SUCCESS) { 5251 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5252 "Remove intr handler failed: %d\n", rc); 5253 return (DDI_FAILURE); 5254 } 5255 5256 rc = ddi_intr_free(Adapter->htable[x]); 5257 if (rc != DDI_SUCCESS) { 5258 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5259 "Free intr failed: %d\n", rc); 5260 return (DDI_FAILURE); 5261 } 5262 } 5263 5264 kmem_free(Adapter->htable, Adapter->intr_size); 5265 5266 return (DDI_SUCCESS); 5267 } 5268 5269 static int 5270 e1000g_enable_intrs(struct e1000g *Adapter) 5271 { 5272 int x; 5273 int rc; 5274 5275 /* Enable interrupts */ 5276 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5277 /* Call ddi_intr_block_enable() for MSI */ 5278 rc = ddi_intr_block_enable(Adapter->htable, 5279 Adapter->intr_cnt); 5280 if (rc != DDI_SUCCESS) { 5281 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5282 "Enable block intr failed: %d\n", rc); 5283 return (DDI_FAILURE); 5284 } 5285 } else { 5286 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5287 for (x = 0; x < Adapter->intr_cnt; x++) { 5288 rc = ddi_intr_enable(Adapter->htable[x]); 5289 if (rc != DDI_SUCCESS) { 5290 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5291 "Enable intr failed: %d\n", rc); 5292 return (DDI_FAILURE); 5293 } 5294 } 5295 } 5296 5297 return (DDI_SUCCESS); 5298 } 5299 5300 static int 5301 e1000g_disable_intrs(struct e1000g *Adapter) 5302 { 5303 int x; 5304 int rc; 5305 5306 /* Disable all interrupts */ 5307 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5308 rc = ddi_intr_block_disable(Adapter->htable, 5309 Adapter->intr_cnt); 5310 if (rc != DDI_SUCCESS) { 5311 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5312 "Disable block intr failed: %d\n", rc); 5313 return (DDI_FAILURE); 5314 } 5315 } else { 5316 for (x = 0; x < Adapter->intr_cnt; x++) { 5317 rc = ddi_intr_disable(Adapter->htable[x]); 5318 if (rc != DDI_SUCCESS) { 5319 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5320 "Disable intr failed: %d\n", rc); 5321 return (DDI_FAILURE); 5322 } 5323 } 5324 } 5325 5326 return (DDI_SUCCESS); 5327 } 5328 5329 /* 5330 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5331 */ 5332 static void 5333 e1000g_get_phy_state(struct e1000g *Adapter) 5334 { 5335 struct e1000_hw *hw = &Adapter->shared; 5336 5337 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5338 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5339 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 5340 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 5341 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 5342 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 5343 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5344 &Adapter->phy_1000t_status); 5345 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 5346 5347 Adapter->param_autoneg_cap = 5348 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5349 Adapter->param_pause_cap = 5350 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5351 Adapter->param_asym_pause_cap = 5352 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5353 Adapter->param_1000fdx_cap = 5354 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5355 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5356 Adapter->param_1000hdx_cap = 5357 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5358 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5359 Adapter->param_100t4_cap = 5360 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5361 Adapter->param_100fdx_cap = 5362 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5363 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5364 Adapter->param_100hdx_cap = 5365 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5366 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5367 Adapter->param_10fdx_cap = 5368 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5369 Adapter->param_10hdx_cap = 5370 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5371 5372 Adapter->param_adv_autoneg = hw->mac.autoneg; 5373 Adapter->param_adv_pause = 5374 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5375 Adapter->param_adv_asym_pause = 5376 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5377 Adapter->param_adv_1000hdx = 5378 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5379 Adapter->param_adv_100t4 = 5380 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5381 if (Adapter->param_adv_autoneg == 1) { 5382 Adapter->param_adv_1000fdx = 5383 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5384 Adapter->param_adv_100fdx = 5385 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5386 Adapter->param_adv_100hdx = 5387 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5388 Adapter->param_adv_10fdx = 5389 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5390 Adapter->param_adv_10hdx = 5391 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5392 } 5393 5394 Adapter->param_lp_autoneg = 5395 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5396 Adapter->param_lp_pause = 5397 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5398 Adapter->param_lp_asym_pause = 5399 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5400 Adapter->param_lp_1000fdx = 5401 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5402 Adapter->param_lp_1000hdx = 5403 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5404 Adapter->param_lp_100t4 = 5405 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5406 Adapter->param_lp_100fdx = 5407 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5408 Adapter->param_lp_100hdx = 5409 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5410 Adapter->param_lp_10fdx = 5411 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5412 Adapter->param_lp_10hdx = 5413 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5414 } 5415 5416 /* 5417 * FMA support 5418 */ 5419 5420 int 5421 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5422 { 5423 ddi_fm_error_t de; 5424 5425 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5426 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5427 return (de.fme_status); 5428 } 5429 5430 int 5431 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5432 { 5433 ddi_fm_error_t de; 5434 5435 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5436 return (de.fme_status); 5437 } 5438 5439 /* 5440 * The IO fault service error handling callback function 5441 */ 5442 /* ARGSUSED2 */ 5443 static int 5444 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5445 { 5446 /* 5447 * as the driver can always deal with an error in any dma or 5448 * access handle, we can just return the fme_status value. 5449 */ 5450 pci_ereport_post(dip, err, NULL); 5451 return (err->fme_status); 5452 } 5453 5454 static void 5455 e1000g_fm_init(struct e1000g *Adapter) 5456 { 5457 ddi_iblock_cookie_t iblk; 5458 int fma_acc_flag, fma_dma_flag; 5459 5460 /* Only register with IO Fault Services if we have some capability */ 5461 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5462 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5463 fma_acc_flag = 1; 5464 } else { 5465 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5466 fma_acc_flag = 0; 5467 } 5468 5469 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5470 fma_dma_flag = 1; 5471 } else { 5472 fma_dma_flag = 0; 5473 } 5474 5475 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5476 5477 if (Adapter->fm_capabilities) { 5478 5479 /* Register capabilities with IO Fault Services */ 5480 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5481 5482 /* 5483 * Initialize pci ereport capabilities if ereport capable 5484 */ 5485 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5486 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5487 pci_ereport_setup(Adapter->dip); 5488 5489 /* 5490 * Register error callback if error callback capable 5491 */ 5492 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5493 ddi_fm_handler_register(Adapter->dip, 5494 e1000g_fm_error_cb, (void*) Adapter); 5495 } 5496 } 5497 5498 static void 5499 e1000g_fm_fini(struct e1000g *Adapter) 5500 { 5501 /* Only unregister FMA capabilities if we registered some */ 5502 if (Adapter->fm_capabilities) { 5503 5504 /* 5505 * Release any resources allocated by pci_ereport_setup() 5506 */ 5507 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5508 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5509 pci_ereport_teardown(Adapter->dip); 5510 5511 /* 5512 * Un-register error callback if error callback capable 5513 */ 5514 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5515 ddi_fm_handler_unregister(Adapter->dip); 5516 5517 /* Unregister from IO Fault Services */ 5518 ddi_fm_fini(Adapter->dip); 5519 } 5520 } 5521 5522 void 5523 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 5524 { 5525 uint64_t ena; 5526 char buf[FM_MAX_CLASS]; 5527 5528 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5529 ena = fm_ena_generate(0, FM_ENA_FMT1); 5530 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 5531 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 5532 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5533 } 5534 } 5535 5536 /* 5537 * quiesce(9E) entry point. 5538 * 5539 * This function is called when the system is single-threaded at high 5540 * PIL with preemption disabled. Therefore, this function must not be 5541 * blocked. 5542 * 5543 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 5544 * DDI_FAILURE indicates an error condition and should almost never happen. 5545 */ 5546 static int 5547 e1000g_quiesce(dev_info_t *devinfo) 5548 { 5549 struct e1000g *Adapter; 5550 5551 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 5552 5553 if (Adapter == NULL) 5554 return (DDI_FAILURE); 5555 5556 e1000g_clear_all_interrupts(Adapter); 5557 5558 (void) e1000_reset_hw(&Adapter->shared); 5559 5560 /* Setup our HW Tx Head & Tail descriptor pointers */ 5561 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 5562 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 5563 5564 /* Setup our HW Rx Head & Tail descriptor pointers */ 5565 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 5566 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 5567 5568 return (DDI_SUCCESS); 5569 } 5570 5571 static int 5572 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 5573 uint_t pr_valsize, void *pr_val) 5574 { 5575 link_flowctrl_t fl; 5576 int err = 0; 5577 5578 ASSERT(pr_valsize > 0); 5579 switch (pr_num) { 5580 case MAC_PROP_AUTONEG: 5581 *(uint8_t *)pr_val = 5582 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0); 5583 break; 5584 case MAC_PROP_FLOWCTRL: 5585 if (pr_valsize < sizeof (link_flowctrl_t)) 5586 return (EINVAL); 5587 fl = LINK_FLOWCTRL_BI; 5588 bcopy(&fl, pr_val, sizeof (fl)); 5589 break; 5590 case MAC_PROP_ADV_1000FDX_CAP: 5591 case MAC_PROP_EN_1000FDX_CAP: 5592 *(uint8_t *)pr_val = 5593 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5594 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5595 break; 5596 case MAC_PROP_ADV_1000HDX_CAP: 5597 case MAC_PROP_EN_1000HDX_CAP: 5598 *(uint8_t *)pr_val = 5599 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5600 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5601 break; 5602 case MAC_PROP_ADV_100FDX_CAP: 5603 case MAC_PROP_EN_100FDX_CAP: 5604 *(uint8_t *)pr_val = 5605 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5606 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5607 break; 5608 case MAC_PROP_ADV_100HDX_CAP: 5609 case MAC_PROP_EN_100HDX_CAP: 5610 *(uint8_t *)pr_val = 5611 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5612 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5613 break; 5614 case MAC_PROP_ADV_10FDX_CAP: 5615 case MAC_PROP_EN_10FDX_CAP: 5616 *(uint8_t *)pr_val = 5617 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5618 break; 5619 case MAC_PROP_ADV_10HDX_CAP: 5620 case MAC_PROP_EN_10HDX_CAP: 5621 *(uint8_t *)pr_val = 5622 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5623 break; 5624 default: 5625 err = ENOTSUP; 5626 break; 5627 } 5628 return (err); 5629 } 5630 5631 /* 5632 * synchronize the adv* and en* parameters. 5633 * 5634 * See comments in <sys/dld.h> for details of the *_en_* 5635 * parameters. The usage of ndd for setting adv parameters will 5636 * synchronize all the en parameters with the e1000g parameters, 5637 * implicitly disabling any settings made via dladm. 5638 */ 5639 static void 5640 e1000g_param_sync(struct e1000g *Adapter) 5641 { 5642 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 5643 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 5644 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 5645 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 5646 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 5647 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 5648 } 5649 5650 /* 5651 * e1000g_get_driver_control - tell manageability firmware that the driver 5652 * has control. 5653 */ 5654 static void 5655 e1000g_get_driver_control(struct e1000_hw *hw) 5656 { 5657 uint32_t ctrl_ext; 5658 uint32_t swsm; 5659 5660 /* tell manageability firmware the driver has taken over */ 5661 switch (hw->mac.type) { 5662 case e1000_82573: 5663 swsm = E1000_READ_REG(hw, E1000_SWSM); 5664 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 5665 break; 5666 case e1000_82571: 5667 case e1000_82572: 5668 case e1000_82574: 5669 case e1000_80003es2lan: 5670 case e1000_ich8lan: 5671 case e1000_ich9lan: 5672 case e1000_ich10lan: 5673 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5674 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 5675 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 5676 break; 5677 default: 5678 /* no manageability firmware: do nothing */ 5679 break; 5680 } 5681 } 5682 5683 /* 5684 * e1000g_release_driver_control - tell manageability firmware that the driver 5685 * has released control. 5686 */ 5687 static void 5688 e1000g_release_driver_control(struct e1000_hw *hw) 5689 { 5690 uint32_t ctrl_ext; 5691 uint32_t swsm; 5692 5693 /* tell manageability firmware the driver has released control */ 5694 switch (hw->mac.type) { 5695 case e1000_82573: 5696 swsm = E1000_READ_REG(hw, E1000_SWSM); 5697 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 5698 break; 5699 case e1000_82571: 5700 case e1000_82572: 5701 case e1000_82574: 5702 case e1000_80003es2lan: 5703 case e1000_ich8lan: 5704 case e1000_ich9lan: 5705 case e1000_ich10lan: 5706 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5707 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 5708 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 5709 break; 5710 default: 5711 /* no manageability firmware: do nothing */ 5712 break; 5713 } 5714 } 5715 5716 /* 5717 * Restore e1000g promiscuous mode. 5718 */ 5719 static void 5720 e1000g_restore_promisc(struct e1000g *Adapter) 5721 { 5722 if (Adapter->e1000g_promisc) { 5723 uint32_t rctl; 5724 5725 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 5726 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 5727 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 5728 } 5729 } 5730