1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet"; 48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 49 static char e1000g_version[] = "Driver Ver. 5.3.21"; 50 51 /* 52 * Proto types for DDI entry points 53 */ 54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 56 static int e1000g_quiesce(dev_info_t *); 57 58 /* 59 * init and intr routines prototype 60 */ 61 static int e1000g_resume(dev_info_t *); 62 static int e1000g_suspend(dev_info_t *); 63 static uint_t e1000g_intr_pciexpress(caddr_t); 64 static uint_t e1000g_intr(caddr_t); 65 static void e1000g_intr_work(struct e1000g *, uint32_t); 66 #pragma inline(e1000g_intr_work) 67 static int e1000g_init(struct e1000g *); 68 static int e1000g_start(struct e1000g *, boolean_t); 69 static void e1000g_stop(struct e1000g *, boolean_t); 70 static int e1000g_m_start(void *); 71 static void e1000g_m_stop(void *); 72 static int e1000g_m_promisc(void *, boolean_t); 73 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 74 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 75 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 76 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 77 uint_t, const void *); 78 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 79 uint_t, uint_t, void *, uint_t *); 80 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 81 const void *); 82 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 83 uint_t, void *, uint_t *); 84 static void e1000g_init_locks(struct e1000g *); 85 static void e1000g_destroy_locks(struct e1000g *); 86 static int e1000g_identify_hardware(struct e1000g *); 87 static int e1000g_regs_map(struct e1000g *); 88 static int e1000g_set_driver_params(struct e1000g *); 89 static void e1000g_set_bufsize(struct e1000g *); 90 static int e1000g_register_mac(struct e1000g *); 91 static boolean_t e1000g_rx_drain(struct e1000g *); 92 static boolean_t e1000g_tx_drain(struct e1000g *); 93 static void e1000g_init_unicst(struct e1000g *); 94 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int); 95 static int e1000g_alloc_rx_data(struct e1000g *); 96 static void e1000g_release_multicast(struct e1000g *); 97 static void e1000g_pch_limits(struct e1000g *); 98 static uint32_t e1000g_mtu2maxframe(uint32_t); 99 100 /* 101 * Local routines 102 */ 103 static boolean_t e1000g_reset_adapter(struct e1000g *); 104 static void e1000g_tx_clean(struct e1000g *); 105 static void e1000g_rx_clean(struct e1000g *); 106 static void e1000g_link_timer(void *); 107 static void e1000g_local_timer(void *); 108 static boolean_t e1000g_link_check(struct e1000g *); 109 static boolean_t e1000g_stall_check(struct e1000g *); 110 static void e1000g_smartspeed(struct e1000g *); 111 static void e1000g_get_conf(struct e1000g *); 112 static boolean_t e1000g_get_prop(struct e1000g *, char *, int, int, int, 113 int *); 114 static void enable_watchdog_timer(struct e1000g *); 115 static void disable_watchdog_timer(struct e1000g *); 116 static void start_watchdog_timer(struct e1000g *); 117 static void restart_watchdog_timer(struct e1000g *); 118 static void stop_watchdog_timer(struct e1000g *); 119 static void stop_link_timer(struct e1000g *); 120 static void stop_82547_timer(e1000g_tx_ring_t *); 121 static void e1000g_force_speed_duplex(struct e1000g *); 122 static void e1000g_setup_max_mtu(struct e1000g *); 123 static void e1000g_get_max_frame_size(struct e1000g *); 124 static boolean_t is_valid_mac_addr(uint8_t *); 125 static void e1000g_unattach(dev_info_t *, struct e1000g *); 126 static int e1000g_get_bar_info(dev_info_t *, int, bar_info_t *); 127 #ifdef E1000G_DEBUG 128 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 129 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 130 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 131 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 132 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 133 struct iocblk *, mblk_t *); 134 #endif 135 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 136 struct iocblk *, mblk_t *); 137 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 138 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 139 static void e1000g_set_internal_loopback(struct e1000g *); 140 static void e1000g_set_external_loopback_1000(struct e1000g *); 141 static void e1000g_set_external_loopback_100(struct e1000g *); 142 static void e1000g_set_external_loopback_10(struct e1000g *); 143 static int e1000g_add_intrs(struct e1000g *); 144 static int e1000g_intr_add(struct e1000g *, int); 145 static int e1000g_rem_intrs(struct e1000g *); 146 static int e1000g_enable_intrs(struct e1000g *); 147 static int e1000g_disable_intrs(struct e1000g *); 148 static boolean_t e1000g_link_up(struct e1000g *); 149 #ifdef __sparc 150 static boolean_t e1000g_find_mac_address(struct e1000g *); 151 #endif 152 static void e1000g_get_phy_state(struct e1000g *); 153 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 154 const void *impl_data); 155 static void e1000g_fm_init(struct e1000g *Adapter); 156 static void e1000g_fm_fini(struct e1000g *Adapter); 157 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 158 static void e1000g_param_sync(struct e1000g *); 159 static void e1000g_get_driver_control(struct e1000_hw *); 160 static void e1000g_release_driver_control(struct e1000_hw *); 161 static void e1000g_restore_promisc(struct e1000g *Adapter); 162 163 mac_priv_prop_t e1000g_priv_props[] = { 164 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 165 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 166 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 167 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 168 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 169 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 170 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 171 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 172 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 173 {"_intr_adaptive", MAC_PROP_PERM_RW}, 174 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 175 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 176 }; 177 #define E1000G_MAX_PRIV_PROPS \ 178 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 179 180 181 static struct cb_ops cb_ws_ops = { 182 nulldev, /* cb_open */ 183 nulldev, /* cb_close */ 184 nodev, /* cb_strategy */ 185 nodev, /* cb_print */ 186 nodev, /* cb_dump */ 187 nodev, /* cb_read */ 188 nodev, /* cb_write */ 189 nodev, /* cb_ioctl */ 190 nodev, /* cb_devmap */ 191 nodev, /* cb_mmap */ 192 nodev, /* cb_segmap */ 193 nochpoll, /* cb_chpoll */ 194 ddi_prop_op, /* cb_prop_op */ 195 NULL, /* cb_stream */ 196 D_MP | D_HOTPLUG, /* cb_flag */ 197 CB_REV, /* cb_rev */ 198 nodev, /* cb_aread */ 199 nodev /* cb_awrite */ 200 }; 201 202 static struct dev_ops ws_ops = { 203 DEVO_REV, /* devo_rev */ 204 0, /* devo_refcnt */ 205 NULL, /* devo_getinfo */ 206 nulldev, /* devo_identify */ 207 nulldev, /* devo_probe */ 208 e1000g_attach, /* devo_attach */ 209 e1000g_detach, /* devo_detach */ 210 nodev, /* devo_reset */ 211 &cb_ws_ops, /* devo_cb_ops */ 212 NULL, /* devo_bus_ops */ 213 ddi_power, /* devo_power */ 214 e1000g_quiesce /* devo_quiesce */ 215 }; 216 217 static struct modldrv modldrv = { 218 &mod_driverops, /* Type of module. This one is a driver */ 219 ident, /* Discription string */ 220 &ws_ops, /* driver ops */ 221 }; 222 223 static struct modlinkage modlinkage = { 224 MODREV_1, &modldrv, NULL 225 }; 226 227 /* Access attributes for register mapping */ 228 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 229 DDI_DEVICE_ATTR_V1, 230 DDI_STRUCTURE_LE_ACC, 231 DDI_STRICTORDER_ACC, 232 DDI_FLAGERR_ACC 233 }; 234 235 #define E1000G_M_CALLBACK_FLAGS \ 236 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 237 238 static mac_callbacks_t e1000g_m_callbacks = { 239 E1000G_M_CALLBACK_FLAGS, 240 e1000g_m_stat, 241 e1000g_m_start, 242 e1000g_m_stop, 243 e1000g_m_promisc, 244 e1000g_m_multicst, 245 NULL, 246 e1000g_m_tx, 247 e1000g_m_ioctl, 248 e1000g_m_getcapab, 249 NULL, 250 NULL, 251 e1000g_m_setprop, 252 e1000g_m_getprop 253 }; 254 255 /* 256 * Global variables 257 */ 258 uint32_t e1000g_mblks_pending = 0; 259 /* 260 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 261 * Here we maintain a private dev_info list if e1000g_force_detach is 262 * enabled. If we force the driver to detach while there are still some 263 * rx buffers retained in the upper layer, we have to keep a copy of the 264 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 265 * structure will be freed after the driver is detached. However when we 266 * finally free those rx buffers released by the upper layer, we need to 267 * refer to the dev_info to free the dma buffers. So we save a copy of 268 * the dev_info for this purpose. On x86 platform, we assume this copy 269 * of dev_info is always valid, but on SPARC platform, it could be invalid 270 * after the system board level DR operation. For this reason, the global 271 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 272 */ 273 #ifdef __sparc 274 boolean_t e1000g_force_detach = B_FALSE; 275 #else 276 boolean_t e1000g_force_detach = B_TRUE; 277 #endif 278 private_devi_list_t *e1000g_private_devi_list = NULL; 279 280 /* 281 * The mutex e1000g_rx_detach_lock is defined to protect the processing of 282 * the private dev_info list, and to serialize the processing of rx buffer 283 * freeing and rx buffer recycling. 284 */ 285 kmutex_t e1000g_rx_detach_lock; 286 /* 287 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 288 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 289 * If there are many e1000g instances, the system may run out of DVMA 290 * resources during the initialization of the instances, then the flag will 291 * be changed to "USE_DMA". Because different e1000g instances are initialized 292 * in parallel, we need to use this lock to protect the flag. 293 */ 294 krwlock_t e1000g_dma_type_lock; 295 296 /* 297 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 298 * Based on the information from Intel, the 82546 chipset has some hardware 299 * problem. When one port is being reset and the other port is trying to 300 * access the eeprom, it could cause system hang or panic. To workaround this 301 * hardware problem, we use a global mutex to prevent such operations from 302 * happening simultaneously on different instances. This workaround is applied 303 * to all the devices supported by this driver. 304 */ 305 kmutex_t e1000g_nvm_lock; 306 307 /* 308 * Loadable module configuration entry points for the driver 309 */ 310 311 /* 312 * _init - module initialization 313 */ 314 int 315 _init(void) 316 { 317 int status; 318 319 mac_init_ops(&ws_ops, WSNAME); 320 status = mod_install(&modlinkage); 321 if (status != DDI_SUCCESS) 322 mac_fini_ops(&ws_ops); 323 else { 324 mutex_init(&e1000g_rx_detach_lock, NULL, MUTEX_DRIVER, NULL); 325 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 326 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 327 } 328 329 return (status); 330 } 331 332 /* 333 * _fini - module finalization 334 */ 335 int 336 _fini(void) 337 { 338 int status; 339 340 if (e1000g_mblks_pending != 0) 341 return (EBUSY); 342 343 status = mod_remove(&modlinkage); 344 if (status == DDI_SUCCESS) { 345 mac_fini_ops(&ws_ops); 346 347 if (e1000g_force_detach) { 348 private_devi_list_t *devi_node; 349 350 mutex_enter(&e1000g_rx_detach_lock); 351 while (e1000g_private_devi_list != NULL) { 352 devi_node = e1000g_private_devi_list; 353 e1000g_private_devi_list = 354 e1000g_private_devi_list->next; 355 356 kmem_free(devi_node->priv_dip, 357 sizeof (struct dev_info)); 358 kmem_free(devi_node, 359 sizeof (private_devi_list_t)); 360 } 361 mutex_exit(&e1000g_rx_detach_lock); 362 } 363 364 mutex_destroy(&e1000g_rx_detach_lock); 365 rw_destroy(&e1000g_dma_type_lock); 366 mutex_destroy(&e1000g_nvm_lock); 367 } 368 369 return (status); 370 } 371 372 /* 373 * _info - module information 374 */ 375 int 376 _info(struct modinfo *modinfop) 377 { 378 return (mod_info(&modlinkage, modinfop)); 379 } 380 381 /* 382 * e1000g_attach - driver attach 383 * 384 * This function is the device-specific initialization entry 385 * point. This entry point is required and must be written. 386 * The DDI_ATTACH command must be provided in the attach entry 387 * point. When attach() is called with cmd set to DDI_ATTACH, 388 * all normal kernel services (such as kmem_alloc(9F)) are 389 * available for use by the driver. 390 * 391 * The attach() function will be called once for each instance 392 * of the device on the system with cmd set to DDI_ATTACH. 393 * Until attach() succeeds, the only driver entry points which 394 * may be called are open(9E) and getinfo(9E). 395 */ 396 static int 397 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 398 { 399 struct e1000g *Adapter; 400 struct e1000_hw *hw; 401 struct e1000g_osdep *osdep; 402 int instance; 403 404 switch (cmd) { 405 default: 406 e1000g_log(NULL, CE_WARN, 407 "Unsupported command send to e1000g_attach... "); 408 return (DDI_FAILURE); 409 410 case DDI_RESUME: 411 return (e1000g_resume(devinfo)); 412 413 case DDI_ATTACH: 414 break; 415 } 416 417 /* 418 * get device instance number 419 */ 420 instance = ddi_get_instance(devinfo); 421 422 /* 423 * Allocate soft data structure 424 */ 425 Adapter = 426 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 427 428 Adapter->dip = devinfo; 429 Adapter->instance = instance; 430 Adapter->tx_ring->adapter = Adapter; 431 Adapter->rx_ring->adapter = Adapter; 432 433 hw = &Adapter->shared; 434 osdep = &Adapter->osdep; 435 hw->back = osdep; 436 osdep->adapter = Adapter; 437 438 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 439 440 /* 441 * Initialize for fma support 442 */ 443 (void) e1000g_get_prop(Adapter, "fm-capable", 444 0, 0x0f, 445 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 446 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE, 447 &Adapter->fm_capabilities); 448 e1000g_fm_init(Adapter); 449 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 450 451 /* 452 * PCI Configure 453 */ 454 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 455 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 456 goto attach_fail; 457 } 458 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 459 460 /* 461 * Setup hardware 462 */ 463 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 464 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 465 goto attach_fail; 466 } 467 468 /* 469 * Map in the device registers. 470 */ 471 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 472 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 473 goto attach_fail; 474 } 475 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 476 477 /* 478 * Initialize driver parameters 479 */ 480 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 481 goto attach_fail; 482 } 483 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 484 485 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 486 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 487 goto attach_fail; 488 } 489 490 /* 491 * Initialize interrupts 492 */ 493 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 494 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 495 goto attach_fail; 496 } 497 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 498 499 /* 500 * Initialize mutex's for this device. 501 * Do this before enabling the interrupt handler and 502 * register the softint to avoid the condition where 503 * interrupt handler can try using uninitialized mutex 504 */ 505 e1000g_init_locks(Adapter); 506 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 507 508 /* 509 * Initialize Driver Counters 510 */ 511 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 512 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 513 goto attach_fail; 514 } 515 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 516 517 /* 518 * Initialize chip hardware and software structures 519 */ 520 rw_enter(&Adapter->chip_lock, RW_WRITER); 521 if (e1000g_init(Adapter) != DDI_SUCCESS) { 522 rw_exit(&Adapter->chip_lock); 523 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 524 goto attach_fail; 525 } 526 rw_exit(&Adapter->chip_lock); 527 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 528 529 /* 530 * Register the driver to the MAC 531 */ 532 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 533 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 534 goto attach_fail; 535 } 536 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 537 538 /* 539 * Now that mutex locks are initialized, and the chip is also 540 * initialized, enable interrupts. 541 */ 542 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 543 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 544 goto attach_fail; 545 } 546 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 547 548 /* 549 * If e1000g_force_detach is enabled, in global private dip list, 550 * we will create a new entry, which maintains the priv_dip for DR 551 * supports after driver detached. 552 */ 553 if (e1000g_force_detach) { 554 private_devi_list_t *devi_node; 555 556 Adapter->priv_dip = 557 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 558 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 559 sizeof (struct dev_info)); 560 561 devi_node = 562 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 563 564 mutex_enter(&e1000g_rx_detach_lock); 565 devi_node->priv_dip = Adapter->priv_dip; 566 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 567 devi_node->pending_rx_count = 0; 568 569 Adapter->priv_devi_node = devi_node; 570 571 if (e1000g_private_devi_list == NULL) { 572 devi_node->prev = NULL; 573 devi_node->next = NULL; 574 e1000g_private_devi_list = devi_node; 575 } else { 576 devi_node->prev = NULL; 577 devi_node->next = e1000g_private_devi_list; 578 e1000g_private_devi_list->prev = devi_node; 579 e1000g_private_devi_list = devi_node; 580 } 581 mutex_exit(&e1000g_rx_detach_lock); 582 } 583 584 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 585 Adapter->e1000g_state = E1000G_INITIALIZED; 586 587 return (DDI_SUCCESS); 588 589 attach_fail: 590 e1000g_unattach(devinfo, Adapter); 591 return (DDI_FAILURE); 592 } 593 594 static int 595 e1000g_register_mac(struct e1000g *Adapter) 596 { 597 struct e1000_hw *hw = &Adapter->shared; 598 mac_register_t *mac; 599 int err; 600 601 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 602 return (DDI_FAILURE); 603 604 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 605 mac->m_driver = Adapter; 606 mac->m_dip = Adapter->dip; 607 mac->m_src_addr = hw->mac.addr; 608 mac->m_callbacks = &e1000g_m_callbacks; 609 mac->m_min_sdu = 0; 610 mac->m_max_sdu = Adapter->default_mtu; 611 mac->m_margin = VLAN_TAGSZ; 612 mac->m_priv_props = e1000g_priv_props; 613 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 614 mac->m_v12n = MAC_VIRT_LEVEL1; 615 616 err = mac_register(mac, &Adapter->mh); 617 mac_free(mac); 618 619 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 620 } 621 622 static int 623 e1000g_identify_hardware(struct e1000g *Adapter) 624 { 625 struct e1000_hw *hw = &Adapter->shared; 626 struct e1000g_osdep *osdep = &Adapter->osdep; 627 628 /* Get the device id */ 629 hw->vendor_id = 630 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 631 hw->device_id = 632 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 633 hw->revision_id = 634 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 635 hw->subsystem_device_id = 636 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 637 hw->subsystem_vendor_id = 638 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 639 640 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 641 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 642 "MAC type could not be set properly."); 643 return (DDI_FAILURE); 644 } 645 646 return (DDI_SUCCESS); 647 } 648 649 static int 650 e1000g_regs_map(struct e1000g *Adapter) 651 { 652 dev_info_t *devinfo = Adapter->dip; 653 struct e1000_hw *hw = &Adapter->shared; 654 struct e1000g_osdep *osdep = &Adapter->osdep; 655 off_t mem_size; 656 bar_info_t bar_info; 657 int offset, rnumber; 658 659 rnumber = ADAPTER_REG_SET; 660 /* Get size of adapter register memory */ 661 if (ddi_dev_regsize(devinfo, rnumber, &mem_size) != 662 DDI_SUCCESS) { 663 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 664 "ddi_dev_regsize for registers failed"); 665 return (DDI_FAILURE); 666 } 667 668 /* Map adapter register memory */ 669 if ((ddi_regs_map_setup(devinfo, rnumber, 670 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 671 &osdep->reg_handle)) != DDI_SUCCESS) { 672 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 673 "ddi_regs_map_setup for registers failed"); 674 goto regs_map_fail; 675 } 676 677 /* ICH needs to map flash memory */ 678 switch (hw->mac.type) { 679 case e1000_ich8lan: 680 case e1000_ich9lan: 681 case e1000_ich10lan: 682 case e1000_pchlan: 683 rnumber = ICH_FLASH_REG_SET; 684 685 /* get flash size */ 686 if (ddi_dev_regsize(devinfo, rnumber, 687 &mem_size) != DDI_SUCCESS) { 688 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 689 "ddi_dev_regsize for ICH flash failed"); 690 goto regs_map_fail; 691 } 692 693 /* map flash in */ 694 if (ddi_regs_map_setup(devinfo, rnumber, 695 (caddr_t *)&hw->flash_address, 0, 696 mem_size, &e1000g_regs_acc_attr, 697 &osdep->ich_flash_handle) != DDI_SUCCESS) { 698 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 699 "ddi_regs_map_setup for ICH flash failed"); 700 goto regs_map_fail; 701 } 702 break; 703 default: 704 break; 705 } 706 707 /* map io space */ 708 switch (hw->mac.type) { 709 case e1000_82544: 710 case e1000_82540: 711 case e1000_82545: 712 case e1000_82546: 713 case e1000_82541: 714 case e1000_82541_rev_2: 715 /* find the IO bar */ 716 rnumber = -1; 717 for (offset = PCI_CONF_BASE1; 718 offset <= PCI_CONF_BASE5; offset += 4) { 719 if (e1000g_get_bar_info(devinfo, offset, &bar_info) 720 != DDI_SUCCESS) 721 continue; 722 if (bar_info.type == E1000G_BAR_IO) { 723 rnumber = bar_info.rnumber; 724 break; 725 } 726 } 727 728 if (rnumber < 0) { 729 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 730 "No io space is found"); 731 goto regs_map_fail; 732 } 733 734 /* get io space size */ 735 if (ddi_dev_regsize(devinfo, rnumber, 736 &mem_size) != DDI_SUCCESS) { 737 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 738 "ddi_dev_regsize for io space failed"); 739 goto regs_map_fail; 740 } 741 742 /* map io space */ 743 if ((ddi_regs_map_setup(devinfo, rnumber, 744 (caddr_t *)&hw->io_base, 0, mem_size, 745 &e1000g_regs_acc_attr, 746 &osdep->io_reg_handle)) != DDI_SUCCESS) { 747 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 748 "ddi_regs_map_setup for io space failed"); 749 goto regs_map_fail; 750 } 751 break; 752 default: 753 hw->io_base = 0; 754 break; 755 } 756 757 return (DDI_SUCCESS); 758 759 regs_map_fail: 760 if (osdep->reg_handle != NULL) 761 ddi_regs_map_free(&osdep->reg_handle); 762 if (osdep->ich_flash_handle != NULL) 763 ddi_regs_map_free(&osdep->ich_flash_handle); 764 return (DDI_FAILURE); 765 } 766 767 static int 768 e1000g_set_driver_params(struct e1000g *Adapter) 769 { 770 struct e1000_hw *hw; 771 772 hw = &Adapter->shared; 773 774 /* Set MAC type and initialize hardware functions */ 775 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 776 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 777 "Could not setup hardware functions"); 778 return (DDI_FAILURE); 779 } 780 781 /* Get bus information */ 782 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 783 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 784 "Could not get bus information"); 785 return (DDI_FAILURE); 786 } 787 788 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 789 790 hw->mac.autoneg_failed = B_TRUE; 791 792 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 793 hw->phy.autoneg_wait_to_complete = B_FALSE; 794 795 /* Adaptive IFS related changes */ 796 hw->mac.adaptive_ifs = B_TRUE; 797 798 /* Enable phy init script for IGP phy of 82541/82547 */ 799 if ((hw->mac.type == e1000_82547) || 800 (hw->mac.type == e1000_82541) || 801 (hw->mac.type == e1000_82547_rev_2) || 802 (hw->mac.type == e1000_82541_rev_2)) 803 e1000_init_script_state_82541(hw, B_TRUE); 804 805 /* Enable the TTL workaround for 82541/82547 */ 806 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 807 808 #ifdef __sparc 809 Adapter->strip_crc = B_TRUE; 810 #else 811 Adapter->strip_crc = B_FALSE; 812 #endif 813 814 /* setup the maximum MTU size of the chip */ 815 e1000g_setup_max_mtu(Adapter); 816 817 /* Get speed/duplex settings in conf file */ 818 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 819 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 820 e1000g_force_speed_duplex(Adapter); 821 822 /* Get Jumbo Frames settings in conf file */ 823 e1000g_get_max_frame_size(Adapter); 824 825 /* Get conf file properties */ 826 e1000g_get_conf(Adapter); 827 828 /* enforce PCH limits */ 829 e1000g_pch_limits(Adapter); 830 831 /* Set Rx/Tx buffer size */ 832 e1000g_set_bufsize(Adapter); 833 834 /* Master Latency Timer */ 835 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 836 837 /* copper options */ 838 if (hw->phy.media_type == e1000_media_type_copper) { 839 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 840 hw->phy.disable_polarity_correction = B_FALSE; 841 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 842 } 843 844 /* The initial link state should be "unknown" */ 845 Adapter->link_state = LINK_STATE_UNKNOWN; 846 847 /* Initialize rx parameters */ 848 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 849 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 850 851 /* Initialize tx parameters */ 852 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 853 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 854 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 855 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 856 857 /* Initialize rx parameters */ 858 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 859 860 return (DDI_SUCCESS); 861 } 862 863 static void 864 e1000g_setup_max_mtu(struct e1000g *Adapter) 865 { 866 struct e1000_mac_info *mac = &Adapter->shared.mac; 867 struct e1000_phy_info *phy = &Adapter->shared.phy; 868 869 switch (mac->type) { 870 /* types that do not support jumbo frames */ 871 case e1000_ich8lan: 872 case e1000_82573: 873 case e1000_82583: 874 Adapter->max_mtu = ETHERMTU; 875 break; 876 /* ich9 supports jumbo frames except on one phy type */ 877 case e1000_ich9lan: 878 if (phy->type == e1000_phy_ife) 879 Adapter->max_mtu = ETHERMTU; 880 else 881 Adapter->max_mtu = MAXIMUM_MTU_9K; 882 break; 883 /* pch can do jumbo frames up to 4K */ 884 case e1000_pchlan: 885 Adapter->max_mtu = MAXIMUM_MTU_4K; 886 break; 887 /* types with a special limit */ 888 case e1000_82571: 889 case e1000_82572: 890 case e1000_82574: 891 case e1000_80003es2lan: 892 case e1000_ich10lan: 893 Adapter->max_mtu = MAXIMUM_MTU_9K; 894 break; 895 /* default limit is 16K */ 896 default: 897 Adapter->max_mtu = FRAME_SIZE_UPTO_16K - 898 sizeof (struct ether_vlan_header) - ETHERFCSL - 899 E1000G_IPALIGNPRESERVEROOM; 900 break; 901 } 902 } 903 904 static void 905 e1000g_set_bufsize(struct e1000g *Adapter) 906 { 907 struct e1000_mac_info *mac = &Adapter->shared.mac; 908 uint64_t rx_size; 909 uint64_t tx_size; 910 911 dev_info_t *devinfo = Adapter->dip; 912 #ifdef __sparc 913 ulong_t iommu_pagesize; 914 #endif 915 /* Get the system page size */ 916 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 917 918 #ifdef __sparc 919 iommu_pagesize = dvma_pagesize(devinfo); 920 if (iommu_pagesize != 0) { 921 if (Adapter->sys_page_sz == iommu_pagesize) { 922 if (iommu_pagesize > 0x4000) 923 Adapter->sys_page_sz = 0x4000; 924 } else { 925 if (Adapter->sys_page_sz > iommu_pagesize) 926 Adapter->sys_page_sz = iommu_pagesize; 927 } 928 } 929 if (Adapter->lso_enable) { 930 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 931 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 932 } else { 933 Adapter->dvma_page_num = Adapter->max_frame_size / 934 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 935 } 936 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 937 #endif 938 939 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 940 941 if (Adapter->mem_workaround_82546 && 942 ((mac->type == e1000_82545) || 943 (mac->type == e1000_82546) || 944 (mac->type == e1000_82546_rev_3))) { 945 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 946 } else { 947 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 948 if ((rx_size > FRAME_SIZE_UPTO_2K) && 949 (rx_size <= FRAME_SIZE_UPTO_4K)) 950 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 951 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 952 (rx_size <= FRAME_SIZE_UPTO_8K)) 953 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 954 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 955 (rx_size <= FRAME_SIZE_UPTO_16K)) 956 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 957 else 958 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 959 } 960 961 tx_size = Adapter->max_frame_size; 962 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 963 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 964 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 965 (tx_size <= FRAME_SIZE_UPTO_8K)) 966 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 967 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 968 (tx_size <= FRAME_SIZE_UPTO_16K)) 969 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 970 else 971 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 972 973 /* 974 * For Wiseman adapters we have an requirement of having receive 975 * buffers aligned at 256 byte boundary. Since Livengood does not 976 * require this and forcing it for all hardwares will have 977 * performance implications, I am making it applicable only for 978 * Wiseman and for Jumbo frames enabled mode as rest of the time, 979 * it is okay to have normal frames...but it does involve a 980 * potential risk where we may loose data if buffer is not 981 * aligned...so all wiseman boards to have 256 byte aligned 982 * buffers 983 */ 984 if (mac->type < e1000_82543) 985 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 986 else 987 Adapter->rx_buf_align = 1; 988 } 989 990 /* 991 * e1000g_detach - driver detach 992 * 993 * The detach() function is the complement of the attach routine. 994 * If cmd is set to DDI_DETACH, detach() is used to remove the 995 * state associated with a given instance of a device node 996 * prior to the removal of that instance from the system. 997 * 998 * The detach() function will be called once for each instance 999 * of the device for which there has been a successful attach() 1000 * once there are no longer any opens on the device. 1001 * 1002 * Interrupts routine are disabled, All memory allocated by this 1003 * driver are freed. 1004 */ 1005 static int 1006 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 1007 { 1008 struct e1000g *Adapter; 1009 boolean_t rx_drain; 1010 1011 switch (cmd) { 1012 default: 1013 return (DDI_FAILURE); 1014 1015 case DDI_SUSPEND: 1016 return (e1000g_suspend(devinfo)); 1017 1018 case DDI_DETACH: 1019 break; 1020 } 1021 1022 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1023 if (Adapter == NULL) 1024 return (DDI_FAILURE); 1025 1026 rx_drain = e1000g_rx_drain(Adapter); 1027 if (!rx_drain && !e1000g_force_detach) 1028 return (DDI_FAILURE); 1029 1030 if (mac_unregister(Adapter->mh) != 0) { 1031 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 1032 return (DDI_FAILURE); 1033 } 1034 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 1035 1036 ASSERT(!(Adapter->e1000g_state & E1000G_STARTED)); 1037 1038 if (!e1000g_force_detach && !rx_drain) 1039 return (DDI_FAILURE); 1040 1041 e1000g_unattach(devinfo, Adapter); 1042 1043 return (DDI_SUCCESS); 1044 } 1045 1046 /* 1047 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 1048 */ 1049 void 1050 e1000g_free_priv_devi_node(private_devi_list_t *devi_node) 1051 { 1052 ASSERT(e1000g_private_devi_list != NULL); 1053 ASSERT(devi_node != NULL); 1054 1055 if (devi_node->prev != NULL) 1056 devi_node->prev->next = devi_node->next; 1057 if (devi_node->next != NULL) 1058 devi_node->next->prev = devi_node->prev; 1059 if (devi_node == e1000g_private_devi_list) 1060 e1000g_private_devi_list = devi_node->next; 1061 1062 kmem_free(devi_node->priv_dip, 1063 sizeof (struct dev_info)); 1064 kmem_free(devi_node, 1065 sizeof (private_devi_list_t)); 1066 } 1067 1068 static void 1069 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1070 { 1071 private_devi_list_t *devi_node; 1072 int result; 1073 1074 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1075 (void) e1000g_disable_intrs(Adapter); 1076 } 1077 1078 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1079 (void) mac_unregister(Adapter->mh); 1080 } 1081 1082 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1083 (void) e1000g_rem_intrs(Adapter); 1084 } 1085 1086 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1087 (void) ddi_prop_remove_all(devinfo); 1088 } 1089 1090 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1091 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1092 } 1093 1094 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1095 stop_link_timer(Adapter); 1096 1097 mutex_enter(&e1000g_nvm_lock); 1098 result = e1000_reset_hw(&Adapter->shared); 1099 mutex_exit(&e1000g_nvm_lock); 1100 1101 if (result != E1000_SUCCESS) { 1102 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1103 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1104 } 1105 } 1106 1107 e1000g_release_multicast(Adapter); 1108 1109 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1110 if (Adapter->osdep.reg_handle != NULL) 1111 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1112 if (Adapter->osdep.ich_flash_handle != NULL) 1113 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1114 if (Adapter->osdep.io_reg_handle != NULL) 1115 ddi_regs_map_free(&Adapter->osdep.io_reg_handle); 1116 } 1117 1118 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1119 if (Adapter->osdep.cfg_handle != NULL) 1120 pci_config_teardown(&Adapter->osdep.cfg_handle); 1121 } 1122 1123 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1124 e1000g_destroy_locks(Adapter); 1125 } 1126 1127 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1128 e1000g_fm_fini(Adapter); 1129 } 1130 1131 mutex_enter(&e1000g_rx_detach_lock); 1132 if (e1000g_force_detach && (Adapter->priv_devi_node != NULL)) { 1133 devi_node = Adapter->priv_devi_node; 1134 devi_node->flag |= E1000G_PRIV_DEVI_DETACH; 1135 1136 if (devi_node->pending_rx_count == 0) { 1137 e1000g_free_priv_devi_node(devi_node); 1138 } 1139 } 1140 mutex_exit(&e1000g_rx_detach_lock); 1141 1142 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1143 1144 /* 1145 * Another hotplug spec requirement, 1146 * run ddi_set_driver_private(devinfo, null); 1147 */ 1148 ddi_set_driver_private(devinfo, NULL); 1149 } 1150 1151 /* 1152 * Get the BAR type and rnumber for a given PCI BAR offset 1153 */ 1154 static int 1155 e1000g_get_bar_info(dev_info_t *dip, int bar_offset, bar_info_t *bar_info) 1156 { 1157 pci_regspec_t *regs; 1158 uint_t regs_length; 1159 int type, rnumber; 1160 1161 ASSERT((bar_offset >= PCI_CONF_BASE0) && 1162 (bar_offset <= PCI_CONF_BASE5)); 1163 1164 /* 1165 * Get the DDI "reg" property 1166 */ 1167 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 1168 DDI_PROP_DONTPASS, "reg", (int **)®s, 1169 ®s_length) != DDI_PROP_SUCCESS) { 1170 return (DDI_FAILURE); 1171 } 1172 1173 /* 1174 * Check the BAR offset 1175 */ 1176 for (rnumber = 0; rnumber < regs_length; ++rnumber) { 1177 if (PCI_REG_REG_G(regs[rnumber].pci_phys_hi) == bar_offset) { 1178 type = regs[rnumber].pci_phys_hi & PCI_ADDR_MASK; 1179 break; 1180 } 1181 } 1182 1183 ddi_prop_free(regs); 1184 1185 if (rnumber >= regs_length) 1186 return (DDI_FAILURE); 1187 1188 switch (type) { 1189 case PCI_ADDR_CONFIG: 1190 bar_info->type = E1000G_BAR_CONFIG; 1191 break; 1192 case PCI_ADDR_IO: 1193 bar_info->type = E1000G_BAR_IO; 1194 break; 1195 case PCI_ADDR_MEM32: 1196 bar_info->type = E1000G_BAR_MEM32; 1197 break; 1198 case PCI_ADDR_MEM64: 1199 bar_info->type = E1000G_BAR_MEM64; 1200 break; 1201 default: 1202 return (DDI_FAILURE); 1203 } 1204 bar_info->rnumber = rnumber; 1205 return (DDI_SUCCESS); 1206 } 1207 1208 static void 1209 e1000g_init_locks(struct e1000g *Adapter) 1210 { 1211 e1000g_tx_ring_t *tx_ring; 1212 e1000g_rx_ring_t *rx_ring; 1213 1214 rw_init(&Adapter->chip_lock, NULL, 1215 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1216 mutex_init(&Adapter->link_lock, NULL, 1217 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1218 mutex_init(&Adapter->watchdog_lock, NULL, 1219 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1220 1221 tx_ring = Adapter->tx_ring; 1222 1223 mutex_init(&tx_ring->tx_lock, NULL, 1224 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1225 mutex_init(&tx_ring->usedlist_lock, NULL, 1226 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1227 mutex_init(&tx_ring->freelist_lock, NULL, 1228 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1229 1230 rx_ring = Adapter->rx_ring; 1231 1232 mutex_init(&rx_ring->rx_lock, NULL, 1233 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1234 } 1235 1236 static void 1237 e1000g_destroy_locks(struct e1000g *Adapter) 1238 { 1239 e1000g_tx_ring_t *tx_ring; 1240 e1000g_rx_ring_t *rx_ring; 1241 1242 tx_ring = Adapter->tx_ring; 1243 mutex_destroy(&tx_ring->tx_lock); 1244 mutex_destroy(&tx_ring->usedlist_lock); 1245 mutex_destroy(&tx_ring->freelist_lock); 1246 1247 rx_ring = Adapter->rx_ring; 1248 mutex_destroy(&rx_ring->rx_lock); 1249 1250 mutex_destroy(&Adapter->link_lock); 1251 mutex_destroy(&Adapter->watchdog_lock); 1252 rw_destroy(&Adapter->chip_lock); 1253 1254 /* destory mutex initialized in shared code */ 1255 e1000_destroy_hw_mutex(&Adapter->shared); 1256 } 1257 1258 static int 1259 e1000g_resume(dev_info_t *devinfo) 1260 { 1261 struct e1000g *Adapter; 1262 1263 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1264 if (Adapter == NULL) 1265 e1000g_log(Adapter, CE_PANIC, 1266 "Instance pointer is null\n"); 1267 1268 if (Adapter->dip != devinfo) 1269 e1000g_log(Adapter, CE_PANIC, 1270 "Devinfo is not the same as saved devinfo\n"); 1271 1272 rw_enter(&Adapter->chip_lock, RW_WRITER); 1273 1274 if (Adapter->e1000g_state & E1000G_STARTED) { 1275 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1276 rw_exit(&Adapter->chip_lock); 1277 /* 1278 * We note the failure, but return success, as the 1279 * system is still usable without this controller. 1280 */ 1281 e1000g_log(Adapter, CE_WARN, 1282 "e1000g_resume: failed to restart controller\n"); 1283 return (DDI_SUCCESS); 1284 } 1285 /* Enable and start the watchdog timer */ 1286 enable_watchdog_timer(Adapter); 1287 } 1288 1289 Adapter->e1000g_state &= ~E1000G_SUSPENDED; 1290 1291 rw_exit(&Adapter->chip_lock); 1292 1293 return (DDI_SUCCESS); 1294 } 1295 1296 static int 1297 e1000g_suspend(dev_info_t *devinfo) 1298 { 1299 struct e1000g *Adapter; 1300 1301 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1302 if (Adapter == NULL) 1303 return (DDI_FAILURE); 1304 1305 rw_enter(&Adapter->chip_lock, RW_WRITER); 1306 1307 Adapter->e1000g_state |= E1000G_SUSPENDED; 1308 1309 /* if the port isn't plumbed, we can simply return */ 1310 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 1311 rw_exit(&Adapter->chip_lock); 1312 return (DDI_SUCCESS); 1313 } 1314 1315 e1000g_stop(Adapter, B_FALSE); 1316 1317 rw_exit(&Adapter->chip_lock); 1318 1319 /* Disable and stop all the timers */ 1320 disable_watchdog_timer(Adapter); 1321 stop_link_timer(Adapter); 1322 stop_82547_timer(Adapter->tx_ring); 1323 1324 return (DDI_SUCCESS); 1325 } 1326 1327 static int 1328 e1000g_init(struct e1000g *Adapter) 1329 { 1330 uint32_t pba; 1331 uint32_t high_water; 1332 struct e1000_hw *hw; 1333 clock_t link_timeout; 1334 int result; 1335 1336 hw = &Adapter->shared; 1337 1338 /* 1339 * reset to put the hardware in a known state 1340 * before we try to do anything with the eeprom 1341 */ 1342 mutex_enter(&e1000g_nvm_lock); 1343 result = e1000_reset_hw(hw); 1344 mutex_exit(&e1000g_nvm_lock); 1345 1346 if (result != E1000_SUCCESS) { 1347 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1348 goto init_fail; 1349 } 1350 1351 mutex_enter(&e1000g_nvm_lock); 1352 result = e1000_validate_nvm_checksum(hw); 1353 if (result < E1000_SUCCESS) { 1354 /* 1355 * Some PCI-E parts fail the first check due to 1356 * the link being in sleep state. Call it again, 1357 * if it fails a second time its a real issue. 1358 */ 1359 result = e1000_validate_nvm_checksum(hw); 1360 } 1361 mutex_exit(&e1000g_nvm_lock); 1362 1363 if (result < E1000_SUCCESS) { 1364 e1000g_log(Adapter, CE_WARN, 1365 "Invalid NVM checksum. Please contact " 1366 "the vendor to update the NVM."); 1367 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1368 goto init_fail; 1369 } 1370 1371 result = 0; 1372 #ifdef __sparc 1373 /* 1374 * First, we try to get the local ethernet address from OBP. If 1375 * failed, then we get it from the EEPROM of NIC card. 1376 */ 1377 result = e1000g_find_mac_address(Adapter); 1378 #endif 1379 /* Get the local ethernet address. */ 1380 if (!result) { 1381 mutex_enter(&e1000g_nvm_lock); 1382 result = e1000_read_mac_addr(hw); 1383 mutex_exit(&e1000g_nvm_lock); 1384 } 1385 1386 if (result < E1000_SUCCESS) { 1387 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1388 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1389 goto init_fail; 1390 } 1391 1392 /* check for valid mac address */ 1393 if (!is_valid_mac_addr(hw->mac.addr)) { 1394 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1395 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1396 goto init_fail; 1397 } 1398 1399 /* Set LAA state for 82571 chipset */ 1400 e1000_set_laa_state_82571(hw, B_TRUE); 1401 1402 /* Master Latency Timer implementation */ 1403 if (Adapter->master_latency_timer) { 1404 pci_config_put8(Adapter->osdep.cfg_handle, 1405 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1406 } 1407 1408 if (hw->mac.type < e1000_82547) { 1409 /* 1410 * Total FIFO is 64K 1411 */ 1412 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1413 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1414 else 1415 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1416 } else if ((hw->mac.type == e1000_82571) || 1417 (hw->mac.type == e1000_82572) || 1418 (hw->mac.type == e1000_80003es2lan)) { 1419 /* 1420 * Total FIFO is 48K 1421 */ 1422 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1423 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1424 else 1425 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1426 } else if (hw->mac.type == e1000_82573) { 1427 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1428 } else if (hw->mac.type == e1000_82574) { 1429 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1430 pba = E1000_READ_REG(hw, E1000_PBA); 1431 } else if (hw->mac.type == e1000_ich8lan) { 1432 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1433 } else if (hw->mac.type == e1000_ich9lan) { 1434 pba = E1000_PBA_10K; 1435 } else if (hw->mac.type == e1000_ich10lan) { 1436 pba = E1000_PBA_10K; 1437 } else if (hw->mac.type == e1000_pchlan) { 1438 pba = E1000_PBA_26K; 1439 } else { 1440 /* 1441 * Total FIFO is 40K 1442 */ 1443 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1444 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1445 else 1446 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1447 } 1448 E1000_WRITE_REG(hw, E1000_PBA, pba); 1449 1450 /* 1451 * These parameters set thresholds for the adapter's generation(Tx) 1452 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1453 * settings. Flow control is enabled or disabled in the configuration 1454 * file. 1455 * High-water mark is set down from the top of the rx fifo (not 1456 * sensitive to max_frame_size) and low-water is set just below 1457 * high-water mark. 1458 * The high water mark must be low enough to fit one full frame above 1459 * it in the rx FIFO. Should be the lower of: 1460 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1461 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1462 * Rx FIFO size minus one full frame. 1463 */ 1464 high_water = min(((pba << 10) * 9 / 10), 1465 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 || 1466 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ? 1467 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1468 ((pba << 10) - Adapter->max_frame_size))); 1469 1470 hw->fc.high_water = high_water & 0xFFF8; 1471 hw->fc.low_water = hw->fc.high_water - 8; 1472 1473 if (hw->mac.type == e1000_80003es2lan) 1474 hw->fc.pause_time = 0xFFFF; 1475 else 1476 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1477 hw->fc.send_xon = B_TRUE; 1478 1479 /* 1480 * Reset the adapter hardware the second time. 1481 */ 1482 mutex_enter(&e1000g_nvm_lock); 1483 result = e1000_reset_hw(hw); 1484 mutex_exit(&e1000g_nvm_lock); 1485 1486 if (result != E1000_SUCCESS) { 1487 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1488 goto init_fail; 1489 } 1490 1491 /* disable wakeup control by default */ 1492 if (hw->mac.type >= e1000_82544) 1493 E1000_WRITE_REG(hw, E1000_WUC, 0); 1494 1495 /* 1496 * MWI should be disabled on 82546. 1497 */ 1498 if (hw->mac.type == e1000_82546) 1499 e1000_pci_clear_mwi(hw); 1500 else 1501 e1000_pci_set_mwi(hw); 1502 1503 /* 1504 * Configure/Initialize hardware 1505 */ 1506 mutex_enter(&e1000g_nvm_lock); 1507 result = e1000_init_hw(hw); 1508 mutex_exit(&e1000g_nvm_lock); 1509 1510 if (result < E1000_SUCCESS) { 1511 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1512 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1513 goto init_fail; 1514 } 1515 1516 /* 1517 * Restore LED settings to the default from EEPROM 1518 * to meet the standard for Sun platforms. 1519 */ 1520 (void) e1000_cleanup_led(hw); 1521 1522 /* Disable Smart Power Down */ 1523 phy_spd_state(hw, B_FALSE); 1524 1525 /* Make sure driver has control */ 1526 e1000g_get_driver_control(hw); 1527 1528 /* 1529 * Initialize unicast addresses. 1530 */ 1531 e1000g_init_unicst(Adapter); 1532 1533 /* 1534 * Setup and initialize the mctable structures. After this routine 1535 * completes Multicast table will be set 1536 */ 1537 e1000_update_mc_addr_list(hw, 1538 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 1539 msec_delay(5); 1540 1541 /* 1542 * Implement Adaptive IFS 1543 */ 1544 e1000_reset_adaptive(hw); 1545 1546 /* Setup Interrupt Throttling Register */ 1547 if (hw->mac.type >= e1000_82540) { 1548 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1549 } else 1550 Adapter->intr_adaptive = B_FALSE; 1551 1552 /* Start the timer for link setup */ 1553 if (hw->mac.autoneg) 1554 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1555 else 1556 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1557 1558 mutex_enter(&Adapter->link_lock); 1559 if (hw->phy.autoneg_wait_to_complete) { 1560 Adapter->link_complete = B_TRUE; 1561 } else { 1562 Adapter->link_complete = B_FALSE; 1563 Adapter->link_tid = timeout(e1000g_link_timer, 1564 (void *)Adapter, link_timeout); 1565 } 1566 mutex_exit(&Adapter->link_lock); 1567 1568 /* Save the state of the phy */ 1569 e1000g_get_phy_state(Adapter); 1570 1571 e1000g_param_sync(Adapter); 1572 1573 Adapter->init_count++; 1574 1575 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1576 goto init_fail; 1577 } 1578 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1579 goto init_fail; 1580 } 1581 1582 Adapter->poll_mode = e1000g_poll_mode; 1583 1584 return (DDI_SUCCESS); 1585 1586 init_fail: 1587 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1588 return (DDI_FAILURE); 1589 } 1590 1591 static int 1592 e1000g_alloc_rx_data(struct e1000g *Adapter) 1593 { 1594 e1000g_rx_ring_t *rx_ring; 1595 e1000g_rx_data_t *rx_data; 1596 1597 rx_ring = Adapter->rx_ring; 1598 1599 rx_data = kmem_zalloc(sizeof (e1000g_rx_data_t), KM_NOSLEEP); 1600 1601 if (rx_data == NULL) 1602 return (DDI_FAILURE); 1603 1604 rx_data->priv_devi_node = Adapter->priv_devi_node; 1605 rx_data->rx_ring = rx_ring; 1606 1607 mutex_init(&rx_data->freelist_lock, NULL, 1608 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1609 mutex_init(&rx_data->recycle_lock, NULL, 1610 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1611 1612 rx_ring->rx_data = rx_data; 1613 1614 return (DDI_SUCCESS); 1615 } 1616 1617 void 1618 e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data) 1619 { 1620 rx_sw_packet_t *packet, *next_packet; 1621 1622 if (rx_data == NULL) 1623 return; 1624 1625 packet = rx_data->packet_area; 1626 while (packet != NULL) { 1627 next_packet = packet->next; 1628 e1000g_free_rx_sw_packet(packet, B_TRUE); 1629 packet = next_packet; 1630 } 1631 rx_data->packet_area = NULL; 1632 } 1633 1634 void 1635 e1000g_free_rx_data(e1000g_rx_data_t *rx_data) 1636 { 1637 if (rx_data == NULL) 1638 return; 1639 1640 mutex_destroy(&rx_data->freelist_lock); 1641 mutex_destroy(&rx_data->recycle_lock); 1642 1643 kmem_free(rx_data, sizeof (e1000g_rx_data_t)); 1644 } 1645 1646 /* 1647 * Check if the link is up 1648 */ 1649 static boolean_t 1650 e1000g_link_up(struct e1000g *Adapter) 1651 { 1652 struct e1000_hw *hw = &Adapter->shared; 1653 boolean_t link_up = B_FALSE; 1654 1655 /* 1656 * get_link_status is set in the interrupt handler on link-status-change 1657 * or rx sequence error interrupt. get_link_status will stay 1658 * false until the e1000_check_for_link establishes link only 1659 * for copper adapters. 1660 */ 1661 switch (hw->phy.media_type) { 1662 case e1000_media_type_copper: 1663 if (hw->mac.get_link_status) { 1664 (void) e1000_check_for_link(hw); 1665 link_up = !hw->mac.get_link_status; 1666 } else { 1667 link_up = B_TRUE; 1668 } 1669 break; 1670 case e1000_media_type_fiber: 1671 (void) e1000_check_for_link(hw); 1672 link_up = (E1000_READ_REG(hw, E1000_STATUS) & 1673 E1000_STATUS_LU); 1674 break; 1675 case e1000_media_type_internal_serdes: 1676 (void) e1000_check_for_link(hw); 1677 link_up = hw->mac.serdes_has_link; 1678 break; 1679 } 1680 1681 return (link_up); 1682 } 1683 1684 static void 1685 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1686 { 1687 struct iocblk *iocp; 1688 struct e1000g *e1000gp; 1689 enum ioc_reply status; 1690 1691 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1692 iocp->ioc_error = 0; 1693 e1000gp = (struct e1000g *)arg; 1694 1695 ASSERT(e1000gp); 1696 if (e1000gp == NULL) { 1697 miocnak(q, mp, 0, EINVAL); 1698 return; 1699 } 1700 1701 rw_enter(&e1000gp->chip_lock, RW_READER); 1702 if (e1000gp->e1000g_state & E1000G_SUSPENDED) { 1703 rw_exit(&e1000gp->chip_lock); 1704 miocnak(q, mp, 0, EINVAL); 1705 return; 1706 } 1707 rw_exit(&e1000gp->chip_lock); 1708 1709 switch (iocp->ioc_cmd) { 1710 1711 case LB_GET_INFO_SIZE: 1712 case LB_GET_INFO: 1713 case LB_GET_MODE: 1714 case LB_SET_MODE: 1715 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1716 break; 1717 1718 1719 #ifdef E1000G_DEBUG 1720 case E1000G_IOC_REG_PEEK: 1721 case E1000G_IOC_REG_POKE: 1722 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1723 break; 1724 case E1000G_IOC_CHIP_RESET: 1725 e1000gp->reset_count++; 1726 if (e1000g_reset_adapter(e1000gp)) 1727 status = IOC_ACK; 1728 else 1729 status = IOC_INVAL; 1730 break; 1731 #endif 1732 default: 1733 status = IOC_INVAL; 1734 break; 1735 } 1736 1737 /* 1738 * Decide how to reply 1739 */ 1740 switch (status) { 1741 default: 1742 case IOC_INVAL: 1743 /* 1744 * Error, reply with a NAK and EINVAL or the specified error 1745 */ 1746 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1747 EINVAL : iocp->ioc_error); 1748 break; 1749 1750 case IOC_DONE: 1751 /* 1752 * OK, reply already sent 1753 */ 1754 break; 1755 1756 case IOC_ACK: 1757 /* 1758 * OK, reply with an ACK 1759 */ 1760 miocack(q, mp, 0, 0); 1761 break; 1762 1763 case IOC_REPLY: 1764 /* 1765 * OK, send prepared reply as ACK or NAK 1766 */ 1767 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1768 M_IOCACK : M_IOCNAK; 1769 qreply(q, mp); 1770 break; 1771 } 1772 } 1773 1774 /* 1775 * The default value of e1000g_poll_mode == 0 assumes that the NIC is 1776 * capable of supporting only one interrupt and we shouldn't disable 1777 * the physical interrupt. In this case we let the interrupt come and 1778 * we queue the packets in the rx ring itself in case we are in polling 1779 * mode (better latency but slightly lower performance and a very 1780 * high intrrupt count in mpstat which is harmless). 1781 * 1782 * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt 1783 * which can be disabled in poll mode. This gives better overall 1784 * throughput (compared to the mode above), shows very low interrupt 1785 * count but has slightly higher latency since we pick the packets when 1786 * the poll thread does polling. 1787 * 1788 * Currently, this flag should be enabled only while doing performance 1789 * measurement or when it can be guaranteed that entire NIC going 1790 * in poll mode will not harm any traffic like cluster heartbeat etc. 1791 */ 1792 int e1000g_poll_mode = 0; 1793 1794 /* 1795 * Called from the upper layers when driver is in polling mode to 1796 * pick up any queued packets. Care should be taken to not block 1797 * this thread. 1798 */ 1799 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup) 1800 { 1801 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)arg; 1802 mblk_t *mp = NULL; 1803 mblk_t *tail; 1804 struct e1000g *adapter; 1805 1806 adapter = rx_ring->adapter; 1807 1808 rw_enter(&adapter->chip_lock, RW_READER); 1809 1810 if (adapter->e1000g_state & E1000G_SUSPENDED) { 1811 rw_exit(&adapter->chip_lock); 1812 return (NULL); 1813 } 1814 1815 mutex_enter(&rx_ring->rx_lock); 1816 mp = e1000g_receive(rx_ring, &tail, bytes_to_pickup); 1817 mutex_exit(&rx_ring->rx_lock); 1818 rw_exit(&adapter->chip_lock); 1819 return (mp); 1820 } 1821 1822 static int 1823 e1000g_m_start(void *arg) 1824 { 1825 struct e1000g *Adapter = (struct e1000g *)arg; 1826 1827 rw_enter(&Adapter->chip_lock, RW_WRITER); 1828 1829 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1830 rw_exit(&Adapter->chip_lock); 1831 return (ECANCELED); 1832 } 1833 1834 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1835 rw_exit(&Adapter->chip_lock); 1836 return (ENOTACTIVE); 1837 } 1838 1839 Adapter->e1000g_state |= E1000G_STARTED; 1840 1841 rw_exit(&Adapter->chip_lock); 1842 1843 /* Enable and start the watchdog timer */ 1844 enable_watchdog_timer(Adapter); 1845 1846 return (0); 1847 } 1848 1849 static int 1850 e1000g_start(struct e1000g *Adapter, boolean_t global) 1851 { 1852 e1000g_rx_data_t *rx_data; 1853 1854 if (global) { 1855 if (e1000g_alloc_rx_data(Adapter) != DDI_SUCCESS) { 1856 e1000g_log(Adapter, CE_WARN, "Allocate rx data failed"); 1857 goto start_fail; 1858 } 1859 1860 /* Allocate dma resources for descriptors and buffers */ 1861 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1862 e1000g_log(Adapter, CE_WARN, 1863 "Alloc DMA resources failed"); 1864 goto start_fail; 1865 } 1866 Adapter->rx_buffer_setup = B_FALSE; 1867 } 1868 1869 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1870 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1871 e1000g_log(Adapter, CE_WARN, 1872 "Adapter initialization failed"); 1873 goto start_fail; 1874 } 1875 } 1876 1877 /* Setup and initialize the transmit structures */ 1878 e1000g_tx_setup(Adapter); 1879 msec_delay(5); 1880 1881 /* Setup and initialize the receive structures */ 1882 e1000g_rx_setup(Adapter); 1883 msec_delay(5); 1884 1885 /* Restore the e1000g promiscuous mode */ 1886 e1000g_restore_promisc(Adapter); 1887 1888 e1000g_mask_interrupt(Adapter); 1889 1890 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1891 1892 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1893 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1894 goto start_fail; 1895 } 1896 1897 return (DDI_SUCCESS); 1898 1899 start_fail: 1900 rx_data = Adapter->rx_ring->rx_data; 1901 1902 if (global) { 1903 e1000g_release_dma_resources(Adapter); 1904 e1000g_free_rx_pending_buffers(rx_data); 1905 e1000g_free_rx_data(rx_data); 1906 } 1907 1908 mutex_enter(&e1000g_nvm_lock); 1909 (void) e1000_reset_hw(&Adapter->shared); 1910 mutex_exit(&e1000g_nvm_lock); 1911 1912 return (DDI_FAILURE); 1913 } 1914 1915 static void 1916 e1000g_m_stop(void *arg) 1917 { 1918 struct e1000g *Adapter = (struct e1000g *)arg; 1919 1920 /* Drain tx sessions */ 1921 (void) e1000g_tx_drain(Adapter); 1922 1923 rw_enter(&Adapter->chip_lock, RW_WRITER); 1924 1925 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1926 rw_exit(&Adapter->chip_lock); 1927 return; 1928 } 1929 Adapter->e1000g_state &= ~E1000G_STARTED; 1930 e1000g_stop(Adapter, B_TRUE); 1931 1932 rw_exit(&Adapter->chip_lock); 1933 1934 /* Disable and stop all the timers */ 1935 disable_watchdog_timer(Adapter); 1936 stop_link_timer(Adapter); 1937 stop_82547_timer(Adapter->tx_ring); 1938 } 1939 1940 static void 1941 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1942 { 1943 private_devi_list_t *devi_node; 1944 e1000g_rx_data_t *rx_data; 1945 int result; 1946 1947 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1948 1949 /* Stop the chip and release pending resources */ 1950 1951 /* Tell firmware driver is no longer in control */ 1952 e1000g_release_driver_control(&Adapter->shared); 1953 1954 e1000g_clear_all_interrupts(Adapter); 1955 1956 mutex_enter(&e1000g_nvm_lock); 1957 result = e1000_reset_hw(&Adapter->shared); 1958 mutex_exit(&e1000g_nvm_lock); 1959 1960 if (result != E1000_SUCCESS) { 1961 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1962 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1963 } 1964 1965 /* Release resources still held by the TX descriptors */ 1966 e1000g_tx_clean(Adapter); 1967 1968 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1969 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1970 1971 /* Clean the pending rx jumbo packet fragment */ 1972 e1000g_rx_clean(Adapter); 1973 1974 if (global) { 1975 e1000g_release_dma_resources(Adapter); 1976 1977 mutex_enter(&e1000g_rx_detach_lock); 1978 rx_data = Adapter->rx_ring->rx_data; 1979 rx_data->flag |= E1000G_RX_STOPPED; 1980 1981 if (rx_data->pending_count == 0) { 1982 e1000g_free_rx_pending_buffers(rx_data); 1983 e1000g_free_rx_data(rx_data); 1984 } else { 1985 devi_node = rx_data->priv_devi_node; 1986 if (devi_node != NULL) 1987 atomic_inc_32(&devi_node->pending_rx_count); 1988 else 1989 atomic_inc_32(&Adapter->pending_rx_count); 1990 } 1991 mutex_exit(&e1000g_rx_detach_lock); 1992 } 1993 1994 if (Adapter->link_state == LINK_STATE_UP) { 1995 Adapter->link_state = LINK_STATE_UNKNOWN; 1996 if (!Adapter->reset_flag) 1997 mac_link_update(Adapter->mh, Adapter->link_state); 1998 } 1999 } 2000 2001 static void 2002 e1000g_rx_clean(struct e1000g *Adapter) 2003 { 2004 e1000g_rx_data_t *rx_data = Adapter->rx_ring->rx_data; 2005 2006 if (rx_data == NULL) 2007 return; 2008 2009 if (rx_data->rx_mblk != NULL) { 2010 freemsg(rx_data->rx_mblk); 2011 rx_data->rx_mblk = NULL; 2012 rx_data->rx_mblk_tail = NULL; 2013 rx_data->rx_mblk_len = 0; 2014 } 2015 } 2016 2017 static void 2018 e1000g_tx_clean(struct e1000g *Adapter) 2019 { 2020 e1000g_tx_ring_t *tx_ring; 2021 p_tx_sw_packet_t packet; 2022 mblk_t *mp; 2023 mblk_t *nmp; 2024 uint32_t packet_count; 2025 2026 tx_ring = Adapter->tx_ring; 2027 2028 /* 2029 * Here we don't need to protect the lists using 2030 * the usedlist_lock and freelist_lock, for they 2031 * have been protected by the chip_lock. 2032 */ 2033 mp = NULL; 2034 nmp = NULL; 2035 packet_count = 0; 2036 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 2037 while (packet != NULL) { 2038 if (packet->mp != NULL) { 2039 /* Assemble the message chain */ 2040 if (mp == NULL) { 2041 mp = packet->mp; 2042 nmp = packet->mp; 2043 } else { 2044 nmp->b_next = packet->mp; 2045 nmp = packet->mp; 2046 } 2047 /* Disconnect the message from the sw packet */ 2048 packet->mp = NULL; 2049 } 2050 2051 e1000g_free_tx_swpkt(packet); 2052 packet_count++; 2053 2054 packet = (p_tx_sw_packet_t) 2055 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 2056 } 2057 2058 if (mp != NULL) 2059 freemsgchain(mp); 2060 2061 if (packet_count > 0) { 2062 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 2063 QUEUE_INIT_LIST(&tx_ring->used_list); 2064 2065 /* Setup TX descriptor pointers */ 2066 tx_ring->tbd_next = tx_ring->tbd_first; 2067 tx_ring->tbd_oldest = tx_ring->tbd_first; 2068 2069 /* Setup our HW Tx Head & Tail descriptor pointers */ 2070 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 2071 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 2072 } 2073 } 2074 2075 static boolean_t 2076 e1000g_tx_drain(struct e1000g *Adapter) 2077 { 2078 int i; 2079 boolean_t done; 2080 e1000g_tx_ring_t *tx_ring; 2081 2082 tx_ring = Adapter->tx_ring; 2083 2084 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 2085 for (i = 0; i < TX_DRAIN_TIME; i++) { 2086 mutex_enter(&tx_ring->usedlist_lock); 2087 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 2088 mutex_exit(&tx_ring->usedlist_lock); 2089 2090 if (done) 2091 break; 2092 2093 msec_delay(1); 2094 } 2095 2096 return (done); 2097 } 2098 2099 static boolean_t 2100 e1000g_rx_drain(struct e1000g *Adapter) 2101 { 2102 int i; 2103 boolean_t done; 2104 2105 /* 2106 * Allow up to RX_DRAIN_TIME for pending received packets to complete. 2107 */ 2108 for (i = 0; i < RX_DRAIN_TIME; i++) { 2109 done = (Adapter->pending_rx_count == 0); 2110 2111 if (done) 2112 break; 2113 2114 msec_delay(1); 2115 } 2116 2117 return (done); 2118 } 2119 2120 static boolean_t 2121 e1000g_reset_adapter(struct e1000g *Adapter) 2122 { 2123 /* Disable and stop all the timers */ 2124 disable_watchdog_timer(Adapter); 2125 stop_link_timer(Adapter); 2126 stop_82547_timer(Adapter->tx_ring); 2127 2128 rw_enter(&Adapter->chip_lock, RW_WRITER); 2129 2130 if (Adapter->stall_flag) { 2131 Adapter->stall_flag = B_FALSE; 2132 Adapter->reset_flag = B_TRUE; 2133 } 2134 2135 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2136 rw_exit(&Adapter->chip_lock); 2137 return (B_TRUE); 2138 } 2139 2140 e1000g_stop(Adapter, B_FALSE); 2141 2142 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 2143 rw_exit(&Adapter->chip_lock); 2144 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2145 return (B_FALSE); 2146 } 2147 2148 rw_exit(&Adapter->chip_lock); 2149 2150 /* Enable and start the watchdog timer */ 2151 enable_watchdog_timer(Adapter); 2152 2153 return (B_TRUE); 2154 } 2155 2156 boolean_t 2157 e1000g_global_reset(struct e1000g *Adapter) 2158 { 2159 /* Disable and stop all the timers */ 2160 disable_watchdog_timer(Adapter); 2161 stop_link_timer(Adapter); 2162 stop_82547_timer(Adapter->tx_ring); 2163 2164 rw_enter(&Adapter->chip_lock, RW_WRITER); 2165 2166 e1000g_stop(Adapter, B_TRUE); 2167 2168 Adapter->init_count = 0; 2169 2170 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 2171 rw_exit(&Adapter->chip_lock); 2172 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2173 return (B_FALSE); 2174 } 2175 2176 rw_exit(&Adapter->chip_lock); 2177 2178 /* Enable and start the watchdog timer */ 2179 enable_watchdog_timer(Adapter); 2180 2181 return (B_TRUE); 2182 } 2183 2184 /* 2185 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 2186 * 2187 * This interrupt service routine is for PCI-Express adapters. 2188 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 2189 * bit is set. 2190 */ 2191 static uint_t 2192 e1000g_intr_pciexpress(caddr_t arg) 2193 { 2194 struct e1000g *Adapter; 2195 uint32_t icr; 2196 2197 Adapter = (struct e1000g *)(uintptr_t)arg; 2198 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2199 2200 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2201 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2202 return (DDI_INTR_CLAIMED); 2203 } 2204 2205 if (icr & E1000_ICR_INT_ASSERTED) { 2206 /* 2207 * E1000_ICR_INT_ASSERTED bit was set: 2208 * Read(Clear) the ICR, claim this interrupt, 2209 * look for work to do. 2210 */ 2211 e1000g_intr_work(Adapter, icr); 2212 return (DDI_INTR_CLAIMED); 2213 } else { 2214 /* 2215 * E1000_ICR_INT_ASSERTED bit was not set: 2216 * Don't claim this interrupt, return immediately. 2217 */ 2218 return (DDI_INTR_UNCLAIMED); 2219 } 2220 } 2221 2222 /* 2223 * e1000g_intr - ISR for PCI/PCI-X chipsets 2224 * 2225 * This interrupt service routine is for PCI/PCI-X adapters. 2226 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 2227 * bit is set or not. 2228 */ 2229 static uint_t 2230 e1000g_intr(caddr_t arg) 2231 { 2232 struct e1000g *Adapter; 2233 uint32_t icr; 2234 2235 Adapter = (struct e1000g *)(uintptr_t)arg; 2236 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2237 2238 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2239 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2240 return (DDI_INTR_CLAIMED); 2241 } 2242 2243 if (icr) { 2244 /* 2245 * Any bit was set in ICR: 2246 * Read(Clear) the ICR, claim this interrupt, 2247 * look for work to do. 2248 */ 2249 e1000g_intr_work(Adapter, icr); 2250 return (DDI_INTR_CLAIMED); 2251 } else { 2252 /* 2253 * No bit was set in ICR: 2254 * Don't claim this interrupt, return immediately. 2255 */ 2256 return (DDI_INTR_UNCLAIMED); 2257 } 2258 } 2259 2260 /* 2261 * e1000g_intr_work - actual processing of ISR 2262 * 2263 * Read(clear) the ICR contents and call appropriate interrupt 2264 * processing routines. 2265 */ 2266 static void 2267 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 2268 { 2269 struct e1000_hw *hw; 2270 hw = &Adapter->shared; 2271 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2272 2273 Adapter->rx_pkt_cnt = 0; 2274 Adapter->tx_pkt_cnt = 0; 2275 2276 rw_enter(&Adapter->chip_lock, RW_READER); 2277 2278 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2279 rw_exit(&Adapter->chip_lock); 2280 return; 2281 } 2282 /* 2283 * Here we need to check the "e1000g_state" flag within the chip_lock to 2284 * ensure the receive routine will not execute when the adapter is 2285 * being reset. 2286 */ 2287 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2288 rw_exit(&Adapter->chip_lock); 2289 return; 2290 } 2291 2292 if (icr & E1000_ICR_RXT0) { 2293 mblk_t *mp = NULL; 2294 mblk_t *tail = NULL; 2295 e1000g_rx_ring_t *rx_ring; 2296 2297 rx_ring = Adapter->rx_ring; 2298 mutex_enter(&rx_ring->rx_lock); 2299 /* 2300 * Sometimes with legacy interrupts, it possible that 2301 * there is a single interrupt for Rx/Tx. In which 2302 * case, if poll flag is set, we shouldn't really 2303 * be doing Rx processing. 2304 */ 2305 if (!rx_ring->poll_flag) 2306 mp = e1000g_receive(rx_ring, &tail, 2307 E1000G_CHAIN_NO_LIMIT); 2308 mutex_exit(&rx_ring->rx_lock); 2309 rw_exit(&Adapter->chip_lock); 2310 if (mp != NULL) 2311 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2312 mp, rx_ring->ring_gen_num); 2313 } else 2314 rw_exit(&Adapter->chip_lock); 2315 2316 if (icr & E1000_ICR_TXDW) { 2317 if (!Adapter->tx_intr_enable) 2318 e1000g_clear_tx_interrupt(Adapter); 2319 2320 /* Recycle the tx descriptors */ 2321 rw_enter(&Adapter->chip_lock, RW_READER); 2322 (void) e1000g_recycle(tx_ring); 2323 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 2324 rw_exit(&Adapter->chip_lock); 2325 2326 if (tx_ring->resched_needed && 2327 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 2328 tx_ring->resched_needed = B_FALSE; 2329 mac_tx_update(Adapter->mh); 2330 E1000G_STAT(tx_ring->stat_reschedule); 2331 } 2332 } 2333 2334 /* 2335 * The Receive Sequence errors RXSEQ and the link status change LSC 2336 * are checked to detect that the cable has been pulled out. For 2337 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 2338 * are an indication that cable is not connected. 2339 */ 2340 if ((icr & E1000_ICR_RXSEQ) || 2341 (icr & E1000_ICR_LSC) || 2342 (icr & E1000_ICR_GPI_EN1)) { 2343 boolean_t link_changed; 2344 timeout_id_t tid = 0; 2345 2346 stop_watchdog_timer(Adapter); 2347 2348 rw_enter(&Adapter->chip_lock, RW_WRITER); 2349 2350 /* 2351 * Because we got a link-status-change interrupt, force 2352 * e1000_check_for_link() to look at phy 2353 */ 2354 Adapter->shared.mac.get_link_status = B_TRUE; 2355 2356 /* e1000g_link_check takes care of link status change */ 2357 link_changed = e1000g_link_check(Adapter); 2358 2359 /* Get new phy state */ 2360 e1000g_get_phy_state(Adapter); 2361 2362 /* 2363 * If the link timer has not timed out, we'll not notify 2364 * the upper layer with any link state until the link is up. 2365 */ 2366 if (link_changed && !Adapter->link_complete) { 2367 if (Adapter->link_state == LINK_STATE_UP) { 2368 mutex_enter(&Adapter->link_lock); 2369 Adapter->link_complete = B_TRUE; 2370 tid = Adapter->link_tid; 2371 Adapter->link_tid = 0; 2372 mutex_exit(&Adapter->link_lock); 2373 } else { 2374 link_changed = B_FALSE; 2375 } 2376 } 2377 rw_exit(&Adapter->chip_lock); 2378 2379 if (link_changed) { 2380 if (tid != 0) 2381 (void) untimeout(tid); 2382 2383 /* 2384 * Workaround for esb2. Data stuck in fifo on a link 2385 * down event. Stop receiver here and reset in watchdog. 2386 */ 2387 if ((Adapter->link_state == LINK_STATE_DOWN) && 2388 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2389 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2390 E1000_WRITE_REG(hw, E1000_RCTL, 2391 rctl & ~E1000_RCTL_EN); 2392 e1000g_log(Adapter, CE_WARN, 2393 "ESB2 receiver disabled"); 2394 Adapter->esb2_workaround = B_TRUE; 2395 } 2396 if (!Adapter->reset_flag) 2397 mac_link_update(Adapter->mh, 2398 Adapter->link_state); 2399 if (Adapter->link_state == LINK_STATE_UP) 2400 Adapter->reset_flag = B_FALSE; 2401 } 2402 2403 start_watchdog_timer(Adapter); 2404 } 2405 } 2406 2407 static void 2408 e1000g_init_unicst(struct e1000g *Adapter) 2409 { 2410 struct e1000_hw *hw; 2411 int slot; 2412 2413 hw = &Adapter->shared; 2414 2415 if (Adapter->init_count == 0) { 2416 /* Initialize the multiple unicast addresses */ 2417 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2418 2419 /* Workaround for an erratum of 82571 chipst */ 2420 if ((hw->mac.type == e1000_82571) && 2421 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2422 Adapter->unicst_total--; 2423 2424 Adapter->unicst_avail = Adapter->unicst_total; 2425 2426 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2427 /* Clear both the flag and MAC address */ 2428 Adapter->unicst_addr[slot].reg.high = 0; 2429 Adapter->unicst_addr[slot].reg.low = 0; 2430 } 2431 } else { 2432 /* Workaround for an erratum of 82571 chipst */ 2433 if ((hw->mac.type == e1000_82571) && 2434 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2435 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2436 2437 /* Re-configure the RAR registers */ 2438 for (slot = 0; slot < Adapter->unicst_total; slot++) 2439 if (Adapter->unicst_addr[slot].mac.set == 1) 2440 e1000_rar_set(hw, 2441 Adapter->unicst_addr[slot].mac.addr, slot); 2442 } 2443 2444 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2445 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2446 } 2447 2448 static int 2449 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2450 int slot) 2451 { 2452 struct e1000_hw *hw; 2453 2454 hw = &Adapter->shared; 2455 2456 /* 2457 * The first revision of Wiseman silicon (rev 2.0) has an errata 2458 * that requires the receiver to be in reset when any of the 2459 * receive address registers (RAR regs) are accessed. The first 2460 * rev of Wiseman silicon also requires MWI to be disabled when 2461 * a global reset or a receive reset is issued. So before we 2462 * initialize the RARs, we check the rev of the Wiseman controller 2463 * and work around any necessary HW errata. 2464 */ 2465 if ((hw->mac.type == e1000_82542) && 2466 (hw->revision_id == E1000_REVISION_2)) { 2467 e1000_pci_clear_mwi(hw); 2468 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2469 msec_delay(5); 2470 } 2471 if (mac_addr == NULL) { 2472 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0); 2473 E1000_WRITE_FLUSH(hw); 2474 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0); 2475 E1000_WRITE_FLUSH(hw); 2476 /* Clear both the flag and MAC address */ 2477 Adapter->unicst_addr[slot].reg.high = 0; 2478 Adapter->unicst_addr[slot].reg.low = 0; 2479 } else { 2480 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, 2481 ETHERADDRL); 2482 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2483 Adapter->unicst_addr[slot].mac.set = 1; 2484 } 2485 2486 /* Workaround for an erratum of 82571 chipst */ 2487 if (slot == 0) { 2488 if ((hw->mac.type == e1000_82571) && 2489 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2490 if (mac_addr == NULL) { 2491 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2492 slot << 1, 0); 2493 E1000_WRITE_FLUSH(hw); 2494 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2495 (slot << 1) + 1, 0); 2496 E1000_WRITE_FLUSH(hw); 2497 } else { 2498 e1000_rar_set(hw, (uint8_t *)mac_addr, 2499 LAST_RAR_ENTRY); 2500 } 2501 } 2502 2503 /* 2504 * If we are using Wiseman rev 2.0 silicon, we will have previously 2505 * put the receive in reset, and disabled MWI, to work around some 2506 * HW errata. Now we should take the receiver out of reset, and 2507 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2508 */ 2509 if ((hw->mac.type == e1000_82542) && 2510 (hw->revision_id == E1000_REVISION_2)) { 2511 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2512 msec_delay(1); 2513 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2514 e1000_pci_set_mwi(hw); 2515 e1000g_rx_setup(Adapter); 2516 } 2517 2518 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2519 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2520 return (EIO); 2521 } 2522 2523 return (0); 2524 } 2525 2526 static int 2527 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2528 { 2529 struct e1000_hw *hw = &Adapter->shared; 2530 struct ether_addr *newtable; 2531 size_t new_len; 2532 size_t old_len; 2533 int res = 0; 2534 2535 if ((multiaddr[0] & 01) == 0) { 2536 res = EINVAL; 2537 e1000g_log(Adapter, CE_WARN, "Illegal multicast address"); 2538 goto done; 2539 } 2540 2541 if (Adapter->mcast_count >= Adapter->mcast_max_num) { 2542 res = ENOENT; 2543 e1000g_log(Adapter, CE_WARN, 2544 "Adapter requested more than %d mcast addresses", 2545 Adapter->mcast_max_num); 2546 goto done; 2547 } 2548 2549 2550 if (Adapter->mcast_count == Adapter->mcast_alloc_count) { 2551 old_len = Adapter->mcast_alloc_count * 2552 sizeof (struct ether_addr); 2553 new_len = (Adapter->mcast_alloc_count + MCAST_ALLOC_SIZE) * 2554 sizeof (struct ether_addr); 2555 2556 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2557 if (newtable == NULL) { 2558 res = ENOMEM; 2559 e1000g_log(Adapter, CE_WARN, 2560 "Not enough memory to alloc mcast table"); 2561 goto done; 2562 } 2563 2564 if (Adapter->mcast_table != NULL) { 2565 bcopy(Adapter->mcast_table, newtable, old_len); 2566 kmem_free(Adapter->mcast_table, old_len); 2567 } 2568 Adapter->mcast_alloc_count += MCAST_ALLOC_SIZE; 2569 Adapter->mcast_table = newtable; 2570 } 2571 2572 bcopy(multiaddr, 2573 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2574 Adapter->mcast_count++; 2575 2576 /* 2577 * Update the MC table in the hardware 2578 */ 2579 e1000g_clear_interrupt(Adapter); 2580 2581 e1000_update_mc_addr_list(hw, 2582 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2583 2584 e1000g_mask_interrupt(Adapter); 2585 2586 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2587 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2588 res = EIO; 2589 } 2590 2591 done: 2592 return (res); 2593 } 2594 2595 static int 2596 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2597 { 2598 struct e1000_hw *hw = &Adapter->shared; 2599 struct ether_addr *newtable; 2600 size_t new_len; 2601 size_t old_len; 2602 unsigned i; 2603 2604 for (i = 0; i < Adapter->mcast_count; i++) { 2605 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2606 ETHERADDRL) == 0) { 2607 for (i++; i < Adapter->mcast_count; i++) { 2608 Adapter->mcast_table[i - 1] = 2609 Adapter->mcast_table[i]; 2610 } 2611 Adapter->mcast_count--; 2612 break; 2613 } 2614 } 2615 2616 if ((Adapter->mcast_alloc_count - Adapter->mcast_count) > 2617 MCAST_ALLOC_SIZE) { 2618 old_len = Adapter->mcast_alloc_count * 2619 sizeof (struct ether_addr); 2620 new_len = (Adapter->mcast_alloc_count - MCAST_ALLOC_SIZE) * 2621 sizeof (struct ether_addr); 2622 2623 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2624 if (newtable != NULL) { 2625 bcopy(Adapter->mcast_table, newtable, new_len); 2626 kmem_free(Adapter->mcast_table, old_len); 2627 2628 Adapter->mcast_alloc_count -= MCAST_ALLOC_SIZE; 2629 Adapter->mcast_table = newtable; 2630 } 2631 } 2632 2633 /* 2634 * Update the MC table in the hardware 2635 */ 2636 e1000g_clear_interrupt(Adapter); 2637 2638 e1000_update_mc_addr_list(hw, 2639 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2640 2641 e1000g_mask_interrupt(Adapter); 2642 2643 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2644 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2645 return (EIO); 2646 } 2647 2648 return (0); 2649 } 2650 2651 static void 2652 e1000g_release_multicast(struct e1000g *Adapter) 2653 { 2654 if (Adapter->mcast_table != NULL) { 2655 kmem_free(Adapter->mcast_table, 2656 Adapter->mcast_alloc_count * sizeof (struct ether_addr)); 2657 Adapter->mcast_table = NULL; 2658 } 2659 } 2660 2661 int 2662 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2663 { 2664 struct e1000g *Adapter = (struct e1000g *)arg; 2665 int result; 2666 2667 rw_enter(&Adapter->chip_lock, RW_WRITER); 2668 2669 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2670 result = ECANCELED; 2671 goto done; 2672 } 2673 2674 result = (add) ? multicst_add(Adapter, addr) 2675 : multicst_remove(Adapter, addr); 2676 2677 done: 2678 rw_exit(&Adapter->chip_lock); 2679 return (result); 2680 2681 } 2682 2683 int 2684 e1000g_m_promisc(void *arg, boolean_t on) 2685 { 2686 struct e1000g *Adapter = (struct e1000g *)arg; 2687 uint32_t rctl; 2688 2689 rw_enter(&Adapter->chip_lock, RW_WRITER); 2690 2691 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2692 rw_exit(&Adapter->chip_lock); 2693 return (ECANCELED); 2694 } 2695 2696 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2697 2698 if (on) 2699 rctl |= 2700 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2701 else 2702 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2703 2704 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2705 2706 Adapter->e1000g_promisc = on; 2707 2708 rw_exit(&Adapter->chip_lock); 2709 2710 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2711 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2712 return (EIO); 2713 } 2714 2715 return (0); 2716 } 2717 2718 /* 2719 * Entry points to enable and disable interrupts at the granularity of 2720 * a group. 2721 * Turns the poll_mode for the whole adapter on and off to enable or 2722 * override the ring level polling control over the hardware interrupts. 2723 */ 2724 static int 2725 e1000g_rx_group_intr_enable(mac_intr_handle_t arg) 2726 { 2727 struct e1000g *adapter = (struct e1000g *)arg; 2728 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2729 2730 /* 2731 * Later interrupts at the granularity of the this ring will 2732 * invoke mac_rx() with NULL, indicating the need for another 2733 * software classification. 2734 * We have a single ring usable per adapter now, so we only need to 2735 * reset the rx handle for that one. 2736 * When more RX rings can be used, we should update each one of them. 2737 */ 2738 mutex_enter(&rx_ring->rx_lock); 2739 rx_ring->mrh = NULL; 2740 adapter->poll_mode = B_FALSE; 2741 mutex_exit(&rx_ring->rx_lock); 2742 return (0); 2743 } 2744 2745 static int 2746 e1000g_rx_group_intr_disable(mac_intr_handle_t arg) 2747 { 2748 struct e1000g *adapter = (struct e1000g *)arg; 2749 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2750 2751 mutex_enter(&rx_ring->rx_lock); 2752 2753 /* 2754 * Later interrupts at the granularity of the this ring will 2755 * invoke mac_rx() with the handle for this ring; 2756 */ 2757 adapter->poll_mode = B_TRUE; 2758 rx_ring->mrh = rx_ring->mrh_init; 2759 mutex_exit(&rx_ring->rx_lock); 2760 return (0); 2761 } 2762 2763 /* 2764 * Entry points to enable and disable interrupts at the granularity of 2765 * a ring. 2766 * adapter poll_mode controls whether we actually proceed with hardware 2767 * interrupt toggling. 2768 */ 2769 static int 2770 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh) 2771 { 2772 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2773 struct e1000g *adapter = rx_ring->adapter; 2774 struct e1000_hw *hw = &adapter->shared; 2775 uint32_t intr_mask; 2776 2777 rw_enter(&adapter->chip_lock, RW_READER); 2778 2779 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2780 rw_exit(&adapter->chip_lock); 2781 return (0); 2782 } 2783 2784 mutex_enter(&rx_ring->rx_lock); 2785 rx_ring->poll_flag = 0; 2786 mutex_exit(&rx_ring->rx_lock); 2787 2788 /* Rx interrupt enabling for MSI and legacy */ 2789 intr_mask = E1000_READ_REG(hw, E1000_IMS); 2790 intr_mask |= E1000_IMS_RXT0; 2791 E1000_WRITE_REG(hw, E1000_IMS, intr_mask); 2792 E1000_WRITE_FLUSH(hw); 2793 2794 /* Trigger a Rx interrupt to check Rx ring */ 2795 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2796 E1000_WRITE_FLUSH(hw); 2797 2798 rw_exit(&adapter->chip_lock); 2799 return (0); 2800 } 2801 2802 static int 2803 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh) 2804 { 2805 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2806 struct e1000g *adapter = rx_ring->adapter; 2807 struct e1000_hw *hw = &adapter->shared; 2808 2809 rw_enter(&adapter->chip_lock, RW_READER); 2810 2811 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2812 rw_exit(&adapter->chip_lock); 2813 return (0); 2814 } 2815 mutex_enter(&rx_ring->rx_lock); 2816 rx_ring->poll_flag = 1; 2817 mutex_exit(&rx_ring->rx_lock); 2818 2819 /* Rx interrupt disabling for MSI and legacy */ 2820 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0); 2821 E1000_WRITE_FLUSH(hw); 2822 2823 rw_exit(&adapter->chip_lock); 2824 return (0); 2825 } 2826 2827 /* 2828 * e1000g_unicst_find - Find the slot for the specified unicast address 2829 */ 2830 static int 2831 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr) 2832 { 2833 int slot; 2834 2835 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2836 if ((Adapter->unicst_addr[slot].mac.set == 1) && 2837 (bcmp(Adapter->unicst_addr[slot].mac.addr, 2838 mac_addr, ETHERADDRL) == 0)) 2839 return (slot); 2840 } 2841 2842 return (-1); 2843 } 2844 2845 /* 2846 * Entry points to add and remove a MAC address to a ring group. 2847 * The caller takes care of adding and removing the MAC addresses 2848 * to the filter via these two routines. 2849 */ 2850 2851 static int 2852 e1000g_addmac(void *arg, const uint8_t *mac_addr) 2853 { 2854 struct e1000g *Adapter = (struct e1000g *)arg; 2855 int slot, err; 2856 2857 rw_enter(&Adapter->chip_lock, RW_WRITER); 2858 2859 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2860 rw_exit(&Adapter->chip_lock); 2861 return (ECANCELED); 2862 } 2863 2864 if (e1000g_unicst_find(Adapter, mac_addr) != -1) { 2865 /* The same address is already in slot */ 2866 rw_exit(&Adapter->chip_lock); 2867 return (0); 2868 } 2869 2870 if (Adapter->unicst_avail == 0) { 2871 /* no slots available */ 2872 rw_exit(&Adapter->chip_lock); 2873 return (ENOSPC); 2874 } 2875 2876 /* Search for a free slot */ 2877 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2878 if (Adapter->unicst_addr[slot].mac.set == 0) 2879 break; 2880 } 2881 ASSERT(slot < Adapter->unicst_total); 2882 2883 err = e1000g_unicst_set(Adapter, mac_addr, slot); 2884 if (err == 0) 2885 Adapter->unicst_avail--; 2886 2887 rw_exit(&Adapter->chip_lock); 2888 2889 return (err); 2890 } 2891 2892 static int 2893 e1000g_remmac(void *arg, const uint8_t *mac_addr) 2894 { 2895 struct e1000g *Adapter = (struct e1000g *)arg; 2896 int slot, err; 2897 2898 rw_enter(&Adapter->chip_lock, RW_WRITER); 2899 2900 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2901 rw_exit(&Adapter->chip_lock); 2902 return (ECANCELED); 2903 } 2904 2905 slot = e1000g_unicst_find(Adapter, mac_addr); 2906 if (slot == -1) { 2907 rw_exit(&Adapter->chip_lock); 2908 return (EINVAL); 2909 } 2910 2911 ASSERT(Adapter->unicst_addr[slot].mac.set); 2912 2913 /* Clear this slot */ 2914 err = e1000g_unicst_set(Adapter, NULL, slot); 2915 if (err == 0) 2916 Adapter->unicst_avail++; 2917 2918 rw_exit(&Adapter->chip_lock); 2919 2920 return (err); 2921 } 2922 2923 static int 2924 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num) 2925 { 2926 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh; 2927 2928 mutex_enter(&rx_ring->rx_lock); 2929 rx_ring->ring_gen_num = mr_gen_num; 2930 mutex_exit(&rx_ring->rx_lock); 2931 return (0); 2932 } 2933 2934 /* 2935 * Callback funtion for MAC layer to register all rings. 2936 * 2937 * The hardware supports a single group with currently only one ring 2938 * available. 2939 * Though not offering virtualization ability per se, exposing the 2940 * group/ring still enables the polling and interrupt toggling. 2941 */ 2942 /* ARGSUSED */ 2943 void 2944 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index, 2945 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh) 2946 { 2947 struct e1000g *Adapter = (struct e1000g *)arg; 2948 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 2949 mac_intr_t *mintr; 2950 2951 /* 2952 * We advertised only RX group/rings, so the MAC framework shouldn't 2953 * ask for any thing else. 2954 */ 2955 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0); 2956 2957 rx_ring->mrh = rx_ring->mrh_init = rh; 2958 infop->mri_driver = (mac_ring_driver_t)rx_ring; 2959 infop->mri_start = e1000g_ring_start; 2960 infop->mri_stop = NULL; 2961 infop->mri_poll = e1000g_poll_ring; 2962 2963 /* Ring level interrupts */ 2964 mintr = &infop->mri_intr; 2965 mintr->mi_handle = (mac_intr_handle_t)rx_ring; 2966 mintr->mi_enable = e1000g_rx_ring_intr_enable; 2967 mintr->mi_disable = e1000g_rx_ring_intr_disable; 2968 } 2969 2970 /* ARGSUSED */ 2971 static void 2972 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index, 2973 mac_group_info_t *infop, mac_group_handle_t gh) 2974 { 2975 struct e1000g *Adapter = (struct e1000g *)arg; 2976 mac_intr_t *mintr; 2977 2978 /* 2979 * We advertised a single RX ring. Getting a request for anything else 2980 * signifies a bug in the MAC framework. 2981 */ 2982 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0); 2983 2984 Adapter->rx_group = gh; 2985 2986 infop->mgi_driver = (mac_group_driver_t)Adapter; 2987 infop->mgi_start = NULL; 2988 infop->mgi_stop = NULL; 2989 infop->mgi_addmac = e1000g_addmac; 2990 infop->mgi_remmac = e1000g_remmac; 2991 infop->mgi_count = 1; 2992 2993 /* Group level interrupts */ 2994 mintr = &infop->mgi_intr; 2995 mintr->mi_handle = (mac_intr_handle_t)Adapter; 2996 mintr->mi_enable = e1000g_rx_group_intr_enable; 2997 mintr->mi_disable = e1000g_rx_group_intr_disable; 2998 } 2999 3000 static boolean_t 3001 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 3002 { 3003 struct e1000g *Adapter = (struct e1000g *)arg; 3004 3005 switch (cap) { 3006 case MAC_CAPAB_HCKSUM: { 3007 uint32_t *txflags = cap_data; 3008 3009 if (Adapter->tx_hcksum_enable) 3010 *txflags = HCKSUM_IPHDRCKSUM | 3011 HCKSUM_INET_PARTIAL; 3012 else 3013 return (B_FALSE); 3014 break; 3015 } 3016 3017 case MAC_CAPAB_LSO: { 3018 mac_capab_lso_t *cap_lso = cap_data; 3019 3020 if (Adapter->lso_enable) { 3021 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 3022 cap_lso->lso_basic_tcp_ipv4.lso_max = 3023 E1000_LSO_MAXLEN; 3024 } else 3025 return (B_FALSE); 3026 break; 3027 } 3028 case MAC_CAPAB_RINGS: { 3029 mac_capab_rings_t *cap_rings = cap_data; 3030 3031 /* No TX rings exposed yet */ 3032 if (cap_rings->mr_type != MAC_RING_TYPE_RX) 3033 return (B_FALSE); 3034 3035 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC; 3036 cap_rings->mr_rnum = 1; 3037 cap_rings->mr_gnum = 1; 3038 cap_rings->mr_rget = e1000g_fill_ring; 3039 cap_rings->mr_gget = e1000g_fill_group; 3040 break; 3041 } 3042 default: 3043 return (B_FALSE); 3044 } 3045 return (B_TRUE); 3046 } 3047 3048 static boolean_t 3049 e1000g_param_locked(mac_prop_id_t pr_num) 3050 { 3051 /* 3052 * All en_* parameters are locked (read-only) while 3053 * the device is in any sort of loopback mode ... 3054 */ 3055 switch (pr_num) { 3056 case MAC_PROP_EN_1000FDX_CAP: 3057 case MAC_PROP_EN_1000HDX_CAP: 3058 case MAC_PROP_EN_100FDX_CAP: 3059 case MAC_PROP_EN_100HDX_CAP: 3060 case MAC_PROP_EN_10FDX_CAP: 3061 case MAC_PROP_EN_10HDX_CAP: 3062 case MAC_PROP_AUTONEG: 3063 case MAC_PROP_FLOWCTRL: 3064 return (B_TRUE); 3065 } 3066 return (B_FALSE); 3067 } 3068 3069 /* 3070 * callback function for set/get of properties 3071 */ 3072 static int 3073 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3074 uint_t pr_valsize, const void *pr_val) 3075 { 3076 struct e1000g *Adapter = arg; 3077 struct e1000_hw *hw = &Adapter->shared; 3078 struct e1000_fc_info *fc = &Adapter->shared.fc; 3079 int err = 0; 3080 link_flowctrl_t flowctrl; 3081 uint32_t cur_mtu, new_mtu; 3082 3083 rw_enter(&Adapter->chip_lock, RW_WRITER); 3084 3085 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 3086 rw_exit(&Adapter->chip_lock); 3087 return (ECANCELED); 3088 } 3089 3090 if (Adapter->loopback_mode != E1000G_LB_NONE && 3091 e1000g_param_locked(pr_num)) { 3092 /* 3093 * All en_* parameters are locked (read-only) 3094 * while the device is in any sort of loopback mode. 3095 */ 3096 rw_exit(&Adapter->chip_lock); 3097 return (EBUSY); 3098 } 3099 3100 switch (pr_num) { 3101 case MAC_PROP_EN_1000FDX_CAP: 3102 if (hw->phy.media_type != e1000_media_type_copper) { 3103 err = ENOTSUP; 3104 break; 3105 } 3106 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 3107 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 3108 goto reset; 3109 case MAC_PROP_EN_100FDX_CAP: 3110 if (hw->phy.media_type != e1000_media_type_copper) { 3111 err = ENOTSUP; 3112 break; 3113 } 3114 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 3115 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 3116 goto reset; 3117 case MAC_PROP_EN_100HDX_CAP: 3118 if (hw->phy.media_type != e1000_media_type_copper) { 3119 err = ENOTSUP; 3120 break; 3121 } 3122 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 3123 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 3124 goto reset; 3125 case MAC_PROP_EN_10FDX_CAP: 3126 if (hw->phy.media_type != e1000_media_type_copper) { 3127 err = ENOTSUP; 3128 break; 3129 } 3130 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 3131 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 3132 goto reset; 3133 case MAC_PROP_EN_10HDX_CAP: 3134 if (hw->phy.media_type != e1000_media_type_copper) { 3135 err = ENOTSUP; 3136 break; 3137 } 3138 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 3139 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 3140 goto reset; 3141 case MAC_PROP_AUTONEG: 3142 if (hw->phy.media_type != e1000_media_type_copper) { 3143 err = ENOTSUP; 3144 break; 3145 } 3146 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 3147 goto reset; 3148 case MAC_PROP_FLOWCTRL: 3149 fc->send_xon = B_TRUE; 3150 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 3151 3152 switch (flowctrl) { 3153 default: 3154 err = EINVAL; 3155 break; 3156 case LINK_FLOWCTRL_NONE: 3157 fc->requested_mode = e1000_fc_none; 3158 break; 3159 case LINK_FLOWCTRL_RX: 3160 fc->requested_mode = e1000_fc_rx_pause; 3161 break; 3162 case LINK_FLOWCTRL_TX: 3163 fc->requested_mode = e1000_fc_tx_pause; 3164 break; 3165 case LINK_FLOWCTRL_BI: 3166 fc->requested_mode = e1000_fc_full; 3167 break; 3168 } 3169 reset: 3170 if (err == 0) { 3171 /* check PCH limits & reset the link */ 3172 e1000g_pch_limits(Adapter); 3173 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 3174 err = EINVAL; 3175 } 3176 break; 3177 case MAC_PROP_ADV_1000FDX_CAP: 3178 case MAC_PROP_ADV_1000HDX_CAP: 3179 case MAC_PROP_ADV_100FDX_CAP: 3180 case MAC_PROP_ADV_100HDX_CAP: 3181 case MAC_PROP_ADV_10FDX_CAP: 3182 case MAC_PROP_ADV_10HDX_CAP: 3183 case MAC_PROP_EN_1000HDX_CAP: 3184 case MAC_PROP_STATUS: 3185 case MAC_PROP_SPEED: 3186 case MAC_PROP_DUPLEX: 3187 err = ENOTSUP; /* read-only prop. Can't set this. */ 3188 break; 3189 case MAC_PROP_MTU: 3190 /* adapter must be stopped for an MTU change */ 3191 if (Adapter->e1000g_state & E1000G_STARTED) { 3192 err = EBUSY; 3193 break; 3194 } 3195 3196 cur_mtu = Adapter->default_mtu; 3197 3198 /* get new requested MTU */ 3199 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 3200 if (new_mtu == cur_mtu) { 3201 err = 0; 3202 break; 3203 } 3204 3205 if ((new_mtu < DEFAULT_MTU) || 3206 (new_mtu > Adapter->max_mtu)) { 3207 err = EINVAL; 3208 break; 3209 } 3210 3211 /* inform MAC framework of new MTU */ 3212 err = mac_maxsdu_update(Adapter->mh, new_mtu); 3213 3214 if (err == 0) { 3215 Adapter->default_mtu = new_mtu; 3216 Adapter->max_frame_size = 3217 e1000g_mtu2maxframe(new_mtu); 3218 3219 /* 3220 * check PCH limits & set buffer sizes to 3221 * match new MTU 3222 */ 3223 e1000g_pch_limits(Adapter); 3224 e1000g_set_bufsize(Adapter); 3225 3226 /* 3227 * decrease the number of descriptors and free 3228 * packets for jumbo frames to reduce tx/rx 3229 * resource consumption 3230 */ 3231 if (Adapter->max_frame_size >= 3232 (FRAME_SIZE_UPTO_4K - 3233 E1000G_IPALIGNPRESERVEROOM)) { 3234 3235 if (Adapter->tx_desc_num_flag == 0) 3236 Adapter->tx_desc_num = 3237 DEFAULT_JUMBO_NUM_TX_DESC; 3238 3239 if (Adapter->rx_desc_num_flag == 0) 3240 Adapter->rx_desc_num = 3241 DEFAULT_JUMBO_NUM_RX_DESC; 3242 3243 if (Adapter->tx_buf_num_flag == 0) 3244 Adapter->tx_freelist_num = 3245 DEFAULT_JUMBO_NUM_TX_BUF; 3246 3247 if (Adapter->rx_buf_num_flag == 0) 3248 Adapter->rx_freelist_num = 3249 DEFAULT_JUMBO_NUM_RX_BUF; 3250 } else { 3251 if (Adapter->tx_desc_num_flag == 0) 3252 Adapter->tx_desc_num = 3253 DEFAULT_NUM_TX_DESCRIPTOR; 3254 3255 if (Adapter->rx_desc_num_flag == 0) 3256 Adapter->rx_desc_num = 3257 DEFAULT_NUM_RX_DESCRIPTOR; 3258 3259 if (Adapter->tx_buf_num_flag == 0) 3260 Adapter->tx_freelist_num = 3261 DEFAULT_NUM_TX_FREELIST; 3262 3263 if (Adapter->rx_buf_num_flag == 0) 3264 Adapter->rx_freelist_num = 3265 DEFAULT_NUM_RX_FREELIST; 3266 } 3267 } 3268 break; 3269 case MAC_PROP_PRIVATE: 3270 err = e1000g_set_priv_prop(Adapter, pr_name, 3271 pr_valsize, pr_val); 3272 break; 3273 default: 3274 err = ENOTSUP; 3275 break; 3276 } 3277 rw_exit(&Adapter->chip_lock); 3278 return (err); 3279 } 3280 3281 static int 3282 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3283 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3284 { 3285 struct e1000g *Adapter = arg; 3286 struct e1000_fc_info *fc = &Adapter->shared.fc; 3287 struct e1000_hw *hw = &Adapter->shared; 3288 int err = 0; 3289 link_flowctrl_t flowctrl; 3290 uint64_t tmp = 0; 3291 3292 if (pr_valsize == 0) 3293 return (EINVAL); 3294 3295 *perm = MAC_PROP_PERM_RW; 3296 3297 bzero(pr_val, pr_valsize); 3298 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 3299 return (e1000g_get_def_val(Adapter, pr_num, 3300 pr_valsize, pr_val)); 3301 } 3302 3303 switch (pr_num) { 3304 case MAC_PROP_DUPLEX: 3305 *perm = MAC_PROP_PERM_READ; 3306 if (pr_valsize >= sizeof (link_duplex_t)) { 3307 bcopy(&Adapter->link_duplex, pr_val, 3308 sizeof (link_duplex_t)); 3309 } else 3310 err = EINVAL; 3311 break; 3312 case MAC_PROP_SPEED: 3313 *perm = MAC_PROP_PERM_READ; 3314 if (pr_valsize >= sizeof (uint64_t)) { 3315 tmp = Adapter->link_speed * 1000000ull; 3316 bcopy(&tmp, pr_val, sizeof (tmp)); 3317 } else 3318 err = EINVAL; 3319 break; 3320 case MAC_PROP_AUTONEG: 3321 if (hw->phy.media_type != e1000_media_type_copper) 3322 *perm = MAC_PROP_PERM_READ; 3323 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 3324 break; 3325 case MAC_PROP_FLOWCTRL: 3326 if (pr_valsize >= sizeof (link_flowctrl_t)) { 3327 switch (fc->current_mode) { 3328 case e1000_fc_none: 3329 flowctrl = LINK_FLOWCTRL_NONE; 3330 break; 3331 case e1000_fc_rx_pause: 3332 flowctrl = LINK_FLOWCTRL_RX; 3333 break; 3334 case e1000_fc_tx_pause: 3335 flowctrl = LINK_FLOWCTRL_TX; 3336 break; 3337 case e1000_fc_full: 3338 flowctrl = LINK_FLOWCTRL_BI; 3339 break; 3340 } 3341 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 3342 } else 3343 err = EINVAL; 3344 break; 3345 case MAC_PROP_ADV_1000FDX_CAP: 3346 *perm = MAC_PROP_PERM_READ; 3347 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 3348 break; 3349 case MAC_PROP_EN_1000FDX_CAP: 3350 if (hw->phy.media_type != e1000_media_type_copper) 3351 *perm = MAC_PROP_PERM_READ; 3352 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 3353 break; 3354 case MAC_PROP_ADV_1000HDX_CAP: 3355 *perm = MAC_PROP_PERM_READ; 3356 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 3357 break; 3358 case MAC_PROP_EN_1000HDX_CAP: 3359 *perm = MAC_PROP_PERM_READ; 3360 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 3361 break; 3362 case MAC_PROP_ADV_100FDX_CAP: 3363 *perm = MAC_PROP_PERM_READ; 3364 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 3365 break; 3366 case MAC_PROP_EN_100FDX_CAP: 3367 if (hw->phy.media_type != e1000_media_type_copper) 3368 *perm = MAC_PROP_PERM_READ; 3369 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 3370 break; 3371 case MAC_PROP_ADV_100HDX_CAP: 3372 *perm = MAC_PROP_PERM_READ; 3373 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 3374 break; 3375 case MAC_PROP_EN_100HDX_CAP: 3376 if (hw->phy.media_type != e1000_media_type_copper) 3377 *perm = MAC_PROP_PERM_READ; 3378 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 3379 break; 3380 case MAC_PROP_ADV_10FDX_CAP: 3381 *perm = MAC_PROP_PERM_READ; 3382 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 3383 break; 3384 case MAC_PROP_EN_10FDX_CAP: 3385 if (hw->phy.media_type != e1000_media_type_copper) 3386 *perm = MAC_PROP_PERM_READ; 3387 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 3388 break; 3389 case MAC_PROP_ADV_10HDX_CAP: 3390 *perm = MAC_PROP_PERM_READ; 3391 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 3392 break; 3393 case MAC_PROP_EN_10HDX_CAP: 3394 if (hw->phy.media_type != e1000_media_type_copper) 3395 *perm = MAC_PROP_PERM_READ; 3396 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 3397 break; 3398 case MAC_PROP_ADV_100T4_CAP: 3399 case MAC_PROP_EN_100T4_CAP: 3400 *perm = MAC_PROP_PERM_READ; 3401 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 3402 break; 3403 case MAC_PROP_PRIVATE: 3404 err = e1000g_get_priv_prop(Adapter, pr_name, 3405 pr_flags, pr_valsize, pr_val, perm); 3406 break; 3407 case MAC_PROP_MTU: { 3408 struct e1000_mac_info *mac = &Adapter->shared.mac; 3409 struct e1000_phy_info *phy = &Adapter->shared.phy; 3410 mac_propval_range_t range; 3411 3412 if (!(pr_flags & MAC_PROP_POSSIBLE)) 3413 return (ENOTSUP); 3414 if (pr_valsize < sizeof (mac_propval_range_t)) 3415 return (EINVAL); 3416 range.mpr_count = 1; 3417 range.mpr_type = MAC_PROPVAL_UINT32; 3418 range.range_uint32[0].mpur_min = DEFAULT_MTU; 3419 range.range_uint32[0].mpur_max = Adapter->max_mtu; 3420 /* following MAC type do not support jumbo frames */ 3421 if ((mac->type == e1000_ich8lan) || 3422 ((mac->type == e1000_ich9lan) && (phy->type == 3423 e1000_phy_ife))) { 3424 range.range_uint32[0].mpur_max = DEFAULT_MTU; 3425 } 3426 bcopy(&range, pr_val, sizeof (range)); 3427 break; 3428 } 3429 default: 3430 err = ENOTSUP; 3431 break; 3432 } 3433 return (err); 3434 } 3435 3436 /* ARGSUSED2 */ 3437 static int 3438 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 3439 uint_t pr_valsize, const void *pr_val) 3440 { 3441 int err = 0; 3442 long result; 3443 struct e1000_hw *hw = &Adapter->shared; 3444 3445 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3446 if (pr_val == NULL) { 3447 err = EINVAL; 3448 return (err); 3449 } 3450 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3451 if (result < MIN_TX_BCOPY_THRESHOLD || 3452 result > MAX_TX_BCOPY_THRESHOLD) 3453 err = EINVAL; 3454 else { 3455 Adapter->tx_bcopy_thresh = (uint32_t)result; 3456 } 3457 return (err); 3458 } 3459 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3460 if (pr_val == NULL) { 3461 err = EINVAL; 3462 return (err); 3463 } 3464 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3465 if (result < 0 || result > 1) 3466 err = EINVAL; 3467 else { 3468 Adapter->tx_intr_enable = (result == 1) ? 3469 B_TRUE: B_FALSE; 3470 if (Adapter->tx_intr_enable) 3471 e1000g_mask_tx_interrupt(Adapter); 3472 else 3473 e1000g_clear_tx_interrupt(Adapter); 3474 if (e1000g_check_acc_handle( 3475 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3476 ddi_fm_service_impact(Adapter->dip, 3477 DDI_SERVICE_DEGRADED); 3478 err = EIO; 3479 } 3480 } 3481 return (err); 3482 } 3483 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3484 if (pr_val == NULL) { 3485 err = EINVAL; 3486 return (err); 3487 } 3488 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3489 if (result < MIN_TX_INTR_DELAY || 3490 result > MAX_TX_INTR_DELAY) 3491 err = EINVAL; 3492 else { 3493 Adapter->tx_intr_delay = (uint32_t)result; 3494 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 3495 if (e1000g_check_acc_handle( 3496 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3497 ddi_fm_service_impact(Adapter->dip, 3498 DDI_SERVICE_DEGRADED); 3499 err = EIO; 3500 } 3501 } 3502 return (err); 3503 } 3504 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3505 if (pr_val == NULL) { 3506 err = EINVAL; 3507 return (err); 3508 } 3509 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3510 if (result < MIN_TX_INTR_ABS_DELAY || 3511 result > MAX_TX_INTR_ABS_DELAY) 3512 err = EINVAL; 3513 else { 3514 Adapter->tx_intr_abs_delay = (uint32_t)result; 3515 E1000_WRITE_REG(hw, E1000_TADV, 3516 Adapter->tx_intr_abs_delay); 3517 if (e1000g_check_acc_handle( 3518 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3519 ddi_fm_service_impact(Adapter->dip, 3520 DDI_SERVICE_DEGRADED); 3521 err = EIO; 3522 } 3523 } 3524 return (err); 3525 } 3526 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3527 if (pr_val == NULL) { 3528 err = EINVAL; 3529 return (err); 3530 } 3531 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3532 if (result < MIN_RX_BCOPY_THRESHOLD || 3533 result > MAX_RX_BCOPY_THRESHOLD) 3534 err = EINVAL; 3535 else 3536 Adapter->rx_bcopy_thresh = (uint32_t)result; 3537 return (err); 3538 } 3539 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3540 if (pr_val == NULL) { 3541 err = EINVAL; 3542 return (err); 3543 } 3544 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3545 if (result < MIN_RX_LIMIT_ON_INTR || 3546 result > MAX_RX_LIMIT_ON_INTR) 3547 err = EINVAL; 3548 else 3549 Adapter->rx_limit_onintr = (uint32_t)result; 3550 return (err); 3551 } 3552 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3553 if (pr_val == NULL) { 3554 err = EINVAL; 3555 return (err); 3556 } 3557 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3558 if (result < MIN_RX_INTR_DELAY || 3559 result > MAX_RX_INTR_DELAY) 3560 err = EINVAL; 3561 else { 3562 Adapter->rx_intr_delay = (uint32_t)result; 3563 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3564 if (e1000g_check_acc_handle( 3565 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3566 ddi_fm_service_impact(Adapter->dip, 3567 DDI_SERVICE_DEGRADED); 3568 err = EIO; 3569 } 3570 } 3571 return (err); 3572 } 3573 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3574 if (pr_val == NULL) { 3575 err = EINVAL; 3576 return (err); 3577 } 3578 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3579 if (result < MIN_RX_INTR_ABS_DELAY || 3580 result > MAX_RX_INTR_ABS_DELAY) 3581 err = EINVAL; 3582 else { 3583 Adapter->rx_intr_abs_delay = (uint32_t)result; 3584 E1000_WRITE_REG(hw, E1000_RADV, 3585 Adapter->rx_intr_abs_delay); 3586 if (e1000g_check_acc_handle( 3587 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3588 ddi_fm_service_impact(Adapter->dip, 3589 DDI_SERVICE_DEGRADED); 3590 err = EIO; 3591 } 3592 } 3593 return (err); 3594 } 3595 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3596 if (pr_val == NULL) { 3597 err = EINVAL; 3598 return (err); 3599 } 3600 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3601 if (result < MIN_INTR_THROTTLING || 3602 result > MAX_INTR_THROTTLING) 3603 err = EINVAL; 3604 else { 3605 if (hw->mac.type >= e1000_82540) { 3606 Adapter->intr_throttling_rate = 3607 (uint32_t)result; 3608 E1000_WRITE_REG(hw, E1000_ITR, 3609 Adapter->intr_throttling_rate); 3610 if (e1000g_check_acc_handle( 3611 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3612 ddi_fm_service_impact(Adapter->dip, 3613 DDI_SERVICE_DEGRADED); 3614 err = EIO; 3615 } 3616 } else 3617 err = EINVAL; 3618 } 3619 return (err); 3620 } 3621 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3622 if (pr_val == NULL) { 3623 err = EINVAL; 3624 return (err); 3625 } 3626 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3627 if (result < 0 || result > 1) 3628 err = EINVAL; 3629 else { 3630 if (hw->mac.type >= e1000_82540) { 3631 Adapter->intr_adaptive = (result == 1) ? 3632 B_TRUE : B_FALSE; 3633 } else { 3634 err = EINVAL; 3635 } 3636 } 3637 return (err); 3638 } 3639 return (ENOTSUP); 3640 } 3641 3642 static int 3643 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3644 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3645 { 3646 int err = ENOTSUP; 3647 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3648 int value; 3649 3650 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3651 *perm = MAC_PROP_PERM_READ; 3652 if (is_default) 3653 goto done; 3654 value = Adapter->param_adv_pause; 3655 err = 0; 3656 goto done; 3657 } 3658 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3659 *perm = MAC_PROP_PERM_READ; 3660 if (is_default) 3661 goto done; 3662 value = Adapter->param_adv_asym_pause; 3663 err = 0; 3664 goto done; 3665 } 3666 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3667 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3668 Adapter->tx_bcopy_thresh); 3669 err = 0; 3670 goto done; 3671 } 3672 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3673 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3674 Adapter->tx_intr_enable); 3675 err = 0; 3676 goto done; 3677 } 3678 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3679 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3680 Adapter->tx_intr_delay); 3681 err = 0; 3682 goto done; 3683 } 3684 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3685 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3686 Adapter->tx_intr_abs_delay); 3687 err = 0; 3688 goto done; 3689 } 3690 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3691 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3692 Adapter->rx_bcopy_thresh); 3693 err = 0; 3694 goto done; 3695 } 3696 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3697 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3698 Adapter->rx_limit_onintr); 3699 err = 0; 3700 goto done; 3701 } 3702 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3703 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3704 Adapter->rx_intr_delay); 3705 err = 0; 3706 goto done; 3707 } 3708 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3709 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3710 Adapter->rx_intr_abs_delay); 3711 err = 0; 3712 goto done; 3713 } 3714 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3715 value = (is_default ? DEFAULT_INTR_THROTTLING : 3716 Adapter->intr_throttling_rate); 3717 err = 0; 3718 goto done; 3719 } 3720 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3721 value = (is_default ? 1 : Adapter->intr_adaptive); 3722 err = 0; 3723 goto done; 3724 } 3725 done: 3726 if (err == 0) { 3727 (void) snprintf(pr_val, pr_valsize, "%d", value); 3728 } 3729 return (err); 3730 } 3731 3732 /* 3733 * e1000g_get_conf - get configurations set in e1000g.conf 3734 * This routine gets user-configured values out of the configuration 3735 * file e1000g.conf. 3736 * 3737 * For each configurable value, there is a minimum, a maximum, and a 3738 * default. 3739 * If user does not configure a value, use the default. 3740 * If user configures below the minimum, use the minumum. 3741 * If user configures above the maximum, use the maxumum. 3742 */ 3743 static void 3744 e1000g_get_conf(struct e1000g *Adapter) 3745 { 3746 struct e1000_hw *hw = &Adapter->shared; 3747 boolean_t tbi_compatibility = B_FALSE; 3748 boolean_t is_jumbo = B_FALSE; 3749 int propval; 3750 /* 3751 * decrease the number of descriptors and free packets 3752 * for jumbo frames to reduce tx/rx resource consumption 3753 */ 3754 if (Adapter->max_frame_size >= 3755 (FRAME_SIZE_UPTO_4K - 3756 E1000G_IPALIGNPRESERVEROOM)) { 3757 is_jumbo = B_TRUE; 3758 } 3759 3760 /* 3761 * get each configurable property from e1000g.conf 3762 */ 3763 3764 /* 3765 * NumTxDescriptors 3766 */ 3767 Adapter->tx_desc_num_flag = 3768 e1000g_get_prop(Adapter, "NumTxDescriptors", 3769 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3770 is_jumbo ? DEFAULT_JUMBO_NUM_TX_DESC 3771 : DEFAULT_NUM_TX_DESCRIPTOR, &propval); 3772 Adapter->tx_desc_num = propval; 3773 3774 /* 3775 * NumRxDescriptors 3776 */ 3777 Adapter->rx_desc_num_flag = 3778 e1000g_get_prop(Adapter, "NumRxDescriptors", 3779 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3780 is_jumbo ? DEFAULT_JUMBO_NUM_RX_DESC 3781 : DEFAULT_NUM_RX_DESCRIPTOR, &propval); 3782 Adapter->rx_desc_num = propval; 3783 3784 /* 3785 * NumRxFreeList 3786 */ 3787 Adapter->rx_buf_num_flag = 3788 e1000g_get_prop(Adapter, "NumRxFreeList", 3789 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3790 is_jumbo ? DEFAULT_JUMBO_NUM_RX_BUF 3791 : DEFAULT_NUM_RX_FREELIST, &propval); 3792 Adapter->rx_freelist_num = propval; 3793 3794 /* 3795 * NumTxPacketList 3796 */ 3797 Adapter->tx_buf_num_flag = 3798 e1000g_get_prop(Adapter, "NumTxPacketList", 3799 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3800 is_jumbo ? DEFAULT_JUMBO_NUM_TX_BUF 3801 : DEFAULT_NUM_TX_FREELIST, &propval); 3802 Adapter->tx_freelist_num = propval; 3803 3804 /* 3805 * FlowControl 3806 */ 3807 hw->fc.send_xon = B_TRUE; 3808 (void) e1000g_get_prop(Adapter, "FlowControl", 3809 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL, &propval); 3810 hw->fc.requested_mode = propval; 3811 /* 4 is the setting that says "let the eeprom decide" */ 3812 if (hw->fc.requested_mode == 4) 3813 hw->fc.requested_mode = e1000_fc_default; 3814 3815 /* 3816 * Max Num Receive Packets on Interrupt 3817 */ 3818 (void) e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3819 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3820 DEFAULT_RX_LIMIT_ON_INTR, &propval); 3821 Adapter->rx_limit_onintr = propval; 3822 3823 /* 3824 * PHY master slave setting 3825 */ 3826 (void) e1000g_get_prop(Adapter, "SetMasterSlave", 3827 e1000_ms_hw_default, e1000_ms_auto, 3828 e1000_ms_hw_default, &propval); 3829 hw->phy.ms_type = propval; 3830 3831 /* 3832 * Parameter which controls TBI mode workaround, which is only 3833 * needed on certain switches such as Cisco 6500/Foundry 3834 */ 3835 (void) e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3836 0, 1, DEFAULT_TBI_COMPAT_ENABLE, &propval); 3837 tbi_compatibility = (propval == 1); 3838 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3839 3840 /* 3841 * MSI Enable 3842 */ 3843 (void) e1000g_get_prop(Adapter, "MSIEnable", 3844 0, 1, DEFAULT_MSI_ENABLE, &propval); 3845 Adapter->msi_enable = (propval == 1); 3846 3847 /* 3848 * Interrupt Throttling Rate 3849 */ 3850 (void) e1000g_get_prop(Adapter, "intr_throttling_rate", 3851 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3852 DEFAULT_INTR_THROTTLING, &propval); 3853 Adapter->intr_throttling_rate = propval; 3854 3855 /* 3856 * Adaptive Interrupt Blanking Enable/Disable 3857 * It is enabled by default 3858 */ 3859 (void) e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1, 3860 &propval); 3861 Adapter->intr_adaptive = (propval == 1); 3862 3863 /* 3864 * Hardware checksum enable/disable parameter 3865 */ 3866 (void) e1000g_get_prop(Adapter, "tx_hcksum_enable", 3867 0, 1, DEFAULT_TX_HCKSUM_ENABLE, &propval); 3868 Adapter->tx_hcksum_enable = (propval == 1); 3869 /* 3870 * Checksum on/off selection via global parameters. 3871 * 3872 * If the chip is flagged as not capable of (correctly) 3873 * handling checksumming, we don't enable it on either 3874 * Rx or Tx side. Otherwise, we take this chip's settings 3875 * from the patchable global defaults. 3876 * 3877 * We advertise our capabilities only if TX offload is 3878 * enabled. On receive, the stack will accept checksummed 3879 * packets anyway, even if we haven't said we can deliver 3880 * them. 3881 */ 3882 switch (hw->mac.type) { 3883 case e1000_82540: 3884 case e1000_82544: 3885 case e1000_82545: 3886 case e1000_82545_rev_3: 3887 case e1000_82546: 3888 case e1000_82546_rev_3: 3889 case e1000_82571: 3890 case e1000_82572: 3891 case e1000_82573: 3892 case e1000_80003es2lan: 3893 break; 3894 /* 3895 * For the following Intel PRO/1000 chipsets, we have not 3896 * tested the hardware checksum offload capability, so we 3897 * disable the capability for them. 3898 * e1000_82542, 3899 * e1000_82543, 3900 * e1000_82541, 3901 * e1000_82541_rev_2, 3902 * e1000_82547, 3903 * e1000_82547_rev_2, 3904 */ 3905 default: 3906 Adapter->tx_hcksum_enable = B_FALSE; 3907 } 3908 3909 /* 3910 * Large Send Offloading(LSO) Enable/Disable 3911 * If the tx hardware checksum is not enabled, LSO should be 3912 * disabled. 3913 */ 3914 (void) e1000g_get_prop(Adapter, "lso_enable", 3915 0, 1, DEFAULT_LSO_ENABLE, &propval); 3916 Adapter->lso_enable = (propval == 1); 3917 3918 switch (hw->mac.type) { 3919 case e1000_82546: 3920 case e1000_82546_rev_3: 3921 if (Adapter->lso_enable) 3922 Adapter->lso_premature_issue = B_TRUE; 3923 /* FALLTHRU */ 3924 case e1000_82571: 3925 case e1000_82572: 3926 case e1000_82573: 3927 case e1000_80003es2lan: 3928 break; 3929 default: 3930 Adapter->lso_enable = B_FALSE; 3931 } 3932 3933 if (!Adapter->tx_hcksum_enable) { 3934 Adapter->lso_premature_issue = B_FALSE; 3935 Adapter->lso_enable = B_FALSE; 3936 } 3937 3938 /* 3939 * If mem_workaround_82546 is enabled, the rx buffer allocated by 3940 * e1000_82545, e1000_82546 and e1000_82546_rev_3 3941 * will not cross 64k boundary. 3942 */ 3943 (void) e1000g_get_prop(Adapter, "mem_workaround_82546", 3944 0, 1, DEFAULT_MEM_WORKAROUND_82546, &propval); 3945 Adapter->mem_workaround_82546 = (propval == 1); 3946 3947 /* 3948 * Max number of multicast addresses 3949 */ 3950 (void) e1000g_get_prop(Adapter, "mcast_max_num", 3951 MIN_MCAST_NUM, MAX_MCAST_NUM, hw->mac.mta_reg_count * 32, 3952 &propval); 3953 Adapter->mcast_max_num = propval; 3954 } 3955 3956 /* 3957 * e1000g_get_prop - routine to read properties 3958 * 3959 * Get a user-configure property value out of the configuration 3960 * file e1000g.conf. 3961 * 3962 * Caller provides name of the property, a default value, a minimum 3963 * value, a maximum value and a pointer to the returned property 3964 * value. 3965 * 3966 * Return B_TRUE if the configured value of the property is not a default 3967 * value, otherwise return B_FALSE. 3968 */ 3969 static boolean_t 3970 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3971 char *propname, /* name of the property */ 3972 int minval, /* minimum acceptable value */ 3973 int maxval, /* maximim acceptable value */ 3974 int defval, /* default value */ 3975 int *propvalue) /* property value return to caller */ 3976 { 3977 int propval; /* value returned for requested property */ 3978 int *props; /* point to array of properties returned */ 3979 uint_t nprops; /* number of property value returned */ 3980 boolean_t ret = B_TRUE; 3981 3982 /* 3983 * get the array of properties from the config file 3984 */ 3985 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3986 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3987 /* got some properties, test if we got enough */ 3988 if (Adapter->instance < nprops) { 3989 propval = props[Adapter->instance]; 3990 } else { 3991 /* not enough properties configured */ 3992 propval = defval; 3993 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3994 "Not Enough %s values found in e1000g.conf" 3995 " - set to %d\n", 3996 propname, propval); 3997 ret = B_FALSE; 3998 } 3999 4000 /* free memory allocated for properties */ 4001 ddi_prop_free(props); 4002 4003 } else { 4004 propval = defval; 4005 ret = B_FALSE; 4006 } 4007 4008 /* 4009 * enforce limits 4010 */ 4011 if (propval > maxval) { 4012 propval = maxval; 4013 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4014 "Too High %s value in e1000g.conf - set to %d\n", 4015 propname, propval); 4016 } 4017 4018 if (propval < minval) { 4019 propval = minval; 4020 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4021 "Too Low %s value in e1000g.conf - set to %d\n", 4022 propname, propval); 4023 } 4024 4025 *propvalue = propval; 4026 return (ret); 4027 } 4028 4029 static boolean_t 4030 e1000g_link_check(struct e1000g *Adapter) 4031 { 4032 uint16_t speed, duplex, phydata; 4033 boolean_t link_changed = B_FALSE; 4034 struct e1000_hw *hw; 4035 uint32_t reg_tarc; 4036 4037 hw = &Adapter->shared; 4038 4039 if (e1000g_link_up(Adapter)) { 4040 /* 4041 * The Link is up, check whether it was marked as down earlier 4042 */ 4043 if (Adapter->link_state != LINK_STATE_UP) { 4044 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 4045 Adapter->link_speed = speed; 4046 Adapter->link_duplex = duplex; 4047 Adapter->link_state = LINK_STATE_UP; 4048 link_changed = B_TRUE; 4049 4050 if (Adapter->link_speed == SPEED_1000) 4051 Adapter->stall_threshold = TX_STALL_TIME_2S; 4052 else 4053 Adapter->stall_threshold = TX_STALL_TIME_8S; 4054 4055 Adapter->tx_link_down_timeout = 0; 4056 4057 if ((hw->mac.type == e1000_82571) || 4058 (hw->mac.type == e1000_82572)) { 4059 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 4060 if (speed == SPEED_1000) 4061 reg_tarc |= (1 << 21); 4062 else 4063 reg_tarc &= ~(1 << 21); 4064 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 4065 } 4066 } 4067 Adapter->smartspeed = 0; 4068 } else { 4069 if (Adapter->link_state != LINK_STATE_DOWN) { 4070 Adapter->link_speed = 0; 4071 Adapter->link_duplex = 0; 4072 Adapter->link_state = LINK_STATE_DOWN; 4073 link_changed = B_TRUE; 4074 4075 /* 4076 * SmartSpeed workaround for Tabor/TanaX, When the 4077 * driver loses link disable auto master/slave 4078 * resolution. 4079 */ 4080 if (hw->phy.type == e1000_phy_igp) { 4081 (void) e1000_read_phy_reg(hw, 4082 PHY_1000T_CTRL, &phydata); 4083 phydata |= CR_1000T_MS_ENABLE; 4084 (void) e1000_write_phy_reg(hw, 4085 PHY_1000T_CTRL, phydata); 4086 } 4087 } else { 4088 e1000g_smartspeed(Adapter); 4089 } 4090 4091 if (Adapter->e1000g_state & E1000G_STARTED) { 4092 if (Adapter->tx_link_down_timeout < 4093 MAX_TX_LINK_DOWN_TIMEOUT) { 4094 Adapter->tx_link_down_timeout++; 4095 } else if (Adapter->tx_link_down_timeout == 4096 MAX_TX_LINK_DOWN_TIMEOUT) { 4097 e1000g_tx_clean(Adapter); 4098 Adapter->tx_link_down_timeout++; 4099 } 4100 } 4101 } 4102 4103 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4104 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4105 4106 return (link_changed); 4107 } 4108 4109 /* 4110 * e1000g_reset_link - Using the link properties to setup the link 4111 */ 4112 int 4113 e1000g_reset_link(struct e1000g *Adapter) 4114 { 4115 struct e1000_mac_info *mac; 4116 struct e1000_phy_info *phy; 4117 struct e1000_hw *hw; 4118 boolean_t invalid; 4119 4120 mac = &Adapter->shared.mac; 4121 phy = &Adapter->shared.phy; 4122 hw = &Adapter->shared; 4123 invalid = B_FALSE; 4124 4125 if (hw->phy.media_type != e1000_media_type_copper) 4126 goto out; 4127 4128 if (Adapter->param_adv_autoneg == 1) { 4129 mac->autoneg = B_TRUE; 4130 phy->autoneg_advertised = 0; 4131 4132 /* 4133 * 1000hdx is not supported for autonegotiation 4134 */ 4135 if (Adapter->param_adv_1000fdx == 1) 4136 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 4137 4138 if (Adapter->param_adv_100fdx == 1) 4139 phy->autoneg_advertised |= ADVERTISE_100_FULL; 4140 4141 if (Adapter->param_adv_100hdx == 1) 4142 phy->autoneg_advertised |= ADVERTISE_100_HALF; 4143 4144 if (Adapter->param_adv_10fdx == 1) 4145 phy->autoneg_advertised |= ADVERTISE_10_FULL; 4146 4147 if (Adapter->param_adv_10hdx == 1) 4148 phy->autoneg_advertised |= ADVERTISE_10_HALF; 4149 4150 if (phy->autoneg_advertised == 0) 4151 invalid = B_TRUE; 4152 } else { 4153 mac->autoneg = B_FALSE; 4154 4155 /* 4156 * For Intel copper cards, 1000fdx and 1000hdx are not 4157 * supported for forced link 4158 */ 4159 if (Adapter->param_adv_100fdx == 1) 4160 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4161 else if (Adapter->param_adv_100hdx == 1) 4162 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4163 else if (Adapter->param_adv_10fdx == 1) 4164 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4165 else if (Adapter->param_adv_10hdx == 1) 4166 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4167 else 4168 invalid = B_TRUE; 4169 4170 } 4171 4172 if (invalid) { 4173 e1000g_log(Adapter, CE_WARN, 4174 "Invalid link settings. Setup link to " 4175 "support autonegotiation with all link capabilities."); 4176 mac->autoneg = B_TRUE; 4177 phy->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 4178 } 4179 4180 out: 4181 return (e1000_setup_link(&Adapter->shared)); 4182 } 4183 4184 static void 4185 e1000g_timer_tx_resched(struct e1000g *Adapter) 4186 { 4187 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 4188 4189 rw_enter(&Adapter->chip_lock, RW_READER); 4190 4191 if (tx_ring->resched_needed && 4192 ((ddi_get_lbolt() - tx_ring->resched_timestamp) > 4193 drv_usectohz(1000000)) && 4194 (Adapter->e1000g_state & E1000G_STARTED) && 4195 (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) { 4196 tx_ring->resched_needed = B_FALSE; 4197 mac_tx_update(Adapter->mh); 4198 E1000G_STAT(tx_ring->stat_reschedule); 4199 E1000G_STAT(tx_ring->stat_timer_reschedule); 4200 } 4201 4202 rw_exit(&Adapter->chip_lock); 4203 } 4204 4205 static void 4206 e1000g_local_timer(void *ws) 4207 { 4208 struct e1000g *Adapter = (struct e1000g *)ws; 4209 struct e1000_hw *hw; 4210 e1000g_ether_addr_t ether_addr; 4211 boolean_t link_changed; 4212 4213 hw = &Adapter->shared; 4214 4215 if (Adapter->e1000g_state & E1000G_ERROR) { 4216 rw_enter(&Adapter->chip_lock, RW_WRITER); 4217 Adapter->e1000g_state &= ~E1000G_ERROR; 4218 rw_exit(&Adapter->chip_lock); 4219 4220 Adapter->reset_count++; 4221 if (e1000g_global_reset(Adapter)) { 4222 ddi_fm_service_impact(Adapter->dip, 4223 DDI_SERVICE_RESTORED); 4224 e1000g_timer_tx_resched(Adapter); 4225 } else 4226 ddi_fm_service_impact(Adapter->dip, 4227 DDI_SERVICE_LOST); 4228 return; 4229 } 4230 4231 if (e1000g_stall_check(Adapter)) { 4232 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4233 "Tx stall detected. Activate automatic recovery.\n"); 4234 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 4235 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 4236 Adapter->reset_count++; 4237 if (e1000g_reset_adapter(Adapter)) { 4238 ddi_fm_service_impact(Adapter->dip, 4239 DDI_SERVICE_RESTORED); 4240 e1000g_timer_tx_resched(Adapter); 4241 } 4242 return; 4243 } 4244 4245 link_changed = B_FALSE; 4246 rw_enter(&Adapter->chip_lock, RW_READER); 4247 if (Adapter->link_complete) 4248 link_changed = e1000g_link_check(Adapter); 4249 rw_exit(&Adapter->chip_lock); 4250 4251 if (link_changed) { 4252 if (!Adapter->reset_flag) 4253 mac_link_update(Adapter->mh, Adapter->link_state); 4254 if (Adapter->link_state == LINK_STATE_UP) 4255 Adapter->reset_flag = B_FALSE; 4256 } 4257 /* 4258 * Workaround for esb2. Data stuck in fifo on a link 4259 * down event. Reset the adapter to recover it. 4260 */ 4261 if (Adapter->esb2_workaround) { 4262 Adapter->esb2_workaround = B_FALSE; 4263 (void) e1000g_reset_adapter(Adapter); 4264 return; 4265 } 4266 4267 /* 4268 * With 82571 controllers, any locally administered address will 4269 * be overwritten when there is a reset on the other port. 4270 * Detect this circumstance and correct it. 4271 */ 4272 if ((hw->mac.type == e1000_82571) && 4273 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 4274 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 4275 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 4276 4277 ether_addr.reg.low = ntohl(ether_addr.reg.low); 4278 ether_addr.reg.high = ntohl(ether_addr.reg.high); 4279 4280 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 4281 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 4282 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 4283 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 4284 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 4285 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 4286 e1000_rar_set(hw, hw->mac.addr, 0); 4287 } 4288 } 4289 4290 /* 4291 * Long TTL workaround for 82541/82547 4292 */ 4293 (void) e1000_igp_ttl_workaround_82547(hw); 4294 4295 /* 4296 * Check for Adaptive IFS settings If there are lots of collisions 4297 * change the value in steps... 4298 * These properties should only be set for 10/100 4299 */ 4300 if ((hw->phy.media_type == e1000_media_type_copper) && 4301 ((Adapter->link_speed == SPEED_100) || 4302 (Adapter->link_speed == SPEED_10))) { 4303 e1000_update_adaptive(hw); 4304 } 4305 /* 4306 * Set Timer Interrupts 4307 */ 4308 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 4309 4310 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4311 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4312 else 4313 e1000g_timer_tx_resched(Adapter); 4314 4315 restart_watchdog_timer(Adapter); 4316 } 4317 4318 /* 4319 * The function e1000g_link_timer() is called when the timer for link setup 4320 * is expired, which indicates the completion of the link setup. The link 4321 * state will not be updated until the link setup is completed. And the 4322 * link state will not be sent to the upper layer through mac_link_update() 4323 * in this function. It will be updated in the local timer routine or the 4324 * interrupt service routine after the interface is started (plumbed). 4325 */ 4326 static void 4327 e1000g_link_timer(void *arg) 4328 { 4329 struct e1000g *Adapter = (struct e1000g *)arg; 4330 4331 mutex_enter(&Adapter->link_lock); 4332 Adapter->link_complete = B_TRUE; 4333 Adapter->link_tid = 0; 4334 mutex_exit(&Adapter->link_lock); 4335 } 4336 4337 /* 4338 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 4339 * 4340 * This function read the forced speed and duplex for 10/100 Mbps speeds 4341 * and also for 1000 Mbps speeds from the e1000g.conf file 4342 */ 4343 static void 4344 e1000g_force_speed_duplex(struct e1000g *Adapter) 4345 { 4346 int forced; 4347 int propval; 4348 struct e1000_mac_info *mac = &Adapter->shared.mac; 4349 struct e1000_phy_info *phy = &Adapter->shared.phy; 4350 4351 /* 4352 * get value out of config file 4353 */ 4354 (void) e1000g_get_prop(Adapter, "ForceSpeedDuplex", 4355 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY, &forced); 4356 4357 switch (forced) { 4358 case GDIAG_10_HALF: 4359 /* 4360 * Disable Auto Negotiation 4361 */ 4362 mac->autoneg = B_FALSE; 4363 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4364 break; 4365 case GDIAG_10_FULL: 4366 /* 4367 * Disable Auto Negotiation 4368 */ 4369 mac->autoneg = B_FALSE; 4370 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4371 break; 4372 case GDIAG_100_HALF: 4373 /* 4374 * Disable Auto Negotiation 4375 */ 4376 mac->autoneg = B_FALSE; 4377 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4378 break; 4379 case GDIAG_100_FULL: 4380 /* 4381 * Disable Auto Negotiation 4382 */ 4383 mac->autoneg = B_FALSE; 4384 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4385 break; 4386 case GDIAG_1000_FULL: 4387 /* 4388 * The gigabit spec requires autonegotiation. Therefore, 4389 * when the user wants to force the speed to 1000Mbps, we 4390 * enable AutoNeg, but only allow the harware to advertise 4391 * 1000Mbps. This is different from 10/100 operation, where 4392 * we are allowed to link without any negotiation. 4393 */ 4394 mac->autoneg = B_TRUE; 4395 phy->autoneg_advertised = ADVERTISE_1000_FULL; 4396 break; 4397 default: /* obey the setting of AutoNegAdvertised */ 4398 mac->autoneg = B_TRUE; 4399 (void) e1000g_get_prop(Adapter, "AutoNegAdvertised", 4400 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 4401 AUTONEG_ADVERTISE_SPEED_DEFAULT, &propval); 4402 phy->autoneg_advertised = (uint16_t)propval; 4403 break; 4404 } /* switch */ 4405 } 4406 4407 /* 4408 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 4409 * 4410 * This function reads MaxFrameSize from e1000g.conf 4411 */ 4412 static void 4413 e1000g_get_max_frame_size(struct e1000g *Adapter) 4414 { 4415 int max_frame; 4416 4417 /* 4418 * get value out of config file 4419 */ 4420 (void) e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0, 4421 &max_frame); 4422 4423 switch (max_frame) { 4424 case 0: 4425 Adapter->default_mtu = ETHERMTU; 4426 break; 4427 /* 4428 * To avoid excessive memory allocation for rx buffers, 4429 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 4430 */ 4431 case 1: 4432 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 4433 sizeof (struct ether_vlan_header) - ETHERFCSL - 4434 E1000G_IPALIGNPRESERVEROOM; 4435 break; 4436 case 2: 4437 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 4438 sizeof (struct ether_vlan_header) - ETHERFCSL - 4439 E1000G_IPALIGNPRESERVEROOM; 4440 break; 4441 case 3: 4442 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 4443 sizeof (struct ether_vlan_header) - ETHERFCSL - 4444 E1000G_IPALIGNPRESERVEROOM; 4445 break; 4446 default: 4447 Adapter->default_mtu = ETHERMTU; 4448 break; 4449 } /* switch */ 4450 4451 /* 4452 * If the user configed MTU is larger than the deivce's maximum MTU, 4453 * the MTU is set to the deivce's maximum value. 4454 */ 4455 if (Adapter->default_mtu > Adapter->max_mtu) 4456 Adapter->default_mtu = Adapter->max_mtu; 4457 4458 Adapter->max_frame_size = e1000g_mtu2maxframe(Adapter->default_mtu); 4459 } 4460 4461 /* 4462 * e1000g_pch_limits - Apply limits of the PCH silicon type 4463 * 4464 * At any frame size larger than the ethernet default, 4465 * prevent linking at 10/100 speeds. 4466 */ 4467 static void 4468 e1000g_pch_limits(struct e1000g *Adapter) 4469 { 4470 struct e1000_hw *hw = &Adapter->shared; 4471 4472 /* only applies to PCH silicon type */ 4473 if (hw->mac.type != e1000_pchlan) 4474 return; 4475 4476 /* only applies to frames larger than ethernet default */ 4477 if (Adapter->max_frame_size > DEFAULT_FRAME_SIZE) { 4478 hw->mac.autoneg = B_TRUE; 4479 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL; 4480 4481 Adapter->param_adv_autoneg = 1; 4482 Adapter->param_adv_1000fdx = 1; 4483 4484 Adapter->param_adv_100fdx = 0; 4485 Adapter->param_adv_100hdx = 0; 4486 Adapter->param_adv_10fdx = 0; 4487 Adapter->param_adv_10hdx = 0; 4488 4489 e1000g_param_sync(Adapter); 4490 } 4491 } 4492 4493 /* 4494 * e1000g_mtu2maxframe - convert given MTU to maximum frame size 4495 */ 4496 static uint32_t 4497 e1000g_mtu2maxframe(uint32_t mtu) 4498 { 4499 uint32_t maxframe; 4500 4501 maxframe = mtu + sizeof (struct ether_vlan_header) + ETHERFCSL; 4502 4503 return (maxframe); 4504 } 4505 4506 static void 4507 arm_watchdog_timer(struct e1000g *Adapter) 4508 { 4509 Adapter->watchdog_tid = 4510 timeout(e1000g_local_timer, 4511 (void *)Adapter, 1 * drv_usectohz(1000000)); 4512 } 4513 #pragma inline(arm_watchdog_timer) 4514 4515 static void 4516 enable_watchdog_timer(struct e1000g *Adapter) 4517 { 4518 mutex_enter(&Adapter->watchdog_lock); 4519 4520 if (!Adapter->watchdog_timer_enabled) { 4521 Adapter->watchdog_timer_enabled = B_TRUE; 4522 Adapter->watchdog_timer_started = B_TRUE; 4523 arm_watchdog_timer(Adapter); 4524 } 4525 4526 mutex_exit(&Adapter->watchdog_lock); 4527 } 4528 4529 static void 4530 disable_watchdog_timer(struct e1000g *Adapter) 4531 { 4532 timeout_id_t tid; 4533 4534 mutex_enter(&Adapter->watchdog_lock); 4535 4536 Adapter->watchdog_timer_enabled = B_FALSE; 4537 Adapter->watchdog_timer_started = B_FALSE; 4538 tid = Adapter->watchdog_tid; 4539 Adapter->watchdog_tid = 0; 4540 4541 mutex_exit(&Adapter->watchdog_lock); 4542 4543 if (tid != 0) 4544 (void) untimeout(tid); 4545 } 4546 4547 static void 4548 start_watchdog_timer(struct e1000g *Adapter) 4549 { 4550 mutex_enter(&Adapter->watchdog_lock); 4551 4552 if (Adapter->watchdog_timer_enabled) { 4553 if (!Adapter->watchdog_timer_started) { 4554 Adapter->watchdog_timer_started = B_TRUE; 4555 arm_watchdog_timer(Adapter); 4556 } 4557 } 4558 4559 mutex_exit(&Adapter->watchdog_lock); 4560 } 4561 4562 static void 4563 restart_watchdog_timer(struct e1000g *Adapter) 4564 { 4565 mutex_enter(&Adapter->watchdog_lock); 4566 4567 if (Adapter->watchdog_timer_started) 4568 arm_watchdog_timer(Adapter); 4569 4570 mutex_exit(&Adapter->watchdog_lock); 4571 } 4572 4573 static void 4574 stop_watchdog_timer(struct e1000g *Adapter) 4575 { 4576 timeout_id_t tid; 4577 4578 mutex_enter(&Adapter->watchdog_lock); 4579 4580 Adapter->watchdog_timer_started = B_FALSE; 4581 tid = Adapter->watchdog_tid; 4582 Adapter->watchdog_tid = 0; 4583 4584 mutex_exit(&Adapter->watchdog_lock); 4585 4586 if (tid != 0) 4587 (void) untimeout(tid); 4588 } 4589 4590 static void 4591 stop_link_timer(struct e1000g *Adapter) 4592 { 4593 timeout_id_t tid; 4594 4595 /* Disable the link timer */ 4596 mutex_enter(&Adapter->link_lock); 4597 4598 tid = Adapter->link_tid; 4599 Adapter->link_tid = 0; 4600 4601 mutex_exit(&Adapter->link_lock); 4602 4603 if (tid != 0) 4604 (void) untimeout(tid); 4605 } 4606 4607 static void 4608 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4609 { 4610 timeout_id_t tid; 4611 4612 /* Disable the tx timer for 82547 chipset */ 4613 mutex_enter(&tx_ring->tx_lock); 4614 4615 tx_ring->timer_enable_82547 = B_FALSE; 4616 tid = tx_ring->timer_id_82547; 4617 tx_ring->timer_id_82547 = 0; 4618 4619 mutex_exit(&tx_ring->tx_lock); 4620 4621 if (tid != 0) 4622 (void) untimeout(tid); 4623 } 4624 4625 void 4626 e1000g_clear_interrupt(struct e1000g *Adapter) 4627 { 4628 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4629 0xffffffff & ~E1000_IMS_RXSEQ); 4630 } 4631 4632 void 4633 e1000g_mask_interrupt(struct e1000g *Adapter) 4634 { 4635 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4636 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4637 4638 if (Adapter->tx_intr_enable) 4639 e1000g_mask_tx_interrupt(Adapter); 4640 } 4641 4642 /* 4643 * This routine is called by e1000g_quiesce(), therefore must not block. 4644 */ 4645 void 4646 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4647 { 4648 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4649 } 4650 4651 void 4652 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4653 { 4654 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4655 } 4656 4657 void 4658 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4659 { 4660 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4661 } 4662 4663 static void 4664 e1000g_smartspeed(struct e1000g *Adapter) 4665 { 4666 struct e1000_hw *hw = &Adapter->shared; 4667 uint16_t phy_status; 4668 uint16_t phy_ctrl; 4669 4670 /* 4671 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4672 * advertising 1000Full, we don't even use the workaround 4673 */ 4674 if ((hw->phy.type != e1000_phy_igp) || 4675 !hw->mac.autoneg || 4676 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4677 return; 4678 4679 /* 4680 * True if this is the first call of this function or after every 4681 * 30 seconds of not having link 4682 */ 4683 if (Adapter->smartspeed == 0) { 4684 /* 4685 * If Master/Slave config fault is asserted twice, we 4686 * assume back-to-back 4687 */ 4688 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4689 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4690 return; 4691 4692 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4693 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4694 return; 4695 /* 4696 * We're assuming back-2-back because our status register 4697 * insists! there's a fault in the master/slave 4698 * relationship that was "negotiated" 4699 */ 4700 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4701 /* 4702 * Is the phy configured for manual configuration of 4703 * master/slave? 4704 */ 4705 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4706 /* 4707 * Yes. Then disable manual configuration (enable 4708 * auto configuration) of master/slave 4709 */ 4710 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4711 (void) e1000_write_phy_reg(hw, 4712 PHY_1000T_CTRL, phy_ctrl); 4713 /* 4714 * Effectively starting the clock 4715 */ 4716 Adapter->smartspeed++; 4717 /* 4718 * Restart autonegotiation 4719 */ 4720 if (!e1000_phy_setup_autoneg(hw) && 4721 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4722 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4723 MII_CR_RESTART_AUTO_NEG); 4724 (void) e1000_write_phy_reg(hw, 4725 PHY_CONTROL, phy_ctrl); 4726 } 4727 } 4728 return; 4729 /* 4730 * Has 6 seconds transpired still without link? Remember, 4731 * you should reset the smartspeed counter once you obtain 4732 * link 4733 */ 4734 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4735 /* 4736 * Yes. Remember, we did at the start determine that 4737 * there's a master/slave configuration fault, so we're 4738 * still assuming there's someone on the other end, but we 4739 * just haven't yet been able to talk to it. We then 4740 * re-enable auto configuration of master/slave to see if 4741 * we're running 2/3 pair cables. 4742 */ 4743 /* 4744 * If still no link, perhaps using 2/3 pair cable 4745 */ 4746 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4747 phy_ctrl |= CR_1000T_MS_ENABLE; 4748 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4749 /* 4750 * Restart autoneg with phy enabled for manual 4751 * configuration of master/slave 4752 */ 4753 if (!e1000_phy_setup_autoneg(hw) && 4754 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4755 phy_ctrl |= 4756 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4757 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4758 } 4759 /* 4760 * Hopefully, there are no more faults and we've obtained 4761 * link as a result. 4762 */ 4763 } 4764 /* 4765 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4766 * seconds) 4767 */ 4768 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4769 Adapter->smartspeed = 0; 4770 } 4771 4772 static boolean_t 4773 is_valid_mac_addr(uint8_t *mac_addr) 4774 { 4775 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4776 const uint8_t addr_test2[6] = 4777 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4778 4779 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4780 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4781 return (B_FALSE); 4782 4783 return (B_TRUE); 4784 } 4785 4786 /* 4787 * e1000g_stall_check - check for tx stall 4788 * 4789 * This function checks if the adapter is stalled (in transmit). 4790 * 4791 * It is called each time the watchdog timeout is invoked. 4792 * If the transmit descriptor reclaim continuously fails, 4793 * the watchdog value will increment by 1. If the watchdog 4794 * value exceeds the threshold, the adapter is assumed to 4795 * have stalled and need to be reset. 4796 */ 4797 static boolean_t 4798 e1000g_stall_check(struct e1000g *Adapter) 4799 { 4800 e1000g_tx_ring_t *tx_ring; 4801 4802 tx_ring = Adapter->tx_ring; 4803 4804 if (Adapter->link_state != LINK_STATE_UP) 4805 return (B_FALSE); 4806 4807 (void) e1000g_recycle(tx_ring); 4808 4809 if (Adapter->stall_flag) 4810 return (B_TRUE); 4811 4812 return (B_FALSE); 4813 } 4814 4815 #ifdef E1000G_DEBUG 4816 static enum ioc_reply 4817 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4818 { 4819 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4820 e1000g_peekpoke_t *ppd; 4821 uint64_t mem_va; 4822 uint64_t maxoff; 4823 boolean_t peek; 4824 4825 switch (iocp->ioc_cmd) { 4826 4827 case E1000G_IOC_REG_PEEK: 4828 peek = B_TRUE; 4829 break; 4830 4831 case E1000G_IOC_REG_POKE: 4832 peek = B_FALSE; 4833 break; 4834 4835 deault: 4836 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4837 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4838 iocp->ioc_cmd); 4839 return (IOC_INVAL); 4840 } 4841 4842 /* 4843 * Validate format of ioctl 4844 */ 4845 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4846 return (IOC_INVAL); 4847 if (mp->b_cont == NULL) 4848 return (IOC_INVAL); 4849 4850 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4851 4852 /* 4853 * Validate request parameters 4854 */ 4855 switch (ppd->pp_acc_space) { 4856 4857 default: 4858 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4859 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4860 ppd->pp_acc_space); 4861 return (IOC_INVAL); 4862 4863 case E1000G_PP_SPACE_REG: 4864 /* 4865 * Memory-mapped I/O space 4866 */ 4867 ASSERT(ppd->pp_acc_size == 4); 4868 if (ppd->pp_acc_size != 4) 4869 return (IOC_INVAL); 4870 4871 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4872 return (IOC_INVAL); 4873 4874 mem_va = 0; 4875 maxoff = 0x10000; 4876 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4877 break; 4878 4879 case E1000G_PP_SPACE_E1000G: 4880 /* 4881 * E1000g data structure! 4882 */ 4883 mem_va = (uintptr_t)e1000gp; 4884 maxoff = sizeof (struct e1000g); 4885 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4886 break; 4887 4888 } 4889 4890 if (ppd->pp_acc_offset >= maxoff) 4891 return (IOC_INVAL); 4892 4893 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4894 return (IOC_INVAL); 4895 4896 /* 4897 * All OK - go! 4898 */ 4899 ppd->pp_acc_offset += mem_va; 4900 (*ppfn)(e1000gp, ppd); 4901 return (peek ? IOC_REPLY : IOC_ACK); 4902 } 4903 4904 static void 4905 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4906 { 4907 ddi_acc_handle_t handle; 4908 uint32_t *regaddr; 4909 4910 handle = e1000gp->osdep.reg_handle; 4911 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4912 (uintptr_t)ppd->pp_acc_offset); 4913 4914 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4915 } 4916 4917 static void 4918 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4919 { 4920 ddi_acc_handle_t handle; 4921 uint32_t *regaddr; 4922 uint32_t value; 4923 4924 handle = e1000gp->osdep.reg_handle; 4925 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4926 (uintptr_t)ppd->pp_acc_offset); 4927 value = (uint32_t)ppd->pp_acc_data; 4928 4929 ddi_put32(handle, regaddr, value); 4930 } 4931 4932 static void 4933 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4934 { 4935 uint64_t value; 4936 void *vaddr; 4937 4938 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4939 4940 switch (ppd->pp_acc_size) { 4941 case 1: 4942 value = *(uint8_t *)vaddr; 4943 break; 4944 4945 case 2: 4946 value = *(uint16_t *)vaddr; 4947 break; 4948 4949 case 4: 4950 value = *(uint32_t *)vaddr; 4951 break; 4952 4953 case 8: 4954 value = *(uint64_t *)vaddr; 4955 break; 4956 } 4957 4958 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4959 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4960 (void *)e1000gp, (void *)ppd, value, vaddr); 4961 4962 ppd->pp_acc_data = value; 4963 } 4964 4965 static void 4966 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4967 { 4968 uint64_t value; 4969 void *vaddr; 4970 4971 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4972 value = ppd->pp_acc_data; 4973 4974 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4975 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4976 (void *)e1000gp, (void *)ppd, value, vaddr); 4977 4978 switch (ppd->pp_acc_size) { 4979 case 1: 4980 *(uint8_t *)vaddr = (uint8_t)value; 4981 break; 4982 4983 case 2: 4984 *(uint16_t *)vaddr = (uint16_t)value; 4985 break; 4986 4987 case 4: 4988 *(uint32_t *)vaddr = (uint32_t)value; 4989 break; 4990 4991 case 8: 4992 *(uint64_t *)vaddr = (uint64_t)value; 4993 break; 4994 } 4995 } 4996 #endif 4997 4998 /* 4999 * Loopback Support 5000 */ 5001 static lb_property_t lb_normal = 5002 { normal, "normal", E1000G_LB_NONE }; 5003 static lb_property_t lb_external1000 = 5004 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 5005 static lb_property_t lb_external100 = 5006 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 5007 static lb_property_t lb_external10 = 5008 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 5009 static lb_property_t lb_phy = 5010 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 5011 5012 static enum ioc_reply 5013 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 5014 { 5015 lb_info_sz_t *lbsp; 5016 lb_property_t *lbpp; 5017 struct e1000_hw *hw; 5018 uint32_t *lbmp; 5019 uint32_t size; 5020 uint32_t value; 5021 5022 hw = &Adapter->shared; 5023 5024 if (mp->b_cont == NULL) 5025 return (IOC_INVAL); 5026 5027 if (!e1000g_check_loopback_support(hw)) { 5028 e1000g_log(NULL, CE_WARN, 5029 "Loopback is not supported on e1000g%d", Adapter->instance); 5030 return (IOC_INVAL); 5031 } 5032 5033 switch (iocp->ioc_cmd) { 5034 default: 5035 return (IOC_INVAL); 5036 5037 case LB_GET_INFO_SIZE: 5038 size = sizeof (lb_info_sz_t); 5039 if (iocp->ioc_count != size) 5040 return (IOC_INVAL); 5041 5042 rw_enter(&Adapter->chip_lock, RW_WRITER); 5043 e1000g_get_phy_state(Adapter); 5044 5045 /* 5046 * Workaround for hardware faults. In order to get a stable 5047 * state of phy, we will wait for a specific interval and 5048 * try again. The time delay is an experiential value based 5049 * on our testing. 5050 */ 5051 msec_delay(100); 5052 e1000g_get_phy_state(Adapter); 5053 rw_exit(&Adapter->chip_lock); 5054 5055 value = sizeof (lb_normal); 5056 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5057 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5058 (hw->phy.media_type == e1000_media_type_fiber) || 5059 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5060 value += sizeof (lb_phy); 5061 switch (hw->mac.type) { 5062 case e1000_82571: 5063 case e1000_82572: 5064 case e1000_80003es2lan: 5065 value += sizeof (lb_external1000); 5066 break; 5067 } 5068 } 5069 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5070 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5071 value += sizeof (lb_external100); 5072 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5073 value += sizeof (lb_external10); 5074 5075 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 5076 *lbsp = value; 5077 break; 5078 5079 case LB_GET_INFO: 5080 value = sizeof (lb_normal); 5081 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5082 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5083 (hw->phy.media_type == e1000_media_type_fiber) || 5084 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5085 value += sizeof (lb_phy); 5086 switch (hw->mac.type) { 5087 case e1000_82571: 5088 case e1000_82572: 5089 case e1000_80003es2lan: 5090 value += sizeof (lb_external1000); 5091 break; 5092 } 5093 } 5094 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5095 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5096 value += sizeof (lb_external100); 5097 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5098 value += sizeof (lb_external10); 5099 5100 size = value; 5101 if (iocp->ioc_count != size) 5102 return (IOC_INVAL); 5103 5104 value = 0; 5105 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 5106 lbpp[value++] = lb_normal; 5107 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5108 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5109 (hw->phy.media_type == e1000_media_type_fiber) || 5110 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5111 lbpp[value++] = lb_phy; 5112 switch (hw->mac.type) { 5113 case e1000_82571: 5114 case e1000_82572: 5115 case e1000_80003es2lan: 5116 lbpp[value++] = lb_external1000; 5117 break; 5118 } 5119 } 5120 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5121 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5122 lbpp[value++] = lb_external100; 5123 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5124 lbpp[value++] = lb_external10; 5125 break; 5126 5127 case LB_GET_MODE: 5128 size = sizeof (uint32_t); 5129 if (iocp->ioc_count != size) 5130 return (IOC_INVAL); 5131 5132 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 5133 *lbmp = Adapter->loopback_mode; 5134 break; 5135 5136 case LB_SET_MODE: 5137 size = 0; 5138 if (iocp->ioc_count != sizeof (uint32_t)) 5139 return (IOC_INVAL); 5140 5141 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 5142 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 5143 return (IOC_INVAL); 5144 break; 5145 } 5146 5147 iocp->ioc_count = size; 5148 iocp->ioc_error = 0; 5149 5150 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 5151 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 5152 return (IOC_INVAL); 5153 } 5154 5155 return (IOC_REPLY); 5156 } 5157 5158 static boolean_t 5159 e1000g_check_loopback_support(struct e1000_hw *hw) 5160 { 5161 switch (hw->mac.type) { 5162 case e1000_82540: 5163 case e1000_82545: 5164 case e1000_82545_rev_3: 5165 case e1000_82546: 5166 case e1000_82546_rev_3: 5167 case e1000_82541: 5168 case e1000_82541_rev_2: 5169 case e1000_82547: 5170 case e1000_82547_rev_2: 5171 case e1000_82571: 5172 case e1000_82572: 5173 case e1000_82573: 5174 case e1000_82574: 5175 case e1000_80003es2lan: 5176 case e1000_ich9lan: 5177 case e1000_ich10lan: 5178 return (B_TRUE); 5179 } 5180 return (B_FALSE); 5181 } 5182 5183 static boolean_t 5184 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 5185 { 5186 struct e1000_hw *hw; 5187 int i, times; 5188 boolean_t link_up; 5189 5190 if (mode == Adapter->loopback_mode) 5191 return (B_TRUE); 5192 5193 hw = &Adapter->shared; 5194 times = 0; 5195 5196 Adapter->loopback_mode = mode; 5197 5198 if (mode == E1000G_LB_NONE) { 5199 /* Reset the chip */ 5200 hw->phy.autoneg_wait_to_complete = B_TRUE; 5201 (void) e1000g_reset_adapter(Adapter); 5202 hw->phy.autoneg_wait_to_complete = B_FALSE; 5203 return (B_TRUE); 5204 } 5205 5206 again: 5207 5208 rw_enter(&Adapter->chip_lock, RW_WRITER); 5209 5210 switch (mode) { 5211 default: 5212 rw_exit(&Adapter->chip_lock); 5213 return (B_FALSE); 5214 5215 case E1000G_LB_EXTERNAL_1000: 5216 e1000g_set_external_loopback_1000(Adapter); 5217 break; 5218 5219 case E1000G_LB_EXTERNAL_100: 5220 e1000g_set_external_loopback_100(Adapter); 5221 break; 5222 5223 case E1000G_LB_EXTERNAL_10: 5224 e1000g_set_external_loopback_10(Adapter); 5225 break; 5226 5227 case E1000G_LB_INTERNAL_PHY: 5228 e1000g_set_internal_loopback(Adapter); 5229 break; 5230 } 5231 5232 times++; 5233 5234 rw_exit(&Adapter->chip_lock); 5235 5236 /* Wait for link up */ 5237 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 5238 msec_delay(100); 5239 5240 rw_enter(&Adapter->chip_lock, RW_WRITER); 5241 5242 link_up = e1000g_link_up(Adapter); 5243 5244 rw_exit(&Adapter->chip_lock); 5245 5246 if (!link_up) { 5247 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5248 "Failed to get the link up"); 5249 if (times < 2) { 5250 /* Reset the link */ 5251 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5252 "Reset the link ..."); 5253 (void) e1000g_reset_adapter(Adapter); 5254 goto again; 5255 } 5256 5257 /* 5258 * Reset driver to loopback none when set loopback failed 5259 * for the second time. 5260 */ 5261 Adapter->loopback_mode = E1000G_LB_NONE; 5262 5263 /* Reset the chip */ 5264 hw->phy.autoneg_wait_to_complete = B_TRUE; 5265 (void) e1000g_reset_adapter(Adapter); 5266 hw->phy.autoneg_wait_to_complete = B_FALSE; 5267 5268 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5269 "Set loopback mode failed, reset to loopback none"); 5270 5271 return (B_FALSE); 5272 } 5273 5274 return (B_TRUE); 5275 } 5276 5277 /* 5278 * The following loopback settings are from Intel's technical 5279 * document - "How To Loopback". All the register settings and 5280 * time delay values are directly inherited from the document 5281 * without more explanations available. 5282 */ 5283 static void 5284 e1000g_set_internal_loopback(struct e1000g *Adapter) 5285 { 5286 struct e1000_hw *hw; 5287 uint32_t ctrl; 5288 uint32_t status; 5289 uint16_t phy_ctrl; 5290 uint16_t phy_reg; 5291 uint32_t txcw; 5292 5293 hw = &Adapter->shared; 5294 5295 /* Disable Smart Power Down */ 5296 phy_spd_state(hw, B_FALSE); 5297 5298 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 5299 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 5300 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 5301 5302 switch (hw->mac.type) { 5303 case e1000_82540: 5304 case e1000_82545: 5305 case e1000_82545_rev_3: 5306 case e1000_82546: 5307 case e1000_82546_rev_3: 5308 case e1000_82573: 5309 /* Auto-MDI/MDIX off */ 5310 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 5311 /* Reset PHY to update Auto-MDI/MDIX */ 5312 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5313 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 5314 /* Reset PHY to auto-neg off and force 1000 */ 5315 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5316 phy_ctrl | MII_CR_RESET); 5317 /* 5318 * Disable PHY receiver for 82540/545/546 and 82573 Family. 5319 * See comments above e1000g_set_internal_loopback() for the 5320 * background. 5321 */ 5322 (void) e1000_write_phy_reg(hw, 29, 0x001F); 5323 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 5324 (void) e1000_write_phy_reg(hw, 29, 0x001A); 5325 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 5326 break; 5327 case e1000_80003es2lan: 5328 /* Force Link Up */ 5329 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 5330 0x1CC); 5331 /* Sets PCS loopback at 1Gbs */ 5332 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 5333 0x1046); 5334 break; 5335 } 5336 5337 /* 5338 * The following registers should be set for e1000_phy_bm phy type. 5339 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy. 5340 * For others, we do not need to set these registers. 5341 */ 5342 if (hw->phy.type == e1000_phy_bm) { 5343 /* Set Default MAC Interface speed to 1GB */ 5344 (void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg); 5345 phy_reg &= ~0x0007; 5346 phy_reg |= 0x006; 5347 (void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg); 5348 /* Assert SW reset for above settings to take effect */ 5349 (void) e1000_phy_commit(hw); 5350 msec_delay(1); 5351 /* Force Full Duplex */ 5352 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5353 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5354 phy_reg | 0x000C); 5355 /* Set Link Up (in force link) */ 5356 (void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg); 5357 (void) e1000_write_phy_reg(hw, PHY_REG(776, 16), 5358 phy_reg | 0x0040); 5359 /* Force Link */ 5360 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5361 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5362 phy_reg | 0x0040); 5363 /* Set Early Link Enable */ 5364 (void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg); 5365 (void) e1000_write_phy_reg(hw, PHY_REG(769, 20), 5366 phy_reg | 0x0400); 5367 } 5368 5369 /* Set loopback */ 5370 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 5371 5372 msec_delay(250); 5373 5374 /* Now set up the MAC to the same speed/duplex as the PHY. */ 5375 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5376 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5377 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5378 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5379 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 5380 E1000_CTRL_FD); /* Force Duplex to FULL */ 5381 5382 switch (hw->mac.type) { 5383 case e1000_82540: 5384 case e1000_82545: 5385 case e1000_82545_rev_3: 5386 case e1000_82546: 5387 case e1000_82546_rev_3: 5388 /* 5389 * For some serdes we'll need to commit the writes now 5390 * so that the status is updated on link 5391 */ 5392 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 5393 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5394 msec_delay(100); 5395 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5396 } 5397 5398 if (hw->phy.media_type == e1000_media_type_copper) { 5399 /* Invert Loss of Signal */ 5400 ctrl |= E1000_CTRL_ILOS; 5401 } else { 5402 /* Set ILOS on fiber nic if half duplex is detected */ 5403 status = E1000_READ_REG(hw, E1000_STATUS); 5404 if ((status & E1000_STATUS_FD) == 0) 5405 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5406 } 5407 break; 5408 5409 case e1000_82571: 5410 case e1000_82572: 5411 /* 5412 * The fiber/SerDes versions of this adapter do not contain an 5413 * accessible PHY. Therefore, loopback beyond MAC must be done 5414 * using SerDes analog loopback. 5415 */ 5416 if (hw->phy.media_type != e1000_media_type_copper) { 5417 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5418 txcw = E1000_READ_REG(hw, E1000_TXCW); 5419 txcw &= ~((uint32_t)1 << 31); 5420 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5421 5422 /* 5423 * Write 0x410 to Serdes Control register 5424 * to enable Serdes analog loopback 5425 */ 5426 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5427 msec_delay(10); 5428 } 5429 5430 status = E1000_READ_REG(hw, E1000_STATUS); 5431 /* Set ILOS on fiber nic if half duplex is detected */ 5432 if ((hw->phy.media_type == e1000_media_type_fiber) && 5433 ((status & E1000_STATUS_FD) == 0 || 5434 (status & E1000_STATUS_LU) == 0)) 5435 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5436 else if (hw->phy.media_type == e1000_media_type_internal_serdes) 5437 ctrl |= E1000_CTRL_SLU; 5438 break; 5439 5440 case e1000_82573: 5441 ctrl |= E1000_CTRL_ILOS; 5442 break; 5443 case e1000_ich9lan: 5444 case e1000_ich10lan: 5445 ctrl |= E1000_CTRL_SLU; 5446 break; 5447 } 5448 if (hw->phy.type == e1000_phy_bm) 5449 ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS; 5450 5451 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5452 } 5453 5454 static void 5455 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 5456 { 5457 struct e1000_hw *hw; 5458 uint32_t rctl; 5459 uint32_t ctrl_ext; 5460 uint32_t ctrl; 5461 uint32_t status; 5462 uint32_t txcw; 5463 uint16_t phydata; 5464 5465 hw = &Adapter->shared; 5466 5467 /* Disable Smart Power Down */ 5468 phy_spd_state(hw, B_FALSE); 5469 5470 switch (hw->mac.type) { 5471 case e1000_82571: 5472 case e1000_82572: 5473 switch (hw->phy.media_type) { 5474 case e1000_media_type_copper: 5475 /* Force link up (Must be done before the PHY writes) */ 5476 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5477 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 5478 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5479 5480 rctl = E1000_READ_REG(hw, E1000_RCTL); 5481 rctl |= (E1000_RCTL_EN | 5482 E1000_RCTL_SBP | 5483 E1000_RCTL_UPE | 5484 E1000_RCTL_MPE | 5485 E1000_RCTL_LPE | 5486 E1000_RCTL_BAM); /* 0x803E */ 5487 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 5488 5489 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5490 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 5491 E1000_CTRL_EXT_SDP6_DATA | 5492 E1000_CTRL_EXT_SDP3_DATA | 5493 E1000_CTRL_EXT_SDP4_DIR | 5494 E1000_CTRL_EXT_SDP6_DIR | 5495 E1000_CTRL_EXT_SDP3_DIR); /* 0x0DD0 */ 5496 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5497 5498 /* 5499 * This sequence tunes the PHY's SDP and no customer 5500 * settable values. For background, see comments above 5501 * e1000g_set_internal_loopback(). 5502 */ 5503 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 5504 msec_delay(10); 5505 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 5506 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 5507 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 5508 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 5509 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 5510 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 5511 5512 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 5513 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 5514 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 5515 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 5516 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 5517 5518 msec_delay(50); 5519 break; 5520 case e1000_media_type_fiber: 5521 case e1000_media_type_internal_serdes: 5522 status = E1000_READ_REG(hw, E1000_STATUS); 5523 if (((status & E1000_STATUS_LU) == 0) || 5524 (hw->phy.media_type == 5525 e1000_media_type_internal_serdes)) { 5526 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5527 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5528 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5529 } 5530 5531 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5532 txcw = E1000_READ_REG(hw, E1000_TXCW); 5533 txcw &= ~((uint32_t)1 << 31); 5534 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5535 5536 /* 5537 * Write 0x410 to Serdes Control register 5538 * to enable Serdes analog loopback 5539 */ 5540 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5541 msec_delay(10); 5542 break; 5543 default: 5544 break; 5545 } 5546 break; 5547 case e1000_82574: 5548 case e1000_80003es2lan: 5549 case e1000_ich9lan: 5550 case e1000_ich10lan: 5551 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 5552 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 5553 phydata | (1 << 5)); 5554 Adapter->param_adv_autoneg = 1; 5555 Adapter->param_adv_1000fdx = 1; 5556 (void) e1000g_reset_link(Adapter); 5557 break; 5558 } 5559 } 5560 5561 static void 5562 e1000g_set_external_loopback_100(struct e1000g *Adapter) 5563 { 5564 struct e1000_hw *hw; 5565 uint32_t ctrl; 5566 uint16_t phy_ctrl; 5567 5568 hw = &Adapter->shared; 5569 5570 /* Disable Smart Power Down */ 5571 phy_spd_state(hw, B_FALSE); 5572 5573 phy_ctrl = (MII_CR_FULL_DUPLEX | 5574 MII_CR_SPEED_100); 5575 5576 /* Force 100/FD, reset PHY */ 5577 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5578 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 5579 msec_delay(10); 5580 5581 /* Force 100/FD */ 5582 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5583 phy_ctrl); /* 0x2100 */ 5584 msec_delay(10); 5585 5586 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5587 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5588 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5589 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5590 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5591 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5592 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 5593 E1000_CTRL_FD); /* Force Duplex to FULL */ 5594 5595 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5596 } 5597 5598 static void 5599 e1000g_set_external_loopback_10(struct e1000g *Adapter) 5600 { 5601 struct e1000_hw *hw; 5602 uint32_t ctrl; 5603 uint16_t phy_ctrl; 5604 5605 hw = &Adapter->shared; 5606 5607 /* Disable Smart Power Down */ 5608 phy_spd_state(hw, B_FALSE); 5609 5610 phy_ctrl = (MII_CR_FULL_DUPLEX | 5611 MII_CR_SPEED_10); 5612 5613 /* Force 10/FD, reset PHY */ 5614 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5615 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 5616 msec_delay(10); 5617 5618 /* Force 10/FD */ 5619 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5620 phy_ctrl); /* 0x0100 */ 5621 msec_delay(10); 5622 5623 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5624 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5625 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5626 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5627 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5628 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5629 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 5630 E1000_CTRL_FD); /* Force Duplex to FULL */ 5631 5632 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5633 } 5634 5635 #ifdef __sparc 5636 static boolean_t 5637 e1000g_find_mac_address(struct e1000g *Adapter) 5638 { 5639 struct e1000_hw *hw = &Adapter->shared; 5640 uchar_t *bytes; 5641 struct ether_addr sysaddr; 5642 uint_t nelts; 5643 int err; 5644 boolean_t found = B_FALSE; 5645 5646 /* 5647 * The "vendor's factory-set address" may already have 5648 * been extracted from the chip, but if the property 5649 * "local-mac-address" is set we use that instead. 5650 * 5651 * We check whether it looks like an array of 6 5652 * bytes (which it should, if OBP set it). If we can't 5653 * make sense of it this way, we'll ignore it. 5654 */ 5655 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5656 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 5657 if (err == DDI_PROP_SUCCESS) { 5658 if (nelts == ETHERADDRL) { 5659 while (nelts--) 5660 hw->mac.addr[nelts] = bytes[nelts]; 5661 found = B_TRUE; 5662 } 5663 ddi_prop_free(bytes); 5664 } 5665 5666 /* 5667 * Look up the OBP property "local-mac-address?". If the user has set 5668 * 'local-mac-address? = false', use "the system address" instead. 5669 */ 5670 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5671 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5672 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5673 if (localetheraddr(NULL, &sysaddr) != 0) { 5674 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5675 found = B_TRUE; 5676 } 5677 } 5678 ddi_prop_free(bytes); 5679 } 5680 5681 /* 5682 * Finally(!), if there's a valid "mac-address" property (created 5683 * if we netbooted from this interface), we must use this instead 5684 * of any of the above to ensure that the NFS/install server doesn't 5685 * get confused by the address changing as Solaris takes over! 5686 */ 5687 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5688 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5689 if (err == DDI_PROP_SUCCESS) { 5690 if (nelts == ETHERADDRL) { 5691 while (nelts--) 5692 hw->mac.addr[nelts] = bytes[nelts]; 5693 found = B_TRUE; 5694 } 5695 ddi_prop_free(bytes); 5696 } 5697 5698 if (found) { 5699 bcopy(hw->mac.addr, hw->mac.perm_addr, 5700 ETHERADDRL); 5701 } 5702 5703 return (found); 5704 } 5705 #endif 5706 5707 static int 5708 e1000g_add_intrs(struct e1000g *Adapter) 5709 { 5710 dev_info_t *devinfo; 5711 int intr_types; 5712 int rc; 5713 5714 devinfo = Adapter->dip; 5715 5716 /* Get supported interrupt types */ 5717 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5718 5719 if (rc != DDI_SUCCESS) { 5720 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5721 "Get supported interrupt types failed: %d\n", rc); 5722 return (DDI_FAILURE); 5723 } 5724 5725 /* 5726 * Based on Intel Technical Advisory document (TA-160), there are some 5727 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5728 * that it supports MSI, but in fact has problems. 5729 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5730 * PCI/PCI-X NICs. 5731 */ 5732 if (Adapter->shared.mac.type < e1000_82571) 5733 Adapter->msi_enable = B_FALSE; 5734 5735 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5736 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5737 5738 if (rc != DDI_SUCCESS) { 5739 /* EMPTY */ 5740 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5741 "Add MSI failed, trying Legacy interrupts\n"); 5742 } else { 5743 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5744 } 5745 } 5746 5747 if ((Adapter->intr_type == 0) && 5748 (intr_types & DDI_INTR_TYPE_FIXED)) { 5749 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5750 5751 if (rc != DDI_SUCCESS) { 5752 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5753 "Add Legacy interrupts failed\n"); 5754 return (DDI_FAILURE); 5755 } 5756 5757 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5758 } 5759 5760 if (Adapter->intr_type == 0) { 5761 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5762 "No interrupts registered\n"); 5763 return (DDI_FAILURE); 5764 } 5765 5766 return (DDI_SUCCESS); 5767 } 5768 5769 /* 5770 * e1000g_intr_add() handles MSI/Legacy interrupts 5771 */ 5772 static int 5773 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5774 { 5775 dev_info_t *devinfo; 5776 int count, avail, actual; 5777 int x, y, rc, inum = 0; 5778 int flag; 5779 ddi_intr_handler_t *intr_handler; 5780 5781 devinfo = Adapter->dip; 5782 5783 /* get number of interrupts */ 5784 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5785 if ((rc != DDI_SUCCESS) || (count == 0)) { 5786 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5787 "Get interrupt number failed. Return: %d, count: %d\n", 5788 rc, count); 5789 return (DDI_FAILURE); 5790 } 5791 5792 /* get number of available interrupts */ 5793 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5794 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5795 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5796 "Get interrupt available number failed. " 5797 "Return: %d, available: %d\n", rc, avail); 5798 return (DDI_FAILURE); 5799 } 5800 5801 if (avail < count) { 5802 /* EMPTY */ 5803 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5804 "Interrupts count: %d, available: %d\n", 5805 count, avail); 5806 } 5807 5808 /* Allocate an array of interrupt handles */ 5809 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5810 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5811 5812 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5813 flag = DDI_INTR_ALLOC_NORMAL; 5814 5815 /* call ddi_intr_alloc() */ 5816 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5817 count, &actual, flag); 5818 5819 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5820 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5821 "Allocate interrupts failed: %d\n", rc); 5822 5823 kmem_free(Adapter->htable, Adapter->intr_size); 5824 return (DDI_FAILURE); 5825 } 5826 5827 if (actual < count) { 5828 /* EMPTY */ 5829 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5830 "Interrupts requested: %d, received: %d\n", 5831 count, actual); 5832 } 5833 5834 Adapter->intr_cnt = actual; 5835 5836 /* Get priority for first msi, assume remaining are all the same */ 5837 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5838 5839 if (rc != DDI_SUCCESS) { 5840 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5841 "Get interrupt priority failed: %d\n", rc); 5842 5843 /* Free already allocated intr */ 5844 for (y = 0; y < actual; y++) 5845 (void) ddi_intr_free(Adapter->htable[y]); 5846 5847 kmem_free(Adapter->htable, Adapter->intr_size); 5848 return (DDI_FAILURE); 5849 } 5850 5851 /* 5852 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5853 * use the interrupt service routine e1000g_intr_pciexpress() 5854 * to avoid interrupt stealing when sharing interrupt with other 5855 * devices. 5856 */ 5857 if (Adapter->shared.mac.type < e1000_82571) 5858 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5859 else 5860 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5861 5862 /* Call ddi_intr_add_handler() */ 5863 for (x = 0; x < actual; x++) { 5864 rc = ddi_intr_add_handler(Adapter->htable[x], 5865 intr_handler, (caddr_t)Adapter, NULL); 5866 5867 if (rc != DDI_SUCCESS) { 5868 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5869 "Add interrupt handler failed: %d\n", rc); 5870 5871 /* Remove already added handler */ 5872 for (y = 0; y < x; y++) 5873 (void) ddi_intr_remove_handler( 5874 Adapter->htable[y]); 5875 5876 /* Free already allocated intr */ 5877 for (y = 0; y < actual; y++) 5878 (void) ddi_intr_free(Adapter->htable[y]); 5879 5880 kmem_free(Adapter->htable, Adapter->intr_size); 5881 return (DDI_FAILURE); 5882 } 5883 } 5884 5885 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5886 5887 if (rc != DDI_SUCCESS) { 5888 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5889 "Get interrupt cap failed: %d\n", rc); 5890 5891 /* Free already allocated intr */ 5892 for (y = 0; y < actual; y++) { 5893 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5894 (void) ddi_intr_free(Adapter->htable[y]); 5895 } 5896 5897 kmem_free(Adapter->htable, Adapter->intr_size); 5898 return (DDI_FAILURE); 5899 } 5900 5901 return (DDI_SUCCESS); 5902 } 5903 5904 static int 5905 e1000g_rem_intrs(struct e1000g *Adapter) 5906 { 5907 int x; 5908 int rc; 5909 5910 for (x = 0; x < Adapter->intr_cnt; x++) { 5911 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5912 if (rc != DDI_SUCCESS) { 5913 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5914 "Remove intr handler failed: %d\n", rc); 5915 return (DDI_FAILURE); 5916 } 5917 5918 rc = ddi_intr_free(Adapter->htable[x]); 5919 if (rc != DDI_SUCCESS) { 5920 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5921 "Free intr failed: %d\n", rc); 5922 return (DDI_FAILURE); 5923 } 5924 } 5925 5926 kmem_free(Adapter->htable, Adapter->intr_size); 5927 5928 return (DDI_SUCCESS); 5929 } 5930 5931 static int 5932 e1000g_enable_intrs(struct e1000g *Adapter) 5933 { 5934 int x; 5935 int rc; 5936 5937 /* Enable interrupts */ 5938 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5939 /* Call ddi_intr_block_enable() for MSI */ 5940 rc = ddi_intr_block_enable(Adapter->htable, 5941 Adapter->intr_cnt); 5942 if (rc != DDI_SUCCESS) { 5943 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5944 "Enable block intr failed: %d\n", rc); 5945 return (DDI_FAILURE); 5946 } 5947 } else { 5948 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5949 for (x = 0; x < Adapter->intr_cnt; x++) { 5950 rc = ddi_intr_enable(Adapter->htable[x]); 5951 if (rc != DDI_SUCCESS) { 5952 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5953 "Enable intr failed: %d\n", rc); 5954 return (DDI_FAILURE); 5955 } 5956 } 5957 } 5958 5959 return (DDI_SUCCESS); 5960 } 5961 5962 static int 5963 e1000g_disable_intrs(struct e1000g *Adapter) 5964 { 5965 int x; 5966 int rc; 5967 5968 /* Disable all interrupts */ 5969 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5970 rc = ddi_intr_block_disable(Adapter->htable, 5971 Adapter->intr_cnt); 5972 if (rc != DDI_SUCCESS) { 5973 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5974 "Disable block intr failed: %d\n", rc); 5975 return (DDI_FAILURE); 5976 } 5977 } else { 5978 for (x = 0; x < Adapter->intr_cnt; x++) { 5979 rc = ddi_intr_disable(Adapter->htable[x]); 5980 if (rc != DDI_SUCCESS) { 5981 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5982 "Disable intr failed: %d\n", rc); 5983 return (DDI_FAILURE); 5984 } 5985 } 5986 } 5987 5988 return (DDI_SUCCESS); 5989 } 5990 5991 /* 5992 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5993 */ 5994 static void 5995 e1000g_get_phy_state(struct e1000g *Adapter) 5996 { 5997 struct e1000_hw *hw = &Adapter->shared; 5998 5999 if (hw->phy.media_type == e1000_media_type_copper) { 6000 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 6001 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 6002 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 6003 &Adapter->phy_an_adv); 6004 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, 6005 &Adapter->phy_an_exp); 6006 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, 6007 &Adapter->phy_ext_status); 6008 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, 6009 &Adapter->phy_1000t_ctrl); 6010 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 6011 &Adapter->phy_1000t_status); 6012 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, 6013 &Adapter->phy_lp_able); 6014 6015 Adapter->param_autoneg_cap = 6016 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 6017 Adapter->param_pause_cap = 6018 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 6019 Adapter->param_asym_pause_cap = 6020 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 6021 Adapter->param_1000fdx_cap = 6022 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 6023 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 6024 Adapter->param_1000hdx_cap = 6025 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 6026 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 6027 Adapter->param_100t4_cap = 6028 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 6029 Adapter->param_100fdx_cap = 6030 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 6031 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 6032 Adapter->param_100hdx_cap = 6033 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 6034 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 6035 Adapter->param_10fdx_cap = 6036 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 6037 Adapter->param_10hdx_cap = 6038 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 6039 6040 Adapter->param_adv_autoneg = hw->mac.autoneg; 6041 Adapter->param_adv_pause = 6042 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 6043 Adapter->param_adv_asym_pause = 6044 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 6045 Adapter->param_adv_1000hdx = 6046 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 6047 Adapter->param_adv_100t4 = 6048 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 6049 if (Adapter->param_adv_autoneg == 1) { 6050 Adapter->param_adv_1000fdx = 6051 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) 6052 ? 1 : 0; 6053 Adapter->param_adv_100fdx = 6054 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) 6055 ? 1 : 0; 6056 Adapter->param_adv_100hdx = 6057 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) 6058 ? 1 : 0; 6059 Adapter->param_adv_10fdx = 6060 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 6061 Adapter->param_adv_10hdx = 6062 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 6063 } 6064 6065 Adapter->param_lp_autoneg = 6066 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 6067 Adapter->param_lp_pause = 6068 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 6069 Adapter->param_lp_asym_pause = 6070 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 6071 Adapter->param_lp_1000fdx = 6072 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 6073 Adapter->param_lp_1000hdx = 6074 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 6075 Adapter->param_lp_100t4 = 6076 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 6077 Adapter->param_lp_100fdx = 6078 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 6079 Adapter->param_lp_100hdx = 6080 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 6081 Adapter->param_lp_10fdx = 6082 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 6083 Adapter->param_lp_10hdx = 6084 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 6085 } else { 6086 /* 6087 * 1Gig Fiber adapter only offers 1Gig Full Duplex. Meaning, 6088 * it can only work with 1Gig Full Duplex Link Partner. 6089 */ 6090 Adapter->param_autoneg_cap = 0; 6091 Adapter->param_pause_cap = 1; 6092 Adapter->param_asym_pause_cap = 1; 6093 Adapter->param_1000fdx_cap = 1; 6094 Adapter->param_1000hdx_cap = 0; 6095 Adapter->param_100t4_cap = 0; 6096 Adapter->param_100fdx_cap = 0; 6097 Adapter->param_100hdx_cap = 0; 6098 Adapter->param_10fdx_cap = 0; 6099 Adapter->param_10hdx_cap = 0; 6100 6101 Adapter->param_adv_autoneg = 0; 6102 Adapter->param_adv_pause = 1; 6103 Adapter->param_adv_asym_pause = 1; 6104 Adapter->param_adv_1000fdx = 1; 6105 Adapter->param_adv_1000hdx = 0; 6106 Adapter->param_adv_100t4 = 0; 6107 Adapter->param_adv_100fdx = 0; 6108 Adapter->param_adv_100hdx = 0; 6109 Adapter->param_adv_10fdx = 0; 6110 Adapter->param_adv_10hdx = 0; 6111 6112 Adapter->param_lp_autoneg = 0; 6113 Adapter->param_lp_pause = 0; 6114 Adapter->param_lp_asym_pause = 0; 6115 Adapter->param_lp_1000fdx = 0; 6116 Adapter->param_lp_1000hdx = 0; 6117 Adapter->param_lp_100t4 = 0; 6118 Adapter->param_lp_100fdx = 0; 6119 Adapter->param_lp_100hdx = 0; 6120 Adapter->param_lp_10fdx = 0; 6121 Adapter->param_lp_10hdx = 0; 6122 } 6123 } 6124 6125 /* 6126 * FMA support 6127 */ 6128 6129 int 6130 e1000g_check_acc_handle(ddi_acc_handle_t handle) 6131 { 6132 ddi_fm_error_t de; 6133 6134 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 6135 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 6136 return (de.fme_status); 6137 } 6138 6139 int 6140 e1000g_check_dma_handle(ddi_dma_handle_t handle) 6141 { 6142 ddi_fm_error_t de; 6143 6144 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 6145 return (de.fme_status); 6146 } 6147 6148 /* 6149 * The IO fault service error handling callback function 6150 */ 6151 /* ARGSUSED2 */ 6152 static int 6153 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 6154 { 6155 /* 6156 * as the driver can always deal with an error in any dma or 6157 * access handle, we can just return the fme_status value. 6158 */ 6159 pci_ereport_post(dip, err, NULL); 6160 return (err->fme_status); 6161 } 6162 6163 static void 6164 e1000g_fm_init(struct e1000g *Adapter) 6165 { 6166 ddi_iblock_cookie_t iblk; 6167 int fma_dma_flag; 6168 6169 /* Only register with IO Fault Services if we have some capability */ 6170 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 6171 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 6172 } else { 6173 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 6174 } 6175 6176 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 6177 fma_dma_flag = 1; 6178 } else { 6179 fma_dma_flag = 0; 6180 } 6181 6182 (void) e1000g_set_fma_flags(fma_dma_flag); 6183 6184 if (Adapter->fm_capabilities) { 6185 6186 /* Register capabilities with IO Fault Services */ 6187 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 6188 6189 /* 6190 * Initialize pci ereport capabilities if ereport capable 6191 */ 6192 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6193 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6194 pci_ereport_setup(Adapter->dip); 6195 6196 /* 6197 * Register error callback if error callback capable 6198 */ 6199 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6200 ddi_fm_handler_register(Adapter->dip, 6201 e1000g_fm_error_cb, (void*) Adapter); 6202 } 6203 } 6204 6205 static void 6206 e1000g_fm_fini(struct e1000g *Adapter) 6207 { 6208 /* Only unregister FMA capabilities if we registered some */ 6209 if (Adapter->fm_capabilities) { 6210 6211 /* 6212 * Release any resources allocated by pci_ereport_setup() 6213 */ 6214 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6215 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6216 pci_ereport_teardown(Adapter->dip); 6217 6218 /* 6219 * Un-register error callback if error callback capable 6220 */ 6221 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6222 ddi_fm_handler_unregister(Adapter->dip); 6223 6224 /* Unregister from IO Fault Services */ 6225 mutex_enter(&e1000g_rx_detach_lock); 6226 ddi_fm_fini(Adapter->dip); 6227 if (Adapter->priv_dip != NULL) { 6228 DEVI(Adapter->priv_dip)->devi_fmhdl = NULL; 6229 } 6230 mutex_exit(&e1000g_rx_detach_lock); 6231 } 6232 } 6233 6234 void 6235 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 6236 { 6237 uint64_t ena; 6238 char buf[FM_MAX_CLASS]; 6239 6240 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 6241 ena = fm_ena_generate(0, FM_ENA_FMT1); 6242 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 6243 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 6244 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 6245 } 6246 } 6247 6248 /* 6249 * quiesce(9E) entry point. 6250 * 6251 * This function is called when the system is single-threaded at high 6252 * PIL with preemption disabled. Therefore, this function must not be 6253 * blocked. 6254 * 6255 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 6256 * DDI_FAILURE indicates an error condition and should almost never happen. 6257 */ 6258 static int 6259 e1000g_quiesce(dev_info_t *devinfo) 6260 { 6261 struct e1000g *Adapter; 6262 6263 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 6264 6265 if (Adapter == NULL) 6266 return (DDI_FAILURE); 6267 6268 e1000g_clear_all_interrupts(Adapter); 6269 6270 (void) e1000_reset_hw(&Adapter->shared); 6271 6272 /* Setup our HW Tx Head & Tail descriptor pointers */ 6273 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 6274 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 6275 6276 /* Setup our HW Rx Head & Tail descriptor pointers */ 6277 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 6278 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 6279 6280 return (DDI_SUCCESS); 6281 } 6282 6283 static int 6284 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 6285 uint_t pr_valsize, void *pr_val) 6286 { 6287 link_flowctrl_t fl; 6288 struct e1000_hw *hw = &Adapter->shared; 6289 int err = 0; 6290 6291 ASSERT(pr_valsize > 0); 6292 switch (pr_num) { 6293 case MAC_PROP_AUTONEG: 6294 if (hw->phy.media_type != e1000_media_type_copper) 6295 *(uint8_t *)pr_val = 0; 6296 else 6297 *(uint8_t *)pr_val = 6298 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) 6299 ? 1 : 0); 6300 break; 6301 case MAC_PROP_FLOWCTRL: 6302 if (pr_valsize < sizeof (link_flowctrl_t)) 6303 return (EINVAL); 6304 fl = LINK_FLOWCTRL_BI; 6305 bcopy(&fl, pr_val, sizeof (fl)); 6306 break; 6307 case MAC_PROP_ADV_1000FDX_CAP: 6308 case MAC_PROP_EN_1000FDX_CAP: 6309 if (hw->phy.media_type != e1000_media_type_copper) 6310 *(uint8_t *)pr_val = 1; 6311 else 6312 *(uint8_t *)pr_val = 6313 ((Adapter->phy_ext_status & 6314 IEEE_ESR_1000T_FD_CAPS) || 6315 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) 6316 ? 1 : 0; 6317 break; 6318 case MAC_PROP_ADV_1000HDX_CAP: 6319 case MAC_PROP_EN_1000HDX_CAP: 6320 *(uint8_t *)pr_val = 0; 6321 break; 6322 case MAC_PROP_ADV_100FDX_CAP: 6323 case MAC_PROP_EN_100FDX_CAP: 6324 if (hw->phy.media_type != e1000_media_type_copper) 6325 *(uint8_t *)pr_val = 0; 6326 else 6327 *(uint8_t *)pr_val = 6328 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 6329 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 6330 ? 1 : 0; 6331 break; 6332 case MAC_PROP_ADV_100HDX_CAP: 6333 case MAC_PROP_EN_100HDX_CAP: 6334 if (hw->phy.media_type != e1000_media_type_copper) 6335 *(uint8_t *)pr_val = 0; 6336 else 6337 *(uint8_t *)pr_val = 6338 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 6339 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) 6340 ? 1 : 0; 6341 break; 6342 case MAC_PROP_ADV_10FDX_CAP: 6343 case MAC_PROP_EN_10FDX_CAP: 6344 if (hw->phy.media_type != e1000_media_type_copper) 6345 *(uint8_t *)pr_val = 0; 6346 else 6347 *(uint8_t *)pr_val = 6348 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 6349 break; 6350 case MAC_PROP_ADV_10HDX_CAP: 6351 case MAC_PROP_EN_10HDX_CAP: 6352 if (hw->phy.media_type != e1000_media_type_copper) 6353 *(uint8_t *)pr_val = 0; 6354 else 6355 *(uint8_t *)pr_val = 6356 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 6357 break; 6358 default: 6359 err = ENOTSUP; 6360 break; 6361 } 6362 return (err); 6363 } 6364 6365 /* 6366 * synchronize the adv* and en* parameters. 6367 * 6368 * See comments in <sys/dld.h> for details of the *_en_* 6369 * parameters. The usage of ndd for setting adv parameters will 6370 * synchronize all the en parameters with the e1000g parameters, 6371 * implicitly disabling any settings made via dladm. 6372 */ 6373 static void 6374 e1000g_param_sync(struct e1000g *Adapter) 6375 { 6376 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 6377 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 6378 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 6379 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 6380 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 6381 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 6382 } 6383 6384 /* 6385 * e1000g_get_driver_control - tell manageability firmware that the driver 6386 * has control. 6387 */ 6388 static void 6389 e1000g_get_driver_control(struct e1000_hw *hw) 6390 { 6391 uint32_t ctrl_ext; 6392 uint32_t swsm; 6393 6394 /* tell manageability firmware the driver has taken over */ 6395 switch (hw->mac.type) { 6396 case e1000_82573: 6397 swsm = E1000_READ_REG(hw, E1000_SWSM); 6398 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 6399 break; 6400 case e1000_82571: 6401 case e1000_82572: 6402 case e1000_82574: 6403 case e1000_80003es2lan: 6404 case e1000_ich8lan: 6405 case e1000_ich9lan: 6406 case e1000_ich10lan: 6407 case e1000_pchlan: 6408 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6409 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6410 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 6411 break; 6412 default: 6413 /* no manageability firmware: do nothing */ 6414 break; 6415 } 6416 } 6417 6418 /* 6419 * e1000g_release_driver_control - tell manageability firmware that the driver 6420 * has released control. 6421 */ 6422 static void 6423 e1000g_release_driver_control(struct e1000_hw *hw) 6424 { 6425 uint32_t ctrl_ext; 6426 uint32_t swsm; 6427 6428 /* tell manageability firmware the driver has released control */ 6429 switch (hw->mac.type) { 6430 case e1000_82573: 6431 swsm = E1000_READ_REG(hw, E1000_SWSM); 6432 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 6433 break; 6434 case e1000_82571: 6435 case e1000_82572: 6436 case e1000_82574: 6437 case e1000_80003es2lan: 6438 case e1000_ich8lan: 6439 case e1000_ich9lan: 6440 case e1000_ich10lan: 6441 case e1000_pchlan: 6442 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6443 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6444 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 6445 break; 6446 default: 6447 /* no manageability firmware: do nothing */ 6448 break; 6449 } 6450 } 6451 6452 /* 6453 * Restore e1000g promiscuous mode. 6454 */ 6455 static void 6456 e1000g_restore_promisc(struct e1000g *Adapter) 6457 { 6458 if (Adapter->e1000g_promisc) { 6459 uint32_t rctl; 6460 6461 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 6462 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 6463 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 6464 } 6465 } 6466