1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #ifndef _E1000_OSDEP_H 27 #define _E1000_OSDEP_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <sys/types.h> 34 #include <sys/conf.h> 35 #include <sys/debug.h> 36 #include <sys/stropts.h> 37 #include <sys/stream.h> 38 #include <sys/strlog.h> 39 #include <sys/kmem.h> 40 #include <sys/stat.h> 41 #include <sys/kstat.h> 42 #include <sys/modctl.h> 43 #include <sys/errno.h> 44 #include <sys/ddi.h> 45 #include <sys/sunddi.h> 46 #include <sys/pci.h> 47 #include <sys/atomic.h> 48 #include <sys/note.h> 49 #include "e1000g_debug.h" 50 51 #define usec_delay(x) drv_usecwait(x) 52 #define msec_delay(x) drv_usecwait(x * 1000) 53 #define msec_delay_irq msec_delay 54 55 #ifdef E1000G_DEBUG 56 #define DEBUGOUT(S) \ 57 E1000G_DEBUGLOG_0(NULL, E1000G_INFO_LEVEL, S) 58 #define DEBUGOUT1(S, A) \ 59 E1000G_DEBUGLOG_1(NULL, E1000G_INFO_LEVEL, S, A) 60 #define DEBUGOUT2(S, A, B) \ 61 E1000G_DEBUGLOG_2(NULL, E1000G_INFO_LEVEL, S, A, B) 62 #define DEBUGOUT3(S, A, B, C) \ 63 E1000G_DEBUGLOG_3(NULL, E1000G_INFO_LEVEL, S, A, B, C) 64 #define DEBUGFUNC(F) \ 65 E1000G_DEBUGLOG_0(NULL, E1000G_TRACE_LEVEL, F) 66 #else 67 #define DEBUGOUT(S) 68 #define DEBUGOUT1(S, A) 69 #define DEBUGOUT2(S, A, B) 70 #define DEBUGOUT3(S, A, B, C) 71 #define DEBUGFUNC(F) 72 #endif 73 74 #define OS_DEP(hw) ((struct e1000g_osdep *)((hw)->back)) 75 76 #define false 0 77 #define true 1 78 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ 79 #define PCI_COMMAND_REGISTER 0x04 80 #define PCI_EX_CONF_CAP 0xE0 81 #define ADAPTER_REG_SET 1 /* solaris mapping of adapter registers */ 82 #define ICH_FLASH_REG_SET 2 /* solaris mapping of flash memory */ 83 84 #define RECEIVE_BUFFER_ALIGN_SIZE 256 85 #define E1000_MDALIGN 4096 86 #define E1000_ERT_2048 0x100 87 88 /* PHY Extended Status Register */ 89 #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 90 #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 91 #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 92 #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 93 94 /* 95 * required by shared code 96 */ 97 #define E1000_WRITE_FLUSH(a) (void)E1000_READ_REG(a, E1000_STATUS) 98 99 #define E1000_WRITE_REG(hw, reg, value) \ 100 {\ 101 if ((hw)->mac.type != e1000_82542) \ 102 ddi_put32((OS_DEP(hw))->reg_handle, \ 103 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg), \ 104 value); \ 105 else \ 106 ddi_put32((OS_DEP(hw))->reg_handle, \ 107 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 108 e1000_translate_register_82542(reg)), \ 109 value); \ 110 } 111 112 #define E1000_READ_REG(hw, reg) (\ 113 ((hw)->mac.type != e1000_82542) ? \ 114 ddi_get32((OS_DEP(hw))->reg_handle, \ 115 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg)) : \ 116 ddi_get32((OS_DEP(hw))->reg_handle, \ 117 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 118 e1000_translate_register_82542(reg)))) 119 120 #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ 121 {\ 122 if ((hw)->mac.type != e1000_82542) \ 123 ddi_put32((OS_DEP(hw))->reg_handle, \ 124 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 125 reg + ((offset) << 2)),\ 126 value); \ 127 else \ 128 ddi_put32((OS_DEP(hw))->reg_handle, \ 129 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 130 e1000_translate_register_82542(reg) + \ 131 ((offset) << 2)), value); \ 132 } 133 134 #define E1000_READ_REG_ARRAY(hw, reg, offset) (\ 135 ((hw)->mac.type != e1000_82542) ? \ 136 ddi_get32((OS_DEP(hw))->reg_handle, \ 137 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg + \ 138 ((offset) << 2))) : \ 139 ddi_get32((OS_DEP(hw))->reg_handle, \ 140 (uint32_t *)((uintptr_t)(hw)->hw_addr + \ 141 e1000_translate_register_82542(reg) + \ 142 ((offset) << 2)))) 143 144 145 #define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value) \ 146 E1000_WRITE_REG_ARRAY(a, reg, offset, value) 147 #define E1000_READ_REG_ARRAY_DWORD(a, reg, offset) \ 148 E1000_READ_REG_ARRAY(a, reg, offset) 149 150 151 #define E1000_READ_FLASH_REG(hw, reg) \ 152 ddi_get32((OS_DEP(hw))->ich_flash_handle, \ 153 (uint32_t *)((uintptr_t)(hw)->flash_address + (reg))) 154 155 #define E1000_READ_FLASH_REG16(hw, reg) \ 156 ddi_get16((OS_DEP(hw))->ich_flash_handle, \ 157 (uint16_t *)((uintptr_t)(hw)->flash_address + (reg))) 158 159 #define E1000_WRITE_FLASH_REG(hw, reg, value) \ 160 ddi_put32((OS_DEP(hw))->ich_flash_handle, \ 161 (uint32_t *)((uintptr_t)(hw)->flash_address + (reg)), (value)) 162 163 #define E1000_WRITE_FLASH_REG16(hw, reg, value) \ 164 ddi_put16((OS_DEP(hw))->ich_flash_handle, \ 165 (uint16_t *)((uintptr_t)(hw)->flash_address + (reg)), (value)) 166 167 #define UNREFERENCED_1PARAMETER(_p) _NOTE(ARGUNUSED(_p)) 168 #define UNREFERENCED_2PARAMETER(_p, _q) _NOTE(ARGUNUSED(_p, _q)) 169 #define UNREFERENCED_3PARAMETER(_p, _q, _r) _NOTE(ARGUNUSED(_p, _q, _r)) 170 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) _NOTE(ARGUNUSED(_p, _q, _r, _s)) 171 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) \ 172 _NOTE(ARGUNUSED(_p, _q, _r, _s, _t)) 173 174 typedef int8_t s8; 175 typedef int16_t s16; 176 typedef int32_t s32; 177 typedef int64_t s64; 178 typedef uint8_t u8; 179 typedef uint16_t u16; 180 typedef uint32_t u32; 181 typedef uint64_t u64; 182 typedef boolean_t bool; 183 184 struct e1000g_osdep { 185 ddi_acc_handle_t reg_handle; 186 ddi_acc_handle_t cfg_handle; 187 ddi_acc_handle_t ich_flash_handle; 188 struct e1000g *adapter; 189 }; 190 191 #ifdef __sparc /* on SPARC, use only memory-mapped routines */ 192 #define E1000_WRITE_REG_IO E1000_WRITE_REG 193 #else /* on x86, use port io routines */ 194 #define E1000_WRITE_REG_IO(a, reg, val) { \ 195 outl(((a)->io_base), reg); \ 196 outl(((a)->io_base + 4), val); } 197 #endif /* __sparc */ 198 199 #ifdef __cplusplus 200 } 201 #endif 202 203 #endif /* _E1000_OSDEP_H */ 204