1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #ifndef _E1000_OSDEP_H 27 #define _E1000_OSDEP_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/types.h> 36 #include <sys/conf.h> 37 #include <sys/debug.h> 38 #include <sys/stropts.h> 39 #include <sys/stream.h> 40 #include <sys/strlog.h> 41 #include <sys/kmem.h> 42 #include <sys/stat.h> 43 #include <sys/kstat.h> 44 #include <sys/modctl.h> 45 #include <sys/errno.h> 46 #include <sys/ddi.h> 47 #include <sys/sunddi.h> 48 #include <sys/pci.h> 49 #include <sys/atomic.h> 50 #include "e1000g_debug.h" 51 52 /* 53 * === BEGIN CONTENT FORMERLY IN FXHW.H === 54 */ 55 #define usec_delay(x) drv_usecwait(x) 56 #define msec_delay(x) drv_usecwait(x * 1000) 57 58 #ifdef E1000G_DEBUG 59 #define DEBUGOUT(S) \ 60 E1000G_DEBUGLOG_0(NULL, E1000G_INFO_LEVEL, S) 61 #define DEBUGOUT1(S, A) \ 62 E1000G_DEBUGLOG_1(NULL, E1000G_INFO_LEVEL, S, A) 63 #define DEBUGOUT2(S, A, B) \ 64 E1000G_DEBUGLOG_2(NULL, E1000G_INFO_LEVEL, S, A, B) 65 #define DEBUGOUT3(S, A, B, C) \ 66 E1000G_DEBUGLOG_3(NULL, E1000G_INFO_LEVEL, S, A, B, C) 67 #define DEBUGFUNC(F) \ 68 E1000G_DEBUGLOG_0(NULL, E1000G_TRACE_LEVEL, F) 69 #else 70 #define DEBUGOUT(S) 71 #define DEBUGOUT1(S, A) 72 #define DEBUGOUT2(S, A, B) 73 #define DEBUGOUT3(S, A, B, C) 74 #define DEBUGFUNC(F) 75 #endif 76 77 #define OS_DEP(hw) ((struct e1000g_osdep *)((hw)->back)) 78 79 #define FALSE 0 80 #define TRUE 1 81 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ 82 #define PCI_COMMAND_REGISTER 0x04 83 #define PCI_EX_CONF_CAP 0xE0 84 #define ICH_FLASH_REG_SET 2 /* solaris mapping of flash memory */ 85 86 #define RECEIVE_BUFFER_ALIGN_SIZE 256 87 #define E1000_MDALIGN 4096 88 #define E1000_ERT_2048 0x100 89 90 /* PHY Extended Status Register */ 91 #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 92 #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 93 #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 94 #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 95 96 /* 97 * required by shared code 98 */ 99 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS) 100 101 #define E1000_WRITE_REG(hw, reg, value) \ 102 {\ 103 if ((hw)->mac.type != e1000_82542) \ 104 ddi_put32((OS_DEP(hw))->reg_handle, \ 105 (uint32_t *)((hw)->hw_addr + reg), \ 106 value); \ 107 else \ 108 ddi_put32((OS_DEP(hw))->reg_handle, \ 109 (uint32_t *)((hw)->hw_addr + \ 110 e1000_translate_register_82542(reg)), \ 111 value); \ 112 } 113 114 #define E1000_READ_REG(hw, reg) (\ 115 ((hw)->mac.type != e1000_82542) ? \ 116 ddi_get32((OS_DEP(hw))->reg_handle, \ 117 (uint32_t *)((hw)->hw_addr + reg)) : \ 118 ddi_get32((OS_DEP(hw))->reg_handle, \ 119 (uint32_t *)((hw)->hw_addr + \ 120 e1000_translate_register_82542(reg)))) 121 122 #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ 123 {\ 124 if ((hw)->mac.type != e1000_82542) \ 125 ddi_put32((OS_DEP(hw))->reg_handle, \ 126 (uint32_t *)((hw)->hw_addr + reg + ((offset) << 2)),\ 127 value); \ 128 else \ 129 ddi_put32((OS_DEP(hw))->reg_handle, \ 130 (uint32_t *)((hw)->hw_addr + \ 131 e1000_translate_register_82542(reg) + \ 132 ((offset) << 2)), value); \ 133 } 134 135 #define E1000_READ_REG_ARRAY(hw, reg, offset) (\ 136 ((hw)->mac.type != e1000_82542) ? \ 137 ddi_get32((OS_DEP(hw))->reg_handle, \ 138 (uint32_t *)((hw)->hw_addr + reg + ((offset) << 2))) : \ 139 ddi_get32((OS_DEP(hw))->reg_handle, \ 140 (uint32_t *)((hw)->hw_addr + \ 141 e1000_translate_register_82542(reg) + \ 142 ((offset) << 2)))) 143 144 145 #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) NULL 146 #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) NULL 147 #define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value) NULL 148 #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) NULL 149 #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) NULL 150 #define E1000_READ_REG_ARRAY_DWORD(a, reg, offset) NULL 151 152 153 #define E1000_READ_FLASH_REG(hw, reg) \ 154 ddi_get32((OS_DEP(hw))->ich_flash_handle, \ 155 (uint32_t *)((hw)->flash_address + (reg))) 156 157 #define E1000_READ_FLASH_REG16(hw, reg) \ 158 ddi_get16((OS_DEP(hw))->ich_flash_handle, \ 159 (uint16_t *)((hw)->flash_address + (reg))) 160 161 #define E1000_WRITE_FLASH_REG(hw, reg, value) \ 162 ddi_put32((OS_DEP(hw))->ich_flash_handle, \ 163 (uint32_t *)((hw)->flash_address + (reg)), (value)) 164 165 #define E1000_WRITE_FLASH_REG16(hw, reg, value) \ 166 ddi_put16((OS_DEP(hw))->ich_flash_handle, \ 167 (uint16_t *)((hw)->flash_address + (reg)), (value)) 168 169 /* 170 * === END CONTENT FORMERLY IN FXHW.H === 171 */ 172 173 #define msec_delay_irq msec_delay 174 175 typedef int8_t s8; 176 typedef int16_t s16; 177 typedef int32_t s32; 178 typedef int64_t s64; 179 typedef uint8_t u8; 180 typedef uint16_t u16; 181 typedef uint32_t u32; 182 typedef uint64_t u64; 183 184 typedef uint8_t UCHAR; /* 8-bit unsigned */ 185 typedef UCHAR UINT8; /* 8-bit unsigned */ 186 typedef uint16_t USHORT; /* 16-bit unsigned */ 187 typedef uint16_t UINT16; /* 16-bit unsigned */ 188 typedef uint32_t ULONG; /* 32-bit unsigned */ 189 typedef uint32_t UINT32; 190 typedef uint32_t UINT; /* 32-bit unsigned */ 191 typedef UCHAR BOOLEAN; 192 typedef BOOLEAN bool; 193 typedef UCHAR *PUCHAR; 194 typedef UINT *PUINT; 195 typedef ULONG *PLONG; 196 typedef ULONG NDIS_STATUS; 197 typedef USHORT *PUSHORT; 198 typedef PUSHORT PUINT16; /* 16-bit unsigned pointer */ 199 typedef ULONG E1000_32_BIT_PHYSICAL_ADDRESS, 200 *PFX_32_BIT_PHYSICAL_ADDRESS; 201 typedef uint64_t E1000_64_BIT_PHYSICAL_ADDRESS, 202 *PFX_64_BIT_PHYSICAL_ADDRESS; 203 204 struct e1000g_osdep { 205 ddi_acc_handle_t reg_handle; 206 ddi_acc_handle_t cfg_handle; 207 ddi_acc_handle_t ich_flash_handle; 208 struct e1000g *adapter; 209 }; 210 211 #ifdef __sparc /* on SPARC, use only memory-mapped routines */ 212 #define E1000_WRITE_REG_IO E1000_WRITE_REG 213 #else /* on x86, use port io routines */ 214 #define E1000_WRITE_REG_IO(a, reg, val) { \ 215 outl(((a)->io_base), reg); \ 216 outl(((a)->io_base + 4), val); } 217 #endif /* __sparc */ 218 219 #ifdef __cplusplus 220 } 221 #endif 222 223 #endif /* _E1000_OSDEP_H */ 224