1 /****************************************************************************** 2 3 Copyright (c) 2001-2014, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_PHY_H_ 36 #define _E1000_PHY_H_ 37 38 void e1000_init_phy_ops_generic(struct e1000_hw *hw); 39 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data); 40 void e1000_null_phy_generic(struct e1000_hw *hw); 41 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active); 42 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data); 43 s32 e1000_null_set_page(struct e1000_hw *hw, u16 data); 44 s32 e1000_read_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset, 45 u8 dev_addr, u8 *data); 46 s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset, 47 u8 dev_addr, u8 data); 48 s32 e1000_check_downshift_generic(struct e1000_hw *hw); 49 s32 e1000_check_polarity_m88(struct e1000_hw *hw); 50 s32 e1000_check_polarity_igp(struct e1000_hw *hw); 51 s32 e1000_check_polarity_ife(struct e1000_hw *hw); 52 s32 e1000_check_reset_block_generic(struct e1000_hw *hw); 53 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); 54 s32 e1000_copper_link_autoneg(struct e1000_hw *hw); 55 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw); 56 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw); 57 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw); 58 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw); 59 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw); 60 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); 61 s32 e1000_get_cable_length_m88(struct e1000_hw *hw); 62 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw); 63 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw); 64 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw); 65 s32 e1000_get_phy_id(struct e1000_hw *hw); 66 s32 e1000_get_phy_info_igp(struct e1000_hw *hw); 67 s32 e1000_get_phy_info_m88(struct e1000_hw *hw); 68 s32 e1000_get_phy_info_ife(struct e1000_hw *hw); 69 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw); 70 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); 71 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw); 72 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw); 73 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data); 74 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data); 75 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page); 76 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); 77 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data); 78 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); 79 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active); 80 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw); 81 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data); 82 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data); 83 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); 84 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data); 85 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); 86 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 87 u32 usec_interval, bool *success); 88 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw); 89 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id); 90 s32 e1000_determine_phy_address(struct e1000_hw *hw); 91 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); 92 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); 93 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); 94 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); 95 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); 96 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); 97 void e1000_power_up_phy_copper(struct e1000_hw *hw); 98 void e1000_power_down_phy_copper(struct e1000_hw *hw); 99 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); 100 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); 101 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data); 102 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data); 103 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data); 104 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data); 105 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); 106 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data); 107 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data); 108 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data); 109 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data); 110 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data); 111 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); 112 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw); 113 s32 e1000_check_polarity_82577(struct e1000_hw *hw); 114 s32 e1000_get_phy_info_82577(struct e1000_hw *hw); 115 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); 116 s32 e1000_get_cable_length_82577(struct e1000_hw *hw); 117 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data); 118 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); 119 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data); 120 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data, 121 bool line_override); 122 bool e1000_is_mphy_ready(struct e1000_hw *hw); 123 124 #define E1000_MAX_PHY_ADDR 8 125 126 /* IGP01E1000 Specific Registers */ 127 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 128 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ 129 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ 130 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 131 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */ 132 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 133 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ 134 #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ 135 #define IGP_PAGE_SHIFT 5 136 #define PHY_REG_MASK 0x1F 137 138 /* GS40G - I210 PHY defines */ 139 #define GS40G_PAGE_SELECT 0x16 140 #define GS40G_PAGE_SHIFT 16 141 #define GS40G_OFFSET_MASK 0xFFFF 142 #define GS40G_PAGE_2 0x20000 143 #define GS40G_MAC_REG2 0x15 144 #define GS40G_MAC_LB 0x4140 145 #define GS40G_MAC_SPEED_1G 0X0006 146 #define GS40G_COPPER_SPEC 0x0010 147 148 /* BM/HV Specific Registers */ 149 #define BM_PORT_CTRL_PAGE 769 150 #define BM_WUC_PAGE 800 151 #define BM_WUC_ADDRESS_OPCODE 0x11 152 #define BM_WUC_DATA_OPCODE 0x12 153 #define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE 154 #define BM_WUC_ENABLE_REG 17 155 #define BM_WUC_ENABLE_BIT (1 << 2) 156 #define BM_WUC_HOST_WU_BIT (1 << 4) 157 #define BM_WUC_ME_WU_BIT (1 << 5) 158 159 #define PHY_UPPER_SHIFT 21 160 #define BM_PHY_REG(page, reg) \ 161 (((reg) & MAX_PHY_REG_ADDRESS) |\ 162 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\ 163 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT))) 164 #define BM_PHY_REG_PAGE(offset) \ 165 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) 166 #define BM_PHY_REG_NUM(offset) \ 167 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ 168 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ 169 ~MAX_PHY_REG_ADDRESS))) 170 171 #define HV_INTC_FC_PAGE_START 768 172 #define I82578_ADDR_REG 29 173 #define I82577_ADDR_REG 16 174 #define I82577_CFG_REG 22 175 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) 176 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift */ 177 #define I82577_CTRL_REG 23 178 179 /* 82577 specific PHY registers */ 180 #define I82577_PHY_CTRL_2 18 181 #define I82577_PHY_LBK_CTRL 19 182 #define I82577_PHY_STATUS_2 26 183 #define I82577_PHY_DIAG_STATUS 31 184 185 /* I82577 PHY Status 2 */ 186 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 187 #define I82577_PHY_STATUS2_MDIX 0x0800 188 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 189 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 190 191 /* I82577 PHY Control 2 */ 192 #define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200 193 #define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400 194 #define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600 195 196 /* I82577 PHY Diagnostics Status */ 197 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC 198 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 199 200 /* 82580 PHY Power Management */ 201 #define E1000_82580_PHY_POWER_MGMT 0xE14 202 #define E1000_82580_PM_SPD 0x0001 /* Smart Power Down */ 203 #define E1000_82580_PM_D0_LPLU 0x0002 /* For D0a states */ 204 #define E1000_82580_PM_D3_LPLU 0x0004 /* For all other states */ 205 #define E1000_82580_PM_GO_LINKD 0x0020 /* Go Link Disconnect */ 206 207 #define E1000_MPHY_DIS_ACCESS 0x80000000 /* disable_access bit */ 208 #define E1000_MPHY_ENA_ACCESS 0x40000000 /* enable_access bit */ 209 #define E1000_MPHY_BUSY 0x00010000 /* busy bit */ 210 #define E1000_MPHY_ADDRESS_FNC_OVERRIDE 0x20000000 /* fnc_override bit */ 211 #define E1000_MPHY_ADDRESS_MASK 0x0000FFFF /* address mask */ 212 213 /* BM PHY Copper Specific Control 1 */ 214 #define BM_CS_CTRL1 16 215 216 /* BM PHY Copper Specific Status */ 217 #define BM_CS_STATUS 17 218 #define BM_CS_STATUS_LINK_UP 0x0400 219 #define BM_CS_STATUS_RESOLVED 0x0800 220 #define BM_CS_STATUS_SPEED_MASK 0xC000 221 #define BM_CS_STATUS_SPEED_1000 0x8000 222 223 /* 82577 Mobile Phy Status Register */ 224 #define HV_M_STATUS 26 225 #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000 226 #define HV_M_STATUS_SPEED_MASK 0x0300 227 #define HV_M_STATUS_SPEED_1000 0x0200 228 #define HV_M_STATUS_SPEED_100 0x0100 229 #define HV_M_STATUS_LINK_UP 0x0040 230 231 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 232 #define IGP01E1000_PHY_POLARITY_MASK 0x0078 233 234 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 235 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ 236 237 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 238 239 /* Enable flexible speed on link-up */ 240 #define IGP01E1000_GMII_FLEX_SPD 0x0010 241 #define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */ 242 243 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 244 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ 245 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ 246 247 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 248 249 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 250 #define IGP01E1000_PSSR_MDIX 0x0800 251 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 252 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 253 254 #define IGP02E1000_PHY_CHANNEL_NUM 4 255 #define IGP02E1000_PHY_AGC_A 0x11B1 256 #define IGP02E1000_PHY_AGC_B 0x12B1 257 #define IGP02E1000_PHY_AGC_C 0x14B1 258 #define IGP02E1000_PHY_AGC_D 0x18B1 259 260 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */ 261 #define IGP02E1000_AGC_LENGTH_MASK 0x7F 262 #define IGP02E1000_AGC_RANGE 15 263 264 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF 265 266 #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 267 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 268 #define E1000_KMRNCTRLSTA_REN 0x00200000 269 #define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */ 270 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ 271 #define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */ 272 #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */ 273 #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */ 274 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ 275 #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7 276 #define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */ 277 #define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */ 278 279 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 280 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */ 281 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */ 282 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ 283 284 /* IFE PHY Extended Status Control */ 285 #define IFE_PESC_POLARITY_REVERSED 0x0100 286 287 /* IFE PHY Special Control */ 288 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 289 #define IFE_PSC_FORCE_POLARITY 0x0020 290 291 /* IFE PHY Special Control and LED Control */ 292 #define IFE_PSCL_PROBE_MODE 0x0020 293 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 294 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 295 296 /* IFE PHY MDIX Control */ 297 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 298 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ 299 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */ 300 301 /* SFP modules ID memory locations */ 302 #define E1000_SFF_IDENTIFIER_OFFSET 0x00 303 #define E1000_SFF_IDENTIFIER_SFF 0x02 304 #define E1000_SFF_IDENTIFIER_SFP 0x03 305 306 #define E1000_SFF_ETH_FLAGS_OFFSET 0x06 307 /* Flags for SFP modules compatible with ETH up to 1Gb */ 308 struct sfp_e1000_flags { 309 u8 e1000_base_sx:1; 310 u8 e1000_base_lx:1; 311 u8 e1000_base_cx:1; 312 u8 e1000_base_t:1; 313 u8 e100_base_lx:1; 314 u8 e100_base_fx:1; 315 u8 e10_base_bx10:1; 316 u8 e10_base_px:1; 317 }; 318 319 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ 320 #define E1000_SFF_VENDOR_OUI_TYCO 0x00407600 321 #define E1000_SFF_VENDOR_OUI_FTL 0x00906500 322 #define E1000_SFF_VENDOR_OUI_AVAGO 0x00176A00 323 #define E1000_SFF_VENDOR_OUI_INTEL 0x001B2100 324 325 #endif 326