xref: /titanic_51/usr/src/uts/common/io/cxgbe/t4nex/t4nex.h (revision 56b2bdd1f04d465cfe4a95b88ae5cba5884154e4)
1*56b2bdd1SGireesh Nagabhushana /*
2*56b2bdd1SGireesh Nagabhushana  * This file and its contents are supplied under the terms of the
3*56b2bdd1SGireesh Nagabhushana  * Common Development and Distribution License ("CDDL"), version 1.0.
4*56b2bdd1SGireesh Nagabhushana  * You may only use this file in accordance with the terms of version
5*56b2bdd1SGireesh Nagabhushana  * 1.0 of the CDDL.
6*56b2bdd1SGireesh Nagabhushana  *
7*56b2bdd1SGireesh Nagabhushana  * A full copy of the text of the CDDL should have accompanied this
8*56b2bdd1SGireesh Nagabhushana  * source. A copy of the CDDL is also available via the Internet at
9*56b2bdd1SGireesh Nagabhushana  * http://www.illumos.org/license/CDDL.
10*56b2bdd1SGireesh Nagabhushana  */
11*56b2bdd1SGireesh Nagabhushana 
12*56b2bdd1SGireesh Nagabhushana /*
13*56b2bdd1SGireesh Nagabhushana  * This file is part of the Chelsio T4 support code.
14*56b2bdd1SGireesh Nagabhushana  *
15*56b2bdd1SGireesh Nagabhushana  * Copyright (C) 2011-2013 Chelsio Communications.  All rights reserved.
16*56b2bdd1SGireesh Nagabhushana  *
17*56b2bdd1SGireesh Nagabhushana  * This program is distributed in the hope that it will be useful, but WITHOUT
18*56b2bdd1SGireesh Nagabhushana  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19*56b2bdd1SGireesh Nagabhushana  * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
20*56b2bdd1SGireesh Nagabhushana  * release for licensing terms and conditions.
21*56b2bdd1SGireesh Nagabhushana  */
22*56b2bdd1SGireesh Nagabhushana 
23*56b2bdd1SGireesh Nagabhushana #ifndef __T4NEX_H
24*56b2bdd1SGireesh Nagabhushana #define	__T4NEX_H
25*56b2bdd1SGireesh Nagabhushana 
26*56b2bdd1SGireesh Nagabhushana #ifdef __cplusplus
27*56b2bdd1SGireesh Nagabhushana extern "C" {
28*56b2bdd1SGireesh Nagabhushana #endif
29*56b2bdd1SGireesh Nagabhushana 
30*56b2bdd1SGireesh Nagabhushana #define	T4_IOCTL		((('t' << 16) | '4') << 8)
31*56b2bdd1SGireesh Nagabhushana #define	T4_IOCTL_PCIGET32	(T4_IOCTL + 1)
32*56b2bdd1SGireesh Nagabhushana #define	T4_IOCTL_PCIPUT32	(T4_IOCTL + 2)
33*56b2bdd1SGireesh Nagabhushana #define	T4_IOCTL_GET32		(T4_IOCTL + 3)
34*56b2bdd1SGireesh Nagabhushana #define	T4_IOCTL_PUT32		(T4_IOCTL + 4)
35*56b2bdd1SGireesh Nagabhushana #define	T4_IOCTL_REGDUMP	(T4_IOCTL + 5)
36*56b2bdd1SGireesh Nagabhushana #define	T4_IOCTL_SGE_CONTEXT	(T4_IOCTL + 6)
37*56b2bdd1SGireesh Nagabhushana #define	T4_IOCTL_DEVLOG		(T4_IOCTL + 7)
38*56b2bdd1SGireesh Nagabhushana #define	T4_IOCTL_GET_MEM	(T4_IOCTL + 8)
39*56b2bdd1SGireesh Nagabhushana #define	T4_IOCTL_GET_TID_TAB	(T4_IOCTL + 9)
40*56b2bdd1SGireesh Nagabhushana #define	T4_IOCTL_GET_MBOX	(T4_IOCTL + 10)
41*56b2bdd1SGireesh Nagabhushana #define	T4_IOCTL_GET_CIM_LA	(T4_IOCTL + 11)
42*56b2bdd1SGireesh Nagabhushana #define	T4_IOCTL_GET_CIM_QCFG	(T4_IOCTL + 12)
43*56b2bdd1SGireesh Nagabhushana #define	T4_IOCTL_GET_CIM_IBQ	(T4_IOCTL + 13)
44*56b2bdd1SGireesh Nagabhushana #define	T4_IOCTL_GET_EDC	(T4_IOCTL + 14)
45*56b2bdd1SGireesh Nagabhushana 
46*56b2bdd1SGireesh Nagabhushana enum {
47*56b2bdd1SGireesh Nagabhushana 	T4_CTXT_EGRESS,
48*56b2bdd1SGireesh Nagabhushana 	T4_CTXT_INGRESS,
49*56b2bdd1SGireesh Nagabhushana 	T4_CTXT_FLM
50*56b2bdd1SGireesh Nagabhushana };
51*56b2bdd1SGireesh Nagabhushana 
52*56b2bdd1SGireesh Nagabhushana struct t4_reg32_cmd {
53*56b2bdd1SGireesh Nagabhushana 	uint32_t reg;
54*56b2bdd1SGireesh Nagabhushana 	uint32_t value;
55*56b2bdd1SGireesh Nagabhushana };
56*56b2bdd1SGireesh Nagabhushana 
57*56b2bdd1SGireesh Nagabhushana #define	T4_REGDUMP_SIZE (160 * 1024)
58*56b2bdd1SGireesh Nagabhushana struct t4_regdump {
59*56b2bdd1SGireesh Nagabhushana 	uint32_t  version;
60*56b2bdd1SGireesh Nagabhushana 	uint32_t  len;
61*56b2bdd1SGireesh Nagabhushana 	uint8_t   *data;
62*56b2bdd1SGireesh Nagabhushana };
63*56b2bdd1SGireesh Nagabhushana 
64*56b2bdd1SGireesh Nagabhushana struct t4_sge_context {
65*56b2bdd1SGireesh Nagabhushana 	uint32_t version;
66*56b2bdd1SGireesh Nagabhushana 	uint32_t mem_id;
67*56b2bdd1SGireesh Nagabhushana 	uint32_t addr;
68*56b2bdd1SGireesh Nagabhushana 	uint32_t len;
69*56b2bdd1SGireesh Nagabhushana 	uint8_t  *data;
70*56b2bdd1SGireesh Nagabhushana };
71*56b2bdd1SGireesh Nagabhushana 
72*56b2bdd1SGireesh Nagabhushana struct t4_mem_range {
73*56b2bdd1SGireesh Nagabhushana 	uint32_t addr;
74*56b2bdd1SGireesh Nagabhushana 	uint32_t len;
75*56b2bdd1SGireesh Nagabhushana 	uint32_t *data;
76*56b2bdd1SGireesh Nagabhushana };
77*56b2bdd1SGireesh Nagabhushana 
78*56b2bdd1SGireesh Nagabhushana struct t4_tid_info {
79*56b2bdd1SGireesh Nagabhushana 	uint32_t len;
80*56b2bdd1SGireesh Nagabhushana 	uint32_t *data;
81*56b2bdd1SGireesh Nagabhushana };
82*56b2bdd1SGireesh Nagabhushana 
83*56b2bdd1SGireesh Nagabhushana struct t4_mbox {
84*56b2bdd1SGireesh Nagabhushana 	uint32_t len;
85*56b2bdd1SGireesh Nagabhushana 	uint32_t *data;
86*56b2bdd1SGireesh Nagabhushana };
87*56b2bdd1SGireesh Nagabhushana 
88*56b2bdd1SGireesh Nagabhushana struct t4_cim_la {
89*56b2bdd1SGireesh Nagabhushana 	uint32_t len;
90*56b2bdd1SGireesh Nagabhushana 	uint32_t *data;
91*56b2bdd1SGireesh Nagabhushana };
92*56b2bdd1SGireesh Nagabhushana 
93*56b2bdd1SGireesh Nagabhushana struct t4_ibq {
94*56b2bdd1SGireesh Nagabhushana 	uint32_t len;
95*56b2bdd1SGireesh Nagabhushana 	uint32_t *data;
96*56b2bdd1SGireesh Nagabhushana };
97*56b2bdd1SGireesh Nagabhushana 
98*56b2bdd1SGireesh Nagabhushana struct t4_edc {
99*56b2bdd1SGireesh Nagabhushana 	uint32_t len;
100*56b2bdd1SGireesh Nagabhushana 	uint32_t mem;
101*56b2bdd1SGireesh Nagabhushana 	uint32_t pos;
102*56b2bdd1SGireesh Nagabhushana 	char *data;
103*56b2bdd1SGireesh Nagabhushana };
104*56b2bdd1SGireesh Nagabhushana 
105*56b2bdd1SGireesh Nagabhushana struct t4_cim_qcfg {
106*56b2bdd1SGireesh Nagabhushana 	uint16_t base[6];
107*56b2bdd1SGireesh Nagabhushana 	uint16_t size[6];
108*56b2bdd1SGireesh Nagabhushana 	uint16_t thres[6];
109*56b2bdd1SGireesh Nagabhushana 	uint32_t stat[4 * (6)];
110*56b2bdd1SGireesh Nagabhushana };
111*56b2bdd1SGireesh Nagabhushana 
112*56b2bdd1SGireesh Nagabhushana #define	T4_DEVLOG_SIZE	32768
113*56b2bdd1SGireesh Nagabhushana struct t4_devlog {
114*56b2bdd1SGireesh Nagabhushana 	uint32_t len;
115*56b2bdd1SGireesh Nagabhushana 	uint8_t  *data;
116*56b2bdd1SGireesh Nagabhushana };
117*56b2bdd1SGireesh Nagabhushana 
118*56b2bdd1SGireesh Nagabhushana #ifdef __cplusplus
119*56b2bdd1SGireesh Nagabhushana }
120*56b2bdd1SGireesh Nagabhushana #endif
121*56b2bdd1SGireesh Nagabhushana 
122*56b2bdd1SGireesh Nagabhushana #endif /* __T4NEX_H */
123