1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _BGE_HW_H 28 #define _BGE_HW_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <sys/types.h> 35 36 37 /* 38 * First section: 39 * Identification of the various Broadcom chips 40 * 41 * Note: the various ID values are *not* all unique ;-( 42 * 43 * Note: the presence of an ID here does *not* imply that the chip is 44 * supported. At this time, only the 5703C, 5704C, and 5704S devices 45 * used on the motherboards of certain Sun products are supported. 46 * 47 * Note: the revision-id values in the PCI revision ID register are 48 * *NOT* guaranteed correct. Use the chip ID from the MHCR instead. 49 */ 50 51 #define VENDOR_ID_BROADCOM 0x14e4 52 #define VENDOR_ID_SUN 0x108e 53 54 #define DEVICE_ID_5700 0x1644 55 #define DEVICE_ID_5700x 0x0003 56 #define DEVICE_ID_5701 0x1645 57 #define DEVICE_ID_5702 0x16a6 58 #define DEVICE_ID_5702fe 0x164d 59 #define DEVICE_ID_5703C 0x16a7 60 #define DEVICE_ID_5703S 0x1647 61 #define DEVICE_ID_5703 0x16c7 62 #define DEVICE_ID_5704C 0x1648 63 #define DEVICE_ID_5704S 0x16a8 64 #define DEVICE_ID_5704 0x1649 65 #define DEVICE_ID_5705C 0x1653 66 #define DEVICE_ID_5705_2 0x1654 67 #define DEVICE_ID_5705M 0x165d 68 #define DEVICE_ID_5705MA3 0x165e 69 #define DEVICE_ID_5705F 0x166e 70 #define DEVICE_ID_5780 0x166a 71 #define DEVICE_ID_5782 0x1696 72 #define DEVICE_ID_5785 0x1699 73 #define DEVICE_ID_5787 0x169b 74 #define DEVICE_ID_5787M 0x1693 75 #define DEVICE_ID_5788 0x169c 76 #define DEVICE_ID_5789 0x169d 77 #define DEVICE_ID_5751 0x1677 78 #define DEVICE_ID_5751M 0x167d 79 #define DEVICE_ID_5752 0x1600 80 #define DEVICE_ID_5752M 0x1601 81 #define DEVICE_ID_5753 0x16fd 82 #define DEVICE_ID_5754 0x167a 83 #define DEVICE_ID_5755 0x167b 84 #define DEVICE_ID_5755M 0x1673 85 #define DEVICE_ID_5756M 0x1674 86 #define DEVICE_ID_5721 0x1659 87 #define DEVICE_ID_5722 0x165a 88 #define DEVICE_ID_5723 0x165b 89 #define DEVICE_ID_5714C 0x1668 90 #define DEVICE_ID_5714S 0x1669 91 #define DEVICE_ID_5715C 0x1678 92 #define DEVICE_ID_5715S 0x1679 93 #define DEVICE_ID_5761E 0x1680 94 #define DEVICE_ID_5761 0x1681 95 #define DEVICE_ID_5764 0x1684 96 #define DEVICE_ID_5906 0x1712 97 #define DEVICE_ID_5906M 0x1713 98 99 #define REVISION_ID_5700_B0 0x10 100 #define REVISION_ID_5700_B2 0x12 101 #define REVISION_ID_5700_B3 0x13 102 #define REVISION_ID_5700_C0 0x20 103 #define REVISION_ID_5700_C1 0x21 104 #define REVISION_ID_5700_C2 0x22 105 106 #define REVISION_ID_5701_A0 0x08 107 #define REVISION_ID_5701_A2 0x12 108 #define REVISION_ID_5701_A3 0x15 109 110 #define REVISION_ID_5702_A0 0x00 111 112 #define REVISION_ID_5703_A0 0x00 113 #define REVISION_ID_5703_A1 0x01 114 #define REVISION_ID_5703_A2 0x02 115 116 #define REVISION_ID_5704_A0 0x00 117 #define REVISION_ID_5704_A1 0x01 118 #define REVISION_ID_5704_A2 0x02 119 #define REVISION_ID_5704_A3 0x03 120 #define REVISION_ID_5704_B0 0x10 121 122 #define REVISION_ID_5705_A0 0x00 123 #define REVISION_ID_5705_A1 0x01 124 #define REVISION_ID_5705_A2 0x02 125 #define REVISION_ID_5705_A3 0x03 126 127 #define REVISION_ID_5721_A0 0x00 128 #define REVISION_ID_5721_A1 0x01 129 130 #define REVISION_ID_5751_A0 0x00 131 #define REVISION_ID_5751_A1 0x01 132 133 #define REVISION_ID_5714_A0 0x00 134 #define REVISION_ID_5714_A1 0x01 135 #define REVISION_ID_5714_A2 0xA2 136 #define REVISION_ID_5714_A3 0xA3 137 138 #define REVISION_ID_5715_A0 0x00 139 #define REVISION_ID_5715_A1 0x01 140 #define REVISION_ID_5715_A2 0xA2 141 142 #define REVISION_ID_5715S_A0 0x00 143 #define REVISION_ID_5715S_A1 0x01 144 145 #define REVISION_ID_5754_A0 0x00 146 #define REVISION_ID_5754_A1 0x01 147 148 #define DEVICE_5704_SERIES_CHIPSETS(bgep)\ 149 ((bgep->chipid.device == DEVICE_ID_5700) ||\ 150 (bgep->chipid.device == DEVICE_ID_5701) ||\ 151 (bgep->chipid.device == DEVICE_ID_5702) ||\ 152 (bgep->chipid.device == DEVICE_ID_5702fe)||\ 153 (bgep->chipid.device == DEVICE_ID_5703C) ||\ 154 (bgep->chipid.device == DEVICE_ID_5703S) ||\ 155 (bgep->chipid.device == DEVICE_ID_5703) ||\ 156 (bgep->chipid.device == DEVICE_ID_5704C) ||\ 157 (bgep->chipid.device == DEVICE_ID_5704S) ||\ 158 (bgep->chipid.device == DEVICE_ID_5704)) 159 160 #define DEVICE_5702_SERIES_CHIPSETS(bgep) \ 161 ((bgep->chipid.device == DEVICE_ID_5702) ||\ 162 (bgep->chipid.device == DEVICE_ID_5702fe)) 163 164 #define DEVICE_5705_SERIES_CHIPSETS(bgep) \ 165 ((bgep->chipid.device == DEVICE_ID_5705C) ||\ 166 (bgep->chipid.device == DEVICE_ID_5705M) ||\ 167 (bgep->chipid.device == DEVICE_ID_5705MA3) ||\ 168 (bgep->chipid.device == DEVICE_ID_5705F) ||\ 169 (bgep->chipid.device == DEVICE_ID_5780) ||\ 170 (bgep->chipid.device == DEVICE_ID_5782) ||\ 171 (bgep->chipid.device == DEVICE_ID_5788) ||\ 172 (bgep->chipid.device == DEVICE_ID_5705_2) ||\ 173 (bgep->chipid.device == DEVICE_ID_5754) ||\ 174 (bgep->chipid.device == DEVICE_ID_5755) ||\ 175 (bgep->chipid.device == DEVICE_ID_5756M) ||\ 176 (bgep->chipid.device == DEVICE_ID_5753)) 177 178 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \ 179 ((bgep->chipid.device == DEVICE_ID_5721) ||\ 180 (bgep->chipid.device == DEVICE_ID_5751) ||\ 181 (bgep->chipid.device == DEVICE_ID_5751M) ||\ 182 (bgep->chipid.device == DEVICE_ID_5752) ||\ 183 (bgep->chipid.device == DEVICE_ID_5752M) ||\ 184 (bgep->chipid.device == DEVICE_ID_5789)) 185 186 #define DEVICE_5723_SERIES_CHIPSETS(bgep) \ 187 ((bgep->chipid.device == DEVICE_ID_5723) ||\ 188 (bgep->chipid.device == DEVICE_ID_5761) ||\ 189 (bgep->chipid.device == DEVICE_ID_5761E) ||\ 190 (bgep->chipid.device == DEVICE_ID_5764) ||\ 191 (bgep->chipid.device == DEVICE_ID_5785)) 192 193 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \ 194 ((bgep->chipid.device == DEVICE_ID_5714C) ||\ 195 (bgep->chipid.device == DEVICE_ID_5714S) ||\ 196 (bgep->chipid.device == DEVICE_ID_5715C) ||\ 197 (bgep->chipid.device == DEVICE_ID_5715S)) 198 199 #define DEVICE_5906_SERIES_CHIPSETS(bgep) \ 200 ((bgep->chipid.device == DEVICE_ID_5906) ||\ 201 (bgep->chipid.device == DEVICE_ID_5906M)) 202 203 /* 204 * Second section: 205 * Offsets of important registers & definitions for bits therein 206 */ 207 208 /* 209 * PCI-X registers & bits 210 */ 211 #define PCIX_CONF_COMM 0x42 212 #define PCIX_COMM_RELAXED 0x0002 213 214 /* 215 * Miscellaneous Host Control Register, in PCI config space 216 */ 217 #define PCI_CONF_BGE_MHCR 0x68 218 #define MHCR_CHIP_REV_MASK 0xffff0000 219 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200 220 #define MHCR_MASK_INTERRUPT_MODE 0x00000100 221 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080 222 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040 223 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020 224 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010 225 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008 226 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004 227 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002 228 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001 229 230 #define MHCR_CHIP_REV_5700_B0 0x71000000 231 #define MHCR_CHIP_REV_5700_B2 0x71020000 232 #define MHCR_CHIP_REV_5700_B3 0x71030000 233 #define MHCR_CHIP_REV_5700_C0 0x72000000 234 #define MHCR_CHIP_REV_5700_C1 0x72010000 235 #define MHCR_CHIP_REV_5700_C2 0x72020000 236 237 #define MHCR_CHIP_REV_5701_A0 0x00000000 238 #define MHCR_CHIP_REV_5701_A2 0x00020000 239 #define MHCR_CHIP_REV_5701_A3 0x00030000 240 #define MHCR_CHIP_REV_5701_A5 0x01050000 241 242 #define MHCR_CHIP_REV_5702_A0 0x10000000 243 #define MHCR_CHIP_REV_5702_A1 0x10010000 244 #define MHCR_CHIP_REV_5702_A2 0x10020000 245 246 #define MHCR_CHIP_REV_5703_A0 0x10000000 247 #define MHCR_CHIP_REV_5703_A1 0x10010000 248 #define MHCR_CHIP_REV_5703_A2 0x10020000 249 #define MHCR_CHIP_REV_5703_B0 0x11000000 250 #define MHCR_CHIP_REV_5703_B1 0x11010000 251 252 #define MHCR_CHIP_REV_5704_A0 0x20000000 253 #define MHCR_CHIP_REV_5704_A1 0x20010000 254 #define MHCR_CHIP_REV_5704_A2 0x20020000 255 #define MHCR_CHIP_REV_5704_A3 0x20030000 256 #define MHCR_CHIP_REV_5704_B0 0x21000000 257 258 #define MHCR_CHIP_REV_5705_A0 0x30000000 259 #define MHCR_CHIP_REV_5705_A1 0x30010000 260 #define MHCR_CHIP_REV_5705_A2 0x30020000 261 #define MHCR_CHIP_REV_5705_A3 0x30030000 262 #define MHCR_CHIP_REV_5705_A5 0x30050000 263 264 #define MHCR_CHIP_REV_5782_A0 0x30030000 265 #define MHCR_CHIP_REV_5782_A1 0x30030088 266 267 #define MHCR_CHIP_REV_5788_A1 0x30050000 268 269 #define MHCR_CHIP_REV_5751_A0 0x40000000 270 #define MHCR_CHIP_REV_5751_A1 0x40010000 271 272 #define MHCR_CHIP_REV_5721_A0 0x41000000 273 #define MHCR_CHIP_REV_5721_A1 0x41010000 274 275 #define MHCR_CHIP_REV_5714_A0 0x50000000 276 #define MHCR_CHIP_REV_5714_A1 0x90010000 277 278 #define MHCR_CHIP_REV_5715_A0 0x50000000 279 #define MHCR_CHIP_REV_5715_A1 0x90010000 280 281 #define MHCR_CHIP_REV_5715S_A0 0x50000000 282 #define MHCR_CHIP_REV_5715S_A1 0x90010000 283 284 #define MHCR_CHIP_REV_5754_A0 0xb0000000 285 #define MHCR_CHIP_REV_5754_A1 0xb0010000 286 287 #define MHCR_CHIP_REV_5787_A0 0xb0000000 288 #define MHCR_CHIP_REV_5787_A1 0xb0010000 289 #define MHCR_CHIP_REV_5787_A2 0xb0020000 290 291 #define MHCR_CHIP_REV_5755_A0 0xa0000000 292 #define MHCR_CHIP_REV_5755_A1 0xa0010000 293 294 #define MHCR_CHIP_REV_5906_A0 0xc0000000 295 #define MHCR_CHIP_REV_5906_A1 0xc0010000 296 #define MHCR_CHIP_REV_5906_A2 0xc0020000 297 298 #define MHCR_CHIP_REV_5723_A0 0xf0000000 299 #define MHCR_CHIP_REV_5723_A1 0xf0010000 300 #define MHCR_CHIP_REV_5723_A2 0xf0020000 301 #define MHCR_CHIP_REV_5723_B0 0xf1000000 302 303 #define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000) 304 #define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28) 305 #define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28) 306 #define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28) 307 #define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28) 308 #define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28) 309 #define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28) 310 #define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28) 311 #define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28) 312 #define MHCR_CHIP_ASIC_REV_5754 (0xb << 28) 313 #define MHCR_CHIP_ASIC_REV_5787 ((uint32_t)0xb << 28) 314 #define MHCR_CHIP_ASIC_REV_5755 ((uint32_t)0xa << 28) 315 #define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28) 316 #define MHCR_CHIP_ASIC_REV_5906 ((uint32_t)0xc << 28) 317 #define MHCR_CHIP_ASIC_REV_5723 ((uint32_t)0xf << 28) 318 319 320 /* 321 * PCI DMA read/write Control Register, in PCI config space 322 * 323 * Note that several fields previously defined here have been deleted 324 * as they are not implemented in the 5703/4. 325 * 326 * Note: the value of this register is critical. It is possible to 327 * cause various unpleasant effects (DTOs, transaction deadlock, etc) 328 * by programming the wrong value. The value #defined below has been 329 * tested and shown to avoid all known problems. If it is to be changed, 330 * correct operation must be reverified on all supported platforms. 331 * 332 * In particular, we set both watermark fields to 2xCacheLineSize (128) 333 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions 334 * with Tomatillo's internal pipelines, that otherwise result in stalls, 335 * repeated retries, and DTOs. 336 */ 337 #define PCI_CONF_BGE_PDRWCR 0x6c 338 #define PDRWCR_RWCMD_MASK 0xFF000000 339 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000 340 #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000 341 #define PDRWCR_READ_WATERMARK_MASK 0x00070000 342 #define PDRWCR_CONCURRENCY_MASK 0x0000c000 343 #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000 344 #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000 345 #define PDRWCR_MIN_BEAT_MASK 0x000000ff 346 347 /* 348 * These are the actual values to be put into the fields shown above 349 */ 350 #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */ 351 #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */ 352 #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */ 353 #define PDRWCR_MIN_BEATS 0x00000000 354 355 #define PDRWCR_VAR_DEFAULT 0x761b0000 356 #define PDRWCR_VAR_5721 0x76180000 357 #define PDRWCR_VAR_5714 0x76148000 /* OR of above */ 358 #define PDRWCR_VAR_5715 0x76144000 /* OR of above */ 359 360 /* 361 * PCI State Register, in PCI config space 362 * 363 * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit 364 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW 365 */ 366 #define PCI_CONF_BGE_PCISTATE 0x70 367 #define PCISTATE_RETRY_SAME_DMA 0x00002000 368 #define PCISTATE_FLAT_VIEW 0x00000100 369 #define PCISTATE_EXT_ROM_RETRY 0x00000040 370 #define PCISTATE_EXT_ROM_ENABLE 0x00000020 371 #define PCISTATE_BUS_IS_32_BIT 0x00000010 372 #define PCISTATE_BUS_IS_FAST 0x00000008 373 #define PCISTATE_BUS_IS_PCI 0x00000004 374 #define PCISTATE_INTA_STATE 0x00000002 375 #define PCISTATE_FORCE_RESET 0x00000001 376 377 /* 378 * PCI Clock Control Register, in PCI config space 379 */ 380 #define PCI_CONF_BGE_CLKCTL 0x74 381 #define CLKCTL_PCIE_PLP_DISABLE 0x80000000 382 #define CLKCTL_PCIE_DLP_DISABLE 0x40000000 383 #define CLKCTL_PCIE_TLP_DISABLE 0x20000000 384 #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000 385 #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000 386 #define CLKCTL_PCIE_A0_FIX 0x00101000 387 388 /* 389 * Dual MAC Control Register, in PCI config space 390 */ 391 #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8 392 #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */ 393 #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */ 394 395 /* 396 * Register Indirect Access Address Register, 0x78 in PCI config 397 * space. Once this is set, accesses to the Register Indirect 398 * Access Data Register (0x80) refer to the register whose address 399 * is given by *this* register. This allows access to all the 400 * operating registers, while using only config space accesses. 401 * 402 * Note that the address written to the RIIAR should lie in one 403 * of the following ranges: 404 * 0x00000000 <= address < 0x00008000 (regular registers) 405 * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad) 406 * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad) 407 * 0x00038000 <= address < 0x00038800 (RxRISC ROM) 408 */ 409 #define PCI_CONF_BGE_RIAAR 0x78 410 #define PCI_CONF_BGE_RIADR 0x80 411 412 #define RIAAR_REGISTER_MIN 0x00000000 413 #define RIAAR_REGISTER_MAX 0x00008000 414 #define RIAAR_RX_SCRATCH_MIN 0x00030000 415 #define RIAAR_RX_SCRATCH_MAX 0x00034000 416 #define RIAAR_TX_SCRATCH_MIN 0x00034000 417 #define RIAAR_TX_SCRATCH_MAX 0x00038000 418 #define RIAAR_RXROM_MIN 0x00038000 419 #define RIAAR_RXROM_MAX 0x00038800 420 421 /* 422 * Memory Window Base Address Register, 0x7c in PCI config space 423 * Once this is set, accesses to the Memory Window Data Access Register 424 * (0x84) refer to the word of NIC-local memory whose address is given 425 * by this register. When used in this way, the whole of the address 426 * written to this register is significant. 427 * 428 * This register also provides the 32K-aligned base address for a 32K 429 * region of NIC-local memory that the host can directly address in 430 * the upper 32K of the 64K of PCI memory space allocated to the chip. 431 * In this case, the bottom 15 bits of the register are ignored. 432 * 433 * Note that the address written to the MWBAR should lie in the range 434 * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M 435 * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external 436 * memory were present, but it's only supported on the 5700, not the 437 * 5701/5703/5704. 438 */ 439 #define PCI_CONF_BGE_MWBAR 0x7c 440 #define PCI_CONF_BGE_MWDAR 0x84 441 #define MWBAR_GRANULARITY 0x00008000 /* 32k */ 442 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1) 443 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */ 444 445 /* 446 * The PCI express device control register and device status register 447 * which are only applicable on BCM5751 and BCM5721. 448 */ 449 #define PCI_CONF_DEV_CTRL 0xd8 450 #define PCI_CONF_DEV_CTRL_5723 0xd4 451 #define READ_REQ_SIZE_MAX 0x5000 452 #define DEV_CTRL_NO_SNOOP 0x0800 453 #define DEV_CTRL_RELAXED 0x0010 454 455 #define PCI_CONF_DEV_STUS 0xda 456 #define PCI_CONF_DEV_STUS_5723 0xd6 457 #define DEVICE_ERROR_STUS 0xf 458 459 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */ 460 461 /* 462 * Where to find things in NIC-local (on-chip) memory 463 */ 464 #define NIC_MEM_SEND_RINGS 0x0100 465 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring)) 466 #define NIC_MEM_RECV_RINGS 0x0200 467 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring)) 468 #define NIC_MEM_STATISTICS 0x0300 469 #define NIC_MEM_STATISTICS_SIZE 0x0800 470 #define NIC_MEM_STATUS_BLOCK 0x0b00 471 #define NIC_MEM_STATUS_SIZE 0x0050 472 #define NIC_MEM_GENCOMM 0x0b50 473 474 475 /* 476 * Note: the (non-bogus) values below are appropriate for systems 477 * without external memory. They would be different on a 5700 with 478 * external memory. 479 * 480 * Note: The higher send ring addresses and the mini ring shadow 481 * buffer address are dummies - systems without external memory 482 * are limited to 4 send rings and no mini receive ring. 483 */ 484 #define NIC_MEM_SHADOW_DMA 0x2000 485 #define NIC_MEM_SHADOW_SEND_1_4 0x4000 486 #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */ 487 #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */ 488 #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */ 489 #define NIC_MEM_SHADOW_BUFF_STD 0x6000 490 #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000 491 #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */ 492 #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots)) 493 494 /* 495 * Put this in the GENCOMM port to tell the firmware not to run PXE 496 */ 497 #define T3_MAGIC_NUMBER 0x4b657654u 498 499 /* 500 * The remaining registers appear in the low 32K of regular 501 * PCI Memory Address Space 502 */ 503 504 /* 505 * All the state machine control registers below have at least a 506 * <RESET> bit and an <ENABLE> bit as defined below. Some also 507 * have an <ATTN_ENABLE> bit. 508 */ 509 #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004 510 #define STATE_MACHINE_ENABLE_BIT 0x00000002 511 #define STATE_MACHINE_RESET_BIT 0x00000001 512 513 #define TRANSMIT_MAC_MODE_REG 0x045c 514 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00 515 #define SEND_DATA_COMPLETION_MODE_REG 0x1000 516 #define SEND_BD_SELECTOR_MODE_REG 0x1400 517 #define SEND_BD_INITIATOR_MODE_REG 0x1800 518 #define SEND_BD_COMPLETION_MODE_REG 0x1c00 519 520 #define RECEIVE_MAC_MODE_REG 0x0468 521 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000 522 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400 523 #define RCV_DATA_COMPLETION_MODE_REG 0x2800 524 #define RCV_BD_INITIATOR_MODE_REG 0x2c00 525 #define RCV_BD_COMPLETION_MODE_REG 0x3000 526 #define RCV_LIST_SELECTOR_MODE_REG 0x3400 527 528 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800 529 #define HOST_COALESCE_MODE_REG 0x3c00 530 #define MEMORY_ARBITER_MODE_REG 0x4000 531 #define BUFFER_MANAGER_MODE_REG 0x4400 532 #define READ_DMA_MODE_REG 0x4800 533 #define WRITE_DMA_MODE_REG 0x4c00 534 #define DMA_COMPLETION_MODE_REG 0x6400 535 536 /* 537 * Other bits in some of the above state machine control registers 538 */ 539 540 /* 541 * Transmit MAC Mode Register 542 * (TRANSMIT_MAC_MODE_REG, 0x045c) 543 */ 544 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040 545 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020 546 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010 547 548 /* 549 * Receive MAC Mode Register 550 * (RECEIVE_MAC_MODE_REG, 0x0468) 551 */ 552 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400 553 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200 554 #define RECEIVE_MODE_PROMISCUOUS 0x00000100 555 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080 556 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040 557 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020 558 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010 559 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004 560 561 /* 562 * Receive BD Initiator Mode Register 563 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00) 564 * 565 * Each of these bits controls whether ATTN is asserted 566 * on a particular condition 567 */ 568 #define RCV_BD_DISABLED_RING_ATTN 0x00000004 569 570 /* 571 * Receive Data & Receive BD Initiator Mode Register 572 * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400) 573 * 574 * Each of these bits controls whether ATTN is asserted 575 * on a particular condition 576 */ 577 #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010 578 #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008 579 #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004 580 581 #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c 582 583 /* 584 * Host Coalescing Mode Control Register 585 * (HOST_COALESCE_MODE_REG, 0x3c00) 586 */ 587 #define COALESCE_64_BYTE_RINGS 12 588 #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000 589 #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800 590 #define COALESCE_CLR_TICKS_TX 0x00000400 591 #define COALESCE_CLR_TICKS_RX 0x00000200 592 #define COALESCE_32_BYTE_STATUS 0x00000100 593 #define COALESCE_64_BYTE_STATUS 0x00000080 594 #define COALESCE_NOW 0x00000008 595 596 /* 597 * Memory Arbiter Mode Register 598 * (MEMORY_ARBITER_MODE_REG, 0x4000) 599 */ 600 #define MEMORY_ARBITER_ENABLE 0x00000002 601 602 /* 603 * Buffer Manager Mode Register 604 * (BUFFER_MANAGER_MODE_REG, 0x4400) 605 * 606 * In addition to the usual error-attn common to most state machines 607 * this register has a separate bit for attn on running-low-on-mbufs 608 */ 609 #define BUFF_MGR_TEST_MODE 0x00000008 610 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010 611 612 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014 613 614 /* 615 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG, 616 * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00) 617 * 618 * These registers each contain a 2-bit priority field, which controls 619 * the relative priority of that type of DMA (read vs. write vs. MSI), 620 * and a set of bits that control whether ATTN is asserted on each 621 * particular condition 622 */ 623 #define DMA_PRIORITY_MASK 0xc0000000 624 #define DMA_PRIORITY_SHIFT 30 625 #define ALL_DMA_ATTN_BITS 0x000003fc 626 627 /* 628 * BCM5755, 5755M, 5906, 5906M only 629 * 1 - Enable Fix. Device will send out the status block before 630 * the interrupt message 631 * 0 - Disable fix. Device will send out the interrupt message 632 * before the status block 633 */ 634 #define DMA_STATUS_TAG_FIX_CQ12384 0x20000000 635 636 /* 637 * End of state machine control register definitions 638 */ 639 640 641 /* 642 * High priority mailbox registers. 643 * Mailbox Registers (8 bytes each, but high half unused) 644 */ 645 #define INTERRUPT_MBOX_0_REG 0x0200 646 #define INTERRUPT_MBOX_1_REG 0x0208 647 #define INTERRUPT_MBOX_2_REG 0x0210 648 #define INTERRUPT_MBOX_3_REG 0x0218 649 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n)) 650 651 /* 652 * Low priority mailbox registers, for BCM5906, BCM5906M. 653 */ 654 #define INTERRUPT_LP_MBOX_0_REG 0x5800 655 656 /* 657 * Ring Producer/Consumer Index (Mailbox) Registers 658 */ 659 #define RECV_STD_PROD_INDEX_REG 0x0268 660 #define RECV_JUMBO_PROD_INDEX_REG 0x0270 661 #define RECV_MINI_PROD_INDEX_REG 0x0278 662 #define RECV_RING_CONS_INDEX_REGS 0x0280 663 #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300 664 #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380 665 666 #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring)) 667 #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring)) 668 #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring)) 669 670 /* 671 * Ethernet MAC Mode Register 672 */ 673 #define ETHERNET_MAC_MODE_REG 0x0400 674 #define ETHERNET_MODE_ENABLE_FHDE 0x00800000 675 #define ETHERNET_MODE_ENABLE_RDE 0x00400000 676 #define ETHERNET_MODE_ENABLE_TDE 0x00200000 677 #define ETHERNET_MODE_ENABLE_MIP 0x00100000 678 #define ETHERNET_MODE_ENABLE_ACPI 0x00080000 679 #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000 680 #define ETHERNET_MODE_SEND_CFGS 0x00020000 681 #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000 682 #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000 683 #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000 684 #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000 685 #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000 686 #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800 687 #define ETHERNET_MODE_LINK_POLARITY 0x00000400 688 #define ETHERNET_MODE_MAX_DEFER 0x00000200 689 #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100 690 #define ETHERNET_MODE_TAGGED_MODE 0x00000080 691 #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010 692 #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c 693 #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c 694 #define ETHERNET_MODE_PORTMODE_GMII 0x00000008 695 #define ETHERNET_MODE_PORTMODE_MII 0x00000004 696 #define ETHERNET_MODE_PORTMODE_NONE 0x00000000 697 #define ETHERNET_MODE_HALF_DUPLEX 0x00000002 698 #define ETHERNET_MODE_GLOBAL_RESET 0x00000001 699 700 /* 701 * Ethernet MAC Status & Event Registers 702 */ 703 #define ETHERNET_MAC_STATUS_REG 0x0404 704 #define ETHERNET_STATUS_MI_INT 0x00800000 705 #define ETHERNET_STATUS_MI_COMPLETE 0x00400000 706 #define ETHERNET_STATUS_LINK_CHANGED 0x00001000 707 #define ETHERNET_STATUS_PCS_ERROR 0x00000400 708 #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010 709 #define ETHERNET_STATUS_CFG_CHANGED 0x00000008 710 #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004 711 #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002 712 #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001 713 714 #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408 715 #define ETHERNET_EVENT_MI_INT 0x00800000 716 #define ETHERNET_EVENT_LINK_INT 0x00001000 717 #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400 718 719 /* 720 * Ethernet MAC LED Control Register 721 * 722 * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and 723 * the external LED driver circuitry is wired up to assume that this mode 724 * will always be selected. Software must not change it! 725 */ 726 #define ETHERNET_MAC_LED_CONTROL_REG 0x040c 727 #define LED_CONTROL_OVERRIDE_BLINK 0x80000000 728 #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000 729 #define LED_CONTROL_LED_MODE_MASK 0x00001800 730 #define LED_CONTROL_LED_MODE_5700 0x00000000 731 #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */ 732 #define LED_CONTROL_LED_MODE_PHY_2 0x00001000 733 #define LED_CONTROL_LED_MODE_RESERVED 0x00001800 734 #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400 735 #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200 736 #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100 737 #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080 738 #define LED_CONTROL_BLINK_TRAFFIC 0x00000040 739 #define LED_CONTROL_TRAFFIC_LED 0x00000020 740 #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010 741 #define LED_CONTROL_10MBPS_LED 0x00000008 742 #define LED_CONTROL_100MBPS_LED 0x00000004 743 #define LED_CONTROL_1000MBPS_LED 0x00000002 744 #define LED_CONTROL_OVERRIDE_LINK 0x00000001 745 #define LED_CONTROL_DEFAULT 0x02000800 746 747 /* 748 * MAC Address registers 749 * 750 * These four eight-byte registers each hold one unicast address 751 * (six bytes), right justified & zero-filled on the left. 752 * They will normally all be set to the same value, as a station 753 * usually only has one h/w address. The value in register 0 is 754 * used for pause packets; any of the four can be specified for 755 * substitution into other transmitted packets if required. 756 */ 757 #define MAC_ADDRESS_0_REG 0x0410 758 #define MAC_ADDRESS_1_REG 0x0418 759 #define MAC_ADDRESS_2_REG 0x0420 760 #define MAC_ADDRESS_3_REG 0x0428 761 762 #define MAC_ADDRESS_REG(n) (0x0410+8*(n)) 763 #define MAC_ADDRESS_REGS_MAX 4 764 765 /* 766 * More MAC Registers ... 767 */ 768 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438 769 #define MAC_RX_MTU_SIZE_REG 0x043c 770 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */ 771 #define MAC_TX_LENGTHS_REG 0x0464 772 #define MAC_TX_LENGTHS_DEFAULT 0x00002620 773 774 /* 775 * MII access registers 776 */ 777 #define MI_COMMS_REG 0x044c 778 #define MI_COMMS_START 0x20000000 779 #define MI_COMMS_READ_FAILED 0x10000000 780 #define MI_COMMS_COMMAND_MASK 0x0c000000 781 #define MI_COMMS_COMMAND_READ 0x08000000 782 #define MI_COMMS_COMMAND_WRITE 0x04000000 783 #define MI_COMMS_ADDRESS_MASK 0x03e00000 784 #define MI_COMMS_ADDRESS_SHIFT 21 785 #define MI_COMMS_REGISTER_MASK 0x001f0000 786 #define MI_COMMS_REGISTER_SHIFT 16 787 #define MI_COMMS_DATA_MASK 0x0000ffff 788 #define MI_COMMS_DATA_SHIFT 0 789 790 #define MI_STATUS_REG 0x0450 791 #define MI_STATUS_10MBPS 0x00000002 792 #define MI_STATUS_LINK 0x00000001 793 794 #define MI_MODE_REG 0x0454 795 #define MI_MODE_CLOCK_MASK 0x001f0000 796 #define MI_MODE_AUTOPOLL 0x00000010 797 #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002 798 #define MI_MODE_DEFAULT 0x000c0000 799 800 #define MI_AUTOPOLL_STATUS_REG 0x0458 801 #define MI_AUTOPOLL_ERROR 0x00000001 802 803 #define TRANSMIT_MAC_STATUS_REG 0x0460 804 #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020 805 #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010 806 #define TRANSMIT_STATUS_LINK_UP 0x00000008 807 #define TRANSMIT_STATUS_SENT_XON 0x00000004 808 #define TRANSMIT_STATUS_SENT_XOFF 0x00000002 809 #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001 810 811 #define RECEIVE_MAC_STATUS_REG 0x046c 812 #define RECEIVE_STATUS_RCVD_XON 0x00000004 813 #define RECEIVE_STATUS_RCVD_XOFF 0x00000002 814 #define RECEIVE_STATUS_SENT_XOFF 0x00000001 815 816 /* 817 * These four-byte registers constitute a hash table for deciding 818 * whether to accept incoming multicast packets. The bits are 819 * numbered in big-endian fashion, from hash 0 => the MSB of 820 * register 0 to hash 127 => the LSB of the highest-numbered 821 * register. 822 * 823 * NOTE: the 5704 can use a 256-bit table (registers 0-7) if 824 * enabled by setting the appropriate bit in the Rx MAC mode 825 * register. Otherwise, and on all earlier chips, the table 826 * is only 128 bits (registers 0-3). 827 */ 828 #define MAC_HASH_0_REG 0x0470 829 #define MAC_HASH_1_REG 0x0474 830 #define MAC_HASH_2_REG 0x0478 831 #define MAC_HASH_3_REG 0x047c 832 #define MAC_HASH_4_REG 0x???? 833 #define MAC_HASH_5_REG 0x???? 834 #define MAC_HASH_6_REG 0x???? 835 #define MAC_HASH_7_REG 0x???? 836 #define MAC_HASH_REG(n) (0x470+4*(n)) 837 838 /* 839 * Receive Rules Registers: 16 pairs of control+mask/value pairs 840 */ 841 #define RCV_RULES_CONTROL_0_REG 0x0480 842 #define RCV_RULES_MASK_0_REG 0x0484 843 #define RCV_RULES_CONTROL_15_REG 0x04f8 844 #define RCV_RULES_MASK_15_REG 0x04fc 845 #define RCV_RULES_CONFIG_REG 0x0500 846 #define RCV_RULES_CONFIG_DEFAULT 0x00000008 847 848 #define RECV_RULES_NUM_MAX 16 849 #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule)) 850 #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule)) 851 852 #define RECV_RULE_CTL_ENABLE 0x80000000 853 #define RECV_RULE_CTL_AND 0x40000000 854 #define RECV_RULE_CTL_P1 0x20000000 855 #define RECV_RULE_CTL_P2 0x10000000 856 #define RECV_RULE_CTL_P3 0x08000000 857 #define RECV_RULE_CTL_MASK 0x04000000 858 #define RECV_RULE_CTL_DISCARD 0x02000000 859 #define RECV_RULE_CTL_MAP 0x01000000 860 #define RECV_RULE_CTL_RESV_BITS 0x00fc0000 861 #define RECV_RULE_CTL_OP 0x00030000 862 #define RECV_RULE_CTL_OP_EQ 0x00000000 863 #define RECV_RULE_CTL_OP_NEQ 0x00010000 864 #define RECV_RULE_CTL_OP_GREAT 0x00020000 865 #define RECV_RULE_CTL_OP_LESS 0x00030000 866 #define RECV_RULE_CTL_HEADER 0x0000e000 867 #define RECV_RULE_CTL_HEADER_FRAME 0x00000000 868 #define RECV_RULE_CTL_HEADER_IP 0x00002000 869 #define RECV_RULE_CTL_HEADER_TCP 0x00004000 870 #define RECV_RULE_CTL_HEADER_UDP 0x00006000 871 #define RECV_RULE_CTL_HEADER_DATA 0x00008000 872 #define RECV_RULE_CTL_CLASS_BITS 0x00001f00 873 #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \ 874 RECV_RULE_CTL_CLASS_BITS) 875 #define RECV_RULE_CTL_OFFSET 0x000000ff 876 877 /* 878 * Receive Rules definition 879 */ 880 #define ETHERHEADER_DEST_OFFSET 0x00 881 #define IPHEADER_PROTO_OFFSET 0x08 882 #define IPHEADER_SIP_OFFSET 0x0c 883 #define IPHEADER_DIP_OFFSET 0x10 884 #define TCPHEADER_SPORT_OFFSET 0x00 885 #define TCPHEADER_DPORT_OFFSET 0x02 886 #define UDPHEADER_SPORT_OFFSET 0x00 887 #define UDPHEADER_DPORT_OFFSET 0x02 888 889 #define RULE_MATCH(ring) (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \ 890 RECV_RULE_CTL_CLASS((ring))) 891 892 #define RULE_MATCH_MASK(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_MASK) 893 894 #define RULE_DEST_MAC_1(ring) (RULE_MATCH(ring) | \ 895 RECV_RULE_CTL_HEADER_FRAME | \ 896 ETHERHEADER_DEST_OFFSET) 897 898 #define RULE_DEST_MAC_2(ring) (RULE_MATCH_MASK(ring) | \ 899 RECV_RULE_CTL_HEADER_FRAME | \ 900 ETHERHEADER_DEST_OFFSET + 4) 901 902 #define RULE_LOCAL_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \ 903 IPHEADER_DIP_OFFSET) 904 905 #define RULE_REMOTE_IP(ring) (RULE_MATCH(ring) | RECV_RULE_CTL_HEADER_IP | \ 906 IPHEADER_SIP_OFFSET) 907 908 #define RULE_IP_PROTO(ring) (RULE_MATCH_MASK(ring) | \ 909 RECV_RULE_CTL_HEADER_IP | \ 910 IPHEADER_PROTO_OFFSET) 911 912 #define RULE_TCP_SPORT(ring) (RULE_MATCH_MASK(ring) | \ 913 RECV_RULE_CTL_HEADER_TCP | \ 914 TCPHEADER_SPORT_OFFSET) 915 916 #define RULE_TCP_DPORT(ring) (RULE_MATCH_MASK(ring) | \ 917 RECV_RULE_CTL_HEADER_TCP | \ 918 TCPHEADER_DPORT_OFFSET) 919 920 #define RULE_UDP_SPORT(ring) (RULE_MATCH_MASK(ring) | \ 921 RECV_RULE_CTL_HEADER_UDP | \ 922 UDPHEADER_SPORT_OFFSET) 923 924 #define RULE_UDP_DPORT(ring) (RULE_MATCH_MASK(ring) | \ 925 RECV_RULE_CTL_HEADER_UDP | \ 926 UDPHEADER_DPORT_OFFSET) 927 928 /* 929 * 1000BaseX low-level access registers 930 */ 931 #define MAC_GIGABIT_PCS_TEST_REG 0x0440 932 #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000 933 #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff 934 #define TX_1000BASEX_AUTONEG_REG 0x0444 935 #define RX_1000BASEX_AUTONEG_REG 0x0448 936 937 /* 938 * Autoneg code bits for the 1000BASE-X AUTONEG registers 939 */ 940 #define AUTONEG_CODE_PAUSE 0x00008000 941 #define AUTONEG_CODE_HALF_DUPLEX 0x00004000 942 #define AUTONEG_CODE_FULL_DUPLEX 0x00002000 943 #define AUTONEG_CODE_NEXT_PAGE 0x00000080 944 #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040 945 #define AUTONEG_CODE_FAULT_MASK 0x00000030 946 #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030 947 #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020 948 #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010 949 #define AUTONEG_CODE_ASYM_PAUSE 0x00000001 950 951 /* 952 * SerDes Registers (5703S/5704S only) 953 */ 954 #define SERDES_CONTROL_REG 0x0590 955 #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000 956 #define SERDES_CONTROL_COMMA_DETECT 0x00010000 957 #define SERDES_CONTROL_TX_DISABLE 0x00004000 958 #define SERDES_STATUS_REG 0x0594 959 #define SERDES_STATUS_COMMA_DETECTED 0x00000100 960 #define SERDES_STATUS_RXSTAT 0x000000ff 961 962 /* 963 * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only) 964 */ 965 #define STAT_IFHCOUT_OCTETS_REG 0x0800 966 #define STAT_ETHER_COLLIS_REG 0x0808 967 #define STAT_OUTXON_SENT_REG 0x080c 968 #define STAT_OUTXOFF_SENT_REG 0x0810 969 #define STAT_DOT3_INTMACTX_ERR_REG 0x0818 970 #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c 971 #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820 972 #define STAT_DOT3_DEFERED_TX_REG 0x0824 973 #define STAT_DOT3_EXCE_COLLI_REG 0x082c 974 #define STAT_DOT3_LATE_COLLI_REG 0x0830 975 #define STAT_IFHCOUT_UPKGS_REG 0x086c 976 #define STAT_IFHCOUT_MPKGS_REG 0x0870 977 #define STAT_IFHCOUT_BPKGS_REG 0x0874 978 979 #define STAT_IFHCIN_OCTETS_REG 0x0880 980 #define STAT_ETHER_FRAGMENT_REG 0x0888 981 #define STAT_IFHCIN_UPKGS_REG 0x088c 982 #define STAT_IFHCIN_MPKGS_REG 0x0890 983 #define STAT_IFHCIN_BPKGS_REG 0x0894 984 985 #define STAT_DOT3_FCS_ERR_REG 0x0898 986 #define STAT_DOT3_ALIGN_ERR_REG 0x089c 987 #define STAT_XON_PAUSE_RX_REG 0x08a0 988 #define STAT_XOFF_PAUSE_RX_REG 0x08a4 989 #define STAT_MAC_CTRL_RX_REG 0x08a8 990 #define STAT_XOFF_STATE_ENTER_REG 0x08ac 991 #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0 992 #define STAT_ETHER_JABBERS_REG 0x08b4 993 #define STAT_ETHER_UNDERSIZE_REG 0x08b8 994 #define SIZE_OF_STATISTIC_REG 0x1B 995 /* 996 * Send Data Initiator Registers 997 */ 998 #define SEND_INIT_STATS_CONTROL_REG 0x0c08 999 #define SEND_INIT_STATS_ZERO 0x00000010 1000 #define SEND_INIT_STATS_FLUSH 0x00000008 1001 #define SEND_INIT_STATS_CLEAR 0x00000004 1002 #define SEND_INIT_STATS_FASTER 0x00000002 1003 #define SEND_INIT_STATS_ENABLE 0x00000001 1004 1005 #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c 1006 1007 /* 1008 * Send Buffer Descriptor Selector Control Registers 1009 */ 1010 #define SEND_BD_SELECTOR_STATUS_REG 0x1404 1011 #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408 1012 #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n)) 1013 1014 /* 1015 * Receive List Placement Registers 1016 */ 1017 #define RCV_LP_CONFIG_REG 0x2010 1018 #define RCV_LP_CONFIG_DEFAULT 0x00000009 1019 #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1) 1020 1021 #define RCV_LP_STATS_CONTROL_REG 0x2014 1022 #define RCV_LP_STATS_ZERO 0x00000010 1023 #define RCV_LP_STATS_FLUSH 0x00000008 1024 #define RCV_LP_STATS_CLEAR 0x00000004 1025 #define RCV_LP_STATS_FASTER 0x00000002 1026 #define RCV_LP_STATS_ENABLE 0x00000001 1027 1028 #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018 1029 #define RCV_LP_STATS_DISABLE_MACTQ 0x040000 1030 1031 /* 1032 * Receive Data & BD Initiator Registers 1033 */ 1034 #define RCV_INITIATOR_STATUS_REG 0x2404 1035 1036 /* 1037 * Receive Buffer Descriptor Ring Control Block Registers 1038 * NB: sixteen bytes (128 bits) each 1039 */ 1040 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440 1041 #define STD_RCV_BD_RING_RCB_REG 0x2450 1042 #define MINI_RCV_BD_RING_RCB_REG 0x2460 1043 1044 /* 1045 * Receive Buffer Descriptor Ring Replenish Threshold Registers 1046 */ 1047 #define MINI_RCV_BD_REPLENISH_REG 0x2c14 1048 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */ 1049 #define STD_RCV_BD_REPLENISH_REG 0x2c18 1050 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */ 1051 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c 1052 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */ 1053 1054 /* 1055 * Host Coalescing Engine Control Registers 1056 */ 1057 #define RCV_COALESCE_TICKS_REG 0x3c08 1058 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 1059 #define SEND_COALESCE_TICKS_REG 0x3c0c 1060 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 1061 #define RCV_COALESCE_MAX_BD_REG 0x3c10 1062 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1063 #define SEND_COALESCE_MAX_BD_REG 0x3c14 1064 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1065 #define RCV_COALESCE_INT_TICKS_REG 0x3c18 1066 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1067 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c 1068 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1069 #define RCV_COALESCE_INT_BD_REG 0x3c20 1070 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1071 #define SEND_COALESCE_INT_BD_REG 0x3c24 1072 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1073 #define STATISTICS_TICKS_REG 0x3c28 1074 #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */ 1075 #define STATISTICS_HOST_ADDR_REG 0x3c30 1076 #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38 1077 #define STATISTICS_BASE_ADDR_REG 0x3c40 1078 #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44 1079 #define FLOW_ATTN_REG 0x3c48 1080 1081 #define NIC_JUMBO_RECV_INDEX_REG 0x3c50 1082 #define NIC_STD_RECV_INDEX_REG 0x3c54 1083 #define NIC_MINI_RECV_INDEX_REG 0x3c58 1084 #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n)) 1085 #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n)) 1086 1087 /* 1088 * Mbuf Pool Initialisation & Watermark Registers 1089 * 1090 * There are some conflicts in the PRM; compare the recommendations 1091 * on pp. 115, 236, and 339. The values here were recommended by 1092 * dkim@broadcom.com (and the PRM should be corrected soon ;-) 1093 */ 1094 #define BUFFER_MANAGER_STATUS_REG 0x4404 1095 #define MBUF_POOL_BASE_REG 0x4408 1096 #define MBUF_POOL_BASE_DEFAULT 0x00008000 1097 #define MBUF_POOL_BASE_5721 0x00010000 1098 #define MBUF_POOL_BASE_5704 0x00010000 1099 #define MBUF_POOL_BASE_5705 0x00010000 1100 #define MBUF_POOL_LENGTH_REG 0x440c 1101 #define MBUF_POOL_LENGTH_DEFAULT 0x00018000 1102 #define MBUF_POOL_LENGTH_5704 0x00010000 1103 #define MBUF_POOL_LENGTH_5705 0x00008000 1104 #define MBUF_POOL_LENGTH_5721 0x00008000 1105 #define RDMA_MBUF_LOWAT_REG 0x4410 1106 #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050 1107 #define RDMA_MBUF_LOWAT_5705 0x00000000 1108 #define RDMA_MBUF_LOWAT_5906 0x00000000 1109 #define RDMA_MBUF_LOWAT_JUMBO 0x00000130 1110 #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000 1111 #define MAC_RX_MBUF_LOWAT_REG 0x4414 1112 #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020 1113 #define MAC_RX_MBUF_LOWAT_5705 0x00000010 1114 #define MAC_RX_MBUF_LOWAT_5906 0x00000004 1115 #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098 1116 #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b 1117 #define MBUF_HIWAT_REG 0x4418 1118 #define MBUF_HIWAT_DEFAULT 0x00000060 1119 #define MBUF_HIWAT_5705 0x00000060 1120 #define MBUF_HIWAT_5906 0x00000010 1121 #define MBUF_HIWAT_JUMBO 0x0000017c 1122 #define MBUF_HIWAT_5714_JUMBO 0x00000096 1123 1124 /* 1125 * DMA Descriptor Pool Initialisation & Watermark Registers 1126 */ 1127 #define DMAD_POOL_BASE_REG 0x442c 1128 #define DMAD_POOL_BASE_DEFAULT 0x00002000 1129 #define DMAD_POOL_LENGTH_REG 0x4430 1130 #define DMAD_POOL_LENGTH_DEFAULT 0x00002000 1131 #define DMAD_POOL_LOWAT_REG 0x4434 1132 #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */ 1133 #define DMAD_POOL_HIWAT_REG 0x4438 1134 #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */ 1135 1136 /* 1137 * More threshold/watermark registers ... 1138 */ 1139 #define RECV_FLOW_THRESHOLD_REG 0x4458 1140 #define LOWAT_MAX_RECV_FRAMES_REG 0x0504 1141 #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002 1142 1143 /* 1144 * Read/Write DMA Status Registers 1145 */ 1146 #define READ_DMA_STATUS_REG 0x4804 1147 #define WRITE_DMA_STATUS_REG 0x4c04 1148 1149 /* 1150 * RX/TX RISC Registers 1151 */ 1152 #define RX_RISC_MODE_REG 0x5000 1153 #define RX_RISC_STATE_REG 0x5004 1154 #define RX_RISC_PC_REG 0x501c 1155 #define TX_RISC_MODE_REG 0x5400 1156 #define TX_RISC_STATE_REG 0x5404 1157 #define TX_RISC_PC_REG 0x541c 1158 1159 /* 1160 * V? RISC Registerss 1161 */ 1162 #define VCPU_STATUS_REG 0x5100 1163 #define VCPU_INIT_DONE 0x04000000 1164 #define VCPU_DRV_RESET 0x08000000 1165 1166 #define VCPU_EXT_CTL 0x6890 1167 #define VCPU_EXT_CTL_HALF 0x00400000 1168 1169 #define FTQ_RESET_REG 0x5c00 1170 1171 #define MSI_MODE_REG 0x6000 1172 #define MSI_PRI_HIGHEST 0xc0000000 1173 #define MSI_MSI_ENABLE 0x00000002 1174 #define MSI_ERROR_ATTENTION 0x0000001c 1175 1176 #define MSI_STATUS_REG 0x6004 1177 1178 #define MODE_CONTROL_REG 0x6800 1179 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000 1180 #define MODE_4X_NIC_SEND_RINGS 0x20000000 1181 #define MODE_INT_ON_FLOW_ATTN 0x10000000 1182 #define MODE_INT_ON_DMA_ATTN 0x08000000 1183 #define MODE_INT_ON_MAC_ATTN 0x04000000 1184 #define MODE_INT_ON_RXRISC_ATTN 0x02000000 1185 #define MODE_INT_ON_TXRISC_ATTN 0x01000000 1186 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000 1187 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000 1188 #define MODE_HOST_SEND_BDS 0x00020000 1189 #define MODE_HOST_STACK_UP 0x00010000 1190 #define MODE_FORCE_32_BIT_PCI 0x00008000 1191 #define MODE_NO_INT_ON_RECV 0x00004000 1192 #define MODE_NO_INT_ON_SEND 0x00002000 1193 #define MODE_ALLOW_BAD_FRAMES 0x00000800 1194 #define MODE_NO_CRC 0x00000400 1195 #define MODE_NO_FRAME_CRACKING 0x00000200 1196 #define MODE_WORD_SWAP_FRAME 0x00000020 1197 #define MODE_BYTE_SWAP_FRAME 0x00000010 1198 #define MODE_WORD_SWAP_NONFRAME 0x00000004 1199 #define MODE_BYTE_SWAP_NONFRAME 0x00000002 1200 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001 1201 1202 /* 1203 * Miscellaneous Configuration Register 1204 * 1205 * This contains various bits relating to power control (which differ 1206 * among different members of the chip family), but the important bits 1207 * for our purposes are the RESET bit and the Timer Prescaler field. 1208 * 1209 * The RESET bit in this register serves to reset the whole chip, even 1210 * including the PCI interface(!) Once it's set, the chip will not 1211 * respond to ANY accesses -- not even CONFIG space -- until the reset 1212 * completes internally. According to the PRM, this should take less 1213 * than 100us. Any access during this period will get a bus error. 1214 * 1215 * The Timer Prescaler field must be programmed so that the timer period 1216 * is as near as possible to 1us. The value in this field should be 1217 * the Core Clock frequency in MHz minus 1. From my reading of the PRM, 1218 * the Core Clock should always be 66MHz (independently of the bus speed, 1219 * at least for PCI rather than PCI-X), so this register must be set to 1220 * the value 0x82 ((66-1) << 1). 1221 */ 1222 #define CORE_CLOCK_MHZ 66 1223 #define MISC_CONFIG_REG 0x6804 1224 #define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000 1225 #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000 1226 #define MISC_CONFIG_POWERDOWN 0x00100000 1227 #define MISC_CONFIG_POWER_STATE 0x00060000 1228 #define MISC_CONFIG_PRESCALE_MASK 0x000000fe 1229 #define MISC_CONFIG_RESET_BIT 0x00000001 1230 #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1) 1231 #define MISC_CONFIG_EPHY_IDDQ 0x00200000 1232 1233 /* 1234 * Miscellaneous Local Control Register (MLCR) 1235 */ 1236 #define MISC_LOCAL_CONTROL_REG 0x6808 1237 #define MLCR_PCI_CTRL_SELECT 0x10000000 1238 #define MLCR_LEGACY_PCI_MODE 0x08000000 1239 #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000 1240 #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000 1241 #define MLCR_SSRAM_TYPE 0x00400000 1242 #define MLCR_BANK_SELECT 0x00200000 1243 #define MLCR_SRAM_SIZE_MASK 0x001c0000 1244 #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000 1245 1246 #define MLCR_MISC_PINS_OUTPUT_2 0x00010000 1247 #define MLCR_MISC_PINS_OUTPUT_1 0x00008000 1248 #define MLCR_MISC_PINS_OUTPUT_0 0x00004000 1249 #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000 1250 #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000 1251 #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800 1252 #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */ 1253 #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */ 1254 #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */ 1255 1256 #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */ 1257 #define MLCR_SET_INT 0x00000004 /* W/O */ 1258 #define MLCR_CLR_INT 0x00000002 /* W/O */ 1259 #define MLCR_INTA_STATE 0x00000001 /* R/O */ 1260 1261 /* 1262 * This value defines all GPIO bits as INPUTS, but sets their default 1263 * values as outputs to HIGH, on the assumption that external circuits 1264 * (if any) will probably be active-LOW with passive pullups. 1265 * 1266 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in 1267 * just this fashion. It has to be set as an OUTPUT and driven LOW to 1268 * enable writing. Otherwise, the SEEPROM is protected. 1269 */ 1270 #define MLCR_DEFAULT 0x0101c000 1271 #define MLCR_DEFAULT_5714 0x1901c000 1272 1273 /* 1274 * Serial EEPROM Data/Address Registers (auto-access mode) 1275 */ 1276 #define SERIAL_EEPROM_DATA_REG 0x683c 1277 #define SERIAL_EEPROM_ADDRESS_REG 0x6838 1278 #define SEEPROM_ACCESS_READ 0x80000000 1279 #define SEEPROM_ACCESS_WRITE 0x00000000 1280 #define SEEPROM_ACCESS_COMPLETE 0x40000000 1281 #define SEEPROM_ACCESS_RESET 0x20000000 1282 #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000 1283 #define SEEPROM_ACCESS_START 0x02000000 1284 #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000 1285 #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc 1286 1287 #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */ 1288 #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */ 1289 #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */ 1290 1291 #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */ 1292 #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */ 1293 1294 /* 1295 * "Linearised" address mask, treating multiple devices as consecutive 1296 */ 1297 #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */ 1298 1299 /* 1300 * Non-Volatile Memory Interface Registers 1301 * Note: on chips that support the flash interface (5702+), flash is the 1302 * default and the legacy seeprom interface must be explicitly enabled 1303 * if required. On older chips (5700/01), SEEPROM is the default (and 1304 * only) non-volatile memory available, and these registers don't exist! 1305 */ 1306 #define NVM_FLASH_CMD_REG 0x7000 1307 #define NVM_FLASH_CMD_LAST 0x00000100 1308 #define NVM_FLASH_CMD_FIRST 0x00000080 1309 #define NVM_FLASH_CMD_RD 0x00000000 1310 #define NVM_FLASH_CMD_WR 0x00000020 1311 #define NVM_FLASH_CMD_DOIT 0x00000010 1312 #define NVM_FLASH_CMD_DONE 0x00000008 1313 1314 #define NVM_FLASH_WRITE_REG 0x7008 1315 #define NVM_FLASH_READ_REG 0x7010 1316 1317 #define NVM_FLASH_ADDR_REG 0x700c 1318 #define NVM_FLASH_ADDR_MASK 0x00fffffc 1319 1320 #define NVM_CONFIG1_REG 0x7014 1321 #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000 1322 #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800 1323 #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780 1324 #define NVM_CFG1_BUFFERED_MODE 0x00000002 1325 #define NVM_CFG1_FLASH_MODE 0x00000001 1326 1327 #define NVM_SW_ARBITRATION_REG 0x7020 1328 #define NVM_READ_REQ3 0X00008000 1329 #define NVM_READ_REQ2 0X00004000 1330 #define NVM_READ_REQ1 0X00002000 1331 #define NVM_READ_REQ0 0X00001000 1332 #define NVM_WON_REQ3 0X00000800 1333 #define NVM_WON_REQ2 0X00000400 1334 #define NVM_WON_REQ1 0X00000200 1335 #define NVM_WON_REQ0 0X00000100 1336 #define NVM_RESET_REQ3 0X00000080 1337 #define NVM_RESET_REQ2 0X00000040 1338 #define NVM_RESET_REQ1 0X00000020 1339 #define NVM_RESET_REQ0 0X00000010 1340 #define NVM_SET_REQ3 0X00000008 1341 #define NVM_SET_REQ2 0X00000004 1342 #define NVM_SET_REQ1 0X00000002 1343 #define NVM_SET_REQ0 0X00000001 1344 1345 /* 1346 * NVM access register 1347 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714 1348 * and BCM5715 only. 1349 */ 1350 #define NVM_ACCESS_REG 0X7024 1351 #define NVM_WRITE_ENABLE 0X00000002 1352 #define NVM_ACCESS_ENABLE 0X00000001 1353 1354 /* 1355 * TLP Control Register 1356 * Applicable to BCM5721 and BCM5751 only 1357 */ 1358 #define TLP_CONTROL_REG 0x7c00 1359 #define TLP_DATA_FIFO_PROTECT 0x02000000 1360 1361 /* 1362 * PHY Test Control Register 1363 * Applicable to BCM5721 and BCM5751 only 1364 */ 1365 #define PHY_TEST_CTRL_REG 0x7e2c 1366 #define PHY_PCIE_SCRAM_MODE 0x20 1367 #define PHY_PCIE_LTASS_MODE 0x40 1368 1369 /* 1370 * The internal firmware expects a certain layout of the non-volatile 1371 * memory (if fitted), and will check for it during startup, and use the 1372 * contents to initialise various internal parameters if it looks good. 1373 * 1374 * The offsets and field definitions below refer to where to find some 1375 * important values, and how to interpret them ... 1376 */ 1377 #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */ 1378 #define NVMEM_DATA_MAC_ADDRESS_5906 0x0010 /* 8 bytes */ 1379 1380 /* 1381 * Vendor-specific MII registers 1382 */ 1383 #define MII_EXT_CONTROL MII_VENDOR(0) 1384 #define MII_EXT_STATUS MII_VENDOR(1) 1385 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 1386 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 1387 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 1388 #define MII_AUX_CONTROL MII_VENDOR(8) 1389 #define MII_AUX_STATUS MII_VENDOR(9) 1390 #define MII_INTR_STATUS MII_VENDOR(10) 1391 #define MII_INTR_MASK MII_VENDOR(11) 1392 #define MII_HCD_STATUS MII_VENDOR(13) 1393 1394 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 1395 1396 /* 1397 * Bits in the MII_EXT_CONTROL register 1398 */ 1399 #define MII_EXT_CTRL_INTERFACE_TBI 0x8000 1400 #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000 1401 #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000 1402 #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000 1403 #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800 1404 #define MII_EXT_CTRL_BYPASS_4B5B 0x0400 1405 #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200 1406 #define MII_EXT_CTRL_BYPASS_MLT3 0x0100 1407 #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080 1408 #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040 1409 #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020 1410 #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010 1411 #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008 1412 #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004 1413 #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002 1414 #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001 1415 1416 /* 1417 * Bits in the MII_EXT_STATUS register 1418 */ 1419 #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000 1420 #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000 1421 #define MII_EXT_STAT_MDIX_STATE 0x2000 1422 #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000 1423 #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800 1424 #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400 1425 #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200 1426 #define MII_EXT_STAT_LINK_STATUS 0x0100 1427 #define MII_EXT_STAT_CRC_ERROR 0x0080 1428 #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040 1429 #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020 1430 #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010 1431 #define MII_EXT_STAT_RECEIVE_ERROR 0x0008 1432 #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004 1433 #define MII_EXT_STAT_LOCK_ERROR 0x0002 1434 #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001 1435 1436 /* 1437 * The AUX CONTROL register is seriously weird! 1438 * 1439 * It hides (up to) eight 'shadow' registers. When writing, which one 1440 * of them is written is determined by the low-order bits of the data 1441 * written(!), but when reading, which one is read is determined by the 1442 * value previously written to (part of) one of the shadow registers!!! 1443 */ 1444 1445 /* 1446 * Shadow register numbers 1447 */ 1448 #define MII_AUX_CTRL_NORMAL 0 1449 #define MII_AUX_CTRL_10BASE_T 1 1450 #define MII_AUX_CTRL_POWER 2 1451 #define MII_AUX_CTRL_TEST_1 4 1452 #define MII_AUX_CTRL_MISC 7 1453 1454 /* 1455 * Selected bits in some of the shadow registers ... 1456 */ 1457 #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000 1458 #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000 1459 #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000 1460 #define MII_AUX_CTRL_NORM_TX_MODE 0x0400 1461 #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008 1462 1463 #define MII_AUX_CTRL_TEST_TX_HALF 0x0008 1464 1465 #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000 1466 #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010 1467 1468 /* 1469 * Write this value to the AUX control register 1470 * to select which shadow register will be read 1471 */ 1472 #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC) 1473 1474 /* 1475 * Bits in the MII_AUX_STATUS register 1476 */ 1477 #define MII_AUX_STATUS_MODE_MASK 0x0700 1478 #define MII_AUX_STATUS_MODE_1000_F 0x0700 1479 #define MII_AUX_STATUS_MODE_1000_H 0x0600 1480 #define MII_AUX_STATUS_MODE_100_F 0x0500 1481 #define MII_AUX_STATUS_MODE_100_4 0x0400 1482 #define MII_AUX_STATUS_MODE_100_H 0x0300 1483 #define MII_AUX_STATUS_MODE_10_F 0x0200 1484 #define MII_AUX_STATUS_MODE_10_H 0x0100 1485 #define MII_AUX_STATUS_MODE_NONE 0x0000 1486 #define MII_AUX_STATUS_MODE_SHIFT 8 1487 1488 #define MII_AUX_STATUS_PAR_FAULT 0x0080 1489 #define MII_AUX_STATUS_REM_FAULT 0x0040 1490 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 1491 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 1492 1493 #define MII_AUX_STATUS_LINKUP 0x0004 1494 #define MII_AUX_STATUS_RX_PAUSE 0x0002 1495 #define MII_AUX_STATUS_TX_PAUSE 0x0001 1496 1497 #define MII_AUX_STATUS_SPEED_IND_5906 0x0008 1498 #define MII_AUX_STATUS_NEG_ENABLED_5906 0x0002 1499 #define MII_AUX_STATUS_DUPLEX_IND_5906 0x0001 1500 1501 /* 1502 * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers 1503 */ 1504 #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020 1505 #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010 1506 #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008 1507 #define MII_INTR_LINK_SPEED_CHANGE 0x0004 1508 #define MII_INTR_LINK_STATUS_CHANGE 0x0002 1509 1510 1511 /* 1512 * Third section: 1513 * Hardware-defined data structures 1514 * 1515 * Note that the chip is naturally BIG-endian, so, for a big-endian 1516 * host, the structures defined below match those described in the PRM. 1517 * For little-endian hosts, some structures have to be swapped around. 1518 */ 1519 1520 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 1521 #error Host endianness not defined 1522 #endif 1523 1524 /* 1525 * Architectural constants: absolute maximum numbers of each type of ring 1526 */ 1527 #ifdef BGE_EXT_MEM 1528 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */ 1529 #else 1530 #define BGE_SEND_RINGS_MAX 4 1531 #endif 1532 #define BGE_SEND_RINGS_MAX_5705 1 1533 #define BGE_RECV_RINGS_MAX 16 1534 #define BGE_RECV_RINGS_MAX_5705 1 1535 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */ 1536 /* only with ext mem) */ 1537 1538 #define BGE_SEND_SLOTS_MAX 512 1539 #define BGE_STD_SLOTS_MAX 512 1540 #define BGE_JUMBO_SLOTS_MAX 256 1541 #define BGE_MINI_SLOTS_MAX 1024 1542 #define BGE_RECV_SLOTS_MAX 2048 1543 #define BGE_RECV_SLOTS_5705 512 1544 #define BGE_RECV_SLOTS_5782 512 1545 #define BGE_RECV_SLOTS_5721 512 1546 1547 /* 1548 * Hardware-defined Ring Control Block 1549 */ 1550 typedef struct { 1551 uint64_t host_ring_addr; 1552 #ifdef _BIG_ENDIAN 1553 uint16_t max_len; 1554 uint16_t flags; 1555 uint32_t nic_ring_addr; 1556 #else 1557 uint32_t nic_ring_addr; 1558 uint16_t flags; 1559 uint16_t max_len; 1560 #endif /* _BIG_ENDIAN */ 1561 } bge_rcb_t; 1562 1563 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001 1564 #define RCB_FLAG_RING_DISABLED 0x0002 1565 1566 /* 1567 * Hardware-defined Send Buffer Descriptor 1568 */ 1569 typedef struct { 1570 uint64_t host_buf_addr; 1571 #ifdef _BIG_ENDIAN 1572 uint16_t len; 1573 uint16_t flags; 1574 uint16_t reserved; 1575 uint16_t vlan_tci; 1576 #else 1577 uint16_t vlan_tci; 1578 uint16_t reserved; 1579 uint16_t flags; 1580 uint16_t len; 1581 #endif /* _BIG_ENDIAN */ 1582 } bge_sbd_t; 1583 1584 #define SBD_FLAG_TCP_UDP_CKSUM 0x0001 1585 #define SBD_FLAG_IP_CKSUM 0x0002 1586 #define SBD_FLAG_PACKET_END 0x0004 1587 #define SBD_FLAG_IP_FRAG 0x0008 1588 #define SBD_FLAG_IP_FRAG_END 0x0010 1589 1590 #define SBD_FLAG_VLAN_TAG 0x0040 1591 #define SBD_FLAG_COAL_NOW 0x0080 1592 #define SBD_FLAG_CPU_PRE_DMA 0x0100 1593 #define SBD_FLAG_CPU_POST_DMA 0x0200 1594 1595 #define SBD_FLAG_INSERT_SRC_ADDR 0x1000 1596 #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000 1597 #define SBD_FLAG_DONT_GEN_CRC 0x8000 1598 1599 /* 1600 * Hardware-defined Receive Buffer Descriptor 1601 */ 1602 typedef struct { 1603 uint64_t host_buf_addr; 1604 #ifdef _BIG_ENDIAN 1605 uint16_t index; 1606 uint16_t len; 1607 uint16_t type; 1608 uint16_t flags; 1609 uint16_t ip_cksum; 1610 uint16_t tcp_udp_cksum; 1611 uint16_t error_flag; 1612 uint16_t vlan_tci; 1613 uint32_t reserved; 1614 uint32_t opaque; 1615 #else 1616 uint16_t flags; 1617 uint16_t type; 1618 uint16_t len; 1619 uint16_t index; 1620 uint16_t vlan_tci; 1621 uint16_t error_flag; 1622 uint16_t tcp_udp_cksum; 1623 uint16_t ip_cksum; 1624 uint32_t opaque; 1625 uint32_t reserved; 1626 #endif /* _BIG_ENDIAN */ 1627 } bge_rbd_t; 1628 1629 #define RBD_FLAG_STD_RING 0x0000 1630 #define RBD_FLAG_PACKET_END 0x0004 1631 1632 #define RBD_FLAG_JUMBO_RING 0x0020 1633 #define RBD_FLAG_VLAN_TAG 0x0040 1634 1635 #define RBD_FLAG_FRAME_HAS_ERROR 0x0400 1636 #define RBD_FLAG_MINI_RING 0x0800 1637 #define RBD_FLAG_IP_CHECKSUM 0x1000 1638 #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000 1639 #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000 1640 1641 #define RBD_FLAG_DEFAULT 0x0000 1642 1643 #define RBD_ERROR_BAD_CRC 0x00010000 1644 #define RBD_ERROR_COLL_DETECT 0x00020000 1645 #define RBD_ERROR_LINK_LOST 0x00040000 1646 #define RBD_ERROR_PHY_DECODE_ERR 0x00080000 1647 #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000 1648 #define RBD_ERROR_MAC_ABORT 0x00200000 1649 #define RBD_ERROR_LEN_LESS_64 0x00400000 1650 #define RBD_ERROR_TRUNC_NO_RES 0x00800000 1651 #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000 1652 1653 /* 1654 * Hardware-defined Status Block,Size of status block 1655 * is actually 0x50 bytes.Use 0x80 bytes for cache line 1656 * alignment.For BCM5705/5788/5721/5751/5752/5714 1657 * and 5715,there is only 1 recv and send ring index,but 1658 * driver defined 16 indexs here,please pay attention only 1659 * one ring is enabled in these chipsets. 1660 */ 1661 typedef struct { 1662 uint64_t flags_n_tag; 1663 uint16_t buff_cons_index[4]; 1664 struct { 1665 #ifdef _BIG_ENDIAN 1666 uint16_t send_cons_index; 1667 uint16_t recv_prod_index; 1668 #else 1669 uint16_t recv_prod_index; 1670 uint16_t send_cons_index; 1671 #endif /* _BIG_ENDIAN */ 1672 } index[16]; 1673 } bge_status_t; 1674 1675 /* 1676 * Hardware-defined Receive BD Rule 1677 */ 1678 typedef struct { 1679 uint32_t control; 1680 uint32_t mask_value; 1681 } bge_recv_rule_t; 1682 1683 /* 1684 * This describes which sub-rule slots are used by a particular rule. 1685 */ 1686 typedef struct { 1687 int start; 1688 int count; 1689 } bge_rule_info_t; 1690 1691 /* 1692 * Indexes into the <buff_cons_index> array 1693 */ 1694 #ifdef _BIG_ENDIAN 1695 #define STATUS_STD_BUFF_CONS_INDEX 0 1696 #define STATUS_JUMBO_BUFF_CONS_INDEX 1 1697 #define STATUS_MINI_BUFF_CONS_INDEX 3 1698 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index) 1699 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index) 1700 #else 1701 #define STATUS_STD_BUFF_CONS_INDEX 3 1702 #define STATUS_JUMBO_BUFF_CONS_INDEX 2 1703 #define STATUS_MINI_BUFF_CONS_INDEX 0 1704 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index) 1705 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index) 1706 #endif /* _BIG_ENDIAN */ 1707 1708 /* 1709 * Bits in the <flags_n_tag> word 1710 */ 1711 #define STATUS_FLAG_UPDATED 0x0000000100000000ull 1712 #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull 1713 #define STATUS_FLAG_ERROR 0x0000000400000000ull 1714 #define STATUS_TAG_MASK 0x00000000000000FFull 1715 1716 /* 1717 * The tag from the status block is fed back to Interrupt Mailbox 0 1718 * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This 1719 * lets the chip know what updates have been processed, so it can 1720 * reassert its interrupt if more updates have occurred since. 1721 * 1722 * These macros extract the tag from the <flags_n_tag> word, shift 1723 * it to the proper position in the Mailbox register, and provide 1724 * the complete values to write to INTERRUPT_MBOX_0_REG to disable 1725 * or enable interrupts 1726 */ 1727 #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK) 1728 #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24) 1729 #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1) 1730 #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0) 1731 1732 /* 1733 * Hardware-defined Statistics Block Offsets 1734 * 1735 * These are given in the manual as addresses in NIC memory, starting 1736 * from the NIC statistics area base address of 0x300; but here we 1737 * convert them into indexes into an array of (uint64_t)s, so we can 1738 * use them directly for accessing the copy of the statistics block 1739 * that the chip DMAs into main memory ... 1740 */ 1741 1742 #define KS_BASE 0x300 1743 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t)) 1744 1745 typedef enum { 1746 KS_ifHCInOctets = KS_ADDR(0x400), 1747 KS_etherStatsFragments = KS_ADDR(0x410), 1748 KS_ifHCInUcastPkts, 1749 KS_ifHCInMulticastPkts, 1750 KS_ifHCInBroadcastPkts, 1751 KS_dot3StatsFCSErrors, 1752 KS_dot3StatsAlignmentErrors, 1753 KS_xonPauseFramesReceived, 1754 KS_xoffPauseFramesReceived, 1755 KS_macControlFramesReceived, 1756 KS_xoffStateEntered, 1757 KS_dot3StatsFrameTooLongs, 1758 KS_etherStatsJabbers, 1759 KS_etherStatsUndersizePkts, 1760 KS_inRangeLengthError, 1761 KS_outRangeLengthError, 1762 KS_etherStatsPkts64Octets, 1763 KS_etherStatsPkts65to127Octets, 1764 KS_etherStatsPkts128to255Octets, 1765 KS_etherStatsPkts256to511Octets, 1766 KS_etherStatsPkts512to1023Octets, 1767 KS_etherStatsPkts1024to1518Octets, 1768 KS_etherStatsPkts1519to2047Octets, 1769 KS_etherStatsPkts2048to4095Octets, 1770 KS_etherStatsPkts4096to8191Octets, 1771 KS_etherStatsPkts8192to9022Octets, 1772 1773 KS_ifHCOutOctets = KS_ADDR(0x600), 1774 KS_etherStatsCollisions = KS_ADDR(0x610), 1775 KS_outXonSent, 1776 KS_outXoffSent, 1777 KS_flowControlDone, 1778 KS_dot3StatsInternalMacTransmitErrors, 1779 KS_dot3StatsSingleCollisionFrames, 1780 KS_dot3StatsMultipleCollisionFrames, 1781 KS_dot3StatsDeferredTransmissions, 1782 KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658), 1783 KS_dot3StatsLateCollisions, 1784 KS_dot3Collided2Times, 1785 KS_dot3Collided3Times, 1786 KS_dot3Collided4Times, 1787 KS_dot3Collided5Times, 1788 KS_dot3Collided6Times, 1789 KS_dot3Collided7Times, 1790 KS_dot3Collided8Times, 1791 KS_dot3Collided9Times, 1792 KS_dot3Collided10Times, 1793 KS_dot3Collided11Times, 1794 KS_dot3Collided12Times, 1795 KS_dot3Collided13Times, 1796 KS_dot3Collided14Times, 1797 KS_dot3Collided15Times, 1798 KS_ifHCOutUcastPkts, 1799 KS_ifHCOutMulticastPkts, 1800 KS_ifHCOutBroadcastPkts, 1801 KS_dot3StatsCarrierSenseErrors, 1802 KS_ifOutDiscards, 1803 KS_ifOutErrors, 1804 1805 KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */ 1806 KS_COSIfHCInPkts_2, 1807 KS_COSIfHCInPkts_3, 1808 KS_COSIfHCInPkts_4, 1809 KS_COSIfHCInPkts_5, 1810 KS_COSIfHCInPkts_6, 1811 KS_COSIfHCInPkts_7, 1812 KS_COSIfHCInPkts_8, 1813 KS_COSIfHCInPkts_9, 1814 KS_COSIfHCInPkts_10, 1815 KS_COSIfHCInPkts_11, 1816 KS_COSIfHCInPkts_12, 1817 KS_COSIfHCInPkts_13, 1818 KS_COSIfHCInPkts_14, 1819 KS_COSIfHCInPkts_15, 1820 KS_COSIfHCInPkts_16, 1821 KS_COSFramesDroppedDueToFilters, 1822 KS_nicDmaWriteQueueFull, 1823 KS_nicDmaWriteHighPriQueueFull, 1824 KS_nicNoMoreRxBDs, 1825 KS_ifInDiscards, 1826 KS_ifInErrors, 1827 KS_nicRecvThresholdHit, 1828 1829 KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */ 1830 KS_COSIfHCOutPkts_2, 1831 KS_COSIfHCOutPkts_3, 1832 KS_COSIfHCOutPkts_4, 1833 KS_COSIfHCOutPkts_5, 1834 KS_COSIfHCOutPkts_6, 1835 KS_COSIfHCOutPkts_7, 1836 KS_COSIfHCOutPkts_8, 1837 KS_COSIfHCOutPkts_9, 1838 KS_COSIfHCOutPkts_10, 1839 KS_COSIfHCOutPkts_11, 1840 KS_COSIfHCOutPkts_12, 1841 KS_COSIfHCOutPkts_13, 1842 KS_COSIfHCOutPkts_14, 1843 KS_COSIfHCOutPkts_15, 1844 KS_COSIfHCOutPkts_16, 1845 KS_nicDmaReadQueueFull, 1846 KS_nicDmaReadHighPriQueueFull, 1847 KS_nicSendDataCompQueueFull, 1848 KS_nicRingSetSendProdIndex, 1849 KS_nicRingStatusUpdate, 1850 KS_nicInterrupts, 1851 KS_nicAvoidedInterrupts, 1852 KS_nicSendThresholdHit, 1853 1854 KS_STATS_SIZE = KS_ADDR(0xb00) 1855 } bge_stats_offset_t; 1856 1857 /* 1858 * Hardware-defined Statistics Block 1859 * 1860 * Another view of the statistic block, as a array and a structure ... 1861 */ 1862 1863 typedef union { 1864 uint64_t a[KS_STATS_SIZE]; 1865 struct { 1866 uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)]; 1867 1868 uint64_t ifHCInOctets; /* 0x0400 */ 1869 uint64_t spare2[1]; 1870 uint64_t etherStatsFragments; 1871 uint64_t ifHCInUcastPkts; 1872 uint64_t ifHCInMulticastPkts; 1873 uint64_t ifHCInBroadcastPkts; 1874 uint64_t dot3StatsFCSErrors; 1875 uint64_t dot3StatsAlignmentErrors; 1876 uint64_t xonPauseFramesReceived; 1877 uint64_t xoffPauseFramesReceived; 1878 uint64_t macControlFramesReceived; 1879 uint64_t xoffStateEntered; 1880 uint64_t dot3StatsFrameTooLongs; 1881 uint64_t etherStatsJabbers; 1882 uint64_t etherStatsUndersizePkts; 1883 uint64_t inRangeLengthError; 1884 uint64_t outRangeLengthError; 1885 uint64_t etherStatsPkts64Octets; 1886 uint64_t etherStatsPkts65to127Octets; 1887 uint64_t etherStatsPkts128to255Octets; 1888 uint64_t etherStatsPkts256to511Octets; 1889 uint64_t etherStatsPkts512to1023Octets; 1890 uint64_t etherStatsPkts1024to1518Octets; 1891 uint64_t etherStatsPkts1519to2047Octets; 1892 uint64_t etherStatsPkts2048to4095Octets; 1893 uint64_t etherStatsPkts4096to8191Octets; 1894 uint64_t etherStatsPkts8192to9022Octets; 1895 uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)]; 1896 1897 uint64_t ifHCOutOctets; /* 0x0600 */ 1898 uint64_t spare4[1]; 1899 uint64_t etherStatsCollisions; 1900 uint64_t outXonSent; 1901 uint64_t outXoffSent; 1902 uint64_t flowControlDone; 1903 uint64_t dot3StatsInternalMacTransmitErrors; 1904 uint64_t dot3StatsSingleCollisionFrames; 1905 uint64_t dot3StatsMultipleCollisionFrames; 1906 uint64_t dot3StatsDeferredTransmissions; 1907 uint64_t spare5[1]; 1908 uint64_t dot3StatsExcessiveCollisions; 1909 uint64_t dot3StatsLateCollisions; 1910 uint64_t dot3Collided2Times; 1911 uint64_t dot3Collided3Times; 1912 uint64_t dot3Collided4Times; 1913 uint64_t dot3Collided5Times; 1914 uint64_t dot3Collided6Times; 1915 uint64_t dot3Collided7Times; 1916 uint64_t dot3Collided8Times; 1917 uint64_t dot3Collided9Times; 1918 uint64_t dot3Collided10Times; 1919 uint64_t dot3Collided11Times; 1920 uint64_t dot3Collided12Times; 1921 uint64_t dot3Collided13Times; 1922 uint64_t dot3Collided14Times; 1923 uint64_t dot3Collided15Times; 1924 uint64_t ifHCOutUcastPkts; 1925 uint64_t ifHCOutMulticastPkts; 1926 uint64_t ifHCOutBroadcastPkts; 1927 uint64_t dot3StatsCarrierSenseErrors; 1928 uint64_t ifOutDiscards; 1929 uint64_t ifOutErrors; 1930 uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)]; 1931 1932 uint64_t COSIfHCInPkts[16]; /* 0x0800 */ 1933 uint64_t COSFramesDroppedDueToFilters; 1934 uint64_t nicDmaWriteQueueFull; 1935 uint64_t nicDmaWriteHighPriQueueFull; 1936 uint64_t nicNoMoreRxBDs; 1937 uint64_t ifInDiscards; 1938 uint64_t ifInErrors; 1939 uint64_t nicRecvThresholdHit; 1940 uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)]; 1941 1942 uint64_t COSIfHCOutPkts[16]; /* 0x0900 */ 1943 uint64_t nicDmaReadQueueFull; 1944 uint64_t nicDmaReadHighPriQueueFull; 1945 uint64_t nicSendDataCompQueueFull; 1946 uint64_t nicRingSetSendProdIndex; 1947 uint64_t nicRingStatusUpdate; 1948 uint64_t nicInterrupts; 1949 uint64_t nicAvoidedInterrupts; 1950 uint64_t nicSendThresholdHit; 1951 uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)]; 1952 } s; 1953 } bge_statistics_t; 1954 1955 #define KS_STAT_REG_SIZE (0x1B) 1956 #define KS_STAT_REG_BASE (0x800) 1957 1958 typedef struct { 1959 uint32_t ifHCOutOctets; 1960 uint32_t etherStatsCollisions; 1961 uint32_t outXonSent; 1962 uint32_t outXoffSent; 1963 uint32_t dot3StatsInternalMacTransmitErrors; 1964 uint32_t dot3StatsSingleCollisionFrames; 1965 uint32_t dot3StatsMultipleCollisionFrames; 1966 uint32_t dot3StatsDeferredTransmissions; 1967 uint32_t dot3StatsExcessiveCollisions; 1968 uint32_t dot3StatsLateCollisions; 1969 uint32_t ifHCOutUcastPkts; 1970 uint32_t ifHCOutMulticastPkts; 1971 uint32_t ifHCOutBroadcastPkts; 1972 uint32_t ifHCInOctets; 1973 uint32_t etherStatsFragments; 1974 uint32_t ifHCInUcastPkts; 1975 uint32_t ifHCInMulticastPkts; 1976 uint32_t ifHCInBroadcastPkts; 1977 uint32_t dot3StatsFCSErrors; 1978 uint32_t dot3StatsAlignmentErrors; 1979 uint32_t xonPauseFramesReceived; 1980 uint32_t xoffPauseFramesReceived; 1981 uint32_t macControlFramesReceived; 1982 uint32_t xoffStateEntered; 1983 uint32_t dot3StatsFrameTooLongs; 1984 uint32_t etherStatsJabbers; 1985 uint32_t etherStatsUndersizePkts; 1986 } bge_statistics_reg_t; 1987 1988 1989 #ifdef BGE_IPMI_ASF 1990 1991 /* 1992 * Device internal memory entries 1993 */ 1994 1995 #define BGE_FIRMWARE_MAILBOX 0x0b50 1996 #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654 1997 #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b 1998 1999 2000 #define BGE_NIC_DATA_SIG_ADDR 0x0b54 2001 #define BGE_NIC_DATA_SIG 0x4b657654 2002 2003 2004 #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58 2005 2006 #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004 2007 #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008 2008 #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004 2009 #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008 2010 #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c 2011 2012 #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000 2013 #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010 2014 #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020 2015 #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030 2016 2017 #define BGE_NIC_CFG_ENABLE_WOL 0x000040 2018 #define BGE_NIC_CFG_ENABLE_ASF 0x000080 2019 #define BGE_NIC_CFG_EEPROM_WP 0x000100 2020 #define BGE_NIC_CFG_POWER_SAVING 0x000200 2021 #define BGE_NIC_CFG_SWAP_PORT 0x000800 2022 #define BGE_NIC_CFG_MINI_PCI 0x001000 2023 #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000 2024 #define BGE_NIC_CFG_5753_12x12 0x100000 2025 2026 2027 #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c 2028 2029 2030 #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74 2031 #define BGE_NIC_PHY_ID1_MASK 0xffff0000 2032 #define BGE_NIC_PHY_ID2_MASK 0x0000ffff 2033 2034 2035 #define BGE_CMD_MAILBOX 0x0b78 2036 #define BGE_CMD_NICDRV_ALIVE 0x00000001 2037 #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002 2038 #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003 2039 #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004 2040 2041 2042 #define BGE_CMD_LENGTH_MAILBOX 0x0b7c 2043 #define BGE_CMD_DATA_MAILBOX 0x0b80 2044 #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00 2045 2046 #define BGE_DRV_STATE_MAILBOX 0x0c04 2047 #define BGE_DRV_STATE_START 0x00000001 2048 #define BGE_DRV_STATE_START_DONE 0x80000001 2049 #define BGE_DRV_STATE_UNLOAD 0x00000002 2050 #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002 2051 #define BGE_DRV_STATE_WOL 0x00000003 2052 #define BGE_DRV_STATE_SUSPEND 0x00000004 2053 2054 2055 #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08 2056 #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001 2057 #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002 2058 2059 2060 #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14 2061 #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18 2062 2063 2064 /* 2065 * RX-RISC event register 2066 */ 2067 #define RX_RISC_EVENT_REG 0x6810 2068 #define RRER_ASF_EVENT 0x4000 2069 2070 #endif /* BGE_IPMI_ASF */ 2071 2072 #ifdef __cplusplus 2073 } 2074 #endif 2075 2076 #endif /* _BGE_HW_H */ 2077