1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "sys/bge_impl2.h" 30 31 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 32 33 /* 34 * Future features ... ? 35 */ 36 #define BGE_CFG_IO8 0 /* 8/16-bit cfg space BIS/BIC */ 37 #define BGE_IND_IO32 0 /* indirect access code */ 38 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 39 #define BGE_FLASH_IO32 1 /* FLASH access code */ 40 41 /* 42 * BGE MSI tunable: 43 * 44 * By default MSI is enabled on all supported platforms but it is disabled 45 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 46 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 47 */ 48 #if defined(__sparc) 49 boolean_t bge_enable_msi = B_TRUE; 50 #else 51 boolean_t bge_enable_msi = B_FALSE; 52 #endif 53 54 /* 55 * Property names 56 */ 57 static char knownids_propname[] = "bge-known-subsystems"; 58 59 /* 60 * Patchable globals: 61 * 62 * bge_autorecover 63 * Enables/disables automatic recovery after fault detection 64 * 65 * bge_mlcr_default 66 * Value to program into the MLCR; controls the chip's GPIO pins 67 * 68 * bge_dma_{rd,wr}prio 69 * Relative priorities of DMA reads & DMA writes respectively. 70 * These may each be patched to any value 0-3. Equal values 71 * will give "fair" (round-robin) arbitration for PCI access. 72 * Unequal values will give one or the other function priority. 73 * 74 * bge_dma_rwctrl 75 * Value to put in the Read/Write DMA control register. See 76 * the Broadcom PRM for things you can fiddle with in this 77 * register ... 78 * 79 * bge_{tx,rx}_{count,ticks}_{norm,intr} 80 * Send/receive interrupt coalescing parameters. Counts are 81 * #s of descriptors, ticks are in microseconds. *norm* values 82 * apply between status updates/interrupts; the *intr* values 83 * refer to the 'during-interrupt' versions - see the PRM. 84 * 85 * NOTE: these values have been determined by measurement. They 86 * differ significantly from the values recommended in the PRM. 87 */ 88 static uint32_t bge_autorecover = 1; 89 static uint32_t bge_mlcr_default = MLCR_DEFAULT; 90 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 91 92 static uint32_t bge_dma_rdprio = 1; 93 static uint32_t bge_dma_wrprio = 0; 94 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 95 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 96 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 97 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 98 99 uint32_t bge_rx_ticks_norm = 128; 100 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 101 uint32_t bge_rx_count_norm = 8; 102 uint32_t bge_tx_count_norm = 128; 103 104 static uint32_t bge_rx_ticks_intr = 128; 105 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 106 static uint32_t bge_rx_count_intr = 2; 107 static uint32_t bge_tx_count_intr = 0; 108 109 /* 110 * Memory pool configuration parameters. 111 * 112 * These are generally specific to each member of the chip family, since 113 * each one may have a different memory size/configuration. 114 * 115 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 116 * the driver from programming the various registers; instead they are left 117 * at their hardware defaults. This is the preferred option for later chips 118 * (5705+), whereas the older chips *required* these registers to be set, 119 * since the h/w default was 0 ;-( 120 */ 121 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 122 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 123 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 124 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 125 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 126 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 127 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 128 static uint32_t bge_mbuf_pool_len_5721 = 0; 129 130 /* 131 * Various high and low water marks, thresholds, etc ... 132 * 133 * Note: these are taken from revision 7 of the PRM, and some are different 134 * from both the values in earlier PRMs *and* those determined experimentally 135 * and used in earlier versions of this driver ... 136 */ 137 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 138 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 139 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 140 141 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 142 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 143 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 144 145 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 146 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 147 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 148 149 static uint32_t bge_watchdog_count = 1 << 16; 150 static uint16_t bge_dma_miss_limit = 20; 151 152 static uint32_t bge_stop_start_on_sync = 0; 153 154 boolean_t bge_jumbo_enable = B_TRUE; 155 static uint32_t bge_default_jumbo_size = BGE_JUMBO_BUFF_SIZE; 156 157 /* 158 * ========== Low-level chip & ring buffer manipulation ========== 159 */ 160 161 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 162 163 164 /* 165 * Config space read-modify-write routines 166 */ 167 168 #if BGE_CFG_IO8 169 170 /* 171 * 8- and 16-bit set/clr operations are not used; all the config registers 172 * that we need to do bit-twiddling on are 32 bits wide. I'll leave the 173 * code here, though, in case we ever find that we do want it after all ... 174 */ 175 176 static void bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 177 #pragma inline(bge_cfg_set8) 178 179 static void 180 bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 181 { 182 uint8_t regval; 183 184 BGE_TRACE(("bge_cfg_set8($%p, 0x%lx, 0x%x)", 185 (void *)bgep, regno, bits)); 186 187 regval = pci_config_get8(bgep->cfg_handle, regno); 188 189 BGE_DEBUG(("bge_cfg_set8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 190 (void *)bgep, regno, bits, regval, regval | bits)); 191 192 regval |= bits; 193 pci_config_put8(bgep->cfg_handle, regno, regval); 194 } 195 196 static void bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 197 #pragma inline(bge_cfg_clr8) 198 199 static void 200 bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 201 { 202 uint8_t regval; 203 204 BGE_TRACE(("bge_cfg_clr8($%p, 0x%lx, 0x%x)", 205 (void *)bgep, regno, bits)); 206 207 regval = pci_config_get8(bgep->cfg_handle, regno); 208 209 BGE_DEBUG(("bge_cfg_clr8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 210 (void *)bgep, regno, bits, regval, regval & ~bits)); 211 212 regval &= ~bits; 213 pci_config_put8(bgep->cfg_handle, regno, regval); 214 } 215 216 static void bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 217 #pragma inline(bge_cfg_set16) 218 219 static void 220 bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 221 { 222 uint16_t regval; 223 224 BGE_TRACE(("bge_cfg_set16($%p, 0x%lx, 0x%x)", 225 (void *)bgep, regno, bits)); 226 227 regval = pci_config_get16(bgep->cfg_handle, regno); 228 229 BGE_DEBUG(("bge_cfg_set16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 230 (void *)bgep, regno, bits, regval, regval | bits)); 231 232 regval |= bits; 233 pci_config_put16(bgep->cfg_handle, regno, regval); 234 } 235 236 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 237 #pragma inline(bge_cfg_clr16) 238 239 static void 240 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 241 { 242 uint16_t regval; 243 244 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 245 (void *)bgep, regno, bits)); 246 247 regval = pci_config_get16(bgep->cfg_handle, regno); 248 249 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 250 (void *)bgep, regno, bits, regval, regval & ~bits)); 251 252 regval &= ~bits; 253 pci_config_put16(bgep->cfg_handle, regno, regval); 254 } 255 256 #endif /* BGE_CFG_IO8 */ 257 258 static void bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 259 #pragma inline(bge_cfg_set32) 260 261 static void 262 bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 263 { 264 uint32_t regval; 265 266 BGE_TRACE(("bge_cfg_set32($%p, 0x%lx, 0x%x)", 267 (void *)bgep, regno, bits)); 268 269 regval = pci_config_get32(bgep->cfg_handle, regno); 270 271 BGE_DEBUG(("bge_cfg_set32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 272 (void *)bgep, regno, bits, regval, regval | bits)); 273 274 regval |= bits; 275 pci_config_put32(bgep->cfg_handle, regno, regval); 276 } 277 278 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 279 #pragma inline(bge_cfg_clr32) 280 281 static void 282 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 283 { 284 uint32_t regval; 285 286 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 287 (void *)bgep, regno, bits)); 288 289 regval = pci_config_get32(bgep->cfg_handle, regno); 290 291 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 292 (void *)bgep, regno, bits, regval, regval & ~bits)); 293 294 regval &= ~bits; 295 pci_config_put32(bgep->cfg_handle, regno, regval); 296 } 297 298 #if BGE_IND_IO32 299 300 /* 301 * Indirect access to registers & RISC scratchpads, using config space 302 * accesses only. 303 * 304 * This isn't currently used, but someday we might want to use it for 305 * restoring the Subsystem Device/Vendor registers (which aren't directly 306 * writable in Config Space), or for downloading firmware into the RISCs 307 * 308 * In any case there are endian issues to be resolved before this code is 309 * enabled; the bizarre way that bytes get twisted by this chip AND by 310 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 311 * it's been thoroughly tested for all access sizes on all supported 312 * architectures (SPARC *and* x86!). 313 */ 314 static uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 315 #pragma inline(bge_ind_get32) 316 317 static uint32_t 318 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 319 { 320 uint32_t val; 321 322 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 323 324 ASSERT(mutex_owned(bgep->genlock)); 325 326 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 327 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 328 329 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 330 (void *)bgep, regno, val)); 331 332 return (val); 333 } 334 335 static void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 336 #pragma inline(bge_ind_put32) 337 338 static void 339 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 340 { 341 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 342 (void *)bgep, regno, val)); 343 344 ASSERT(mutex_owned(bgep->genlock)); 345 346 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 347 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 348 } 349 350 #endif /* BGE_IND_IO32 */ 351 352 #if BGE_DEBUGGING 353 354 static void bge_pci_check(bge_t *bgep); 355 #pragma no_inline(bge_pci_check) 356 357 static void 358 bge_pci_check(bge_t *bgep) 359 { 360 uint16_t pcistatus; 361 362 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 363 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 364 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 365 (void *)bgep, pcistatus)); 366 } 367 368 #endif /* BGE_DEBUGGING */ 369 370 /* 371 * Perform first-stage chip (re-)initialisation, using only config-space 372 * accesses: 373 * 374 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 375 * returning the data in the structure pointed to by <idp>. 376 * + Configure the target-mode endianness (swap) options. 377 * + Disable interrupts and enable Memory Space accesses. 378 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 379 * 380 * This sequence is adapted from Broadcom document 570X-PG102-R, 381 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 382 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 383 * 384 * This function MUST be called before any non-config-space accesses 385 * are made; on this first call <enable_dma> is B_FALSE, and it 386 * effectively performs steps 3-1(!) of the initialisation sequence 387 * (the rest are not required but should be harmless). 388 * 389 * It MUST also be called also after a chip reset, as this disables 390 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 391 * it is effectively performing steps 6-8. 392 */ 393 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 394 #pragma no_inline(bge_chip_cfg_init) 395 396 void 397 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 398 { 399 ddi_acc_handle_t handle; 400 uint16_t command; 401 uint32_t mhcr; 402 uint16_t value16; 403 int i; 404 405 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 406 (void *)bgep, (void *)cidp, enable_dma)); 407 408 /* 409 * Step 3: save PCI cache line size and subsystem vendor ID 410 * 411 * Read all the config-space registers that characterise the 412 * chip, specifically vendor/device/revision/subsystem vendor 413 * and subsystem device id. We expect (but don't check) that 414 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 415 * 416 * Also save all bus-transation related registers (cache-line 417 * size, bus-grant/latency parameters, etc). Some of these are 418 * cleared by reset, so we'll have to restore them later. This 419 * comes from the Broadcom document 570X-PG102-R ... 420 * 421 * Note: Broadcom document 570X-PG102-R seems to be in error 422 * here w.r.t. the offsets of the Subsystem Vendor ID and 423 * Subsystem (Device) ID registers, which are the opposite way 424 * round according to the PCI standard. For good measure, we 425 * save/restore both anyway. 426 */ 427 handle = bgep->cfg_handle; 428 429 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 430 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 431 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 432 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 433 434 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 435 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 436 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 437 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 438 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 439 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 440 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 441 442 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 443 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 444 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 445 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 446 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 447 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 448 cidp->vendor, cidp->device, cidp->revision)); 449 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 450 cidp->subven, cidp->subdev, cidp->asic_rev)); 451 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 452 cidp->clsize, cidp->latency, cidp->command)); 453 454 /* 455 * Step 2 (also step 6): disable and clear interrupts. 456 * Steps 11-13: configure PIO endianness options, and enable 457 * indirect register access. We'll also select any other 458 * options controlled by the MHCR (eg tagged status, mask 459 * interrupt mode) at this stage ... 460 * 461 * Note: internally, the chip is 64-bit and BIG-endian, but 462 * since it talks to the host over a (LITTLE-endian) PCI bus, 463 * it normally swaps bytes around at the PCI interface. 464 * However, the PCI host bridge on SPARC systems normally 465 * swaps the byte lanes around too, since SPARCs are also 466 * BIG-endian. So it turns out that on SPARC, the right 467 * option is to tell the chip to swap (and the host bridge 468 * will swap back again), whereas on x86 we ask the chip 469 * NOT to swap, so the natural little-endianness of the 470 * PCI bus is assumed. Then the only thing that doesn't 471 * automatically work right is access to an 8-byte register 472 * by a little-endian host; but we don't want to set the 473 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 474 * accesses don't go where expected ;-( So we live with 475 * that, and perform word-swaps in software in the few cases 476 * where a chip register is defined as an 8-byte value -- 477 * see the code below for details ... 478 * 479 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 480 * very clear in the register description in the PRM, but 481 * Broadcom document 570X-PG104-R page 248 explains a little 482 * more (under "Broadcom Mask Mode"). The bit changes the way 483 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 484 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 485 * way as the 5700 did, which isn't very convenient. Setting 486 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 487 * bit do just what its name says -- MASK the PCI #INTA output 488 * (i.e. deassert the signal at the pin) leaving all internal 489 * state unchanged. This is much more convenient for our 490 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 491 * 492 * Note: the inconvenient semantics of the interrupt mailbox 493 * (nonzero disables and acknowledges/clears the interrupt, 494 * zero enables AND CLEARS it) would make race conditions 495 * likely in the interrupt handler: 496 * 497 * (1) acknowledge & disable interrupts 498 * (2) while (more to do) 499 * process packets 500 * (3) enable interrupts -- also clears pending 501 * 502 * If the chip received more packets and internally generated 503 * an interrupt between the check at (2) and the mbox write 504 * at (3), this interrupt would be lost :-( 505 * 506 * The best way to avoid this is to use TAGGED STATUS mode, 507 * where the chip includes a unique tag in each status block 508 * update, and the host, when re-enabling interrupts, passes 509 * the last tag it saw back to the chip; then the chip can 510 * see whether the host is truly up to date, and regenerate 511 * its interrupt if not. 512 */ 513 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 514 MHCR_ENABLE_TAGGED_STATUS_MODE | 515 MHCR_MASK_INTERRUPT_MODE | 516 MHCR_CLEAR_INTERRUPT_INTA; 517 518 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 519 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 520 521 #ifdef _BIG_ENDIAN 522 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 523 #endif /* _BIG_ENDIAN */ 524 525 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 526 527 #ifdef BGE_IPMI_ASF 528 bgep->asf_wordswapped = B_FALSE; 529 #endif 530 /* 531 * Step 1 (also step 7): Enable PCI Memory Space accesses 532 * Disable Memory Write/Invalidate 533 * Enable or disable Bus Mastering 534 * 535 * Note that all other bits are taken from the original value saved 536 * the first time through here, rather than from the current register 537 * value, 'cos that will have been cleared by a soft RESET since. 538 * In this way we preserve the OBP/nexus-parent's preferred settings 539 * of the parity-error and system-error enable bits across multiple 540 * chip RESETs. 541 * 542 * Step 8: Disable PCI-X Relaxed Ordering -- doesn't apply 543 */ 544 command = bgep->chipid.command | PCI_COMM_MAE; 545 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 546 if (enable_dma) 547 command |= PCI_COMM_ME; 548 /* 549 * on BCM5714 revision A0, false parity error gets generated 550 * due to a logic bug. Provide a workaround by disabling parrity 551 * error. 552 */ 553 if (((cidp->device == DEVICE_ID_5714C) || 554 (cidp->device == DEVICE_ID_5714S)) && 555 (cidp->revision == REVISION_ID_5714_A0)) { 556 command &= ~PCI_COMM_PARITY_DETECT; 557 } 558 pci_config_put16(handle, PCI_CONF_COMM, command); 559 560 /* 561 * On some PCI-E device, there were instances when 562 * the device was still link training. 563 */ 564 if (bgep->chipid.pci_type == BGE_PCI_E) { 565 i = 0; 566 value16 = pci_config_get16(handle, PCI_CONF_COMM); 567 while ((value16 != command) && (i < 100)) { 568 drv_usecwait(200); 569 value16 = pci_config_get16(handle, PCI_CONF_COMM); 570 ++i; 571 } 572 } 573 574 /* 575 * Clear any remaining error status bits 576 */ 577 pci_config_put16(handle, PCI_CONF_STAT, ~0); 578 579 /* 580 * Make sure these indirect-access registers are sane 581 * rather than random after power-up or reset 582 * 583 * For BCM5714C A3 silicon to avoid resource deadlocking 584 */ 585 if ((cidp->device == DEVICE_ID_5714C) && 586 (cidp->revision == REVISION_ID_5714_A3)) { 587 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0x4900); 588 pci_config_put32(handle, PCI_CONF_BGE_RIADR, 1); 589 } else { 590 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 591 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 592 } 593 } 594 595 #ifdef __amd64 596 /* 597 * Distinguish CPU types 598 * 599 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 600 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 601 * for PCI-Express based network interface card. This is the work-around 602 * for those nics. 603 */ 604 static boolean_t bge_get_em64t_type(void); 605 #pragma inline(bge_get_em64t_type) 606 607 static boolean_t 608 bge_get_em64t_type(void) 609 { 610 611 return (x86_vendor == X86_VENDOR_Intel); 612 } 613 #endif 614 615 /* 616 * Operating register get/set access routines 617 */ 618 619 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 620 #pragma inline(bge_reg_get32) 621 622 uint32_t 623 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 624 { 625 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 626 (void *)bgep, regno)); 627 628 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 629 } 630 631 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 632 #pragma inline(bge_reg_put32) 633 634 void 635 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 636 { 637 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 638 (void *)bgep, regno, data)); 639 640 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 641 BGE_PCICHK(bgep); 642 } 643 644 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 645 #pragma inline(bge_reg_set32) 646 647 void 648 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 649 { 650 uint32_t regval; 651 652 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 653 (void *)bgep, regno, bits)); 654 655 regval = bge_reg_get32(bgep, regno); 656 regval |= bits; 657 bge_reg_put32(bgep, regno, regval); 658 } 659 660 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 661 #pragma inline(bge_reg_clr32) 662 663 void 664 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 665 { 666 uint32_t regval; 667 668 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 669 (void *)bgep, regno, bits)); 670 671 regval = bge_reg_get32(bgep, regno); 672 regval &= ~bits; 673 bge_reg_put32(bgep, regno, regval); 674 } 675 676 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 677 #pragma inline(bge_reg_get64) 678 679 static uint64_t 680 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 681 { 682 uint64_t regval; 683 684 #ifdef __amd64 685 if (bge_get_em64t_type()) { 686 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 687 regval <<= 32; 688 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 689 } else { 690 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 691 } 692 #else 693 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 694 #endif 695 696 #ifdef _LITTLE_ENDIAN 697 regval = (regval >> 32) | (regval << 32); 698 #endif /* _LITTLE_ENDIAN */ 699 700 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 701 (void *)bgep, regno, regval)); 702 703 return (regval); 704 } 705 706 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 707 #pragma inline(bge_reg_put64) 708 709 static void 710 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 711 { 712 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 713 (void *)bgep, regno, data)); 714 715 #ifdef _LITTLE_ENDIAN 716 data = ((data >> 32) | (data << 32)); 717 #endif /* _LITTLE_ENDIAN */ 718 719 #ifdef __amd64 720 if (bge_get_em64t_type()) { 721 ddi_put32(bgep->io_handle, 722 PIO_ADDR(bgep, regno), (uint32_t)data); 723 BGE_PCICHK(bgep); 724 ddi_put32(bgep->io_handle, 725 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 726 727 } else { 728 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 729 } 730 #else 731 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 732 #endif 733 734 BGE_PCICHK(bgep); 735 } 736 737 /* 738 * The DDI doesn't provide get/put functions for 128 bit data 739 * so we put RCBs out as two 64-bit chunks instead. 740 */ 741 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 742 #pragma inline(bge_reg_putrcb) 743 744 static void 745 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 746 { 747 uint64_t *p; 748 749 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 750 (void *)bgep, addr, rcbp->host_ring_addr, 751 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 752 753 ASSERT((addr % sizeof (*rcbp)) == 0); 754 755 p = (void *)rcbp; 756 bge_reg_put64(bgep, addr, *p++); 757 bge_reg_put64(bgep, addr+8, *p); 758 } 759 760 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 761 #pragma inline(bge_mbx_put) 762 763 void 764 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 765 { 766 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 767 (void *)bgep, regno, data)); 768 769 /* 770 * Mailbox registers are nominally 64 bits on the 5701, but 771 * the MSW isn't used. On the 5703, they're only 32 bits 772 * anyway. So here we just write the lower(!) 32 bits - 773 * remembering that the chip is big-endian, even though the 774 * PCI bus is little-endian ... 775 */ 776 #ifdef _BIG_ENDIAN 777 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 778 #else 779 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 780 #endif /* _BIG_ENDIAN */ 781 BGE_PCICHK(bgep); 782 } 783 784 #if BGE_DEBUGGING 785 786 void bge_led_mark(bge_t *bgep); 787 #pragma no_inline(bge_led_mark) 788 789 void 790 bge_led_mark(bge_t *bgep) 791 { 792 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 793 LED_CONTROL_1000MBPS_LED | 794 LED_CONTROL_100MBPS_LED | 795 LED_CONTROL_10MBPS_LED; 796 797 /* 798 * Blink all three LINK LEDs on simultaneously, then all off, 799 * then restore to automatic hardware control. This is used 800 * in laboratory testing to trigger a logic analyser or scope. 801 */ 802 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 803 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 804 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 805 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 806 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 807 } 808 809 #endif /* BGE_DEBUGGING */ 810 811 /* 812 * NIC on-chip memory access routines 813 * 814 * Only 32K of NIC memory is visible at a time, controlled by the 815 * Memory Window Base Address Register (in PCI config space). Once 816 * this is set, the 32K region of NIC-local memory that it refers 817 * to can be directly addressed in the upper 32K of the 64K of PCI 818 * memory space used for the device. 819 */ 820 821 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 822 #pragma inline(bge_nic_setwin) 823 824 static void 825 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 826 { 827 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 828 (void *)bgep, base)); 829 830 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 831 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 832 } 833 834 835 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 836 #pragma inline(bge_nic_get32) 837 838 static uint32_t 839 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 840 { 841 uint32_t data; 842 843 #ifdef BGE_IPMI_ASF 844 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 845 /* workaround for word swap error */ 846 if (addr & 4) 847 addr = addr - 4; 848 else 849 addr = addr + 4; 850 } 851 #endif 852 853 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 854 addr &= MWBAR_GRANULE_MASK; 855 addr += NIC_MEM_WINDOW_OFFSET; 856 857 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 858 859 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 860 (void *)bgep, addr, data)); 861 862 return (data); 863 } 864 865 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 866 #pragma inline(bge_nic_put32) 867 868 void 869 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 870 { 871 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 872 (void *)bgep, addr, data)); 873 874 #ifdef BGE_IPMI_ASF 875 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 876 /* workaround for word swap error */ 877 if (addr & 4) 878 addr = addr - 4; 879 else 880 addr = addr + 4; 881 } 882 #endif 883 884 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 885 addr &= MWBAR_GRANULE_MASK; 886 addr += NIC_MEM_WINDOW_OFFSET; 887 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 888 BGE_PCICHK(bgep); 889 } 890 891 892 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 893 #pragma inline(bge_nic_get64) 894 895 static uint64_t 896 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 897 { 898 uint64_t data; 899 900 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 901 addr &= MWBAR_GRANULE_MASK; 902 addr += NIC_MEM_WINDOW_OFFSET; 903 904 #ifdef __amd64 905 if (bge_get_em64t_type()) { 906 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 907 data <<= 32; 908 data |= ddi_get32(bgep->io_handle, 909 PIO_ADDR(bgep, addr + 4)); 910 } else { 911 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 912 } 913 #else 914 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 915 #endif 916 917 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 918 (void *)bgep, addr, data)); 919 920 return (data); 921 } 922 923 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 924 #pragma inline(bge_nic_put64) 925 926 static void 927 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 928 { 929 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 930 (void *)bgep, addr, data)); 931 932 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 933 addr &= MWBAR_GRANULE_MASK; 934 addr += NIC_MEM_WINDOW_OFFSET; 935 936 #ifdef __amd64 937 if (bge_get_em64t_type()) { 938 ddi_put32(bgep->io_handle, 939 PIO_ADDR(bgep, addr), (uint32_t)data); 940 BGE_PCICHK(bgep); 941 ddi_put32(bgep->io_handle, 942 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 943 } else { 944 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 945 } 946 #else 947 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 948 #endif 949 950 BGE_PCICHK(bgep); 951 } 952 953 /* 954 * The DDI doesn't provide get/put functions for 128 bit data 955 * so we put RCBs out as two 64-bit chunks instead. 956 */ 957 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 958 #pragma inline(bge_nic_putrcb) 959 960 static void 961 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 962 { 963 uint64_t *p; 964 965 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 966 (void *)bgep, addr, rcbp->host_ring_addr, 967 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 968 969 ASSERT((addr % sizeof (*rcbp)) == 0); 970 971 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 972 addr &= MWBAR_GRANULE_MASK; 973 addr += NIC_MEM_WINDOW_OFFSET; 974 975 p = (void *)rcbp; 976 #ifdef __amd64 977 if (bge_get_em64t_type()) { 978 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 979 (uint32_t)(*p)); 980 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 981 (uint32_t)(*p >> 32)); 982 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 983 (uint32_t)(*(p + 1))); 984 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 985 (uint32_t)(*p >> 32)); 986 987 } else { 988 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 989 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 990 } 991 #else 992 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 993 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 994 #endif 995 996 BGE_PCICHK(bgep); 997 } 998 999 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1000 #pragma inline(bge_nic_zero) 1001 1002 static void 1003 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1004 { 1005 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1006 (void *)bgep, addr, nbytes)); 1007 1008 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1009 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1010 1011 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1012 addr &= MWBAR_GRANULE_MASK; 1013 addr += NIC_MEM_WINDOW_OFFSET; 1014 1015 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1016 nbytes, 1, DDI_DATA_SZ08_ACC); 1017 BGE_PCICHK(bgep); 1018 } 1019 1020 /* 1021 * MII (PHY) register get/set access routines 1022 * 1023 * These use the chip's MII auto-access method, controlled by the 1024 * MII Communication register at 0x044c, so the CPU doesn't have 1025 * to fiddle with the individual bits. 1026 */ 1027 1028 #undef BGE_DBG 1029 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1030 1031 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1032 uint16_t data, uint32_t cmd); 1033 #pragma no_inline(bge_mii_access) 1034 1035 static uint16_t 1036 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1037 { 1038 uint32_t timeout; 1039 uint32_t regval1; 1040 uint32_t regval2; 1041 1042 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1043 (void *)bgep, regno, data, cmd)); 1044 1045 ASSERT(mutex_owned(bgep->genlock)); 1046 1047 /* 1048 * Assemble the command ... 1049 */ 1050 cmd |= data << MI_COMMS_DATA_SHIFT; 1051 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1052 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1053 cmd |= MI_COMMS_START; 1054 1055 /* 1056 * Wait for any command already in progress ... 1057 * 1058 * Note: this *shouldn't* ever find that there is a command 1059 * in progress, because we already hold the <genlock> mutex. 1060 * Nonetheless, we have sometimes seen the MI_COMMS_START 1061 * bit set here -- it seems that the chip can initiate MII 1062 * accesses internally, even with polling OFF. 1063 */ 1064 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1065 for (timeout = 100; ; ) { 1066 if ((regval2 & MI_COMMS_START) == 0) { 1067 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1068 break; 1069 } 1070 if (--timeout == 0) 1071 break; 1072 drv_usecwait(10); 1073 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1074 } 1075 1076 if (timeout == 0) 1077 return ((uint16_t)~0u); 1078 1079 if (timeout != 100) 1080 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1081 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1082 cmd, 10*(100-timeout), regval1, regval2)); 1083 1084 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1085 for (timeout = 1000; ; ) { 1086 if ((regval1 & MI_COMMS_START) == 0) 1087 break; 1088 if (--timeout == 0) 1089 break; 1090 drv_usecwait(10); 1091 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1092 } 1093 1094 /* 1095 * Drop out early if the READ FAILED bit is set -- this chip 1096 * could be a 5703/4S, with a SerDes instead of a PHY! 1097 */ 1098 if (regval2 & MI_COMMS_READ_FAILED) 1099 return ((uint16_t)~0u); 1100 1101 if (timeout == 0) 1102 return ((uint16_t)~0u); 1103 1104 /* 1105 * The PRM says to wait 5us after seeing the START bit clear 1106 * and then re-read the register to get the final value of the 1107 * data field, in order to avoid a race condition where the 1108 * START bit is clear but the data field isn't yet valid. 1109 * 1110 * Note: we don't actually seem to be encounter this race; 1111 * except when the START bit is seen set again (see below), 1112 * the data field doesn't change during this 5us interval. 1113 */ 1114 drv_usecwait(5); 1115 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1116 1117 /* 1118 * Unfortunately, when following the PRMs instructions above, 1119 * we have occasionally seen the START bit set again(!) in the 1120 * value read after the 5us delay. This seems to be due to the 1121 * chip autonomously starting another MII access internally. 1122 * In such cases, the command/data/etc fields relate to the 1123 * internal command, rather than the one that we thought had 1124 * just finished. So in this case, we fall back to returning 1125 * the data from the original read that showed START clear. 1126 */ 1127 if (regval2 & MI_COMMS_START) { 1128 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1129 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1130 cmd, regval1, regval2)); 1131 regval2 = regval1; 1132 } 1133 1134 if (regval2 & MI_COMMS_START) 1135 return ((uint16_t)~0u); 1136 1137 if (regval2 & MI_COMMS_READ_FAILED) 1138 return ((uint16_t)~0u); 1139 1140 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1141 } 1142 1143 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1144 #pragma no_inline(bge_mii_get16) 1145 1146 uint16_t 1147 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1148 { 1149 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1150 (void *)bgep, regno)); 1151 1152 ASSERT(mutex_owned(bgep->genlock)); 1153 1154 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1155 } 1156 1157 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1158 #pragma no_inline(bge_mii_put16) 1159 1160 void 1161 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1162 { 1163 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1164 (void *)bgep, regno, data)); 1165 1166 ASSERT(mutex_owned(bgep->genlock)); 1167 1168 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1169 } 1170 1171 #undef BGE_DBG 1172 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1173 1174 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1175 1176 /* 1177 * Basic SEEPROM get/set access routine 1178 * 1179 * This uses the chip's SEEPROM auto-access method, controlled by the 1180 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1181 * doesn't have to fiddle with the individual bits. 1182 * 1183 * The caller should hold <genlock> and *also* have already acquired 1184 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1185 * 1186 * Return value: 1187 * 0 on success, 1188 * ENODATA on access timeout (maybe retryable: device may just be busy) 1189 * EPROTO on other h/w or s/w errors. 1190 * 1191 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1192 * from a (successful) SEEPROM_ACCESS_READ. 1193 */ 1194 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1195 uint32_t *dp); 1196 #pragma no_inline(bge_seeprom_access) 1197 1198 static int 1199 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1200 { 1201 uint32_t tries; 1202 uint32_t regval; 1203 1204 ASSERT(mutex_owned(bgep->genlock)); 1205 1206 /* 1207 * On the newer chips that support both SEEPROM & Flash, we need 1208 * to specifically enable SEEPROM access (Flash is the default). 1209 * On older chips, we don't; SEEPROM is the only NVtype supported, 1210 * and the NVM control registers don't exist ... 1211 */ 1212 switch (bgep->chipid.nvtype) { 1213 case BGE_NVTYPE_NONE: 1214 case BGE_NVTYPE_UNKNOWN: 1215 _NOTE(NOTREACHED) 1216 case BGE_NVTYPE_SEEPROM: 1217 break; 1218 1219 case BGE_NVTYPE_LEGACY_SEEPROM: 1220 case BGE_NVTYPE_UNBUFFERED_FLASH: 1221 case BGE_NVTYPE_BUFFERED_FLASH: 1222 default: 1223 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1224 NVM_CFG1_LEGACY_SEEPROM_MODE); 1225 break; 1226 } 1227 1228 /* 1229 * Check there's no command in progress. 1230 * 1231 * Note: this *shouldn't* ever find that there is a command 1232 * in progress, because we already hold the <genlock> mutex. 1233 * Also, to ensure we don't have a conflict with the chip's 1234 * internal firmware or a process accessing the same (shared) 1235 * SEEPROM through the other port of a 5704, we've already 1236 * been through the "software arbitration" protocol. 1237 * So this is just a final consistency check: we shouldn't 1238 * see EITHER the START bit (command started but not complete) 1239 * OR the COMPLETE bit (command completed but not cleared). 1240 */ 1241 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1242 if (regval & SEEPROM_ACCESS_START) 1243 return (EPROTO); 1244 if (regval & SEEPROM_ACCESS_COMPLETE) 1245 return (EPROTO); 1246 1247 /* 1248 * Assemble the command ... 1249 */ 1250 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1251 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1252 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1253 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1254 cmd |= SEEPROM_ACCESS_START; 1255 cmd |= SEEPROM_ACCESS_COMPLETE; 1256 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1257 1258 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1259 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1260 1261 /* 1262 * By observation, a successful access takes ~20us on a 5703/4, 1263 * but apparently much longer (up to 1000us) on the obsolescent 1264 * BCM5700/BCM5701. We want to be sure we don't get any false 1265 * timeouts here; but OTOH, we don't want a bogus access to lock 1266 * out interrupts for longer than necessary. So we'll allow up 1267 * to 1000us ... 1268 */ 1269 for (tries = 0; tries < 1000; ++tries) { 1270 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1271 if (regval & SEEPROM_ACCESS_COMPLETE) 1272 break; 1273 drv_usecwait(1); 1274 } 1275 1276 if (regval & SEEPROM_ACCESS_COMPLETE) { 1277 /* 1278 * All OK; read the SEEPROM data register, then write back 1279 * the value read from the address register in order to 1280 * clear the <complete> bit and leave the SEEPROM access 1281 * state machine idle, ready for the next access ... 1282 */ 1283 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1284 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1285 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1286 return (0); 1287 } 1288 1289 /* 1290 * Hmm ... what happened here? 1291 * 1292 * Most likely, the user addressed an non-existent SEEPROM. Or 1293 * maybe the SEEPROM was busy internally (e.g. processing a write) 1294 * and didn't respond to being addressed. Either way, it's left 1295 * the SEEPROM access state machine wedged. So we'll reset it 1296 * before we leave, so it's ready for next time ... 1297 */ 1298 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1299 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1300 return (ENODATA); 1301 } 1302 1303 /* 1304 * Basic Flash get/set access routine 1305 * 1306 * These use the chip's Flash auto-access method, controlled by the 1307 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1308 * fiddle with the individual bits. 1309 * 1310 * The caller should hold <genlock> and *also* have already acquired 1311 * the right to access the Flash, via bge_nvmem_acquire() above. 1312 * 1313 * Return value: 1314 * 0 on success, 1315 * ENODATA on access timeout (maybe retryable: device may just be busy) 1316 * ENODEV if the NVmem device is missing or otherwise unusable 1317 * 1318 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1319 * from a (successful) NVM_FLASH_CMD_RD. 1320 */ 1321 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1322 uint32_t *dp); 1323 #pragma no_inline(bge_flash_access) 1324 1325 static int 1326 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1327 { 1328 uint32_t tries; 1329 uint32_t regval; 1330 1331 ASSERT(mutex_owned(bgep->genlock)); 1332 1333 /* 1334 * On the newer chips that support both SEEPROM & Flash, we need 1335 * to specifically disable SEEPROM access while accessing Flash. 1336 * The older chips don't support Flash, and the NVM registers don't 1337 * exist, so we shouldn't be here at all! 1338 */ 1339 switch (bgep->chipid.nvtype) { 1340 case BGE_NVTYPE_NONE: 1341 case BGE_NVTYPE_UNKNOWN: 1342 _NOTE(NOTREACHED) 1343 case BGE_NVTYPE_SEEPROM: 1344 return (ENODEV); 1345 1346 case BGE_NVTYPE_LEGACY_SEEPROM: 1347 case BGE_NVTYPE_UNBUFFERED_FLASH: 1348 case BGE_NVTYPE_BUFFERED_FLASH: 1349 default: 1350 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1351 NVM_CFG1_LEGACY_SEEPROM_MODE); 1352 break; 1353 } 1354 1355 /* 1356 * Assemble the command ... 1357 */ 1358 addr &= NVM_FLASH_ADDR_MASK; 1359 cmd |= NVM_FLASH_CMD_DOIT; 1360 cmd |= NVM_FLASH_CMD_FIRST; 1361 cmd |= NVM_FLASH_CMD_LAST; 1362 cmd |= NVM_FLASH_CMD_DONE; 1363 1364 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1365 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1366 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1367 1368 /* 1369 * Allow up to 1000ms ... 1370 */ 1371 for (tries = 0; tries < 1000; ++tries) { 1372 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1373 if (regval & NVM_FLASH_CMD_DONE) 1374 break; 1375 drv_usecwait(1); 1376 } 1377 1378 if (regval & NVM_FLASH_CMD_DONE) { 1379 /* 1380 * All OK; read the data from the Flash read register 1381 */ 1382 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1383 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1384 return (0); 1385 } 1386 1387 /* 1388 * Hmm ... what happened here? 1389 * 1390 * Most likely, the user addressed an non-existent Flash. Or 1391 * maybe the Flash was busy internally (e.g. processing a write) 1392 * and didn't respond to being addressed. Either way, there's 1393 * nothing we can here ... 1394 */ 1395 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1396 return (ENODATA); 1397 } 1398 1399 /* 1400 * The next two functions regulate access to the NVram (if fitted). 1401 * 1402 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1403 * (SPI) interface, but they can be accessed through either port. These 1404 * are managed by different instance of this driver and have no software 1405 * state in common. 1406 * 1407 * In addition (and even on a single core chip) the chip's internal 1408 * firmware can access the SEEPROM/Flash, most notably after a RESET 1409 * when it may download code to run internally. 1410 * 1411 * So we need to arbitrate between these various software agents. For 1412 * this purpose, the chip provides the Software Arbitration Register, 1413 * which implements hardware(!) arbitration. 1414 * 1415 * This functionality didn't exist on older (5700/5701) chips, so there's 1416 * nothing we can do by way of arbitration on those; also, if there's no 1417 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1418 * nothing to do. 1419 * 1420 * The internal firmware appears to use Request 0, which is the highest 1421 * priority. So we'd like to use Request 2, leaving one higher and one 1422 * lower for any future developments ... but apparently this doesn't 1423 * always work. So for now, the code uses Request 1 ;-( 1424 */ 1425 1426 #define NVM_READ_REQ NVM_READ_REQ1 1427 #define NVM_RESET_REQ NVM_RESET_REQ1 1428 #define NVM_SET_REQ NVM_SET_REQ1 1429 1430 static void bge_nvmem_relinquish(bge_t *bgep); 1431 #pragma no_inline(bge_nvmem_relinquish) 1432 1433 static void 1434 bge_nvmem_relinquish(bge_t *bgep) 1435 { 1436 ASSERT(mutex_owned(bgep->genlock)); 1437 1438 switch (bgep->chipid.nvtype) { 1439 case BGE_NVTYPE_NONE: 1440 case BGE_NVTYPE_UNKNOWN: 1441 _NOTE(NOTREACHED) 1442 return; 1443 1444 case BGE_NVTYPE_SEEPROM: 1445 /* 1446 * No arbitration performed, no release needed 1447 */ 1448 return; 1449 1450 case BGE_NVTYPE_LEGACY_SEEPROM: 1451 case BGE_NVTYPE_UNBUFFERED_FLASH: 1452 case BGE_NVTYPE_BUFFERED_FLASH: 1453 default: 1454 break; 1455 } 1456 1457 /* 1458 * Our own request should be present (whether or not granted) ... 1459 */ 1460 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1461 1462 /* 1463 * ... this will make it go away. 1464 */ 1465 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1466 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1467 } 1468 1469 /* 1470 * Arbitrate for access to the NVmem, if necessary 1471 * 1472 * Return value: 1473 * 0 on success 1474 * EAGAIN if the device is in use (retryable) 1475 * ENODEV if the NVmem device is missing or otherwise unusable 1476 */ 1477 static int bge_nvmem_acquire(bge_t *bgep); 1478 #pragma no_inline(bge_nvmem_acquire) 1479 1480 static int 1481 bge_nvmem_acquire(bge_t *bgep) 1482 { 1483 uint32_t regval; 1484 uint32_t tries; 1485 1486 ASSERT(mutex_owned(bgep->genlock)); 1487 1488 switch (bgep->chipid.nvtype) { 1489 case BGE_NVTYPE_NONE: 1490 case BGE_NVTYPE_UNKNOWN: 1491 /* 1492 * Access denied: no (recognisable) device fitted 1493 */ 1494 return (ENODEV); 1495 1496 case BGE_NVTYPE_SEEPROM: 1497 /* 1498 * Access granted: no arbitration needed (or possible) 1499 */ 1500 return (0); 1501 1502 case BGE_NVTYPE_LEGACY_SEEPROM: 1503 case BGE_NVTYPE_UNBUFFERED_FLASH: 1504 case BGE_NVTYPE_BUFFERED_FLASH: 1505 default: 1506 /* 1507 * Access conditional: conduct arbitration protocol 1508 */ 1509 break; 1510 } 1511 1512 /* 1513 * We're holding the per-port mutex <genlock>, so no-one other 1514 * threads can be attempting to access the NVmem through *this* 1515 * port. But it could be in use by the *other* port (of a 5704), 1516 * or by the chip's internal firmware, so we have to go through 1517 * the full (hardware) arbitration protocol ... 1518 * 1519 * Note that *because* we're holding <genlock>, the interrupt handler 1520 * won't be able to progress. So we're only willing to spin for a 1521 * fairly short time. Specifically: 1522 * 1523 * We *must* wait long enough for the hardware to resolve all 1524 * requests and determine the winner. Fortunately, this is 1525 * "almost instantaneous", even as observed by GHz CPUs. 1526 * 1527 * A successful access by another Solaris thread (via either 1528 * port) typically takes ~20us. So waiting a bit longer than 1529 * that will give a good chance of success, if the other user 1530 * *is* another thread on the other port. 1531 * 1532 * However, the internal firmware can hold on to the NVmem 1533 * for *much* longer: at least 10 milliseconds just after a 1534 * RESET, and maybe even longer if the NVmem actually contains 1535 * code to download and run on the internal CPUs. 1536 * 1537 * So, we'll allow 50us; if that's not enough then it's up to the 1538 * caller to retry later (hence the choice of return code EAGAIN). 1539 */ 1540 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1541 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1542 1543 for (tries = 0; tries < 50; ++tries) { 1544 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1545 if (regval & NVM_WON_REQ1) 1546 break; 1547 drv_usecwait(1); 1548 } 1549 1550 if (regval & NVM_WON_REQ1) { 1551 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1552 return (0); 1553 } 1554 1555 /* 1556 * Somebody else must be accessing the NVmem, so abandon our 1557 * attempt take control of it. The caller can try again later ... 1558 */ 1559 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1560 bge_nvmem_relinquish(bgep); 1561 return (EAGAIN); 1562 } 1563 1564 /* 1565 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1566 * write protect line in such a way that the NVmem is protected when 1567 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1568 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1569 * 1570 * Note: there's only one set of GPIO pins on a 5704, even though they 1571 * can be accessed through either port. So the chip has to resolve what 1572 * happens if the two ports program a single pin differently ... the rule 1573 * it uses is that if the ports disagree about the *direction* of a pin, 1574 * "output" wins over "input", but if they disagree about its *value* as 1575 * an output, then the pin is TRISTATED instead! In such a case, no-one 1576 * wins, and the external signal does whatever the external circuitry 1577 * defines as the default -- which we've assumed is the PROTECTED state. 1578 * So, we always change GPIO1 back to being an *input* whenever we're not 1579 * specifically using it to unprotect the NVmem. This allows either port 1580 * to update the NVmem, although obviously only one at a a time! 1581 * 1582 * The caller should hold <genlock> and *also* have already acquired the 1583 * right to access the NVmem, via bge_nvmem_acquire() above. 1584 */ 1585 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1586 #pragma inline(bge_nvmem_protect) 1587 1588 static void 1589 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1590 { 1591 uint32_t regval; 1592 1593 ASSERT(mutex_owned(bgep->genlock)); 1594 1595 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1596 if (protect) { 1597 regval |= MLCR_MISC_PINS_OUTPUT_1; 1598 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1599 } else { 1600 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1601 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1602 } 1603 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1604 } 1605 1606 /* 1607 * Now put it all together ... 1608 * 1609 * Try to acquire control of the NVmem; if successful, then: 1610 * unprotect it (if we want to write to it) 1611 * perform the requested access 1612 * reprotect it (after a write) 1613 * relinquish control 1614 * 1615 * Return value: 1616 * 0 on success, 1617 * EAGAIN if the device is in use (retryable) 1618 * ENODATA on access timeout (maybe retryable: device may just be busy) 1619 * ENODEV if the NVmem device is missing or otherwise unusable 1620 * EPROTO on other h/w or s/w errors. 1621 */ 1622 static int 1623 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1624 { 1625 int err; 1626 1627 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1628 switch (cmd) { 1629 case BGE_SEE_READ: 1630 err = bge_seeprom_access(bgep, 1631 SEEPROM_ACCESS_READ, addr, dp); 1632 break; 1633 1634 case BGE_SEE_WRITE: 1635 bge_nvmem_protect(bgep, B_FALSE); 1636 err = bge_seeprom_access(bgep, 1637 SEEPROM_ACCESS_WRITE, addr, dp); 1638 bge_nvmem_protect(bgep, B_TRUE); 1639 break; 1640 1641 case BGE_FLASH_READ: 1642 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1643 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1644 bge_reg_set32(bgep, NVM_ACCESS_REG, 1645 NVM_ACCESS_ENABLE); 1646 } 1647 err = bge_flash_access(bgep, 1648 NVM_FLASH_CMD_RD, addr, dp); 1649 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1650 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1651 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1652 NVM_ACCESS_ENABLE); 1653 } 1654 break; 1655 1656 case BGE_FLASH_WRITE: 1657 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1658 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1659 bge_reg_set32(bgep, NVM_ACCESS_REG, 1660 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1661 } 1662 bge_nvmem_protect(bgep, B_FALSE); 1663 err = bge_flash_access(bgep, 1664 NVM_FLASH_CMD_WR, addr, dp); 1665 bge_nvmem_protect(bgep, B_TRUE); 1666 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1667 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1668 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1669 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1670 } 1671 1672 break; 1673 1674 default: 1675 _NOTE(NOTREACHED) 1676 break; 1677 } 1678 bge_nvmem_relinquish(bgep); 1679 } 1680 1681 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1682 return (err); 1683 } 1684 1685 /* 1686 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1687 */ 1688 static uint64_t bge_get_nvmac(bge_t *bgep); 1689 #pragma no_inline(bge_get_nvmac) 1690 1691 static uint64_t 1692 bge_get_nvmac(bge_t *bgep) 1693 { 1694 uint32_t mac_high; 1695 uint32_t mac_low; 1696 uint32_t addr; 1697 uint32_t cmd; 1698 uint64_t mac; 1699 1700 BGE_TRACE(("bge_get_nvmac($%p)", 1701 (void *)bgep)); 1702 1703 switch (bgep->chipid.nvtype) { 1704 case BGE_NVTYPE_NONE: 1705 case BGE_NVTYPE_UNKNOWN: 1706 default: 1707 return (0ULL); 1708 1709 case BGE_NVTYPE_SEEPROM: 1710 case BGE_NVTYPE_LEGACY_SEEPROM: 1711 cmd = BGE_SEE_READ; 1712 break; 1713 1714 case BGE_NVTYPE_UNBUFFERED_FLASH: 1715 case BGE_NVTYPE_BUFFERED_FLASH: 1716 cmd = BGE_FLASH_READ; 1717 break; 1718 } 1719 1720 addr = NVMEM_DATA_MAC_ADDRESS; 1721 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1722 return (0ULL); 1723 addr += 4; 1724 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1725 return (0ULL); 1726 1727 /* 1728 * The Broadcom chip is natively BIG-endian, so that's how the 1729 * MAC address is represented in NVmem. We may need to swap it 1730 * around on a little-endian host ... 1731 */ 1732 #ifdef _BIG_ENDIAN 1733 mac = mac_high; 1734 mac = mac << 32; 1735 mac |= mac_low; 1736 #else 1737 mac = BGE_BSWAP_32(mac_high); 1738 mac = mac << 32; 1739 mac |= BGE_BSWAP_32(mac_low); 1740 #endif /* _BIG_ENDIAN */ 1741 1742 return (mac); 1743 } 1744 1745 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1746 1747 /* 1748 * Dummy version for when we're not supporting NVmem access 1749 */ 1750 static uint64_t bge_get_nvmac(bge_t *bgep); 1751 #pragma inline(bge_get_nvmac) 1752 1753 static uint64_t 1754 bge_get_nvmac(bge_t *bgep) 1755 { 1756 _NOTE(ARGUNUSED(bgep)) 1757 return (0ULL); 1758 } 1759 1760 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1761 1762 /* 1763 * Determine the type of NVmem that is (or may be) attached to this chip, 1764 */ 1765 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1766 #pragma no_inline(bge_nvmem_id) 1767 1768 static enum bge_nvmem_type 1769 bge_nvmem_id(bge_t *bgep) 1770 { 1771 enum bge_nvmem_type nvtype; 1772 uint32_t config1; 1773 1774 BGE_TRACE(("bge_nvmem_id($%p)", 1775 (void *)bgep)); 1776 1777 switch (bgep->chipid.device) { 1778 default: 1779 /* 1780 * We shouldn't get here; it means we don't recognise 1781 * the chip, which means we don't know how to determine 1782 * what sort of NVmem (if any) it has. So we'll say 1783 * NONE, to disable the NVmem access code ... 1784 */ 1785 nvtype = BGE_NVTYPE_NONE; 1786 break; 1787 1788 case DEVICE_ID_5700: 1789 case DEVICE_ID_5700x: 1790 case DEVICE_ID_5701: 1791 /* 1792 * These devices support *only* SEEPROMs 1793 */ 1794 nvtype = BGE_NVTYPE_SEEPROM; 1795 break; 1796 1797 case DEVICE_ID_5702: 1798 case DEVICE_ID_5702fe: 1799 case DEVICE_ID_5703C: 1800 case DEVICE_ID_5703S: 1801 case DEVICE_ID_5704C: 1802 case DEVICE_ID_5704S: 1803 case DEVICE_ID_5704: 1804 case DEVICE_ID_5705M: 1805 case DEVICE_ID_5705C: 1806 case DEVICE_ID_5706: 1807 case DEVICE_ID_5782: 1808 case DEVICE_ID_5788: 1809 case DEVICE_ID_5751: 1810 case DEVICE_ID_5751M: 1811 case DEVICE_ID_5721: 1812 case DEVICE_ID_5714C: 1813 case DEVICE_ID_5714S: 1814 case DEVICE_ID_5715C: 1815 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1816 if (config1 & NVM_CFG1_FLASH_MODE) 1817 if (config1 & NVM_CFG1_BUFFERED_MODE) 1818 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1819 else 1820 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1821 else 1822 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1823 break; 1824 } 1825 1826 return (nvtype); 1827 } 1828 1829 #undef BGE_DBG 1830 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1831 1832 static void 1833 bge_init_recv_rule(bge_t *bgep) 1834 { 1835 bge_recv_rule_t *rulep; 1836 uint32_t i; 1837 1838 /* 1839 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1840 * 1. to direct UDP traffic, set: 1841 * rulep->control = RULE_PROTO_CONTROL; 1842 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1843 * 2. to direct ICMP traffic, set: 1844 * rulep->control = RULE_PROTO_CONTROL; 1845 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1846 * 3. to direct traffic by source ip, set: 1847 * rulep->control = RULE_SIP_CONTROL; 1848 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1849 */ 1850 rulep = bgep->recv_rules; 1851 rulep->control = RULE_PROTO_CONTROL; 1852 rulep->mask_value = RULE_TCP_MASK_VALUE; 1853 1854 /* 1855 * set receive rule registers 1856 */ 1857 rulep = bgep->recv_rules; 1858 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1859 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1860 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1861 } 1862 } 1863 1864 /* 1865 * Using the values captured by bge_chip_cfg_init(), and additional probes 1866 * as required, characterise the chip fully: determine the label by which 1867 * to refer to this chip, the correct settings for various registers, and 1868 * of course whether the device and/or subsystem are supported! 1869 */ 1870 int bge_chip_id_init(bge_t *bgep); 1871 #pragma no_inline(bge_chip_id_init) 1872 1873 int 1874 bge_chip_id_init(bge_t *bgep) 1875 { 1876 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1877 boolean_t sys_ok; 1878 boolean_t dev_ok; 1879 chip_id_t *cidp; 1880 uint32_t subid; 1881 char *devname; 1882 char *sysname; 1883 int *ids; 1884 int err; 1885 uint_t i; 1886 1887 ASSERT(bgep->bge_chip_state == BGE_CHIP_INITIAL); 1888 1889 sys_ok = dev_ok = B_FALSE; 1890 cidp = &bgep->chipid; 1891 1892 /* 1893 * Check the PCI device ID to determine the generic chip type and 1894 * select parameters that depend on this. 1895 * 1896 * Note: because the SPARC platforms in general don't fit the 1897 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1898 * as zero - which is why we use <asic_rev> rather than <revision> 1899 * below ... 1900 * 1901 * Note: in general we can't distinguish between the Copper/SerDes 1902 * versions by ID alone, as some Copper devices (e.g. some but not 1903 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1904 * treat them the same here, and the MII code works out the media 1905 * type later on ... 1906 */ 1907 cidp->mbuf_base = bge_mbuf_pool_base; 1908 cidp->mbuf_length = bge_mbuf_pool_len; 1909 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1910 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1911 cidp->pci_type = BGE_PCI_X; 1912 cidp->statistic_type = BGE_STAT_BLK; 1913 1914 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1915 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1916 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1917 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1918 1919 cidp->msi_enabled = B_FALSE; 1920 1921 switch (cidp->device) { 1922 case DEVICE_ID_5700: 1923 case DEVICE_ID_5700x: 1924 cidp->chip_label = 5700; 1925 cidp->flags |= CHIP_FLAG_NO_CSUM; 1926 break; 1927 1928 case DEVICE_ID_5701: 1929 cidp->chip_label = 5701; 1930 dev_ok = B_TRUE; 1931 cidp->flags |= CHIP_FLAG_NO_CSUM; 1932 break; 1933 1934 case DEVICE_ID_5702: 1935 case DEVICE_ID_5702fe: 1936 cidp->chip_label = 5702; 1937 dev_ok = B_TRUE; 1938 cidp->flags |= CHIP_FLAG_NO_CSUM; /* for now */ 1939 break; 1940 1941 case DEVICE_ID_5703C: 1942 case DEVICE_ID_5703S: 1943 case DEVICE_ID_5703: 1944 /* 1945 * Revision A0 of the 5703/5793 had various errata 1946 * that we can't or don't work around, so it's not 1947 * supported, but all later versions are 1948 */ 1949 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 1950 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 1951 dev_ok = B_TRUE; 1952 break; 1953 1954 case DEVICE_ID_5704C: 1955 case DEVICE_ID_5704S: 1956 case DEVICE_ID_5704: 1957 /* 1958 * Revision A0 of the 5704/5794 had various errata 1959 * but we have workarounds, so it *is* supported. 1960 */ 1961 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 1962 cidp->mbuf_base = bge_mbuf_pool_base_5704; 1963 cidp->mbuf_length = bge_mbuf_pool_len_5704; 1964 dev_ok = B_TRUE; 1965 break; 1966 1967 case DEVICE_ID_5705C: 1968 case DEVICE_ID_5705M: 1969 case DEVICE_ID_5705MA3: 1970 case DEVICE_ID_5705F: 1971 cidp->chip_label = 5705; 1972 cidp->mbuf_base = bge_mbuf_pool_base_5705; 1973 cidp->mbuf_length = bge_mbuf_pool_len_5705; 1974 cidp->recv_slots = BGE_RECV_SLOTS_5705; 1975 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 1976 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 1977 cidp->flags |= CHIP_FLAG_NO_JUMBO; 1978 cidp->statistic_type = BGE_STAT_REG; 1979 dev_ok = B_TRUE; 1980 break; 1981 1982 case DEVICE_ID_5706: 1983 cidp->chip_label = 5706; 1984 cidp->flags |= CHIP_FLAG_NO_JUMBO; 1985 cidp->flags |= CHIP_FLAG_NO_CSUM; /* for now */ 1986 break; 1987 1988 case DEVICE_ID_5782: 1989 /* 1990 * Apart from the label, we treat this as a 5705(?) 1991 */ 1992 cidp->chip_label = 5782; 1993 cidp->mbuf_base = bge_mbuf_pool_base_5705; 1994 cidp->mbuf_length = bge_mbuf_pool_len_5705; 1995 cidp->recv_slots = BGE_RECV_SLOTS_5705; 1996 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 1997 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 1998 cidp->flags |= CHIP_FLAG_NO_JUMBO; 1999 cidp->statistic_type = BGE_STAT_REG; 2000 dev_ok = B_TRUE; 2001 break; 2002 2003 case DEVICE_ID_5788: 2004 /* 2005 * Apart from the label, we treat this as a 5705(?) 2006 */ 2007 cidp->chip_label = 5788; 2008 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2009 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2010 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2011 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2012 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2013 cidp->statistic_type = BGE_STAT_REG; 2014 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2015 dev_ok = B_TRUE; 2016 break; 2017 2018 case DEVICE_ID_5714C: 2019 if (cidp->revision >= REVISION_ID_5714_A2) 2020 cidp->msi_enabled = bge_enable_msi; 2021 /* FALLTHRU */ 2022 case DEVICE_ID_5714S: 2023 cidp->chip_label = 5714; 2024 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2025 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2026 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2027 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2028 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2029 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2030 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2031 cidp->pci_type = BGE_PCI_E; 2032 cidp->statistic_type = BGE_STAT_REG; 2033 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2034 dev_ok = B_TRUE; 2035 break; 2036 2037 case DEVICE_ID_5715C: 2038 cidp->chip_label = 5715; 2039 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2040 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2041 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2042 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2043 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2044 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2045 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2046 cidp->pci_type = BGE_PCI_E; 2047 cidp->statistic_type = BGE_STAT_REG; 2048 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2049 dev_ok = B_TRUE; 2050 break; 2051 2052 case DEVICE_ID_5721: 2053 cidp->chip_label = 5721; 2054 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2055 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2056 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2057 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2058 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2059 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2060 cidp->pci_type = BGE_PCI_E; 2061 cidp->statistic_type = BGE_STAT_REG; 2062 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2063 dev_ok = B_TRUE; 2064 break; 2065 2066 case DEVICE_ID_5751: 2067 case DEVICE_ID_5751M: 2068 cidp->chip_label = 5751; 2069 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2070 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2071 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2072 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2073 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2074 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2075 cidp->pci_type = BGE_PCI_E; 2076 cidp->statistic_type = BGE_STAT_REG; 2077 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2078 dev_ok = B_TRUE; 2079 break; 2080 2081 } 2082 2083 /* 2084 * Setup the default jumbo parameter. 2085 */ 2086 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 2087 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 2088 cidp->mbuf_hi_water = bge_mbuf_hi_water; 2089 cidp->ethmax_size = ETHERMAX; 2090 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2091 2092 /* 2093 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2094 * setup below jumbo specific parameters. 2095 */ 2096 if (bge_jumbo_enable && 2097 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2098 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2099 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2100 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_JUMBO; 2101 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_JUMBO; 2102 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2103 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2104 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2105 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2106 cidp->ethmax_size = cidp->default_mtu + 2107 sizeof (struct ether_header); 2108 } 2109 2110 /* 2111 * Identify the NV memory type: SEEPROM or Flash? 2112 */ 2113 cidp->nvtype = bge_nvmem_id(bgep); 2114 2115 /* 2116 * Now, we want to check whether this device is part of a 2117 * supported subsystem (e.g., on the motherboard of a Sun 2118 * branded platform). 2119 * 2120 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2121 */ 2122 if (cidp->subven == VENDOR_ID_SUN) 2123 sys_ok = B_TRUE; 2124 2125 /* 2126 * Rule 2: If it's on the list on known subsystems, then it's OK. 2127 * Note: 0x14e41647 should *not* appear in the list, but the code 2128 * doesn't enforce that. 2129 */ 2130 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2131 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2132 if (err == DDI_PROP_SUCCESS) { 2133 /* 2134 * Got the list; scan for a matching subsystem vendor/device 2135 */ 2136 subid = (cidp->subven << 16) | cidp->subdev; 2137 while (i--) 2138 if (ids[i] == subid) 2139 sys_ok = B_TRUE; 2140 ddi_prop_free(ids); 2141 } 2142 2143 /* 2144 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2145 * 2146 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2147 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2148 * we have to check specially for the exact device paths to the 2149 * motherboard devices on those platforms ;-( 2150 * 2151 * Note: we can't just use the "supported-subsystems" mechanism 2152 * above, because the entry would have to be 0x14e41647 -- which 2153 * would then accept *any* plugin card that *didn't* contain a 2154 * (valid) SEEPROM ;-( 2155 */ 2156 sysname = ddi_node_name(ddi_root_node()); 2157 devname = ddi_pathname(bgep->devinfo, buf); 2158 ASSERT(strlen(devname) > 0); 2159 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2160 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2161 sys_ok = B_TRUE; 2162 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2163 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2164 sys_ok = B_TRUE; 2165 2166 /* 2167 * Now check what we've discovered: is this truly a supported 2168 * chip on (the motherboard of) a supported platform? 2169 * 2170 * Possible problems here: 2171 * 1) it's a completely unheard-of chip (e.g. 5761) 2172 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2173 * 3) it's a chip we would support if it were on the motherboard 2174 * of a Sun platform, but this one isn't ;-( 2175 */ 2176 if (cidp->chip_label == 0) 2177 bge_problem(bgep, 2178 "Device 'pci%04x,%04x' not recognized (%d?)", 2179 cidp->vendor, cidp->device, cidp->device); 2180 else if (!dev_ok) 2181 bge_problem(bgep, 2182 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2183 cidp->vendor, cidp->device, cidp->chip_label, 2184 cidp->revision); 2185 #if BGE_DEBUGGING 2186 else if (!sys_ok) 2187 bge_problem(bgep, 2188 "%d-based subsystem 'pci%04x,%04x' not validated", 2189 cidp->chip_label, cidp->subven, cidp->subdev); 2190 #endif 2191 else 2192 cidp->flags |= CHIP_FLAG_SUPPORTED; 2193 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2194 return (EIO); 2195 return (0); 2196 } 2197 2198 void 2199 bge_chip_msi_trig(bge_t *bgep) 2200 { 2201 uint32_t regval; 2202 2203 regval = bgep->param_msi_cnt<<4; 2204 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2205 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2206 } 2207 2208 /* 2209 * Various registers that control the chip's internal engines (state 2210 * machines) have a <reset> and <enable> bits (fortunately, in the 2211 * same place in each such register :-). 2212 * 2213 * To reset the state machine, the <reset> bit must be written with 1; 2214 * it will then read back as 1 while the reset is in progress, but 2215 * self-clear to 0 when the reset completes. 2216 * 2217 * To enable a state machine, one must set the <enable> bit, which 2218 * will continue to read back as 0 until the state machine is running. 2219 * 2220 * To disable a state machine, the <enable> bit must be cleared, but 2221 * it will continue to read back as 1 until the state machine actually 2222 * stops. 2223 * 2224 * This routine implements polling for completion of a reset, enable 2225 * or disable operation, returning B_TRUE on success (bit reached the 2226 * required state) or B_FALSE on timeout (200*100us == 20ms). 2227 */ 2228 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2229 uint32_t mask, uint32_t val); 2230 #pragma no_inline(bge_chip_poll_engine) 2231 2232 static boolean_t 2233 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2234 uint32_t mask, uint32_t val) 2235 { 2236 uint32_t regval; 2237 uint32_t n; 2238 2239 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2240 (void *)bgep, regno, mask, val)); 2241 2242 for (n = 200; n; --n) { 2243 regval = bge_reg_get32(bgep, regno); 2244 if ((regval & mask) == val) 2245 return (B_TRUE); 2246 drv_usecwait(100); 2247 } 2248 2249 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2250 return (B_FALSE); 2251 } 2252 2253 /* 2254 * Various registers that control the chip's internal engines (state 2255 * machines) have a <reset> bit (fortunately, in the same place in 2256 * each such register :-). To reset the state machine, this bit must 2257 * be written with 1; it will then read back as 1 while the reset is 2258 * in progress, but self-clear to 0 when the reset completes. 2259 * 2260 * This code sets the bit, then polls for it to read back as zero. 2261 * The return value is B_TRUE on success (reset bit cleared itself), 2262 * or B_FALSE if the state machine didn't recover :( 2263 * 2264 * NOTE: the Core reset is similar to other resets, except that we 2265 * can't poll for completion, since the Core reset disables memory 2266 * access! So we just have to assume that it will all complete in 2267 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2268 */ 2269 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2270 #pragma no_inline(bge_chip_reset_engine) 2271 2272 static boolean_t 2273 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2274 { 2275 uint32_t regval; 2276 uint32_t val32; 2277 2278 regval = bge_reg_get32(bgep, regno); 2279 2280 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2281 (void *)bgep, regno)); 2282 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2283 regno, regval)); 2284 2285 regval |= STATE_MACHINE_RESET_BIT; 2286 2287 switch (regno) { 2288 case MISC_CONFIG_REG: 2289 /* 2290 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2291 * resetting PCIE block and bringing PCIE link down, bit 29 2292 * in the register needs to be set first, and then set it again 2293 * while the reset bit is written. 2294 * See:P500 of 57xx-PG102-RDS.pdf. 2295 */ 2296 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2297 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2298 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2299 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2300 if (bgep->chipid.pci_type == BGE_PCI_E) { 2301 if (bgep->chipid.asic_rev == 2302 MHCR_CHIP_REV_5751_A0 || 2303 bgep->chipid.asic_rev == 2304 MHCR_CHIP_REV_5721_A0) { 2305 val32 = bge_reg_get32(bgep, 2306 PHY_TEST_CTRL_REG); 2307 if (val32 == (PHY_PCIE_SCRAM_MODE | 2308 PHY_PCIE_LTASS_MODE)) 2309 bge_reg_put32(bgep, 2310 PHY_TEST_CTRL_REG, 2311 PHY_PCIE_SCRAM_MODE); 2312 val32 = pci_config_get32 2313 (bgep->cfg_handle, 2314 PCI_CONF_BGE_CLKCTL); 2315 val32 |= CLKCTL_PCIE_A0_FIX; 2316 pci_config_put32(bgep->cfg_handle, 2317 PCI_CONF_BGE_CLKCTL, val32); 2318 } 2319 bge_reg_set32(bgep, regno, 2320 MISC_CONFIG_GRC_RESET_DISABLE); 2321 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2322 } 2323 } 2324 2325 /* 2326 * Special case - causes Core reset 2327 * 2328 * On SPARC v9 we want to ensure that we don't start 2329 * timing until the I/O access has actually reached 2330 * the chip, otherwise we might make the next access 2331 * too early. And we can't just force the write out 2332 * by following it with a read (even to config space) 2333 * because that would cause the fault we're trying 2334 * to avoid. Hence the need for membar_sync() here. 2335 */ 2336 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2337 #ifdef __sparcv9 2338 membar_sync(); 2339 #endif /* __sparcv9 */ 2340 /* 2341 * On some platforms,system need about 300us for 2342 * link setup. 2343 */ 2344 drv_usecwait(300); 2345 2346 if (bgep->chipid.pci_type == BGE_PCI_E) { 2347 /* PCI-E device need more reset time */ 2348 drv_usecwait(120000); 2349 2350 /* Set PCIE max payload size and clear error status. */ 2351 if (bgep->chipid.chip_label == 5721 || 2352 bgep->chipid.chip_label == 5751) { 2353 pci_config_put16(bgep->cfg_handle, 2354 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2355 pci_config_put16(bgep->cfg_handle, 2356 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2357 } 2358 } 2359 2360 BGE_PCICHK(bgep); 2361 return (B_TRUE); 2362 2363 default: 2364 bge_reg_put32(bgep, regno, regval); 2365 return (bge_chip_poll_engine(bgep, regno, 2366 STATE_MACHINE_RESET_BIT, 0)); 2367 } 2368 } 2369 2370 /* 2371 * Various registers that control the chip's internal engines (state 2372 * machines) have an <enable> bit (fortunately, in the same place in 2373 * each such register :-). To stop the state machine, this bit must 2374 * be written with 0, then polled to see when the state machine has 2375 * actually stopped. 2376 * 2377 * The return value is B_TRUE on success (enable bit cleared), or 2378 * B_FALSE if the state machine didn't stop :( 2379 */ 2380 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2381 uint32_t morebits); 2382 #pragma no_inline(bge_chip_disable_engine) 2383 2384 static boolean_t 2385 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2386 { 2387 uint32_t regval; 2388 2389 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2390 (void *)bgep, regno, morebits)); 2391 2392 switch (regno) { 2393 case FTQ_RESET_REG: 2394 /* 2395 * Not quite like the others; it doesn't 2396 * have an <enable> bit, but instead we 2397 * have to set and then clear all the bits 2398 */ 2399 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2400 drv_usecwait(100); 2401 bge_reg_put32(bgep, regno, 0); 2402 return (B_TRUE); 2403 2404 default: 2405 regval = bge_reg_get32(bgep, regno); 2406 regval &= ~STATE_MACHINE_ENABLE_BIT; 2407 regval &= ~morebits; 2408 bge_reg_put32(bgep, regno, regval); 2409 return (bge_chip_poll_engine(bgep, regno, 2410 STATE_MACHINE_ENABLE_BIT, 0)); 2411 } 2412 } 2413 2414 /* 2415 * Various registers that control the chip's internal engines (state 2416 * machines) have an <enable> bit (fortunately, in the same place in 2417 * each such register :-). To start the state machine, this bit must 2418 * be written with 1, then polled to see when the state machine has 2419 * actually started. 2420 * 2421 * The return value is B_TRUE on success (enable bit set), or 2422 * B_FALSE if the state machine didn't start :( 2423 */ 2424 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2425 uint32_t morebits); 2426 #pragma no_inline(bge_chip_enable_engine) 2427 2428 static boolean_t 2429 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2430 { 2431 uint32_t regval; 2432 2433 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2434 (void *)bgep, regno, morebits)); 2435 2436 switch (regno) { 2437 case FTQ_RESET_REG: 2438 /* 2439 * Not quite like the others; it doesn't 2440 * have an <enable> bit, but instead we 2441 * have to set and then clear all the bits 2442 */ 2443 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2444 drv_usecwait(100); 2445 bge_reg_put32(bgep, regno, 0); 2446 return (B_TRUE); 2447 2448 default: 2449 regval = bge_reg_get32(bgep, regno); 2450 regval |= STATE_MACHINE_ENABLE_BIT; 2451 regval |= morebits; 2452 bge_reg_put32(bgep, regno, regval); 2453 return (bge_chip_poll_engine(bgep, regno, 2454 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2455 } 2456 } 2457 2458 /* 2459 * Reprogram the Ethernet, Transmit, and Receive MAC 2460 * modes to match the param_* variables 2461 */ 2462 static void bge_sync_mac_modes(bge_t *bgep); 2463 #pragma no_inline(bge_sync_mac_modes) 2464 2465 static void 2466 bge_sync_mac_modes(bge_t *bgep) 2467 { 2468 uint32_t macmode; 2469 uint32_t regval; 2470 2471 ASSERT(mutex_owned(bgep->genlock)); 2472 2473 /* 2474 * Reprogram the Ethernet MAC mode ... 2475 */ 2476 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2477 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2478 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2479 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2480 else 2481 macmode |= ETHERNET_MODE_LINK_POLARITY; 2482 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2483 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2484 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2485 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2486 else if (bgep->param_link_speed == 10 || bgep->param_link_speed == 100) 2487 macmode |= ETHERNET_MODE_PORTMODE_MII; 2488 else 2489 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2490 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2491 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2492 else 2493 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2494 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2495 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2496 else 2497 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2498 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2499 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2500 (void *)bgep, regval, macmode)); 2501 2502 /* 2503 * ... the Transmit MAC mode ... 2504 */ 2505 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2506 if (bgep->param_link_tx_pause) 2507 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2508 else 2509 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2510 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2511 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2512 (void *)bgep, regval, macmode)); 2513 2514 /* 2515 * ... and the Receive MAC mode 2516 */ 2517 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2518 if (bgep->param_link_rx_pause) 2519 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2520 else 2521 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2522 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2523 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2524 (void *)bgep, regval, macmode)); 2525 } 2526 2527 /* 2528 * bge_chip_sync() -- program the chip with the unicast MAC address, 2529 * the multicast hash table, the required level of promiscuity, and 2530 * the current loopback mode ... 2531 */ 2532 #ifdef BGE_IPMI_ASF 2533 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2534 #else 2535 int bge_chip_sync(bge_t *bgep); 2536 #endif 2537 #pragma no_inline(bge_chip_sync) 2538 2539 int 2540 #ifdef BGE_IPMI_ASF 2541 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2542 #else 2543 bge_chip_sync(bge_t *bgep) 2544 #endif 2545 { 2546 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2547 boolean_t promisc; 2548 uint64_t macaddr; 2549 uint32_t fill; 2550 int i; 2551 int retval = DDI_SUCCESS; 2552 2553 BGE_TRACE(("bge_chip_sync($%p)", 2554 (void *)bgep)); 2555 2556 ASSERT(mutex_owned(bgep->genlock)); 2557 2558 promisc = B_FALSE; 2559 fill = ~(uint32_t)0; 2560 2561 if (bgep->promisc) 2562 promisc = B_TRUE; 2563 else 2564 fill = (uint32_t)0; 2565 2566 /* 2567 * If the TX/RX MAC engines are already running, we should stop 2568 * them (and reset the RX engine) before changing the parameters. 2569 * If they're not running, this will have no effect ... 2570 * 2571 * NOTE: this is currently disabled by default because stopping 2572 * and restarting the Tx engine may cause an outgoing packet in 2573 * transit to be truncated. Also, stopping and restarting the 2574 * Rx engine seems to not work correctly on the 5705. Testing 2575 * has not (yet!) revealed any problems with NOT stopping and 2576 * restarting these engines (and Broadcom say their drivers don't 2577 * do this), but if it is found to cause problems, this variable 2578 * can be patched to re-enable the old behaviour ... 2579 */ 2580 if (bge_stop_start_on_sync) { 2581 #ifdef BGE_IPMI_ASF 2582 if (!bgep->asf_enabled) { 2583 if (!bge_chip_disable_engine(bgep, 2584 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2585 retval = DDI_FAILURE; 2586 } else { 2587 if (!bge_chip_disable_engine(bgep, 2588 RECEIVE_MAC_MODE_REG, 0)) 2589 retval = DDI_FAILURE; 2590 } 2591 #else 2592 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2593 RECEIVE_MODE_KEEP_VLAN_TAG)) 2594 retval = DDI_FAILURE; 2595 #endif 2596 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2597 retval = DDI_FAILURE; 2598 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2599 retval = DDI_FAILURE; 2600 } 2601 2602 /* 2603 * Reprogram the hashed multicast address table ... 2604 */ 2605 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2606 bge_reg_put32(bgep, MAC_HASH_REG(i), 2607 bgep->mcast_hash[i] | fill); 2608 2609 #ifdef BGE_IPMI_ASF 2610 if (!bgep->asf_enabled || !asf_keeplive) { 2611 #endif 2612 /* 2613 * Transform the MAC address from host to chip format, then 2614 * reprogram the transmit random backoff seed and the unicast 2615 * MAC address(es) ... 2616 */ 2617 for (i = 0, fill = 0, macaddr = 0ull; i < ETHERADDRL; ++i) { 2618 macaddr <<= 8; 2619 macaddr |= bgep->curr_addr.addr[i]; 2620 fill += bgep->curr_addr.addr[i]; 2621 } 2622 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2623 for (i = 0; i < MAC_ADDRESS_REGS_MAX; ++i) 2624 bge_reg_put64(bgep, MAC_ADDRESS_REG(i), macaddr); 2625 2626 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2627 (void *)bgep, macaddr)); 2628 #ifdef BGE_IPMI_ASF 2629 } 2630 #endif 2631 2632 /* 2633 * Set or clear the PROMISCUOUS mode bit 2634 */ 2635 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2636 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2637 2638 /* 2639 * Sync the rest of the MAC modes too ... 2640 */ 2641 bge_sync_mac_modes(bgep); 2642 2643 /* 2644 * Restart RX/TX MAC engines if required ... 2645 */ 2646 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2647 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2648 retval = DDI_FAILURE; 2649 #ifdef BGE_IPMI_ASF 2650 if (!bgep->asf_enabled) { 2651 if (!bge_chip_enable_engine(bgep, 2652 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2653 retval = DDI_FAILURE; 2654 } else { 2655 if (!bge_chip_enable_engine(bgep, 2656 RECEIVE_MAC_MODE_REG, 0)) 2657 retval = DDI_FAILURE; 2658 } 2659 #else 2660 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2661 RECEIVE_MODE_KEEP_VLAN_TAG)) 2662 retval = DDI_FAILURE; 2663 #endif 2664 } 2665 return (retval); 2666 } 2667 2668 /* 2669 * This array defines the sequence of state machine control registers 2670 * in which the <enable> bit must be cleared to bring the chip to a 2671 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2672 */ 2673 static bge_regno_t shutdown_engine_regs[] = { 2674 RECEIVE_MAC_MODE_REG, 2675 RCV_BD_INITIATOR_MODE_REG, 2676 RCV_LIST_PLACEMENT_MODE_REG, 2677 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2678 RCV_DATA_BD_INITIATOR_MODE_REG, 2679 RCV_DATA_COMPLETION_MODE_REG, 2680 RCV_BD_COMPLETION_MODE_REG, 2681 2682 SEND_BD_SELECTOR_MODE_REG, 2683 SEND_BD_INITIATOR_MODE_REG, 2684 SEND_DATA_INITIATOR_MODE_REG, 2685 READ_DMA_MODE_REG, 2686 SEND_DATA_COMPLETION_MODE_REG, 2687 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2688 SEND_BD_COMPLETION_MODE_REG, 2689 TRANSMIT_MAC_MODE_REG, 2690 2691 HOST_COALESCE_MODE_REG, 2692 WRITE_DMA_MODE_REG, 2693 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2694 FTQ_RESET_REG, /* special - see code */ 2695 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2696 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2697 BGE_REGNO_NONE /* terminator */ 2698 }; 2699 2700 /* 2701 * bge_chip_stop() -- stop all chip processing 2702 * 2703 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2704 * we've detected a problem internally; otherwise, this is a normal 2705 * (clean) stop (at user request i.e. the last STREAM has been closed). 2706 */ 2707 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2708 #pragma no_inline(bge_chip_stop) 2709 2710 void 2711 bge_chip_stop(bge_t *bgep, boolean_t fault) 2712 { 2713 bge_regno_t regno; 2714 bge_regno_t *rbp; 2715 boolean_t ok; 2716 2717 BGE_TRACE(("bge_chip_stop($%p)", 2718 (void *)bgep)); 2719 2720 ASSERT(mutex_owned(bgep->genlock)); 2721 2722 rbp = shutdown_engine_regs; 2723 /* 2724 * When driver try to shutdown the BCM5705/5788/5721/5751/ 2725 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 2726 * -ory arbiter should not be disabled. 2727 */ 2728 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 2729 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2730 ok &= bge_chip_disable_engine(bgep, regno, 0); 2731 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 2732 (regno != DMA_COMPLETION_MODE_REG) && 2733 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 2734 (regno != BUFFER_MANAGER_MODE_REG) && 2735 (regno != MEMORY_ARBITER_MODE_REG)) 2736 ok &= bge_chip_disable_engine(bgep, 2737 regno, 0); 2738 } 2739 2740 if (!ok && !fault) 2741 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 2742 2743 /* 2744 * Finally, disable (all) MAC events & clear the MAC status 2745 */ 2746 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 2747 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 2748 2749 /* 2750 * if we're stopping the chip because of a detected fault then do 2751 * appropriate actions 2752 */ 2753 if (fault) { 2754 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 2755 bgep->bge_chip_state = BGE_CHIP_FAULT; 2756 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2757 if (bgep->bge_dma_error) { 2758 /* 2759 * need to free buffers in case the fault was 2760 * due to a memory error in a buffer - got to 2761 * do a fair bit of tidying first 2762 */ 2763 if (bgep->progress & PROGRESS_KSTATS) { 2764 bge_fini_kstats(bgep); 2765 bgep->progress &= ~PROGRESS_KSTATS; 2766 } 2767 if (bgep->progress & PROGRESS_INTR) { 2768 bge_intr_disable(bgep); 2769 rw_enter(bgep->errlock, RW_WRITER); 2770 bge_fini_rings(bgep); 2771 rw_exit(bgep->errlock); 2772 bgep->progress &= ~PROGRESS_INTR; 2773 } 2774 if (bgep->progress & PROGRESS_BUFS) { 2775 bge_free_bufs(bgep); 2776 bgep->progress &= ~PROGRESS_BUFS; 2777 } 2778 bgep->bge_dma_error = B_FALSE; 2779 } 2780 } 2781 } else 2782 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2783 } 2784 2785 /* 2786 * Poll for completion of chip's ROM firmware; also, at least on the 2787 * first time through, find and return the hardware MAC address, if any. 2788 */ 2789 static uint64_t bge_poll_firmware(bge_t *bgep); 2790 #pragma no_inline(bge_poll_firmware) 2791 2792 static uint64_t 2793 bge_poll_firmware(bge_t *bgep) 2794 { 2795 uint64_t magic; 2796 uint64_t mac; 2797 uint32_t gen; 2798 uint32_t i; 2799 2800 /* 2801 * Step 18: put the T3_MAGIC_NUMBER into the GENCOMM port 2802 * 2803 * Step 19: poll for firmware completion (GENCOMM port set 2804 * to the ones complement of T3_MAGIC_NUMBER). 2805 * 2806 * While we're at it, we also read the MAC address register; 2807 * at some stage the the firmware will load this with the 2808 * factory-set value. 2809 * 2810 * When both the magic number and the MAC address are set, 2811 * we're done; but we impose a time limit of one second 2812 * (1000*1000us) in case the firmware fails in some fashion 2813 * or the SEEPROM that provides that MAC address isn't fitted. 2814 * 2815 * After the first time through (chip state != INITIAL), we 2816 * don't need the MAC address to be set (we've already got it 2817 * or not, from the first time), so we don't wait for it, but 2818 * we still have to wait for the T3_MAGIC_NUMBER. 2819 * 2820 * Note: the magic number is only a 32-bit quantity, but the NIC 2821 * memory is 64-bit (and big-endian) internally. Addressing the 2822 * GENCOMM word as "the upper half of a 64-bit quantity" makes 2823 * it work correctly on both big- and little-endian hosts. 2824 */ 2825 #ifdef BGE_IPMI_ASF 2826 if (!bgep->asf_enabled) { 2827 #endif 2828 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 2829 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 2830 BGE_DEBUG(("bge_poll_firmware: put T3 magic 0x%llx in GENCOMM" 2831 " 0x%lx", magic, NIC_MEM_GENCOMM)); 2832 #ifdef BGE_IPMI_ASF 2833 } 2834 #endif 2835 2836 for (i = 0; i < 1000; ++i) { 2837 drv_usecwait(1000); 2838 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 2839 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 2840 #ifdef BGE_IPMI_ASF 2841 if (!bgep->asf_enabled) { 2842 #endif 2843 if (gen != ~T3_MAGIC_NUMBER) 2844 continue; 2845 #ifdef BGE_IPMI_ASF 2846 } 2847 #endif 2848 if (mac != 0ULL) 2849 break; 2850 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 2851 break; 2852 } 2853 2854 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 2855 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 2856 (void *)bgep, gen, i)); 2857 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 2858 mac, magic)); 2859 2860 return (mac); 2861 } 2862 2863 #ifdef BGE_IPMI_ASF 2864 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 2865 #else 2866 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 2867 #endif 2868 #pragma no_inline(bge_chip_reset) 2869 2870 int 2871 #ifdef BGE_IPMI_ASF 2872 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 2873 #else 2874 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 2875 #endif 2876 { 2877 chip_id_t chipid; 2878 uint64_t mac; 2879 uint32_t modeflags; 2880 uint32_t mhcr; 2881 uint32_t sx0; 2882 uint32_t i; 2883 #ifdef BGE_IPMI_ASF 2884 uint32_t mailbox; 2885 #endif 2886 int retval = DDI_SUCCESS; 2887 2888 BGE_TRACE(("bge_chip_reset($%p, %d)", 2889 (void *)bgep, enable_dma)); 2890 2891 ASSERT(mutex_owned(bgep->genlock)); 2892 2893 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 2894 (void *)bgep, enable_dma, bgep->bge_chip_state)); 2895 2896 /* 2897 * Do we need to stop the chip cleanly before resetting? 2898 */ 2899 switch (bgep->bge_chip_state) { 2900 default: 2901 _NOTE(NOTREACHED) 2902 return (DDI_FAILURE); 2903 2904 case BGE_CHIP_INITIAL: 2905 case BGE_CHIP_STOPPED: 2906 case BGE_CHIP_RESET: 2907 break; 2908 2909 case BGE_CHIP_RUNNING: 2910 case BGE_CHIP_ERROR: 2911 case BGE_CHIP_FAULT: 2912 bge_chip_stop(bgep, B_FALSE); 2913 break; 2914 } 2915 2916 #ifdef BGE_IPMI_ASF 2917 if (bgep->asf_enabled) { 2918 if (asf_mode == ASF_MODE_INIT) { 2919 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 2920 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 2921 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 2922 } 2923 } 2924 #endif 2925 /* 2926 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 2927 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 2928 * 2929 * Before reset Core clock,it is 2930 * also required to initialize the Memory Arbiter as specified in step9 2931 * and Misc Host Control Register as specified in step-13 2932 * Step 4-5: reset Core clock & wait for completion 2933 * Steps 6-8: are done by bge_chip_cfg_init() 2934 */ 2935 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 2936 retval = DDI_FAILURE; 2937 2938 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 2939 MHCR_ENABLE_TAGGED_STATUS_MODE | 2940 MHCR_MASK_INTERRUPT_MODE | 2941 MHCR_MASK_PCI_INT_OUTPUT | 2942 MHCR_CLEAR_INTERRUPT_INTA; 2943 #ifdef _BIG_ENDIAN 2944 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 2945 #endif /* _BIG_ENDIAN */ 2946 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 2947 #ifdef BGE_IPMI_ASF 2948 if (bgep->asf_enabled) 2949 bgep->asf_wordswapped = B_FALSE; 2950 #endif 2951 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 2952 retval = DDI_FAILURE; 2953 bge_chip_cfg_init(bgep, &chipid, enable_dma); 2954 2955 /* 2956 * Step 8a: This may belong elsewhere, but BCM5721 needs 2957 * a bit set to avoid a fifo overflow/underflow bug. 2958 */ 2959 if (bgep->chipid.chip_label == 5721 || bgep->chipid.chip_label == 5751) 2960 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 2961 2962 2963 /* 2964 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 2965 * not be changed. 2966 */ 2967 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 2968 retval = DDI_FAILURE; 2969 2970 /* 2971 * Steps 10-11: configure PIO endianness options and 2972 * enable indirect register access -- already done 2973 * Steps 12-13: enable writing to the PCI state & clock 2974 * control registers -- not required; we aren't going to 2975 * use those features. 2976 * Steps 14-15: Configure DMA endianness options. See 2977 * the comments on the setting of the MHCR above. 2978 */ 2979 #ifdef _BIG_ENDIAN 2980 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 2981 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 2982 #else 2983 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 2984 #endif /* _BIG_ENDIAN */ 2985 #ifdef BGE_IPMI_ASF 2986 if (bgep->asf_enabled) 2987 modeflags |= MODE_HOST_STACK_UP; 2988 #endif 2989 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 2990 2991 #ifdef BGE_IPMI_ASF 2992 if (bgep->asf_enabled) { 2993 if (asf_mode != ASF_MODE_NONE) { 2994 /* Wait for NVRAM init */ 2995 i = 0; 2996 drv_usecwait(5000); 2997 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 2998 while ((mailbox != (uint32_t) 2999 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3000 (i < 10000)) { 3001 drv_usecwait(100); 3002 mailbox = bge_nic_get32(bgep, 3003 BGE_FIRMWARE_MAILBOX); 3004 i++; 3005 } 3006 if (!bgep->asf_newhandshake) { 3007 if ((asf_mode == ASF_MODE_INIT) || 3008 (asf_mode == ASF_MODE_POST_INIT)) { 3009 3010 bge_asf_post_reset_old_mode(bgep, 3011 BGE_INIT_RESET); 3012 } else { 3013 bge_asf_post_reset_old_mode(bgep, 3014 BGE_SHUTDOWN_RESET); 3015 } 3016 } 3017 } 3018 } 3019 #endif 3020 /* 3021 * Steps 16-17: poll for firmware completion 3022 */ 3023 mac = bge_poll_firmware(bgep); 3024 3025 /* 3026 * Step 18: enable external memory -- doesn't apply. 3027 * 3028 * However we take the opportunity to set the MLCR anyway, as 3029 * this register also controls the SEEPROM auto-access method 3030 * which we may want to use later ... 3031 * 3032 * The proper value here depends on the way the chip is wired 3033 * into the circuit board, as this register *also* controls which 3034 * of the "Miscellaneous I/O" pins are driven as outputs and the 3035 * values driven onto those pins! 3036 * 3037 * See also step 74 in the PRM ... 3038 */ 3039 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3040 bgep->chipid.bge_mlcr_default); 3041 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3042 3043 /* 3044 * Step 20: clear the Ethernet MAC mode register 3045 */ 3046 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3047 3048 /* 3049 * Step 21: restore cache-line-size, latency timer, and 3050 * subsystem ID registers to their original values (not 3051 * those read into the local structure <chipid>, 'cos 3052 * that was after they were cleared by the RESET). 3053 * 3054 * Note: the Subsystem Vendor/Device ID registers are not 3055 * directly writable in config space, so we use the shadow 3056 * copy in "Page Zero" of register space to restore them 3057 * both in one go ... 3058 */ 3059 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3060 bgep->chipid.clsize); 3061 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3062 bgep->chipid.latency); 3063 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3064 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3065 3066 /* 3067 * The SEND INDEX registers should be reset to zero by the 3068 * global chip reset; if they're not, there'll be trouble 3069 * later on. 3070 */ 3071 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3072 if (sx0 != 0) { 3073 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3074 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3075 return (DDI_FAILURE); 3076 } 3077 3078 /* Enable MSI code */ 3079 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3080 bge_reg_set32(bgep, MSI_MODE_REG, 3081 MSI_PRI_HIGHEST|MSI_MSI_ENABLE); 3082 3083 /* 3084 * On the first time through, save the factory-set MAC address 3085 * (if any). If bge_poll_firmware() above didn't return one 3086 * (from a chip register) consider looking in the attached NV 3087 * memory device, if any. Once we have it, we save it in both 3088 * register-image (64-bit) and byte-array forms. All-zero and 3089 * all-one addresses are not valid, and we refuse to stash those. 3090 */ 3091 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3092 if (mac == 0ULL) 3093 mac = bge_get_nvmac(bgep); 3094 if (mac != 0ULL && mac != ~0ULL) { 3095 bgep->chipid.hw_mac_addr = mac; 3096 for (i = ETHERADDRL; i-- != 0; ) { 3097 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3098 mac >>= 8; 3099 } 3100 bgep->chipid.vendor_addr.set = 1; 3101 } 3102 } 3103 3104 #ifdef BGE_IPMI_ASF 3105 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3106 if (asf_mode != ASF_MODE_NONE) { 3107 if ((asf_mode == ASF_MODE_INIT) || 3108 (asf_mode == ASF_MODE_POST_INIT)) { 3109 3110 bge_asf_post_reset_new_mode(bgep, 3111 BGE_INIT_RESET); 3112 } else { 3113 bge_asf_post_reset_new_mode(bgep, 3114 BGE_SHUTDOWN_RESET); 3115 } 3116 } 3117 } 3118 #endif 3119 3120 /* 3121 * Record the new state 3122 */ 3123 bgep->chip_resets += 1; 3124 bgep->bge_chip_state = BGE_CHIP_RESET; 3125 return (retval); 3126 } 3127 3128 /* 3129 * bge_chip_start() -- start the chip transmitting and/or receiving, 3130 * including enabling interrupts 3131 */ 3132 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3133 #pragma no_inline(bge_chip_start) 3134 3135 int 3136 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3137 { 3138 uint32_t coalmode; 3139 uint32_t ledctl; 3140 uint32_t mtu; 3141 uint32_t maxring; 3142 uint64_t ring; 3143 int retval = DDI_SUCCESS; 3144 3145 BGE_TRACE(("bge_chip_start($%p)", 3146 (void *)bgep)); 3147 3148 ASSERT(mutex_owned(bgep->genlock)); 3149 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3150 3151 /* 3152 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3153 * The document specifies 95 separate steps to fully 3154 * initialise the chip!!!! 3155 * 3156 * The reset code above has already got us as far as step 3157 * 21, so we continue with ... 3158 * 3159 * Step 22: clear the MAC statistics block 3160 * (0x0300-0x0aff in NIC-local memory) 3161 */ 3162 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3163 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3164 NIC_MEM_STATISTICS_SIZE); 3165 3166 /* 3167 * Step 23: clear the status block (in host memory) 3168 */ 3169 DMA_ZERO(bgep->status_block); 3170 3171 /* 3172 * Step 24: set DMA read/write control register 3173 */ 3174 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3175 bgep->chipid.bge_dma_rwctrl); 3176 3177 /* 3178 * Step 25: Configure DMA endianness -- already done (16/17) 3179 * Step 26: Configure Host-Based Send Rings 3180 * Step 27: Indicate Host Stack Up 3181 */ 3182 bge_reg_set32(bgep, MODE_CONTROL_REG, 3183 MODE_HOST_SEND_BDS | 3184 MODE_HOST_STACK_UP); 3185 3186 /* 3187 * Step 28: Configure checksum options: 3188 * Solaris supports the hardware default checksum options. 3189 * 3190 * Workaround for Incorrect pseudo-header checksum calculation. 3191 */ 3192 if (bgep->macp->m_info.mi_cksum & HCKSUM_INET_PARTIAL) 3193 bge_reg_set32(bgep, MODE_CONTROL_REG, 3194 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3195 3196 /* 3197 * Step 29: configure Timer Prescaler. The value is always the 3198 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3199 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3200 * for the whole chip! 3201 */ 3202 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3203 3204 /* 3205 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3206 * 3207 * If the mbuf_length is specified as 0, we just leave these at 3208 * their hardware defaults, rather than explicitly setting them. 3209 * As the Broadcom HRM,driver better not change the parameters 3210 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3211 */ 3212 if ((bgep->chipid.mbuf_length != 0) && 3213 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3214 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3215 bgep->chipid.mbuf_base); 3216 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3217 bgep->chipid.mbuf_length); 3218 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3219 DMAD_POOL_BASE_DEFAULT); 3220 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3221 DMAD_POOL_LENGTH_DEFAULT); 3222 } 3223 3224 /* 3225 * Step 32: configure MAC memory pool watermarks 3226 */ 3227 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3228 bgep->chipid.mbuf_lo_water_rdma); 3229 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3230 bgep->chipid.mbuf_lo_water_rmac); 3231 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3232 bgep->chipid.mbuf_hi_water); 3233 3234 /* 3235 * Step 33: configure DMA resource watermarks 3236 */ 3237 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3238 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3239 bge_dmad_lo_water); 3240 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3241 bge_dmad_hi_water); 3242 } 3243 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3244 3245 /* 3246 * Steps 34-36: enable buffer manager & internal h/w queues 3247 */ 3248 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3249 STATE_MACHINE_ATTN_ENABLE_BIT)) 3250 retval = DDI_FAILURE; 3251 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3252 retval = DDI_FAILURE; 3253 3254 /* 3255 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3256 */ 3257 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3258 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3259 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3260 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3261 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3262 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3263 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3264 } 3265 3266 /* 3267 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3268 */ 3269 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3270 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3271 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3272 bge_replenish_jumbo); 3273 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3274 bge_replenish_mini); 3275 } 3276 3277 /* 3278 * Steps 41-43: clear Send Ring Producer Indices and initialise 3279 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3280 */ 3281 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3282 maxring = BGE_SEND_RINGS_MAX; 3283 else 3284 maxring = BGE_SEND_RINGS_MAX_5705; 3285 for (ring = 0; ring < maxring; ++ring) { 3286 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3287 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3288 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3289 &bgep->send[ring].hw_rcb); 3290 } 3291 3292 /* 3293 * Steps 44-45: initialise Receive Return Rings 3294 * (0x0200-0x02ff in NIC-local memory) 3295 */ 3296 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3297 maxring = BGE_RECV_RINGS_MAX; 3298 else 3299 maxring = BGE_RECV_RINGS_MAX_5705; 3300 for (ring = 0; ring < maxring; ++ring) 3301 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3302 &bgep->recv[ring].hw_rcb); 3303 3304 /* 3305 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3306 */ 3307 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3308 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3309 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3310 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3311 } 3312 /* 3313 * Step 47: configure the MAC unicast address 3314 * Step 48: configure the random backoff seed 3315 * Step 96: set up multicast filters 3316 */ 3317 #ifdef BGE_IPMI_ASF 3318 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3319 #else 3320 if (bge_chip_sync(bgep) == DDI_FAILURE) 3321 #endif 3322 retval = DDI_FAILURE; 3323 3324 /* 3325 * Step 49: configure the MTU 3326 */ 3327 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3328 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3329 3330 /* 3331 * Step 50: configure the IPG et al 3332 */ 3333 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3334 3335 /* 3336 * Step 51: configure the default Rx Return Ring 3337 */ 3338 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3339 3340 /* 3341 * Steps 52-54: configure Receive List Placement, 3342 * and enable Receive List Placement Statistics 3343 */ 3344 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3345 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3346 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3347 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3348 3349 if (bgep->chipid.rx_rings > 1) 3350 bge_init_recv_rule(bgep); 3351 3352 /* 3353 * Steps 55-56: enable Send Data Initiator Statistics 3354 */ 3355 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3356 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3357 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3358 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3359 } else { 3360 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3361 SEND_INIT_STATS_ENABLE); 3362 } 3363 /* 3364 * Steps 57-58: stop (?) the Host Coalescing Engine 3365 */ 3366 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3367 retval = DDI_FAILURE; 3368 3369 /* 3370 * Steps 59-62: initialise Host Coalescing parameters 3371 */ 3372 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3373 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3374 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3375 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3376 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3377 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3378 bge_tx_count_intr); 3379 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3380 bge_tx_ticks_intr); 3381 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3382 bge_rx_count_intr); 3383 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3384 bge_rx_ticks_intr); 3385 } 3386 3387 /* 3388 * Steps 63-64: initialise status block & statistics 3389 * host memory addresses 3390 * The statistic block does not exist in some chipsets 3391 * Step 65: initialise Statistics Coalescing Tick Counter 3392 */ 3393 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3394 bgep->status_block.cookie.dmac_laddress); 3395 3396 /* 3397 * Steps 66-67: initialise status block & statistics 3398 * NIC-local memory addresses 3399 */ 3400 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3401 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3402 bgep->statistics.cookie.dmac_laddress); 3403 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3404 STATISTICS_TICKS_DEFAULT); 3405 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3406 NIC_MEM_STATUS_BLOCK); 3407 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3408 NIC_MEM_STATISTICS); 3409 } 3410 3411 /* 3412 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3413 * Completion Engine, the Receive List Placement Engine, and the 3414 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3415 * and BCM5715. 3416 */ 3417 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3418 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3419 coalmode = COALESCE_64_BYTE_STATUS; 3420 else 3421 coalmode = 0; 3422 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3423 retval = DDI_FAILURE; 3424 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3425 STATE_MACHINE_ATTN_ENABLE_BIT)) 3426 retval = DDI_FAILURE; 3427 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3428 retval = DDI_FAILURE; 3429 3430 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3431 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3432 STATE_MACHINE_ATTN_ENABLE_BIT)) 3433 retval = DDI_FAILURE; 3434 3435 /* 3436 * Step 72: Enable MAC DMA engines 3437 * Step 73: Clear & enable MAC statistics 3438 */ 3439 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3440 ETHERNET_MODE_ENABLE_FHDE | 3441 ETHERNET_MODE_ENABLE_RDE | 3442 ETHERNET_MODE_ENABLE_TDE); 3443 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3444 ETHERNET_MODE_ENABLE_TX_STATS | 3445 ETHERNET_MODE_ENABLE_RX_STATS | 3446 ETHERNET_MODE_CLEAR_TX_STATS | 3447 ETHERNET_MODE_CLEAR_RX_STATS); 3448 3449 /* 3450 * Step 74: configure the MLCR (Miscellaneous Local Control 3451 * Register); not required, as we set up the MLCR in step 10 3452 * (part of the reset code) above. 3453 * 3454 * Step 75: clear Interrupt Mailbox 0 3455 */ 3456 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3457 3458 /* 3459 * Steps 76-87: Gentlemen, start your engines ... 3460 * 3461 * Enable the DMA Completion Engine, the Write DMA Engine, 3462 * the Read DMA Engine, Receive Data Completion Engine, 3463 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3464 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3465 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3466 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3467 * 3468 * Beware exhaust fumes? 3469 */ 3470 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3471 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3472 retval = DDI_FAILURE; 3473 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3474 (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3475 retval = DDI_FAILURE; 3476 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3477 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3478 retval = DDI_FAILURE; 3479 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3480 STATE_MACHINE_ATTN_ENABLE_BIT)) 3481 retval = DDI_FAILURE; 3482 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3483 if (!bge_chip_enable_engine(bgep, 3484 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3485 retval = DDI_FAILURE; 3486 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3487 retval = DDI_FAILURE; 3488 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3489 STATE_MACHINE_ATTN_ENABLE_BIT)) 3490 retval = DDI_FAILURE; 3491 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3492 RCV_BD_DISABLED_RING_ATTN)) 3493 retval = DDI_FAILURE; 3494 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3495 RCV_DATA_BD_ILL_RING_ATTN)) 3496 retval = DDI_FAILURE; 3497 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3498 retval = DDI_FAILURE; 3499 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3500 STATE_MACHINE_ATTN_ENABLE_BIT)) 3501 retval = DDI_FAILURE; 3502 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3503 STATE_MACHINE_ATTN_ENABLE_BIT)) 3504 retval = DDI_FAILURE; 3505 3506 /* 3507 * Step 88: download firmware -- doesn't apply 3508 * Steps 89-90: enable Transmit & Receive MAC Engines 3509 */ 3510 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3511 retval = DDI_FAILURE; 3512 #ifdef BGE_IPMI_ASF 3513 if (!bgep->asf_enabled) { 3514 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3515 RECEIVE_MODE_KEEP_VLAN_TAG)) 3516 retval = DDI_FAILURE; 3517 } else { 3518 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3519 retval = DDI_FAILURE; 3520 } 3521 #else 3522 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3523 RECEIVE_MODE_KEEP_VLAN_TAG)) 3524 retval = DDI_FAILURE; 3525 #endif 3526 3527 /* 3528 * Step 91: disable auto-polling of PHY status 3529 */ 3530 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3531 3532 /* 3533 * Step 92: configure D0 power state (not required) 3534 * Step 93: initialise LED control register () 3535 */ 3536 ledctl = LED_CONTROL_DEFAULT; 3537 switch (bgep->chipid.device) { 3538 case DEVICE_ID_5700: 3539 case DEVICE_ID_5700x: 3540 case DEVICE_ID_5701: 3541 /* 3542 * Switch to 5700 (MAC) mode on these older chips 3543 */ 3544 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3545 ledctl |= LED_CONTROL_LED_MODE_5700; 3546 break; 3547 3548 default: 3549 break; 3550 } 3551 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3552 3553 /* 3554 * Step 94: activate link 3555 */ 3556 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3557 3558 /* 3559 * Step 95: set up physical layer (PHY/SerDes) 3560 * restart autoneg (if required) 3561 */ 3562 if (reset_phys) 3563 if (bge_phys_update(bgep) == DDI_FAILURE) 3564 retval = DDI_FAILURE; 3565 3566 /* 3567 * Extra step (DSG): hand over all the Receive Buffers to the chip 3568 */ 3569 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3570 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3571 bgep->buff[ring].rf_next); 3572 3573 /* 3574 * MSI bits:The least significant MSI 16-bit word. 3575 * ISR will be triggered different. 3576 */ 3577 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3578 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3579 3580 /* 3581 * Extra step (DSG): select which interrupts are enabled 3582 * 3583 * Program the Ethernet MAC engine to signal attention on 3584 * Link Change events, then enable interrupts on MAC, DMA, 3585 * and FLOW attention signals. 3586 */ 3587 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3588 ETHERNET_EVENT_LINK_INT | 3589 ETHERNET_STATUS_PCS_ERROR_INT); 3590 #ifdef BGE_IPMI_ASF 3591 if (bgep->asf_enabled) { 3592 bge_reg_set32(bgep, MODE_CONTROL_REG, 3593 MODE_INT_ON_FLOW_ATTN | 3594 MODE_INT_ON_DMA_ATTN | 3595 MODE_HOST_STACK_UP| 3596 MODE_INT_ON_MAC_ATTN); 3597 } else { 3598 #endif 3599 bge_reg_set32(bgep, MODE_CONTROL_REG, 3600 MODE_INT_ON_FLOW_ATTN | 3601 MODE_INT_ON_DMA_ATTN | 3602 MODE_INT_ON_MAC_ATTN); 3603 #ifdef BGE_IPMI_ASF 3604 } 3605 #endif 3606 3607 /* 3608 * Step 97: enable PCI interrupts!!! 3609 */ 3610 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3611 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3612 MHCR_MASK_PCI_INT_OUTPUT); 3613 3614 /* 3615 * All done! 3616 */ 3617 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3618 return (retval); 3619 } 3620 3621 3622 /* 3623 * ========== Hardware interrupt handler ========== 3624 */ 3625 3626 #undef BGE_DBG 3627 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 3628 3629 /* 3630 * Sync the status block, then atomically clear the specified bits in 3631 * the <flags-and-tag> field of the status block. 3632 * the <flags> word of the status block, returning the value of the 3633 * <tag> and the <flags> before the bits were cleared. 3634 */ 3635 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 3636 #pragma inline(bge_status_sync) 3637 3638 static int 3639 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 3640 { 3641 bge_status_t *bsp; 3642 int retval; 3643 3644 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 3645 (void *)bgep, bits)); 3646 3647 ASSERT(bgep->bge_guard == BGE_GUARD); 3648 3649 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 3650 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 3651 if (retval != DDI_FM_OK) 3652 return (retval); 3653 3654 bsp = DMA_VPTR(bgep->status_block); 3655 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 3656 3657 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 3658 (void *)bgep, bits, *flags)); 3659 3660 return (retval); 3661 } 3662 3663 static void bge_wake_factotum(bge_t *bgep); 3664 #pragma inline(bge_wake_factotum) 3665 3666 static void 3667 bge_wake_factotum(bge_t *bgep) 3668 { 3669 mutex_enter(bgep->softintrlock); 3670 if (bgep->factotum_flag == 0) { 3671 bgep->factotum_flag = 1; 3672 ddi_trigger_softintr(bgep->factotum_id); 3673 } 3674 mutex_exit(bgep->softintrlock); 3675 } 3676 3677 /* 3678 * bge_intr() -- handle chip interrupts 3679 */ 3680 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 3681 #pragma no_inline(bge_intr) 3682 3683 uint_t 3684 bge_intr(caddr_t arg1, caddr_t arg2) 3685 { 3686 bge_t *bgep = (bge_t *)arg1; /* private device info */ 3687 bge_status_t *bsp; 3688 uint64_t flags; 3689 uint32_t mlcr = 0; 3690 uint_t result; 3691 int retval; 3692 3693 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 3694 3695 /* 3696 * GLD v2 checks that s/w setup is complete before passing 3697 * interrupts to this routine, thus eliminating the old 3698 * (and well-known) race condition around ddi_add_intr() 3699 */ 3700 ASSERT(bgep->progress & PROGRESS_HWINT); 3701 3702 /* 3703 * Check whether chip's says it's asserting #INTA; 3704 * if not, don't process or claim the interrupt. 3705 * 3706 * Note that the PCI signal is active low, so the 3707 * bit is *zero* when the interrupt is asserted. 3708 */ 3709 result = DDI_INTR_UNCLAIMED; 3710 mutex_enter(bgep->genlock); 3711 3712 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3713 mlcr = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 3714 3715 BGE_DEBUG(("bge_intr($%p) ($%p) mlcr 0x%08x", arg1, arg2, mlcr)); 3716 3717 if ((mlcr & MLCR_INTA_STATE) == 0) { 3718 /* 3719 * Block further PCI interrupts ... 3720 */ 3721 result = DDI_INTR_CLAIMED; 3722 3723 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 3724 bge_cfg_set32(bgep, PCI_CONF_BGE_MHCR, 3725 MHCR_MASK_PCI_INT_OUTPUT); 3726 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 3727 DDI_FM_OK) 3728 goto chip_stop; 3729 } 3730 3731 /* 3732 * Sync the status block and grab the flags-n-tag from it. 3733 * We count the number of interrupts where there doesn't 3734 * seem to have been a DMA update of the status block; if 3735 * it *has* been updated, the counter will be cleared in 3736 * the while() loop below ... 3737 */ 3738 bgep->missed_dmas += 1; 3739 bsp = DMA_VPTR(bgep->status_block); 3740 for (;;) { 3741 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 3742 /* 3743 * bge_chip_stop() may have freed dma area etc 3744 * while we were in this interrupt handler - 3745 * better not call bge_status_sync() 3746 */ 3747 (void) bge_check_acc_handle(bgep, 3748 bgep->io_handle); 3749 mutex_exit(bgep->genlock); 3750 return (DDI_INTR_CLAIMED); 3751 } 3752 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 3753 &flags); 3754 if (retval != DDI_FM_OK) { 3755 bgep->bge_dma_error = B_TRUE; 3756 goto chip_stop; 3757 } 3758 3759 if (!(flags & STATUS_FLAG_UPDATED)) 3760 break; 3761 3762 /* 3763 * Tell the chip that we're processing the interrupt 3764 */ 3765 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 3766 INTERRUPT_MBOX_DISABLE(flags)); 3767 if (bge_check_acc_handle(bgep, bgep->io_handle) != 3768 DDI_FM_OK) 3769 goto chip_stop; 3770 3771 /* 3772 * Drop the mutex while we: 3773 * Receive any newly-arrived packets 3774 * Recycle any newly-finished send buffers 3775 */ 3776 bgep->bge_intr_running = B_TRUE; 3777 mutex_exit(bgep->genlock); 3778 bge_receive(bgep, bsp); 3779 bge_recycle(bgep, bsp); 3780 mutex_enter(bgep->genlock); 3781 bgep->bge_intr_running = B_FALSE; 3782 3783 /* 3784 * Tell the chip we've finished processing, and 3785 * give it the tag that we got from the status 3786 * block earlier, so that it knows just how far 3787 * we've gone. If it's got more for us to do, 3788 * it will now update the status block and try 3789 * to assert an interrupt (but we've got the 3790 * #INTA blocked at present). If we see the 3791 * update, we'll loop around to do some more. 3792 * Eventually we'll get out of here ... 3793 */ 3794 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 3795 INTERRUPT_MBOX_ENABLE(flags)); 3796 bgep->missed_dmas = 0; 3797 } 3798 3799 /* 3800 * Check for exceptional conditions that we need to handle 3801 * 3802 * Link status changed 3803 * Status block not updated 3804 */ 3805 if (flags & STATUS_FLAG_LINK_CHANGED) 3806 bge_wake_factotum(bgep); 3807 3808 if (bgep->missed_dmas) { 3809 /* 3810 * Probably due to the internal status tag not 3811 * being reset. Force a status block update now; 3812 * this should ensure that we get an update and 3813 * a new interrupt. After that, we should be in 3814 * sync again ... 3815 */ 3816 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 3817 "not updated?", flags)); 3818 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 3819 COALESCE_NOW); 3820 3821 if (bgep->missed_dmas >= bge_dma_miss_limit) { 3822 /* 3823 * If this happens multiple times in a row, 3824 * it means DMA is just not working. Maybe 3825 * the chip's failed, or maybe there's a 3826 * problem on the PCI bus or in the host-PCI 3827 * bridge (Tomatillo). 3828 * 3829 * At all events, we want to stop further 3830 * interrupts and let the recovery code take 3831 * over to see whether anything can be done 3832 * about it ... 3833 */ 3834 bge_fm_ereport(bgep, 3835 DDI_FM_DEVICE_BADINT_LIMIT); 3836 goto chip_stop; 3837 } 3838 } 3839 3840 /* 3841 * Reenable assertion of #INTA, unless there's a DMA fault 3842 */ 3843 if (result == DDI_INTR_CLAIMED) { 3844 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 3845 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3846 MHCR_MASK_PCI_INT_OUTPUT); 3847 if (bge_check_acc_handle(bgep, 3848 bgep->cfg_handle) != DDI_FM_OK) 3849 goto chip_stop; 3850 } 3851 } 3852 } 3853 3854 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 3855 goto chip_stop; 3856 3857 mutex_exit(bgep->genlock); 3858 return (result); 3859 3860 chip_stop: 3861 #ifdef BGE_IPMI_ASF 3862 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 3863 /* 3864 * We must stop ASF heart beat before 3865 * bge_chip_stop(), otherwise some 3866 * computers (ex. IBM HS20 blade 3867 * server) may crash. 3868 */ 3869 bge_asf_update_status(bgep); 3870 bge_asf_stop_timer(bgep); 3871 bgep->asf_status = ASF_STAT_STOP; 3872 3873 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3874 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 3875 } 3876 #endif 3877 bge_chip_stop(bgep, B_TRUE); 3878 (void) bge_check_acc_handle(bgep, bgep->io_handle); 3879 mutex_exit(bgep->genlock); 3880 return (result); 3881 } 3882 3883 /* 3884 * ========== Factotum, implemented as a softint handler ========== 3885 */ 3886 3887 #undef BGE_DBG 3888 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 3889 3890 static void bge_factotum_error_handler(bge_t *bgep); 3891 #pragma no_inline(bge_factotum_error_handler) 3892 3893 static void 3894 bge_factotum_error_handler(bge_t *bgep) 3895 { 3896 uint32_t flow; 3897 uint32_t rdma; 3898 uint32_t wdma; 3899 uint32_t tmac; 3900 uint32_t rmac; 3901 uint32_t rxrs; 3902 uint32_t txrs = 0; 3903 3904 ASSERT(mutex_owned(bgep->genlock)); 3905 3906 /* 3907 * Read all the registers that show the possible 3908 * reasons for the ERROR bit to be asserted 3909 */ 3910 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 3911 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 3912 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 3913 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 3914 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 3915 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 3916 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3917 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 3918 3919 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 3920 (void *)bgep, flow, rdma, wdma)); 3921 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 3922 (void *)bgep, tmac, rmac, rxrs, txrs)); 3923 3924 /* 3925 * For now, just clear all the errors ... 3926 */ 3927 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3928 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 3929 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 3930 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 3931 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 3932 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 3933 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 3934 } 3935 3936 /* 3937 * Handler for hardware link state change. 3938 * 3939 * When this routine is called, the hardware link state has changed 3940 * and the new state is reflected in the param_* variables. Here 3941 * we must update the softstate, reprogram the MAC to match, and 3942 * record the change in the log and/or on the console. 3943 */ 3944 static void bge_factotum_link_handler(bge_t *bgep); 3945 #pragma no_inline(bge_factotum_link_handler) 3946 3947 static void 3948 bge_factotum_link_handler(bge_t *bgep) 3949 { 3950 void (*logfn)(bge_t *bgep, const char *fmt, ...); 3951 const char *msg; 3952 hrtime_t deltat; 3953 3954 ASSERT(mutex_owned(bgep->genlock)); 3955 3956 /* 3957 * Update the s/w link_state 3958 */ 3959 if (bgep->param_link_up) 3960 bgep->link_state = LINK_STATE_UP; 3961 else 3962 bgep->link_state = LINK_STATE_DOWN; 3963 3964 /* 3965 * Reprogram the MAC modes to match 3966 */ 3967 bge_sync_mac_modes(bgep); 3968 3969 /* 3970 * Finally, we have to decide whether to write a message 3971 * on the console or only in the log. If the PHY has 3972 * been reprogrammed (at user request) "recently", then 3973 * the message only goes in the log. Otherwise it's an 3974 * "unexpected" event, and it goes on the console as well. 3975 */ 3976 deltat = bgep->phys_event_time - bgep->phys_write_time; 3977 if (deltat > BGE_LINK_SETTLE_TIME) 3978 msg = ""; 3979 else if (bgep->param_link_up) 3980 msg = bgep->link_up_msg; 3981 else 3982 msg = bgep->link_down_msg; 3983 3984 logfn = (msg == NULL || *msg == '\0') ? bge_notice : bge_log; 3985 (*logfn)(bgep, "link %s%s", bgep->link_mode_msg, msg); 3986 } 3987 3988 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 3989 #pragma no_inline(bge_factotum_link_check) 3990 3991 static boolean_t 3992 bge_factotum_link_check(bge_t *bgep, int *dma_state) 3993 { 3994 boolean_t check; 3995 uint64_t flags; 3996 uint32_t tmac_status; 3997 3998 ASSERT(mutex_owned(bgep->genlock)); 3999 4000 /* 4001 * Get & clear the writable status bits in the Tx status register 4002 * (some bits are write-1-to-clear, others are just readonly). 4003 */ 4004 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4005 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4006 4007 /* 4008 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4009 */ 4010 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4011 STATUS_FLAG_LINK_CHANGED, &flags); 4012 if (*dma_state != DDI_FM_OK) 4013 return (B_FALSE); 4014 4015 /* 4016 * Clear any errors flagged in the status block ... 4017 */ 4018 if (flags & STATUS_FLAG_ERROR) 4019 bge_factotum_error_handler(bgep); 4020 4021 /* 4022 * We need to check the link status if: 4023 * the status block says there's been a link change 4024 * or there's any discrepancy between the various 4025 * flags indicating the link state (link_state, 4026 * param_link_up, and the LINK STATE bit in the 4027 * Transmit MAC status register). 4028 */ 4029 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4030 switch (bgep->link_state) { 4031 case LINK_STATE_UP: 4032 check |= (bgep->param_link_up == B_FALSE); 4033 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4034 break; 4035 4036 case LINK_STATE_DOWN: 4037 check |= (bgep->param_link_up != B_FALSE); 4038 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4039 break; 4040 4041 default: 4042 check = B_TRUE; 4043 break; 4044 } 4045 4046 /* 4047 * If <check> is false, we're sure the link hasn't changed. 4048 * If true, however, it's not yet definitive; we have to call 4049 * bge_phys_check() to determine whether the link has settled 4050 * into a new state yet ... and if it has, then call the link 4051 * state change handler.But when the chip is 5700 in Dell 6650 4052 * ,even if check is false, the link may have changed.So we 4053 * have to call bge_phys_check() to determine the link state. 4054 */ 4055 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4056 check = bge_phys_check(bgep); 4057 if (check) 4058 bge_factotum_link_handler(bgep); 4059 } 4060 4061 return (check); 4062 } 4063 4064 /* 4065 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4066 */ 4067 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4068 #pragma no_inline(bge_factotum_stall_check) 4069 4070 static boolean_t 4071 bge_factotum_stall_check(bge_t *bgep) 4072 { 4073 uint32_t dogval; 4074 4075 ASSERT(mutex_owned(bgep->genlock)); 4076 4077 /* 4078 * Specific check for Tx stall ... 4079 * 4080 * The 'watchdog' counter is incremented whenever a packet 4081 * is queued, reset to 1 when some (but not all) buffers 4082 * are reclaimed, reset to 0 (disabled) when all buffers 4083 * are reclaimed, and shifted left here. If it exceeds the 4084 * threshold value, the chip is assumed to have stalled and 4085 * is put into the ERROR state. The factotum will then reset 4086 * it on the next pass. 4087 * 4088 * All of which should ensure that we don't get into a state 4089 * where packets are left pending indefinitely! 4090 */ 4091 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4092 if (dogval < bge_watchdog_count) 4093 return (B_FALSE); 4094 4095 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4096 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4097 return (B_TRUE); 4098 } 4099 4100 /* 4101 * The factotum is woken up when there's something to do that we'd rather 4102 * not do from inside a hardware interrupt handler or high-level cyclic. 4103 * Its two main tasks are: 4104 * reset & restart the chip after an error 4105 * check the link status whenever necessary 4106 */ 4107 uint_t bge_chip_factotum(caddr_t arg); 4108 #pragma no_inline(bge_chip_factotum) 4109 4110 uint_t 4111 bge_chip_factotum(caddr_t arg) 4112 { 4113 bge_t *bgep; 4114 uint_t result; 4115 boolean_t error; 4116 boolean_t linkchg; 4117 int dma_state; 4118 4119 bgep = (bge_t *)arg; 4120 4121 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4122 4123 mutex_enter(bgep->softintrlock); 4124 if (bgep->factotum_flag == 0) { 4125 mutex_exit(bgep->softintrlock); 4126 return (DDI_INTR_UNCLAIMED); 4127 } 4128 bgep->factotum_flag = 0; 4129 mutex_exit(bgep->softintrlock); 4130 4131 result = DDI_INTR_CLAIMED; 4132 error = B_FALSE; 4133 linkchg = B_FALSE; 4134 4135 mutex_enter(bgep->genlock); 4136 switch (bgep->bge_chip_state) { 4137 default: 4138 break; 4139 4140 case BGE_CHIP_RUNNING: 4141 linkchg = bge_factotum_link_check(bgep, &dma_state); 4142 error = bge_factotum_stall_check(bgep); 4143 if (dma_state != DDI_FM_OK) { 4144 bgep->bge_dma_error = B_TRUE; 4145 error = B_TRUE; 4146 } 4147 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4148 error = B_TRUE; 4149 if (error) 4150 bgep->bge_chip_state = BGE_CHIP_ERROR; 4151 break; 4152 4153 case BGE_CHIP_ERROR: 4154 error = B_TRUE; 4155 break; 4156 4157 case BGE_CHIP_FAULT: 4158 /* 4159 * Fault detected, time to reset ... 4160 */ 4161 if (bge_autorecover) { 4162 if (!(bgep->progress & PROGRESS_BUFS)) { 4163 /* 4164 * if we can't allocate the ring buffers, 4165 * try later 4166 */ 4167 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4168 mutex_exit(bgep->genlock); 4169 return (result); 4170 } 4171 bgep->progress |= PROGRESS_BUFS; 4172 } 4173 if (!(bgep->progress & PROGRESS_INTR)) { 4174 bge_init_rings(bgep); 4175 bge_intr_enable(bgep); 4176 bgep->progress |= PROGRESS_INTR; 4177 } 4178 if (!(bgep->progress & PROGRESS_KSTATS)) { 4179 bge_init_kstats(bgep, 4180 ddi_get_instance(bgep->devinfo)); 4181 bgep->progress |= PROGRESS_KSTATS; 4182 } 4183 4184 BGE_REPORT((bgep, "automatic recovery activated")); 4185 4186 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4187 bgep->bge_chip_state = BGE_CHIP_ERROR; 4188 error = B_TRUE; 4189 } 4190 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4191 DDI_FM_OK) { 4192 bgep->bge_chip_state = BGE_CHIP_ERROR; 4193 error = B_TRUE; 4194 } 4195 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4196 DDI_FM_OK) { 4197 bgep->bge_chip_state = BGE_CHIP_ERROR; 4198 error = B_TRUE; 4199 } 4200 if (error == B_FALSE) { 4201 #ifdef BGE_IPMI_ASF 4202 if (bgep->asf_enabled && 4203 bgep->asf_status != ASF_STAT_RUN) { 4204 bgep->asf_timeout_id = timeout( 4205 bge_asf_heartbeat, (void *)bgep, 4206 drv_usectohz( 4207 BGE_ASF_HEARTBEAT_INTERVAL)); 4208 bgep->asf_status = ASF_STAT_RUN; 4209 } 4210 #endif 4211 ddi_fm_service_impact(bgep->devinfo, 4212 DDI_SERVICE_RESTORED); 4213 } 4214 } 4215 break; 4216 } 4217 4218 4219 /* 4220 * If an error is detected, stop the chip now, marking it as 4221 * faulty, so that it will be reset next time through ... 4222 * 4223 * Note that if intr_running is set, then bge_intr() has dropped 4224 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4225 * this point so have to wait until the next time the factotum runs. 4226 */ 4227 if (error && !bgep->bge_intr_running) { 4228 #ifdef BGE_IPMI_ASF 4229 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4230 /* 4231 * We must stop ASF heart beat before bge_chip_stop(), 4232 * otherwise some computers (ex. IBM HS20 blade server) 4233 * may crash. 4234 */ 4235 bge_asf_update_status(bgep); 4236 bge_asf_stop_timer(bgep); 4237 bgep->asf_status = ASF_STAT_STOP; 4238 4239 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4240 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4241 } 4242 #endif 4243 bge_chip_stop(bgep, B_TRUE); 4244 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4245 } 4246 mutex_exit(bgep->genlock); 4247 4248 /* 4249 * If the link state changed, tell the world about it. 4250 * Note: can't do this while still holding the mutex. 4251 */ 4252 if (linkchg) 4253 mac_link_update(bgep->macp, bgep->link_state); 4254 4255 return (result); 4256 } 4257 4258 /* 4259 * High-level cyclic handler 4260 * 4261 * This routine schedules a (low-level) softint callback to the 4262 * factotum, and prods the chip to update the status block (which 4263 * will cause a hardware interrupt when complete). 4264 */ 4265 void bge_chip_cyclic(void *arg); 4266 #pragma no_inline(bge_chip_cyclic) 4267 4268 void 4269 bge_chip_cyclic(void *arg) 4270 { 4271 bge_t *bgep; 4272 4273 bgep = arg; 4274 4275 switch (bgep->bge_chip_state) { 4276 default: 4277 return; 4278 4279 case BGE_CHIP_RUNNING: 4280 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4281 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4282 ddi_fm_service_impact(bgep->devinfo, 4283 DDI_SERVICE_UNAFFECTED); 4284 break; 4285 4286 case BGE_CHIP_FAULT: 4287 case BGE_CHIP_ERROR: 4288 break; 4289 } 4290 4291 bge_wake_factotum(bgep); 4292 } 4293 4294 4295 /* 4296 * ========== Ioctl subfunctions ========== 4297 */ 4298 4299 #undef BGE_DBG 4300 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4301 4302 #if BGE_DEBUGGING || BGE_DO_PPIO 4303 4304 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4305 #pragma no_inline(bge_chip_peek_cfg) 4306 4307 static void 4308 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4309 { 4310 uint64_t regval; 4311 uint64_t regno; 4312 4313 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4314 (void *)bgep, (void *)ppd)); 4315 4316 regno = ppd->pp_acc_offset; 4317 4318 switch (ppd->pp_acc_size) { 4319 case 1: 4320 regval = pci_config_get8(bgep->cfg_handle, regno); 4321 break; 4322 4323 case 2: 4324 regval = pci_config_get16(bgep->cfg_handle, regno); 4325 break; 4326 4327 case 4: 4328 regval = pci_config_get32(bgep->cfg_handle, regno); 4329 break; 4330 4331 case 8: 4332 regval = pci_config_get64(bgep->cfg_handle, regno); 4333 break; 4334 } 4335 4336 ppd->pp_acc_data = regval; 4337 } 4338 4339 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4340 #pragma no_inline(bge_chip_poke_cfg) 4341 4342 static void 4343 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4344 { 4345 uint64_t regval; 4346 uint64_t regno; 4347 4348 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4349 (void *)bgep, (void *)ppd)); 4350 4351 regno = ppd->pp_acc_offset; 4352 regval = ppd->pp_acc_data; 4353 4354 switch (ppd->pp_acc_size) { 4355 case 1: 4356 pci_config_put8(bgep->cfg_handle, regno, regval); 4357 break; 4358 4359 case 2: 4360 pci_config_put16(bgep->cfg_handle, regno, regval); 4361 break; 4362 4363 case 4: 4364 pci_config_put32(bgep->cfg_handle, regno, regval); 4365 break; 4366 4367 case 8: 4368 pci_config_put64(bgep->cfg_handle, regno, regval); 4369 break; 4370 } 4371 } 4372 4373 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4374 #pragma no_inline(bge_chip_peek_reg) 4375 4376 static void 4377 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4378 { 4379 uint64_t regval; 4380 void *regaddr; 4381 4382 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4383 (void *)bgep, (void *)ppd)); 4384 4385 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4386 4387 switch (ppd->pp_acc_size) { 4388 case 1: 4389 regval = ddi_get8(bgep->io_handle, regaddr); 4390 break; 4391 4392 case 2: 4393 regval = ddi_get16(bgep->io_handle, regaddr); 4394 break; 4395 4396 case 4: 4397 regval = ddi_get32(bgep->io_handle, regaddr); 4398 break; 4399 4400 case 8: 4401 regval = ddi_get64(bgep->io_handle, regaddr); 4402 break; 4403 } 4404 4405 ppd->pp_acc_data = regval; 4406 } 4407 4408 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4409 #pragma no_inline(bge_chip_peek_reg) 4410 4411 static void 4412 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4413 { 4414 uint64_t regval; 4415 void *regaddr; 4416 4417 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4418 (void *)bgep, (void *)ppd)); 4419 4420 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4421 regval = ppd->pp_acc_data; 4422 4423 switch (ppd->pp_acc_size) { 4424 case 1: 4425 ddi_put8(bgep->io_handle, regaddr, regval); 4426 break; 4427 4428 case 2: 4429 ddi_put16(bgep->io_handle, regaddr, regval); 4430 break; 4431 4432 case 4: 4433 ddi_put32(bgep->io_handle, regaddr, regval); 4434 break; 4435 4436 case 8: 4437 ddi_put64(bgep->io_handle, regaddr, regval); 4438 break; 4439 } 4440 BGE_PCICHK(bgep); 4441 } 4442 4443 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4444 #pragma no_inline(bge_chip_peek_nic) 4445 4446 static void 4447 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4448 { 4449 uint64_t regoff; 4450 uint64_t regval; 4451 void *regaddr; 4452 4453 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4454 (void *)bgep, (void *)ppd)); 4455 4456 regoff = ppd->pp_acc_offset; 4457 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4458 regoff &= MWBAR_GRANULE_MASK; 4459 regoff += NIC_MEM_WINDOW_OFFSET; 4460 regaddr = PIO_ADDR(bgep, regoff); 4461 4462 switch (ppd->pp_acc_size) { 4463 case 1: 4464 regval = ddi_get8(bgep->io_handle, regaddr); 4465 break; 4466 4467 case 2: 4468 regval = ddi_get16(bgep->io_handle, regaddr); 4469 break; 4470 4471 case 4: 4472 regval = ddi_get32(bgep->io_handle, regaddr); 4473 break; 4474 4475 case 8: 4476 regval = ddi_get64(bgep->io_handle, regaddr); 4477 break; 4478 } 4479 4480 ppd->pp_acc_data = regval; 4481 } 4482 4483 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4484 #pragma no_inline(bge_chip_poke_nic) 4485 4486 static void 4487 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4488 { 4489 uint64_t regoff; 4490 uint64_t regval; 4491 void *regaddr; 4492 4493 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4494 (void *)bgep, (void *)ppd)); 4495 4496 regoff = ppd->pp_acc_offset; 4497 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4498 regoff &= MWBAR_GRANULE_MASK; 4499 regoff += NIC_MEM_WINDOW_OFFSET; 4500 regaddr = PIO_ADDR(bgep, regoff); 4501 regval = ppd->pp_acc_data; 4502 4503 switch (ppd->pp_acc_size) { 4504 case 1: 4505 ddi_put8(bgep->io_handle, regaddr, regval); 4506 break; 4507 4508 case 2: 4509 ddi_put16(bgep->io_handle, regaddr, regval); 4510 break; 4511 4512 case 4: 4513 ddi_put32(bgep->io_handle, regaddr, regval); 4514 break; 4515 4516 case 8: 4517 ddi_put64(bgep->io_handle, regaddr, regval); 4518 break; 4519 } 4520 BGE_PCICHK(bgep); 4521 } 4522 4523 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4524 #pragma no_inline(bge_chip_peek_mii) 4525 4526 static void 4527 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4528 { 4529 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4530 (void *)bgep, (void *)ppd)); 4531 4532 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4533 } 4534 4535 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4536 #pragma no_inline(bge_chip_poke_mii) 4537 4538 static void 4539 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4540 { 4541 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4542 (void *)bgep, (void *)ppd)); 4543 4544 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4545 } 4546 4547 #if BGE_SEE_IO32 4548 4549 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4550 #pragma no_inline(bge_chip_peek_seeprom) 4551 4552 static void 4553 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4554 { 4555 uint32_t data; 4556 int err; 4557 4558 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4559 (void *)bgep, (void *)ppd)); 4560 4561 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4562 ppd->pp_acc_data = err ? ~0ull : data; 4563 } 4564 4565 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4566 #pragma no_inline(bge_chip_poke_seeprom) 4567 4568 static void 4569 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4570 { 4571 uint32_t data; 4572 4573 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4574 (void *)bgep, (void *)ppd)); 4575 4576 data = ppd->pp_acc_data; 4577 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4578 } 4579 #endif /* BGE_SEE_IO32 */ 4580 4581 #if BGE_FLASH_IO32 4582 4583 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4584 #pragma no_inline(bge_chip_peek_flash) 4585 4586 static void 4587 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4588 { 4589 uint32_t data; 4590 int err; 4591 4592 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4593 (void *)bgep, (void *)ppd)); 4594 4595 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4596 ppd->pp_acc_data = err ? ~0ull : data; 4597 } 4598 4599 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4600 #pragma no_inline(bge_chip_poke_flash) 4601 4602 static void 4603 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4604 { 4605 uint32_t data; 4606 4607 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4608 (void *)bgep, (void *)ppd)); 4609 4610 data = ppd->pp_acc_data; 4611 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 4612 ppd->pp_acc_offset, &data); 4613 } 4614 #endif /* BGE_FLASH_IO32 */ 4615 4616 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4617 #pragma no_inline(bge_chip_peek_mem) 4618 4619 static void 4620 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4621 { 4622 uint64_t regval; 4623 void *vaddr; 4624 4625 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 4626 (void *)bgep, (void *)ppd)); 4627 4628 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4629 4630 switch (ppd->pp_acc_size) { 4631 case 1: 4632 regval = *(uint8_t *)vaddr; 4633 break; 4634 4635 case 2: 4636 regval = *(uint16_t *)vaddr; 4637 break; 4638 4639 case 4: 4640 regval = *(uint32_t *)vaddr; 4641 break; 4642 4643 case 8: 4644 regval = *(uint64_t *)vaddr; 4645 break; 4646 } 4647 4648 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 4649 (void *)bgep, (void *)ppd, regval, vaddr)); 4650 4651 ppd->pp_acc_data = regval; 4652 } 4653 4654 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4655 #pragma no_inline(bge_chip_poke_mem) 4656 4657 static void 4658 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4659 { 4660 uint64_t regval; 4661 void *vaddr; 4662 4663 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 4664 (void *)bgep, (void *)ppd)); 4665 4666 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4667 regval = ppd->pp_acc_data; 4668 4669 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 4670 (void *)bgep, (void *)ppd, regval, vaddr)); 4671 4672 switch (ppd->pp_acc_size) { 4673 case 1: 4674 *(uint8_t *)vaddr = (uint8_t)regval; 4675 break; 4676 4677 case 2: 4678 *(uint16_t *)vaddr = (uint16_t)regval; 4679 break; 4680 4681 case 4: 4682 *(uint32_t *)vaddr = (uint32_t)regval; 4683 break; 4684 4685 case 8: 4686 *(uint64_t *)vaddr = (uint64_t)regval; 4687 break; 4688 } 4689 } 4690 4691 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4692 struct iocblk *iocp); 4693 #pragma no_inline(bge_pp_ioctl) 4694 4695 static enum ioc_reply 4696 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4697 { 4698 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 4699 bge_peekpoke_t *ppd; 4700 dma_area_t *areap; 4701 uint64_t sizemask; 4702 uint64_t mem_va; 4703 uint64_t maxoff; 4704 boolean_t peek; 4705 4706 switch (cmd) { 4707 default: 4708 /* NOTREACHED */ 4709 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 4710 return (IOC_INVAL); 4711 4712 case BGE_PEEK: 4713 peek = B_TRUE; 4714 break; 4715 4716 case BGE_POKE: 4717 peek = B_FALSE; 4718 break; 4719 } 4720 4721 /* 4722 * Validate format of ioctl 4723 */ 4724 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 4725 return (IOC_INVAL); 4726 if (mp->b_cont == NULL) 4727 return (IOC_INVAL); 4728 ppd = (bge_peekpoke_t *)mp->b_cont->b_rptr; 4729 4730 /* 4731 * Validate request parameters 4732 */ 4733 switch (ppd->pp_acc_space) { 4734 default: 4735 return (IOC_INVAL); 4736 4737 case BGE_PP_SPACE_CFG: 4738 /* 4739 * Config space 4740 */ 4741 sizemask = 8|4|2|1; 4742 mem_va = 0; 4743 maxoff = PCI_CONF_HDR_SIZE; 4744 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 4745 break; 4746 4747 case BGE_PP_SPACE_REG: 4748 /* 4749 * Memory-mapped I/O space 4750 */ 4751 sizemask = 8|4|2|1; 4752 mem_va = 0; 4753 maxoff = RIAAR_REGISTER_MAX; 4754 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 4755 break; 4756 4757 case BGE_PP_SPACE_NIC: 4758 /* 4759 * NIC on-chip memory 4760 */ 4761 sizemask = 8|4|2|1; 4762 mem_va = 0; 4763 maxoff = MWBAR_ONCHIP_MAX; 4764 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 4765 break; 4766 4767 case BGE_PP_SPACE_MII: 4768 /* 4769 * PHY's MII registers 4770 * NB: all PHY registers are two bytes, but the 4771 * addresses increment in ones (word addressing). 4772 * So we scale the address here, then undo the 4773 * transformation inside the peek/poke functions. 4774 */ 4775 ppd->pp_acc_offset *= 2; 4776 sizemask = 2; 4777 mem_va = 0; 4778 maxoff = (MII_MAXREG+1)*2; 4779 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 4780 break; 4781 4782 #if BGE_SEE_IO32 4783 case BGE_PP_SPACE_SEEPROM: 4784 /* 4785 * Attached SEEPROM(s), if any. 4786 * NB: we use the high-order bits of the 'address' as 4787 * a device select to accommodate multiple SEEPROMS, 4788 * If each one is the maximum size (64kbytes), this 4789 * makes them appear contiguous. Otherwise, there may 4790 * be holes in the mapping. ENxS doesn't have any 4791 * SEEPROMs anyway ... 4792 */ 4793 sizemask = 4; 4794 mem_va = 0; 4795 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 4796 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 4797 break; 4798 #endif /* BGE_SEE_IO32 */ 4799 4800 #if BGE_FLASH_IO32 4801 case BGE_PP_SPACE_FLASH: 4802 /* 4803 * Attached Flash device (if any); a maximum of one device 4804 * is currently supported. But it can be up to 1MB (unlike 4805 * the 64k limit on SEEPROMs) so why would you need more ;-) 4806 */ 4807 sizemask = 4; 4808 mem_va = 0; 4809 maxoff = NVM_FLASH_ADDR_MASK; 4810 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 4811 break; 4812 #endif /* BGE_FLASH_IO32 */ 4813 4814 case BGE_PP_SPACE_BGE: 4815 /* 4816 * BGE data structure! 4817 */ 4818 sizemask = 8|4|2|1; 4819 mem_va = (uintptr_t)bgep; 4820 maxoff = sizeof (*bgep); 4821 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 4822 break; 4823 4824 case BGE_PP_SPACE_STATUS: 4825 case BGE_PP_SPACE_STATISTICS: 4826 case BGE_PP_SPACE_TXDESC: 4827 case BGE_PP_SPACE_TXBUFF: 4828 case BGE_PP_SPACE_RXDESC: 4829 case BGE_PP_SPACE_RXBUFF: 4830 /* 4831 * Various DMA_AREAs 4832 */ 4833 switch (ppd->pp_acc_space) { 4834 case BGE_PP_SPACE_TXDESC: 4835 areap = &bgep->tx_desc; 4836 break; 4837 case BGE_PP_SPACE_TXBUFF: 4838 areap = &bgep->tx_buff[0]; 4839 break; 4840 case BGE_PP_SPACE_RXDESC: 4841 areap = &bgep->rx_desc[0]; 4842 break; 4843 case BGE_PP_SPACE_RXBUFF: 4844 areap = &bgep->rx_buff[0]; 4845 break; 4846 case BGE_PP_SPACE_STATUS: 4847 areap = &bgep->status_block; 4848 break; 4849 case BGE_PP_SPACE_STATISTICS: 4850 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 4851 areap = &bgep->statistics; 4852 break; 4853 } 4854 4855 sizemask = 8|4|2|1; 4856 mem_va = (uintptr_t)areap->mem_va; 4857 maxoff = areap->alength; 4858 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 4859 break; 4860 } 4861 4862 switch (ppd->pp_acc_size) { 4863 default: 4864 return (IOC_INVAL); 4865 4866 case 8: 4867 case 4: 4868 case 2: 4869 case 1: 4870 if ((ppd->pp_acc_size & sizemask) == 0) 4871 return (IOC_INVAL); 4872 break; 4873 } 4874 4875 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4876 return (IOC_INVAL); 4877 4878 if (ppd->pp_acc_offset >= maxoff) 4879 return (IOC_INVAL); 4880 4881 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 4882 return (IOC_INVAL); 4883 4884 /* 4885 * All OK - go do it! 4886 */ 4887 ppd->pp_acc_offset += mem_va; 4888 (*ppfn)(bgep, ppd); 4889 return (peek ? IOC_REPLY : IOC_ACK); 4890 } 4891 4892 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4893 struct iocblk *iocp); 4894 #pragma no_inline(bge_diag_ioctl) 4895 4896 static enum ioc_reply 4897 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4898 { 4899 ASSERT(mutex_owned(bgep->genlock)); 4900 4901 switch (cmd) { 4902 default: 4903 /* NOTREACHED */ 4904 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 4905 return (IOC_INVAL); 4906 4907 case BGE_DIAG: 4908 /* 4909 * Currently a no-op 4910 */ 4911 return (IOC_ACK); 4912 4913 case BGE_PEEK: 4914 case BGE_POKE: 4915 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 4916 4917 case BGE_PHY_RESET: 4918 return (IOC_RESTART_ACK); 4919 4920 case BGE_SOFT_RESET: 4921 case BGE_HARD_RESET: 4922 /* 4923 * Reset and reinitialise the 570x hardware 4924 */ 4925 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 4926 return (IOC_ACK); 4927 } 4928 4929 /* NOTREACHED */ 4930 } 4931 4932 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 4933 4934 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4935 struct iocblk *iocp); 4936 #pragma no_inline(bge_mii_ioctl) 4937 4938 static enum ioc_reply 4939 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4940 { 4941 struct bge_mii_rw *miirwp; 4942 4943 /* 4944 * Validate format of ioctl 4945 */ 4946 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 4947 return (IOC_INVAL); 4948 if (mp->b_cont == NULL) 4949 return (IOC_INVAL); 4950 miirwp = (struct bge_mii_rw *)mp->b_cont->b_rptr; 4951 4952 /* 4953 * Validate request parameters ... 4954 */ 4955 if (miirwp->mii_reg > MII_MAXREG) 4956 return (IOC_INVAL); 4957 4958 switch (cmd) { 4959 default: 4960 /* NOTREACHED */ 4961 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 4962 return (IOC_INVAL); 4963 4964 case BGE_MII_READ: 4965 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 4966 return (IOC_REPLY); 4967 4968 case BGE_MII_WRITE: 4969 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 4970 return (IOC_ACK); 4971 } 4972 4973 /* NOTREACHED */ 4974 } 4975 4976 #if BGE_SEE_IO32 4977 4978 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4979 struct iocblk *iocp); 4980 #pragma no_inline(bge_see_ioctl) 4981 4982 static enum ioc_reply 4983 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4984 { 4985 struct bge_see_rw *seerwp; 4986 4987 /* 4988 * Validate format of ioctl 4989 */ 4990 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 4991 return (IOC_INVAL); 4992 if (mp->b_cont == NULL) 4993 return (IOC_INVAL); 4994 seerwp = (struct bge_see_rw *)mp->b_cont->b_rptr; 4995 4996 /* 4997 * Validate request parameters ... 4998 */ 4999 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5000 return (IOC_INVAL); 5001 5002 switch (cmd) { 5003 default: 5004 /* NOTREACHED */ 5005 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5006 return (IOC_INVAL); 5007 5008 case BGE_SEE_READ: 5009 case BGE_SEE_WRITE: 5010 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5011 seerwp->see_addr, &seerwp->see_data); 5012 return (IOC_REPLY); 5013 } 5014 5015 /* NOTREACHED */ 5016 } 5017 5018 #endif /* BGE_SEE_IO32 */ 5019 5020 #if BGE_FLASH_IO32 5021 5022 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5023 struct iocblk *iocp); 5024 #pragma no_inline(bge_flash_ioctl) 5025 5026 static enum ioc_reply 5027 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5028 { 5029 struct bge_flash_rw *flashrwp; 5030 5031 /* 5032 * Validate format of ioctl 5033 */ 5034 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5035 return (IOC_INVAL); 5036 if (mp->b_cont == NULL) 5037 return (IOC_INVAL); 5038 flashrwp = (struct bge_flash_rw *)mp->b_cont->b_rptr; 5039 5040 /* 5041 * Validate request parameters ... 5042 */ 5043 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5044 return (IOC_INVAL); 5045 5046 switch (cmd) { 5047 default: 5048 /* NOTREACHED */ 5049 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5050 return (IOC_INVAL); 5051 5052 case BGE_FLASH_READ: 5053 case BGE_FLASH_WRITE: 5054 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5055 flashrwp->flash_addr, &flashrwp->flash_data); 5056 return (IOC_REPLY); 5057 } 5058 5059 /* NOTREACHED */ 5060 } 5061 5062 #endif /* BGE_FLASH_IO32 */ 5063 5064 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5065 struct iocblk *iocp); 5066 #pragma no_inline(bge_chip_ioctl) 5067 5068 enum ioc_reply 5069 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5070 { 5071 int cmd; 5072 5073 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5074 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5075 5076 ASSERT(mutex_owned(bgep->genlock)); 5077 5078 cmd = iocp->ioc_cmd; 5079 switch (cmd) { 5080 default: 5081 /* NOTREACHED */ 5082 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5083 return (IOC_INVAL); 5084 5085 case BGE_DIAG: 5086 case BGE_PEEK: 5087 case BGE_POKE: 5088 case BGE_PHY_RESET: 5089 case BGE_SOFT_RESET: 5090 case BGE_HARD_RESET: 5091 #if BGE_DEBUGGING || BGE_DO_PPIO 5092 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5093 #else 5094 return (IOC_INVAL); 5095 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5096 5097 case BGE_MII_READ: 5098 case BGE_MII_WRITE: 5099 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5100 5101 #if BGE_SEE_IO32 5102 case BGE_SEE_READ: 5103 case BGE_SEE_WRITE: 5104 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5105 #endif /* BGE_SEE_IO32 */ 5106 5107 #if BGE_FLASH_IO32 5108 case BGE_FLASH_READ: 5109 case BGE_FLASH_WRITE: 5110 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5111 #endif /* BGE_FLASH_IO32 */ 5112 } 5113 5114 /* NOTREACHED */ 5115 } 5116 5117 void 5118 bge_chip_blank(void *arg, time_t ticks, uint_t count) 5119 { 5120 bge_t *bgep = arg; 5121 5122 mutex_enter(bgep->genlock); 5123 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5124 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5125 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5126 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5127 mutex_exit(bgep->genlock); 5128 } 5129 5130 #ifdef BGE_IPMI_ASF 5131 5132 uint32_t 5133 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5134 { 5135 uint32_t data; 5136 5137 if (!bgep->asf_wordswapped) { 5138 /* a workaround word swap error */ 5139 if (addr & 4) 5140 addr = addr - 4; 5141 else 5142 addr = addr + 4; 5143 } 5144 5145 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5146 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5147 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5148 5149 return (data); 5150 } 5151 5152 5153 void 5154 bge_asf_update_status(bge_t *bgep) 5155 { 5156 uint32_t event; 5157 5158 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5159 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5160 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5161 5162 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5163 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5164 } 5165 5166 5167 /* 5168 * The driver is supposed to notify ASF that the OS is still running 5169 * every three seconds, otherwise the management server may attempt 5170 * to reboot the machine. If it hasn't actually failed, this is 5171 * not a desireable result. However, this isn't running as a real-time 5172 * thread, and even if it were, it might not be able to generate the 5173 * heartbeat in a timely manner due to system load. As it isn't a 5174 * significant strain on the machine, we will set the interval to half 5175 * of the required value. 5176 */ 5177 void 5178 bge_asf_heartbeat(void *arg) 5179 { 5180 bge_t *bgep = (bge_t *)arg; 5181 5182 mutex_enter(bgep->genlock); 5183 bge_asf_update_status((bge_t *)bgep); 5184 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5185 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5186 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5187 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5188 mutex_exit(bgep->genlock); 5189 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5190 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5191 } 5192 5193 5194 void 5195 bge_asf_stop_timer(bge_t *bgep) 5196 { 5197 timeout_id_t tmp_id = 0; 5198 5199 while ((bgep->asf_timeout_id != 0) && 5200 (tmp_id != bgep->asf_timeout_id)) { 5201 tmp_id = bgep->asf_timeout_id; 5202 (void) untimeout(tmp_id); 5203 } 5204 bgep->asf_timeout_id = 0; 5205 } 5206 5207 5208 5209 /* 5210 * This function should be placed at the earliest postion of bge_attach(). 5211 */ 5212 void 5213 bge_asf_get_config(bge_t *bgep) 5214 { 5215 uint32_t nicsig; 5216 uint32_t niccfg; 5217 5218 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5219 if (nicsig == BGE_NIC_DATA_SIG) { 5220 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5221 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5222 /* 5223 * Here, we don't consider BAXTER, because BGE haven't 5224 * supported BAXTER (that is 5752). Also, as I know, 5225 * BAXTER doesn't support ASF feature. 5226 */ 5227 bgep->asf_enabled = B_TRUE; 5228 else 5229 bgep->asf_enabled = B_FALSE; 5230 } else 5231 bgep->asf_enabled = B_FALSE; 5232 } 5233 5234 5235 void 5236 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5237 { 5238 uint32_t tries; 5239 uint32_t event; 5240 5241 ASSERT(bgep->asf_enabled); 5242 5243 /* Issues "pause firmware" command and wait for ACK */ 5244 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5245 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5246 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5247 5248 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5249 tries = 0; 5250 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5251 drv_usecwait(1); 5252 tries ++; 5253 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5254 } 5255 5256 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5257 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5258 5259 if (bgep->asf_newhandshake) { 5260 switch (mode) { 5261 case BGE_INIT_RESET: 5262 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5263 BGE_DRV_STATE_START); 5264 break; 5265 case BGE_SHUTDOWN_RESET: 5266 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5267 BGE_DRV_STATE_UNLOAD); 5268 break; 5269 case BGE_SUSPEND_RESET: 5270 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5271 BGE_DRV_STATE_SUSPEND); 5272 break; 5273 default: 5274 break; 5275 } 5276 } 5277 } 5278 5279 5280 void 5281 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5282 { 5283 switch (mode) { 5284 case BGE_INIT_RESET: 5285 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5286 BGE_DRV_STATE_START); 5287 break; 5288 case BGE_SHUTDOWN_RESET: 5289 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5290 BGE_DRV_STATE_UNLOAD); 5291 break; 5292 case BGE_SUSPEND_RESET: 5293 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5294 BGE_DRV_STATE_SUSPEND); 5295 break; 5296 default: 5297 break; 5298 } 5299 } 5300 5301 5302 void 5303 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5304 { 5305 switch (mode) { 5306 case BGE_INIT_RESET: 5307 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5308 BGE_DRV_STATE_START_DONE); 5309 break; 5310 case BGE_SHUTDOWN_RESET: 5311 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5312 BGE_DRV_STATE_UNLOAD_DONE); 5313 break; 5314 default: 5315 break; 5316 } 5317 } 5318 5319 #endif /* BGE_IPMI_ASF */ 5320