1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include "bge_impl.h" 28 29 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 30 31 /* 32 * Future features ... ? 33 */ 34 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 35 #define BGE_IND_IO32 1 /* indirect access code */ 36 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 37 #define BGE_FLASH_IO32 1 /* FLASH access code */ 38 39 /* 40 * BGE MSI tunable: 41 * 42 * By default MSI is enabled on all supported platforms but it is disabled 43 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 44 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 45 */ 46 boolean_t bge_enable_msi = B_TRUE; 47 48 /* 49 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 50 */ 51 boolean_t bge_relaxed_ordering = B_TRUE; 52 53 /* 54 * Property names 55 */ 56 static char knownids_propname[] = "bge-known-subsystems"; 57 58 /* 59 * Patchable globals: 60 * 61 * bge_autorecover 62 * Enables/disables automatic recovery after fault detection 63 * 64 * bge_mlcr_default 65 * Value to program into the MLCR; controls the chip's GPIO pins 66 * 67 * bge_dma_{rd,wr}prio 68 * Relative priorities of DMA reads & DMA writes respectively. 69 * These may each be patched to any value 0-3. Equal values 70 * will give "fair" (round-robin) arbitration for PCI access. 71 * Unequal values will give one or the other function priority. 72 * 73 * bge_dma_rwctrl 74 * Value to put in the Read/Write DMA control register. See 75 * the Broadcom PRM for things you can fiddle with in this 76 * register ... 77 * 78 * bge_{tx,rx}_{count,ticks}_{norm,intr} 79 * Send/receive interrupt coalescing parameters. Counts are 80 * #s of descriptors, ticks are in microseconds. *norm* values 81 * apply between status updates/interrupts; the *intr* values 82 * refer to the 'during-interrupt' versions - see the PRM. 83 * 84 * NOTE: these values have been determined by measurement. They 85 * differ significantly from the values recommended in the PRM. 86 */ 87 static uint32_t bge_autorecover = 1; 88 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 89 90 static uint32_t bge_dma_rdprio = 1; 91 static uint32_t bge_dma_wrprio = 0; 92 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 93 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 94 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 95 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 96 97 uint32_t bge_rx_ticks_norm = 128; 98 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 99 uint32_t bge_rx_count_norm = 8; 100 uint32_t bge_tx_count_norm = 128; 101 102 static uint32_t bge_rx_ticks_intr = 128; 103 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 104 static uint32_t bge_rx_count_intr = 2; 105 static uint32_t bge_tx_count_intr = 0; 106 107 /* 108 * Memory pool configuration parameters. 109 * 110 * These are generally specific to each member of the chip family, since 111 * each one may have a different memory size/configuration. 112 * 113 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 114 * the driver from programming the various registers; instead they are left 115 * at their hardware defaults. This is the preferred option for later chips 116 * (5705+), whereas the older chips *required* these registers to be set, 117 * since the h/w default was 0 ;-( 118 */ 119 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 120 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 121 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 122 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 123 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 124 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 125 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 126 static uint32_t bge_mbuf_pool_len_5721 = 0; 127 128 /* 129 * Various high and low water marks, thresholds, etc ... 130 * 131 * Note: these are taken from revision 7 of the PRM, and some are different 132 * from both the values in earlier PRMs *and* those determined experimentally 133 * and used in earlier versions of this driver ... 134 */ 135 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 136 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 137 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 138 139 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 140 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 141 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 142 143 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 144 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 145 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 146 147 static uint32_t bge_watchdog_count = 1 << 16; 148 static uint16_t bge_dma_miss_limit = 20; 149 150 static uint32_t bge_stop_start_on_sync = 0; 151 152 /* 153 * bge_intr_max_loop controls the maximum loop number within bge_intr. 154 * When loading NIC with heavy network traffic, it is useful. 155 * Increasing this value could have positive effect to throughput, 156 * but it might also increase ticks of a bge ISR stick on CPU, which might 157 * lead to bad UI interactive experience. So tune this with caution. 158 */ 159 static int bge_intr_max_loop = 1; 160 161 /* 162 * ========== Low-level chip & ring buffer manipulation ========== 163 */ 164 165 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 166 167 168 /* 169 * Config space read-modify-write routines 170 */ 171 172 #if BGE_CFG_IO8 173 174 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 175 #pragma inline(bge_cfg_clr16) 176 177 static void 178 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 179 { 180 uint16_t regval; 181 182 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 183 (void *)bgep, regno, bits)); 184 185 regval = pci_config_get16(bgep->cfg_handle, regno); 186 187 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 188 (void *)bgep, regno, bits, regval, regval & ~bits)); 189 190 regval &= ~bits; 191 pci_config_put16(bgep->cfg_handle, regno, regval); 192 } 193 194 #endif /* BGE_CFG_IO8 */ 195 196 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 197 #pragma inline(bge_cfg_clr32) 198 199 static void 200 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 201 { 202 uint32_t regval; 203 204 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 205 (void *)bgep, regno, bits)); 206 207 regval = pci_config_get32(bgep->cfg_handle, regno); 208 209 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 210 (void *)bgep, regno, bits, regval, regval & ~bits)); 211 212 regval &= ~bits; 213 pci_config_put32(bgep->cfg_handle, regno, regval); 214 } 215 216 #if BGE_IND_IO32 217 218 /* 219 * Indirect access to registers & RISC scratchpads, using config space 220 * accesses only. 221 * 222 * This isn't currently used, but someday we might want to use it for 223 * restoring the Subsystem Device/Vendor registers (which aren't directly 224 * writable in Config Space), or for downloading firmware into the RISCs 225 * 226 * In any case there are endian issues to be resolved before this code is 227 * enabled; the bizarre way that bytes get twisted by this chip AND by 228 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 229 * it's been thoroughly tested for all access sizes on all supported 230 * architectures (SPARC *and* x86!). 231 */ 232 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 233 #pragma inline(bge_ind_get32) 234 235 uint32_t 236 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 237 { 238 uint32_t val; 239 240 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 241 242 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 243 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 244 245 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 246 (void *)bgep, regno, val)); 247 248 val = LE_32(val); 249 250 return (val); 251 } 252 253 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 254 #pragma inline(bge_ind_put32) 255 256 void 257 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 258 { 259 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 260 (void *)bgep, regno, val)); 261 262 val = LE_32(val); 263 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 264 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 265 } 266 267 #endif /* BGE_IND_IO32 */ 268 269 #if BGE_DEBUGGING 270 271 static void bge_pci_check(bge_t *bgep); 272 #pragma no_inline(bge_pci_check) 273 274 static void 275 bge_pci_check(bge_t *bgep) 276 { 277 uint16_t pcistatus; 278 279 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 280 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 281 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 282 (void *)bgep, pcistatus)); 283 } 284 285 #endif /* BGE_DEBUGGING */ 286 287 /* 288 * Perform first-stage chip (re-)initialisation, using only config-space 289 * accesses: 290 * 291 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 292 * returning the data in the structure pointed to by <idp>. 293 * + Configure the target-mode endianness (swap) options. 294 * + Disable interrupts and enable Memory Space accesses. 295 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 296 * 297 * This sequence is adapted from Broadcom document 570X-PG102-R, 298 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 299 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 300 * 301 * This function MUST be called before any non-config-space accesses 302 * are made; on this first call <enable_dma> is B_FALSE, and it 303 * effectively performs steps 3-1(!) of the initialisation sequence 304 * (the rest are not required but should be harmless). 305 * 306 * It MUST also be called after a chip reset, as this disables 307 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 308 * it is effectively performing steps 6-8. 309 */ 310 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 311 #pragma no_inline(bge_chip_cfg_init) 312 313 void 314 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 315 { 316 ddi_acc_handle_t handle; 317 uint16_t command; 318 uint32_t mhcr; 319 uint16_t value16; 320 int i; 321 322 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 323 (void *)bgep, (void *)cidp, enable_dma)); 324 325 /* 326 * Step 3: save PCI cache line size and subsystem vendor ID 327 * 328 * Read all the config-space registers that characterise the 329 * chip, specifically vendor/device/revision/subsystem vendor 330 * and subsystem device id. We expect (but don't check) that 331 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 332 * 333 * Also save all bus-transaction related registers (cache-line 334 * size, bus-grant/latency parameters, etc). Some of these are 335 * cleared by reset, so we'll have to restore them later. This 336 * comes from the Broadcom document 570X-PG102-R ... 337 * 338 * Note: Broadcom document 570X-PG102-R seems to be in error 339 * here w.r.t. the offsets of the Subsystem Vendor ID and 340 * Subsystem (Device) ID registers, which are the opposite way 341 * round according to the PCI standard. For good measure, we 342 * save/restore both anyway. 343 */ 344 handle = bgep->cfg_handle; 345 346 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 347 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 348 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 349 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 350 351 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 352 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 353 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 354 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 355 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 356 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 357 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 358 359 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 360 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 361 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 362 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 363 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 364 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 365 cidp->vendor, cidp->device, cidp->revision)); 366 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 367 cidp->subven, cidp->subdev, cidp->asic_rev)); 368 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 369 cidp->clsize, cidp->latency, cidp->command)); 370 371 /* 372 * Step 2 (also step 6): disable and clear interrupts. 373 * Steps 11-13: configure PIO endianness options, and enable 374 * indirect register access. We'll also select any other 375 * options controlled by the MHCR (e.g. tagged status, mask 376 * interrupt mode) at this stage ... 377 * 378 * Note: internally, the chip is 64-bit and BIG-endian, but 379 * since it talks to the host over a (LITTLE-endian) PCI bus, 380 * it normally swaps bytes around at the PCI interface. 381 * However, the PCI host bridge on SPARC systems normally 382 * swaps the byte lanes around too, since SPARCs are also 383 * BIG-endian. So it turns out that on SPARC, the right 384 * option is to tell the chip to swap (and the host bridge 385 * will swap back again), whereas on x86 we ask the chip 386 * NOT to swap, so the natural little-endianness of the 387 * PCI bus is assumed. Then the only thing that doesn't 388 * automatically work right is access to an 8-byte register 389 * by a little-endian host; but we don't want to set the 390 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 391 * accesses don't go where expected ;-( So we live with 392 * that, and perform word-swaps in software in the few cases 393 * where a chip register is defined as an 8-byte value -- 394 * see the code below for details ... 395 * 396 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 397 * very clear in the register description in the PRM, but 398 * Broadcom document 570X-PG104-R page 248 explains a little 399 * more (under "Broadcom Mask Mode"). The bit changes the way 400 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 401 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 402 * way as the 5700 did, which isn't very convenient. Setting 403 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 404 * bit do just what its name says -- MASK the PCI #INTA output 405 * (i.e. deassert the signal at the pin) leaving all internal 406 * state unchanged. This is much more convenient for our 407 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 408 * 409 * Note: the inconvenient semantics of the interrupt mailbox 410 * (nonzero disables and acknowledges/clears the interrupt, 411 * zero enables AND CLEARS it) would make race conditions 412 * likely in the interrupt handler: 413 * 414 * (1) acknowledge & disable interrupts 415 * (2) while (more to do) 416 * process packets 417 * (3) enable interrupts -- also clears pending 418 * 419 * If the chip received more packets and internally generated 420 * an interrupt between the check at (2) and the mbox write 421 * at (3), this interrupt would be lost :-( 422 * 423 * The best way to avoid this is to use TAGGED STATUS mode, 424 * where the chip includes a unique tag in each status block 425 * update, and the host, when re-enabling interrupts, passes 426 * the last tag it saw back to the chip; then the chip can 427 * see whether the host is truly up to date, and regenerate 428 * its interrupt if not. 429 */ 430 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 431 MHCR_ENABLE_TAGGED_STATUS_MODE | 432 MHCR_MASK_INTERRUPT_MODE | 433 MHCR_CLEAR_INTERRUPT_INTA; 434 435 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 436 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 437 438 #ifdef _BIG_ENDIAN 439 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 440 #endif /* _BIG_ENDIAN */ 441 442 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 443 444 #ifdef BGE_IPMI_ASF 445 bgep->asf_wordswapped = B_FALSE; 446 #endif 447 /* 448 * Step 1 (also step 7): Enable PCI Memory Space accesses 449 * Disable Memory Write/Invalidate 450 * Enable or disable Bus Mastering 451 * 452 * Note that all other bits are taken from the original value saved 453 * the first time through here, rather than from the current register 454 * value, 'cos that will have been cleared by a soft RESET since. 455 * In this way we preserve the OBP/nexus-parent's preferred settings 456 * of the parity-error and system-error enable bits across multiple 457 * chip RESETs. 458 */ 459 command = bgep->chipid.command | PCI_COMM_MAE; 460 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 461 if (enable_dma) 462 command |= PCI_COMM_ME; 463 /* 464 * on BCM5714 revision A0, false parity error gets generated 465 * due to a logic bug. Provide a workaround by disabling parity 466 * error. 467 */ 468 if (((cidp->device == DEVICE_ID_5714C) || 469 (cidp->device == DEVICE_ID_5714S)) && 470 (cidp->revision == REVISION_ID_5714_A0)) { 471 command &= ~PCI_COMM_PARITY_DETECT; 472 } 473 pci_config_put16(handle, PCI_CONF_COMM, command); 474 475 /* 476 * On some PCI-E device, there were instances when 477 * the device was still link training. 478 */ 479 if (bgep->chipid.pci_type == BGE_PCI_E) { 480 i = 0; 481 value16 = pci_config_get16(handle, PCI_CONF_COMM); 482 while ((value16 != command) && (i < 100)) { 483 drv_usecwait(200); 484 value16 = pci_config_get16(handle, PCI_CONF_COMM); 485 ++i; 486 } 487 } 488 489 /* 490 * Clear any remaining error status bits 491 */ 492 pci_config_put16(handle, PCI_CONF_STAT, ~0); 493 494 /* 495 * Do following if and only if the device is NOT BCM5714C OR 496 * BCM5715C 497 */ 498 if (!((cidp->device == DEVICE_ID_5714C) || 499 (cidp->device == DEVICE_ID_5715C))) { 500 /* 501 * Make sure these indirect-access registers are sane 502 * rather than random after power-up or reset 503 */ 504 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 505 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 506 } 507 /* 508 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 509 */ 510 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 511 512 if (cidp->pci_type == BGE_PCI_E) { 513 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 514 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723, 515 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 516 } else 517 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 518 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 519 } 520 } 521 522 #ifdef __amd64 523 /* 524 * Distinguish CPU types 525 * 526 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 527 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 528 * for PCI-Express based network interface card. This is the work-around 529 * for those nics. 530 */ 531 static boolean_t bge_get_em64t_type(void); 532 #pragma inline(bge_get_em64t_type) 533 534 static boolean_t 535 bge_get_em64t_type(void) 536 { 537 538 return (x86_vendor == X86_VENDOR_Intel); 539 } 540 #endif 541 542 /* 543 * Operating register get/set access routines 544 */ 545 546 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 547 #pragma inline(bge_reg_get32) 548 549 uint32_t 550 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 551 { 552 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 553 (void *)bgep, regno)); 554 555 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 556 } 557 558 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 559 #pragma inline(bge_reg_put32) 560 561 void 562 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 563 { 564 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 565 (void *)bgep, regno, data)); 566 567 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 568 BGE_PCICHK(bgep); 569 } 570 571 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 572 #pragma inline(bge_reg_set32) 573 574 void 575 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 576 { 577 uint32_t regval; 578 579 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 580 (void *)bgep, regno, bits)); 581 582 regval = bge_reg_get32(bgep, regno); 583 regval |= bits; 584 bge_reg_put32(bgep, regno, regval); 585 } 586 587 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 588 #pragma inline(bge_reg_clr32) 589 590 void 591 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 592 { 593 uint32_t regval; 594 595 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 596 (void *)bgep, regno, bits)); 597 598 regval = bge_reg_get32(bgep, regno); 599 regval &= ~bits; 600 bge_reg_put32(bgep, regno, regval); 601 } 602 603 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 604 #pragma inline(bge_reg_get64) 605 606 static uint64_t 607 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 608 { 609 uint64_t regval; 610 611 #ifdef __amd64 612 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 613 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 614 regval <<= 32; 615 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 616 } else { 617 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 618 } 619 #elif defined(__sparc) 620 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 621 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 622 regval <<= 32; 623 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 624 } else { 625 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 626 } 627 #else 628 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 629 #endif 630 631 #ifdef _LITTLE_ENDIAN 632 regval = (regval >> 32) | (regval << 32); 633 #endif /* _LITTLE_ENDIAN */ 634 635 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 636 (void *)bgep, regno, regval)); 637 638 return (regval); 639 } 640 641 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 642 #pragma inline(bge_reg_put64) 643 644 static void 645 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 646 { 647 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 648 (void *)bgep, regno, data)); 649 650 #ifdef _LITTLE_ENDIAN 651 data = ((data >> 32) | (data << 32)); 652 #endif /* _LITTLE_ENDIAN */ 653 654 #ifdef __amd64 655 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 656 ddi_put32(bgep->io_handle, 657 PIO_ADDR(bgep, regno), (uint32_t)data); 658 BGE_PCICHK(bgep); 659 ddi_put32(bgep->io_handle, 660 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 661 662 } else { 663 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 664 } 665 #elif defined(__sparc) 666 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 667 ddi_put32(bgep->io_handle, 668 PIO_ADDR(bgep, regno + 4), (uint32_t)data); 669 BGE_PCICHK(bgep); 670 ddi_put32(bgep->io_handle, 671 PIO_ADDR(bgep, regno), (uint32_t)(data >> 32)); 672 } else { 673 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 674 } 675 #else 676 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 677 #endif 678 679 BGE_PCICHK(bgep); 680 } 681 682 /* 683 * The DDI doesn't provide get/put functions for 128 bit data 684 * so we put RCBs out as two 64-bit chunks instead. 685 */ 686 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 687 #pragma inline(bge_reg_putrcb) 688 689 static void 690 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 691 { 692 uint64_t *p; 693 694 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 695 (void *)bgep, addr, rcbp->host_ring_addr, 696 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 697 698 ASSERT((addr % sizeof (*rcbp)) == 0); 699 700 p = (void *)rcbp; 701 bge_reg_put64(bgep, addr, *p++); 702 bge_reg_put64(bgep, addr+8, *p); 703 } 704 705 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 706 #pragma inline(bge_mbx_put) 707 708 void 709 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 710 { 711 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 712 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 713 714 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 715 (void *)bgep, regno, data)); 716 717 /* 718 * Mailbox registers are nominally 64 bits on the 5701, but 719 * the MSW isn't used. On the 5703, they're only 32 bits 720 * anyway. So here we just write the lower(!) 32 bits - 721 * remembering that the chip is big-endian, even though the 722 * PCI bus is little-endian ... 723 */ 724 #ifdef _BIG_ENDIAN 725 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 726 #else 727 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 728 #endif /* _BIG_ENDIAN */ 729 BGE_PCICHK(bgep); 730 } 731 732 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 733 #pragma inline(bge_mbx_get) 734 735 uint32_t 736 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 737 { 738 uint32_t val32; 739 740 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 741 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 742 743 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 744 (void *)bgep, regno)); 745 746 #ifdef _BIG_ENDIAN 747 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 748 #else 749 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 750 #endif /* _BIG_ENDIAN */ 751 BGE_PCICHK(bgep); 752 753 return (val32); 754 } 755 756 757 #if BGE_DEBUGGING 758 759 void bge_led_mark(bge_t *bgep); 760 #pragma no_inline(bge_led_mark) 761 762 void 763 bge_led_mark(bge_t *bgep) 764 { 765 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 766 LED_CONTROL_1000MBPS_LED | 767 LED_CONTROL_100MBPS_LED | 768 LED_CONTROL_10MBPS_LED; 769 770 /* 771 * Blink all three LINK LEDs on simultaneously, then all off, 772 * then restore to automatic hardware control. This is used 773 * in laboratory testing to trigger a logic analyser or scope. 774 */ 775 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 776 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 777 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 778 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 779 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 780 } 781 782 #endif /* BGE_DEBUGGING */ 783 784 /* 785 * NIC on-chip memory access routines 786 * 787 * Only 32K of NIC memory is visible at a time, controlled by the 788 * Memory Window Base Address Register (in PCI config space). Once 789 * this is set, the 32K region of NIC-local memory that it refers 790 * to can be directly addressed in the upper 32K of the 64K of PCI 791 * memory space used for the device. 792 */ 793 794 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 795 #pragma inline(bge_nic_setwin) 796 797 static void 798 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 799 { 800 chip_id_t *cidp; 801 802 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 803 (void *)bgep, base)); 804 805 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 806 807 /* 808 * Don't do repeated zero data writes, 809 * if the device is BCM5714C/15C. 810 */ 811 cidp = &bgep->chipid; 812 if ((cidp->device == DEVICE_ID_5714C) || 813 (cidp->device == DEVICE_ID_5715C)) { 814 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 815 return; 816 /* Adjust lastWriteZeroData */ 817 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 818 B_TRUE : B_FALSE); 819 } 820 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 821 } 822 823 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 824 #pragma inline(bge_nic_get32) 825 826 static uint32_t 827 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 828 { 829 uint32_t data; 830 831 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 832 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 833 /* workaround for word swap error */ 834 if (addr & 4) 835 addr = addr - 4; 836 else 837 addr = addr + 4; 838 } 839 #endif 840 841 #ifdef __sparc 842 data = bge_nic_read32(bgep, addr); 843 #else 844 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 845 addr &= MWBAR_GRANULE_MASK; 846 addr += NIC_MEM_WINDOW_OFFSET; 847 848 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 849 #endif 850 851 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 852 (void *)bgep, addr, data)); 853 854 return (data); 855 } 856 857 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 858 #pragma inline(bge_nic_put32) 859 860 void 861 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 862 { 863 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 864 (void *)bgep, addr, data)); 865 866 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 867 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 868 /* workaround for word swap error */ 869 if (addr & 4) 870 addr = addr - 4; 871 else 872 addr = addr + 4; 873 } 874 #endif 875 876 #ifdef __sparc 877 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 878 data = LE_32(data); 879 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 880 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 881 #else 882 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 883 addr &= MWBAR_GRANULE_MASK; 884 addr += NIC_MEM_WINDOW_OFFSET; 885 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 886 BGE_PCICHK(bgep); 887 #endif 888 } 889 890 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 891 #pragma inline(bge_nic_get64) 892 893 static uint64_t 894 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 895 { 896 uint64_t data; 897 898 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 899 addr &= MWBAR_GRANULE_MASK; 900 addr += NIC_MEM_WINDOW_OFFSET; 901 902 #ifdef __amd64 903 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 904 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 905 data <<= 32; 906 data |= ddi_get32(bgep->io_handle, 907 PIO_ADDR(bgep, addr + 4)); 908 } else { 909 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 910 } 911 #elif defined(__sparc) 912 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 913 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 914 data <<= 32; 915 data |= ddi_get32(bgep->io_handle, 916 PIO_ADDR(bgep, addr + 4)); 917 } else { 918 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 919 } 920 #else 921 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 922 #endif 923 924 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 925 (void *)bgep, addr, data)); 926 927 return (data); 928 } 929 930 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 931 #pragma inline(bge_nic_put64) 932 933 static void 934 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 935 { 936 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 937 (void *)bgep, addr, data)); 938 939 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 940 addr &= MWBAR_GRANULE_MASK; 941 addr += NIC_MEM_WINDOW_OFFSET; 942 943 #ifdef __amd64 944 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 945 ddi_put32(bgep->io_handle, 946 PIO_ADDR(bgep, addr), (uint32_t)data); 947 BGE_PCICHK(bgep); 948 ddi_put32(bgep->io_handle, 949 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 950 } else { 951 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 952 } 953 #elif defined(__sparc) 954 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 955 ddi_put32(bgep->io_handle, 956 PIO_ADDR(bgep, addr + 4), (uint32_t)data); 957 BGE_PCICHK(bgep); 958 ddi_put32(bgep->io_handle, 959 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32)); 960 } else { 961 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 962 } 963 #else 964 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 965 #endif 966 967 BGE_PCICHK(bgep); 968 } 969 970 /* 971 * The DDI doesn't provide get/put functions for 128 bit data 972 * so we put RCBs out as two 64-bit chunks instead. 973 */ 974 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 975 #pragma inline(bge_nic_putrcb) 976 977 static void 978 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 979 { 980 uint64_t *p; 981 982 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 983 (void *)bgep, addr, rcbp->host_ring_addr, 984 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 985 986 ASSERT((addr % sizeof (*rcbp)) == 0); 987 988 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 989 addr &= MWBAR_GRANULE_MASK; 990 addr += NIC_MEM_WINDOW_OFFSET; 991 992 p = (void *)rcbp; 993 #ifdef __amd64 994 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 995 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 996 (uint32_t)(*p)); 997 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 998 (uint32_t)(*p >> 32)); 999 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1000 (uint32_t)(*(p + 1))); 1001 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1002 (uint32_t)(*p >> 32)); 1003 1004 } else { 1005 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1006 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1007 } 1008 #elif defined(__sparc) 1009 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 1010 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1011 (uint32_t)(*p)); 1012 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1013 (uint32_t)(*p >> 32)); 1014 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1015 (uint32_t)(*(p + 1))); 1016 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1017 (uint32_t)(*p >> 32)); 1018 } else { 1019 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1020 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1021 } 1022 #else 1023 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1024 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1025 #endif 1026 1027 BGE_PCICHK(bgep); 1028 } 1029 1030 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1031 #pragma inline(bge_nic_zero) 1032 1033 static void 1034 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1035 { 1036 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1037 (void *)bgep, addr, nbytes)); 1038 1039 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1040 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1041 1042 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1043 addr &= MWBAR_GRANULE_MASK; 1044 addr += NIC_MEM_WINDOW_OFFSET; 1045 1046 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1047 nbytes, 1, DDI_DATA_SZ08_ACC); 1048 BGE_PCICHK(bgep); 1049 } 1050 1051 /* 1052 * MII (PHY) register get/set access routines 1053 * 1054 * These use the chip's MII auto-access method, controlled by the 1055 * MII Communication register at 0x044c, so the CPU doesn't have 1056 * to fiddle with the individual bits. 1057 */ 1058 1059 #undef BGE_DBG 1060 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1061 1062 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1063 uint16_t data, uint32_t cmd); 1064 #pragma no_inline(bge_mii_access) 1065 1066 static uint16_t 1067 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1068 { 1069 uint32_t timeout; 1070 uint32_t regval1; 1071 uint32_t regval2; 1072 1073 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1074 (void *)bgep, regno, data, cmd)); 1075 1076 ASSERT(mutex_owned(bgep->genlock)); 1077 1078 /* 1079 * Assemble the command ... 1080 */ 1081 cmd |= data << MI_COMMS_DATA_SHIFT; 1082 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1083 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1084 cmd |= MI_COMMS_START; 1085 1086 /* 1087 * Wait for any command already in progress ... 1088 * 1089 * Note: this *shouldn't* ever find that there is a command 1090 * in progress, because we already hold the <genlock> mutex. 1091 * Nonetheless, we have sometimes seen the MI_COMMS_START 1092 * bit set here -- it seems that the chip can initiate MII 1093 * accesses internally, even with polling OFF. 1094 */ 1095 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1096 for (timeout = 100; ; ) { 1097 if ((regval2 & MI_COMMS_START) == 0) { 1098 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1099 break; 1100 } 1101 if (--timeout == 0) 1102 break; 1103 drv_usecwait(10); 1104 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1105 } 1106 1107 if (timeout == 0) 1108 return ((uint16_t)~0u); 1109 1110 if (timeout != 100) 1111 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1112 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1113 cmd, 10*(100-timeout), regval1, regval2)); 1114 1115 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1116 for (timeout = 1000; ; ) { 1117 if ((regval1 & MI_COMMS_START) == 0) 1118 break; 1119 if (--timeout == 0) 1120 break; 1121 drv_usecwait(10); 1122 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1123 } 1124 1125 /* 1126 * Drop out early if the READ FAILED bit is set -- this chip 1127 * could be a 5703/4S, with a SerDes instead of a PHY! 1128 */ 1129 if (regval2 & MI_COMMS_READ_FAILED) 1130 return ((uint16_t)~0u); 1131 1132 if (timeout == 0) 1133 return ((uint16_t)~0u); 1134 1135 /* 1136 * The PRM says to wait 5us after seeing the START bit clear 1137 * and then re-read the register to get the final value of the 1138 * data field, in order to avoid a race condition where the 1139 * START bit is clear but the data field isn't yet valid. 1140 * 1141 * Note: we don't actually seem to be encounter this race; 1142 * except when the START bit is seen set again (see below), 1143 * the data field doesn't change during this 5us interval. 1144 */ 1145 drv_usecwait(5); 1146 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1147 1148 /* 1149 * Unfortunately, when following the PRMs instructions above, 1150 * we have occasionally seen the START bit set again(!) in the 1151 * value read after the 5us delay. This seems to be due to the 1152 * chip autonomously starting another MII access internally. 1153 * In such cases, the command/data/etc fields relate to the 1154 * internal command, rather than the one that we thought had 1155 * just finished. So in this case, we fall back to returning 1156 * the data from the original read that showed START clear. 1157 */ 1158 if (regval2 & MI_COMMS_START) { 1159 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1160 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1161 cmd, regval1, regval2)); 1162 regval2 = regval1; 1163 } 1164 1165 if (regval2 & MI_COMMS_START) 1166 return ((uint16_t)~0u); 1167 1168 if (regval2 & MI_COMMS_READ_FAILED) 1169 return ((uint16_t)~0u); 1170 1171 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1172 } 1173 1174 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1175 #pragma no_inline(bge_mii_get16) 1176 1177 uint16_t 1178 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1179 { 1180 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1181 (void *)bgep, regno)); 1182 1183 ASSERT(mutex_owned(bgep->genlock)); 1184 1185 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1186 (regno == MII_MSCONTROL))) 1187 return (0); 1188 1189 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1190 } 1191 1192 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1193 #pragma no_inline(bge_mii_put16) 1194 1195 void 1196 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1197 { 1198 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1199 (void *)bgep, regno, data)); 1200 1201 ASSERT(mutex_owned(bgep->genlock)); 1202 1203 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1204 (regno == MII_MSCONTROL))) 1205 return; 1206 1207 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1208 } 1209 1210 #undef BGE_DBG 1211 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1212 1213 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1214 1215 /* 1216 * Basic SEEPROM get/set access routine 1217 * 1218 * This uses the chip's SEEPROM auto-access method, controlled by the 1219 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1220 * doesn't have to fiddle with the individual bits. 1221 * 1222 * The caller should hold <genlock> and *also* have already acquired 1223 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1224 * 1225 * Return value: 1226 * 0 on success, 1227 * ENODATA on access timeout (maybe retryable: device may just be busy) 1228 * EPROTO on other h/w or s/w errors. 1229 * 1230 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1231 * from a (successful) SEEPROM_ACCESS_READ. 1232 */ 1233 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1234 uint32_t *dp); 1235 #pragma no_inline(bge_seeprom_access) 1236 1237 static int 1238 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1239 { 1240 uint32_t tries; 1241 uint32_t regval; 1242 1243 ASSERT(mutex_owned(bgep->genlock)); 1244 1245 /* 1246 * On the newer chips that support both SEEPROM & Flash, we need 1247 * to specifically enable SEEPROM access (Flash is the default). 1248 * On older chips, we don't; SEEPROM is the only NVtype supported, 1249 * and the NVM control registers don't exist ... 1250 */ 1251 switch (bgep->chipid.nvtype) { 1252 case BGE_NVTYPE_NONE: 1253 case BGE_NVTYPE_UNKNOWN: 1254 _NOTE(NOTREACHED) 1255 case BGE_NVTYPE_SEEPROM: 1256 break; 1257 1258 case BGE_NVTYPE_LEGACY_SEEPROM: 1259 case BGE_NVTYPE_UNBUFFERED_FLASH: 1260 case BGE_NVTYPE_BUFFERED_FLASH: 1261 default: 1262 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1263 NVM_CFG1_LEGACY_SEEPROM_MODE); 1264 break; 1265 } 1266 1267 /* 1268 * Check there's no command in progress. 1269 * 1270 * Note: this *shouldn't* ever find that there is a command 1271 * in progress, because we already hold the <genlock> mutex. 1272 * Also, to ensure we don't have a conflict with the chip's 1273 * internal firmware or a process accessing the same (shared) 1274 * SEEPROM through the other port of a 5704, we've already 1275 * been through the "software arbitration" protocol. 1276 * So this is just a final consistency check: we shouldn't 1277 * see EITHER the START bit (command started but not complete) 1278 * OR the COMPLETE bit (command completed but not cleared). 1279 */ 1280 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1281 if (regval & SEEPROM_ACCESS_START) 1282 return (EPROTO); 1283 if (regval & SEEPROM_ACCESS_COMPLETE) 1284 return (EPROTO); 1285 1286 /* 1287 * Assemble the command ... 1288 */ 1289 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1290 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1291 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1292 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1293 cmd |= SEEPROM_ACCESS_START; 1294 cmd |= SEEPROM_ACCESS_COMPLETE; 1295 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1296 1297 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1298 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1299 1300 /* 1301 * By observation, a successful access takes ~20us on a 5703/4, 1302 * but apparently much longer (up to 1000us) on the obsolescent 1303 * BCM5700/BCM5701. We want to be sure we don't get any false 1304 * timeouts here; but OTOH, we don't want a bogus access to lock 1305 * out interrupts for longer than necessary. So we'll allow up 1306 * to 1000us ... 1307 */ 1308 for (tries = 0; tries < 1000; ++tries) { 1309 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1310 if (regval & SEEPROM_ACCESS_COMPLETE) 1311 break; 1312 drv_usecwait(1); 1313 } 1314 1315 if (regval & SEEPROM_ACCESS_COMPLETE) { 1316 /* 1317 * All OK; read the SEEPROM data register, then write back 1318 * the value read from the address register in order to 1319 * clear the <complete> bit and leave the SEEPROM access 1320 * state machine idle, ready for the next access ... 1321 */ 1322 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1323 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1324 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1325 return (0); 1326 } 1327 1328 /* 1329 * Hmm ... what happened here? 1330 * 1331 * Most likely, the user addressed a non-existent SEEPROM. Or 1332 * maybe the SEEPROM was busy internally (e.g. processing a write) 1333 * and didn't respond to being addressed. Either way, it's left 1334 * the SEEPROM access state machine wedged. So we'll reset it 1335 * before we leave, so it's ready for next time ... 1336 */ 1337 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1338 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1339 return (ENODATA); 1340 } 1341 1342 /* 1343 * Basic Flash get/set access routine 1344 * 1345 * These use the chip's Flash auto-access method, controlled by the 1346 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1347 * fiddle with the individual bits. 1348 * 1349 * The caller should hold <genlock> and *also* have already acquired 1350 * the right to access the Flash, via bge_nvmem_acquire() above. 1351 * 1352 * Return value: 1353 * 0 on success, 1354 * ENODATA on access timeout (maybe retryable: device may just be busy) 1355 * ENODEV if the NVmem device is missing or otherwise unusable 1356 * 1357 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1358 * from a (successful) NVM_FLASH_CMD_RD. 1359 */ 1360 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1361 uint32_t *dp); 1362 #pragma no_inline(bge_flash_access) 1363 1364 static int 1365 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1366 { 1367 uint32_t tries; 1368 uint32_t regval; 1369 1370 ASSERT(mutex_owned(bgep->genlock)); 1371 1372 /* 1373 * On the newer chips that support both SEEPROM & Flash, we need 1374 * to specifically disable SEEPROM access while accessing Flash. 1375 * The older chips don't support Flash, and the NVM registers don't 1376 * exist, so we shouldn't be here at all! 1377 */ 1378 switch (bgep->chipid.nvtype) { 1379 case BGE_NVTYPE_NONE: 1380 case BGE_NVTYPE_UNKNOWN: 1381 _NOTE(NOTREACHED) 1382 case BGE_NVTYPE_SEEPROM: 1383 return (ENODEV); 1384 1385 case BGE_NVTYPE_LEGACY_SEEPROM: 1386 case BGE_NVTYPE_UNBUFFERED_FLASH: 1387 case BGE_NVTYPE_BUFFERED_FLASH: 1388 default: 1389 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1390 NVM_CFG1_LEGACY_SEEPROM_MODE); 1391 break; 1392 } 1393 1394 /* 1395 * Assemble the command ... 1396 */ 1397 addr &= NVM_FLASH_ADDR_MASK; 1398 cmd |= NVM_FLASH_CMD_DOIT; 1399 cmd |= NVM_FLASH_CMD_FIRST; 1400 cmd |= NVM_FLASH_CMD_LAST; 1401 cmd |= NVM_FLASH_CMD_DONE; 1402 1403 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1404 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1405 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1406 1407 /* 1408 * Allow up to 1000ms ... 1409 */ 1410 for (tries = 0; tries < 1000; ++tries) { 1411 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1412 if (regval & NVM_FLASH_CMD_DONE) 1413 break; 1414 drv_usecwait(1); 1415 } 1416 1417 if (regval & NVM_FLASH_CMD_DONE) { 1418 /* 1419 * All OK; read the data from the Flash read register 1420 */ 1421 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1422 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1423 return (0); 1424 } 1425 1426 /* 1427 * Hmm ... what happened here? 1428 * 1429 * Most likely, the user addressed a non-existent Flash. Or 1430 * maybe the Flash was busy internally (e.g. processing a write) 1431 * and didn't respond to being addressed. Either way, there's 1432 * nothing we can here ... 1433 */ 1434 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1435 return (ENODATA); 1436 } 1437 1438 /* 1439 * The next two functions regulate access to the NVram (if fitted). 1440 * 1441 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1442 * (SPI) interface, but they can be accessed through either port. These 1443 * are managed by different instance of this driver and have no software 1444 * state in common. 1445 * 1446 * In addition (and even on a single core chip) the chip's internal 1447 * firmware can access the SEEPROM/Flash, most notably after a RESET 1448 * when it may download code to run internally. 1449 * 1450 * So we need to arbitrate between these various software agents. For 1451 * this purpose, the chip provides the Software Arbitration Register, 1452 * which implements hardware(!) arbitration. 1453 * 1454 * This functionality didn't exist on older (5700/5701) chips, so there's 1455 * nothing we can do by way of arbitration on those; also, if there's no 1456 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1457 * nothing to do. 1458 * 1459 * The internal firmware appears to use Request 0, which is the highest 1460 * priority. So we'd like to use Request 2, leaving one higher and one 1461 * lower for any future developments ... but apparently this doesn't 1462 * always work. So for now, the code uses Request 1 ;-( 1463 */ 1464 1465 #define NVM_READ_REQ NVM_READ_REQ1 1466 #define NVM_RESET_REQ NVM_RESET_REQ1 1467 #define NVM_SET_REQ NVM_SET_REQ1 1468 1469 static void bge_nvmem_relinquish(bge_t *bgep); 1470 #pragma no_inline(bge_nvmem_relinquish) 1471 1472 static void 1473 bge_nvmem_relinquish(bge_t *bgep) 1474 { 1475 ASSERT(mutex_owned(bgep->genlock)); 1476 1477 switch (bgep->chipid.nvtype) { 1478 case BGE_NVTYPE_NONE: 1479 case BGE_NVTYPE_UNKNOWN: 1480 _NOTE(NOTREACHED) 1481 return; 1482 1483 case BGE_NVTYPE_SEEPROM: 1484 /* 1485 * No arbitration performed, no release needed 1486 */ 1487 return; 1488 1489 case BGE_NVTYPE_LEGACY_SEEPROM: 1490 case BGE_NVTYPE_UNBUFFERED_FLASH: 1491 case BGE_NVTYPE_BUFFERED_FLASH: 1492 default: 1493 break; 1494 } 1495 1496 /* 1497 * Our own request should be present (whether or not granted) ... 1498 */ 1499 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1500 1501 /* 1502 * ... this will make it go away. 1503 */ 1504 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1505 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1506 } 1507 1508 /* 1509 * Arbitrate for access to the NVmem, if necessary 1510 * 1511 * Return value: 1512 * 0 on success 1513 * EAGAIN if the device is in use (retryable) 1514 * ENODEV if the NVmem device is missing or otherwise unusable 1515 */ 1516 static int bge_nvmem_acquire(bge_t *bgep); 1517 #pragma no_inline(bge_nvmem_acquire) 1518 1519 static int 1520 bge_nvmem_acquire(bge_t *bgep) 1521 { 1522 uint32_t regval; 1523 uint32_t tries; 1524 1525 ASSERT(mutex_owned(bgep->genlock)); 1526 1527 switch (bgep->chipid.nvtype) { 1528 case BGE_NVTYPE_NONE: 1529 case BGE_NVTYPE_UNKNOWN: 1530 /* 1531 * Access denied: no (recognisable) device fitted 1532 */ 1533 return (ENODEV); 1534 1535 case BGE_NVTYPE_SEEPROM: 1536 /* 1537 * Access granted: no arbitration needed (or possible) 1538 */ 1539 return (0); 1540 1541 case BGE_NVTYPE_LEGACY_SEEPROM: 1542 case BGE_NVTYPE_UNBUFFERED_FLASH: 1543 case BGE_NVTYPE_BUFFERED_FLASH: 1544 default: 1545 /* 1546 * Access conditional: conduct arbitration protocol 1547 */ 1548 break; 1549 } 1550 1551 /* 1552 * We're holding the per-port mutex <genlock>, so no-one other 1553 * thread can be attempting to access the NVmem through *this* 1554 * port. But it could be in use by the *other* port (of a 5704), 1555 * or by the chip's internal firmware, so we have to go through 1556 * the full (hardware) arbitration protocol ... 1557 * 1558 * Note that *because* we're holding <genlock>, the interrupt handler 1559 * won't be able to progress. So we're only willing to spin for a 1560 * fairly short time. Specifically: 1561 * 1562 * We *must* wait long enough for the hardware to resolve all 1563 * requests and determine the winner. Fortunately, this is 1564 * "almost instantaneous", even as observed by GHz CPUs. 1565 * 1566 * A successful access by another Solaris thread (via either 1567 * port) typically takes ~20us. So waiting a bit longer than 1568 * that will give a good chance of success, if the other user 1569 * *is* another thread on the other port. 1570 * 1571 * However, the internal firmware can hold on to the NVmem 1572 * for *much* longer: at least 10 milliseconds just after a 1573 * RESET, and maybe even longer if the NVmem actually contains 1574 * code to download and run on the internal CPUs. 1575 * 1576 * So, we'll allow 50us; if that's not enough then it's up to the 1577 * caller to retry later (hence the choice of return code EAGAIN). 1578 */ 1579 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1580 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1581 1582 for (tries = 0; tries < 50; ++tries) { 1583 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1584 if (regval & NVM_WON_REQ1) 1585 break; 1586 drv_usecwait(1); 1587 } 1588 1589 if (regval & NVM_WON_REQ1) { 1590 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1591 return (0); 1592 } 1593 1594 /* 1595 * Somebody else must be accessing the NVmem, so abandon our 1596 * attempt take control of it. The caller can try again later ... 1597 */ 1598 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1599 bge_nvmem_relinquish(bgep); 1600 return (EAGAIN); 1601 } 1602 1603 /* 1604 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1605 * write protect line in such a way that the NVmem is protected when 1606 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1607 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1608 * 1609 * Note: there's only one set of GPIO pins on a 5704, even though they 1610 * can be accessed through either port. So the chip has to resolve what 1611 * happens if the two ports program a single pin differently ... the rule 1612 * it uses is that if the ports disagree about the *direction* of a pin, 1613 * "output" wins over "input", but if they disagree about its *value* as 1614 * an output, then the pin is TRISTATED instead! In such a case, no-one 1615 * wins, and the external signal does whatever the external circuitry 1616 * defines as the default -- which we've assumed is the PROTECTED state. 1617 * So, we always change GPIO1 back to being an *input* whenever we're not 1618 * specifically using it to unprotect the NVmem. This allows either port 1619 * to update the NVmem, although obviously only one at a time! 1620 * 1621 * The caller should hold <genlock> and *also* have already acquired the 1622 * right to access the NVmem, via bge_nvmem_acquire() above. 1623 */ 1624 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1625 #pragma inline(bge_nvmem_protect) 1626 1627 static void 1628 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1629 { 1630 uint32_t regval; 1631 1632 ASSERT(mutex_owned(bgep->genlock)); 1633 1634 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1635 if (protect) { 1636 regval |= MLCR_MISC_PINS_OUTPUT_1; 1637 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1638 } else { 1639 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1640 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1641 } 1642 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1643 } 1644 1645 /* 1646 * Now put it all together ... 1647 * 1648 * Try to acquire control of the NVmem; if successful, then: 1649 * unprotect it (if we want to write to it) 1650 * perform the requested access 1651 * reprotect it (after a write) 1652 * relinquish control 1653 * 1654 * Return value: 1655 * 0 on success, 1656 * EAGAIN if the device is in use (retryable) 1657 * ENODATA on access timeout (maybe retryable: device may just be busy) 1658 * ENODEV if the NVmem device is missing or otherwise unusable 1659 * EPROTO on other h/w or s/w errors. 1660 */ 1661 static int 1662 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1663 { 1664 int err; 1665 1666 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1667 switch (cmd) { 1668 case BGE_SEE_READ: 1669 err = bge_seeprom_access(bgep, 1670 SEEPROM_ACCESS_READ, addr, dp); 1671 break; 1672 1673 case BGE_SEE_WRITE: 1674 bge_nvmem_protect(bgep, B_FALSE); 1675 err = bge_seeprom_access(bgep, 1676 SEEPROM_ACCESS_WRITE, addr, dp); 1677 bge_nvmem_protect(bgep, B_TRUE); 1678 break; 1679 1680 case BGE_FLASH_READ: 1681 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1682 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1683 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1684 bge_reg_set32(bgep, NVM_ACCESS_REG, 1685 NVM_ACCESS_ENABLE); 1686 } 1687 err = bge_flash_access(bgep, 1688 NVM_FLASH_CMD_RD, addr, dp); 1689 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1690 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1691 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1692 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1693 NVM_ACCESS_ENABLE); 1694 } 1695 break; 1696 1697 case BGE_FLASH_WRITE: 1698 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1699 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1700 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1701 bge_reg_set32(bgep, NVM_ACCESS_REG, 1702 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1703 } 1704 bge_nvmem_protect(bgep, B_FALSE); 1705 err = bge_flash_access(bgep, 1706 NVM_FLASH_CMD_WR, addr, dp); 1707 bge_nvmem_protect(bgep, B_TRUE); 1708 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1709 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1710 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1711 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1712 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1713 } 1714 1715 break; 1716 1717 default: 1718 _NOTE(NOTREACHED) 1719 break; 1720 } 1721 bge_nvmem_relinquish(bgep); 1722 } 1723 1724 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1725 return (err); 1726 } 1727 1728 /* 1729 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1730 */ 1731 static uint64_t bge_get_nvmac(bge_t *bgep); 1732 #pragma no_inline(bge_get_nvmac) 1733 1734 static uint64_t 1735 bge_get_nvmac(bge_t *bgep) 1736 { 1737 uint32_t mac_high; 1738 uint32_t mac_low; 1739 uint32_t addr; 1740 uint32_t cmd; 1741 uint64_t mac; 1742 1743 BGE_TRACE(("bge_get_nvmac($%p)", 1744 (void *)bgep)); 1745 1746 switch (bgep->chipid.nvtype) { 1747 case BGE_NVTYPE_NONE: 1748 case BGE_NVTYPE_UNKNOWN: 1749 default: 1750 return (0ULL); 1751 1752 case BGE_NVTYPE_SEEPROM: 1753 case BGE_NVTYPE_LEGACY_SEEPROM: 1754 cmd = BGE_SEE_READ; 1755 break; 1756 1757 case BGE_NVTYPE_UNBUFFERED_FLASH: 1758 case BGE_NVTYPE_BUFFERED_FLASH: 1759 cmd = BGE_FLASH_READ; 1760 break; 1761 } 1762 1763 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 1764 addr = NVMEM_DATA_MAC_ADDRESS_5906; 1765 else 1766 addr = NVMEM_DATA_MAC_ADDRESS; 1767 1768 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1769 return (0ULL); 1770 addr += 4; 1771 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1772 return (0ULL); 1773 1774 /* 1775 * The Broadcom chip is natively BIG-endian, so that's how the 1776 * MAC address is represented in NVmem. We may need to swap it 1777 * around on a little-endian host ... 1778 */ 1779 #ifdef _BIG_ENDIAN 1780 mac = mac_high; 1781 mac = mac << 32; 1782 mac |= mac_low; 1783 #else 1784 mac = BGE_BSWAP_32(mac_high); 1785 mac = mac << 32; 1786 mac |= BGE_BSWAP_32(mac_low); 1787 #endif /* _BIG_ENDIAN */ 1788 1789 return (mac); 1790 } 1791 1792 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1793 1794 /* 1795 * Dummy version for when we're not supporting NVmem access 1796 */ 1797 static uint64_t bge_get_nvmac(bge_t *bgep); 1798 #pragma inline(bge_get_nvmac) 1799 1800 static uint64_t 1801 bge_get_nvmac(bge_t *bgep) 1802 { 1803 _NOTE(ARGUNUSED(bgep)) 1804 return (0ULL); 1805 } 1806 1807 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1808 1809 /* 1810 * Determine the type of NVmem that is (or may be) attached to this chip, 1811 */ 1812 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1813 #pragma no_inline(bge_nvmem_id) 1814 1815 static enum bge_nvmem_type 1816 bge_nvmem_id(bge_t *bgep) 1817 { 1818 enum bge_nvmem_type nvtype; 1819 uint32_t config1; 1820 1821 BGE_TRACE(("bge_nvmem_id($%p)", 1822 (void *)bgep)); 1823 1824 switch (bgep->chipid.device) { 1825 default: 1826 /* 1827 * We shouldn't get here; it means we don't recognise 1828 * the chip, which means we don't know how to determine 1829 * what sort of NVmem (if any) it has. So we'll say 1830 * NONE, to disable the NVmem access code ... 1831 */ 1832 nvtype = BGE_NVTYPE_NONE; 1833 break; 1834 1835 case DEVICE_ID_5700: 1836 case DEVICE_ID_5700x: 1837 case DEVICE_ID_5701: 1838 /* 1839 * These devices support *only* SEEPROMs 1840 */ 1841 nvtype = BGE_NVTYPE_SEEPROM; 1842 break; 1843 1844 case DEVICE_ID_5702: 1845 case DEVICE_ID_5702fe: 1846 case DEVICE_ID_5703C: 1847 case DEVICE_ID_5703S: 1848 case DEVICE_ID_5704C: 1849 case DEVICE_ID_5704S: 1850 case DEVICE_ID_5704: 1851 case DEVICE_ID_5705M: 1852 case DEVICE_ID_5705C: 1853 case DEVICE_ID_5705_2: 1854 case DEVICE_ID_5780: 1855 case DEVICE_ID_5782: 1856 case DEVICE_ID_5787: 1857 case DEVICE_ID_5787M: 1858 case DEVICE_ID_5788: 1859 case DEVICE_ID_5789: 1860 case DEVICE_ID_5751: 1861 case DEVICE_ID_5751M: 1862 case DEVICE_ID_5752: 1863 case DEVICE_ID_5752M: 1864 case DEVICE_ID_5754: 1865 case DEVICE_ID_5755: 1866 case DEVICE_ID_5755M: 1867 case DEVICE_ID_5756M: 1868 case DEVICE_ID_5721: 1869 case DEVICE_ID_5722: 1870 case DEVICE_ID_5723: 1871 case DEVICE_ID_5761: 1872 case DEVICE_ID_5761E: 1873 case DEVICE_ID_5714C: 1874 case DEVICE_ID_5714S: 1875 case DEVICE_ID_5715C: 1876 case DEVICE_ID_5715S: 1877 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1878 if (config1 & NVM_CFG1_FLASH_MODE) 1879 if (config1 & NVM_CFG1_BUFFERED_MODE) 1880 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1881 else 1882 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1883 else 1884 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1885 break; 1886 case DEVICE_ID_5906: 1887 case DEVICE_ID_5906M: 1888 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1889 break; 1890 } 1891 1892 return (nvtype); 1893 } 1894 1895 #undef BGE_DBG 1896 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1897 1898 static void 1899 bge_init_recv_rule(bge_t *bgep) 1900 { 1901 bge_recv_rule_t *rulep = bgep->recv_rules; 1902 uint32_t i; 1903 1904 /* 1905 * Initialize receive rule registers. 1906 * Note that rules may persist across each bge_m_start/stop() call. 1907 */ 1908 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1909 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1910 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1911 } 1912 } 1913 1914 /* 1915 * Using the values captured by bge_chip_cfg_init(), and additional probes 1916 * as required, characterise the chip fully: determine the label by which 1917 * to refer to this chip, the correct settings for various registers, and 1918 * of course whether the device and/or subsystem are supported! 1919 */ 1920 int bge_chip_id_init(bge_t *bgep); 1921 #pragma no_inline(bge_chip_id_init) 1922 1923 int 1924 bge_chip_id_init(bge_t *bgep) 1925 { 1926 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1927 boolean_t sys_ok; 1928 boolean_t dev_ok; 1929 chip_id_t *cidp; 1930 uint32_t subid; 1931 char *devname; 1932 char *sysname; 1933 int *ids; 1934 int err; 1935 uint_t i; 1936 1937 sys_ok = dev_ok = B_FALSE; 1938 cidp = &bgep->chipid; 1939 1940 /* 1941 * Check the PCI device ID to determine the generic chip type and 1942 * select parameters that depend on this. 1943 * 1944 * Note: because the SPARC platforms in general don't fit the 1945 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1946 * as zero - which is why we use <asic_rev> rather than <revision> 1947 * below ... 1948 * 1949 * Note: in general we can't distinguish between the Copper/SerDes 1950 * versions by ID alone, as some Copper devices (e.g. some but not 1951 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1952 * treat them the same here, and the MII code works out the media 1953 * type later on ... 1954 */ 1955 cidp->mbuf_base = bge_mbuf_pool_base; 1956 cidp->mbuf_length = bge_mbuf_pool_len; 1957 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1958 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1959 cidp->pci_type = BGE_PCI_X; 1960 cidp->statistic_type = BGE_STAT_BLK; 1961 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1962 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1963 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1964 cidp->rx_ticks_norm = bge_rx_ticks_norm; 1965 cidp->rx_count_norm = bge_rx_count_norm; 1966 cidp->tx_ticks_norm = bge_tx_ticks_norm; 1967 cidp->tx_count_norm = bge_tx_count_norm; 1968 1969 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1970 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1971 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1972 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1973 1974 cidp->msi_enabled = B_FALSE; 1975 1976 switch (cidp->device) { 1977 case DEVICE_ID_5700: 1978 case DEVICE_ID_5700x: 1979 cidp->chip_label = 5700; 1980 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1981 break; 1982 1983 case DEVICE_ID_5701: 1984 cidp->chip_label = 5701; 1985 dev_ok = B_TRUE; 1986 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1987 break; 1988 1989 case DEVICE_ID_5702: 1990 case DEVICE_ID_5702fe: 1991 cidp->chip_label = 5702; 1992 dev_ok = B_TRUE; 1993 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1994 cidp->pci_type = BGE_PCI; 1995 break; 1996 1997 case DEVICE_ID_5703C: 1998 case DEVICE_ID_5703S: 1999 case DEVICE_ID_5703: 2000 /* 2001 * Revision A0 of the 5703/5793 had various errata 2002 * that we can't or don't work around, so it's not 2003 * supported, but all later versions are 2004 */ 2005 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 2006 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 2007 dev_ok = B_TRUE; 2008 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2009 break; 2010 2011 case DEVICE_ID_5704C: 2012 case DEVICE_ID_5704S: 2013 case DEVICE_ID_5704: 2014 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 2015 cidp->mbuf_base = bge_mbuf_pool_base_5704; 2016 cidp->mbuf_length = bge_mbuf_pool_len_5704; 2017 dev_ok = B_TRUE; 2018 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2019 break; 2020 2021 case DEVICE_ID_5705C: 2022 case DEVICE_ID_5705M: 2023 case DEVICE_ID_5705MA3: 2024 case DEVICE_ID_5705F: 2025 case DEVICE_ID_5705_2: 2026 case DEVICE_ID_5754: 2027 if (cidp->device == DEVICE_ID_5754) { 2028 cidp->chip_label = 5754; 2029 cidp->pci_type = BGE_PCI_E; 2030 } else { 2031 cidp->chip_label = 5705; 2032 cidp->pci_type = BGE_PCI; 2033 } 2034 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2035 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2036 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2037 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2038 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2039 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2040 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2041 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2042 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2043 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2044 cidp->statistic_type = BGE_STAT_REG; 2045 dev_ok = B_TRUE; 2046 break; 2047 2048 case DEVICE_ID_5906: 2049 case DEVICE_ID_5906M: 2050 cidp->chip_label = 5906; 2051 cidp->pci_type = BGE_PCI_E; 2052 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906; 2053 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906; 2054 cidp->mbuf_hi_water = MBUF_HIWAT_5906; 2055 cidp->mbuf_base = bge_mbuf_pool_base; 2056 cidp->mbuf_length = bge_mbuf_pool_len; 2057 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2058 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2059 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2060 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2061 cidp->statistic_type = BGE_STAT_REG; 2062 dev_ok = B_TRUE; 2063 break; 2064 2065 case DEVICE_ID_5753: 2066 cidp->chip_label = 5753; 2067 cidp->pci_type = BGE_PCI_E; 2068 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2069 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2070 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2071 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2072 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2073 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2074 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2075 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2076 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2077 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2078 cidp->statistic_type = BGE_STAT_REG; 2079 dev_ok = B_TRUE; 2080 break; 2081 2082 case DEVICE_ID_5755: 2083 case DEVICE_ID_5755M: 2084 cidp->chip_label = 5755; 2085 cidp->pci_type = BGE_PCI_E; 2086 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2087 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2088 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2089 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2090 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2091 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2092 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2093 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2094 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2095 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2096 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2097 cidp->statistic_type = BGE_STAT_REG; 2098 dev_ok = B_TRUE; 2099 break; 2100 2101 case DEVICE_ID_5756M: 2102 /* 2103 * This is nearly identical to the 5755M. 2104 * (Actually reports the 5755 chip ID.) 2105 */ 2106 cidp->chip_label = 5756; 2107 cidp->pci_type = BGE_PCI_E; 2108 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2109 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2110 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2111 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2112 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2113 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2114 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2115 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2116 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2117 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2118 cidp->statistic_type = BGE_STAT_REG; 2119 dev_ok = B_TRUE; 2120 break; 2121 2122 case DEVICE_ID_5787: 2123 case DEVICE_ID_5787M: 2124 cidp->chip_label = 5787; 2125 cidp->pci_type = BGE_PCI_E; 2126 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2127 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2128 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2129 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2130 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2131 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2132 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2133 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2134 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2135 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2136 cidp->statistic_type = BGE_STAT_REG; 2137 dev_ok = B_TRUE; 2138 break; 2139 2140 case DEVICE_ID_5723: 2141 case DEVICE_ID_5761: 2142 case DEVICE_ID_5761E: 2143 cidp->chip_label = cidp->device == DEVICE_ID_5723 ? 5723: 5761; 2144 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2145 cidp->msi_enabled = bge_enable_msi; 2146 cidp->pci_type = BGE_PCI_E; 2147 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2148 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2149 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2150 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2151 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2152 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2153 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2154 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2155 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2156 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2157 cidp->statistic_type = BGE_STAT_REG; 2158 dev_ok = B_TRUE; 2159 break; 2160 2161 /* PCI-X device, identical to 5714 */ 2162 case DEVICE_ID_5780: 2163 cidp->chip_label = 5780; 2164 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2165 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2166 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2167 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2168 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2169 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2170 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2171 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2172 cidp->statistic_type = BGE_STAT_REG; 2173 dev_ok = B_TRUE; 2174 break; 2175 2176 case DEVICE_ID_5782: 2177 /* 2178 * Apart from the label, we treat this as a 5705(?) 2179 */ 2180 cidp->chip_label = 5782; 2181 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2182 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2183 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2184 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2185 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2186 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2187 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2188 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2189 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2190 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2191 cidp->statistic_type = BGE_STAT_REG; 2192 dev_ok = B_TRUE; 2193 break; 2194 2195 case DEVICE_ID_5788: 2196 /* 2197 * Apart from the label, we treat this as a 5705(?) 2198 */ 2199 cidp->chip_label = 5788; 2200 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2201 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2202 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2203 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2204 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2205 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2206 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2207 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2208 cidp->statistic_type = BGE_STAT_REG; 2209 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2210 dev_ok = B_TRUE; 2211 break; 2212 2213 case DEVICE_ID_5714C: 2214 if (cidp->revision >= REVISION_ID_5714_A2) 2215 cidp->msi_enabled = bge_enable_msi; 2216 /* FALLTHRU */ 2217 case DEVICE_ID_5714S: 2218 cidp->chip_label = 5714; 2219 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2220 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2221 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2222 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2223 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2224 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2225 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2226 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2227 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2228 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2229 cidp->pci_type = BGE_PCI_E; 2230 cidp->statistic_type = BGE_STAT_REG; 2231 dev_ok = B_TRUE; 2232 break; 2233 2234 case DEVICE_ID_5715C: 2235 case DEVICE_ID_5715S: 2236 cidp->chip_label = 5715; 2237 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2238 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2239 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2240 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2241 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2242 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2243 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2244 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2245 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2246 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2247 cidp->pci_type = BGE_PCI_E; 2248 cidp->statistic_type = BGE_STAT_REG; 2249 if (cidp->revision >= REVISION_ID_5715_A2) 2250 cidp->msi_enabled = bge_enable_msi; 2251 dev_ok = B_TRUE; 2252 break; 2253 2254 case DEVICE_ID_5721: 2255 cidp->chip_label = 5721; 2256 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2257 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2258 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2259 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2260 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2261 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2262 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2263 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2264 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2265 cidp->pci_type = BGE_PCI_E; 2266 cidp->statistic_type = BGE_STAT_REG; 2267 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2268 dev_ok = B_TRUE; 2269 break; 2270 2271 case DEVICE_ID_5722: 2272 cidp->chip_label = 5722; 2273 cidp->pci_type = BGE_PCI_E; 2274 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2275 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2276 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2277 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2278 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2279 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2280 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2281 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2282 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2283 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2284 cidp->statistic_type = BGE_STAT_REG; 2285 dev_ok = B_TRUE; 2286 break; 2287 2288 case DEVICE_ID_5751: 2289 case DEVICE_ID_5751M: 2290 cidp->chip_label = 5751; 2291 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2292 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2293 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2294 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2295 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2296 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2297 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2298 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2299 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2300 cidp->pci_type = BGE_PCI_E; 2301 cidp->statistic_type = BGE_STAT_REG; 2302 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2303 dev_ok = B_TRUE; 2304 break; 2305 2306 case DEVICE_ID_5752: 2307 case DEVICE_ID_5752M: 2308 cidp->chip_label = 5752; 2309 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2310 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2311 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2312 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2313 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2314 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2315 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2316 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2317 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2318 cidp->pci_type = BGE_PCI_E; 2319 cidp->statistic_type = BGE_STAT_REG; 2320 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2321 dev_ok = B_TRUE; 2322 break; 2323 2324 case DEVICE_ID_5789: 2325 cidp->chip_label = 5789; 2326 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2327 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2328 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2329 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2330 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2331 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2332 cidp->pci_type = BGE_PCI_E; 2333 cidp->statistic_type = BGE_STAT_REG; 2334 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2335 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2336 cidp->msi_enabled = B_TRUE; 2337 dev_ok = B_TRUE; 2338 break; 2339 2340 } 2341 2342 /* 2343 * Setup the default jumbo parameter. 2344 */ 2345 cidp->ethmax_size = ETHERMAX; 2346 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2347 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2348 2349 /* 2350 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2351 * setup below jumbo specific parameters. 2352 * 2353 * For BCM5714/5715, there is only one standard receive ring. So the 2354 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2355 * feature is enabled. 2356 */ 2357 if (!(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2358 (cidp->default_mtu > BGE_DEFAULT_MTU)) { 2359 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2360 cidp->mbuf_lo_water_rdma = 2361 RDMA_MBUF_LOWAT_5714_JUMBO; 2362 cidp->mbuf_lo_water_rmac = 2363 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2364 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2365 cidp->jumbo_slots = 0; 2366 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2367 } else { 2368 cidp->mbuf_lo_water_rdma = 2369 RDMA_MBUF_LOWAT_JUMBO; 2370 cidp->mbuf_lo_water_rmac = 2371 MAC_RX_MBUF_LOWAT_JUMBO; 2372 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2373 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2374 } 2375 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2376 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2377 cidp->ethmax_size = cidp->default_mtu + 2378 sizeof (struct ether_header); 2379 } 2380 2381 /* 2382 * Identify the NV memory type: SEEPROM or Flash? 2383 */ 2384 cidp->nvtype = bge_nvmem_id(bgep); 2385 2386 /* 2387 * Now, we want to check whether this device is part of a 2388 * supported subsystem (e.g., on the motherboard of a Sun 2389 * branded platform). 2390 * 2391 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2392 */ 2393 if (cidp->subven == VENDOR_ID_SUN) 2394 sys_ok = B_TRUE; 2395 2396 /* 2397 * Rule 2: If it's on the list on known subsystems, then it's OK. 2398 * Note: 0x14e41647 should *not* appear in the list, but the code 2399 * doesn't enforce that. 2400 */ 2401 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2402 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2403 if (err == DDI_PROP_SUCCESS) { 2404 /* 2405 * Got the list; scan for a matching subsystem vendor/device 2406 */ 2407 subid = (cidp->subven << 16) | cidp->subdev; 2408 while (i--) 2409 if (ids[i] == subid) 2410 sys_ok = B_TRUE; 2411 ddi_prop_free(ids); 2412 } 2413 2414 /* 2415 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2416 * 2417 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2418 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2419 * we have to check specially for the exact device paths to the 2420 * motherboard devices on those platforms ;-( 2421 * 2422 * Note: we can't just use the "supported-subsystems" mechanism 2423 * above, because the entry would have to be 0x14e41647 -- which 2424 * would then accept *any* plugin card that *didn't* contain a 2425 * (valid) SEEPROM ;-( 2426 */ 2427 sysname = ddi_node_name(ddi_root_node()); 2428 devname = ddi_pathname(bgep->devinfo, buf); 2429 ASSERT(strlen(devname) > 0); 2430 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2431 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2432 sys_ok = B_TRUE; 2433 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2434 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2435 sys_ok = B_TRUE; 2436 2437 /* 2438 * Now check what we've discovered: is this truly a supported 2439 * chip on (the motherboard of) a supported platform? 2440 * 2441 * Possible problems here: 2442 * 1) it's a completely unheard-of chip 2443 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2444 * 3) it's a chip we would support if it were on the motherboard 2445 * of a Sun platform, but this one isn't ;-( 2446 */ 2447 if (cidp->chip_label == 0) 2448 bge_problem(bgep, 2449 "Device 'pci%04x,%04x' not recognized (%d?)", 2450 cidp->vendor, cidp->device, cidp->device); 2451 else if (!dev_ok) 2452 bge_problem(bgep, 2453 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2454 cidp->vendor, cidp->device, cidp->chip_label, 2455 cidp->revision); 2456 #if BGE_DEBUGGING 2457 else if (!sys_ok) 2458 bge_problem(bgep, 2459 "%d-based subsystem 'pci%04x,%04x' not validated", 2460 cidp->chip_label, cidp->subven, cidp->subdev); 2461 #endif 2462 else 2463 cidp->flags |= CHIP_FLAG_SUPPORTED; 2464 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2465 return (EIO); 2466 return (0); 2467 } 2468 2469 void 2470 bge_chip_msi_trig(bge_t *bgep) 2471 { 2472 uint32_t regval; 2473 2474 regval = bgep->param_msi_cnt<<4; 2475 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2476 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2477 } 2478 2479 /* 2480 * Various registers that control the chip's internal engines (state 2481 * machines) have a <reset> and <enable> bits (fortunately, in the 2482 * same place in each such register :-). 2483 * 2484 * To reset the state machine, the <reset> bit must be written with 1; 2485 * it will then read back as 1 while the reset is in progress, but 2486 * self-clear to 0 when the reset completes. 2487 * 2488 * To enable a state machine, one must set the <enable> bit, which 2489 * will continue to read back as 0 until the state machine is running. 2490 * 2491 * To disable a state machine, the <enable> bit must be cleared, but 2492 * it will continue to read back as 1 until the state machine actually 2493 * stops. 2494 * 2495 * This routine implements polling for completion of a reset, enable 2496 * or disable operation, returning B_TRUE on success (bit reached the 2497 * required state) or B_FALSE on timeout (200*100us == 20ms). 2498 */ 2499 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2500 uint32_t mask, uint32_t val); 2501 #pragma no_inline(bge_chip_poll_engine) 2502 2503 static boolean_t 2504 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2505 uint32_t mask, uint32_t val) 2506 { 2507 uint32_t regval; 2508 uint32_t n; 2509 2510 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2511 (void *)bgep, regno, mask, val)); 2512 2513 for (n = 200; n; --n) { 2514 regval = bge_reg_get32(bgep, regno); 2515 if ((regval & mask) == val) 2516 return (B_TRUE); 2517 drv_usecwait(100); 2518 } 2519 2520 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2521 return (B_FALSE); 2522 } 2523 2524 /* 2525 * Various registers that control the chip's internal engines (state 2526 * machines) have a <reset> bit (fortunately, in the same place in 2527 * each such register :-). To reset the state machine, this bit must 2528 * be written with 1; it will then read back as 1 while the reset is 2529 * in progress, but self-clear to 0 when the reset completes. 2530 * 2531 * This code sets the bit, then polls for it to read back as zero. 2532 * The return value is B_TRUE on success (reset bit cleared itself), 2533 * or B_FALSE if the state machine didn't recover :( 2534 * 2535 * NOTE: the Core reset is similar to other resets, except that we 2536 * can't poll for completion, since the Core reset disables memory 2537 * access! So we just have to assume that it will all complete in 2538 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2539 */ 2540 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2541 #pragma no_inline(bge_chip_reset_engine) 2542 2543 static boolean_t 2544 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2545 { 2546 uint32_t regval; 2547 uint32_t val32; 2548 2549 regval = bge_reg_get32(bgep, regno); 2550 2551 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2552 (void *)bgep, regno)); 2553 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2554 regno, regval)); 2555 2556 regval |= STATE_MACHINE_RESET_BIT; 2557 2558 switch (regno) { 2559 case MISC_CONFIG_REG: 2560 /* 2561 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2562 * resetting PCIE block and bringing PCIE link down, bit 29 2563 * in the register needs to be set first, and then set it again 2564 * while the reset bit is written. 2565 * See:P500 of 57xx-PG102-RDS.pdf. 2566 */ 2567 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2568 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2569 DEVICE_5723_SERIES_CHIPSETS(bgep)|| 2570 DEVICE_5714_SERIES_CHIPSETS(bgep)|| 2571 DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2572 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2573 if (bgep->chipid.pci_type == BGE_PCI_E) { 2574 if (bgep->chipid.asic_rev == 2575 MHCR_CHIP_REV_5751_A0 || 2576 bgep->chipid.asic_rev == 2577 MHCR_CHIP_REV_5721_A0 || 2578 bgep->chipid.asic_rev == 2579 MHCR_CHIP_REV_5755_A0) { 2580 val32 = bge_reg_get32(bgep, 2581 PHY_TEST_CTRL_REG); 2582 if (val32 == (PHY_PCIE_SCRAM_MODE | 2583 PHY_PCIE_LTASS_MODE)) 2584 bge_reg_put32(bgep, 2585 PHY_TEST_CTRL_REG, 2586 PHY_PCIE_SCRAM_MODE); 2587 val32 = pci_config_get32 2588 (bgep->cfg_handle, 2589 PCI_CONF_BGE_CLKCTL); 2590 val32 |= CLKCTL_PCIE_A0_FIX; 2591 pci_config_put32(bgep->cfg_handle, 2592 PCI_CONF_BGE_CLKCTL, val32); 2593 } 2594 bge_reg_set32(bgep, regno, 2595 MISC_CONFIG_GRC_RESET_DISABLE); 2596 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2597 } 2598 } 2599 2600 /* 2601 * Special case - causes Core reset 2602 * 2603 * On SPARC v9 we want to ensure that we don't start 2604 * timing until the I/O access has actually reached 2605 * the chip, otherwise we might make the next access 2606 * too early. And we can't just force the write out 2607 * by following it with a read (even to config space) 2608 * because that would cause the fault we're trying 2609 * to avoid. Hence the need for membar_sync() here. 2610 */ 2611 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2612 #ifdef __sparcv9 2613 membar_sync(); 2614 #endif /* __sparcv9 */ 2615 /* 2616 * On some platforms,system need about 300us for 2617 * link setup. 2618 */ 2619 drv_usecwait(300); 2620 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2621 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET); 2622 bge_reg_clr32( 2623 bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF); 2624 } 2625 2626 if (bgep->chipid.pci_type == BGE_PCI_E) { 2627 /* PCI-E device need more reset time */ 2628 drv_usecwait(120000); 2629 2630 /* Set PCIE max payload size and clear error status. */ 2631 if ((bgep->chipid.chip_label == 5721) || 2632 (bgep->chipid.chip_label == 5751) || 2633 (bgep->chipid.chip_label == 5752) || 2634 (bgep->chipid.chip_label == 5789) || 2635 (bgep->chipid.chip_label == 5906)) { 2636 pci_config_put16(bgep->cfg_handle, 2637 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2638 pci_config_put16(bgep->cfg_handle, 2639 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2640 } 2641 2642 if ((bgep->chipid.chip_label == 5723) || 2643 (bgep->chipid.chip_label == 5761)) { 2644 pci_config_put16(bgep->cfg_handle, 2645 PCI_CONF_DEV_CTRL_5723, READ_REQ_SIZE_MAX); 2646 pci_config_put16(bgep->cfg_handle, 2647 PCI_CONF_DEV_STUS_5723, DEVICE_ERROR_STUS); 2648 } 2649 } 2650 2651 BGE_PCICHK(bgep); 2652 return (B_TRUE); 2653 2654 default: 2655 bge_reg_put32(bgep, regno, regval); 2656 return (bge_chip_poll_engine(bgep, regno, 2657 STATE_MACHINE_RESET_BIT, 0)); 2658 } 2659 } 2660 2661 /* 2662 * Various registers that control the chip's internal engines (state 2663 * machines) have an <enable> bit (fortunately, in the same place in 2664 * each such register :-). To stop the state machine, this bit must 2665 * be written with 0, then polled to see when the state machine has 2666 * actually stopped. 2667 * 2668 * The return value is B_TRUE on success (enable bit cleared), or 2669 * B_FALSE if the state machine didn't stop :( 2670 */ 2671 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2672 uint32_t morebits); 2673 #pragma no_inline(bge_chip_disable_engine) 2674 2675 static boolean_t 2676 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2677 { 2678 uint32_t regval; 2679 2680 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2681 (void *)bgep, regno, morebits)); 2682 2683 switch (regno) { 2684 case FTQ_RESET_REG: 2685 /* 2686 * For Schumacher's bugfix CR6490108 2687 */ 2688 #ifdef BGE_IPMI_ASF 2689 #ifdef BGE_NETCONSOLE 2690 if (bgep->asf_enabled) 2691 return (B_TRUE); 2692 #endif 2693 #endif 2694 /* 2695 * Not quite like the others; it doesn't 2696 * have an <enable> bit, but instead we 2697 * have to set and then clear all the bits 2698 */ 2699 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2700 drv_usecwait(100); 2701 bge_reg_put32(bgep, regno, 0); 2702 return (B_TRUE); 2703 2704 default: 2705 regval = bge_reg_get32(bgep, regno); 2706 regval &= ~STATE_MACHINE_ENABLE_BIT; 2707 regval &= ~morebits; 2708 bge_reg_put32(bgep, regno, regval); 2709 return (bge_chip_poll_engine(bgep, regno, 2710 STATE_MACHINE_ENABLE_BIT, 0)); 2711 } 2712 } 2713 2714 /* 2715 * Various registers that control the chip's internal engines (state 2716 * machines) have an <enable> bit (fortunately, in the same place in 2717 * each such register :-). To start the state machine, this bit must 2718 * be written with 1, then polled to see when the state machine has 2719 * actually started. 2720 * 2721 * The return value is B_TRUE on success (enable bit set), or 2722 * B_FALSE if the state machine didn't start :( 2723 */ 2724 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2725 uint32_t morebits); 2726 #pragma no_inline(bge_chip_enable_engine) 2727 2728 static boolean_t 2729 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2730 { 2731 uint32_t regval; 2732 2733 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2734 (void *)bgep, regno, morebits)); 2735 2736 switch (regno) { 2737 case FTQ_RESET_REG: 2738 #ifdef BGE_IPMI_ASF 2739 #ifdef BGE_NETCONSOLE 2740 if (bgep->asf_enabled) 2741 return (B_TRUE); 2742 #endif 2743 #endif 2744 /* 2745 * Not quite like the others; it doesn't 2746 * have an <enable> bit, but instead we 2747 * have to set and then clear all the bits 2748 */ 2749 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2750 drv_usecwait(100); 2751 bge_reg_put32(bgep, regno, 0); 2752 return (B_TRUE); 2753 2754 default: 2755 regval = bge_reg_get32(bgep, regno); 2756 regval |= STATE_MACHINE_ENABLE_BIT; 2757 regval |= morebits; 2758 bge_reg_put32(bgep, regno, regval); 2759 return (bge_chip_poll_engine(bgep, regno, 2760 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2761 } 2762 } 2763 2764 /* 2765 * Reprogram the Ethernet, Transmit, and Receive MAC 2766 * modes to match the param_* variables 2767 */ 2768 void bge_sync_mac_modes(bge_t *bgep); 2769 #pragma no_inline(bge_sync_mac_modes) 2770 2771 void 2772 bge_sync_mac_modes(bge_t *bgep) 2773 { 2774 uint32_t macmode; 2775 uint32_t regval; 2776 2777 ASSERT(mutex_owned(bgep->genlock)); 2778 2779 /* 2780 * Reprogram the Ethernet MAC mode ... 2781 */ 2782 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2783 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2784 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2785 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2786 macmode |= ETHERNET_MODE_LINK_POLARITY; 2787 else 2788 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2789 else 2790 macmode |= ETHERNET_MODE_LINK_POLARITY; 2791 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2792 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2793 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) { 2794 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2795 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2796 else 2797 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2798 } else if (bgep->param_link_speed == 10 || 2799 bgep->param_link_speed == 100) 2800 macmode |= ETHERNET_MODE_PORTMODE_MII; 2801 else 2802 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2803 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2804 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2805 else 2806 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2807 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2808 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2809 else 2810 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2811 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2812 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2813 (void *)bgep, regval, macmode)); 2814 2815 /* 2816 * ... the Transmit MAC mode ... 2817 */ 2818 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2819 if (bgep->param_link_tx_pause) 2820 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2821 else 2822 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2823 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2824 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2825 (void *)bgep, regval, macmode)); 2826 2827 /* 2828 * ... and the Receive MAC mode 2829 */ 2830 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2831 if (bgep->param_link_rx_pause) 2832 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2833 else 2834 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2835 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2836 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2837 (void *)bgep, regval, macmode)); 2838 } 2839 2840 /* 2841 * bge_chip_sync() -- program the chip with the unicast MAC address, 2842 * the multicast hash table, the required level of promiscuity, and 2843 * the current loopback mode ... 2844 */ 2845 #ifdef BGE_IPMI_ASF 2846 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2847 #else 2848 int bge_chip_sync(bge_t *bgep); 2849 #endif 2850 #pragma no_inline(bge_chip_sync) 2851 2852 int 2853 #ifdef BGE_IPMI_ASF 2854 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2855 #else 2856 bge_chip_sync(bge_t *bgep) 2857 #endif 2858 { 2859 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2860 boolean_t promisc; 2861 uint64_t macaddr; 2862 uint32_t fill = 0; 2863 int i, j; 2864 int retval = DDI_SUCCESS; 2865 2866 BGE_TRACE(("bge_chip_sync($%p)", 2867 (void *)bgep)); 2868 2869 ASSERT(mutex_owned(bgep->genlock)); 2870 2871 promisc = B_FALSE; 2872 fill = ~(uint32_t)0; 2873 2874 if (bgep->promisc) 2875 promisc = B_TRUE; 2876 else 2877 fill = (uint32_t)0; 2878 2879 /* 2880 * If the TX/RX MAC engines are already running, we should stop 2881 * them (and reset the RX engine) before changing the parameters. 2882 * If they're not running, this will have no effect ... 2883 * 2884 * NOTE: this is currently disabled by default because stopping 2885 * and restarting the Tx engine may cause an outgoing packet in 2886 * transit to be truncated. Also, stopping and restarting the 2887 * Rx engine seems to not work correctly on the 5705. Testing 2888 * has not (yet!) revealed any problems with NOT stopping and 2889 * restarting these engines (and Broadcom say their drivers don't 2890 * do this), but if it is found to cause problems, this variable 2891 * can be patched to re-enable the old behaviour ... 2892 */ 2893 if (bge_stop_start_on_sync) { 2894 #ifdef BGE_IPMI_ASF 2895 if (!bgep->asf_enabled) { 2896 if (!bge_chip_disable_engine(bgep, 2897 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2898 retval = DDI_FAILURE; 2899 } else { 2900 if (!bge_chip_disable_engine(bgep, 2901 RECEIVE_MAC_MODE_REG, 0)) 2902 retval = DDI_FAILURE; 2903 } 2904 #else 2905 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2906 RECEIVE_MODE_KEEP_VLAN_TAG)) 2907 retval = DDI_FAILURE; 2908 #endif 2909 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2910 retval = DDI_FAILURE; 2911 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2912 retval = DDI_FAILURE; 2913 } 2914 2915 /* 2916 * Reprogram the hashed multicast address table ... 2917 */ 2918 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2919 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 2920 2921 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2922 bge_reg_put32(bgep, MAC_HASH_REG(i), 2923 bgep->mcast_hash[i] | fill); 2924 2925 #ifdef BGE_IPMI_ASF 2926 if (!bgep->asf_enabled || !asf_keeplive) { 2927 #endif 2928 /* 2929 * Transform the MAC address(es) from host to chip format, then 2930 * reprogram the transmit random backoff seed and the unicast 2931 * MAC address(es) ... 2932 */ 2933 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2934 for (i = 0, macaddr = 0ull; 2935 i < ETHERADDRL; ++i) { 2936 macaddr <<= 8; 2937 macaddr |= bgep->curr_addr[j].addr[i]; 2938 } 2939 fill += (macaddr >> 16) + (macaddr & 0xffffffff); 2940 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2941 2942 BGE_DEBUG(("bge_chip_sync($%p) " 2943 "setting MAC address %012llx", 2944 (void *)bgep, macaddr)); 2945 } 2946 #ifdef BGE_IPMI_ASF 2947 } 2948 #endif 2949 /* 2950 * Set random seed of backoff interval 2951 * - Writing zero means no backoff interval 2952 */ 2953 fill = ((fill >> 20) + (fill >> 10) + fill) & 0x3ff; 2954 if (fill == 0) 2955 fill = 1; 2956 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2957 2958 /* 2959 * Set or clear the PROMISCUOUS mode bit 2960 */ 2961 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2962 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2963 2964 /* 2965 * Sync the rest of the MAC modes too ... 2966 */ 2967 bge_sync_mac_modes(bgep); 2968 2969 /* 2970 * Restart RX/TX MAC engines if required ... 2971 */ 2972 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2973 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2974 retval = DDI_FAILURE; 2975 #ifdef BGE_IPMI_ASF 2976 if (!bgep->asf_enabled) { 2977 if (!bge_chip_enable_engine(bgep, 2978 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2979 retval = DDI_FAILURE; 2980 } else { 2981 if (!bge_chip_enable_engine(bgep, 2982 RECEIVE_MAC_MODE_REG, 0)) 2983 retval = DDI_FAILURE; 2984 } 2985 #else 2986 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2987 RECEIVE_MODE_KEEP_VLAN_TAG)) 2988 retval = DDI_FAILURE; 2989 #endif 2990 } 2991 return (retval); 2992 } 2993 2994 /* 2995 * This array defines the sequence of state machine control registers 2996 * in which the <enable> bit must be cleared to bring the chip to a 2997 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2998 */ 2999 static bge_regno_t shutdown_engine_regs[] = { 3000 RECEIVE_MAC_MODE_REG, 3001 RCV_BD_INITIATOR_MODE_REG, 3002 RCV_LIST_PLACEMENT_MODE_REG, 3003 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 3004 RCV_DATA_BD_INITIATOR_MODE_REG, 3005 RCV_DATA_COMPLETION_MODE_REG, 3006 RCV_BD_COMPLETION_MODE_REG, 3007 3008 SEND_BD_SELECTOR_MODE_REG, 3009 SEND_BD_INITIATOR_MODE_REG, 3010 SEND_DATA_INITIATOR_MODE_REG, 3011 READ_DMA_MODE_REG, 3012 SEND_DATA_COMPLETION_MODE_REG, 3013 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 3014 SEND_BD_COMPLETION_MODE_REG, 3015 TRANSMIT_MAC_MODE_REG, 3016 3017 HOST_COALESCE_MODE_REG, 3018 WRITE_DMA_MODE_REG, 3019 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 3020 FTQ_RESET_REG, /* special - see code */ 3021 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 3022 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 3023 BGE_REGNO_NONE /* terminator */ 3024 }; 3025 3026 #ifndef __sparc 3027 static bge_regno_t quiesce_regs[] = { 3028 READ_DMA_MODE_REG, 3029 DMA_COMPLETION_MODE_REG, 3030 WRITE_DMA_MODE_REG, 3031 BGE_REGNO_NONE 3032 }; 3033 3034 void bge_chip_stop_nonblocking(bge_t *bgep); 3035 #pragma no_inline(bge_chip_stop_nonblocking) 3036 3037 /* 3038 * This function is called by bge_quiesce(). We 3039 * turn off all the DMA engines here. 3040 */ 3041 void 3042 bge_chip_stop_nonblocking(bge_t *bgep) 3043 { 3044 bge_regno_t *rbp; 3045 3046 /* 3047 * Flag that no more activity may be initiated 3048 */ 3049 bgep->progress &= ~PROGRESS_READY; 3050 3051 rbp = quiesce_regs; 3052 while (*rbp != BGE_REGNO_NONE) { 3053 (void) bge_chip_disable_engine(bgep, *rbp, 0); 3054 ++rbp; 3055 } 3056 3057 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3058 } 3059 3060 #endif 3061 3062 /* 3063 * bge_chip_stop() -- stop all chip processing 3064 * 3065 * If the <fault> parameter is B_TRUE, we're stopping the chip because 3066 * we've detected a problem internally; otherwise, this is a normal 3067 * (clean) stop (at user request i.e. the last STREAM has been closed). 3068 */ 3069 void bge_chip_stop(bge_t *bgep, boolean_t fault); 3070 #pragma no_inline(bge_chip_stop) 3071 3072 void 3073 bge_chip_stop(bge_t *bgep, boolean_t fault) 3074 { 3075 bge_regno_t regno; 3076 bge_regno_t *rbp; 3077 boolean_t ok; 3078 3079 BGE_TRACE(("bge_chip_stop($%p)", 3080 (void *)bgep)); 3081 3082 ASSERT(mutex_owned(bgep->genlock)); 3083 3084 rbp = shutdown_engine_regs; 3085 /* 3086 * When driver try to shutdown the BCM5705/5788/5721/5751/ 3087 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 3088 * -ory arbiter should not be disabled. 3089 */ 3090 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 3091 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3092 ok &= bge_chip_disable_engine(bgep, regno, 0); 3093 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 3094 (regno != DMA_COMPLETION_MODE_REG) && 3095 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 3096 (regno != BUFFER_MANAGER_MODE_REG) && 3097 (regno != MEMORY_ARBITER_MODE_REG)) 3098 ok &= bge_chip_disable_engine(bgep, 3099 regno, 0); 3100 } 3101 3102 if (!ok && !fault) 3103 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 3104 3105 /* 3106 * Finally, disable (all) MAC events & clear the MAC status 3107 */ 3108 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 3109 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 3110 3111 /* 3112 * if we're stopping the chip because of a detected fault then do 3113 * appropriate actions 3114 */ 3115 if (fault) { 3116 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 3117 bgep->bge_chip_state = BGE_CHIP_FAULT; 3118 if (!bgep->manual_reset) 3119 ddi_fm_service_impact(bgep->devinfo, 3120 DDI_SERVICE_LOST); 3121 if (bgep->bge_dma_error) { 3122 /* 3123 * need to free buffers in case the fault was 3124 * due to a memory error in a buffer - got to 3125 * do a fair bit of tidying first 3126 */ 3127 if (bgep->progress & PROGRESS_KSTATS) { 3128 bge_fini_kstats(bgep); 3129 bgep->progress &= ~PROGRESS_KSTATS; 3130 } 3131 if (bgep->progress & PROGRESS_INTR) { 3132 bge_intr_disable(bgep); 3133 rw_enter(bgep->errlock, RW_WRITER); 3134 bge_fini_rings(bgep); 3135 rw_exit(bgep->errlock); 3136 bgep->progress &= ~PROGRESS_INTR; 3137 } 3138 if (bgep->progress & PROGRESS_BUFS) { 3139 bge_free_bufs(bgep); 3140 bgep->progress &= ~PROGRESS_BUFS; 3141 } 3142 bgep->bge_dma_error = B_FALSE; 3143 } 3144 } 3145 } else 3146 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3147 } 3148 3149 /* 3150 * Poll for completion of chip's ROM firmware; also, at least on the 3151 * first time through, find and return the hardware MAC address, if any. 3152 */ 3153 static uint64_t bge_poll_firmware(bge_t *bgep); 3154 #pragma no_inline(bge_poll_firmware) 3155 3156 static uint64_t 3157 bge_poll_firmware(bge_t *bgep) 3158 { 3159 uint64_t magic; 3160 uint64_t mac; 3161 uint32_t gen, val; 3162 uint32_t i; 3163 3164 /* 3165 * Step 19: poll for firmware completion (GENCOMM port set 3166 * to the ones complement of T3_MAGIC_NUMBER). 3167 * 3168 * While we're at it, we also read the MAC address register; 3169 * at some stage the firmware will load this with the 3170 * factory-set value. 3171 * 3172 * When both the magic number and the MAC address are set, 3173 * we're done; but we impose a time limit of one second 3174 * (1000*1000us) in case the firmware fails in some fashion 3175 * or the SEEPROM that provides that MAC address isn't fitted. 3176 * 3177 * After the first time through (chip state != INITIAL), we 3178 * don't need the MAC address to be set (we've already got it 3179 * or not, from the first time), so we don't wait for it, but 3180 * we still have to wait for the T3_MAGIC_NUMBER. 3181 * 3182 * Note: the magic number is only a 32-bit quantity, but the NIC 3183 * memory is 64-bit (and big-endian) internally. Addressing the 3184 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3185 * it work correctly on both big- and little-endian hosts. 3186 */ 3187 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3188 MHCR_CHIP_ASIC_REV_5906) { 3189 for (i = 0; i < 1000; ++i) { 3190 drv_usecwait(1000); 3191 val = bge_reg_get32(bgep, VCPU_STATUS_REG); 3192 if (val & VCPU_INIT_DONE) 3193 break; 3194 } 3195 BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops", 3196 (void *)bgep, i)); 3197 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3198 } else { 3199 for (i = 0; i < 1000; ++i) { 3200 drv_usecwait(1000); 3201 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3202 if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep)) 3203 drv_usecwait(100000); 3204 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3205 #ifdef BGE_IPMI_ASF 3206 if (!bgep->asf_enabled) { 3207 #endif 3208 if (gen != ~T3_MAGIC_NUMBER) 3209 continue; 3210 #ifdef BGE_IPMI_ASF 3211 } 3212 #endif 3213 if (mac != 0ULL) 3214 break; 3215 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3216 break; 3217 } 3218 } 3219 3220 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3221 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3222 (void *)bgep, gen, i)); 3223 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3224 mac, magic)); 3225 3226 return (mac); 3227 } 3228 3229 /* 3230 * Maximum times of trying to get the NVRAM access lock 3231 * by calling bge_nvmem_acquire() 3232 */ 3233 #define MAX_TRY_NVMEM_ACQUIRE 10000 3234 3235 #ifdef BGE_IPMI_ASF 3236 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3237 #else 3238 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3239 #endif 3240 #pragma no_inline(bge_chip_reset) 3241 3242 int 3243 #ifdef BGE_IPMI_ASF 3244 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3245 #else 3246 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3247 #endif 3248 { 3249 chip_id_t chipid; 3250 uint64_t mac; 3251 uint64_t magic; 3252 uint32_t modeflags; 3253 uint32_t mhcr; 3254 uint32_t sx0; 3255 uint32_t i, tries; 3256 #ifdef BGE_IPMI_ASF 3257 uint32_t mailbox; 3258 #endif 3259 int retval = DDI_SUCCESS; 3260 3261 BGE_TRACE(("bge_chip_reset($%p, %d)", 3262 (void *)bgep, enable_dma)); 3263 3264 ASSERT(mutex_owned(bgep->genlock)); 3265 3266 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3267 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3268 3269 /* 3270 * Do we need to stop the chip cleanly before resetting? 3271 */ 3272 switch (bgep->bge_chip_state) { 3273 default: 3274 _NOTE(NOTREACHED) 3275 return (DDI_FAILURE); 3276 3277 case BGE_CHIP_INITIAL: 3278 case BGE_CHIP_STOPPED: 3279 case BGE_CHIP_RESET: 3280 break; 3281 3282 case BGE_CHIP_RUNNING: 3283 case BGE_CHIP_ERROR: 3284 case BGE_CHIP_FAULT: 3285 bge_chip_stop(bgep, B_FALSE); 3286 break; 3287 } 3288 3289 #ifdef BGE_IPMI_ASF 3290 if (bgep->asf_enabled) { 3291 #ifdef __sparc 3292 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3293 MHCR_ENABLE_TAGGED_STATUS_MODE | 3294 MHCR_MASK_INTERRUPT_MODE | 3295 MHCR_MASK_PCI_INT_OUTPUT | 3296 MHCR_CLEAR_INTERRUPT_INTA | 3297 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3298 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3299 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3300 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3301 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3302 MEMORY_ARBITER_ENABLE); 3303 #endif 3304 if (asf_mode == ASF_MODE_INIT) { 3305 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3306 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3307 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3308 } 3309 } 3310 #endif 3311 /* 3312 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3313 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3314 * 3315 * Before reset Core clock,it is 3316 * also required to initialize the Memory Arbiter as specified in step9 3317 * and Misc Host Control Register as specified in step-13 3318 * Step 4-5: reset Core clock & wait for completion 3319 * Steps 6-8: are done by bge_chip_cfg_init() 3320 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3321 */ 3322 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3323 retval = DDI_FAILURE; 3324 3325 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3326 MHCR_ENABLE_TAGGED_STATUS_MODE | 3327 MHCR_MASK_INTERRUPT_MODE | 3328 MHCR_MASK_PCI_INT_OUTPUT | 3329 MHCR_CLEAR_INTERRUPT_INTA; 3330 #ifdef _BIG_ENDIAN 3331 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3332 #endif /* _BIG_ENDIAN */ 3333 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3334 #ifdef BGE_IPMI_ASF 3335 if (bgep->asf_enabled) 3336 bgep->asf_wordswapped = B_FALSE; 3337 #endif 3338 /* 3339 * NVRAM Corruption Workaround 3340 */ 3341 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3342 if (bge_nvmem_acquire(bgep) != EAGAIN) 3343 break; 3344 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3345 BGE_DEBUG(("%s: fail to acquire nvram lock", 3346 bgep->ifname)); 3347 3348 #ifdef BGE_IPMI_ASF 3349 if (!bgep->asf_enabled) { 3350 #endif 3351 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3352 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3353 #ifdef BGE_IPMI_ASF 3354 } 3355 #endif 3356 3357 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3358 retval = DDI_FAILURE; 3359 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3360 3361 /* 3362 * Step 8a: This may belong elsewhere, but BCM5721 needs 3363 * a bit set to avoid a fifo overflow/underflow bug. 3364 */ 3365 if ((bgep->chipid.chip_label == 5721) || 3366 (bgep->chipid.chip_label == 5751) || 3367 (bgep->chipid.chip_label == 5752) || 3368 (bgep->chipid.chip_label == 5755) || 3369 (bgep->chipid.chip_label == 5756) || 3370 (bgep->chipid.chip_label == 5789) || 3371 (bgep->chipid.chip_label == 5906)) 3372 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3373 3374 3375 /* 3376 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3377 * not be changed. 3378 */ 3379 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3380 retval = DDI_FAILURE; 3381 3382 /* 3383 * Steps 10-11: configure PIO endianness options and 3384 * enable indirect register access -- already done 3385 * Steps 12-13: enable writing to the PCI state & clock 3386 * control registers -- not required; we aren't going to 3387 * use those features. 3388 * Steps 14-15: Configure DMA endianness options. See 3389 * the comments on the setting of the MHCR above. 3390 */ 3391 #ifdef _BIG_ENDIAN 3392 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3393 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3394 #else 3395 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3396 #endif /* _BIG_ENDIAN */ 3397 #ifdef BGE_IPMI_ASF 3398 if (bgep->asf_enabled) 3399 modeflags |= MODE_HOST_STACK_UP; 3400 #endif 3401 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3402 3403 #ifdef BGE_IPMI_ASF 3404 if (bgep->asf_enabled) { 3405 #ifdef __sparc 3406 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3407 MEMORY_ARBITER_ENABLE | 3408 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3409 #endif 3410 3411 #ifdef BGE_NETCONSOLE 3412 if (!bgep->asf_newhandshake) { 3413 if ((asf_mode == ASF_MODE_INIT) || 3414 (asf_mode == ASF_MODE_POST_INIT)) { 3415 bge_asf_post_reset_old_mode(bgep, 3416 BGE_INIT_RESET); 3417 } else { 3418 bge_asf_post_reset_old_mode(bgep, 3419 BGE_SHUTDOWN_RESET); 3420 } 3421 } 3422 #endif 3423 3424 /* Wait for NVRAM init */ 3425 i = 0; 3426 drv_usecwait(5000); 3427 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3428 3429 while ((mailbox != (uint32_t) 3430 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3431 (i < 10000)) { 3432 drv_usecwait(100); 3433 mailbox = bge_nic_get32(bgep, 3434 BGE_FIRMWARE_MAILBOX); 3435 i++; 3436 } 3437 3438 #ifndef BGE_NETCONSOLE 3439 if (!bgep->asf_newhandshake) { 3440 if ((asf_mode == ASF_MODE_INIT) || 3441 (asf_mode == ASF_MODE_POST_INIT)) { 3442 3443 bge_asf_post_reset_old_mode(bgep, 3444 BGE_INIT_RESET); 3445 } else { 3446 bge_asf_post_reset_old_mode(bgep, 3447 BGE_SHUTDOWN_RESET); 3448 } 3449 } 3450 #endif 3451 } 3452 #endif 3453 /* 3454 * Steps 16-17: poll for firmware completion 3455 */ 3456 mac = bge_poll_firmware(bgep); 3457 3458 /* 3459 * Step 18: enable external memory -- doesn't apply. 3460 * 3461 * However we take the opportunity to set the MLCR anyway, as 3462 * this register also controls the SEEPROM auto-access method 3463 * which we may want to use later ... 3464 * 3465 * The proper value here depends on the way the chip is wired 3466 * into the circuit board, as this register *also* controls which 3467 * of the "Miscellaneous I/O" pins are driven as outputs and the 3468 * values driven onto those pins! 3469 * 3470 * See also step 74 in the PRM ... 3471 */ 3472 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3473 bgep->chipid.bge_mlcr_default); 3474 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3475 3476 /* 3477 * Step 20: clear the Ethernet MAC mode register 3478 */ 3479 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3480 3481 /* 3482 * Step 21: restore cache-line-size, latency timer, and 3483 * subsystem ID registers to their original values (not 3484 * those read into the local structure <chipid>, 'cos 3485 * that was after they were cleared by the RESET). 3486 * 3487 * Note: the Subsystem Vendor/Device ID registers are not 3488 * directly writable in config space, so we use the shadow 3489 * copy in "Page Zero" of register space to restore them 3490 * both in one go ... 3491 */ 3492 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3493 bgep->chipid.clsize); 3494 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3495 bgep->chipid.latency); 3496 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3497 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3498 3499 /* 3500 * The SEND INDEX registers should be reset to zero by the 3501 * global chip reset; if they're not, there'll be trouble 3502 * later on. 3503 */ 3504 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3505 if (sx0 != 0) { 3506 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3507 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3508 retval = DDI_FAILURE; 3509 } 3510 3511 /* Enable MSI code */ 3512 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3513 bge_reg_set32(bgep, MSI_MODE_REG, 3514 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3515 3516 /* 3517 * On the first time through, save the factory-set MAC address 3518 * (if any). If bge_poll_firmware() above didn't return one 3519 * (from a chip register) consider looking in the attached NV 3520 * memory device, if any. Once we have it, we save it in both 3521 * register-image (64-bit) and byte-array forms. All-zero and 3522 * all-one addresses are not valid, and we refuse to stash those. 3523 */ 3524 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3525 if (mac == 0ULL) 3526 mac = bge_get_nvmac(bgep); 3527 if (mac != 0ULL && mac != ~0ULL) { 3528 bgep->chipid.hw_mac_addr = mac; 3529 for (i = ETHERADDRL; i-- != 0; ) { 3530 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3531 mac >>= 8; 3532 } 3533 bgep->chipid.vendor_addr.set = B_TRUE; 3534 } 3535 } 3536 3537 #ifdef BGE_IPMI_ASF 3538 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3539 if (asf_mode != ASF_MODE_NONE) { 3540 if ((asf_mode == ASF_MODE_INIT) || 3541 (asf_mode == ASF_MODE_POST_INIT)) { 3542 3543 bge_asf_post_reset_new_mode(bgep, 3544 BGE_INIT_RESET); 3545 } else { 3546 bge_asf_post_reset_new_mode(bgep, 3547 BGE_SHUTDOWN_RESET); 3548 } 3549 } 3550 } 3551 #endif 3552 3553 /* 3554 * Record the new state 3555 */ 3556 bgep->chip_resets += 1; 3557 bgep->bge_chip_state = BGE_CHIP_RESET; 3558 return (retval); 3559 } 3560 3561 /* 3562 * bge_chip_start() -- start the chip transmitting and/or receiving, 3563 * including enabling interrupts 3564 */ 3565 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3566 #pragma no_inline(bge_chip_start) 3567 3568 void 3569 bge_chip_coalesce_update(bge_t *bgep) 3570 { 3571 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, 3572 bgep->chipid.tx_count_norm); 3573 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, 3574 bgep->chipid.tx_ticks_norm); 3575 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, 3576 bgep->chipid.rx_count_norm); 3577 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, 3578 bgep->chipid.rx_ticks_norm); 3579 } 3580 3581 int 3582 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3583 { 3584 uint32_t coalmode; 3585 uint32_t ledctl; 3586 uint32_t mtu; 3587 uint32_t maxring; 3588 uint32_t stats_mask; 3589 uint32_t dma_wrprio; 3590 uint64_t ring; 3591 int retval = DDI_SUCCESS; 3592 3593 BGE_TRACE(("bge_chip_start($%p)", 3594 (void *)bgep)); 3595 3596 ASSERT(mutex_owned(bgep->genlock)); 3597 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3598 3599 /* 3600 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3601 * The document specifies 95 separate steps to fully 3602 * initialise the chip!!!! 3603 * 3604 * The reset code above has already got us as far as step 3605 * 21, so we continue with ... 3606 * 3607 * Step 22: clear the MAC statistics block 3608 * (0x0300-0x0aff in NIC-local memory) 3609 */ 3610 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3611 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3612 NIC_MEM_STATISTICS_SIZE); 3613 3614 /* 3615 * Step 23: clear the status block (in host memory) 3616 */ 3617 DMA_ZERO(bgep->status_block); 3618 3619 /* 3620 * Step 24: set DMA read/write control register 3621 */ 3622 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3623 bgep->chipid.bge_dma_rwctrl); 3624 3625 /* 3626 * Step 25: Configure DMA endianness -- already done (16/17) 3627 * Step 26: Configure Host-Based Send Rings 3628 * Step 27: Indicate Host Stack Up 3629 */ 3630 bge_reg_set32(bgep, MODE_CONTROL_REG, 3631 MODE_HOST_SEND_BDS | 3632 MODE_HOST_STACK_UP); 3633 3634 /* 3635 * Step 28: Configure checksum options: 3636 * Solaris supports the hardware default checksum options. 3637 * 3638 * Workaround for Incorrect pseudo-header checksum calculation. 3639 */ 3640 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3641 bge_reg_set32(bgep, MODE_CONTROL_REG, 3642 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3643 3644 /* 3645 * Step 29: configure Timer Prescaler. The value is always the 3646 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3647 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3648 * for the whole chip! 3649 */ 3650 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3651 3652 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 3653 drv_usecwait(40); 3654 /* put PHY into ready state */ 3655 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ); 3656 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */ 3657 drv_usecwait(40); 3658 } 3659 3660 /* 3661 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3662 * 3663 * If the mbuf_length is specified as 0, we just leave these at 3664 * their hardware defaults, rather than explicitly setting them. 3665 * As the Broadcom HRM,driver better not change the parameters 3666 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3667 */ 3668 if ((bgep->chipid.mbuf_length != 0) && 3669 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3670 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3671 bgep->chipid.mbuf_base); 3672 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3673 bgep->chipid.mbuf_length); 3674 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3675 DMAD_POOL_BASE_DEFAULT); 3676 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3677 DMAD_POOL_LENGTH_DEFAULT); 3678 } 3679 3680 /* 3681 * Step 32: configure MAC memory pool watermarks 3682 */ 3683 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3684 bgep->chipid.mbuf_lo_water_rdma); 3685 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3686 bgep->chipid.mbuf_lo_water_rmac); 3687 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3688 bgep->chipid.mbuf_hi_water); 3689 3690 /* 3691 * Step 33: configure DMA resource watermarks 3692 */ 3693 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3694 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3695 bge_dmad_lo_water); 3696 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3697 bge_dmad_hi_water); 3698 } 3699 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3700 3701 /* 3702 * Steps 34-36: enable buffer manager & internal h/w queues 3703 */ 3704 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3705 STATE_MACHINE_ATTN_ENABLE_BIT)) 3706 retval = DDI_FAILURE; 3707 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3708 retval = DDI_FAILURE; 3709 3710 /* 3711 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3712 */ 3713 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3714 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3715 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3716 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3717 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3718 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3719 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3720 } 3721 3722 /* 3723 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3724 */ 3725 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3726 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3727 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3728 bge_replenish_jumbo); 3729 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3730 bge_replenish_mini); 3731 } 3732 3733 /* 3734 * Steps 41-43: clear Send Ring Producer Indices and initialise 3735 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3736 */ 3737 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3738 maxring = BGE_SEND_RINGS_MAX; 3739 else 3740 maxring = BGE_SEND_RINGS_MAX_5705; 3741 for (ring = 0; ring < maxring; ++ring) { 3742 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3743 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3744 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3745 &bgep->send[ring].hw_rcb); 3746 } 3747 3748 /* 3749 * Steps 44-45: initialise Receive Return Rings 3750 * (0x0200-0x02ff in NIC-local memory) 3751 */ 3752 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3753 maxring = BGE_RECV_RINGS_MAX; 3754 else 3755 maxring = BGE_RECV_RINGS_MAX_5705; 3756 for (ring = 0; ring < maxring; ++ring) 3757 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3758 &bgep->recv[ring].hw_rcb); 3759 3760 /* 3761 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3762 */ 3763 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3764 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3765 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3766 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3767 } 3768 /* 3769 * Step 47: configure the MAC unicast address 3770 * Step 48: configure the random backoff seed 3771 * Step 96: set up multicast filters 3772 */ 3773 #ifdef BGE_IPMI_ASF 3774 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3775 #else 3776 if (bge_chip_sync(bgep) == DDI_FAILURE) 3777 #endif 3778 retval = DDI_FAILURE; 3779 3780 /* 3781 * Step 49: configure the MTU 3782 */ 3783 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3784 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3785 3786 /* 3787 * Step 50: configure the IPG et al 3788 */ 3789 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3790 3791 /* 3792 * Step 51: configure the default Rx Return Ring 3793 */ 3794 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3795 3796 /* 3797 * Steps 52-54: configure Receive List Placement, 3798 * and enable Receive List Placement Statistics 3799 */ 3800 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3801 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3802 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3803 case MHCR_CHIP_ASIC_REV_5700: 3804 case MHCR_CHIP_ASIC_REV_5701: 3805 case MHCR_CHIP_ASIC_REV_5703: 3806 case MHCR_CHIP_ASIC_REV_5704: 3807 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3808 break; 3809 case MHCR_CHIP_ASIC_REV_5705: 3810 break; 3811 default: 3812 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3813 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3814 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3815 break; 3816 } 3817 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3818 3819 if (bgep->chipid.rx_rings > 1) 3820 bge_init_recv_rule(bgep); 3821 3822 /* 3823 * Steps 55-56: enable Send Data Initiator Statistics 3824 */ 3825 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3826 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3827 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3828 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3829 } else { 3830 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3831 SEND_INIT_STATS_ENABLE); 3832 } 3833 /* 3834 * Steps 57-58: stop (?) the Host Coalescing Engine 3835 */ 3836 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3837 retval = DDI_FAILURE; 3838 3839 /* 3840 * Steps 59-62: initialise Host Coalescing parameters 3841 */ 3842 bge_chip_coalesce_update(bgep); 3843 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3844 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3845 bge_tx_count_intr); 3846 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3847 bge_tx_ticks_intr); 3848 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3849 bge_rx_count_intr); 3850 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3851 bge_rx_ticks_intr); 3852 } 3853 3854 /* 3855 * Steps 63-64: initialise status block & statistics 3856 * host memory addresses 3857 * The statistic block does not exist in some chipsets 3858 * Step 65: initialise Statistics Coalescing Tick Counter 3859 */ 3860 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3861 bgep->status_block.cookie.dmac_laddress); 3862 3863 /* 3864 * Steps 66-67: initialise status block & statistics 3865 * NIC-local memory addresses 3866 */ 3867 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3868 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3869 bgep->statistics.cookie.dmac_laddress); 3870 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3871 STATISTICS_TICKS_DEFAULT); 3872 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3873 NIC_MEM_STATUS_BLOCK); 3874 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3875 NIC_MEM_STATISTICS); 3876 } 3877 3878 /* 3879 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3880 * Completion Engine, the Receive List Placement Engine, and the 3881 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3882 * and BCM5715. 3883 */ 3884 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3885 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3886 coalmode = COALESCE_64_BYTE_STATUS; 3887 else 3888 coalmode = 0; 3889 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3890 retval = DDI_FAILURE; 3891 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3892 STATE_MACHINE_ATTN_ENABLE_BIT)) 3893 retval = DDI_FAILURE; 3894 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3895 retval = DDI_FAILURE; 3896 3897 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3898 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3899 STATE_MACHINE_ATTN_ENABLE_BIT)) 3900 retval = DDI_FAILURE; 3901 3902 /* 3903 * Step 72: Enable MAC DMA engines 3904 * Step 73: Clear & enable MAC statistics 3905 */ 3906 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3907 ETHERNET_MODE_ENABLE_FHDE | 3908 ETHERNET_MODE_ENABLE_RDE | 3909 ETHERNET_MODE_ENABLE_TDE); 3910 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3911 ETHERNET_MODE_ENABLE_TX_STATS | 3912 ETHERNET_MODE_ENABLE_RX_STATS | 3913 ETHERNET_MODE_CLEAR_TX_STATS | 3914 ETHERNET_MODE_CLEAR_RX_STATS); 3915 3916 /* 3917 * Step 74: configure the MLCR (Miscellaneous Local Control 3918 * Register); not required, as we set up the MLCR in step 10 3919 * (part of the reset code) above. 3920 * 3921 * Step 75: clear Interrupt Mailbox 0 3922 */ 3923 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3924 3925 /* 3926 * Steps 76-87: Gentlemen, start your engines ... 3927 * 3928 * Enable the DMA Completion Engine, the Write DMA Engine, 3929 * the Read DMA Engine, Receive Data Completion Engine, 3930 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3931 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3932 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3933 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3934 * 3935 * Beware exhaust fumes? 3936 */ 3937 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3938 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3939 retval = DDI_FAILURE; 3940 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 3941 ALL_DMA_ATTN_BITS; 3942 if ((MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3943 MHCR_CHIP_ASIC_REV_5755) || 3944 (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3945 MHCR_CHIP_ASIC_REV_5906)) { 3946 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 3947 } 3948 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3949 dma_wrprio)) 3950 retval = DDI_FAILURE; 3951 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3952 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3953 retval = DDI_FAILURE; 3954 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3955 STATE_MACHINE_ATTN_ENABLE_BIT)) 3956 retval = DDI_FAILURE; 3957 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3958 if (!bge_chip_enable_engine(bgep, 3959 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3960 retval = DDI_FAILURE; 3961 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3962 retval = DDI_FAILURE; 3963 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3964 STATE_MACHINE_ATTN_ENABLE_BIT)) 3965 retval = DDI_FAILURE; 3966 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3967 RCV_BD_DISABLED_RING_ATTN)) 3968 retval = DDI_FAILURE; 3969 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3970 RCV_DATA_BD_ILL_RING_ATTN)) 3971 retval = DDI_FAILURE; 3972 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3973 retval = DDI_FAILURE; 3974 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3975 STATE_MACHINE_ATTN_ENABLE_BIT)) 3976 retval = DDI_FAILURE; 3977 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3978 STATE_MACHINE_ATTN_ENABLE_BIT)) 3979 retval = DDI_FAILURE; 3980 3981 /* 3982 * Step 88: download firmware -- doesn't apply 3983 * Steps 89-90: enable Transmit & Receive MAC Engines 3984 */ 3985 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3986 retval = DDI_FAILURE; 3987 #ifdef BGE_IPMI_ASF 3988 if (!bgep->asf_enabled) { 3989 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3990 RECEIVE_MODE_KEEP_VLAN_TAG)) 3991 retval = DDI_FAILURE; 3992 } else { 3993 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3994 retval = DDI_FAILURE; 3995 } 3996 #else 3997 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3998 RECEIVE_MODE_KEEP_VLAN_TAG)) 3999 retval = DDI_FAILURE; 4000 #endif 4001 4002 /* 4003 * Step 91: disable auto-polling of PHY status 4004 */ 4005 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 4006 4007 /* 4008 * Step 92: configure D0 power state (not required) 4009 * Step 93: initialise LED control register () 4010 */ 4011 ledctl = LED_CONTROL_DEFAULT; 4012 switch (bgep->chipid.device) { 4013 case DEVICE_ID_5700: 4014 case DEVICE_ID_5700x: 4015 case DEVICE_ID_5701: 4016 /* 4017 * Switch to 5700 (MAC) mode on these older chips 4018 */ 4019 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 4020 ledctl |= LED_CONTROL_LED_MODE_5700; 4021 break; 4022 4023 default: 4024 break; 4025 } 4026 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 4027 4028 /* 4029 * Step 94: activate link 4030 */ 4031 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 4032 4033 /* 4034 * Step 95: set up physical layer (PHY/SerDes) 4035 * restart autoneg (if required) 4036 */ 4037 if (reset_phys) 4038 if (bge_phys_update(bgep) == DDI_FAILURE) 4039 retval = DDI_FAILURE; 4040 4041 /* 4042 * Extra step (DSG): hand over all the Receive Buffers to the chip 4043 */ 4044 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 4045 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 4046 bgep->buff[ring].rf_next); 4047 4048 /* 4049 * MSI bits:The least significant MSI 16-bit word. 4050 * ISR will be triggered different. 4051 */ 4052 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 4053 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 4054 4055 /* 4056 * Extra step (DSG): select which interrupts are enabled 4057 * 4058 * Program the Ethernet MAC engine to signal attention on 4059 * Link Change events, then enable interrupts on MAC, DMA, 4060 * and FLOW attention signals. 4061 */ 4062 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 4063 ETHERNET_EVENT_LINK_INT | 4064 ETHERNET_STATUS_PCS_ERROR_INT); 4065 #ifdef BGE_IPMI_ASF 4066 if (bgep->asf_enabled) { 4067 bge_reg_set32(bgep, MODE_CONTROL_REG, 4068 MODE_INT_ON_FLOW_ATTN | 4069 MODE_INT_ON_DMA_ATTN | 4070 MODE_HOST_STACK_UP| 4071 MODE_INT_ON_MAC_ATTN); 4072 } else { 4073 #endif 4074 bge_reg_set32(bgep, MODE_CONTROL_REG, 4075 MODE_INT_ON_FLOW_ATTN | 4076 MODE_INT_ON_DMA_ATTN | 4077 MODE_INT_ON_MAC_ATTN); 4078 #ifdef BGE_IPMI_ASF 4079 } 4080 #endif 4081 4082 /* 4083 * Step 97: enable PCI interrupts!!! 4084 */ 4085 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 4086 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 4087 MHCR_MASK_PCI_INT_OUTPUT); 4088 4089 /* 4090 * All done! 4091 */ 4092 bgep->bge_chip_state = BGE_CHIP_RUNNING; 4093 return (retval); 4094 } 4095 4096 4097 /* 4098 * ========== Hardware interrupt handler ========== 4099 */ 4100 4101 #undef BGE_DBG 4102 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 4103 4104 /* 4105 * Sync the status block, then atomically clear the specified bits in 4106 * the <flags-and-tag> field of the status block. 4107 * the <flags> word of the status block, returning the value of the 4108 * <tag> and the <flags> before the bits were cleared. 4109 */ 4110 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 4111 #pragma inline(bge_status_sync) 4112 4113 static int 4114 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 4115 { 4116 bge_status_t *bsp; 4117 int retval; 4118 4119 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 4120 (void *)bgep, bits)); 4121 4122 ASSERT(bgep->bge_guard == BGE_GUARD); 4123 4124 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 4125 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 4126 if (retval != DDI_FM_OK) 4127 return (retval); 4128 4129 bsp = DMA_VPTR(bgep->status_block); 4130 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 4131 4132 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 4133 (void *)bgep, bits, *flags)); 4134 4135 return (retval); 4136 } 4137 4138 void bge_wake_factotum(bge_t *bgep); 4139 #pragma inline(bge_wake_factotum) 4140 4141 void 4142 bge_wake_factotum(bge_t *bgep) 4143 { 4144 mutex_enter(bgep->softintrlock); 4145 if (bgep->factotum_flag == 0) { 4146 bgep->factotum_flag = 1; 4147 ddi_trigger_softintr(bgep->factotum_id); 4148 } 4149 mutex_exit(bgep->softintrlock); 4150 } 4151 4152 /* 4153 * bge_intr() -- handle chip interrupts 4154 */ 4155 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 4156 #pragma no_inline(bge_intr) 4157 4158 uint_t 4159 bge_intr(caddr_t arg1, caddr_t arg2) 4160 { 4161 bge_t *bgep = (void *)arg1; /* private device info */ 4162 bge_status_t *bsp; 4163 uint64_t flags; 4164 uint32_t regval; 4165 uint_t result; 4166 int retval, loop_cnt = 0; 4167 4168 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 4169 4170 /* 4171 * GLD v2 checks that s/w setup is complete before passing 4172 * interrupts to this routine, thus eliminating the old 4173 * (and well-known) race condition around ddi_add_intr() 4174 */ 4175 ASSERT(bgep->progress & PROGRESS_HWINT); 4176 4177 result = DDI_INTR_UNCLAIMED; 4178 mutex_enter(bgep->genlock); 4179 4180 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4181 /* 4182 * Check whether chip's says it's asserting #INTA; 4183 * if not, don't process or claim the interrupt. 4184 * 4185 * Note that the PCI signal is active low, so the 4186 * bit is *zero* when the interrupt is asserted. 4187 */ 4188 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 4189 if (regval & MLCR_INTA_STATE) { 4190 if (bge_check_acc_handle(bgep, bgep->io_handle) 4191 != DDI_FM_OK) 4192 goto chip_stop; 4193 mutex_exit(bgep->genlock); 4194 return (result); 4195 } 4196 4197 /* 4198 * Block further PCI interrupts ... 4199 */ 4200 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 4201 MHCR_MASK_PCI_INT_OUTPUT); 4202 4203 } else { 4204 /* 4205 * Check MSI status 4206 */ 4207 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 4208 if (regval & MSI_ERROR_ATTENTION) { 4209 BGE_REPORT((bgep, "msi error attention," 4210 " status=0x%x", regval)); 4211 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 4212 } 4213 } 4214 4215 result = DDI_INTR_CLAIMED; 4216 4217 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 4218 4219 /* 4220 * Sync the status block and grab the flags-n-tag from it. 4221 * We count the number of interrupts where there doesn't 4222 * seem to have been a DMA update of the status block; if 4223 * it *has* been updated, the counter will be cleared in 4224 * the while() loop below ... 4225 */ 4226 bgep->missed_dmas += 1; 4227 bsp = DMA_VPTR(bgep->status_block); 4228 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 4229 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 4230 /* 4231 * bge_chip_stop() may have freed dma area etc 4232 * while we were in this interrupt handler - 4233 * better not call bge_status_sync() 4234 */ 4235 (void) bge_check_acc_handle(bgep, 4236 bgep->io_handle); 4237 mutex_exit(bgep->genlock); 4238 return (DDI_INTR_CLAIMED); 4239 } 4240 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 4241 &flags); 4242 if (retval != DDI_FM_OK) { 4243 bgep->bge_dma_error = B_TRUE; 4244 goto chip_stop; 4245 } 4246 4247 if (!(flags & STATUS_FLAG_UPDATED)) 4248 break; 4249 4250 /* 4251 * Tell the chip that we're processing the interrupt 4252 */ 4253 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4254 INTERRUPT_MBOX_DISABLE(flags)); 4255 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4256 DDI_FM_OK) 4257 goto chip_stop; 4258 4259 /* 4260 * Drop the mutex while we: 4261 * Receive any newly-arrived packets 4262 * Recycle any newly-finished send buffers 4263 */ 4264 bgep->bge_intr_running = B_TRUE; 4265 mutex_exit(bgep->genlock); 4266 bge_receive(bgep, bsp); 4267 bge_recycle(bgep, bsp); 4268 mutex_enter(bgep->genlock); 4269 bgep->bge_intr_running = B_FALSE; 4270 4271 /* 4272 * Tell the chip we've finished processing, and 4273 * give it the tag that we got from the status 4274 * block earlier, so that it knows just how far 4275 * we've gone. If it's got more for us to do, 4276 * it will now update the status block and try 4277 * to assert an interrupt (but we've got the 4278 * #INTA blocked at present). If we see the 4279 * update, we'll loop around to do some more. 4280 * Eventually we'll get out of here ... 4281 */ 4282 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4283 INTERRUPT_MBOX_ENABLE(flags)); 4284 if (bgep->chipid.pci_type == BGE_PCI_E) 4285 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 4286 bgep->missed_dmas = 0; 4287 } 4288 4289 /* 4290 * Check for exceptional conditions that we need to handle 4291 * 4292 * Link status changed 4293 * Status block not updated 4294 */ 4295 if (flags & STATUS_FLAG_LINK_CHANGED) 4296 bge_wake_factotum(bgep); 4297 4298 if (bgep->missed_dmas) { 4299 /* 4300 * Probably due to the internal status tag not 4301 * being reset. Force a status block update now; 4302 * this should ensure that we get an update and 4303 * a new interrupt. After that, we should be in 4304 * sync again ... 4305 */ 4306 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4307 "not updated?", flags)); 4308 bgep->missed_updates++; 4309 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4310 COALESCE_NOW); 4311 4312 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4313 /* 4314 * If this happens multiple times in a row, 4315 * it means DMA is just not working. Maybe 4316 * the chip's failed, or maybe there's a 4317 * problem on the PCI bus or in the host-PCI 4318 * bridge (Tomatillo). 4319 * 4320 * At all events, we want to stop further 4321 * interrupts and let the recovery code take 4322 * over to see whether anything can be done 4323 * about it ... 4324 */ 4325 bge_fm_ereport(bgep, 4326 DDI_FM_DEVICE_BADINT_LIMIT); 4327 goto chip_stop; 4328 } 4329 } 4330 4331 /* 4332 * Reenable assertion of #INTA, unless there's a DMA fault 4333 */ 4334 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4335 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4336 MHCR_MASK_PCI_INT_OUTPUT); 4337 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4338 DDI_FM_OK) 4339 goto chip_stop; 4340 } 4341 4342 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4343 goto chip_stop; 4344 4345 mutex_exit(bgep->genlock); 4346 return (result); 4347 4348 chip_stop: 4349 #ifdef BGE_IPMI_ASF 4350 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4351 /* 4352 * We must stop ASF heart beat before 4353 * bge_chip_stop(), otherwise some 4354 * computers (ex. IBM HS20 blade 4355 * server) may crash. 4356 */ 4357 bge_asf_update_status(bgep); 4358 bge_asf_stop_timer(bgep); 4359 bgep->asf_status = ASF_STAT_STOP; 4360 4361 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4362 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4363 } 4364 #endif 4365 bge_chip_stop(bgep, B_TRUE); 4366 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4367 mutex_exit(bgep->genlock); 4368 return (result); 4369 } 4370 4371 /* 4372 * ========== Factotum, implemented as a softint handler ========== 4373 */ 4374 4375 #undef BGE_DBG 4376 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4377 4378 static void bge_factotum_error_handler(bge_t *bgep); 4379 #pragma no_inline(bge_factotum_error_handler) 4380 4381 static void 4382 bge_factotum_error_handler(bge_t *bgep) 4383 { 4384 uint32_t flow; 4385 uint32_t rdma; 4386 uint32_t wdma; 4387 uint32_t tmac; 4388 uint32_t rmac; 4389 uint32_t rxrs; 4390 uint32_t txrs = 0; 4391 4392 ASSERT(mutex_owned(bgep->genlock)); 4393 4394 /* 4395 * Read all the registers that show the possible 4396 * reasons for the ERROR bit to be asserted 4397 */ 4398 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4399 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4400 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4401 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4402 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4403 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4404 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4405 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4406 4407 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4408 (void *)bgep, flow, rdma, wdma)); 4409 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4410 (void *)bgep, tmac, rmac, rxrs, txrs)); 4411 4412 /* 4413 * For now, just clear all the errors ... 4414 */ 4415 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4416 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4417 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4418 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4419 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4420 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4421 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4422 } 4423 4424 /* 4425 * Handler for hardware link state change. 4426 * 4427 * When this routine is called, the hardware link state has changed 4428 * and the new state is reflected in the param_* variables. Here 4429 * we must update the softstate and reprogram the MAC to match. 4430 */ 4431 static void bge_factotum_link_handler(bge_t *bgep); 4432 #pragma no_inline(bge_factotum_link_handler) 4433 4434 static void 4435 bge_factotum_link_handler(bge_t *bgep) 4436 { 4437 ASSERT(mutex_owned(bgep->genlock)); 4438 4439 /* 4440 * Update the s/w link_state 4441 */ 4442 if (bgep->param_link_up) 4443 bgep->link_state = LINK_STATE_UP; 4444 else 4445 bgep->link_state = LINK_STATE_DOWN; 4446 4447 /* 4448 * Reprogram the MAC modes to match 4449 */ 4450 bge_sync_mac_modes(bgep); 4451 } 4452 4453 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4454 #pragma no_inline(bge_factotum_link_check) 4455 4456 static boolean_t 4457 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4458 { 4459 boolean_t check; 4460 uint64_t flags; 4461 uint32_t tmac_status; 4462 4463 ASSERT(mutex_owned(bgep->genlock)); 4464 4465 /* 4466 * Get & clear the writable status bits in the Tx status register 4467 * (some bits are write-1-to-clear, others are just readonly). 4468 */ 4469 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4470 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4471 4472 /* 4473 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4474 */ 4475 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4476 STATUS_FLAG_LINK_CHANGED, &flags); 4477 if (*dma_state != DDI_FM_OK) 4478 return (B_FALSE); 4479 4480 /* 4481 * Clear any errors flagged in the status block ... 4482 */ 4483 if (flags & STATUS_FLAG_ERROR) 4484 bge_factotum_error_handler(bgep); 4485 4486 /* 4487 * We need to check the link status if: 4488 * the status block says there's been a link change 4489 * or there's any discrepancy between the various 4490 * flags indicating the link state (link_state, 4491 * param_link_up, and the LINK STATE bit in the 4492 * Transmit MAC status register). 4493 */ 4494 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4495 switch (bgep->link_state) { 4496 case LINK_STATE_UP: 4497 check |= (bgep->param_link_up == B_FALSE); 4498 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4499 break; 4500 4501 case LINK_STATE_DOWN: 4502 check |= (bgep->param_link_up != B_FALSE); 4503 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4504 break; 4505 4506 default: 4507 check = B_TRUE; 4508 break; 4509 } 4510 4511 /* 4512 * If <check> is false, we're sure the link hasn't changed. 4513 * If true, however, it's not yet definitive; we have to call 4514 * bge_phys_check() to determine whether the link has settled 4515 * into a new state yet ... and if it has, then call the link 4516 * state change handler.But when the chip is 5700 in Dell 6650 4517 * ,even if check is false, the link may have changed.So we 4518 * have to call bge_phys_check() to determine the link state. 4519 */ 4520 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4521 check = bge_phys_check(bgep); 4522 if (check) 4523 bge_factotum_link_handler(bgep); 4524 } 4525 4526 return (check); 4527 } 4528 4529 /* 4530 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4531 */ 4532 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4533 #pragma no_inline(bge_factotum_stall_check) 4534 4535 static boolean_t 4536 bge_factotum_stall_check(bge_t *bgep) 4537 { 4538 uint32_t dogval; 4539 4540 ASSERT(mutex_owned(bgep->genlock)); 4541 4542 /* 4543 * Specific check for Tx stall ... 4544 * 4545 * The 'watchdog' counter is incremented whenever a packet 4546 * is queued, reset to 1 when some (but not all) buffers 4547 * are reclaimed, reset to 0 (disabled) when all buffers 4548 * are reclaimed, and shifted left here. If it exceeds the 4549 * threshold value, the chip is assumed to have stalled and 4550 * is put into the ERROR state. The factotum will then reset 4551 * it on the next pass. 4552 * 4553 * All of which should ensure that we don't get into a state 4554 * where packets are left pending indefinitely! 4555 */ 4556 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4557 if (dogval < bge_watchdog_count) 4558 return (B_FALSE); 4559 4560 #if !defined(BGE_NETCONSOLE) 4561 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4562 #endif 4563 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4564 return (B_TRUE); 4565 } 4566 4567 /* 4568 * The factotum is woken up when there's something to do that we'd rather 4569 * not do from inside a hardware interrupt handler or high-level cyclic. 4570 * Its two main tasks are: 4571 * reset & restart the chip after an error 4572 * check the link status whenever necessary 4573 */ 4574 uint_t bge_chip_factotum(caddr_t arg); 4575 #pragma no_inline(bge_chip_factotum) 4576 4577 uint_t 4578 bge_chip_factotum(caddr_t arg) 4579 { 4580 bge_t *bgep; 4581 uint_t result; 4582 boolean_t error; 4583 boolean_t linkchg; 4584 int dma_state; 4585 4586 bgep = (void *)arg; 4587 4588 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4589 4590 mutex_enter(bgep->softintrlock); 4591 if (bgep->factotum_flag == 0) { 4592 mutex_exit(bgep->softintrlock); 4593 return (DDI_INTR_UNCLAIMED); 4594 } 4595 bgep->factotum_flag = 0; 4596 mutex_exit(bgep->softintrlock); 4597 4598 result = DDI_INTR_CLAIMED; 4599 error = B_FALSE; 4600 linkchg = B_FALSE; 4601 4602 mutex_enter(bgep->genlock); 4603 switch (bgep->bge_chip_state) { 4604 default: 4605 break; 4606 4607 case BGE_CHIP_RUNNING: 4608 linkchg = bge_factotum_link_check(bgep, &dma_state); 4609 error = bge_factotum_stall_check(bgep); 4610 if (dma_state != DDI_FM_OK) { 4611 bgep->bge_dma_error = B_TRUE; 4612 error = B_TRUE; 4613 } 4614 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4615 error = B_TRUE; 4616 if (error) 4617 bgep->bge_chip_state = BGE_CHIP_ERROR; 4618 break; 4619 4620 case BGE_CHIP_ERROR: 4621 error = B_TRUE; 4622 break; 4623 4624 case BGE_CHIP_FAULT: 4625 /* 4626 * Fault detected, time to reset ... 4627 */ 4628 if (bge_autorecover) { 4629 if (!(bgep->progress & PROGRESS_BUFS)) { 4630 /* 4631 * if we can't allocate the ring buffers, 4632 * try later 4633 */ 4634 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4635 mutex_exit(bgep->genlock); 4636 return (result); 4637 } 4638 bgep->progress |= PROGRESS_BUFS; 4639 } 4640 if (!(bgep->progress & PROGRESS_INTR)) { 4641 bge_init_rings(bgep); 4642 bge_intr_enable(bgep); 4643 bgep->progress |= PROGRESS_INTR; 4644 } 4645 if (!(bgep->progress & PROGRESS_KSTATS)) { 4646 bge_init_kstats(bgep, 4647 ddi_get_instance(bgep->devinfo)); 4648 bgep->progress |= PROGRESS_KSTATS; 4649 } 4650 4651 BGE_REPORT((bgep, "automatic recovery activated")); 4652 4653 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4654 bgep->bge_chip_state = BGE_CHIP_ERROR; 4655 error = B_TRUE; 4656 } 4657 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4658 DDI_FM_OK) { 4659 bgep->bge_chip_state = BGE_CHIP_ERROR; 4660 error = B_TRUE; 4661 } 4662 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4663 DDI_FM_OK) { 4664 bgep->bge_chip_state = BGE_CHIP_ERROR; 4665 error = B_TRUE; 4666 } 4667 if (error == B_FALSE) { 4668 #ifdef BGE_IPMI_ASF 4669 if (bgep->asf_enabled && 4670 bgep->asf_status != ASF_STAT_RUN) { 4671 bgep->asf_timeout_id = timeout( 4672 bge_asf_heartbeat, (void *)bgep, 4673 drv_usectohz( 4674 BGE_ASF_HEARTBEAT_INTERVAL)); 4675 bgep->asf_status = ASF_STAT_RUN; 4676 } 4677 #endif 4678 if (!bgep->manual_reset) { 4679 ddi_fm_service_impact(bgep->devinfo, 4680 DDI_SERVICE_RESTORED); 4681 } 4682 } 4683 } 4684 break; 4685 } 4686 4687 4688 /* 4689 * If an error is detected, stop the chip now, marking it as 4690 * faulty, so that it will be reset next time through ... 4691 * 4692 * Note that if intr_running is set, then bge_intr() has dropped 4693 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4694 * this point so have to wait until the next time the factotum runs. 4695 */ 4696 if (error && !bgep->bge_intr_running) { 4697 #ifdef BGE_IPMI_ASF 4698 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4699 /* 4700 * We must stop ASF heart beat before bge_chip_stop(), 4701 * otherwise some computers (ex. IBM HS20 blade server) 4702 * may crash. 4703 */ 4704 bge_asf_update_status(bgep); 4705 bge_asf_stop_timer(bgep); 4706 bgep->asf_status = ASF_STAT_STOP; 4707 4708 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4709 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4710 } 4711 #endif 4712 bge_chip_stop(bgep, B_TRUE); 4713 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4714 } 4715 mutex_exit(bgep->genlock); 4716 4717 /* 4718 * If the link state changed, tell the world about it. 4719 * Note: can't do this while still holding the mutex. 4720 */ 4721 if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT && 4722 bgep->link_state != LINK_STATE_UNKNOWN) 4723 linkchg = B_TRUE; 4724 else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT && 4725 bgep->link_state == LINK_STATE_DOWN) 4726 linkchg = B_FALSE; 4727 4728 if (linkchg) { 4729 mac_link_update(bgep->mh, bgep->link_state); 4730 bgep->link_update_timer = BGE_LINK_UPDATE_DONE; 4731 } 4732 if (bgep->manual_reset) { 4733 bgep->manual_reset = B_FALSE; 4734 } 4735 4736 return (result); 4737 } 4738 4739 /* 4740 * High-level cyclic handler 4741 * 4742 * This routine schedules a (low-level) softint callback to the 4743 * factotum, and prods the chip to update the status block (which 4744 * will cause a hardware interrupt when complete). 4745 */ 4746 void bge_chip_cyclic(void *arg); 4747 #pragma no_inline(bge_chip_cyclic) 4748 4749 void 4750 bge_chip_cyclic(void *arg) 4751 { 4752 bge_t *bgep; 4753 4754 bgep = arg; 4755 4756 switch (bgep->bge_chip_state) { 4757 default: 4758 return; 4759 4760 case BGE_CHIP_RUNNING: 4761 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4762 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4763 ddi_fm_service_impact(bgep->devinfo, 4764 DDI_SERVICE_UNAFFECTED); 4765 4766 if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT) 4767 bgep->link_update_timer++; 4768 4769 break; 4770 4771 case BGE_CHIP_FAULT: 4772 case BGE_CHIP_ERROR: 4773 break; 4774 } 4775 4776 bge_wake_factotum(bgep); 4777 } 4778 4779 4780 /* 4781 * ========== Ioctl subfunctions ========== 4782 */ 4783 4784 #undef BGE_DBG 4785 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4786 4787 #if BGE_DEBUGGING || BGE_DO_PPIO 4788 4789 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4790 #pragma no_inline(bge_chip_peek_cfg) 4791 4792 static void 4793 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4794 { 4795 uint64_t regval; 4796 uint64_t regno; 4797 4798 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4799 (void *)bgep, (void *)ppd)); 4800 4801 regno = ppd->pp_acc_offset; 4802 4803 switch (ppd->pp_acc_size) { 4804 case 1: 4805 regval = pci_config_get8(bgep->cfg_handle, regno); 4806 break; 4807 4808 case 2: 4809 regval = pci_config_get16(bgep->cfg_handle, regno); 4810 break; 4811 4812 case 4: 4813 regval = pci_config_get32(bgep->cfg_handle, regno); 4814 break; 4815 4816 case 8: 4817 regval = pci_config_get64(bgep->cfg_handle, regno); 4818 break; 4819 } 4820 4821 ppd->pp_acc_data = regval; 4822 } 4823 4824 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4825 #pragma no_inline(bge_chip_poke_cfg) 4826 4827 static void 4828 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4829 { 4830 uint64_t regval; 4831 uint64_t regno; 4832 4833 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4834 (void *)bgep, (void *)ppd)); 4835 4836 regno = ppd->pp_acc_offset; 4837 regval = ppd->pp_acc_data; 4838 4839 switch (ppd->pp_acc_size) { 4840 case 1: 4841 pci_config_put8(bgep->cfg_handle, regno, regval); 4842 break; 4843 4844 case 2: 4845 pci_config_put16(bgep->cfg_handle, regno, regval); 4846 break; 4847 4848 case 4: 4849 pci_config_put32(bgep->cfg_handle, regno, regval); 4850 break; 4851 4852 case 8: 4853 pci_config_put64(bgep->cfg_handle, regno, regval); 4854 break; 4855 } 4856 } 4857 4858 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4859 #pragma no_inline(bge_chip_peek_reg) 4860 4861 static void 4862 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4863 { 4864 uint64_t regval; 4865 void *regaddr; 4866 4867 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4868 (void *)bgep, (void *)ppd)); 4869 4870 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4871 4872 switch (ppd->pp_acc_size) { 4873 case 1: 4874 regval = ddi_get8(bgep->io_handle, regaddr); 4875 break; 4876 4877 case 2: 4878 regval = ddi_get16(bgep->io_handle, regaddr); 4879 break; 4880 4881 case 4: 4882 regval = ddi_get32(bgep->io_handle, regaddr); 4883 break; 4884 4885 case 8: 4886 regval = ddi_get64(bgep->io_handle, regaddr); 4887 break; 4888 } 4889 4890 ppd->pp_acc_data = regval; 4891 } 4892 4893 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4894 #pragma no_inline(bge_chip_peek_reg) 4895 4896 static void 4897 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4898 { 4899 uint64_t regval; 4900 void *regaddr; 4901 4902 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4903 (void *)bgep, (void *)ppd)); 4904 4905 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4906 regval = ppd->pp_acc_data; 4907 4908 switch (ppd->pp_acc_size) { 4909 case 1: 4910 ddi_put8(bgep->io_handle, regaddr, regval); 4911 break; 4912 4913 case 2: 4914 ddi_put16(bgep->io_handle, regaddr, regval); 4915 break; 4916 4917 case 4: 4918 ddi_put32(bgep->io_handle, regaddr, regval); 4919 break; 4920 4921 case 8: 4922 ddi_put64(bgep->io_handle, regaddr, regval); 4923 break; 4924 } 4925 BGE_PCICHK(bgep); 4926 } 4927 4928 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4929 #pragma no_inline(bge_chip_peek_nic) 4930 4931 static void 4932 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4933 { 4934 uint64_t regoff; 4935 uint64_t regval; 4936 void *regaddr; 4937 4938 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4939 (void *)bgep, (void *)ppd)); 4940 4941 regoff = ppd->pp_acc_offset; 4942 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4943 regoff &= MWBAR_GRANULE_MASK; 4944 regoff += NIC_MEM_WINDOW_OFFSET; 4945 regaddr = PIO_ADDR(bgep, regoff); 4946 4947 switch (ppd->pp_acc_size) { 4948 case 1: 4949 regval = ddi_get8(bgep->io_handle, regaddr); 4950 break; 4951 4952 case 2: 4953 regval = ddi_get16(bgep->io_handle, regaddr); 4954 break; 4955 4956 case 4: 4957 regval = ddi_get32(bgep->io_handle, regaddr); 4958 break; 4959 4960 case 8: 4961 regval = ddi_get64(bgep->io_handle, regaddr); 4962 break; 4963 } 4964 4965 ppd->pp_acc_data = regval; 4966 } 4967 4968 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4969 #pragma no_inline(bge_chip_poke_nic) 4970 4971 static void 4972 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4973 { 4974 uint64_t regoff; 4975 uint64_t regval; 4976 void *regaddr; 4977 4978 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4979 (void *)bgep, (void *)ppd)); 4980 4981 regoff = ppd->pp_acc_offset; 4982 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4983 regoff &= MWBAR_GRANULE_MASK; 4984 regoff += NIC_MEM_WINDOW_OFFSET; 4985 regaddr = PIO_ADDR(bgep, regoff); 4986 regval = ppd->pp_acc_data; 4987 4988 switch (ppd->pp_acc_size) { 4989 case 1: 4990 ddi_put8(bgep->io_handle, regaddr, regval); 4991 break; 4992 4993 case 2: 4994 ddi_put16(bgep->io_handle, regaddr, regval); 4995 break; 4996 4997 case 4: 4998 ddi_put32(bgep->io_handle, regaddr, regval); 4999 break; 5000 5001 case 8: 5002 ddi_put64(bgep->io_handle, regaddr, regval); 5003 break; 5004 } 5005 BGE_PCICHK(bgep); 5006 } 5007 5008 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5009 #pragma no_inline(bge_chip_peek_mii) 5010 5011 static void 5012 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5013 { 5014 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 5015 (void *)bgep, (void *)ppd)); 5016 5017 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 5018 } 5019 5020 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5021 #pragma no_inline(bge_chip_poke_mii) 5022 5023 static void 5024 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5025 { 5026 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 5027 (void *)bgep, (void *)ppd)); 5028 5029 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 5030 } 5031 5032 #if BGE_SEE_IO32 5033 5034 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5035 #pragma no_inline(bge_chip_peek_seeprom) 5036 5037 static void 5038 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5039 { 5040 uint32_t data; 5041 int err; 5042 5043 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 5044 (void *)bgep, (void *)ppd)); 5045 5046 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 5047 ppd->pp_acc_data = err ? ~0ull : data; 5048 } 5049 5050 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5051 #pragma no_inline(bge_chip_poke_seeprom) 5052 5053 static void 5054 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5055 { 5056 uint32_t data; 5057 5058 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 5059 (void *)bgep, (void *)ppd)); 5060 5061 data = ppd->pp_acc_data; 5062 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 5063 } 5064 #endif /* BGE_SEE_IO32 */ 5065 5066 #if BGE_FLASH_IO32 5067 5068 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5069 #pragma no_inline(bge_chip_peek_flash) 5070 5071 static void 5072 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5073 { 5074 uint32_t data; 5075 int err; 5076 5077 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 5078 (void *)bgep, (void *)ppd)); 5079 5080 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 5081 ppd->pp_acc_data = err ? ~0ull : data; 5082 } 5083 5084 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5085 #pragma no_inline(bge_chip_poke_flash) 5086 5087 static void 5088 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5089 { 5090 uint32_t data; 5091 5092 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 5093 (void *)bgep, (void *)ppd)); 5094 5095 data = ppd->pp_acc_data; 5096 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 5097 ppd->pp_acc_offset, &data); 5098 } 5099 #endif /* BGE_FLASH_IO32 */ 5100 5101 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5102 #pragma no_inline(bge_chip_peek_mem) 5103 5104 static void 5105 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5106 { 5107 uint64_t regval; 5108 void *vaddr; 5109 5110 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 5111 (void *)bgep, (void *)ppd)); 5112 5113 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5114 5115 switch (ppd->pp_acc_size) { 5116 case 1: 5117 regval = *(uint8_t *)vaddr; 5118 break; 5119 5120 case 2: 5121 regval = *(uint16_t *)vaddr; 5122 break; 5123 5124 case 4: 5125 regval = *(uint32_t *)vaddr; 5126 break; 5127 5128 case 8: 5129 regval = *(uint64_t *)vaddr; 5130 break; 5131 } 5132 5133 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 5134 (void *)bgep, (void *)ppd, regval, vaddr)); 5135 5136 ppd->pp_acc_data = regval; 5137 } 5138 5139 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5140 #pragma no_inline(bge_chip_poke_mem) 5141 5142 static void 5143 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5144 { 5145 uint64_t regval; 5146 void *vaddr; 5147 5148 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 5149 (void *)bgep, (void *)ppd)); 5150 5151 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5152 regval = ppd->pp_acc_data; 5153 5154 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 5155 (void *)bgep, (void *)ppd, regval, vaddr)); 5156 5157 switch (ppd->pp_acc_size) { 5158 case 1: 5159 *(uint8_t *)vaddr = (uint8_t)regval; 5160 break; 5161 5162 case 2: 5163 *(uint16_t *)vaddr = (uint16_t)regval; 5164 break; 5165 5166 case 4: 5167 *(uint32_t *)vaddr = (uint32_t)regval; 5168 break; 5169 5170 case 8: 5171 *(uint64_t *)vaddr = (uint64_t)regval; 5172 break; 5173 } 5174 } 5175 5176 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5177 struct iocblk *iocp); 5178 #pragma no_inline(bge_pp_ioctl) 5179 5180 static enum ioc_reply 5181 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5182 { 5183 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 5184 bge_peekpoke_t *ppd; 5185 dma_area_t *areap; 5186 uint64_t sizemask; 5187 uint64_t mem_va; 5188 uint64_t maxoff; 5189 boolean_t peek; 5190 5191 switch (cmd) { 5192 default: 5193 /* NOTREACHED */ 5194 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 5195 return (IOC_INVAL); 5196 5197 case BGE_PEEK: 5198 peek = B_TRUE; 5199 break; 5200 5201 case BGE_POKE: 5202 peek = B_FALSE; 5203 break; 5204 } 5205 5206 /* 5207 * Validate format of ioctl 5208 */ 5209 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 5210 return (IOC_INVAL); 5211 if (mp->b_cont == NULL) 5212 return (IOC_INVAL); 5213 ppd = (void *)mp->b_cont->b_rptr; 5214 5215 /* 5216 * Validate request parameters 5217 */ 5218 switch (ppd->pp_acc_space) { 5219 default: 5220 return (IOC_INVAL); 5221 5222 case BGE_PP_SPACE_CFG: 5223 /* 5224 * Config space 5225 */ 5226 sizemask = 8|4|2|1; 5227 mem_va = 0; 5228 maxoff = PCI_CONF_HDR_SIZE; 5229 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 5230 break; 5231 5232 case BGE_PP_SPACE_REG: 5233 /* 5234 * Memory-mapped I/O space 5235 */ 5236 sizemask = 8|4|2|1; 5237 mem_va = 0; 5238 maxoff = RIAAR_REGISTER_MAX; 5239 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 5240 break; 5241 5242 case BGE_PP_SPACE_NIC: 5243 /* 5244 * NIC on-chip memory 5245 */ 5246 sizemask = 8|4|2|1; 5247 mem_va = 0; 5248 maxoff = MWBAR_ONCHIP_MAX; 5249 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 5250 break; 5251 5252 case BGE_PP_SPACE_MII: 5253 /* 5254 * PHY's MII registers 5255 * NB: all PHY registers are two bytes, but the 5256 * addresses increment in ones (word addressing). 5257 * So we scale the address here, then undo the 5258 * transformation inside the peek/poke functions. 5259 */ 5260 ppd->pp_acc_offset *= 2; 5261 sizemask = 2; 5262 mem_va = 0; 5263 maxoff = (MII_MAXREG+1)*2; 5264 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5265 break; 5266 5267 #if BGE_SEE_IO32 5268 case BGE_PP_SPACE_SEEPROM: 5269 /* 5270 * Attached SEEPROM(s), if any. 5271 * NB: we use the high-order bits of the 'address' as 5272 * a device select to accommodate multiple SEEPROMS, 5273 * If each one is the maximum size (64kbytes), this 5274 * makes them appear contiguous. Otherwise, there may 5275 * be holes in the mapping. ENxS doesn't have any 5276 * SEEPROMs anyway ... 5277 */ 5278 sizemask = 4; 5279 mem_va = 0; 5280 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5281 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5282 break; 5283 #endif /* BGE_SEE_IO32 */ 5284 5285 #if BGE_FLASH_IO32 5286 case BGE_PP_SPACE_FLASH: 5287 /* 5288 * Attached Flash device (if any); a maximum of one device 5289 * is currently supported. But it can be up to 1MB (unlike 5290 * the 64k limit on SEEPROMs) so why would you need more ;-) 5291 */ 5292 sizemask = 4; 5293 mem_va = 0; 5294 maxoff = NVM_FLASH_ADDR_MASK; 5295 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5296 break; 5297 #endif /* BGE_FLASH_IO32 */ 5298 5299 case BGE_PP_SPACE_BGE: 5300 /* 5301 * BGE data structure! 5302 */ 5303 sizemask = 8|4|2|1; 5304 mem_va = (uintptr_t)bgep; 5305 maxoff = sizeof (*bgep); 5306 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5307 break; 5308 5309 case BGE_PP_SPACE_STATUS: 5310 case BGE_PP_SPACE_STATISTICS: 5311 case BGE_PP_SPACE_TXDESC: 5312 case BGE_PP_SPACE_TXBUFF: 5313 case BGE_PP_SPACE_RXDESC: 5314 case BGE_PP_SPACE_RXBUFF: 5315 /* 5316 * Various DMA_AREAs 5317 */ 5318 switch (ppd->pp_acc_space) { 5319 case BGE_PP_SPACE_TXDESC: 5320 areap = &bgep->tx_desc; 5321 break; 5322 case BGE_PP_SPACE_TXBUFF: 5323 areap = &bgep->tx_buff[0]; 5324 break; 5325 case BGE_PP_SPACE_RXDESC: 5326 areap = &bgep->rx_desc[0]; 5327 break; 5328 case BGE_PP_SPACE_RXBUFF: 5329 areap = &bgep->rx_buff[0]; 5330 break; 5331 case BGE_PP_SPACE_STATUS: 5332 areap = &bgep->status_block; 5333 break; 5334 case BGE_PP_SPACE_STATISTICS: 5335 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5336 areap = &bgep->statistics; 5337 break; 5338 } 5339 5340 sizemask = 8|4|2|1; 5341 mem_va = (uintptr_t)areap->mem_va; 5342 maxoff = areap->alength; 5343 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5344 break; 5345 } 5346 5347 switch (ppd->pp_acc_size) { 5348 default: 5349 return (IOC_INVAL); 5350 5351 case 8: 5352 case 4: 5353 case 2: 5354 case 1: 5355 if ((ppd->pp_acc_size & sizemask) == 0) 5356 return (IOC_INVAL); 5357 break; 5358 } 5359 5360 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5361 return (IOC_INVAL); 5362 5363 if (ppd->pp_acc_offset >= maxoff) 5364 return (IOC_INVAL); 5365 5366 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5367 return (IOC_INVAL); 5368 5369 /* 5370 * All OK - go do it! 5371 */ 5372 ppd->pp_acc_offset += mem_va; 5373 (*ppfn)(bgep, ppd); 5374 return (peek ? IOC_REPLY : IOC_ACK); 5375 } 5376 5377 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5378 struct iocblk *iocp); 5379 #pragma no_inline(bge_diag_ioctl) 5380 5381 static enum ioc_reply 5382 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5383 { 5384 ASSERT(mutex_owned(bgep->genlock)); 5385 5386 switch (cmd) { 5387 default: 5388 /* NOTREACHED */ 5389 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5390 return (IOC_INVAL); 5391 5392 case BGE_DIAG: 5393 /* 5394 * Currently a no-op 5395 */ 5396 return (IOC_ACK); 5397 5398 case BGE_PEEK: 5399 case BGE_POKE: 5400 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5401 5402 case BGE_PHY_RESET: 5403 return (IOC_RESTART_ACK); 5404 5405 case BGE_SOFT_RESET: 5406 case BGE_HARD_RESET: 5407 /* 5408 * Reset and reinitialise the 570x hardware 5409 */ 5410 bgep->bge_chip_state = BGE_CHIP_FAULT; 5411 ddi_trigger_softintr(bgep->factotum_id); 5412 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5413 return (IOC_ACK); 5414 } 5415 5416 /* NOTREACHED */ 5417 } 5418 5419 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5420 5421 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5422 struct iocblk *iocp); 5423 #pragma no_inline(bge_mii_ioctl) 5424 5425 static enum ioc_reply 5426 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5427 { 5428 struct bge_mii_rw *miirwp; 5429 5430 /* 5431 * Validate format of ioctl 5432 */ 5433 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5434 return (IOC_INVAL); 5435 if (mp->b_cont == NULL) 5436 return (IOC_INVAL); 5437 miirwp = (void *)mp->b_cont->b_rptr; 5438 5439 /* 5440 * Validate request parameters ... 5441 */ 5442 if (miirwp->mii_reg > MII_MAXREG) 5443 return (IOC_INVAL); 5444 5445 switch (cmd) { 5446 default: 5447 /* NOTREACHED */ 5448 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5449 return (IOC_INVAL); 5450 5451 case BGE_MII_READ: 5452 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5453 return (IOC_REPLY); 5454 5455 case BGE_MII_WRITE: 5456 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5457 return (IOC_ACK); 5458 } 5459 5460 /* NOTREACHED */ 5461 } 5462 5463 #if BGE_SEE_IO32 5464 5465 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5466 struct iocblk *iocp); 5467 #pragma no_inline(bge_see_ioctl) 5468 5469 static enum ioc_reply 5470 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5471 { 5472 struct bge_see_rw *seerwp; 5473 5474 /* 5475 * Validate format of ioctl 5476 */ 5477 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5478 return (IOC_INVAL); 5479 if (mp->b_cont == NULL) 5480 return (IOC_INVAL); 5481 seerwp = (void *)mp->b_cont->b_rptr; 5482 5483 /* 5484 * Validate request parameters ... 5485 */ 5486 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5487 return (IOC_INVAL); 5488 5489 switch (cmd) { 5490 default: 5491 /* NOTREACHED */ 5492 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5493 return (IOC_INVAL); 5494 5495 case BGE_SEE_READ: 5496 case BGE_SEE_WRITE: 5497 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5498 seerwp->see_addr, &seerwp->see_data); 5499 return (IOC_REPLY); 5500 } 5501 5502 /* NOTREACHED */ 5503 } 5504 5505 #endif /* BGE_SEE_IO32 */ 5506 5507 #if BGE_FLASH_IO32 5508 5509 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5510 struct iocblk *iocp); 5511 #pragma no_inline(bge_flash_ioctl) 5512 5513 static enum ioc_reply 5514 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5515 { 5516 struct bge_flash_rw *flashrwp; 5517 5518 /* 5519 * Validate format of ioctl 5520 */ 5521 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5522 return (IOC_INVAL); 5523 if (mp->b_cont == NULL) 5524 return (IOC_INVAL); 5525 flashrwp = (void *)mp->b_cont->b_rptr; 5526 5527 /* 5528 * Validate request parameters ... 5529 */ 5530 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5531 return (IOC_INVAL); 5532 5533 switch (cmd) { 5534 default: 5535 /* NOTREACHED */ 5536 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5537 return (IOC_INVAL); 5538 5539 case BGE_FLASH_READ: 5540 case BGE_FLASH_WRITE: 5541 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5542 flashrwp->flash_addr, &flashrwp->flash_data); 5543 return (IOC_REPLY); 5544 } 5545 5546 /* NOTREACHED */ 5547 } 5548 5549 #endif /* BGE_FLASH_IO32 */ 5550 5551 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5552 struct iocblk *iocp); 5553 #pragma no_inline(bge_chip_ioctl) 5554 5555 enum ioc_reply 5556 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5557 { 5558 int cmd; 5559 5560 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5561 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5562 5563 ASSERT(mutex_owned(bgep->genlock)); 5564 5565 cmd = iocp->ioc_cmd; 5566 switch (cmd) { 5567 default: 5568 /* NOTREACHED */ 5569 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5570 return (IOC_INVAL); 5571 5572 case BGE_DIAG: 5573 case BGE_PEEK: 5574 case BGE_POKE: 5575 case BGE_PHY_RESET: 5576 case BGE_SOFT_RESET: 5577 case BGE_HARD_RESET: 5578 #if BGE_DEBUGGING || BGE_DO_PPIO 5579 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5580 #else 5581 return (IOC_INVAL); 5582 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5583 5584 case BGE_MII_READ: 5585 case BGE_MII_WRITE: 5586 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5587 5588 #if BGE_SEE_IO32 5589 case BGE_SEE_READ: 5590 case BGE_SEE_WRITE: 5591 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5592 #endif /* BGE_SEE_IO32 */ 5593 5594 #if BGE_FLASH_IO32 5595 case BGE_FLASH_READ: 5596 case BGE_FLASH_WRITE: 5597 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5598 #endif /* BGE_FLASH_IO32 */ 5599 } 5600 5601 /* NOTREACHED */ 5602 } 5603 5604 /* ARGSUSED */ 5605 void 5606 bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag) 5607 { 5608 recv_ring_t *rrp = arg; 5609 bge_t *bgep = rrp->bgep; 5610 5611 mutex_enter(bgep->genlock); 5612 rrp->poll_flag = flag; 5613 #ifdef NOT_YET 5614 /* 5615 * XXX-Sunay: Since most broadcom cards support only one 5616 * interrupt but multiple rx rings, we can't disable the 5617 * physical interrupt. This need to be done via capability 5618 * negotiation depending on the NIC. 5619 */ 5620 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5621 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5622 #endif 5623 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5624 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5625 mutex_exit(bgep->genlock); 5626 } 5627 5628 #ifdef BGE_IPMI_ASF 5629 5630 uint32_t 5631 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5632 { 5633 uint32_t data; 5634 5635 #ifndef __sparc 5636 if (!bgep->asf_wordswapped) { 5637 /* a workaround word swap error */ 5638 if (addr & 4) 5639 addr = addr - 4; 5640 else 5641 addr = addr + 4; 5642 } 5643 #endif 5644 5645 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5646 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5647 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5648 5649 data = LE_32(data); 5650 return (data); 5651 } 5652 5653 void 5654 bge_asf_update_status(bge_t *bgep) 5655 { 5656 uint32_t event; 5657 5658 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5659 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5660 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5661 5662 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5663 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5664 } 5665 5666 5667 /* 5668 * The driver is supposed to notify ASF that the OS is still running 5669 * every three seconds, otherwise the management server may attempt 5670 * to reboot the machine. If it hasn't actually failed, this is 5671 * not a desirable result. However, this isn't running as a real-time 5672 * thread, and even if it were, it might not be able to generate the 5673 * heartbeat in a timely manner due to system load. As it isn't a 5674 * significant strain on the machine, we will set the interval to half 5675 * of the required value. 5676 */ 5677 void 5678 bge_asf_heartbeat(void *arg) 5679 { 5680 bge_t *bgep = (bge_t *)arg; 5681 5682 mutex_enter(bgep->genlock); 5683 bge_asf_update_status((bge_t *)bgep); 5684 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5685 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5686 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5687 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5688 mutex_exit(bgep->genlock); 5689 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5690 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5691 } 5692 5693 5694 void 5695 bge_asf_stop_timer(bge_t *bgep) 5696 { 5697 timeout_id_t tmp_id = 0; 5698 5699 while ((bgep->asf_timeout_id != 0) && 5700 (tmp_id != bgep->asf_timeout_id)) { 5701 tmp_id = bgep->asf_timeout_id; 5702 (void) untimeout(tmp_id); 5703 } 5704 bgep->asf_timeout_id = 0; 5705 } 5706 5707 5708 5709 /* 5710 * This function should be placed at the earliest position of bge_attach(). 5711 */ 5712 void 5713 bge_asf_get_config(bge_t *bgep) 5714 { 5715 uint32_t nicsig; 5716 uint32_t niccfg; 5717 5718 bgep->asf_enabled = B_FALSE; 5719 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5720 if (nicsig == BGE_NIC_DATA_SIG) { 5721 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5722 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5723 /* 5724 * Here, we don't consider BAXTER, because BGE haven't 5725 * supported BAXTER (that is 5752). Also, as I know, 5726 * BAXTER doesn't support ASF feature. 5727 */ 5728 bgep->asf_enabled = B_TRUE; 5729 else 5730 bgep->asf_enabled = B_FALSE; 5731 } else 5732 bgep->asf_enabled = B_FALSE; 5733 } 5734 5735 5736 void 5737 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5738 { 5739 uint32_t tries; 5740 uint32_t event; 5741 5742 ASSERT(bgep->asf_enabled); 5743 5744 /* Issues "pause firmware" command and wait for ACK */ 5745 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5746 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5747 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5748 5749 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5750 tries = 0; 5751 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5752 drv_usecwait(1); 5753 tries ++; 5754 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5755 } 5756 5757 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5758 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5759 5760 if (bgep->asf_newhandshake) { 5761 switch (mode) { 5762 case BGE_INIT_RESET: 5763 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5764 BGE_DRV_STATE_START); 5765 break; 5766 case BGE_SHUTDOWN_RESET: 5767 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5768 BGE_DRV_STATE_UNLOAD); 5769 break; 5770 case BGE_SUSPEND_RESET: 5771 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5772 BGE_DRV_STATE_SUSPEND); 5773 break; 5774 default: 5775 break; 5776 } 5777 } 5778 } 5779 5780 5781 void 5782 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5783 { 5784 switch (mode) { 5785 case BGE_INIT_RESET: 5786 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5787 BGE_DRV_STATE_START); 5788 break; 5789 case BGE_SHUTDOWN_RESET: 5790 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5791 BGE_DRV_STATE_UNLOAD); 5792 break; 5793 case BGE_SUSPEND_RESET: 5794 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5795 BGE_DRV_STATE_SUSPEND); 5796 break; 5797 default: 5798 break; 5799 } 5800 } 5801 5802 5803 void 5804 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5805 { 5806 switch (mode) { 5807 case BGE_INIT_RESET: 5808 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5809 BGE_DRV_STATE_START_DONE); 5810 break; 5811 case BGE_SHUTDOWN_RESET: 5812 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5813 BGE_DRV_STATE_UNLOAD_DONE); 5814 break; 5815 default: 5816 break; 5817 } 5818 } 5819 5820 #endif /* BGE_IPMI_ASF */ 5821