1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include "bge_impl.h" 28 29 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 30 31 /* 32 * Future features ... ? 33 */ 34 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 35 #define BGE_IND_IO32 1 /* indirect access code */ 36 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 37 #define BGE_FLASH_IO32 1 /* FLASH access code */ 38 39 /* 40 * BGE MSI tunable: 41 * 42 * By default MSI is enabled on all supported platforms but it is disabled 43 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 44 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 45 */ 46 boolean_t bge_enable_msi = B_TRUE; 47 48 /* 49 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 50 */ 51 boolean_t bge_relaxed_ordering = B_TRUE; 52 53 /* 54 * Property names 55 */ 56 static char knownids_propname[] = "bge-known-subsystems"; 57 58 /* 59 * Patchable globals: 60 * 61 * bge_autorecover 62 * Enables/disables automatic recovery after fault detection 63 * 64 * bge_mlcr_default 65 * Value to program into the MLCR; controls the chip's GPIO pins 66 * 67 * bge_dma_{rd,wr}prio 68 * Relative priorities of DMA reads & DMA writes respectively. 69 * These may each be patched to any value 0-3. Equal values 70 * will give "fair" (round-robin) arbitration for PCI access. 71 * Unequal values will give one or the other function priority. 72 * 73 * bge_dma_rwctrl 74 * Value to put in the Read/Write DMA control register. See 75 * the Broadcom PRM for things you can fiddle with in this 76 * register ... 77 * 78 * bge_{tx,rx}_{count,ticks}_{norm,intr} 79 * Send/receive interrupt coalescing parameters. Counts are 80 * #s of descriptors, ticks are in microseconds. *norm* values 81 * apply between status updates/interrupts; the *intr* values 82 * refer to the 'during-interrupt' versions - see the PRM. 83 * 84 * NOTE: these values have been determined by measurement. They 85 * differ significantly from the values recommended in the PRM. 86 */ 87 static uint32_t bge_autorecover = 1; 88 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 89 90 static uint32_t bge_dma_rdprio = 1; 91 static uint32_t bge_dma_wrprio = 0; 92 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 93 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 94 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 95 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 96 97 uint32_t bge_rx_ticks_norm = 128; 98 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 99 uint32_t bge_rx_count_norm = 8; 100 uint32_t bge_tx_count_norm = 128; 101 102 static uint32_t bge_rx_ticks_intr = 128; 103 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 104 static uint32_t bge_rx_count_intr = 2; 105 static uint32_t bge_tx_count_intr = 0; 106 107 /* 108 * Memory pool configuration parameters. 109 * 110 * These are generally specific to each member of the chip family, since 111 * each one may have a different memory size/configuration. 112 * 113 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 114 * the driver from programming the various registers; instead they are left 115 * at their hardware defaults. This is the preferred option for later chips 116 * (5705+), whereas the older chips *required* these registers to be set, 117 * since the h/w default was 0 ;-( 118 */ 119 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 120 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 121 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 122 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 123 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 124 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 125 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 126 static uint32_t bge_mbuf_pool_len_5721 = 0; 127 128 /* 129 * Various high and low water marks, thresholds, etc ... 130 * 131 * Note: these are taken from revision 7 of the PRM, and some are different 132 * from both the values in earlier PRMs *and* those determined experimentally 133 * and used in earlier versions of this driver ... 134 */ 135 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 136 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 137 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 138 139 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 140 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 141 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 142 143 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 144 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 145 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 146 147 static uint32_t bge_watchdog_count = 1 << 16; 148 static uint16_t bge_dma_miss_limit = 20; 149 150 static uint32_t bge_stop_start_on_sync = 0; 151 152 /* 153 * bge_intr_max_loop controls the maximum loop number within bge_intr. 154 * When loading NIC with heavy network traffic, it is useful. 155 * Increasing this value could have positive effect to throughput, 156 * but it might also increase ticks of a bge ISR stick on CPU, which might 157 * lead to bad UI interactive experience. So tune this with caution. 158 */ 159 static int bge_intr_max_loop = 1; 160 161 /* 162 * ========== Low-level chip & ring buffer manipulation ========== 163 */ 164 165 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 166 167 168 /* 169 * Config space read-modify-write routines 170 */ 171 172 #if BGE_CFG_IO8 173 174 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 175 #pragma inline(bge_cfg_clr16) 176 177 static void 178 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 179 { 180 uint16_t regval; 181 182 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 183 (void *)bgep, regno, bits)); 184 185 regval = pci_config_get16(bgep->cfg_handle, regno); 186 187 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 188 (void *)bgep, regno, bits, regval, regval & ~bits)); 189 190 regval &= ~bits; 191 pci_config_put16(bgep->cfg_handle, regno, regval); 192 } 193 194 #endif /* BGE_CFG_IO8 */ 195 196 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 197 #pragma inline(bge_cfg_clr32) 198 199 static void 200 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 201 { 202 uint32_t regval; 203 204 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 205 (void *)bgep, regno, bits)); 206 207 regval = pci_config_get32(bgep->cfg_handle, regno); 208 209 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 210 (void *)bgep, regno, bits, regval, regval & ~bits)); 211 212 regval &= ~bits; 213 pci_config_put32(bgep->cfg_handle, regno, regval); 214 } 215 216 #if BGE_IND_IO32 217 218 /* 219 * Indirect access to registers & RISC scratchpads, using config space 220 * accesses only. 221 * 222 * This isn't currently used, but someday we might want to use it for 223 * restoring the Subsystem Device/Vendor registers (which aren't directly 224 * writable in Config Space), or for downloading firmware into the RISCs 225 * 226 * In any case there are endian issues to be resolved before this code is 227 * enabled; the bizarre way that bytes get twisted by this chip AND by 228 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 229 * it's been thoroughly tested for all access sizes on all supported 230 * architectures (SPARC *and* x86!). 231 */ 232 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 233 #pragma inline(bge_ind_get32) 234 235 uint32_t 236 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 237 { 238 uint32_t val; 239 240 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 241 242 #ifdef __sparc 243 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 244 regno = LE_32(regno); 245 #endif 246 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 247 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 248 249 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 250 (void *)bgep, regno, val)); 251 252 val = LE_32(val); 253 254 return (val); 255 } 256 257 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 258 #pragma inline(bge_ind_put32) 259 260 void 261 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 262 { 263 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 264 (void *)bgep, regno, val)); 265 266 val = LE_32(val); 267 #ifdef __sparc 268 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 269 regno = LE_32(regno); 270 #endif 271 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 272 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 273 } 274 275 #endif /* BGE_IND_IO32 */ 276 277 #if BGE_DEBUGGING 278 279 static void bge_pci_check(bge_t *bgep); 280 #pragma no_inline(bge_pci_check) 281 282 static void 283 bge_pci_check(bge_t *bgep) 284 { 285 uint16_t pcistatus; 286 287 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 288 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 289 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 290 (void *)bgep, pcistatus)); 291 } 292 293 #endif /* BGE_DEBUGGING */ 294 295 /* 296 * Perform first-stage chip (re-)initialisation, using only config-space 297 * accesses: 298 * 299 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 300 * returning the data in the structure pointed to by <idp>. 301 * + Configure the target-mode endianness (swap) options. 302 * + Disable interrupts and enable Memory Space accesses. 303 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 304 * 305 * This sequence is adapted from Broadcom document 570X-PG102-R, 306 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 307 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 308 * 309 * This function MUST be called before any non-config-space accesses 310 * are made; on this first call <enable_dma> is B_FALSE, and it 311 * effectively performs steps 3-1(!) of the initialisation sequence 312 * (the rest are not required but should be harmless). 313 * 314 * It MUST also be called after a chip reset, as this disables 315 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 316 * it is effectively performing steps 6-8. 317 */ 318 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 319 #pragma no_inline(bge_chip_cfg_init) 320 321 void 322 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 323 { 324 ddi_acc_handle_t handle; 325 uint16_t command; 326 uint32_t mhcr; 327 uint16_t value16; 328 int i; 329 330 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 331 (void *)bgep, (void *)cidp, enable_dma)); 332 333 /* 334 * Step 3: save PCI cache line size and subsystem vendor ID 335 * 336 * Read all the config-space registers that characterise the 337 * chip, specifically vendor/device/revision/subsystem vendor 338 * and subsystem device id. We expect (but don't check) that 339 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 340 * 341 * Also save all bus-transaction related registers (cache-line 342 * size, bus-grant/latency parameters, etc). Some of these are 343 * cleared by reset, so we'll have to restore them later. This 344 * comes from the Broadcom document 570X-PG102-R ... 345 * 346 * Note: Broadcom document 570X-PG102-R seems to be in error 347 * here w.r.t. the offsets of the Subsystem Vendor ID and 348 * Subsystem (Device) ID registers, which are the opposite way 349 * round according to the PCI standard. For good measure, we 350 * save/restore both anyway. 351 */ 352 handle = bgep->cfg_handle; 353 354 /* 355 * For some chipsets (e.g., BCM5718), if MHCR_ENABLE_ENDIAN_BYTE_SWAP 356 * has been set in PCI_CONF_COMM already, we need to write the 357 * byte-swapped value to it. So we just write zero first for simplicity. 358 */ 359 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 360 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 361 pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0); 362 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 363 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 364 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 365 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 366 367 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 368 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 369 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 370 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 371 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 372 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 373 374 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 375 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 376 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 377 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 378 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 379 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 380 cidp->vendor, cidp->device, cidp->revision)); 381 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 382 cidp->subven, cidp->subdev, cidp->asic_rev)); 383 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 384 cidp->clsize, cidp->latency, cidp->command)); 385 386 /* 387 * Step 2 (also step 6): disable and clear interrupts. 388 * Steps 11-13: configure PIO endianness options, and enable 389 * indirect register access. We'll also select any other 390 * options controlled by the MHCR (e.g. tagged status, mask 391 * interrupt mode) at this stage ... 392 * 393 * Note: internally, the chip is 64-bit and BIG-endian, but 394 * since it talks to the host over a (LITTLE-endian) PCI bus, 395 * it normally swaps bytes around at the PCI interface. 396 * However, the PCI host bridge on SPARC systems normally 397 * swaps the byte lanes around too, since SPARCs are also 398 * BIG-endian. So it turns out that on SPARC, the right 399 * option is to tell the chip to swap (and the host bridge 400 * will swap back again), whereas on x86 we ask the chip 401 * NOT to swap, so the natural little-endianness of the 402 * PCI bus is assumed. Then the only thing that doesn't 403 * automatically work right is access to an 8-byte register 404 * by a little-endian host; but we don't want to set the 405 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 406 * accesses don't go where expected ;-( So we live with 407 * that, and perform word-swaps in software in the few cases 408 * where a chip register is defined as an 8-byte value -- 409 * see the code below for details ... 410 * 411 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 412 * very clear in the register description in the PRM, but 413 * Broadcom document 570X-PG104-R page 248 explains a little 414 * more (under "Broadcom Mask Mode"). The bit changes the way 415 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 416 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 417 * way as the 5700 did, which isn't very convenient. Setting 418 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 419 * bit do just what its name says -- MASK the PCI #INTA output 420 * (i.e. deassert the signal at the pin) leaving all internal 421 * state unchanged. This is much more convenient for our 422 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 423 * 424 * Note: the inconvenient semantics of the interrupt mailbox 425 * (nonzero disables and acknowledges/clears the interrupt, 426 * zero enables AND CLEARS it) would make race conditions 427 * likely in the interrupt handler: 428 * 429 * (1) acknowledge & disable interrupts 430 * (2) while (more to do) 431 * process packets 432 * (3) enable interrupts -- also clears pending 433 * 434 * If the chip received more packets and internally generated 435 * an interrupt between the check at (2) and the mbox write 436 * at (3), this interrupt would be lost :-( 437 * 438 * The best way to avoid this is to use TAGGED STATUS mode, 439 * where the chip includes a unique tag in each status block 440 * update, and the host, when re-enabling interrupts, passes 441 * the last tag it saw back to the chip; then the chip can 442 * see whether the host is truly up to date, and regenerate 443 * its interrupt if not. 444 */ 445 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 446 MHCR_ENABLE_TAGGED_STATUS_MODE | 447 MHCR_MASK_INTERRUPT_MODE | 448 MHCR_CLEAR_INTERRUPT_INTA; 449 450 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 451 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 452 453 #ifdef _BIG_ENDIAN 454 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 455 #endif /* _BIG_ENDIAN */ 456 457 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 458 pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0); 459 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 460 461 #ifdef BGE_IPMI_ASF 462 bgep->asf_wordswapped = B_FALSE; 463 #endif 464 /* 465 * Step 1 (also step 7): Enable PCI Memory Space accesses 466 * Disable Memory Write/Invalidate 467 * Enable or disable Bus Mastering 468 * 469 * Note that all other bits are taken from the original value saved 470 * the first time through here, rather than from the current register 471 * value, 'cos that will have been cleared by a soft RESET since. 472 * In this way we preserve the OBP/nexus-parent's preferred settings 473 * of the parity-error and system-error enable bits across multiple 474 * chip RESETs. 475 */ 476 command = bgep->chipid.command | PCI_COMM_MAE; 477 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 478 if (enable_dma) 479 command |= PCI_COMM_ME; 480 /* 481 * on BCM5714 revision A0, false parity error gets generated 482 * due to a logic bug. Provide a workaround by disabling parity 483 * error. 484 */ 485 if (((cidp->device == DEVICE_ID_5714C) || 486 (cidp->device == DEVICE_ID_5714S)) && 487 (cidp->revision == REVISION_ID_5714_A0)) { 488 command &= ~PCI_COMM_PARITY_DETECT; 489 } 490 pci_config_put16(handle, PCI_CONF_COMM, command); 491 492 /* 493 * On some PCI-E device, there were instances when 494 * the device was still link training. 495 */ 496 if (bgep->chipid.pci_type == BGE_PCI_E) { 497 i = 0; 498 value16 = pci_config_get16(handle, PCI_CONF_COMM); 499 while ((value16 != command) && (i < 100)) { 500 drv_usecwait(200); 501 value16 = pci_config_get16(handle, PCI_CONF_COMM); 502 ++i; 503 } 504 } 505 506 /* 507 * Clear any remaining error status bits 508 */ 509 pci_config_put16(handle, PCI_CONF_STAT, ~0); 510 511 /* 512 * Do following if and only if the device is NOT BCM5714C OR 513 * BCM5715C 514 */ 515 if (!((cidp->device == DEVICE_ID_5714C) || 516 (cidp->device == DEVICE_ID_5715C))) { 517 /* 518 * Make sure these indirect-access registers are sane 519 * rather than random after power-up or reset 520 */ 521 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 522 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 523 } 524 /* 525 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 526 */ 527 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 528 529 if (cidp->pci_type == BGE_PCI_E) { 530 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 531 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723, 532 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 533 } else 534 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 535 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 536 } 537 } 538 539 #ifdef __amd64 540 /* 541 * Distinguish CPU types 542 * 543 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 544 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 545 * for PCI-Express based network interface card. This is the work-around 546 * for those nics. 547 */ 548 static boolean_t bge_get_em64t_type(void); 549 #pragma inline(bge_get_em64t_type) 550 551 static boolean_t 552 bge_get_em64t_type(void) 553 { 554 555 return (x86_vendor == X86_VENDOR_Intel); 556 } 557 #endif 558 559 /* 560 * Operating register get/set access routines 561 */ 562 563 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 564 #pragma inline(bge_reg_get32) 565 566 uint32_t 567 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 568 { 569 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 570 (void *)bgep, regno)); 571 572 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 573 } 574 575 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 576 #pragma inline(bge_reg_put32) 577 578 void 579 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 580 { 581 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 582 (void *)bgep, regno, data)); 583 584 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 585 BGE_PCICHK(bgep); 586 } 587 588 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 589 #pragma inline(bge_reg_set32) 590 591 void 592 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 593 { 594 uint32_t regval; 595 596 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 597 (void *)bgep, regno, bits)); 598 599 regval = bge_reg_get32(bgep, regno); 600 regval |= bits; 601 bge_reg_put32(bgep, regno, regval); 602 } 603 604 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 605 #pragma inline(bge_reg_clr32) 606 607 void 608 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 609 { 610 uint32_t regval; 611 612 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 613 (void *)bgep, regno, bits)); 614 615 regval = bge_reg_get32(bgep, regno); 616 regval &= ~bits; 617 bge_reg_put32(bgep, regno, regval); 618 } 619 620 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 621 #pragma inline(bge_reg_get64) 622 623 static uint64_t 624 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 625 { 626 uint64_t regval; 627 628 #ifdef __amd64 629 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() || 630 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 631 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 632 regval <<= 32; 633 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 634 } else { 635 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 636 } 637 #elif defined(__sparc) 638 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 639 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 640 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 641 regval <<= 32; 642 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 643 } else { 644 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 645 } 646 #else 647 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 648 #endif 649 650 #ifdef _LITTLE_ENDIAN 651 regval = (regval >> 32) | (regval << 32); 652 #endif /* _LITTLE_ENDIAN */ 653 654 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 655 (void *)bgep, regno, regval)); 656 657 return (regval); 658 } 659 660 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 661 #pragma inline(bge_reg_put64) 662 663 static void 664 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 665 { 666 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 667 (void *)bgep, regno, data)); 668 669 #ifdef _LITTLE_ENDIAN 670 data = ((data >> 32) | (data << 32)); 671 #endif /* _LITTLE_ENDIAN */ 672 673 #ifdef __amd64 674 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() || 675 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 676 ddi_put32(bgep->io_handle, 677 PIO_ADDR(bgep, regno), (uint32_t)data); 678 BGE_PCICHK(bgep); 679 ddi_put32(bgep->io_handle, 680 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 681 682 } else { 683 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 684 } 685 #elif defined(__sparc) 686 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 687 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 688 ddi_put32(bgep->io_handle, 689 PIO_ADDR(bgep, regno + 4), (uint32_t)data); 690 BGE_PCICHK(bgep); 691 ddi_put32(bgep->io_handle, 692 PIO_ADDR(bgep, regno), (uint32_t)(data >> 32)); 693 } else { 694 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 695 } 696 #else 697 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 698 #endif 699 700 BGE_PCICHK(bgep); 701 } 702 703 /* 704 * The DDI doesn't provide get/put functions for 128 bit data 705 * so we put RCBs out as two 64-bit chunks instead. 706 */ 707 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 708 #pragma inline(bge_reg_putrcb) 709 710 static void 711 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 712 { 713 uint64_t *p; 714 715 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 716 (void *)bgep, addr, rcbp->host_ring_addr, 717 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 718 719 ASSERT((addr % sizeof (*rcbp)) == 0); 720 721 p = (void *)rcbp; 722 bge_reg_put64(bgep, addr, *p++); 723 bge_reg_put64(bgep, addr+8, *p); 724 } 725 726 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 727 #pragma inline(bge_mbx_put) 728 729 void 730 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 731 { 732 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 733 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 734 735 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 736 (void *)bgep, regno, data)); 737 738 /* 739 * Mailbox registers are nominally 64 bits on the 5701, but 740 * the MSW isn't used. On the 5703, they're only 32 bits 741 * anyway. So here we just write the lower(!) 32 bits - 742 * remembering that the chip is big-endian, even though the 743 * PCI bus is little-endian ... 744 */ 745 #ifdef _BIG_ENDIAN 746 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 747 #else 748 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 749 #endif /* _BIG_ENDIAN */ 750 BGE_PCICHK(bgep); 751 } 752 753 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 754 #pragma inline(bge_mbx_get) 755 756 uint32_t 757 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 758 { 759 uint32_t val32; 760 761 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 762 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 763 764 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 765 (void *)bgep, regno)); 766 767 #ifdef _BIG_ENDIAN 768 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 769 #else 770 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 771 #endif /* _BIG_ENDIAN */ 772 BGE_PCICHK(bgep); 773 774 BGE_DEBUG(("bge_mbx_get($%p, 0x%lx) => 0x%08x", 775 (void *)bgep, regno, val32)); 776 777 return (val32); 778 } 779 780 781 #if BGE_DEBUGGING 782 783 void bge_led_mark(bge_t *bgep); 784 #pragma no_inline(bge_led_mark) 785 786 void 787 bge_led_mark(bge_t *bgep) 788 { 789 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 790 LED_CONTROL_1000MBPS_LED | 791 LED_CONTROL_100MBPS_LED | 792 LED_CONTROL_10MBPS_LED; 793 794 /* 795 * Blink all three LINK LEDs on simultaneously, then all off, 796 * then restore to automatic hardware control. This is used 797 * in laboratory testing to trigger a logic analyser or scope. 798 */ 799 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 800 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 801 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 802 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 803 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 804 } 805 806 #endif /* BGE_DEBUGGING */ 807 808 /* 809 * NIC on-chip memory access routines 810 * 811 * Only 32K of NIC memory is visible at a time, controlled by the 812 * Memory Window Base Address Register (in PCI config space). Once 813 * this is set, the 32K region of NIC-local memory that it refers 814 * to can be directly addressed in the upper 32K of the 64K of PCI 815 * memory space used for the device. 816 */ 817 818 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 819 #pragma inline(bge_nic_setwin) 820 821 static void 822 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 823 { 824 chip_id_t *cidp; 825 826 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 827 (void *)bgep, base)); 828 829 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 830 831 /* 832 * Don't do repeated zero data writes, 833 * if the device is BCM5714C/15C. 834 */ 835 cidp = &bgep->chipid; 836 if ((cidp->device == DEVICE_ID_5714C) || 837 (cidp->device == DEVICE_ID_5715C)) { 838 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 839 return; 840 /* Adjust lastWriteZeroData */ 841 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 842 B_TRUE : B_FALSE); 843 } 844 #ifdef __sparc 845 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 846 base = LE_32(base); 847 #endif 848 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 849 } 850 851 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 852 #pragma inline(bge_nic_get32) 853 854 static uint32_t 855 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 856 { 857 uint32_t data; 858 859 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 860 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 861 /* workaround for word swap error */ 862 if (addr & 4) 863 addr = addr - 4; 864 else 865 addr = addr + 4; 866 } 867 #endif 868 869 #ifdef __sparc 870 data = bge_nic_read32(bgep, addr); 871 #else 872 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 873 addr &= MWBAR_GRANULE_MASK; 874 addr += NIC_MEM_WINDOW_OFFSET; 875 876 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 877 #endif 878 879 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 880 (void *)bgep, addr, data)); 881 882 return (data); 883 } 884 885 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 886 #pragma inline(bge_nic_put32) 887 888 void 889 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 890 { 891 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 892 (void *)bgep, addr, data)); 893 894 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 895 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 896 /* workaround for word swap error */ 897 if (addr & 4) 898 addr = addr - 4; 899 else 900 addr = addr + 4; 901 } 902 #endif 903 904 #ifdef __sparc 905 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 906 addr = LE_32(addr); 907 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 908 data = LE_32(data); 909 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 910 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 911 #else 912 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 913 addr &= MWBAR_GRANULE_MASK; 914 addr += NIC_MEM_WINDOW_OFFSET; 915 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 916 BGE_PCICHK(bgep); 917 #endif 918 } 919 920 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 921 #pragma inline(bge_nic_get64) 922 923 static uint64_t 924 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 925 { 926 uint64_t data; 927 928 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 929 addr &= MWBAR_GRANULE_MASK; 930 addr += NIC_MEM_WINDOW_OFFSET; 931 932 #ifdef __amd64 933 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() || 934 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 935 data = ddi_get32(bgep->io_handle, 936 PIO_ADDR(bgep, addr + 4)); 937 data <<= 32; 938 data |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 939 } else { 940 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 941 } 942 #elif defined(__sparc) 943 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 944 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 945 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 946 data <<= 32; 947 data |= ddi_get32(bgep->io_handle, 948 PIO_ADDR(bgep, addr + 4)); 949 } else { 950 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 951 } 952 #else 953 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 954 #endif 955 956 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 957 (void *)bgep, addr, data)); 958 959 return (data); 960 } 961 962 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 963 #pragma inline(bge_nic_put64) 964 965 static void 966 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 967 { 968 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 969 (void *)bgep, addr, data)); 970 971 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 972 addr &= MWBAR_GRANULE_MASK; 973 addr += NIC_MEM_WINDOW_OFFSET; 974 975 #ifdef __amd64 976 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() || 977 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 978 ddi_put32(bgep->io_handle, 979 PIO_ADDR(bgep, addr + 4), (uint32_t)data); 980 BGE_PCICHK(bgep); 981 ddi_put32(bgep->io_handle, 982 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32)); 983 } else { 984 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 985 } 986 #elif defined(__sparc) 987 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 988 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 989 ddi_put32(bgep->io_handle, 990 PIO_ADDR(bgep, addr + 4), (uint32_t)data); 991 BGE_PCICHK(bgep); 992 ddi_put32(bgep->io_handle, 993 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32)); 994 } else { 995 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 996 } 997 #else 998 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 999 #endif 1000 1001 BGE_PCICHK(bgep); 1002 } 1003 1004 /* 1005 * The DDI doesn't provide get/put functions for 128 bit data 1006 * so we put RCBs out as two 64-bit chunks instead. 1007 */ 1008 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 1009 #pragma inline(bge_nic_putrcb) 1010 1011 static void 1012 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 1013 { 1014 uint64_t *p; 1015 1016 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 1017 (void *)bgep, addr, rcbp->host_ring_addr, 1018 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 1019 1020 ASSERT((addr % sizeof (*rcbp)) == 0); 1021 1022 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1023 addr &= MWBAR_GRANULE_MASK; 1024 addr += NIC_MEM_WINDOW_OFFSET; 1025 1026 p = (void *)rcbp; 1027 #ifdef __amd64 1028 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() || 1029 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 1030 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1031 (uint32_t)(*p)); 1032 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1033 (uint32_t)(*p++ >> 32)); 1034 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1035 (uint32_t)(*p)); 1036 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1037 (uint32_t)(*p >> 32)); 1038 1039 } else { 1040 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1041 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1042 } 1043 #elif defined(__sparc) 1044 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 1045 DEVICE_5717_SERIES_CHIPSETS(bgep)) { 1046 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1047 (uint32_t)(*p)); 1048 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1049 (uint32_t)(*p++ >> 32)); 1050 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1051 (uint32_t)(*p)); 1052 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1053 (uint32_t)(*p >> 32)); 1054 } else { 1055 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1056 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1057 } 1058 #else 1059 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1060 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1061 #endif 1062 1063 BGE_PCICHK(bgep); 1064 } 1065 1066 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1067 #pragma inline(bge_nic_zero) 1068 1069 static void 1070 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1071 { 1072 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1073 (void *)bgep, addr, nbytes)); 1074 1075 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1076 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1077 1078 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1079 addr &= MWBAR_GRANULE_MASK; 1080 addr += NIC_MEM_WINDOW_OFFSET; 1081 1082 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1083 nbytes, 1, DDI_DATA_SZ08_ACC); 1084 BGE_PCICHK(bgep); 1085 } 1086 1087 /* 1088 * MII (PHY) register get/set access routines 1089 * 1090 * These use the chip's MII auto-access method, controlled by the 1091 * MII Communication register at 0x044c, so the CPU doesn't have 1092 * to fiddle with the individual bits. 1093 */ 1094 1095 #undef BGE_DBG 1096 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1097 1098 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1099 uint16_t data, uint32_t cmd); 1100 #pragma no_inline(bge_mii_access) 1101 1102 static uint16_t 1103 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1104 { 1105 uint32_t timeout; 1106 uint32_t regval1; 1107 uint32_t regval2; 1108 1109 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1110 (void *)bgep, regno, data, cmd)); 1111 1112 ASSERT(mutex_owned(bgep->genlock)); 1113 1114 /* 1115 * Assemble the command ... 1116 */ 1117 cmd |= data << MI_COMMS_DATA_SHIFT; 1118 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1119 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1120 cmd |= MI_COMMS_START; 1121 1122 /* 1123 * Wait for any command already in progress ... 1124 * 1125 * Note: this *shouldn't* ever find that there is a command 1126 * in progress, because we already hold the <genlock> mutex. 1127 * Nonetheless, we have sometimes seen the MI_COMMS_START 1128 * bit set here -- it seems that the chip can initiate MII 1129 * accesses internally, even with polling OFF. 1130 */ 1131 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1132 for (timeout = 100; ; ) { 1133 if ((regval2 & MI_COMMS_START) == 0) { 1134 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1135 break; 1136 } 1137 if (--timeout == 0) 1138 break; 1139 drv_usecwait(10); 1140 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1141 } 1142 1143 if (timeout == 0) 1144 return ((uint16_t)~0u); 1145 1146 if (timeout != 100) 1147 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1148 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1149 cmd, 10*(100-timeout), regval1, regval2)); 1150 1151 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1152 for (timeout = 1000; ; ) { 1153 if ((regval1 & MI_COMMS_START) == 0) 1154 break; 1155 if (--timeout == 0) 1156 break; 1157 drv_usecwait(10); 1158 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1159 } 1160 1161 /* 1162 * Drop out early if the READ FAILED bit is set -- this chip 1163 * could be a 5703/4S, with a SerDes instead of a PHY! 1164 */ 1165 if (regval2 & MI_COMMS_READ_FAILED) 1166 return ((uint16_t)~0u); 1167 1168 if (timeout == 0) 1169 return ((uint16_t)~0u); 1170 1171 /* 1172 * The PRM says to wait 5us after seeing the START bit clear 1173 * and then re-read the register to get the final value of the 1174 * data field, in order to avoid a race condition where the 1175 * START bit is clear but the data field isn't yet valid. 1176 * 1177 * Note: we don't actually seem to be encounter this race; 1178 * except when the START bit is seen set again (see below), 1179 * the data field doesn't change during this 5us interval. 1180 */ 1181 drv_usecwait(5); 1182 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1183 1184 /* 1185 * Unfortunately, when following the PRMs instructions above, 1186 * we have occasionally seen the START bit set again(!) in the 1187 * value read after the 5us delay. This seems to be due to the 1188 * chip autonomously starting another MII access internally. 1189 * In such cases, the command/data/etc fields relate to the 1190 * internal command, rather than the one that we thought had 1191 * just finished. So in this case, we fall back to returning 1192 * the data from the original read that showed START clear. 1193 */ 1194 if (regval2 & MI_COMMS_START) { 1195 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1196 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1197 cmd, regval1, regval2)); 1198 regval2 = regval1; 1199 } 1200 1201 if (regval2 & MI_COMMS_START) 1202 return ((uint16_t)~0u); 1203 1204 if (regval2 & MI_COMMS_READ_FAILED) 1205 return ((uint16_t)~0u); 1206 1207 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1208 } 1209 1210 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1211 #pragma no_inline(bge_mii_get16) 1212 1213 uint16_t 1214 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1215 { 1216 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1217 (void *)bgep, regno)); 1218 1219 ASSERT(mutex_owned(bgep->genlock)); 1220 1221 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1222 (regno == MII_MSCONTROL))) 1223 return (0); 1224 1225 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1226 } 1227 1228 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1229 #pragma no_inline(bge_mii_put16) 1230 1231 void 1232 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1233 { 1234 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1235 (void *)bgep, regno, data)); 1236 1237 ASSERT(mutex_owned(bgep->genlock)); 1238 1239 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1240 (regno == MII_MSCONTROL))) 1241 return; 1242 1243 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1244 } 1245 1246 #undef BGE_DBG 1247 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1248 1249 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1250 1251 /* 1252 * Basic SEEPROM get/set access routine 1253 * 1254 * This uses the chip's SEEPROM auto-access method, controlled by the 1255 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1256 * doesn't have to fiddle with the individual bits. 1257 * 1258 * The caller should hold <genlock> and *also* have already acquired 1259 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1260 * 1261 * Return value: 1262 * 0 on success, 1263 * ENODATA on access timeout (maybe retryable: device may just be busy) 1264 * EPROTO on other h/w or s/w errors. 1265 * 1266 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1267 * from a (successful) SEEPROM_ACCESS_READ. 1268 */ 1269 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1270 uint32_t *dp); 1271 #pragma no_inline(bge_seeprom_access) 1272 1273 static int 1274 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1275 { 1276 uint32_t tries; 1277 uint32_t regval; 1278 1279 ASSERT(mutex_owned(bgep->genlock)); 1280 1281 /* 1282 * On the newer chips that support both SEEPROM & Flash, we need 1283 * to specifically enable SEEPROM access (Flash is the default). 1284 * On older chips, we don't; SEEPROM is the only NVtype supported, 1285 * and the NVM control registers don't exist ... 1286 */ 1287 switch (bgep->chipid.nvtype) { 1288 case BGE_NVTYPE_NONE: 1289 case BGE_NVTYPE_UNKNOWN: 1290 _NOTE(NOTREACHED) 1291 case BGE_NVTYPE_SEEPROM: 1292 break; 1293 1294 case BGE_NVTYPE_LEGACY_SEEPROM: 1295 case BGE_NVTYPE_UNBUFFERED_FLASH: 1296 case BGE_NVTYPE_BUFFERED_FLASH: 1297 default: 1298 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1299 NVM_CFG1_LEGACY_SEEPROM_MODE); 1300 break; 1301 } 1302 1303 /* 1304 * Check there's no command in progress. 1305 * 1306 * Note: this *shouldn't* ever find that there is a command 1307 * in progress, because we already hold the <genlock> mutex. 1308 * Also, to ensure we don't have a conflict with the chip's 1309 * internal firmware or a process accessing the same (shared) 1310 * SEEPROM through the other port of a 5704, we've already 1311 * been through the "software arbitration" protocol. 1312 * So this is just a final consistency check: we shouldn't 1313 * see EITHER the START bit (command started but not complete) 1314 * OR the COMPLETE bit (command completed but not cleared). 1315 */ 1316 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1317 if (regval & SEEPROM_ACCESS_START) 1318 return (EPROTO); 1319 if (regval & SEEPROM_ACCESS_COMPLETE) 1320 return (EPROTO); 1321 1322 /* 1323 * Assemble the command ... 1324 */ 1325 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1326 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1327 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1328 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1329 cmd |= SEEPROM_ACCESS_START; 1330 cmd |= SEEPROM_ACCESS_COMPLETE; 1331 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1332 1333 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1334 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1335 1336 /* 1337 * By observation, a successful access takes ~20us on a 5703/4, 1338 * but apparently much longer (up to 1000us) on the obsolescent 1339 * BCM5700/BCM5701. We want to be sure we don't get any false 1340 * timeouts here; but OTOH, we don't want a bogus access to lock 1341 * out interrupts for longer than necessary. So we'll allow up 1342 * to 1000us ... 1343 */ 1344 for (tries = 0; tries < 1000; ++tries) { 1345 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1346 if (regval & SEEPROM_ACCESS_COMPLETE) 1347 break; 1348 drv_usecwait(1); 1349 } 1350 1351 if (regval & SEEPROM_ACCESS_COMPLETE) { 1352 /* 1353 * All OK; read the SEEPROM data register, then write back 1354 * the value read from the address register in order to 1355 * clear the <complete> bit and leave the SEEPROM access 1356 * state machine idle, ready for the next access ... 1357 */ 1358 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1359 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1360 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1361 return (0); 1362 } 1363 1364 /* 1365 * Hmm ... what happened here? 1366 * 1367 * Most likely, the user addressed a non-existent SEEPROM. Or 1368 * maybe the SEEPROM was busy internally (e.g. processing a write) 1369 * and didn't respond to being addressed. Either way, it's left 1370 * the SEEPROM access state machine wedged. So we'll reset it 1371 * before we leave, so it's ready for next time ... 1372 */ 1373 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1374 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1375 return (ENODATA); 1376 } 1377 1378 /* 1379 * Basic Flash get/set access routine 1380 * 1381 * These use the chip's Flash auto-access method, controlled by the 1382 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1383 * fiddle with the individual bits. 1384 * 1385 * The caller should hold <genlock> and *also* have already acquired 1386 * the right to access the Flash, via bge_nvmem_acquire() above. 1387 * 1388 * Return value: 1389 * 0 on success, 1390 * ENODATA on access timeout (maybe retryable: device may just be busy) 1391 * ENODEV if the NVmem device is missing or otherwise unusable 1392 * 1393 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1394 * from a (successful) NVM_FLASH_CMD_RD. 1395 */ 1396 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1397 uint32_t *dp); 1398 #pragma no_inline(bge_flash_access) 1399 1400 static int 1401 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1402 { 1403 uint32_t tries; 1404 uint32_t regval; 1405 1406 ASSERT(mutex_owned(bgep->genlock)); 1407 1408 /* 1409 * On the newer chips that support both SEEPROM & Flash, we need 1410 * to specifically disable SEEPROM access while accessing Flash. 1411 * The older chips don't support Flash, and the NVM registers don't 1412 * exist, so we shouldn't be here at all! 1413 */ 1414 switch (bgep->chipid.nvtype) { 1415 case BGE_NVTYPE_NONE: 1416 case BGE_NVTYPE_UNKNOWN: 1417 _NOTE(NOTREACHED) 1418 case BGE_NVTYPE_SEEPROM: 1419 return (ENODEV); 1420 1421 case BGE_NVTYPE_LEGACY_SEEPROM: 1422 case BGE_NVTYPE_UNBUFFERED_FLASH: 1423 case BGE_NVTYPE_BUFFERED_FLASH: 1424 default: 1425 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1426 NVM_CFG1_LEGACY_SEEPROM_MODE); 1427 break; 1428 } 1429 1430 /* 1431 * Assemble the command ... 1432 */ 1433 addr &= NVM_FLASH_ADDR_MASK; 1434 cmd |= NVM_FLASH_CMD_DOIT; 1435 cmd |= NVM_FLASH_CMD_FIRST; 1436 cmd |= NVM_FLASH_CMD_LAST; 1437 cmd |= NVM_FLASH_CMD_DONE; 1438 1439 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1440 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1441 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1442 1443 /* 1444 * Allow up to 1000ms ... 1445 */ 1446 for (tries = 0; tries < 1000; ++tries) { 1447 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1448 if (regval & NVM_FLASH_CMD_DONE) 1449 break; 1450 drv_usecwait(1); 1451 } 1452 1453 if (regval & NVM_FLASH_CMD_DONE) { 1454 /* 1455 * All OK; read the data from the Flash read register 1456 */ 1457 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1458 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1459 return (0); 1460 } 1461 1462 /* 1463 * Hmm ... what happened here? 1464 * 1465 * Most likely, the user addressed a non-existent Flash. Or 1466 * maybe the Flash was busy internally (e.g. processing a write) 1467 * and didn't respond to being addressed. Either way, there's 1468 * nothing we can here ... 1469 */ 1470 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1471 return (ENODATA); 1472 } 1473 1474 /* 1475 * The next two functions regulate access to the NVram (if fitted). 1476 * 1477 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1478 * (SPI) interface, but they can be accessed through either port. These 1479 * are managed by different instance of this driver and have no software 1480 * state in common. 1481 * 1482 * In addition (and even on a single core chip) the chip's internal 1483 * firmware can access the SEEPROM/Flash, most notably after a RESET 1484 * when it may download code to run internally. 1485 * 1486 * So we need to arbitrate between these various software agents. For 1487 * this purpose, the chip provides the Software Arbitration Register, 1488 * which implements hardware(!) arbitration. 1489 * 1490 * This functionality didn't exist on older (5700/5701) chips, so there's 1491 * nothing we can do by way of arbitration on those; also, if there's no 1492 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1493 * nothing to do. 1494 * 1495 * The internal firmware appears to use Request 0, which is the highest 1496 * priority. So we'd like to use Request 2, leaving one higher and one 1497 * lower for any future developments ... but apparently this doesn't 1498 * always work. So for now, the code uses Request 1 ;-( 1499 */ 1500 1501 #define NVM_READ_REQ NVM_READ_REQ1 1502 #define NVM_RESET_REQ NVM_RESET_REQ1 1503 #define NVM_SET_REQ NVM_SET_REQ1 1504 1505 static void bge_nvmem_relinquish(bge_t *bgep); 1506 #pragma no_inline(bge_nvmem_relinquish) 1507 1508 static void 1509 bge_nvmem_relinquish(bge_t *bgep) 1510 { 1511 ASSERT(mutex_owned(bgep->genlock)); 1512 1513 switch (bgep->chipid.nvtype) { 1514 case BGE_NVTYPE_NONE: 1515 case BGE_NVTYPE_UNKNOWN: 1516 _NOTE(NOTREACHED) 1517 return; 1518 1519 case BGE_NVTYPE_SEEPROM: 1520 /* 1521 * No arbitration performed, no release needed 1522 */ 1523 return; 1524 1525 case BGE_NVTYPE_LEGACY_SEEPROM: 1526 case BGE_NVTYPE_UNBUFFERED_FLASH: 1527 case BGE_NVTYPE_BUFFERED_FLASH: 1528 default: 1529 break; 1530 } 1531 1532 /* 1533 * Our own request should be present (whether or not granted) ... 1534 */ 1535 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1536 1537 /* 1538 * ... this will make it go away. 1539 */ 1540 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1541 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1542 } 1543 1544 /* 1545 * Arbitrate for access to the NVmem, if necessary 1546 * 1547 * Return value: 1548 * 0 on success 1549 * EAGAIN if the device is in use (retryable) 1550 * ENODEV if the NVmem device is missing or otherwise unusable 1551 */ 1552 static int bge_nvmem_acquire(bge_t *bgep); 1553 #pragma no_inline(bge_nvmem_acquire) 1554 1555 static int 1556 bge_nvmem_acquire(bge_t *bgep) 1557 { 1558 uint32_t regval; 1559 uint32_t tries; 1560 1561 ASSERT(mutex_owned(bgep->genlock)); 1562 1563 switch (bgep->chipid.nvtype) { 1564 case BGE_NVTYPE_NONE: 1565 case BGE_NVTYPE_UNKNOWN: 1566 /* 1567 * Access denied: no (recognisable) device fitted 1568 */ 1569 return (ENODEV); 1570 1571 case BGE_NVTYPE_SEEPROM: 1572 /* 1573 * Access granted: no arbitration needed (or possible) 1574 */ 1575 return (0); 1576 1577 case BGE_NVTYPE_LEGACY_SEEPROM: 1578 case BGE_NVTYPE_UNBUFFERED_FLASH: 1579 case BGE_NVTYPE_BUFFERED_FLASH: 1580 default: 1581 /* 1582 * Access conditional: conduct arbitration protocol 1583 */ 1584 break; 1585 } 1586 1587 /* 1588 * We're holding the per-port mutex <genlock>, so no-one other 1589 * thread can be attempting to access the NVmem through *this* 1590 * port. But it could be in use by the *other* port (of a 5704), 1591 * or by the chip's internal firmware, so we have to go through 1592 * the full (hardware) arbitration protocol ... 1593 * 1594 * Note that *because* we're holding <genlock>, the interrupt handler 1595 * won't be able to progress. So we're only willing to spin for a 1596 * fairly short time. Specifically: 1597 * 1598 * We *must* wait long enough for the hardware to resolve all 1599 * requests and determine the winner. Fortunately, this is 1600 * "almost instantaneous", even as observed by GHz CPUs. 1601 * 1602 * A successful access by another Solaris thread (via either 1603 * port) typically takes ~20us. So waiting a bit longer than 1604 * that will give a good chance of success, if the other user 1605 * *is* another thread on the other port. 1606 * 1607 * However, the internal firmware can hold on to the NVmem 1608 * for *much* longer: at least 10 milliseconds just after a 1609 * RESET, and maybe even longer if the NVmem actually contains 1610 * code to download and run on the internal CPUs. 1611 * 1612 * So, we'll allow 50us; if that's not enough then it's up to the 1613 * caller to retry later (hence the choice of return code EAGAIN). 1614 */ 1615 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1616 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1617 1618 for (tries = 0; tries < 50; ++tries) { 1619 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1620 if (regval & NVM_WON_REQ1) 1621 break; 1622 drv_usecwait(1); 1623 } 1624 1625 if (regval & NVM_WON_REQ1) { 1626 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1627 return (0); 1628 } 1629 1630 /* 1631 * Somebody else must be accessing the NVmem, so abandon our 1632 * attempt take control of it. The caller can try again later ... 1633 */ 1634 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1635 bge_nvmem_relinquish(bgep); 1636 return (EAGAIN); 1637 } 1638 1639 /* 1640 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1641 * write protect line in such a way that the NVmem is protected when 1642 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1643 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1644 * 1645 * Note: there's only one set of GPIO pins on a 5704, even though they 1646 * can be accessed through either port. So the chip has to resolve what 1647 * happens if the two ports program a single pin differently ... the rule 1648 * it uses is that if the ports disagree about the *direction* of a pin, 1649 * "output" wins over "input", but if they disagree about its *value* as 1650 * an output, then the pin is TRISTATED instead! In such a case, no-one 1651 * wins, and the external signal does whatever the external circuitry 1652 * defines as the default -- which we've assumed is the PROTECTED state. 1653 * So, we always change GPIO1 back to being an *input* whenever we're not 1654 * specifically using it to unprotect the NVmem. This allows either port 1655 * to update the NVmem, although obviously only one at a time! 1656 * 1657 * The caller should hold <genlock> and *also* have already acquired the 1658 * right to access the NVmem, via bge_nvmem_acquire() above. 1659 */ 1660 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1661 #pragma inline(bge_nvmem_protect) 1662 1663 static void 1664 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1665 { 1666 uint32_t regval; 1667 1668 ASSERT(mutex_owned(bgep->genlock)); 1669 1670 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1671 if (protect) { 1672 regval |= MLCR_MISC_PINS_OUTPUT_1; 1673 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1674 } else { 1675 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1676 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1677 } 1678 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1679 } 1680 1681 /* 1682 * Now put it all together ... 1683 * 1684 * Try to acquire control of the NVmem; if successful, then: 1685 * unprotect it (if we want to write to it) 1686 * perform the requested access 1687 * reprotect it (after a write) 1688 * relinquish control 1689 * 1690 * Return value: 1691 * 0 on success, 1692 * EAGAIN if the device is in use (retryable) 1693 * ENODATA on access timeout (maybe retryable: device may just be busy) 1694 * ENODEV if the NVmem device is missing or otherwise unusable 1695 * EPROTO on other h/w or s/w errors. 1696 */ 1697 static int 1698 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1699 { 1700 int err; 1701 1702 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1703 switch (cmd) { 1704 case BGE_SEE_READ: 1705 err = bge_seeprom_access(bgep, 1706 SEEPROM_ACCESS_READ, addr, dp); 1707 break; 1708 1709 case BGE_SEE_WRITE: 1710 bge_nvmem_protect(bgep, B_FALSE); 1711 err = bge_seeprom_access(bgep, 1712 SEEPROM_ACCESS_WRITE, addr, dp); 1713 bge_nvmem_protect(bgep, B_TRUE); 1714 break; 1715 1716 case BGE_FLASH_READ: 1717 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1718 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1719 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1720 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1721 bge_reg_set32(bgep, NVM_ACCESS_REG, 1722 NVM_ACCESS_ENABLE); 1723 } 1724 err = bge_flash_access(bgep, 1725 NVM_FLASH_CMD_RD, addr, dp); 1726 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1727 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1728 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1729 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1730 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1731 NVM_ACCESS_ENABLE); 1732 } 1733 break; 1734 1735 case BGE_FLASH_WRITE: 1736 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1737 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1738 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1739 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1740 bge_reg_set32(bgep, NVM_ACCESS_REG, 1741 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1742 } 1743 bge_nvmem_protect(bgep, B_FALSE); 1744 err = bge_flash_access(bgep, 1745 NVM_FLASH_CMD_WR, addr, dp); 1746 bge_nvmem_protect(bgep, B_TRUE); 1747 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1748 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1749 DEVICE_5717_SERIES_CHIPSETS(bgep) || 1750 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1751 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1752 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1753 } 1754 1755 break; 1756 1757 default: 1758 _NOTE(NOTREACHED) 1759 break; 1760 } 1761 bge_nvmem_relinquish(bgep); 1762 } 1763 1764 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1765 return (err); 1766 } 1767 1768 /* 1769 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1770 */ 1771 static uint64_t bge_get_nvmac(bge_t *bgep); 1772 #pragma no_inline(bge_get_nvmac) 1773 1774 static uint64_t 1775 bge_get_nvmac(bge_t *bgep) 1776 { 1777 uint32_t mac_high; 1778 uint32_t mac_low; 1779 uint32_t addr; 1780 uint32_t cmd; 1781 uint64_t mac; 1782 1783 BGE_TRACE(("bge_get_nvmac($%p)", 1784 (void *)bgep)); 1785 1786 switch (bgep->chipid.nvtype) { 1787 case BGE_NVTYPE_NONE: 1788 case BGE_NVTYPE_UNKNOWN: 1789 default: 1790 return (0ULL); 1791 1792 case BGE_NVTYPE_SEEPROM: 1793 case BGE_NVTYPE_LEGACY_SEEPROM: 1794 cmd = BGE_SEE_READ; 1795 break; 1796 1797 case BGE_NVTYPE_UNBUFFERED_FLASH: 1798 case BGE_NVTYPE_BUFFERED_FLASH: 1799 cmd = BGE_FLASH_READ; 1800 break; 1801 } 1802 1803 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 1804 addr = NVMEM_DATA_MAC_ADDRESS_5906; 1805 else 1806 addr = NVMEM_DATA_MAC_ADDRESS; 1807 1808 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1809 return (0ULL); 1810 addr += 4; 1811 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1812 return (0ULL); 1813 1814 /* 1815 * The Broadcom chip is natively BIG-endian, so that's how the 1816 * MAC address is represented in NVmem. We may need to swap it 1817 * around on a little-endian host ... 1818 */ 1819 #ifdef _BIG_ENDIAN 1820 mac = mac_high; 1821 mac = mac << 32; 1822 mac |= mac_low; 1823 #else 1824 mac = BGE_BSWAP_32(mac_high); 1825 mac = mac << 32; 1826 mac |= BGE_BSWAP_32(mac_low); 1827 #endif /* _BIG_ENDIAN */ 1828 1829 return (mac); 1830 } 1831 1832 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1833 1834 /* 1835 * Dummy version for when we're not supporting NVmem access 1836 */ 1837 static uint64_t bge_get_nvmac(bge_t *bgep); 1838 #pragma inline(bge_get_nvmac) 1839 1840 static uint64_t 1841 bge_get_nvmac(bge_t *bgep) 1842 { 1843 _NOTE(ARGUNUSED(bgep)) 1844 return (0ULL); 1845 } 1846 1847 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1848 1849 /* 1850 * Determine the type of NVmem that is (or may be) attached to this chip, 1851 */ 1852 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1853 #pragma no_inline(bge_nvmem_id) 1854 1855 static enum bge_nvmem_type 1856 bge_nvmem_id(bge_t *bgep) 1857 { 1858 enum bge_nvmem_type nvtype; 1859 uint32_t config1; 1860 1861 BGE_TRACE(("bge_nvmem_id($%p)", 1862 (void *)bgep)); 1863 1864 switch (bgep->chipid.device) { 1865 default: 1866 /* 1867 * We shouldn't get here; it means we don't recognise 1868 * the chip, which means we don't know how to determine 1869 * what sort of NVmem (if any) it has. So we'll say 1870 * NONE, to disable the NVmem access code ... 1871 */ 1872 nvtype = BGE_NVTYPE_NONE; 1873 break; 1874 1875 case DEVICE_ID_5700: 1876 case DEVICE_ID_5700x: 1877 case DEVICE_ID_5701: 1878 /* 1879 * These devices support *only* SEEPROMs 1880 */ 1881 nvtype = BGE_NVTYPE_SEEPROM; 1882 break; 1883 1884 case DEVICE_ID_5702: 1885 case DEVICE_ID_5702fe: 1886 case DEVICE_ID_5703C: 1887 case DEVICE_ID_5703S: 1888 case DEVICE_ID_5704C: 1889 case DEVICE_ID_5704S: 1890 case DEVICE_ID_5704: 1891 case DEVICE_ID_5705M: 1892 case DEVICE_ID_5705C: 1893 case DEVICE_ID_5705_2: 1894 case DEVICE_ID_5718: 1895 case DEVICE_ID_5780: 1896 case DEVICE_ID_5782: 1897 case DEVICE_ID_5785: 1898 case DEVICE_ID_5787: 1899 case DEVICE_ID_5787M: 1900 case DEVICE_ID_5788: 1901 case DEVICE_ID_5789: 1902 case DEVICE_ID_5751: 1903 case DEVICE_ID_5751M: 1904 case DEVICE_ID_5752: 1905 case DEVICE_ID_5752M: 1906 case DEVICE_ID_5754: 1907 case DEVICE_ID_5755: 1908 case DEVICE_ID_5755M: 1909 case DEVICE_ID_5756M: 1910 case DEVICE_ID_5721: 1911 case DEVICE_ID_5722: 1912 case DEVICE_ID_5723: 1913 case DEVICE_ID_5761: 1914 case DEVICE_ID_5761E: 1915 case DEVICE_ID_5764: 1916 case DEVICE_ID_5714C: 1917 case DEVICE_ID_5714S: 1918 case DEVICE_ID_5715C: 1919 case DEVICE_ID_5715S: 1920 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1921 if (config1 & NVM_CFG1_FLASH_MODE) 1922 if (config1 & NVM_CFG1_BUFFERED_MODE) 1923 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1924 else 1925 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1926 else 1927 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1928 break; 1929 case DEVICE_ID_5906: 1930 case DEVICE_ID_5906M: 1931 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1932 break; 1933 } 1934 1935 return (nvtype); 1936 } 1937 1938 #undef BGE_DBG 1939 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1940 1941 static void 1942 bge_init_recv_rule(bge_t *bgep) 1943 { 1944 bge_recv_rule_t *rulep = bgep->recv_rules; 1945 uint32_t i; 1946 1947 /* 1948 * Initialize receive rule registers. 1949 * Note that rules may persist across each bge_m_start/stop() call. 1950 */ 1951 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1952 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1953 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1954 } 1955 } 1956 1957 /* 1958 * Using the values captured by bge_chip_cfg_init(), and additional probes 1959 * as required, characterise the chip fully: determine the label by which 1960 * to refer to this chip, the correct settings for various registers, and 1961 * of course whether the device and/or subsystem are supported! 1962 */ 1963 int bge_chip_id_init(bge_t *bgep); 1964 #pragma no_inline(bge_chip_id_init) 1965 1966 int 1967 bge_chip_id_init(bge_t *bgep) 1968 { 1969 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1970 boolean_t sys_ok; 1971 boolean_t dev_ok; 1972 chip_id_t *cidp; 1973 uint32_t subid; 1974 char *devname; 1975 char *sysname; 1976 int *ids; 1977 int err; 1978 uint_t i; 1979 1980 sys_ok = dev_ok = B_FALSE; 1981 cidp = &bgep->chipid; 1982 1983 /* 1984 * Check the PCI device ID to determine the generic chip type and 1985 * select parameters that depend on this. 1986 * 1987 * Note: because the SPARC platforms in general don't fit the 1988 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1989 * as zero - which is why we use <asic_rev> rather than <revision> 1990 * below ... 1991 * 1992 * Note: in general we can't distinguish between the Copper/SerDes 1993 * versions by ID alone, as some Copper devices (e.g. some but not 1994 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1995 * treat them the same here, and the MII code works out the media 1996 * type later on ... 1997 */ 1998 cidp->mbuf_base = bge_mbuf_pool_base; 1999 cidp->mbuf_length = bge_mbuf_pool_len; 2000 cidp->recv_slots = BGE_RECV_SLOTS_USED; 2001 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 2002 cidp->pci_type = BGE_PCI_X; 2003 cidp->statistic_type = BGE_STAT_BLK; 2004 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 2005 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 2006 cidp->mbuf_hi_water = bge_mbuf_hi_water; 2007 cidp->rx_ticks_norm = bge_rx_ticks_norm; 2008 cidp->rx_count_norm = bge_rx_count_norm; 2009 cidp->tx_ticks_norm = bge_tx_ticks_norm; 2010 cidp->tx_count_norm = bge_tx_count_norm; 2011 cidp->mask_pci_int = MHCR_MASK_PCI_INT_OUTPUT; 2012 2013 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 2014 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 2015 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 2016 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 2017 2018 cidp->msi_enabled = B_FALSE; 2019 2020 switch (cidp->device) { 2021 case DEVICE_ID_5718: 2022 cidp->chip_label = 5718; 2023 cidp->msi_enabled = bge_enable_msi; 2024 #ifdef __sparc 2025 cidp->mask_pci_int = LE_32(MHCR_MASK_PCI_INT_OUTPUT); 2026 #endif 2027 cidp->bge_dma_rwctrl = LE_32(PDRWCR_VAR_5717); 2028 cidp->pci_type = BGE_PCI_E; 2029 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2030 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5717; 2031 cidp->mbuf_hi_water = MBUF_HIWAT_5717; 2032 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2033 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2034 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2035 cidp->bge_mlcr_default = MLCR_DEFAULT_5717; 2036 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2037 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2038 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2039 cidp->statistic_type = BGE_STAT_REG; 2040 dev_ok = B_TRUE; 2041 break; 2042 2043 case DEVICE_ID_5700: 2044 case DEVICE_ID_5700x: 2045 cidp->chip_label = 5700; 2046 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2047 break; 2048 2049 case DEVICE_ID_5701: 2050 cidp->chip_label = 5701; 2051 dev_ok = B_TRUE; 2052 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2053 break; 2054 2055 case DEVICE_ID_5702: 2056 case DEVICE_ID_5702fe: 2057 cidp->chip_label = 5702; 2058 dev_ok = B_TRUE; 2059 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2060 cidp->pci_type = BGE_PCI; 2061 break; 2062 2063 case DEVICE_ID_5703C: 2064 case DEVICE_ID_5703S: 2065 case DEVICE_ID_5703: 2066 /* 2067 * Revision A0 of the 5703/5793 had various errata 2068 * that we can't or don't work around, so it's not 2069 * supported, but all later versions are 2070 */ 2071 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 2072 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 2073 dev_ok = B_TRUE; 2074 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2075 break; 2076 2077 case DEVICE_ID_5704C: 2078 case DEVICE_ID_5704S: 2079 case DEVICE_ID_5704: 2080 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 2081 cidp->mbuf_base = bge_mbuf_pool_base_5704; 2082 cidp->mbuf_length = bge_mbuf_pool_len_5704; 2083 dev_ok = B_TRUE; 2084 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2085 break; 2086 2087 case DEVICE_ID_5705C: 2088 case DEVICE_ID_5705M: 2089 case DEVICE_ID_5705MA3: 2090 case DEVICE_ID_5705F: 2091 case DEVICE_ID_5705_2: 2092 case DEVICE_ID_5754: 2093 if (cidp->device == DEVICE_ID_5754) { 2094 cidp->chip_label = 5754; 2095 cidp->pci_type = BGE_PCI_E; 2096 } else { 2097 cidp->chip_label = 5705; 2098 cidp->pci_type = BGE_PCI; 2099 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2100 } 2101 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2102 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2103 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2104 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2105 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2106 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2107 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2108 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2109 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2110 cidp->statistic_type = BGE_STAT_REG; 2111 dev_ok = B_TRUE; 2112 break; 2113 2114 case DEVICE_ID_5906: 2115 case DEVICE_ID_5906M: 2116 cidp->chip_label = 5906; 2117 cidp->pci_type = BGE_PCI_E; 2118 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906; 2119 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906; 2120 cidp->mbuf_hi_water = MBUF_HIWAT_5906; 2121 cidp->mbuf_base = bge_mbuf_pool_base; 2122 cidp->mbuf_length = bge_mbuf_pool_len; 2123 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2124 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2125 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2126 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2127 cidp->statistic_type = BGE_STAT_REG; 2128 dev_ok = B_TRUE; 2129 break; 2130 2131 case DEVICE_ID_5753: 2132 cidp->chip_label = 5753; 2133 cidp->pci_type = BGE_PCI_E; 2134 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2135 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2136 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2137 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2138 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2139 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2140 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2141 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2142 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2143 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2144 cidp->statistic_type = BGE_STAT_REG; 2145 dev_ok = B_TRUE; 2146 break; 2147 2148 case DEVICE_ID_5755: 2149 case DEVICE_ID_5755M: 2150 cidp->chip_label = 5755; 2151 cidp->pci_type = BGE_PCI_E; 2152 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2153 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2154 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2155 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2156 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2157 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2158 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2159 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2160 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2161 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2162 if (cidp->device == DEVICE_ID_5755M) 2163 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2164 cidp->statistic_type = BGE_STAT_REG; 2165 dev_ok = B_TRUE; 2166 break; 2167 2168 case DEVICE_ID_5756M: 2169 /* 2170 * This is nearly identical to the 5755M. 2171 * (Actually reports the 5755 chip ID.) 2172 */ 2173 cidp->chip_label = 5756; 2174 cidp->pci_type = BGE_PCI_E; 2175 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2176 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2177 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2178 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2179 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2180 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2181 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2182 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2183 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2184 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2185 cidp->statistic_type = BGE_STAT_REG; 2186 dev_ok = B_TRUE; 2187 break; 2188 2189 case DEVICE_ID_5787: 2190 case DEVICE_ID_5787M: 2191 cidp->chip_label = 5787; 2192 cidp->pci_type = BGE_PCI_E; 2193 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2194 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2195 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2196 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2197 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2198 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2199 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2200 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2201 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2202 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2203 cidp->statistic_type = BGE_STAT_REG; 2204 dev_ok = B_TRUE; 2205 break; 2206 2207 case DEVICE_ID_5723: 2208 case DEVICE_ID_5761: 2209 case DEVICE_ID_5761E: 2210 cidp->msi_enabled = bge_enable_msi; 2211 /* 2212 * We don't use MSI for BCM5764 and BCM5785, as the 2213 * status block may fail to update when the network 2214 * traffic is heavy. 2215 */ 2216 /* FALLTHRU */ 2217 case DEVICE_ID_5785: 2218 case DEVICE_ID_5764: 2219 if (cidp->device == DEVICE_ID_5723) 2220 cidp->chip_label = 5723; 2221 else if (cidp->device == DEVICE_ID_5764) 2222 cidp->chip_label = 5764; 2223 else if (cidp->device == DEVICE_ID_5785) 2224 cidp->chip_label = 5785; 2225 else 2226 cidp->chip_label = 5761; 2227 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2228 cidp->pci_type = BGE_PCI_E; 2229 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2230 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2231 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2232 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2233 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2234 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2235 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2236 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2237 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2238 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2239 cidp->statistic_type = BGE_STAT_REG; 2240 dev_ok = B_TRUE; 2241 break; 2242 2243 /* PCI-X device, identical to 5714 */ 2244 case DEVICE_ID_5780: 2245 cidp->chip_label = 5780; 2246 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2247 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2248 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2249 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2250 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2251 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2252 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2253 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2254 cidp->statistic_type = BGE_STAT_REG; 2255 dev_ok = B_TRUE; 2256 break; 2257 2258 case DEVICE_ID_5782: 2259 /* 2260 * Apart from the label, we treat this as a 5705(?) 2261 */ 2262 cidp->chip_label = 5782; 2263 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2264 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2265 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2266 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2267 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2268 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2269 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2270 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2271 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2272 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2273 cidp->statistic_type = BGE_STAT_REG; 2274 dev_ok = B_TRUE; 2275 break; 2276 2277 case DEVICE_ID_5788: 2278 /* 2279 * Apart from the label, we treat this as a 5705(?) 2280 */ 2281 cidp->chip_label = 5788; 2282 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2283 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2284 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2285 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2286 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2287 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2288 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2289 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2290 cidp->statistic_type = BGE_STAT_REG; 2291 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2292 dev_ok = B_TRUE; 2293 break; 2294 2295 case DEVICE_ID_5714C: 2296 if (cidp->revision >= REVISION_ID_5714_A2) 2297 cidp->msi_enabled = bge_enable_msi; 2298 /* FALLTHRU */ 2299 case DEVICE_ID_5714S: 2300 cidp->chip_label = 5714; 2301 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2302 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2303 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2304 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2305 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2306 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2307 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2308 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2309 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2310 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2311 cidp->pci_type = BGE_PCI_E; 2312 cidp->statistic_type = BGE_STAT_REG; 2313 dev_ok = B_TRUE; 2314 break; 2315 2316 case DEVICE_ID_5715C: 2317 case DEVICE_ID_5715S: 2318 cidp->chip_label = 5715; 2319 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2320 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2321 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2322 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2323 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2324 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2325 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2326 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2327 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2328 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2329 cidp->pci_type = BGE_PCI_E; 2330 cidp->statistic_type = BGE_STAT_REG; 2331 if (cidp->revision >= REVISION_ID_5715_A2) 2332 cidp->msi_enabled = bge_enable_msi; 2333 dev_ok = B_TRUE; 2334 break; 2335 2336 case DEVICE_ID_5721: 2337 cidp->chip_label = 5721; 2338 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2339 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2340 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2341 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2342 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2343 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2344 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2345 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2346 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2347 cidp->pci_type = BGE_PCI_E; 2348 cidp->statistic_type = BGE_STAT_REG; 2349 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2350 dev_ok = B_TRUE; 2351 break; 2352 2353 case DEVICE_ID_5722: 2354 cidp->chip_label = 5722; 2355 cidp->pci_type = BGE_PCI_E; 2356 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2357 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2358 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2359 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2360 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2361 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2362 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2363 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2364 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2365 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2366 cidp->statistic_type = BGE_STAT_REG; 2367 dev_ok = B_TRUE; 2368 break; 2369 2370 case DEVICE_ID_5751: 2371 case DEVICE_ID_5751M: 2372 cidp->chip_label = 5751; 2373 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2374 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2375 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2376 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2377 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2378 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2379 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2380 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2381 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2382 cidp->pci_type = BGE_PCI_E; 2383 cidp->statistic_type = BGE_STAT_REG; 2384 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2385 dev_ok = B_TRUE; 2386 break; 2387 2388 case DEVICE_ID_5752: 2389 case DEVICE_ID_5752M: 2390 cidp->chip_label = 5752; 2391 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2392 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2393 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2394 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2395 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2396 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2397 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2398 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2399 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2400 cidp->pci_type = BGE_PCI_E; 2401 cidp->statistic_type = BGE_STAT_REG; 2402 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2403 dev_ok = B_TRUE; 2404 break; 2405 2406 case DEVICE_ID_5789: 2407 cidp->chip_label = 5789; 2408 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2409 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2410 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2411 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2412 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2413 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2414 cidp->pci_type = BGE_PCI_E; 2415 cidp->statistic_type = BGE_STAT_REG; 2416 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2417 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2418 cidp->msi_enabled = B_TRUE; 2419 dev_ok = B_TRUE; 2420 break; 2421 2422 } 2423 2424 /* 2425 * Setup the default jumbo parameter. 2426 */ 2427 cidp->ethmax_size = ETHERMAX; 2428 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2429 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2430 2431 /* 2432 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2433 * setup below jumbo specific parameters. 2434 * 2435 * For BCM5714/5715, there is only one standard receive ring. So the 2436 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2437 * feature is enabled. 2438 */ 2439 if (!(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2440 (cidp->default_mtu > BGE_DEFAULT_MTU)) { 2441 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2442 cidp->mbuf_lo_water_rdma = 2443 RDMA_MBUF_LOWAT_5714_JUMBO; 2444 cidp->mbuf_lo_water_rmac = 2445 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2446 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2447 cidp->jumbo_slots = 0; 2448 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2449 } else { 2450 cidp->mbuf_lo_water_rdma = 2451 RDMA_MBUF_LOWAT_JUMBO; 2452 cidp->mbuf_lo_water_rmac = 2453 MAC_RX_MBUF_LOWAT_JUMBO; 2454 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2455 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2456 } 2457 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2458 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2459 cidp->ethmax_size = cidp->default_mtu + 2460 sizeof (struct ether_header); 2461 } 2462 2463 /* 2464 * Identify the NV memory type: SEEPROM or Flash? 2465 */ 2466 cidp->nvtype = bge_nvmem_id(bgep); 2467 2468 /* 2469 * Now, we want to check whether this device is part of a 2470 * supported subsystem (e.g., on the motherboard of a Sun 2471 * branded platform). 2472 * 2473 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2474 */ 2475 if (cidp->subven == VENDOR_ID_SUN) 2476 sys_ok = B_TRUE; 2477 2478 /* 2479 * Rule 2: If it's on the list on known subsystems, then it's OK. 2480 * Note: 0x14e41647 should *not* appear in the list, but the code 2481 * doesn't enforce that. 2482 */ 2483 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2484 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2485 if (err == DDI_PROP_SUCCESS) { 2486 /* 2487 * Got the list; scan for a matching subsystem vendor/device 2488 */ 2489 subid = (cidp->subven << 16) | cidp->subdev; 2490 while (i--) 2491 if (ids[i] == subid) 2492 sys_ok = B_TRUE; 2493 ddi_prop_free(ids); 2494 } 2495 2496 /* 2497 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2498 * 2499 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2500 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2501 * we have to check specially for the exact device paths to the 2502 * motherboard devices on those platforms ;-( 2503 * 2504 * Note: we can't just use the "supported-subsystems" mechanism 2505 * above, because the entry would have to be 0x14e41647 -- which 2506 * would then accept *any* plugin card that *didn't* contain a 2507 * (valid) SEEPROM ;-( 2508 */ 2509 sysname = ddi_node_name(ddi_root_node()); 2510 devname = ddi_pathname(bgep->devinfo, buf); 2511 ASSERT(strlen(devname) > 0); 2512 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2513 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2514 sys_ok = B_TRUE; 2515 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2516 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2517 sys_ok = B_TRUE; 2518 2519 /* 2520 * Now check what we've discovered: is this truly a supported 2521 * chip on (the motherboard of) a supported platform? 2522 * 2523 * Possible problems here: 2524 * 1) it's a completely unheard-of chip 2525 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2526 * 3) it's a chip we would support if it were on the motherboard 2527 * of a Sun platform, but this one isn't ;-( 2528 */ 2529 if (cidp->chip_label == 0) 2530 bge_problem(bgep, 2531 "Device 'pci%04x,%04x' not recognized (%d?)", 2532 cidp->vendor, cidp->device, cidp->device); 2533 else if (!dev_ok) 2534 bge_problem(bgep, 2535 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2536 cidp->vendor, cidp->device, cidp->chip_label, 2537 cidp->revision); 2538 #if BGE_DEBUGGING 2539 else if (!sys_ok) 2540 bge_problem(bgep, 2541 "%d-based subsystem 'pci%04x,%04x' not validated", 2542 cidp->chip_label, cidp->subven, cidp->subdev); 2543 #endif 2544 else 2545 cidp->flags |= CHIP_FLAG_SUPPORTED; 2546 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2547 return (EIO); 2548 return (0); 2549 } 2550 2551 void 2552 bge_chip_msi_trig(bge_t *bgep) 2553 { 2554 uint32_t regval; 2555 2556 regval = bgep->param_msi_cnt<<4; 2557 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2558 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2559 } 2560 2561 /* 2562 * Various registers that control the chip's internal engines (state 2563 * machines) have a <reset> and <enable> bits (fortunately, in the 2564 * same place in each such register :-). 2565 * 2566 * To reset the state machine, the <reset> bit must be written with 1; 2567 * it will then read back as 1 while the reset is in progress, but 2568 * self-clear to 0 when the reset completes. 2569 * 2570 * To enable a state machine, one must set the <enable> bit, which 2571 * will continue to read back as 0 until the state machine is running. 2572 * 2573 * To disable a state machine, the <enable> bit must be cleared, but 2574 * it will continue to read back as 1 until the state machine actually 2575 * stops. 2576 * 2577 * This routine implements polling for completion of a reset, enable 2578 * or disable operation, returning B_TRUE on success (bit reached the 2579 * required state) or B_FALSE on timeout (200*100us == 20ms). 2580 */ 2581 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2582 uint32_t mask, uint32_t val); 2583 #pragma no_inline(bge_chip_poll_engine) 2584 2585 static boolean_t 2586 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2587 uint32_t mask, uint32_t val) 2588 { 2589 uint32_t regval; 2590 uint32_t n; 2591 2592 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2593 (void *)bgep, regno, mask, val)); 2594 2595 for (n = 200; n; --n) { 2596 regval = bge_reg_get32(bgep, regno); 2597 if ((regval & mask) == val) 2598 return (B_TRUE); 2599 drv_usecwait(100); 2600 } 2601 2602 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2603 return (B_FALSE); 2604 } 2605 2606 /* 2607 * Various registers that control the chip's internal engines (state 2608 * machines) have a <reset> bit (fortunately, in the same place in 2609 * each such register :-). To reset the state machine, this bit must 2610 * be written with 1; it will then read back as 1 while the reset is 2611 * in progress, but self-clear to 0 when the reset completes. 2612 * 2613 * This code sets the bit, then polls for it to read back as zero. 2614 * The return value is B_TRUE on success (reset bit cleared itself), 2615 * or B_FALSE if the state machine didn't recover :( 2616 * 2617 * NOTE: the Core reset is similar to other resets, except that we 2618 * can't poll for completion, since the Core reset disables memory 2619 * access! So we just have to assume that it will all complete in 2620 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2621 */ 2622 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2623 #pragma no_inline(bge_chip_reset_engine) 2624 2625 static boolean_t 2626 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2627 { 2628 uint32_t regval; 2629 uint32_t val32; 2630 2631 regval = bge_reg_get32(bgep, regno); 2632 2633 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2634 (void *)bgep, regno)); 2635 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2636 regno, regval)); 2637 2638 regval |= STATE_MACHINE_RESET_BIT; 2639 2640 switch (regno) { 2641 case MISC_CONFIG_REG: 2642 /* 2643 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2644 * resetting PCIE block and bringing PCIE link down, bit 29 2645 * in the register needs to be set first, and then set it again 2646 * while the reset bit is written. 2647 * See:P500 of 57xx-PG102-RDS.pdf. 2648 */ 2649 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2650 DEVICE_5717_SERIES_CHIPSETS(bgep)|| 2651 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2652 DEVICE_5723_SERIES_CHIPSETS(bgep)|| 2653 DEVICE_5714_SERIES_CHIPSETS(bgep)|| 2654 DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2655 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2656 if (bgep->chipid.pci_type == BGE_PCI_E) { 2657 if (bgep->chipid.asic_rev == 2658 MHCR_CHIP_REV_5751_A0 || 2659 bgep->chipid.asic_rev == 2660 MHCR_CHIP_REV_5721_A0 || 2661 bgep->chipid.asic_rev == 2662 MHCR_CHIP_REV_5755_A0) { 2663 val32 = bge_reg_get32(bgep, 2664 PHY_TEST_CTRL_REG); 2665 if (val32 == (PHY_PCIE_SCRAM_MODE | 2666 PHY_PCIE_LTASS_MODE)) 2667 bge_reg_put32(bgep, 2668 PHY_TEST_CTRL_REG, 2669 PHY_PCIE_SCRAM_MODE); 2670 val32 = pci_config_get32 2671 (bgep->cfg_handle, 2672 PCI_CONF_BGE_CLKCTL); 2673 val32 |= CLKCTL_PCIE_A0_FIX; 2674 pci_config_put32(bgep->cfg_handle, 2675 PCI_CONF_BGE_CLKCTL, val32); 2676 } 2677 bge_reg_set32(bgep, regno, 2678 MISC_CONFIG_GRC_RESET_DISABLE); 2679 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2680 } 2681 } 2682 2683 /* 2684 * Special case - causes Core reset 2685 * 2686 * On SPARC v9 we want to ensure that we don't start 2687 * timing until the I/O access has actually reached 2688 * the chip, otherwise we might make the next access 2689 * too early. And we can't just force the write out 2690 * by following it with a read (even to config space) 2691 * because that would cause the fault we're trying 2692 * to avoid. Hence the need for membar_sync() here. 2693 */ 2694 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2695 #ifdef __sparcv9 2696 membar_sync(); 2697 #endif /* __sparcv9 */ 2698 /* 2699 * On some platforms,system need about 300us for 2700 * link setup. 2701 */ 2702 drv_usecwait(300); 2703 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2704 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET); 2705 bge_reg_clr32( 2706 bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF); 2707 } 2708 2709 if (bgep->chipid.pci_type == BGE_PCI_E) { 2710 /* PCI-E device need more reset time */ 2711 drv_usecwait(120000); 2712 2713 /* Set PCIE max payload size and clear error status. */ 2714 if ((bgep->chipid.chip_label == 5721) || 2715 (bgep->chipid.chip_label == 5751) || 2716 (bgep->chipid.chip_label == 5752) || 2717 (bgep->chipid.chip_label == 5789) || 2718 (bgep->chipid.chip_label == 5906)) { 2719 pci_config_put16(bgep->cfg_handle, 2720 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2721 pci_config_put16(bgep->cfg_handle, 2722 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2723 } 2724 2725 if ((bgep->chipid.chip_label == 5723) || 2726 (bgep->chipid.chip_label == 5761)) { 2727 pci_config_put16(bgep->cfg_handle, 2728 PCI_CONF_DEV_CTRL_5723, READ_REQ_SIZE_MAX); 2729 pci_config_put16(bgep->cfg_handle, 2730 PCI_CONF_DEV_STUS_5723, DEVICE_ERROR_STUS); 2731 } 2732 } 2733 2734 BGE_PCICHK(bgep); 2735 return (B_TRUE); 2736 2737 default: 2738 bge_reg_put32(bgep, regno, regval); 2739 return (bge_chip_poll_engine(bgep, regno, 2740 STATE_MACHINE_RESET_BIT, 0)); 2741 } 2742 } 2743 2744 /* 2745 * Various registers that control the chip's internal engines (state 2746 * machines) have an <enable> bit (fortunately, in the same place in 2747 * each such register :-). To stop the state machine, this bit must 2748 * be written with 0, then polled to see when the state machine has 2749 * actually stopped. 2750 * 2751 * The return value is B_TRUE on success (enable bit cleared), or 2752 * B_FALSE if the state machine didn't stop :( 2753 */ 2754 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2755 uint32_t morebits); 2756 #pragma no_inline(bge_chip_disable_engine) 2757 2758 static boolean_t 2759 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2760 { 2761 uint32_t regval; 2762 2763 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2764 (void *)bgep, regno, morebits)); 2765 2766 switch (regno) { 2767 case FTQ_RESET_REG: 2768 /* 2769 * For Schumacher's bugfix CR6490108 2770 */ 2771 #ifdef BGE_IPMI_ASF 2772 #ifdef BGE_NETCONSOLE 2773 if (bgep->asf_enabled) 2774 return (B_TRUE); 2775 #endif 2776 #endif 2777 /* 2778 * Not quite like the others; it doesn't 2779 * have an <enable> bit, but instead we 2780 * have to set and then clear all the bits 2781 */ 2782 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2783 drv_usecwait(100); 2784 bge_reg_put32(bgep, regno, 0); 2785 return (B_TRUE); 2786 2787 default: 2788 regval = bge_reg_get32(bgep, regno); 2789 regval &= ~STATE_MACHINE_ENABLE_BIT; 2790 regval &= ~morebits; 2791 bge_reg_put32(bgep, regno, regval); 2792 return (bge_chip_poll_engine(bgep, regno, 2793 STATE_MACHINE_ENABLE_BIT, 0)); 2794 } 2795 } 2796 2797 /* 2798 * Various registers that control the chip's internal engines (state 2799 * machines) have an <enable> bit (fortunately, in the same place in 2800 * each such register :-). To start the state machine, this bit must 2801 * be written with 1, then polled to see when the state machine has 2802 * actually started. 2803 * 2804 * The return value is B_TRUE on success (enable bit set), or 2805 * B_FALSE if the state machine didn't start :( 2806 */ 2807 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2808 uint32_t morebits); 2809 #pragma no_inline(bge_chip_enable_engine) 2810 2811 static boolean_t 2812 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2813 { 2814 uint32_t regval; 2815 2816 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2817 (void *)bgep, regno, morebits)); 2818 2819 switch (regno) { 2820 case FTQ_RESET_REG: 2821 #ifdef BGE_IPMI_ASF 2822 #ifdef BGE_NETCONSOLE 2823 if (bgep->asf_enabled) 2824 return (B_TRUE); 2825 #endif 2826 #endif 2827 /* 2828 * Not quite like the others; it doesn't 2829 * have an <enable> bit, but instead we 2830 * have to set and then clear all the bits 2831 */ 2832 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2833 drv_usecwait(100); 2834 bge_reg_put32(bgep, regno, 0); 2835 return (B_TRUE); 2836 2837 default: 2838 regval = bge_reg_get32(bgep, regno); 2839 regval |= STATE_MACHINE_ENABLE_BIT; 2840 regval |= morebits; 2841 bge_reg_put32(bgep, regno, regval); 2842 return (bge_chip_poll_engine(bgep, regno, 2843 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2844 } 2845 } 2846 2847 /* 2848 * Reprogram the Ethernet, Transmit, and Receive MAC 2849 * modes to match the param_* variables 2850 */ 2851 void bge_sync_mac_modes(bge_t *bgep); 2852 #pragma no_inline(bge_sync_mac_modes) 2853 2854 void 2855 bge_sync_mac_modes(bge_t *bgep) 2856 { 2857 uint32_t macmode; 2858 uint32_t regval; 2859 2860 ASSERT(mutex_owned(bgep->genlock)); 2861 2862 /* 2863 * Reprogram the Ethernet MAC mode ... 2864 */ 2865 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2866 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2867 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2868 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2869 macmode |= ETHERNET_MODE_LINK_POLARITY; 2870 else 2871 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2872 else 2873 macmode |= ETHERNET_MODE_LINK_POLARITY; 2874 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2875 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2876 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) { 2877 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2878 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2879 else 2880 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2881 } else if (bgep->param_link_speed == 10 || 2882 bgep->param_link_speed == 100) 2883 macmode |= ETHERNET_MODE_PORTMODE_MII; 2884 else 2885 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2886 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2887 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2888 else 2889 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2890 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2891 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2892 else 2893 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2894 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2895 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2896 (void *)bgep, regval, macmode)); 2897 2898 /* 2899 * ... the Transmit MAC mode ... 2900 */ 2901 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2902 if (bgep->param_link_tx_pause) 2903 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2904 else 2905 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2906 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2907 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2908 (void *)bgep, regval, macmode)); 2909 2910 /* 2911 * ... and the Receive MAC mode 2912 */ 2913 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2914 if (bgep->param_link_rx_pause) 2915 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2916 else 2917 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2918 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2919 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2920 (void *)bgep, regval, macmode)); 2921 2922 /* 2923 * For BCM5785, we need to configure the link status in the MI Status 2924 * register with a write command when auto-polling is disabled. 2925 */ 2926 if (bgep->chipid.device == DEVICE_ID_5785) 2927 if (bgep->param_link_speed == 10) 2928 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK 2929 | MI_STATUS_10MBPS); 2930 else 2931 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 2932 } 2933 2934 /* 2935 * bge_chip_sync() -- program the chip with the unicast MAC address, 2936 * the multicast hash table, the required level of promiscuity, and 2937 * the current loopback mode ... 2938 */ 2939 #ifdef BGE_IPMI_ASF 2940 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2941 #else 2942 int bge_chip_sync(bge_t *bgep); 2943 #endif 2944 #pragma no_inline(bge_chip_sync) 2945 2946 int 2947 #ifdef BGE_IPMI_ASF 2948 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2949 #else 2950 bge_chip_sync(bge_t *bgep) 2951 #endif 2952 { 2953 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2954 boolean_t promisc; 2955 uint64_t macaddr; 2956 uint32_t fill = 0; 2957 int i, j; 2958 int retval = DDI_SUCCESS; 2959 2960 BGE_TRACE(("bge_chip_sync($%p)", 2961 (void *)bgep)); 2962 2963 ASSERT(mutex_owned(bgep->genlock)); 2964 2965 promisc = B_FALSE; 2966 fill = ~(uint32_t)0; 2967 2968 if (bgep->promisc) 2969 promisc = B_TRUE; 2970 else 2971 fill = (uint32_t)0; 2972 2973 /* 2974 * If the TX/RX MAC engines are already running, we should stop 2975 * them (and reset the RX engine) before changing the parameters. 2976 * If they're not running, this will have no effect ... 2977 * 2978 * NOTE: this is currently disabled by default because stopping 2979 * and restarting the Tx engine may cause an outgoing packet in 2980 * transit to be truncated. Also, stopping and restarting the 2981 * Rx engine seems to not work correctly on the 5705. Testing 2982 * has not (yet!) revealed any problems with NOT stopping and 2983 * restarting these engines (and Broadcom say their drivers don't 2984 * do this), but if it is found to cause problems, this variable 2985 * can be patched to re-enable the old behaviour ... 2986 */ 2987 if (bge_stop_start_on_sync) { 2988 #ifdef BGE_IPMI_ASF 2989 if (!bgep->asf_enabled) { 2990 if (!bge_chip_disable_engine(bgep, 2991 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2992 retval = DDI_FAILURE; 2993 } else { 2994 if (!bge_chip_disable_engine(bgep, 2995 RECEIVE_MAC_MODE_REG, 0)) 2996 retval = DDI_FAILURE; 2997 } 2998 #else 2999 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 3000 RECEIVE_MODE_KEEP_VLAN_TAG)) 3001 retval = DDI_FAILURE; 3002 #endif 3003 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3004 retval = DDI_FAILURE; 3005 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 3006 retval = DDI_FAILURE; 3007 } 3008 3009 /* 3010 * Reprogram the hashed multicast address table ... 3011 */ 3012 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 3013 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 3014 3015 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 3016 bge_reg_put32(bgep, MAC_HASH_REG(i), 3017 bgep->mcast_hash[i] | fill); 3018 3019 #ifdef BGE_IPMI_ASF 3020 if (!bgep->asf_enabled || !asf_keeplive) { 3021 #endif 3022 /* 3023 * Transform the MAC address(es) from host to chip format, then 3024 * reprogram the transmit random backoff seed and the unicast 3025 * MAC address(es) ... 3026 */ 3027 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 3028 for (i = 0, macaddr = 0ull; 3029 i < ETHERADDRL; ++i) { 3030 macaddr <<= 8; 3031 macaddr |= bgep->curr_addr[j].addr[i]; 3032 } 3033 fill += (macaddr >> 16) + (macaddr & 0xffffffff); 3034 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 3035 3036 BGE_DEBUG(("bge_chip_sync($%p) " 3037 "setting MAC address %012llx", 3038 (void *)bgep, macaddr)); 3039 } 3040 #ifdef BGE_IPMI_ASF 3041 } 3042 #endif 3043 /* 3044 * Set random seed of backoff interval 3045 * - Writing zero means no backoff interval 3046 */ 3047 fill = ((fill >> 20) + (fill >> 10) + fill) & 0x3ff; 3048 if (fill == 0) 3049 fill = 1; 3050 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 3051 3052 /* 3053 * Set or clear the PROMISCUOUS mode bit 3054 */ 3055 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 3056 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 3057 3058 /* 3059 * Sync the rest of the MAC modes too ... 3060 */ 3061 bge_sync_mac_modes(bgep); 3062 3063 /* 3064 * Restart RX/TX MAC engines if required ... 3065 */ 3066 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 3067 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3068 retval = DDI_FAILURE; 3069 #ifdef BGE_IPMI_ASF 3070 if (!bgep->asf_enabled) { 3071 if (!bge_chip_enable_engine(bgep, 3072 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 3073 retval = DDI_FAILURE; 3074 } else { 3075 if (!bge_chip_enable_engine(bgep, 3076 RECEIVE_MAC_MODE_REG, 0)) 3077 retval = DDI_FAILURE; 3078 } 3079 #else 3080 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3081 RECEIVE_MODE_KEEP_VLAN_TAG)) 3082 retval = DDI_FAILURE; 3083 #endif 3084 } 3085 return (retval); 3086 } 3087 3088 /* 3089 * This array defines the sequence of state machine control registers 3090 * in which the <enable> bit must be cleared to bring the chip to a 3091 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 3092 */ 3093 static bge_regno_t shutdown_engine_regs[] = { 3094 RECEIVE_MAC_MODE_REG, 3095 RCV_BD_INITIATOR_MODE_REG, 3096 RCV_LIST_PLACEMENT_MODE_REG, 3097 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 3098 RCV_DATA_BD_INITIATOR_MODE_REG, 3099 RCV_DATA_COMPLETION_MODE_REG, 3100 RCV_BD_COMPLETION_MODE_REG, 3101 3102 SEND_BD_SELECTOR_MODE_REG, 3103 SEND_BD_INITIATOR_MODE_REG, 3104 SEND_DATA_INITIATOR_MODE_REG, 3105 READ_DMA_MODE_REG, 3106 SEND_DATA_COMPLETION_MODE_REG, 3107 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 3108 SEND_BD_COMPLETION_MODE_REG, 3109 TRANSMIT_MAC_MODE_REG, 3110 3111 HOST_COALESCE_MODE_REG, 3112 WRITE_DMA_MODE_REG, 3113 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 3114 FTQ_RESET_REG, /* special - see code */ 3115 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 3116 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 3117 BGE_REGNO_NONE /* terminator */ 3118 }; 3119 3120 #ifndef __sparc 3121 static bge_regno_t quiesce_regs[] = { 3122 READ_DMA_MODE_REG, 3123 DMA_COMPLETION_MODE_REG, 3124 WRITE_DMA_MODE_REG, 3125 BGE_REGNO_NONE 3126 }; 3127 3128 void bge_chip_stop_nonblocking(bge_t *bgep); 3129 #pragma no_inline(bge_chip_stop_nonblocking) 3130 3131 /* 3132 * This function is called by bge_quiesce(). We 3133 * turn off all the DMA engines here. 3134 */ 3135 void 3136 bge_chip_stop_nonblocking(bge_t *bgep) 3137 { 3138 bge_regno_t *rbp; 3139 3140 /* 3141 * Flag that no more activity may be initiated 3142 */ 3143 bgep->progress &= ~PROGRESS_READY; 3144 3145 rbp = quiesce_regs; 3146 while (*rbp != BGE_REGNO_NONE) { 3147 (void) bge_chip_disable_engine(bgep, *rbp, 0); 3148 ++rbp; 3149 } 3150 3151 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3152 } 3153 3154 #endif 3155 3156 /* 3157 * bge_chip_stop() -- stop all chip processing 3158 * 3159 * If the <fault> parameter is B_TRUE, we're stopping the chip because 3160 * we've detected a problem internally; otherwise, this is a normal 3161 * (clean) stop (at user request i.e. the last STREAM has been closed). 3162 */ 3163 void bge_chip_stop(bge_t *bgep, boolean_t fault); 3164 #pragma no_inline(bge_chip_stop) 3165 3166 void 3167 bge_chip_stop(bge_t *bgep, boolean_t fault) 3168 { 3169 bge_regno_t regno; 3170 bge_regno_t *rbp; 3171 boolean_t ok; 3172 3173 BGE_TRACE(("bge_chip_stop($%p)", 3174 (void *)bgep)); 3175 3176 ASSERT(mutex_owned(bgep->genlock)); 3177 3178 rbp = shutdown_engine_regs; 3179 /* 3180 * When driver try to shutdown the BCM5705/5788/5721/5751/ 3181 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 3182 * -ory arbiter should not be disabled. 3183 */ 3184 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 3185 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3186 ok &= bge_chip_disable_engine(bgep, regno, 0); 3187 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 3188 (regno != DMA_COMPLETION_MODE_REG) && 3189 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 3190 (regno != BUFFER_MANAGER_MODE_REG) && 3191 (regno != MEMORY_ARBITER_MODE_REG)) 3192 ok &= bge_chip_disable_engine(bgep, 3193 regno, 0); 3194 } 3195 3196 if (!ok && !fault) 3197 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 3198 3199 /* 3200 * Finally, disable (all) MAC events & clear the MAC status 3201 */ 3202 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 3203 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 3204 3205 /* 3206 * if we're stopping the chip because of a detected fault then do 3207 * appropriate actions 3208 */ 3209 if (fault) { 3210 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 3211 bgep->bge_chip_state = BGE_CHIP_FAULT; 3212 if (!bgep->manual_reset) 3213 ddi_fm_service_impact(bgep->devinfo, 3214 DDI_SERVICE_LOST); 3215 if (bgep->bge_dma_error) { 3216 /* 3217 * need to free buffers in case the fault was 3218 * due to a memory error in a buffer - got to 3219 * do a fair bit of tidying first 3220 */ 3221 if (bgep->progress & PROGRESS_KSTATS) { 3222 bge_fini_kstats(bgep); 3223 bgep->progress &= ~PROGRESS_KSTATS; 3224 } 3225 if (bgep->progress & PROGRESS_INTR) { 3226 bge_intr_disable(bgep); 3227 rw_enter(bgep->errlock, RW_WRITER); 3228 bge_fini_rings(bgep); 3229 rw_exit(bgep->errlock); 3230 bgep->progress &= ~PROGRESS_INTR; 3231 } 3232 if (bgep->progress & PROGRESS_BUFS) { 3233 bge_free_bufs(bgep); 3234 bgep->progress &= ~PROGRESS_BUFS; 3235 } 3236 bgep->bge_dma_error = B_FALSE; 3237 } 3238 } 3239 } else 3240 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3241 } 3242 3243 /* 3244 * Poll for completion of chip's ROM firmware; also, at least on the 3245 * first time through, find and return the hardware MAC address, if any. 3246 */ 3247 static uint64_t bge_poll_firmware(bge_t *bgep); 3248 #pragma no_inline(bge_poll_firmware) 3249 3250 static uint64_t 3251 bge_poll_firmware(bge_t *bgep) 3252 { 3253 uint64_t magic; 3254 uint64_t mac; 3255 uint32_t gen, val; 3256 uint32_t i; 3257 3258 /* 3259 * Step 19: poll for firmware completion (GENCOMM port set 3260 * to the ones complement of T3_MAGIC_NUMBER). 3261 * 3262 * While we're at it, we also read the MAC address register; 3263 * at some stage the firmware will load this with the 3264 * factory-set value. 3265 * 3266 * When both the magic number and the MAC address are set, 3267 * we're done; but we impose a time limit of one second 3268 * (1000*1000us) in case the firmware fails in some fashion 3269 * or the SEEPROM that provides that MAC address isn't fitted. 3270 * 3271 * After the first time through (chip state != INITIAL), we 3272 * don't need the MAC address to be set (we've already got it 3273 * or not, from the first time), so we don't wait for it, but 3274 * we still have to wait for the T3_MAGIC_NUMBER. 3275 * 3276 * Note: the magic number is only a 32-bit quantity, but the NIC 3277 * memory is 64-bit (and big-endian) internally. Addressing the 3278 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3279 * it work correctly on both big- and little-endian hosts. 3280 */ 3281 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3282 MHCR_CHIP_ASIC_REV_5906) { 3283 for (i = 0; i < 1000; ++i) { 3284 drv_usecwait(1000); 3285 val = bge_reg_get32(bgep, VCPU_STATUS_REG); 3286 if (val & VCPU_INIT_DONE) 3287 break; 3288 } 3289 BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops", 3290 (void *)bgep, i)); 3291 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3292 } else { 3293 for (i = 0; i < 1000; ++i) { 3294 drv_usecwait(1000); 3295 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3296 if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep)) 3297 drv_usecwait(100000); 3298 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3299 #ifdef BGE_IPMI_ASF 3300 if (!bgep->asf_enabled) { 3301 #endif 3302 if (gen != ~T3_MAGIC_NUMBER) 3303 continue; 3304 #ifdef BGE_IPMI_ASF 3305 } 3306 #endif 3307 if (mac != 0ULL) 3308 break; 3309 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3310 break; 3311 } 3312 } 3313 3314 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3315 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3316 (void *)bgep, gen, i)); 3317 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3318 mac, magic)); 3319 3320 return (mac); 3321 } 3322 3323 /* 3324 * Maximum times of trying to get the NVRAM access lock 3325 * by calling bge_nvmem_acquire() 3326 */ 3327 #define MAX_TRY_NVMEM_ACQUIRE 10000 3328 3329 #ifdef BGE_IPMI_ASF 3330 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3331 #else 3332 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3333 #endif 3334 #pragma no_inline(bge_chip_reset) 3335 3336 int 3337 #ifdef BGE_IPMI_ASF 3338 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3339 #else 3340 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3341 #endif 3342 { 3343 chip_id_t chipid; 3344 uint64_t mac; 3345 uint64_t magic; 3346 uint32_t modeflags; 3347 uint32_t mhcr; 3348 uint32_t sx0; 3349 uint32_t i, tries; 3350 #ifdef BGE_IPMI_ASF 3351 uint32_t mailbox; 3352 #endif 3353 int retval = DDI_SUCCESS; 3354 3355 BGE_TRACE(("bge_chip_reset($%p, %d)", 3356 (void *)bgep, enable_dma)); 3357 3358 ASSERT(mutex_owned(bgep->genlock)); 3359 3360 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3361 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3362 3363 /* 3364 * Do we need to stop the chip cleanly before resetting? 3365 */ 3366 switch (bgep->bge_chip_state) { 3367 default: 3368 _NOTE(NOTREACHED) 3369 return (DDI_FAILURE); 3370 3371 case BGE_CHIP_INITIAL: 3372 case BGE_CHIP_STOPPED: 3373 case BGE_CHIP_RESET: 3374 break; 3375 3376 case BGE_CHIP_RUNNING: 3377 case BGE_CHIP_ERROR: 3378 case BGE_CHIP_FAULT: 3379 bge_chip_stop(bgep, B_FALSE); 3380 break; 3381 } 3382 3383 #ifdef BGE_IPMI_ASF 3384 if (bgep->asf_enabled) { 3385 #ifdef __sparc 3386 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3387 MHCR_ENABLE_TAGGED_STATUS_MODE | 3388 MHCR_MASK_INTERRUPT_MODE | 3389 MHCR_MASK_PCI_INT_OUTPUT | 3390 MHCR_CLEAR_INTERRUPT_INTA | 3391 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3392 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3393 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 3394 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 3395 0); 3396 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3397 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3398 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3399 MEMORY_ARBITER_ENABLE); 3400 #endif 3401 if (asf_mode == ASF_MODE_INIT) { 3402 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3403 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3404 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3405 } 3406 } 3407 #endif 3408 /* 3409 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3410 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3411 * 3412 * Before reset Core clock,it is 3413 * also required to initialize the Memory Arbiter as specified in step9 3414 * and Misc Host Control Register as specified in step-13 3415 * Step 4-5: reset Core clock & wait for completion 3416 * Steps 6-8: are done by bge_chip_cfg_init() 3417 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3418 */ 3419 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3420 retval = DDI_FAILURE; 3421 3422 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3423 MHCR_ENABLE_TAGGED_STATUS_MODE | 3424 MHCR_MASK_INTERRUPT_MODE | 3425 MHCR_MASK_PCI_INT_OUTPUT | 3426 MHCR_CLEAR_INTERRUPT_INTA; 3427 #ifdef _BIG_ENDIAN 3428 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3429 #endif /* _BIG_ENDIAN */ 3430 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 3431 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 0); 3432 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3433 #ifdef BGE_IPMI_ASF 3434 if (bgep->asf_enabled) 3435 bgep->asf_wordswapped = B_FALSE; 3436 #endif 3437 /* 3438 * NVRAM Corruption Workaround 3439 */ 3440 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3441 if (bge_nvmem_acquire(bgep) != EAGAIN) 3442 break; 3443 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3444 BGE_DEBUG(("%s: fail to acquire nvram lock", 3445 bgep->ifname)); 3446 3447 #ifdef BGE_IPMI_ASF 3448 if (!bgep->asf_enabled) { 3449 #endif 3450 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3451 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3452 #ifdef BGE_IPMI_ASF 3453 } 3454 #endif 3455 3456 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3457 retval = DDI_FAILURE; 3458 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3459 3460 /* 3461 * Step 8a: This may belong elsewhere, but BCM5721 needs 3462 * a bit set to avoid a fifo overflow/underflow bug. 3463 */ 3464 if ((bgep->chipid.chip_label == 5721) || 3465 (bgep->chipid.chip_label == 5751) || 3466 (bgep->chipid.chip_label == 5752) || 3467 (bgep->chipid.chip_label == 5755) || 3468 (bgep->chipid.chip_label == 5756) || 3469 (bgep->chipid.chip_label == 5789) || 3470 (bgep->chipid.chip_label == 5906)) 3471 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3472 3473 3474 /* 3475 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3476 * not be changed. 3477 */ 3478 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3479 retval = DDI_FAILURE; 3480 3481 /* 3482 * Steps 10-11: configure PIO endianness options and 3483 * enable indirect register access -- already done 3484 * Steps 12-13: enable writing to the PCI state & clock 3485 * control registers -- not required; we aren't going to 3486 * use those features. 3487 * Steps 14-15: Configure DMA endianness options. See 3488 * the comments on the setting of the MHCR above. 3489 */ 3490 #ifdef _BIG_ENDIAN 3491 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3492 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3493 #else 3494 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3495 #endif /* _BIG_ENDIAN */ 3496 #ifdef BGE_IPMI_ASF 3497 if (bgep->asf_enabled) 3498 modeflags |= MODE_HOST_STACK_UP; 3499 #endif 3500 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3501 3502 #ifdef BGE_IPMI_ASF 3503 if (bgep->asf_enabled) { 3504 #ifdef __sparc 3505 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3506 MEMORY_ARBITER_ENABLE | 3507 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3508 #endif 3509 3510 #ifdef BGE_NETCONSOLE 3511 if (!bgep->asf_newhandshake) { 3512 if ((asf_mode == ASF_MODE_INIT) || 3513 (asf_mode == ASF_MODE_POST_INIT)) { 3514 bge_asf_post_reset_old_mode(bgep, 3515 BGE_INIT_RESET); 3516 } else { 3517 bge_asf_post_reset_old_mode(bgep, 3518 BGE_SHUTDOWN_RESET); 3519 } 3520 } 3521 #endif 3522 3523 /* Wait for NVRAM init */ 3524 i = 0; 3525 drv_usecwait(5000); 3526 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3527 3528 while ((mailbox != (uint32_t) 3529 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3530 (i < 10000)) { 3531 drv_usecwait(100); 3532 mailbox = bge_nic_get32(bgep, 3533 BGE_FIRMWARE_MAILBOX); 3534 i++; 3535 } 3536 3537 #ifndef BGE_NETCONSOLE 3538 if (!bgep->asf_newhandshake) { 3539 if ((asf_mode == ASF_MODE_INIT) || 3540 (asf_mode == ASF_MODE_POST_INIT)) { 3541 3542 bge_asf_post_reset_old_mode(bgep, 3543 BGE_INIT_RESET); 3544 } else { 3545 bge_asf_post_reset_old_mode(bgep, 3546 BGE_SHUTDOWN_RESET); 3547 } 3548 } 3549 #endif 3550 } 3551 #endif 3552 /* 3553 * Steps 16-17: poll for firmware completion 3554 */ 3555 mac = bge_poll_firmware(bgep); 3556 3557 /* 3558 * Step 18: enable external memory -- doesn't apply. 3559 * 3560 * However we take the opportunity to set the MLCR anyway, as 3561 * this register also controls the SEEPROM auto-access method 3562 * which we may want to use later ... 3563 * 3564 * The proper value here depends on the way the chip is wired 3565 * into the circuit board, as this register *also* controls which 3566 * of the "Miscellaneous I/O" pins are driven as outputs and the 3567 * values driven onto those pins! 3568 * 3569 * See also step 74 in the PRM ... 3570 */ 3571 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3572 bgep->chipid.bge_mlcr_default); 3573 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3574 3575 /* 3576 * Step 20: clear the Ethernet MAC mode register 3577 */ 3578 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3579 3580 /* 3581 * Step 21: restore cache-line-size, latency timer, and 3582 * subsystem ID registers to their original values (not 3583 * those read into the local structure <chipid>, 'cos 3584 * that was after they were cleared by the RESET). 3585 * 3586 * Note: the Subsystem Vendor/Device ID registers are not 3587 * directly writable in config space, so we use the shadow 3588 * copy in "Page Zero" of register space to restore them 3589 * both in one go ... 3590 */ 3591 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3592 bgep->chipid.clsize); 3593 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3594 bgep->chipid.latency); 3595 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3596 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3597 3598 /* 3599 * The SEND INDEX registers should be reset to zero by the 3600 * global chip reset; if they're not, there'll be trouble 3601 * later on. 3602 */ 3603 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3604 if (sx0 != 0) { 3605 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3606 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3607 retval = DDI_FAILURE; 3608 } 3609 3610 /* Enable MSI code */ 3611 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3612 bge_reg_set32(bgep, MSI_MODE_REG, 3613 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3614 3615 /* 3616 * On the first time through, save the factory-set MAC address 3617 * (if any). If bge_poll_firmware() above didn't return one 3618 * (from a chip register) consider looking in the attached NV 3619 * memory device, if any. Once we have it, we save it in both 3620 * register-image (64-bit) and byte-array forms. All-zero and 3621 * all-one addresses are not valid, and we refuse to stash those. 3622 */ 3623 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3624 if (mac == 0ULL) 3625 mac = bge_get_nvmac(bgep); 3626 if (mac != 0ULL && mac != ~0ULL) { 3627 bgep->chipid.hw_mac_addr = mac; 3628 for (i = ETHERADDRL; i-- != 0; ) { 3629 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3630 mac >>= 8; 3631 } 3632 bgep->chipid.vendor_addr.set = B_TRUE; 3633 } 3634 } 3635 3636 #ifdef BGE_IPMI_ASF 3637 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3638 if (asf_mode != ASF_MODE_NONE) { 3639 if ((asf_mode == ASF_MODE_INIT) || 3640 (asf_mode == ASF_MODE_POST_INIT)) { 3641 3642 bge_asf_post_reset_new_mode(bgep, 3643 BGE_INIT_RESET); 3644 } else { 3645 bge_asf_post_reset_new_mode(bgep, 3646 BGE_SHUTDOWN_RESET); 3647 } 3648 } 3649 } 3650 #endif 3651 3652 /* 3653 * Record the new state 3654 */ 3655 bgep->chip_resets += 1; 3656 bgep->bge_chip_state = BGE_CHIP_RESET; 3657 return (retval); 3658 } 3659 3660 /* 3661 * bge_chip_start() -- start the chip transmitting and/or receiving, 3662 * including enabling interrupts 3663 */ 3664 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3665 #pragma no_inline(bge_chip_start) 3666 3667 void 3668 bge_chip_coalesce_update(bge_t *bgep) 3669 { 3670 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, 3671 bgep->chipid.tx_count_norm); 3672 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, 3673 bgep->chipid.tx_ticks_norm); 3674 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, 3675 bgep->chipid.rx_count_norm); 3676 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, 3677 bgep->chipid.rx_ticks_norm); 3678 } 3679 3680 int 3681 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3682 { 3683 uint32_t coalmode; 3684 uint32_t ledctl; 3685 uint32_t mtu; 3686 uint32_t maxring; 3687 uint32_t stats_mask; 3688 uint32_t dma_wrprio; 3689 uint64_t ring; 3690 uint32_t regval; 3691 int retval = DDI_SUCCESS; 3692 3693 BGE_TRACE(("bge_chip_start($%p)", 3694 (void *)bgep)); 3695 3696 ASSERT(mutex_owned(bgep->genlock)); 3697 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3698 3699 /* 3700 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3701 * The document specifies 95 separate steps to fully 3702 * initialise the chip!!!! 3703 * 3704 * The reset code above has already got us as far as step 3705 * 21, so we continue with ... 3706 * 3707 * Step 22: clear the MAC statistics block 3708 * (0x0300-0x0aff in NIC-local memory) 3709 */ 3710 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3711 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3712 NIC_MEM_STATISTICS_SIZE); 3713 3714 /* 3715 * Step 23: clear the status block (in host memory) 3716 */ 3717 DMA_ZERO(bgep->status_block); 3718 3719 /* 3720 * Step 24: set DMA read/write control register 3721 */ 3722 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3723 bgep->chipid.bge_dma_rwctrl); 3724 3725 /* 3726 * Step 25: Configure DMA endianness -- already done (16/17) 3727 * Step 26: Configure Host-Based Send Rings 3728 * Step 27: Indicate Host Stack Up 3729 */ 3730 bge_reg_set32(bgep, MODE_CONTROL_REG, 3731 MODE_HOST_SEND_BDS | 3732 MODE_HOST_STACK_UP); 3733 3734 /* 3735 * Step 28: Configure checksum options: 3736 * Solaris supports the hardware default checksum options. 3737 * 3738 * Workaround for Incorrect pseudo-header checksum calculation. 3739 */ 3740 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3741 bge_reg_set32(bgep, MODE_CONTROL_REG, 3742 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3743 3744 /* 3745 * Step 29: configure Timer Prescaler. The value is always the 3746 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3747 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3748 * for the whole chip! 3749 */ 3750 regval = bge_reg_get32(bgep, MISC_CONFIG_REG); 3751 regval = (regval & 0xffffff00) | MISC_CONFIG_DEFAULT; 3752 bge_reg_put32(bgep, MISC_CONFIG_REG, regval); 3753 3754 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 3755 drv_usecwait(40); 3756 /* put PHY into ready state */ 3757 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ); 3758 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */ 3759 drv_usecwait(40); 3760 } 3761 3762 /* 3763 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3764 * 3765 * If the mbuf_length is specified as 0, we just leave these at 3766 * their hardware defaults, rather than explicitly setting them. 3767 * As the Broadcom HRM,driver better not change the parameters 3768 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3769 */ 3770 if ((bgep->chipid.mbuf_length != 0) && 3771 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3772 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3773 bgep->chipid.mbuf_base); 3774 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3775 bgep->chipid.mbuf_length); 3776 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3777 DMAD_POOL_BASE_DEFAULT); 3778 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3779 DMAD_POOL_LENGTH_DEFAULT); 3780 } 3781 3782 /* 3783 * Step 32: configure MAC memory pool watermarks 3784 */ 3785 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3786 bgep->chipid.mbuf_lo_water_rdma); 3787 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3788 bgep->chipid.mbuf_lo_water_rmac); 3789 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3790 bgep->chipid.mbuf_hi_water); 3791 3792 /* 3793 * Step 33: configure DMA resource watermarks 3794 */ 3795 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3796 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3797 bge_dmad_lo_water); 3798 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3799 bge_dmad_hi_water); 3800 } 3801 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3802 3803 /* 3804 * Steps 34-36: enable buffer manager & internal h/w queues 3805 */ 3806 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3807 STATE_MACHINE_ATTN_ENABLE_BIT)) 3808 retval = DDI_FAILURE; 3809 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3810 retval = DDI_FAILURE; 3811 3812 /* 3813 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3814 */ 3815 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) { 3816 buff_ring_t *brp = &bgep->buff[BGE_STD_BUFF_RING]; 3817 bge_reg_put64(bgep, STD_RCV_BD_RING_RCB_REG, 3818 brp->desc.cookie.dmac_laddress); 3819 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 8, 3820 (brp->desc.nslots) << 16 | brp->buf[0].size << 2); 3821 bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 0xc, 3822 NIC_MEM_SHADOW_BUFF_STD_5717); 3823 } else 3824 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3825 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3826 3827 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3828 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3829 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3830 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3831 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3832 } 3833 3834 /* 3835 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3836 */ 3837 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3838 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3839 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3840 bge_replenish_jumbo); 3841 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3842 bge_replenish_mini); 3843 } 3844 3845 /* 3846 * Steps 41-43: clear Send Ring Producer Indices and initialise 3847 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3848 */ 3849 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3850 maxring = BGE_SEND_RINGS_MAX; 3851 else 3852 maxring = BGE_SEND_RINGS_MAX_5705; 3853 for (ring = 0; ring < maxring; ++ring) { 3854 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3855 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3856 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3857 &bgep->send[ring].hw_rcb); 3858 } 3859 3860 /* 3861 * Steps 44-45: initialise Receive Return Rings 3862 * (0x0200-0x02ff in NIC-local memory) 3863 */ 3864 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3865 maxring = BGE_RECV_RINGS_MAX; 3866 else 3867 maxring = BGE_RECV_RINGS_MAX_5705; 3868 for (ring = 0; ring < maxring; ++ring) 3869 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3870 &bgep->recv[ring].hw_rcb); 3871 3872 /* 3873 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3874 */ 3875 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3876 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3877 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3878 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3879 } 3880 /* 3881 * Step 47: configure the MAC unicast address 3882 * Step 48: configure the random backoff seed 3883 * Step 96: set up multicast filters 3884 */ 3885 #ifdef BGE_IPMI_ASF 3886 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3887 #else 3888 if (bge_chip_sync(bgep) == DDI_FAILURE) 3889 #endif 3890 retval = DDI_FAILURE; 3891 3892 /* 3893 * Step 49: configure the MTU 3894 */ 3895 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3896 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3897 3898 /* 3899 * Step 50: configure the IPG et al 3900 */ 3901 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3902 3903 /* 3904 * Step 51: configure the default Rx Return Ring 3905 */ 3906 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3907 3908 /* 3909 * Steps 52-54: configure Receive List Placement, 3910 * and enable Receive List Placement Statistics 3911 */ 3912 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3913 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3914 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3915 case MHCR_CHIP_ASIC_REV_5700: 3916 case MHCR_CHIP_ASIC_REV_5701: 3917 case MHCR_CHIP_ASIC_REV_5703: 3918 case MHCR_CHIP_ASIC_REV_5704: 3919 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3920 break; 3921 case MHCR_CHIP_ASIC_REV_5705: 3922 break; 3923 default: 3924 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3925 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3926 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3927 break; 3928 } 3929 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3930 3931 if (bgep->chipid.rx_rings > 1) 3932 bge_init_recv_rule(bgep); 3933 3934 /* 3935 * Steps 55-56: enable Send Data Initiator Statistics 3936 */ 3937 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3938 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3939 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3940 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3941 } else { 3942 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3943 SEND_INIT_STATS_ENABLE); 3944 } 3945 /* 3946 * Steps 57-58: stop (?) the Host Coalescing Engine 3947 */ 3948 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3949 retval = DDI_FAILURE; 3950 3951 /* 3952 * Steps 59-62: initialise Host Coalescing parameters 3953 */ 3954 bge_chip_coalesce_update(bgep); 3955 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3956 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3957 bge_tx_count_intr); 3958 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3959 bge_tx_ticks_intr); 3960 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3961 bge_rx_count_intr); 3962 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3963 bge_rx_ticks_intr); 3964 } 3965 3966 /* 3967 * Steps 63-64: initialise status block & statistics 3968 * host memory addresses 3969 * The statistic block does not exist in some chipsets 3970 * Step 65: initialise Statistics Coalescing Tick Counter 3971 */ 3972 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3973 bgep->status_block.cookie.dmac_laddress); 3974 3975 /* 3976 * Steps 66-67: initialise status block & statistics 3977 * NIC-local memory addresses 3978 */ 3979 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3980 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3981 bgep->statistics.cookie.dmac_laddress); 3982 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3983 STATISTICS_TICKS_DEFAULT); 3984 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3985 NIC_MEM_STATUS_BLOCK); 3986 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3987 NIC_MEM_STATISTICS); 3988 } 3989 3990 /* 3991 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3992 * Completion Engine, the Receive List Placement Engine, and the 3993 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3994 * and BCM5715. 3995 */ 3996 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3997 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3998 coalmode = COALESCE_64_BYTE_STATUS; 3999 else 4000 coalmode = 0; 4001 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 4002 coalmode = COALESCE_CLR_TICKS_RX; 4003 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 4004 retval = DDI_FAILURE; 4005 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 4006 STATE_MACHINE_ATTN_ENABLE_BIT)) 4007 retval = DDI_FAILURE; 4008 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 4009 retval = DDI_FAILURE; 4010 4011 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4012 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 4013 STATE_MACHINE_ATTN_ENABLE_BIT)) 4014 retval = DDI_FAILURE; 4015 4016 /* 4017 * Step 72: Enable MAC DMA engines 4018 * Step 73: Clear & enable MAC statistics 4019 */ 4020 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 4021 ETHERNET_MODE_ENABLE_FHDE | 4022 ETHERNET_MODE_ENABLE_RDE | 4023 ETHERNET_MODE_ENABLE_TDE); 4024 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 4025 ETHERNET_MODE_ENABLE_TX_STATS | 4026 ETHERNET_MODE_ENABLE_RX_STATS | 4027 ETHERNET_MODE_CLEAR_TX_STATS | 4028 ETHERNET_MODE_CLEAR_RX_STATS); 4029 4030 /* 4031 * Step 74: configure the MLCR (Miscellaneous Local Control 4032 * Register); not required, as we set up the MLCR in step 10 4033 * (part of the reset code) above. 4034 * 4035 * Step 75: clear Interrupt Mailbox 0 4036 */ 4037 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 4038 4039 /* 4040 * Steps 76-87: Gentlemen, start your engines ... 4041 * 4042 * Enable the DMA Completion Engine, the Write DMA Engine, 4043 * the Read DMA Engine, Receive Data Completion Engine, 4044 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 4045 * the Send BD Completion Engine, the Receive BD Initiator Engine, 4046 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 4047 * the Send BD Initiator Engine, and the Send BD Selector Engine. 4048 * 4049 * Beware exhaust fumes? 4050 */ 4051 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4052 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 4053 retval = DDI_FAILURE; 4054 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 4055 ALL_DMA_ATTN_BITS; 4056 if ((MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 4057 MHCR_CHIP_ASIC_REV_5755) || 4058 (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 4059 MHCR_CHIP_ASIC_REV_5723) || 4060 (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 4061 MHCR_CHIP_ASIC_REV_5906)) { 4062 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 4063 } 4064 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 4065 dma_wrprio)) 4066 retval = DDI_FAILURE; 4067 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || 4068 DEVICE_5717_SERIES_CHIPSETS(bgep)) 4069 bge_dma_rdprio = 0; 4070 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 4071 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 4072 retval = DDI_FAILURE; 4073 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 4074 STATE_MACHINE_ATTN_ENABLE_BIT)) 4075 retval = DDI_FAILURE; 4076 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4077 if (!bge_chip_enable_engine(bgep, 4078 MBUF_CLUSTER_FREE_MODE_REG, 0)) 4079 retval = DDI_FAILURE; 4080 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 4081 retval = DDI_FAILURE; 4082 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 4083 STATE_MACHINE_ATTN_ENABLE_BIT)) 4084 retval = DDI_FAILURE; 4085 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 4086 RCV_BD_DISABLED_RING_ATTN)) 4087 retval = DDI_FAILURE; 4088 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 4089 RCV_DATA_BD_ILL_RING_ATTN)) 4090 retval = DDI_FAILURE; 4091 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 4092 retval = DDI_FAILURE; 4093 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 4094 STATE_MACHINE_ATTN_ENABLE_BIT)) 4095 retval = DDI_FAILURE; 4096 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 4097 STATE_MACHINE_ATTN_ENABLE_BIT)) 4098 retval = DDI_FAILURE; 4099 4100 /* 4101 * Step 88: download firmware -- doesn't apply 4102 * Steps 89-90: enable Transmit & Receive MAC Engines 4103 */ 4104 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 4105 retval = DDI_FAILURE; 4106 #ifdef BGE_IPMI_ASF 4107 if (!bgep->asf_enabled) { 4108 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 4109 RECEIVE_MODE_KEEP_VLAN_TAG)) 4110 retval = DDI_FAILURE; 4111 } else { 4112 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 4113 retval = DDI_FAILURE; 4114 } 4115 #else 4116 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 4117 RECEIVE_MODE_KEEP_VLAN_TAG)) 4118 retval = DDI_FAILURE; 4119 #endif 4120 4121 /* 4122 * Step 91: disable auto-polling of PHY status 4123 */ 4124 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 4125 4126 /* 4127 * Step 92: configure D0 power state (not required) 4128 * Step 93: initialise LED control register () 4129 */ 4130 ledctl = LED_CONTROL_DEFAULT; 4131 switch (bgep->chipid.device) { 4132 case DEVICE_ID_5700: 4133 case DEVICE_ID_5700x: 4134 case DEVICE_ID_5701: 4135 /* 4136 * Switch to 5700 (MAC) mode on these older chips 4137 */ 4138 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 4139 ledctl |= LED_CONTROL_LED_MODE_5700; 4140 break; 4141 4142 default: 4143 break; 4144 } 4145 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 4146 4147 /* 4148 * Step 94: activate link 4149 */ 4150 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 4151 4152 /* 4153 * Step 95: set up physical layer (PHY/SerDes) 4154 * restart autoneg (if required) 4155 */ 4156 if (reset_phys) 4157 if (bge_phys_update(bgep) == DDI_FAILURE) 4158 retval = DDI_FAILURE; 4159 4160 /* 4161 * Extra step (DSG): hand over all the Receive Buffers to the chip 4162 */ 4163 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 4164 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 4165 bgep->buff[ring].rf_next); 4166 4167 /* 4168 * MSI bits:The least significant MSI 16-bit word. 4169 * ISR will be triggered different. 4170 */ 4171 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 4172 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 4173 4174 /* 4175 * Extra step (DSG): select which interrupts are enabled 4176 * 4177 * Program the Ethernet MAC engine to signal attention on 4178 * Link Change events, then enable interrupts on MAC, DMA, 4179 * and FLOW attention signals. 4180 */ 4181 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 4182 ETHERNET_EVENT_LINK_INT | 4183 ETHERNET_STATUS_PCS_ERROR_INT); 4184 #ifdef BGE_IPMI_ASF 4185 if (bgep->asf_enabled) { 4186 bge_reg_set32(bgep, MODE_CONTROL_REG, 4187 MODE_INT_ON_FLOW_ATTN | 4188 MODE_INT_ON_DMA_ATTN | 4189 MODE_HOST_STACK_UP| 4190 MODE_INT_ON_MAC_ATTN); 4191 } else { 4192 #endif 4193 bge_reg_set32(bgep, MODE_CONTROL_REG, 4194 MODE_INT_ON_FLOW_ATTN | 4195 MODE_INT_ON_DMA_ATTN | 4196 MODE_INT_ON_MAC_ATTN); 4197 #ifdef BGE_IPMI_ASF 4198 } 4199 #endif 4200 4201 /* 4202 * Step 97: enable PCI interrupts!!! 4203 */ 4204 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 4205 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 4206 bgep->chipid.mask_pci_int); 4207 4208 /* 4209 * All done! 4210 */ 4211 bgep->bge_chip_state = BGE_CHIP_RUNNING; 4212 return (retval); 4213 } 4214 4215 4216 /* 4217 * ========== Hardware interrupt handler ========== 4218 */ 4219 4220 #undef BGE_DBG 4221 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 4222 4223 /* 4224 * Sync the status block, then atomically clear the specified bits in 4225 * the <flags-and-tag> field of the status block. 4226 * the <flags> word of the status block, returning the value of the 4227 * <tag> and the <flags> before the bits were cleared. 4228 */ 4229 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 4230 #pragma inline(bge_status_sync) 4231 4232 static int 4233 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 4234 { 4235 bge_status_t *bsp; 4236 int retval; 4237 4238 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 4239 (void *)bgep, bits)); 4240 4241 ASSERT(bgep->bge_guard == BGE_GUARD); 4242 4243 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 4244 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 4245 if (retval != DDI_FM_OK) 4246 return (retval); 4247 4248 bsp = DMA_VPTR(bgep->status_block); 4249 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 4250 4251 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 4252 (void *)bgep, bits, *flags)); 4253 4254 return (retval); 4255 } 4256 4257 void bge_wake_factotum(bge_t *bgep); 4258 #pragma inline(bge_wake_factotum) 4259 4260 void 4261 bge_wake_factotum(bge_t *bgep) 4262 { 4263 mutex_enter(bgep->softintrlock); 4264 if (bgep->factotum_flag == 0) { 4265 bgep->factotum_flag = 1; 4266 ddi_trigger_softintr(bgep->factotum_id); 4267 } 4268 mutex_exit(bgep->softintrlock); 4269 } 4270 4271 /* 4272 * bge_intr() -- handle chip interrupts 4273 */ 4274 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 4275 #pragma no_inline(bge_intr) 4276 4277 uint_t 4278 bge_intr(caddr_t arg1, caddr_t arg2) 4279 { 4280 bge_t *bgep = (void *)arg1; /* private device info */ 4281 bge_status_t *bsp; 4282 uint64_t flags; 4283 uint32_t regval; 4284 uint_t result; 4285 int retval, loop_cnt = 0; 4286 4287 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 4288 4289 /* 4290 * GLD v2 checks that s/w setup is complete before passing 4291 * interrupts to this routine, thus eliminating the old 4292 * (and well-known) race condition around ddi_add_intr() 4293 */ 4294 ASSERT(bgep->progress & PROGRESS_HWINT); 4295 4296 result = DDI_INTR_UNCLAIMED; 4297 mutex_enter(bgep->genlock); 4298 4299 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4300 /* 4301 * Check whether chip's says it's asserting #INTA; 4302 * if not, don't process or claim the interrupt. 4303 * 4304 * Note that the PCI signal is active low, so the 4305 * bit is *zero* when the interrupt is asserted. 4306 */ 4307 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 4308 if (!(DEVICE_5717_SERIES_CHIPSETS(bgep)) && 4309 (regval & MLCR_INTA_STATE)) { 4310 if (bge_check_acc_handle(bgep, bgep->io_handle) 4311 != DDI_FM_OK) 4312 goto chip_stop; 4313 mutex_exit(bgep->genlock); 4314 return (result); 4315 } 4316 4317 /* 4318 * Block further PCI interrupts ... 4319 */ 4320 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 4321 bgep->chipid.mask_pci_int); 4322 4323 } else { 4324 /* 4325 * Check MSI status 4326 */ 4327 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 4328 if (regval & MSI_ERROR_ATTENTION) { 4329 BGE_REPORT((bgep, "msi error attention," 4330 " status=0x%x", regval)); 4331 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 4332 } 4333 } 4334 4335 result = DDI_INTR_CLAIMED; 4336 4337 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 4338 4339 /* 4340 * Sync the status block and grab the flags-n-tag from it. 4341 * We count the number of interrupts where there doesn't 4342 * seem to have been a DMA update of the status block; if 4343 * it *has* been updated, the counter will be cleared in 4344 * the while() loop below ... 4345 */ 4346 bgep->missed_dmas += 1; 4347 bsp = DMA_VPTR(bgep->status_block); 4348 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 4349 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 4350 /* 4351 * bge_chip_stop() may have freed dma area etc 4352 * while we were in this interrupt handler - 4353 * better not call bge_status_sync() 4354 */ 4355 (void) bge_check_acc_handle(bgep, 4356 bgep->io_handle); 4357 mutex_exit(bgep->genlock); 4358 return (DDI_INTR_CLAIMED); 4359 } 4360 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 4361 &flags); 4362 if (retval != DDI_FM_OK) { 4363 bgep->bge_dma_error = B_TRUE; 4364 goto chip_stop; 4365 } 4366 4367 if (!(flags & STATUS_FLAG_UPDATED)) 4368 break; 4369 4370 /* 4371 * Tell the chip that we're processing the interrupt 4372 */ 4373 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4374 INTERRUPT_MBOX_DISABLE(flags)); 4375 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4376 DDI_FM_OK) 4377 goto chip_stop; 4378 4379 /* 4380 * Drop the mutex while we: 4381 * Receive any newly-arrived packets 4382 * Recycle any newly-finished send buffers 4383 */ 4384 bgep->bge_intr_running = B_TRUE; 4385 mutex_exit(bgep->genlock); 4386 bge_receive(bgep, bsp); 4387 bge_recycle(bgep, bsp); 4388 mutex_enter(bgep->genlock); 4389 bgep->bge_intr_running = B_FALSE; 4390 4391 /* 4392 * Tell the chip we've finished processing, and 4393 * give it the tag that we got from the status 4394 * block earlier, so that it knows just how far 4395 * we've gone. If it's got more for us to do, 4396 * it will now update the status block and try 4397 * to assert an interrupt (but we've got the 4398 * #INTA blocked at present). If we see the 4399 * update, we'll loop around to do some more. 4400 * Eventually we'll get out of here ... 4401 */ 4402 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4403 INTERRUPT_MBOX_ENABLE(flags)); 4404 if (bgep->chipid.pci_type == BGE_PCI_E) 4405 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 4406 bgep->missed_dmas = 0; 4407 } 4408 4409 /* 4410 * Check for exceptional conditions that we need to handle 4411 * 4412 * Link status changed 4413 * Status block not updated 4414 */ 4415 if (flags & STATUS_FLAG_LINK_CHANGED) 4416 bge_wake_factotum(bgep); 4417 4418 if (bgep->missed_dmas) { 4419 /* 4420 * Probably due to the internal status tag not 4421 * being reset. Force a status block update now; 4422 * this should ensure that we get an update and 4423 * a new interrupt. After that, we should be in 4424 * sync again ... 4425 */ 4426 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4427 "not updated?", flags)); 4428 bgep->missed_updates++; 4429 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4430 COALESCE_NOW); 4431 4432 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4433 /* 4434 * If this happens multiple times in a row, 4435 * it means DMA is just not working. Maybe 4436 * the chip's failed, or maybe there's a 4437 * problem on the PCI bus or in the host-PCI 4438 * bridge (Tomatillo). 4439 * 4440 * At all events, we want to stop further 4441 * interrupts and let the recovery code take 4442 * over to see whether anything can be done 4443 * about it ... 4444 */ 4445 bge_fm_ereport(bgep, 4446 DDI_FM_DEVICE_BADINT_LIMIT); 4447 goto chip_stop; 4448 } 4449 } 4450 4451 /* 4452 * Reenable assertion of #INTA, unless there's a DMA fault 4453 */ 4454 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4455 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4456 bgep->chipid.mask_pci_int); 4457 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4458 DDI_FM_OK) 4459 goto chip_stop; 4460 } 4461 4462 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4463 goto chip_stop; 4464 4465 mutex_exit(bgep->genlock); 4466 return (result); 4467 4468 chip_stop: 4469 #ifdef BGE_IPMI_ASF 4470 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4471 /* 4472 * We must stop ASF heart beat before 4473 * bge_chip_stop(), otherwise some 4474 * computers (ex. IBM HS20 blade 4475 * server) may crash. 4476 */ 4477 bge_asf_update_status(bgep); 4478 bge_asf_stop_timer(bgep); 4479 bgep->asf_status = ASF_STAT_STOP; 4480 4481 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4482 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4483 } 4484 #endif 4485 bge_chip_stop(bgep, B_TRUE); 4486 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4487 mutex_exit(bgep->genlock); 4488 return (result); 4489 } 4490 4491 /* 4492 * ========== Factotum, implemented as a softint handler ========== 4493 */ 4494 4495 #undef BGE_DBG 4496 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4497 4498 static void bge_factotum_error_handler(bge_t *bgep); 4499 #pragma no_inline(bge_factotum_error_handler) 4500 4501 static void 4502 bge_factotum_error_handler(bge_t *bgep) 4503 { 4504 uint32_t flow; 4505 uint32_t rdma; 4506 uint32_t wdma; 4507 uint32_t tmac; 4508 uint32_t rmac; 4509 uint32_t rxrs; 4510 uint32_t txrs = 0; 4511 4512 ASSERT(mutex_owned(bgep->genlock)); 4513 4514 /* 4515 * Read all the registers that show the possible 4516 * reasons for the ERROR bit to be asserted 4517 */ 4518 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4519 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4520 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4521 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4522 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4523 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4524 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4525 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4526 4527 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4528 (void *)bgep, flow, rdma, wdma)); 4529 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4530 (void *)bgep, tmac, rmac, rxrs, txrs)); 4531 4532 /* 4533 * For now, just clear all the errors ... 4534 */ 4535 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4536 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4537 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4538 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4539 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4540 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4541 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4542 } 4543 4544 /* 4545 * Handler for hardware link state change. 4546 * 4547 * When this routine is called, the hardware link state has changed 4548 * and the new state is reflected in the param_* variables. Here 4549 * we must update the softstate and reprogram the MAC to match. 4550 */ 4551 static void bge_factotum_link_handler(bge_t *bgep); 4552 #pragma no_inline(bge_factotum_link_handler) 4553 4554 static void 4555 bge_factotum_link_handler(bge_t *bgep) 4556 { 4557 ASSERT(mutex_owned(bgep->genlock)); 4558 4559 /* 4560 * Update the s/w link_state 4561 */ 4562 if (bgep->param_link_up) 4563 bgep->link_state = LINK_STATE_UP; 4564 else 4565 bgep->link_state = LINK_STATE_DOWN; 4566 4567 /* 4568 * Reprogram the MAC modes to match 4569 */ 4570 bge_sync_mac_modes(bgep); 4571 } 4572 4573 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4574 #pragma no_inline(bge_factotum_link_check) 4575 4576 static boolean_t 4577 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4578 { 4579 boolean_t check; 4580 uint64_t flags; 4581 uint32_t tmac_status; 4582 4583 ASSERT(mutex_owned(bgep->genlock)); 4584 4585 /* 4586 * Get & clear the writable status bits in the Tx status register 4587 * (some bits are write-1-to-clear, others are just readonly). 4588 */ 4589 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4590 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4591 4592 /* 4593 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4594 */ 4595 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4596 STATUS_FLAG_LINK_CHANGED, &flags); 4597 if (*dma_state != DDI_FM_OK) 4598 return (B_FALSE); 4599 4600 /* 4601 * Clear any errors flagged in the status block ... 4602 */ 4603 if (flags & STATUS_FLAG_ERROR) 4604 bge_factotum_error_handler(bgep); 4605 4606 /* 4607 * We need to check the link status if: 4608 * the status block says there's been a link change 4609 * or there's any discrepancy between the various 4610 * flags indicating the link state (link_state, 4611 * param_link_up, and the LINK STATE bit in the 4612 * Transmit MAC status register). 4613 */ 4614 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4615 switch (bgep->link_state) { 4616 case LINK_STATE_UP: 4617 check |= (bgep->param_link_up == B_FALSE); 4618 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4619 break; 4620 4621 case LINK_STATE_DOWN: 4622 check |= (bgep->param_link_up != B_FALSE); 4623 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4624 break; 4625 4626 default: 4627 check = B_TRUE; 4628 break; 4629 } 4630 4631 /* 4632 * If <check> is false, we're sure the link hasn't changed. 4633 * If true, however, it's not yet definitive; we have to call 4634 * bge_phys_check() to determine whether the link has settled 4635 * into a new state yet ... and if it has, then call the link 4636 * state change handler.But when the chip is 5700 in Dell 6650 4637 * ,even if check is false, the link may have changed.So we 4638 * have to call bge_phys_check() to determine the link state. 4639 */ 4640 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4641 check = bge_phys_check(bgep); 4642 if (check) 4643 bge_factotum_link_handler(bgep); 4644 } 4645 4646 return (check); 4647 } 4648 4649 /* 4650 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4651 */ 4652 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4653 #pragma no_inline(bge_factotum_stall_check) 4654 4655 static boolean_t 4656 bge_factotum_stall_check(bge_t *bgep) 4657 { 4658 uint32_t dogval; 4659 4660 ASSERT(mutex_owned(bgep->genlock)); 4661 4662 /* 4663 * Specific check for Tx stall ... 4664 * 4665 * The 'watchdog' counter is incremented whenever a packet 4666 * is queued, reset to 1 when some (but not all) buffers 4667 * are reclaimed, reset to 0 (disabled) when all buffers 4668 * are reclaimed, and shifted left here. If it exceeds the 4669 * threshold value, the chip is assumed to have stalled and 4670 * is put into the ERROR state. The factotum will then reset 4671 * it on the next pass. 4672 * 4673 * All of which should ensure that we don't get into a state 4674 * where packets are left pending indefinitely! 4675 */ 4676 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4677 if (dogval < bge_watchdog_count) 4678 return (B_FALSE); 4679 4680 #if !defined(BGE_NETCONSOLE) 4681 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4682 #endif 4683 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4684 return (B_TRUE); 4685 } 4686 4687 /* 4688 * The factotum is woken up when there's something to do that we'd rather 4689 * not do from inside a hardware interrupt handler or high-level cyclic. 4690 * Its two main tasks are: 4691 * reset & restart the chip after an error 4692 * check the link status whenever necessary 4693 */ 4694 uint_t bge_chip_factotum(caddr_t arg); 4695 #pragma no_inline(bge_chip_factotum) 4696 4697 uint_t 4698 bge_chip_factotum(caddr_t arg) 4699 { 4700 bge_t *bgep; 4701 uint_t result; 4702 boolean_t error; 4703 boolean_t linkchg; 4704 int dma_state; 4705 4706 bgep = (void *)arg; 4707 4708 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4709 4710 mutex_enter(bgep->softintrlock); 4711 if (bgep->factotum_flag == 0) { 4712 mutex_exit(bgep->softintrlock); 4713 return (DDI_INTR_UNCLAIMED); 4714 } 4715 bgep->factotum_flag = 0; 4716 mutex_exit(bgep->softintrlock); 4717 4718 result = DDI_INTR_CLAIMED; 4719 error = B_FALSE; 4720 linkchg = B_FALSE; 4721 4722 mutex_enter(bgep->genlock); 4723 switch (bgep->bge_chip_state) { 4724 default: 4725 break; 4726 4727 case BGE_CHIP_RUNNING: 4728 linkchg = bge_factotum_link_check(bgep, &dma_state); 4729 error = bge_factotum_stall_check(bgep); 4730 if (dma_state != DDI_FM_OK) { 4731 bgep->bge_dma_error = B_TRUE; 4732 error = B_TRUE; 4733 } 4734 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4735 error = B_TRUE; 4736 if (error) 4737 bgep->bge_chip_state = BGE_CHIP_ERROR; 4738 break; 4739 4740 case BGE_CHIP_ERROR: 4741 error = B_TRUE; 4742 break; 4743 4744 case BGE_CHIP_FAULT: 4745 /* 4746 * Fault detected, time to reset ... 4747 */ 4748 if (bge_autorecover) { 4749 if (!(bgep->progress & PROGRESS_BUFS)) { 4750 /* 4751 * if we can't allocate the ring buffers, 4752 * try later 4753 */ 4754 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4755 mutex_exit(bgep->genlock); 4756 return (result); 4757 } 4758 bgep->progress |= PROGRESS_BUFS; 4759 } 4760 if (!(bgep->progress & PROGRESS_INTR)) { 4761 bge_init_rings(bgep); 4762 bge_intr_enable(bgep); 4763 bgep->progress |= PROGRESS_INTR; 4764 } 4765 if (!(bgep->progress & PROGRESS_KSTATS)) { 4766 bge_init_kstats(bgep, 4767 ddi_get_instance(bgep->devinfo)); 4768 bgep->progress |= PROGRESS_KSTATS; 4769 } 4770 4771 BGE_REPORT((bgep, "automatic recovery activated")); 4772 4773 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4774 bgep->bge_chip_state = BGE_CHIP_ERROR; 4775 error = B_TRUE; 4776 } 4777 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4778 DDI_FM_OK) { 4779 bgep->bge_chip_state = BGE_CHIP_ERROR; 4780 error = B_TRUE; 4781 } 4782 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4783 DDI_FM_OK) { 4784 bgep->bge_chip_state = BGE_CHIP_ERROR; 4785 error = B_TRUE; 4786 } 4787 if (error == B_FALSE) { 4788 #ifdef BGE_IPMI_ASF 4789 if (bgep->asf_enabled && 4790 bgep->asf_status != ASF_STAT_RUN) { 4791 bgep->asf_timeout_id = timeout( 4792 bge_asf_heartbeat, (void *)bgep, 4793 drv_usectohz( 4794 BGE_ASF_HEARTBEAT_INTERVAL)); 4795 bgep->asf_status = ASF_STAT_RUN; 4796 } 4797 #endif 4798 if (!bgep->manual_reset) { 4799 ddi_fm_service_impact(bgep->devinfo, 4800 DDI_SERVICE_RESTORED); 4801 } 4802 } 4803 } 4804 break; 4805 } 4806 4807 4808 /* 4809 * If an error is detected, stop the chip now, marking it as 4810 * faulty, so that it will be reset next time through ... 4811 * 4812 * Note that if intr_running is set, then bge_intr() has dropped 4813 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4814 * this point so have to wait until the next time the factotum runs. 4815 */ 4816 if (error && !bgep->bge_intr_running) { 4817 #ifdef BGE_IPMI_ASF 4818 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4819 /* 4820 * We must stop ASF heart beat before bge_chip_stop(), 4821 * otherwise some computers (ex. IBM HS20 blade server) 4822 * may crash. 4823 */ 4824 bge_asf_update_status(bgep); 4825 bge_asf_stop_timer(bgep); 4826 bgep->asf_status = ASF_STAT_STOP; 4827 4828 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4829 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4830 } 4831 #endif 4832 bge_chip_stop(bgep, B_TRUE); 4833 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4834 } 4835 mutex_exit(bgep->genlock); 4836 4837 /* 4838 * If the link state changed, tell the world about it. 4839 * Note: can't do this while still holding the mutex. 4840 */ 4841 if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT && 4842 bgep->link_state != LINK_STATE_UNKNOWN) 4843 linkchg = B_TRUE; 4844 else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT && 4845 bgep->link_state == LINK_STATE_DOWN) 4846 linkchg = B_FALSE; 4847 4848 if (linkchg) { 4849 mac_link_update(bgep->mh, bgep->link_state); 4850 bgep->link_update_timer = BGE_LINK_UPDATE_DONE; 4851 } 4852 if (bgep->manual_reset) { 4853 bgep->manual_reset = B_FALSE; 4854 } 4855 4856 return (result); 4857 } 4858 4859 /* 4860 * High-level cyclic handler 4861 * 4862 * This routine schedules a (low-level) softint callback to the 4863 * factotum, and prods the chip to update the status block (which 4864 * will cause a hardware interrupt when complete). 4865 */ 4866 void bge_chip_cyclic(void *arg); 4867 #pragma no_inline(bge_chip_cyclic) 4868 4869 void 4870 bge_chip_cyclic(void *arg) 4871 { 4872 bge_t *bgep; 4873 4874 bgep = arg; 4875 4876 switch (bgep->bge_chip_state) { 4877 default: 4878 return; 4879 4880 case BGE_CHIP_RUNNING: 4881 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4882 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4883 ddi_fm_service_impact(bgep->devinfo, 4884 DDI_SERVICE_UNAFFECTED); 4885 4886 if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT) 4887 bgep->link_update_timer++; 4888 4889 break; 4890 4891 case BGE_CHIP_FAULT: 4892 case BGE_CHIP_ERROR: 4893 break; 4894 } 4895 4896 bge_wake_factotum(bgep); 4897 } 4898 4899 4900 /* 4901 * ========== Ioctl subfunctions ========== 4902 */ 4903 4904 #undef BGE_DBG 4905 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4906 4907 #if BGE_DEBUGGING || BGE_DO_PPIO 4908 4909 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4910 #pragma no_inline(bge_chip_peek_cfg) 4911 4912 static void 4913 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4914 { 4915 uint64_t regval; 4916 uint64_t regno; 4917 4918 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4919 (void *)bgep, (void *)ppd)); 4920 4921 regno = ppd->pp_acc_offset; 4922 4923 switch (ppd->pp_acc_size) { 4924 case 1: 4925 regval = pci_config_get8(bgep->cfg_handle, regno); 4926 break; 4927 4928 case 2: 4929 regval = pci_config_get16(bgep->cfg_handle, regno); 4930 break; 4931 4932 case 4: 4933 regval = pci_config_get32(bgep->cfg_handle, regno); 4934 break; 4935 4936 case 8: 4937 regval = pci_config_get64(bgep->cfg_handle, regno); 4938 break; 4939 } 4940 4941 ppd->pp_acc_data = regval; 4942 } 4943 4944 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4945 #pragma no_inline(bge_chip_poke_cfg) 4946 4947 static void 4948 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4949 { 4950 uint64_t regval; 4951 uint64_t regno; 4952 4953 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4954 (void *)bgep, (void *)ppd)); 4955 4956 regno = ppd->pp_acc_offset; 4957 regval = ppd->pp_acc_data; 4958 4959 switch (ppd->pp_acc_size) { 4960 case 1: 4961 pci_config_put8(bgep->cfg_handle, regno, regval); 4962 break; 4963 4964 case 2: 4965 pci_config_put16(bgep->cfg_handle, regno, regval); 4966 break; 4967 4968 case 4: 4969 pci_config_put32(bgep->cfg_handle, regno, regval); 4970 break; 4971 4972 case 8: 4973 pci_config_put64(bgep->cfg_handle, regno, regval); 4974 break; 4975 } 4976 } 4977 4978 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4979 #pragma no_inline(bge_chip_peek_reg) 4980 4981 static void 4982 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4983 { 4984 uint64_t regval; 4985 void *regaddr; 4986 4987 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4988 (void *)bgep, (void *)ppd)); 4989 4990 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4991 4992 switch (ppd->pp_acc_size) { 4993 case 1: 4994 regval = ddi_get8(bgep->io_handle, regaddr); 4995 break; 4996 4997 case 2: 4998 regval = ddi_get16(bgep->io_handle, regaddr); 4999 break; 5000 5001 case 4: 5002 regval = ddi_get32(bgep->io_handle, regaddr); 5003 break; 5004 5005 case 8: 5006 regval = ddi_get64(bgep->io_handle, regaddr); 5007 break; 5008 } 5009 5010 ppd->pp_acc_data = regval; 5011 } 5012 5013 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 5014 #pragma no_inline(bge_chip_peek_reg) 5015 5016 static void 5017 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 5018 { 5019 uint64_t regval; 5020 void *regaddr; 5021 5022 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 5023 (void *)bgep, (void *)ppd)); 5024 5025 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 5026 regval = ppd->pp_acc_data; 5027 5028 switch (ppd->pp_acc_size) { 5029 case 1: 5030 ddi_put8(bgep->io_handle, regaddr, regval); 5031 break; 5032 5033 case 2: 5034 ddi_put16(bgep->io_handle, regaddr, regval); 5035 break; 5036 5037 case 4: 5038 ddi_put32(bgep->io_handle, regaddr, regval); 5039 break; 5040 5041 case 8: 5042 ddi_put64(bgep->io_handle, regaddr, regval); 5043 break; 5044 } 5045 BGE_PCICHK(bgep); 5046 } 5047 5048 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 5049 #pragma no_inline(bge_chip_peek_nic) 5050 5051 static void 5052 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 5053 { 5054 uint64_t regoff; 5055 uint64_t regval; 5056 void *regaddr; 5057 5058 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 5059 (void *)bgep, (void *)ppd)); 5060 5061 regoff = ppd->pp_acc_offset; 5062 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 5063 regoff &= MWBAR_GRANULE_MASK; 5064 regoff += NIC_MEM_WINDOW_OFFSET; 5065 regaddr = PIO_ADDR(bgep, regoff); 5066 5067 switch (ppd->pp_acc_size) { 5068 case 1: 5069 regval = ddi_get8(bgep->io_handle, regaddr); 5070 break; 5071 5072 case 2: 5073 regval = ddi_get16(bgep->io_handle, regaddr); 5074 break; 5075 5076 case 4: 5077 regval = ddi_get32(bgep->io_handle, regaddr); 5078 break; 5079 5080 case 8: 5081 regval = ddi_get64(bgep->io_handle, regaddr); 5082 break; 5083 } 5084 5085 ppd->pp_acc_data = regval; 5086 } 5087 5088 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 5089 #pragma no_inline(bge_chip_poke_nic) 5090 5091 static void 5092 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 5093 { 5094 uint64_t regoff; 5095 uint64_t regval; 5096 void *regaddr; 5097 5098 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 5099 (void *)bgep, (void *)ppd)); 5100 5101 regoff = ppd->pp_acc_offset; 5102 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 5103 regoff &= MWBAR_GRANULE_MASK; 5104 regoff += NIC_MEM_WINDOW_OFFSET; 5105 regaddr = PIO_ADDR(bgep, regoff); 5106 regval = ppd->pp_acc_data; 5107 5108 switch (ppd->pp_acc_size) { 5109 case 1: 5110 ddi_put8(bgep->io_handle, regaddr, regval); 5111 break; 5112 5113 case 2: 5114 ddi_put16(bgep->io_handle, regaddr, regval); 5115 break; 5116 5117 case 4: 5118 ddi_put32(bgep->io_handle, regaddr, regval); 5119 break; 5120 5121 case 8: 5122 ddi_put64(bgep->io_handle, regaddr, regval); 5123 break; 5124 } 5125 BGE_PCICHK(bgep); 5126 } 5127 5128 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5129 #pragma no_inline(bge_chip_peek_mii) 5130 5131 static void 5132 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5133 { 5134 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 5135 (void *)bgep, (void *)ppd)); 5136 5137 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 5138 } 5139 5140 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5141 #pragma no_inline(bge_chip_poke_mii) 5142 5143 static void 5144 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5145 { 5146 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 5147 (void *)bgep, (void *)ppd)); 5148 5149 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 5150 } 5151 5152 #if BGE_SEE_IO32 5153 5154 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5155 #pragma no_inline(bge_chip_peek_seeprom) 5156 5157 static void 5158 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5159 { 5160 uint32_t data; 5161 int err; 5162 5163 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 5164 (void *)bgep, (void *)ppd)); 5165 5166 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 5167 ppd->pp_acc_data = err ? ~0ull : data; 5168 } 5169 5170 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5171 #pragma no_inline(bge_chip_poke_seeprom) 5172 5173 static void 5174 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5175 { 5176 uint32_t data; 5177 5178 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 5179 (void *)bgep, (void *)ppd)); 5180 5181 data = ppd->pp_acc_data; 5182 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 5183 } 5184 #endif /* BGE_SEE_IO32 */ 5185 5186 #if BGE_FLASH_IO32 5187 5188 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5189 #pragma no_inline(bge_chip_peek_flash) 5190 5191 static void 5192 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5193 { 5194 uint32_t data; 5195 int err; 5196 5197 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 5198 (void *)bgep, (void *)ppd)); 5199 5200 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 5201 ppd->pp_acc_data = err ? ~0ull : data; 5202 } 5203 5204 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5205 #pragma no_inline(bge_chip_poke_flash) 5206 5207 static void 5208 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5209 { 5210 uint32_t data; 5211 5212 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 5213 (void *)bgep, (void *)ppd)); 5214 5215 data = ppd->pp_acc_data; 5216 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 5217 ppd->pp_acc_offset, &data); 5218 } 5219 #endif /* BGE_FLASH_IO32 */ 5220 5221 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5222 #pragma no_inline(bge_chip_peek_mem) 5223 5224 static void 5225 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5226 { 5227 uint64_t regval; 5228 void *vaddr; 5229 5230 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 5231 (void *)bgep, (void *)ppd)); 5232 5233 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5234 5235 switch (ppd->pp_acc_size) { 5236 case 1: 5237 regval = *(uint8_t *)vaddr; 5238 break; 5239 5240 case 2: 5241 regval = *(uint16_t *)vaddr; 5242 break; 5243 5244 case 4: 5245 regval = *(uint32_t *)vaddr; 5246 break; 5247 5248 case 8: 5249 regval = *(uint64_t *)vaddr; 5250 break; 5251 } 5252 5253 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 5254 (void *)bgep, (void *)ppd, regval, vaddr)); 5255 5256 ppd->pp_acc_data = regval; 5257 } 5258 5259 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5260 #pragma no_inline(bge_chip_poke_mem) 5261 5262 static void 5263 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5264 { 5265 uint64_t regval; 5266 void *vaddr; 5267 5268 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 5269 (void *)bgep, (void *)ppd)); 5270 5271 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5272 regval = ppd->pp_acc_data; 5273 5274 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 5275 (void *)bgep, (void *)ppd, regval, vaddr)); 5276 5277 switch (ppd->pp_acc_size) { 5278 case 1: 5279 *(uint8_t *)vaddr = (uint8_t)regval; 5280 break; 5281 5282 case 2: 5283 *(uint16_t *)vaddr = (uint16_t)regval; 5284 break; 5285 5286 case 4: 5287 *(uint32_t *)vaddr = (uint32_t)regval; 5288 break; 5289 5290 case 8: 5291 *(uint64_t *)vaddr = (uint64_t)regval; 5292 break; 5293 } 5294 } 5295 5296 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5297 struct iocblk *iocp); 5298 #pragma no_inline(bge_pp_ioctl) 5299 5300 static enum ioc_reply 5301 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5302 { 5303 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 5304 bge_peekpoke_t *ppd; 5305 dma_area_t *areap; 5306 uint64_t sizemask; 5307 uint64_t mem_va; 5308 uint64_t maxoff; 5309 boolean_t peek; 5310 5311 switch (cmd) { 5312 default: 5313 /* NOTREACHED */ 5314 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 5315 return (IOC_INVAL); 5316 5317 case BGE_PEEK: 5318 peek = B_TRUE; 5319 break; 5320 5321 case BGE_POKE: 5322 peek = B_FALSE; 5323 break; 5324 } 5325 5326 /* 5327 * Validate format of ioctl 5328 */ 5329 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 5330 return (IOC_INVAL); 5331 if (mp->b_cont == NULL) 5332 return (IOC_INVAL); 5333 ppd = (void *)mp->b_cont->b_rptr; 5334 5335 /* 5336 * Validate request parameters 5337 */ 5338 switch (ppd->pp_acc_space) { 5339 default: 5340 return (IOC_INVAL); 5341 5342 case BGE_PP_SPACE_CFG: 5343 /* 5344 * Config space 5345 */ 5346 sizemask = 8|4|2|1; 5347 mem_va = 0; 5348 maxoff = PCI_CONF_HDR_SIZE; 5349 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 5350 break; 5351 5352 case BGE_PP_SPACE_REG: 5353 /* 5354 * Memory-mapped I/O space 5355 */ 5356 sizemask = 8|4|2|1; 5357 mem_va = 0; 5358 maxoff = RIAAR_REGISTER_MAX; 5359 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 5360 break; 5361 5362 case BGE_PP_SPACE_NIC: 5363 /* 5364 * NIC on-chip memory 5365 */ 5366 sizemask = 8|4|2|1; 5367 mem_va = 0; 5368 maxoff = MWBAR_ONCHIP_MAX; 5369 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 5370 break; 5371 5372 case BGE_PP_SPACE_MII: 5373 /* 5374 * PHY's MII registers 5375 * NB: all PHY registers are two bytes, but the 5376 * addresses increment in ones (word addressing). 5377 * So we scale the address here, then undo the 5378 * transformation inside the peek/poke functions. 5379 */ 5380 ppd->pp_acc_offset *= 2; 5381 sizemask = 2; 5382 mem_va = 0; 5383 maxoff = (MII_MAXREG+1)*2; 5384 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5385 break; 5386 5387 #if BGE_SEE_IO32 5388 case BGE_PP_SPACE_SEEPROM: 5389 /* 5390 * Attached SEEPROM(s), if any. 5391 * NB: we use the high-order bits of the 'address' as 5392 * a device select to accommodate multiple SEEPROMS, 5393 * If each one is the maximum size (64kbytes), this 5394 * makes them appear contiguous. Otherwise, there may 5395 * be holes in the mapping. ENxS doesn't have any 5396 * SEEPROMs anyway ... 5397 */ 5398 sizemask = 4; 5399 mem_va = 0; 5400 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5401 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5402 break; 5403 #endif /* BGE_SEE_IO32 */ 5404 5405 #if BGE_FLASH_IO32 5406 case BGE_PP_SPACE_FLASH: 5407 /* 5408 * Attached Flash device (if any); a maximum of one device 5409 * is currently supported. But it can be up to 1MB (unlike 5410 * the 64k limit on SEEPROMs) so why would you need more ;-) 5411 */ 5412 sizemask = 4; 5413 mem_va = 0; 5414 maxoff = NVM_FLASH_ADDR_MASK; 5415 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5416 break; 5417 #endif /* BGE_FLASH_IO32 */ 5418 5419 case BGE_PP_SPACE_BGE: 5420 /* 5421 * BGE data structure! 5422 */ 5423 sizemask = 8|4|2|1; 5424 mem_va = (uintptr_t)bgep; 5425 maxoff = sizeof (*bgep); 5426 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5427 break; 5428 5429 case BGE_PP_SPACE_STATUS: 5430 case BGE_PP_SPACE_STATISTICS: 5431 case BGE_PP_SPACE_TXDESC: 5432 case BGE_PP_SPACE_TXBUFF: 5433 case BGE_PP_SPACE_RXDESC: 5434 case BGE_PP_SPACE_RXBUFF: 5435 /* 5436 * Various DMA_AREAs 5437 */ 5438 switch (ppd->pp_acc_space) { 5439 case BGE_PP_SPACE_TXDESC: 5440 areap = &bgep->tx_desc; 5441 break; 5442 case BGE_PP_SPACE_TXBUFF: 5443 areap = &bgep->tx_buff[0]; 5444 break; 5445 case BGE_PP_SPACE_RXDESC: 5446 areap = &bgep->rx_desc[0]; 5447 break; 5448 case BGE_PP_SPACE_RXBUFF: 5449 areap = &bgep->rx_buff[0]; 5450 break; 5451 case BGE_PP_SPACE_STATUS: 5452 areap = &bgep->status_block; 5453 break; 5454 case BGE_PP_SPACE_STATISTICS: 5455 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5456 areap = &bgep->statistics; 5457 break; 5458 } 5459 5460 sizemask = 8|4|2|1; 5461 mem_va = (uintptr_t)areap->mem_va; 5462 maxoff = areap->alength; 5463 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5464 break; 5465 } 5466 5467 switch (ppd->pp_acc_size) { 5468 default: 5469 return (IOC_INVAL); 5470 5471 case 8: 5472 case 4: 5473 case 2: 5474 case 1: 5475 if ((ppd->pp_acc_size & sizemask) == 0) 5476 return (IOC_INVAL); 5477 break; 5478 } 5479 5480 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5481 return (IOC_INVAL); 5482 5483 if (ppd->pp_acc_offset >= maxoff) 5484 return (IOC_INVAL); 5485 5486 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5487 return (IOC_INVAL); 5488 5489 /* 5490 * All OK - go do it! 5491 */ 5492 ppd->pp_acc_offset += mem_va; 5493 (*ppfn)(bgep, ppd); 5494 return (peek ? IOC_REPLY : IOC_ACK); 5495 } 5496 5497 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5498 struct iocblk *iocp); 5499 #pragma no_inline(bge_diag_ioctl) 5500 5501 static enum ioc_reply 5502 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5503 { 5504 ASSERT(mutex_owned(bgep->genlock)); 5505 5506 switch (cmd) { 5507 default: 5508 /* NOTREACHED */ 5509 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5510 return (IOC_INVAL); 5511 5512 case BGE_DIAG: 5513 /* 5514 * Currently a no-op 5515 */ 5516 return (IOC_ACK); 5517 5518 case BGE_PEEK: 5519 case BGE_POKE: 5520 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5521 5522 case BGE_PHY_RESET: 5523 return (IOC_RESTART_ACK); 5524 5525 case BGE_SOFT_RESET: 5526 case BGE_HARD_RESET: 5527 /* 5528 * Reset and reinitialise the 570x hardware 5529 */ 5530 bgep->bge_chip_state = BGE_CHIP_FAULT; 5531 ddi_trigger_softintr(bgep->factotum_id); 5532 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5533 return (IOC_ACK); 5534 } 5535 5536 /* NOTREACHED */ 5537 } 5538 5539 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5540 5541 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5542 struct iocblk *iocp); 5543 #pragma no_inline(bge_mii_ioctl) 5544 5545 static enum ioc_reply 5546 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5547 { 5548 struct bge_mii_rw *miirwp; 5549 5550 /* 5551 * Validate format of ioctl 5552 */ 5553 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5554 return (IOC_INVAL); 5555 if (mp->b_cont == NULL) 5556 return (IOC_INVAL); 5557 miirwp = (void *)mp->b_cont->b_rptr; 5558 5559 /* 5560 * Validate request parameters ... 5561 */ 5562 if (miirwp->mii_reg > MII_MAXREG) 5563 return (IOC_INVAL); 5564 5565 switch (cmd) { 5566 default: 5567 /* NOTREACHED */ 5568 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5569 return (IOC_INVAL); 5570 5571 case BGE_MII_READ: 5572 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5573 return (IOC_REPLY); 5574 5575 case BGE_MII_WRITE: 5576 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5577 return (IOC_ACK); 5578 } 5579 5580 /* NOTREACHED */ 5581 } 5582 5583 #if BGE_SEE_IO32 5584 5585 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5586 struct iocblk *iocp); 5587 #pragma no_inline(bge_see_ioctl) 5588 5589 static enum ioc_reply 5590 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5591 { 5592 struct bge_see_rw *seerwp; 5593 5594 /* 5595 * Validate format of ioctl 5596 */ 5597 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5598 return (IOC_INVAL); 5599 if (mp->b_cont == NULL) 5600 return (IOC_INVAL); 5601 seerwp = (void *)mp->b_cont->b_rptr; 5602 5603 /* 5604 * Validate request parameters ... 5605 */ 5606 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5607 return (IOC_INVAL); 5608 5609 switch (cmd) { 5610 default: 5611 /* NOTREACHED */ 5612 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5613 return (IOC_INVAL); 5614 5615 case BGE_SEE_READ: 5616 case BGE_SEE_WRITE: 5617 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5618 seerwp->see_addr, &seerwp->see_data); 5619 return (IOC_REPLY); 5620 } 5621 5622 /* NOTREACHED */ 5623 } 5624 5625 #endif /* BGE_SEE_IO32 */ 5626 5627 #if BGE_FLASH_IO32 5628 5629 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5630 struct iocblk *iocp); 5631 #pragma no_inline(bge_flash_ioctl) 5632 5633 static enum ioc_reply 5634 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5635 { 5636 struct bge_flash_rw *flashrwp; 5637 5638 /* 5639 * Validate format of ioctl 5640 */ 5641 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5642 return (IOC_INVAL); 5643 if (mp->b_cont == NULL) 5644 return (IOC_INVAL); 5645 flashrwp = (void *)mp->b_cont->b_rptr; 5646 5647 /* 5648 * Validate request parameters ... 5649 */ 5650 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5651 return (IOC_INVAL); 5652 5653 switch (cmd) { 5654 default: 5655 /* NOTREACHED */ 5656 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5657 return (IOC_INVAL); 5658 5659 case BGE_FLASH_READ: 5660 case BGE_FLASH_WRITE: 5661 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5662 flashrwp->flash_addr, &flashrwp->flash_data); 5663 return (IOC_REPLY); 5664 } 5665 5666 /* NOTREACHED */ 5667 } 5668 5669 #endif /* BGE_FLASH_IO32 */ 5670 5671 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5672 struct iocblk *iocp); 5673 #pragma no_inline(bge_chip_ioctl) 5674 5675 enum ioc_reply 5676 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5677 { 5678 int cmd; 5679 5680 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5681 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5682 5683 ASSERT(mutex_owned(bgep->genlock)); 5684 5685 cmd = iocp->ioc_cmd; 5686 switch (cmd) { 5687 default: 5688 /* NOTREACHED */ 5689 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5690 return (IOC_INVAL); 5691 5692 case BGE_DIAG: 5693 case BGE_PEEK: 5694 case BGE_POKE: 5695 case BGE_PHY_RESET: 5696 case BGE_SOFT_RESET: 5697 case BGE_HARD_RESET: 5698 #if BGE_DEBUGGING || BGE_DO_PPIO 5699 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5700 #else 5701 return (IOC_INVAL); 5702 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5703 5704 case BGE_MII_READ: 5705 case BGE_MII_WRITE: 5706 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5707 5708 #if BGE_SEE_IO32 5709 case BGE_SEE_READ: 5710 case BGE_SEE_WRITE: 5711 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5712 #endif /* BGE_SEE_IO32 */ 5713 5714 #if BGE_FLASH_IO32 5715 case BGE_FLASH_READ: 5716 case BGE_FLASH_WRITE: 5717 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5718 #endif /* BGE_FLASH_IO32 */ 5719 } 5720 5721 /* NOTREACHED */ 5722 } 5723 5724 /* ARGSUSED */ 5725 void 5726 bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag) 5727 { 5728 recv_ring_t *rrp = arg; 5729 bge_t *bgep = rrp->bgep; 5730 5731 mutex_enter(bgep->genlock); 5732 rrp->poll_flag = flag; 5733 #ifdef NOT_YET 5734 /* 5735 * XXX-Sunay: Since most broadcom cards support only one 5736 * interrupt but multiple rx rings, we can't disable the 5737 * physical interrupt. This need to be done via capability 5738 * negotiation depending on the NIC. 5739 */ 5740 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5741 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5742 #endif 5743 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5744 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5745 mutex_exit(bgep->genlock); 5746 } 5747 5748 #ifdef BGE_IPMI_ASF 5749 5750 uint32_t 5751 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5752 { 5753 uint32_t data; 5754 5755 #ifndef __sparc 5756 if (!bgep->asf_wordswapped) { 5757 /* a workaround word swap error */ 5758 if (addr & 4) 5759 addr = addr - 4; 5760 else 5761 addr = addr + 4; 5762 } 5763 #else 5764 if (DEVICE_5717_SERIES_CHIPSETS(bgep)) 5765 addr = LE_32(addr); 5766 #endif 5767 5768 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5769 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5770 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5771 5772 data = LE_32(data); 5773 5774 BGE_DEBUG(("bge_nic_read32($%p, 0x%x) => 0x%x", 5775 (void *)bgep, addr, data)); 5776 5777 return (data); 5778 } 5779 5780 void 5781 bge_asf_update_status(bge_t *bgep) 5782 { 5783 uint32_t event; 5784 5785 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5786 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5787 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5788 5789 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5790 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5791 } 5792 5793 5794 /* 5795 * The driver is supposed to notify ASF that the OS is still running 5796 * every three seconds, otherwise the management server may attempt 5797 * to reboot the machine. If it hasn't actually failed, this is 5798 * not a desirable result. However, this isn't running as a real-time 5799 * thread, and even if it were, it might not be able to generate the 5800 * heartbeat in a timely manner due to system load. As it isn't a 5801 * significant strain on the machine, we will set the interval to half 5802 * of the required value. 5803 */ 5804 void 5805 bge_asf_heartbeat(void *arg) 5806 { 5807 bge_t *bgep = (bge_t *)arg; 5808 5809 mutex_enter(bgep->genlock); 5810 bge_asf_update_status((bge_t *)bgep); 5811 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5812 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5813 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5814 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5815 mutex_exit(bgep->genlock); 5816 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5817 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5818 } 5819 5820 5821 void 5822 bge_asf_stop_timer(bge_t *bgep) 5823 { 5824 timeout_id_t tmp_id = 0; 5825 5826 while ((bgep->asf_timeout_id != 0) && 5827 (tmp_id != bgep->asf_timeout_id)) { 5828 tmp_id = bgep->asf_timeout_id; 5829 (void) untimeout(tmp_id); 5830 } 5831 bgep->asf_timeout_id = 0; 5832 } 5833 5834 5835 5836 /* 5837 * This function should be placed at the earliest position of bge_attach(). 5838 */ 5839 void 5840 bge_asf_get_config(bge_t *bgep) 5841 { 5842 uint32_t nicsig; 5843 uint32_t niccfg; 5844 5845 bgep->asf_enabled = B_FALSE; 5846 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5847 if (nicsig == BGE_NIC_DATA_SIG) { 5848 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5849 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5850 /* 5851 * Here, we don't consider BAXTER, because BGE haven't 5852 * supported BAXTER (that is 5752). Also, as I know, 5853 * BAXTER doesn't support ASF feature. 5854 */ 5855 bgep->asf_enabled = B_TRUE; 5856 else 5857 bgep->asf_enabled = B_FALSE; 5858 } else 5859 bgep->asf_enabled = B_FALSE; 5860 } 5861 5862 5863 void 5864 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5865 { 5866 uint32_t tries; 5867 uint32_t event; 5868 5869 ASSERT(bgep->asf_enabled); 5870 5871 /* Issues "pause firmware" command and wait for ACK */ 5872 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5873 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5874 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5875 5876 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5877 tries = 0; 5878 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5879 drv_usecwait(1); 5880 tries ++; 5881 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5882 } 5883 5884 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5885 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5886 5887 if (bgep->asf_newhandshake) { 5888 switch (mode) { 5889 case BGE_INIT_RESET: 5890 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5891 BGE_DRV_STATE_START); 5892 break; 5893 case BGE_SHUTDOWN_RESET: 5894 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5895 BGE_DRV_STATE_UNLOAD); 5896 break; 5897 case BGE_SUSPEND_RESET: 5898 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5899 BGE_DRV_STATE_SUSPEND); 5900 break; 5901 default: 5902 break; 5903 } 5904 } 5905 } 5906 5907 5908 void 5909 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5910 { 5911 switch (mode) { 5912 case BGE_INIT_RESET: 5913 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5914 BGE_DRV_STATE_START); 5915 break; 5916 case BGE_SHUTDOWN_RESET: 5917 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5918 BGE_DRV_STATE_UNLOAD); 5919 break; 5920 case BGE_SUSPEND_RESET: 5921 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5922 BGE_DRV_STATE_SUSPEND); 5923 break; 5924 default: 5925 break; 5926 } 5927 } 5928 5929 5930 void 5931 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5932 { 5933 switch (mode) { 5934 case BGE_INIT_RESET: 5935 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5936 BGE_DRV_STATE_START_DONE); 5937 break; 5938 case BGE_SHUTDOWN_RESET: 5939 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5940 BGE_DRV_STATE_UNLOAD_DONE); 5941 break; 5942 default: 5943 break; 5944 } 5945 } 5946 5947 #endif /* BGE_IPMI_ASF */ 5948