1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "bge_impl.h" 30 31 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 32 33 /* 34 * Future features ... ? 35 */ 36 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 37 #define BGE_IND_IO32 1 /* indirect access code */ 38 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 39 #define BGE_FLASH_IO32 1 /* FLASH access code */ 40 41 /* 42 * BGE MSI tunable: 43 * 44 * By default MSI is enabled on all supported platforms but it is disabled 45 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 46 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 47 */ 48 #if defined(__sparc) 49 boolean_t bge_enable_msi = B_TRUE; 50 #else 51 boolean_t bge_enable_msi = B_FALSE; 52 #endif 53 54 /* 55 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 56 */ 57 boolean_t bge_relaxed_ordering = B_TRUE; 58 59 /* 60 * Property names 61 */ 62 static char knownids_propname[] = "bge-known-subsystems"; 63 64 /* 65 * Patchable globals: 66 * 67 * bge_autorecover 68 * Enables/disables automatic recovery after fault detection 69 * 70 * bge_mlcr_default 71 * Value to program into the MLCR; controls the chip's GPIO pins 72 * 73 * bge_dma_{rd,wr}prio 74 * Relative priorities of DMA reads & DMA writes respectively. 75 * These may each be patched to any value 0-3. Equal values 76 * will give "fair" (round-robin) arbitration for PCI access. 77 * Unequal values will give one or the other function priority. 78 * 79 * bge_dma_rwctrl 80 * Value to put in the Read/Write DMA control register. See 81 * the Broadcom PRM for things you can fiddle with in this 82 * register ... 83 * 84 * bge_{tx,rx}_{count,ticks}_{norm,intr} 85 * Send/receive interrupt coalescing parameters. Counts are 86 * #s of descriptors, ticks are in microseconds. *norm* values 87 * apply between status updates/interrupts; the *intr* values 88 * refer to the 'during-interrupt' versions - see the PRM. 89 * 90 * NOTE: these values have been determined by measurement. They 91 * differ significantly from the values recommended in the PRM. 92 */ 93 static uint32_t bge_autorecover = 1; 94 static uint32_t bge_mlcr_default = MLCR_DEFAULT; 95 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 96 97 static uint32_t bge_dma_rdprio = 1; 98 static uint32_t bge_dma_wrprio = 0; 99 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 100 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 101 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 102 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 103 104 uint32_t bge_rx_ticks_norm = 128; 105 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 106 uint32_t bge_rx_count_norm = 8; 107 uint32_t bge_tx_count_norm = 128; 108 109 static uint32_t bge_rx_ticks_intr = 128; 110 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 111 static uint32_t bge_rx_count_intr = 2; 112 static uint32_t bge_tx_count_intr = 0; 113 114 /* 115 * Memory pool configuration parameters. 116 * 117 * These are generally specific to each member of the chip family, since 118 * each one may have a different memory size/configuration. 119 * 120 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 121 * the driver from programming the various registers; instead they are left 122 * at their hardware defaults. This is the preferred option for later chips 123 * (5705+), whereas the older chips *required* these registers to be set, 124 * since the h/w default was 0 ;-( 125 */ 126 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 127 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 128 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 129 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 130 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 131 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 132 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 133 static uint32_t bge_mbuf_pool_len_5721 = 0; 134 135 /* 136 * Various high and low water marks, thresholds, etc ... 137 * 138 * Note: these are taken from revision 7 of the PRM, and some are different 139 * from both the values in earlier PRMs *and* those determined experimentally 140 * and used in earlier versions of this driver ... 141 */ 142 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 143 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 144 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 145 146 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 147 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 148 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 149 150 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 151 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 152 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 153 154 static uint32_t bge_watchdog_count = 1 << 16; 155 static uint16_t bge_dma_miss_limit = 20; 156 157 static uint32_t bge_stop_start_on_sync = 0; 158 159 boolean_t bge_jumbo_enable = B_TRUE; 160 static uint32_t bge_default_jumbo_size = BGE_JUMBO_BUFF_SIZE; 161 162 /* 163 * bge_intr_max_loop controls the maximum loop number within bge_intr. 164 * When loading NIC with heavy network traffic, it is useful. 165 * Increasing this value could have positive effect to throughput, 166 * but it might also increase ticks of a bge ISR stick on CPU, which might 167 * lead to bad UI interactive experience. So tune this with caution. 168 */ 169 static int bge_intr_max_loop = 1; 170 171 /* 172 * ========== Low-level chip & ring buffer manipulation ========== 173 */ 174 175 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 176 177 178 /* 179 * Config space read-modify-write routines 180 */ 181 182 #if BGE_CFG_IO8 183 184 /* 185 * 8- and 16-bit set/clr operations are not used; all the config registers 186 * that we need to do bit-twiddling on are 32 bits wide. I'll leave the 187 * code here, though, in case we ever find that we do want it after all ... 188 */ 189 190 static void bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 191 #pragma inline(bge_cfg_set8) 192 193 static void 194 bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 195 { 196 uint8_t regval; 197 198 BGE_TRACE(("bge_cfg_set8($%p, 0x%lx, 0x%x)", 199 (void *)bgep, regno, bits)); 200 201 regval = pci_config_get8(bgep->cfg_handle, regno); 202 203 BGE_DEBUG(("bge_cfg_set8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 204 (void *)bgep, regno, bits, regval, regval | bits)); 205 206 regval |= bits; 207 pci_config_put8(bgep->cfg_handle, regno, regval); 208 } 209 210 static void bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 211 #pragma inline(bge_cfg_clr8) 212 213 static void 214 bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 215 { 216 uint8_t regval; 217 218 BGE_TRACE(("bge_cfg_clr8($%p, 0x%lx, 0x%x)", 219 (void *)bgep, regno, bits)); 220 221 regval = pci_config_get8(bgep->cfg_handle, regno); 222 223 BGE_DEBUG(("bge_cfg_clr8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 224 (void *)bgep, regno, bits, regval, regval & ~bits)); 225 226 regval &= ~bits; 227 pci_config_put8(bgep->cfg_handle, regno, regval); 228 } 229 230 static void bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 231 #pragma inline(bge_cfg_set16) 232 233 static void 234 bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 235 { 236 uint16_t regval; 237 238 BGE_TRACE(("bge_cfg_set16($%p, 0x%lx, 0x%x)", 239 (void *)bgep, regno, bits)); 240 241 regval = pci_config_get16(bgep->cfg_handle, regno); 242 243 BGE_DEBUG(("bge_cfg_set16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 244 (void *)bgep, regno, bits, regval, regval | bits)); 245 246 regval |= bits; 247 pci_config_put16(bgep->cfg_handle, regno, regval); 248 } 249 250 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 251 #pragma inline(bge_cfg_clr16) 252 253 static void 254 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 255 { 256 uint16_t regval; 257 258 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 259 (void *)bgep, regno, bits)); 260 261 regval = pci_config_get16(bgep->cfg_handle, regno); 262 263 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 264 (void *)bgep, regno, bits, regval, regval & ~bits)); 265 266 regval &= ~bits; 267 pci_config_put16(bgep->cfg_handle, regno, regval); 268 } 269 270 #endif /* BGE_CFG_IO8 */ 271 272 static void bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 273 #pragma inline(bge_cfg_set32) 274 275 static void 276 bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 277 { 278 uint32_t regval; 279 280 BGE_TRACE(("bge_cfg_set32($%p, 0x%lx, 0x%x)", 281 (void *)bgep, regno, bits)); 282 283 regval = pci_config_get32(bgep->cfg_handle, regno); 284 285 BGE_DEBUG(("bge_cfg_set32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 286 (void *)bgep, regno, bits, regval, regval | bits)); 287 288 regval |= bits; 289 pci_config_put32(bgep->cfg_handle, regno, regval); 290 } 291 292 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 293 #pragma inline(bge_cfg_clr32) 294 295 static void 296 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 297 { 298 uint32_t regval; 299 300 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 301 (void *)bgep, regno, bits)); 302 303 regval = pci_config_get32(bgep->cfg_handle, regno); 304 305 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 306 (void *)bgep, regno, bits, regval, regval & ~bits)); 307 308 regval &= ~bits; 309 pci_config_put32(bgep->cfg_handle, regno, regval); 310 } 311 312 #if BGE_IND_IO32 313 314 /* 315 * Indirect access to registers & RISC scratchpads, using config space 316 * accesses only. 317 * 318 * This isn't currently used, but someday we might want to use it for 319 * restoring the Subsystem Device/Vendor registers (which aren't directly 320 * writable in Config Space), or for downloading firmware into the RISCs 321 * 322 * In any case there are endian issues to be resolved before this code is 323 * enabled; the bizarre way that bytes get twisted by this chip AND by 324 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 325 * it's been thoroughly tested for all access sizes on all supported 326 * architectures (SPARC *and* x86!). 327 */ 328 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 329 #pragma inline(bge_ind_get32) 330 331 uint32_t 332 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 333 { 334 uint32_t val; 335 336 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 337 338 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 339 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 340 341 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 342 (void *)bgep, regno, val)); 343 344 val = LE_32(val); 345 346 return (val); 347 } 348 349 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 350 #pragma inline(bge_ind_put32) 351 352 void 353 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 354 { 355 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 356 (void *)bgep, regno, val)); 357 358 val = LE_32(val); 359 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 360 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 361 } 362 363 #endif /* BGE_IND_IO32 */ 364 365 #if BGE_DEBUGGING 366 367 static void bge_pci_check(bge_t *bgep); 368 #pragma no_inline(bge_pci_check) 369 370 static void 371 bge_pci_check(bge_t *bgep) 372 { 373 uint16_t pcistatus; 374 375 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 376 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 377 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 378 (void *)bgep, pcistatus)); 379 } 380 381 #endif /* BGE_DEBUGGING */ 382 383 /* 384 * Perform first-stage chip (re-)initialisation, using only config-space 385 * accesses: 386 * 387 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 388 * returning the data in the structure pointed to by <idp>. 389 * + Configure the target-mode endianness (swap) options. 390 * + Disable interrupts and enable Memory Space accesses. 391 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 392 * 393 * This sequence is adapted from Broadcom document 570X-PG102-R, 394 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 395 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 396 * 397 * This function MUST be called before any non-config-space accesses 398 * are made; on this first call <enable_dma> is B_FALSE, and it 399 * effectively performs steps 3-1(!) of the initialisation sequence 400 * (the rest are not required but should be harmless). 401 * 402 * It MUST also be called after a chip reset, as this disables 403 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 404 * it is effectively performing steps 6-8. 405 */ 406 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 407 #pragma no_inline(bge_chip_cfg_init) 408 409 void 410 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 411 { 412 ddi_acc_handle_t handle; 413 uint16_t command; 414 uint32_t mhcr; 415 uint16_t value16; 416 int i; 417 418 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 419 (void *)bgep, (void *)cidp, enable_dma)); 420 421 /* 422 * Step 3: save PCI cache line size and subsystem vendor ID 423 * 424 * Read all the config-space registers that characterise the 425 * chip, specifically vendor/device/revision/subsystem vendor 426 * and subsystem device id. We expect (but don't check) that 427 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 428 * 429 * Also save all bus-transaction related registers (cache-line 430 * size, bus-grant/latency parameters, etc). Some of these are 431 * cleared by reset, so we'll have to restore them later. This 432 * comes from the Broadcom document 570X-PG102-R ... 433 * 434 * Note: Broadcom document 570X-PG102-R seems to be in error 435 * here w.r.t. the offsets of the Subsystem Vendor ID and 436 * Subsystem (Device) ID registers, which are the opposite way 437 * round according to the PCI standard. For good measure, we 438 * save/restore both anyway. 439 */ 440 handle = bgep->cfg_handle; 441 442 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 443 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 444 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 445 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 446 447 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 448 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 449 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 450 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 451 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 452 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 453 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 454 455 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 456 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 457 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 458 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 459 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 460 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 461 cidp->vendor, cidp->device, cidp->revision)); 462 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 463 cidp->subven, cidp->subdev, cidp->asic_rev)); 464 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 465 cidp->clsize, cidp->latency, cidp->command)); 466 467 /* 468 * Step 2 (also step 6): disable and clear interrupts. 469 * Steps 11-13: configure PIO endianness options, and enable 470 * indirect register access. We'll also select any other 471 * options controlled by the MHCR (e.g. tagged status, mask 472 * interrupt mode) at this stage ... 473 * 474 * Note: internally, the chip is 64-bit and BIG-endian, but 475 * since it talks to the host over a (LITTLE-endian) PCI bus, 476 * it normally swaps bytes around at the PCI interface. 477 * However, the PCI host bridge on SPARC systems normally 478 * swaps the byte lanes around too, since SPARCs are also 479 * BIG-endian. So it turns out that on SPARC, the right 480 * option is to tell the chip to swap (and the host bridge 481 * will swap back again), whereas on x86 we ask the chip 482 * NOT to swap, so the natural little-endianness of the 483 * PCI bus is assumed. Then the only thing that doesn't 484 * automatically work right is access to an 8-byte register 485 * by a little-endian host; but we don't want to set the 486 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 487 * accesses don't go where expected ;-( So we live with 488 * that, and perform word-swaps in software in the few cases 489 * where a chip register is defined as an 8-byte value -- 490 * see the code below for details ... 491 * 492 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 493 * very clear in the register description in the PRM, but 494 * Broadcom document 570X-PG104-R page 248 explains a little 495 * more (under "Broadcom Mask Mode"). The bit changes the way 496 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 497 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 498 * way as the 5700 did, which isn't very convenient. Setting 499 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 500 * bit do just what its name says -- MASK the PCI #INTA output 501 * (i.e. deassert the signal at the pin) leaving all internal 502 * state unchanged. This is much more convenient for our 503 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 504 * 505 * Note: the inconvenient semantics of the interrupt mailbox 506 * (nonzero disables and acknowledges/clears the interrupt, 507 * zero enables AND CLEARS it) would make race conditions 508 * likely in the interrupt handler: 509 * 510 * (1) acknowledge & disable interrupts 511 * (2) while (more to do) 512 * process packets 513 * (3) enable interrupts -- also clears pending 514 * 515 * If the chip received more packets and internally generated 516 * an interrupt between the check at (2) and the mbox write 517 * at (3), this interrupt would be lost :-( 518 * 519 * The best way to avoid this is to use TAGGED STATUS mode, 520 * where the chip includes a unique tag in each status block 521 * update, and the host, when re-enabling interrupts, passes 522 * the last tag it saw back to the chip; then the chip can 523 * see whether the host is truly up to date, and regenerate 524 * its interrupt if not. 525 */ 526 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 527 MHCR_ENABLE_TAGGED_STATUS_MODE | 528 MHCR_MASK_INTERRUPT_MODE | 529 MHCR_CLEAR_INTERRUPT_INTA; 530 531 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 532 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 533 534 #ifdef _BIG_ENDIAN 535 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 536 #endif /* _BIG_ENDIAN */ 537 538 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 539 540 #ifdef BGE_IPMI_ASF 541 bgep->asf_wordswapped = B_FALSE; 542 #endif 543 /* 544 * Step 1 (also step 7): Enable PCI Memory Space accesses 545 * Disable Memory Write/Invalidate 546 * Enable or disable Bus Mastering 547 * 548 * Note that all other bits are taken from the original value saved 549 * the first time through here, rather than from the current register 550 * value, 'cos that will have been cleared by a soft RESET since. 551 * In this way we preserve the OBP/nexus-parent's preferred settings 552 * of the parity-error and system-error enable bits across multiple 553 * chip RESETs. 554 */ 555 command = bgep->chipid.command | PCI_COMM_MAE; 556 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 557 if (enable_dma) 558 command |= PCI_COMM_ME; 559 /* 560 * on BCM5714 revision A0, false parity error gets generated 561 * due to a logic bug. Provide a workaround by disabling parity 562 * error. 563 */ 564 if (((cidp->device == DEVICE_ID_5714C) || 565 (cidp->device == DEVICE_ID_5714S)) && 566 (cidp->revision == REVISION_ID_5714_A0)) { 567 command &= ~PCI_COMM_PARITY_DETECT; 568 } 569 pci_config_put16(handle, PCI_CONF_COMM, command); 570 571 /* 572 * On some PCI-E device, there were instances when 573 * the device was still link training. 574 */ 575 if (bgep->chipid.pci_type == BGE_PCI_E) { 576 i = 0; 577 value16 = pci_config_get16(handle, PCI_CONF_COMM); 578 while ((value16 != command) && (i < 100)) { 579 drv_usecwait(200); 580 value16 = pci_config_get16(handle, PCI_CONF_COMM); 581 ++i; 582 } 583 } 584 585 /* 586 * Clear any remaining error status bits 587 */ 588 pci_config_put16(handle, PCI_CONF_STAT, ~0); 589 590 /* 591 * Do following if and only if the device is NOT BCM5714C OR 592 * BCM5715C 593 */ 594 if (!((cidp->device == DEVICE_ID_5714C) || 595 (cidp->device == DEVICE_ID_5715C))) { 596 /* 597 * Make sure these indirect-access registers are sane 598 * rather than random after power-up or reset 599 */ 600 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 601 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 602 } 603 /* 604 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 605 */ 606 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 607 608 if (cidp->pci_type == BGE_PCI_E) 609 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 610 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 611 } 612 613 #ifdef __amd64 614 /* 615 * Distinguish CPU types 616 * 617 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 618 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 619 * for PCI-Express based network interface card. This is the work-around 620 * for those nics. 621 */ 622 static boolean_t bge_get_em64t_type(void); 623 #pragma inline(bge_get_em64t_type) 624 625 static boolean_t 626 bge_get_em64t_type(void) 627 { 628 629 return (x86_vendor == X86_VENDOR_Intel); 630 } 631 #endif 632 633 /* 634 * Operating register get/set access routines 635 */ 636 637 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 638 #pragma inline(bge_reg_get32) 639 640 uint32_t 641 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 642 { 643 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 644 (void *)bgep, regno)); 645 646 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 647 } 648 649 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 650 #pragma inline(bge_reg_put32) 651 652 void 653 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 654 { 655 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 656 (void *)bgep, regno, data)); 657 658 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 659 BGE_PCICHK(bgep); 660 } 661 662 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 663 #pragma inline(bge_reg_set32) 664 665 void 666 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 667 { 668 uint32_t regval; 669 670 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 671 (void *)bgep, regno, bits)); 672 673 regval = bge_reg_get32(bgep, regno); 674 regval |= bits; 675 bge_reg_put32(bgep, regno, regval); 676 } 677 678 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 679 #pragma inline(bge_reg_clr32) 680 681 void 682 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 683 { 684 uint32_t regval; 685 686 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 687 (void *)bgep, regno, bits)); 688 689 regval = bge_reg_get32(bgep, regno); 690 regval &= ~bits; 691 bge_reg_put32(bgep, regno, regval); 692 } 693 694 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 695 #pragma inline(bge_reg_get64) 696 697 static uint64_t 698 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 699 { 700 uint64_t regval; 701 702 #ifdef __amd64 703 if (bge_get_em64t_type()) { 704 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 705 regval <<= 32; 706 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 707 } else { 708 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 709 } 710 #else 711 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 712 #endif 713 714 #ifdef _LITTLE_ENDIAN 715 regval = (regval >> 32) | (regval << 32); 716 #endif /* _LITTLE_ENDIAN */ 717 718 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 719 (void *)bgep, regno, regval)); 720 721 return (regval); 722 } 723 724 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 725 #pragma inline(bge_reg_put64) 726 727 static void 728 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 729 { 730 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 731 (void *)bgep, regno, data)); 732 733 #ifdef _LITTLE_ENDIAN 734 data = ((data >> 32) | (data << 32)); 735 #endif /* _LITTLE_ENDIAN */ 736 737 #ifdef __amd64 738 if (bge_get_em64t_type()) { 739 ddi_put32(bgep->io_handle, 740 PIO_ADDR(bgep, regno), (uint32_t)data); 741 BGE_PCICHK(bgep); 742 ddi_put32(bgep->io_handle, 743 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 744 745 } else { 746 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 747 } 748 #else 749 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 750 #endif 751 752 BGE_PCICHK(bgep); 753 } 754 755 /* 756 * The DDI doesn't provide get/put functions for 128 bit data 757 * so we put RCBs out as two 64-bit chunks instead. 758 */ 759 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 760 #pragma inline(bge_reg_putrcb) 761 762 static void 763 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 764 { 765 uint64_t *p; 766 767 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 768 (void *)bgep, addr, rcbp->host_ring_addr, 769 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 770 771 ASSERT((addr % sizeof (*rcbp)) == 0); 772 773 p = (void *)rcbp; 774 bge_reg_put64(bgep, addr, *p++); 775 bge_reg_put64(bgep, addr+8, *p); 776 } 777 778 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 779 #pragma inline(bge_mbx_put) 780 781 void 782 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 783 { 784 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 785 (void *)bgep, regno, data)); 786 787 /* 788 * Mailbox registers are nominally 64 bits on the 5701, but 789 * the MSW isn't used. On the 5703, they're only 32 bits 790 * anyway. So here we just write the lower(!) 32 bits - 791 * remembering that the chip is big-endian, even though the 792 * PCI bus is little-endian ... 793 */ 794 #ifdef _BIG_ENDIAN 795 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 796 #else 797 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 798 #endif /* _BIG_ENDIAN */ 799 BGE_PCICHK(bgep); 800 } 801 802 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 803 #pragma inline(bge_mbx_get) 804 805 uint32_t 806 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 807 { 808 uint32_t val32; 809 810 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 811 (void *)bgep, regno)); 812 813 #ifdef _BIG_ENDIAN 814 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 815 #else 816 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 817 #endif /* _BIG_ENDIAN */ 818 BGE_PCICHK(bgep); 819 820 return (val32); 821 } 822 823 824 #if BGE_DEBUGGING 825 826 void bge_led_mark(bge_t *bgep); 827 #pragma no_inline(bge_led_mark) 828 829 void 830 bge_led_mark(bge_t *bgep) 831 { 832 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 833 LED_CONTROL_1000MBPS_LED | 834 LED_CONTROL_100MBPS_LED | 835 LED_CONTROL_10MBPS_LED; 836 837 /* 838 * Blink all three LINK LEDs on simultaneously, then all off, 839 * then restore to automatic hardware control. This is used 840 * in laboratory testing to trigger a logic analyser or scope. 841 */ 842 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 843 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 844 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 845 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 846 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 847 } 848 849 #endif /* BGE_DEBUGGING */ 850 851 /* 852 * NIC on-chip memory access routines 853 * 854 * Only 32K of NIC memory is visible at a time, controlled by the 855 * Memory Window Base Address Register (in PCI config space). Once 856 * this is set, the 32K region of NIC-local memory that it refers 857 * to can be directly addressed in the upper 32K of the 64K of PCI 858 * memory space used for the device. 859 */ 860 861 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 862 #pragma inline(bge_nic_setwin) 863 864 static void 865 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 866 { 867 chip_id_t *cidp; 868 869 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 870 (void *)bgep, base)); 871 872 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 873 874 /* 875 * Don't do repeated zero data writes, 876 * if the device is BCM5714C/15C. 877 */ 878 cidp = &bgep->chipid; 879 if ((cidp->device == DEVICE_ID_5714C) || 880 (cidp->device == DEVICE_ID_5715C)) { 881 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 882 return; 883 /* Adjust lastWriteZeroData */ 884 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 885 B_TRUE : B_FALSE); 886 } 887 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 888 } 889 890 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 891 #pragma inline(bge_nic_get32) 892 893 static uint32_t 894 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 895 { 896 uint32_t data; 897 898 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 899 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 900 /* workaround for word swap error */ 901 if (addr & 4) 902 addr = addr - 4; 903 else 904 addr = addr + 4; 905 } 906 #endif 907 908 #ifdef __sparc 909 data = bge_nic_read32(bgep, addr); 910 #else 911 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 912 addr &= MWBAR_GRANULE_MASK; 913 addr += NIC_MEM_WINDOW_OFFSET; 914 915 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 916 #endif 917 918 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 919 (void *)bgep, addr, data)); 920 921 return (data); 922 } 923 924 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 925 #pragma inline(bge_nic_put32) 926 927 void 928 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 929 { 930 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 931 (void *)bgep, addr, data)); 932 933 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 934 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 935 /* workaround for word swap error */ 936 if (addr & 4) 937 addr = addr - 4; 938 else 939 addr = addr + 4; 940 } 941 #endif 942 943 #ifdef __sparc 944 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 945 data = LE_32(data); 946 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 947 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 948 #else 949 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 950 addr &= MWBAR_GRANULE_MASK; 951 addr += NIC_MEM_WINDOW_OFFSET; 952 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 953 BGE_PCICHK(bgep); 954 #endif 955 } 956 957 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 958 #pragma inline(bge_nic_get64) 959 960 static uint64_t 961 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 962 { 963 uint64_t data; 964 965 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 966 addr &= MWBAR_GRANULE_MASK; 967 addr += NIC_MEM_WINDOW_OFFSET; 968 969 #ifdef __amd64 970 if (bge_get_em64t_type()) { 971 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 972 data <<= 32; 973 data |= ddi_get32(bgep->io_handle, 974 PIO_ADDR(bgep, addr + 4)); 975 } else { 976 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 977 } 978 #else 979 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 980 #endif 981 982 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 983 (void *)bgep, addr, data)); 984 985 return (data); 986 } 987 988 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 989 #pragma inline(bge_nic_put64) 990 991 static void 992 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 993 { 994 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 995 (void *)bgep, addr, data)); 996 997 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 998 addr &= MWBAR_GRANULE_MASK; 999 addr += NIC_MEM_WINDOW_OFFSET; 1000 1001 #ifdef __amd64 1002 if (bge_get_em64t_type()) { 1003 ddi_put32(bgep->io_handle, 1004 PIO_ADDR(bgep, addr), (uint32_t)data); 1005 BGE_PCICHK(bgep); 1006 ddi_put32(bgep->io_handle, 1007 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 1008 } else { 1009 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 1010 } 1011 #else 1012 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 1013 #endif 1014 1015 BGE_PCICHK(bgep); 1016 } 1017 1018 /* 1019 * The DDI doesn't provide get/put functions for 128 bit data 1020 * so we put RCBs out as two 64-bit chunks instead. 1021 */ 1022 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 1023 #pragma inline(bge_nic_putrcb) 1024 1025 static void 1026 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 1027 { 1028 uint64_t *p; 1029 1030 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 1031 (void *)bgep, addr, rcbp->host_ring_addr, 1032 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 1033 1034 ASSERT((addr % sizeof (*rcbp)) == 0); 1035 1036 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1037 addr &= MWBAR_GRANULE_MASK; 1038 addr += NIC_MEM_WINDOW_OFFSET; 1039 1040 p = (void *)rcbp; 1041 #ifdef __amd64 1042 if (bge_get_em64t_type()) { 1043 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1044 (uint32_t)(*p)); 1045 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1046 (uint32_t)(*p >> 32)); 1047 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1048 (uint32_t)(*(p + 1))); 1049 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1050 (uint32_t)(*p >> 32)); 1051 1052 } else { 1053 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1054 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1055 } 1056 #else 1057 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1058 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1059 #endif 1060 1061 BGE_PCICHK(bgep); 1062 } 1063 1064 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1065 #pragma inline(bge_nic_zero) 1066 1067 static void 1068 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1069 { 1070 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1071 (void *)bgep, addr, nbytes)); 1072 1073 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1074 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1075 1076 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1077 addr &= MWBAR_GRANULE_MASK; 1078 addr += NIC_MEM_WINDOW_OFFSET; 1079 1080 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1081 nbytes, 1, DDI_DATA_SZ08_ACC); 1082 BGE_PCICHK(bgep); 1083 } 1084 1085 /* 1086 * MII (PHY) register get/set access routines 1087 * 1088 * These use the chip's MII auto-access method, controlled by the 1089 * MII Communication register at 0x044c, so the CPU doesn't have 1090 * to fiddle with the individual bits. 1091 */ 1092 1093 #undef BGE_DBG 1094 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1095 1096 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1097 uint16_t data, uint32_t cmd); 1098 #pragma no_inline(bge_mii_access) 1099 1100 static uint16_t 1101 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1102 { 1103 uint32_t timeout; 1104 uint32_t regval1; 1105 uint32_t regval2; 1106 1107 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1108 (void *)bgep, regno, data, cmd)); 1109 1110 ASSERT(mutex_owned(bgep->genlock)); 1111 1112 /* 1113 * Assemble the command ... 1114 */ 1115 cmd |= data << MI_COMMS_DATA_SHIFT; 1116 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1117 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1118 cmd |= MI_COMMS_START; 1119 1120 /* 1121 * Wait for any command already in progress ... 1122 * 1123 * Note: this *shouldn't* ever find that there is a command 1124 * in progress, because we already hold the <genlock> mutex. 1125 * Nonetheless, we have sometimes seen the MI_COMMS_START 1126 * bit set here -- it seems that the chip can initiate MII 1127 * accesses internally, even with polling OFF. 1128 */ 1129 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1130 for (timeout = 100; ; ) { 1131 if ((regval2 & MI_COMMS_START) == 0) { 1132 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1133 break; 1134 } 1135 if (--timeout == 0) 1136 break; 1137 drv_usecwait(10); 1138 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1139 } 1140 1141 if (timeout == 0) 1142 return ((uint16_t)~0u); 1143 1144 if (timeout != 100) 1145 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1146 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1147 cmd, 10*(100-timeout), regval1, regval2)); 1148 1149 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1150 for (timeout = 1000; ; ) { 1151 if ((regval1 & MI_COMMS_START) == 0) 1152 break; 1153 if (--timeout == 0) 1154 break; 1155 drv_usecwait(10); 1156 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1157 } 1158 1159 /* 1160 * Drop out early if the READ FAILED bit is set -- this chip 1161 * could be a 5703/4S, with a SerDes instead of a PHY! 1162 */ 1163 if (regval2 & MI_COMMS_READ_FAILED) 1164 return ((uint16_t)~0u); 1165 1166 if (timeout == 0) 1167 return ((uint16_t)~0u); 1168 1169 /* 1170 * The PRM says to wait 5us after seeing the START bit clear 1171 * and then re-read the register to get the final value of the 1172 * data field, in order to avoid a race condition where the 1173 * START bit is clear but the data field isn't yet valid. 1174 * 1175 * Note: we don't actually seem to be encounter this race; 1176 * except when the START bit is seen set again (see below), 1177 * the data field doesn't change during this 5us interval. 1178 */ 1179 drv_usecwait(5); 1180 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1181 1182 /* 1183 * Unfortunately, when following the PRMs instructions above, 1184 * we have occasionally seen the START bit set again(!) in the 1185 * value read after the 5us delay. This seems to be due to the 1186 * chip autonomously starting another MII access internally. 1187 * In such cases, the command/data/etc fields relate to the 1188 * internal command, rather than the one that we thought had 1189 * just finished. So in this case, we fall back to returning 1190 * the data from the original read that showed START clear. 1191 */ 1192 if (regval2 & MI_COMMS_START) { 1193 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1194 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1195 cmd, regval1, regval2)); 1196 regval2 = regval1; 1197 } 1198 1199 if (regval2 & MI_COMMS_START) 1200 return ((uint16_t)~0u); 1201 1202 if (regval2 & MI_COMMS_READ_FAILED) 1203 return ((uint16_t)~0u); 1204 1205 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1206 } 1207 1208 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1209 #pragma no_inline(bge_mii_get16) 1210 1211 uint16_t 1212 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1213 { 1214 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1215 (void *)bgep, regno)); 1216 1217 ASSERT(mutex_owned(bgep->genlock)); 1218 1219 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1220 } 1221 1222 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1223 #pragma no_inline(bge_mii_put16) 1224 1225 void 1226 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1227 { 1228 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1229 (void *)bgep, regno, data)); 1230 1231 ASSERT(mutex_owned(bgep->genlock)); 1232 1233 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1234 } 1235 1236 #undef BGE_DBG 1237 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1238 1239 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1240 1241 /* 1242 * Basic SEEPROM get/set access routine 1243 * 1244 * This uses the chip's SEEPROM auto-access method, controlled by the 1245 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1246 * doesn't have to fiddle with the individual bits. 1247 * 1248 * The caller should hold <genlock> and *also* have already acquired 1249 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1250 * 1251 * Return value: 1252 * 0 on success, 1253 * ENODATA on access timeout (maybe retryable: device may just be busy) 1254 * EPROTO on other h/w or s/w errors. 1255 * 1256 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1257 * from a (successful) SEEPROM_ACCESS_READ. 1258 */ 1259 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1260 uint32_t *dp); 1261 #pragma no_inline(bge_seeprom_access) 1262 1263 static int 1264 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1265 { 1266 uint32_t tries; 1267 uint32_t regval; 1268 1269 ASSERT(mutex_owned(bgep->genlock)); 1270 1271 /* 1272 * On the newer chips that support both SEEPROM & Flash, we need 1273 * to specifically enable SEEPROM access (Flash is the default). 1274 * On older chips, we don't; SEEPROM is the only NVtype supported, 1275 * and the NVM control registers don't exist ... 1276 */ 1277 switch (bgep->chipid.nvtype) { 1278 case BGE_NVTYPE_NONE: 1279 case BGE_NVTYPE_UNKNOWN: 1280 _NOTE(NOTREACHED) 1281 case BGE_NVTYPE_SEEPROM: 1282 break; 1283 1284 case BGE_NVTYPE_LEGACY_SEEPROM: 1285 case BGE_NVTYPE_UNBUFFERED_FLASH: 1286 case BGE_NVTYPE_BUFFERED_FLASH: 1287 default: 1288 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1289 NVM_CFG1_LEGACY_SEEPROM_MODE); 1290 break; 1291 } 1292 1293 /* 1294 * Check there's no command in progress. 1295 * 1296 * Note: this *shouldn't* ever find that there is a command 1297 * in progress, because we already hold the <genlock> mutex. 1298 * Also, to ensure we don't have a conflict with the chip's 1299 * internal firmware or a process accessing the same (shared) 1300 * SEEPROM through the other port of a 5704, we've already 1301 * been through the "software arbitration" protocol. 1302 * So this is just a final consistency check: we shouldn't 1303 * see EITHER the START bit (command started but not complete) 1304 * OR the COMPLETE bit (command completed but not cleared). 1305 */ 1306 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1307 if (regval & SEEPROM_ACCESS_START) 1308 return (EPROTO); 1309 if (regval & SEEPROM_ACCESS_COMPLETE) 1310 return (EPROTO); 1311 1312 /* 1313 * Assemble the command ... 1314 */ 1315 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1316 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1317 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1318 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1319 cmd |= SEEPROM_ACCESS_START; 1320 cmd |= SEEPROM_ACCESS_COMPLETE; 1321 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1322 1323 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1324 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1325 1326 /* 1327 * By observation, a successful access takes ~20us on a 5703/4, 1328 * but apparently much longer (up to 1000us) on the obsolescent 1329 * BCM5700/BCM5701. We want to be sure we don't get any false 1330 * timeouts here; but OTOH, we don't want a bogus access to lock 1331 * out interrupts for longer than necessary. So we'll allow up 1332 * to 1000us ... 1333 */ 1334 for (tries = 0; tries < 1000; ++tries) { 1335 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1336 if (regval & SEEPROM_ACCESS_COMPLETE) 1337 break; 1338 drv_usecwait(1); 1339 } 1340 1341 if (regval & SEEPROM_ACCESS_COMPLETE) { 1342 /* 1343 * All OK; read the SEEPROM data register, then write back 1344 * the value read from the address register in order to 1345 * clear the <complete> bit and leave the SEEPROM access 1346 * state machine idle, ready for the next access ... 1347 */ 1348 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1349 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1350 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1351 return (0); 1352 } 1353 1354 /* 1355 * Hmm ... what happened here? 1356 * 1357 * Most likely, the user addressed a non-existent SEEPROM. Or 1358 * maybe the SEEPROM was busy internally (e.g. processing a write) 1359 * and didn't respond to being addressed. Either way, it's left 1360 * the SEEPROM access state machine wedged. So we'll reset it 1361 * before we leave, so it's ready for next time ... 1362 */ 1363 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1364 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1365 return (ENODATA); 1366 } 1367 1368 /* 1369 * Basic Flash get/set access routine 1370 * 1371 * These use the chip's Flash auto-access method, controlled by the 1372 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1373 * fiddle with the individual bits. 1374 * 1375 * The caller should hold <genlock> and *also* have already acquired 1376 * the right to access the Flash, via bge_nvmem_acquire() above. 1377 * 1378 * Return value: 1379 * 0 on success, 1380 * ENODATA on access timeout (maybe retryable: device may just be busy) 1381 * ENODEV if the NVmem device is missing or otherwise unusable 1382 * 1383 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1384 * from a (successful) NVM_FLASH_CMD_RD. 1385 */ 1386 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1387 uint32_t *dp); 1388 #pragma no_inline(bge_flash_access) 1389 1390 static int 1391 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1392 { 1393 uint32_t tries; 1394 uint32_t regval; 1395 1396 ASSERT(mutex_owned(bgep->genlock)); 1397 1398 /* 1399 * On the newer chips that support both SEEPROM & Flash, we need 1400 * to specifically disable SEEPROM access while accessing Flash. 1401 * The older chips don't support Flash, and the NVM registers don't 1402 * exist, so we shouldn't be here at all! 1403 */ 1404 switch (bgep->chipid.nvtype) { 1405 case BGE_NVTYPE_NONE: 1406 case BGE_NVTYPE_UNKNOWN: 1407 _NOTE(NOTREACHED) 1408 case BGE_NVTYPE_SEEPROM: 1409 return (ENODEV); 1410 1411 case BGE_NVTYPE_LEGACY_SEEPROM: 1412 case BGE_NVTYPE_UNBUFFERED_FLASH: 1413 case BGE_NVTYPE_BUFFERED_FLASH: 1414 default: 1415 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1416 NVM_CFG1_LEGACY_SEEPROM_MODE); 1417 break; 1418 } 1419 1420 /* 1421 * Assemble the command ... 1422 */ 1423 addr &= NVM_FLASH_ADDR_MASK; 1424 cmd |= NVM_FLASH_CMD_DOIT; 1425 cmd |= NVM_FLASH_CMD_FIRST; 1426 cmd |= NVM_FLASH_CMD_LAST; 1427 cmd |= NVM_FLASH_CMD_DONE; 1428 1429 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1430 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1431 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1432 1433 /* 1434 * Allow up to 1000ms ... 1435 */ 1436 for (tries = 0; tries < 1000; ++tries) { 1437 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1438 if (regval & NVM_FLASH_CMD_DONE) 1439 break; 1440 drv_usecwait(1); 1441 } 1442 1443 if (regval & NVM_FLASH_CMD_DONE) { 1444 /* 1445 * All OK; read the data from the Flash read register 1446 */ 1447 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1448 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1449 return (0); 1450 } 1451 1452 /* 1453 * Hmm ... what happened here? 1454 * 1455 * Most likely, the user addressed a non-existent Flash. Or 1456 * maybe the Flash was busy internally (e.g. processing a write) 1457 * and didn't respond to being addressed. Either way, there's 1458 * nothing we can here ... 1459 */ 1460 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1461 return (ENODATA); 1462 } 1463 1464 /* 1465 * The next two functions regulate access to the NVram (if fitted). 1466 * 1467 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1468 * (SPI) interface, but they can be accessed through either port. These 1469 * are managed by different instance of this driver and have no software 1470 * state in common. 1471 * 1472 * In addition (and even on a single core chip) the chip's internal 1473 * firmware can access the SEEPROM/Flash, most notably after a RESET 1474 * when it may download code to run internally. 1475 * 1476 * So we need to arbitrate between these various software agents. For 1477 * this purpose, the chip provides the Software Arbitration Register, 1478 * which implements hardware(!) arbitration. 1479 * 1480 * This functionality didn't exist on older (5700/5701) chips, so there's 1481 * nothing we can do by way of arbitration on those; also, if there's no 1482 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1483 * nothing to do. 1484 * 1485 * The internal firmware appears to use Request 0, which is the highest 1486 * priority. So we'd like to use Request 2, leaving one higher and one 1487 * lower for any future developments ... but apparently this doesn't 1488 * always work. So for now, the code uses Request 1 ;-( 1489 */ 1490 1491 #define NVM_READ_REQ NVM_READ_REQ1 1492 #define NVM_RESET_REQ NVM_RESET_REQ1 1493 #define NVM_SET_REQ NVM_SET_REQ1 1494 1495 static void bge_nvmem_relinquish(bge_t *bgep); 1496 #pragma no_inline(bge_nvmem_relinquish) 1497 1498 static void 1499 bge_nvmem_relinquish(bge_t *bgep) 1500 { 1501 ASSERT(mutex_owned(bgep->genlock)); 1502 1503 switch (bgep->chipid.nvtype) { 1504 case BGE_NVTYPE_NONE: 1505 case BGE_NVTYPE_UNKNOWN: 1506 _NOTE(NOTREACHED) 1507 return; 1508 1509 case BGE_NVTYPE_SEEPROM: 1510 /* 1511 * No arbitration performed, no release needed 1512 */ 1513 return; 1514 1515 case BGE_NVTYPE_LEGACY_SEEPROM: 1516 case BGE_NVTYPE_UNBUFFERED_FLASH: 1517 case BGE_NVTYPE_BUFFERED_FLASH: 1518 default: 1519 break; 1520 } 1521 1522 /* 1523 * Our own request should be present (whether or not granted) ... 1524 */ 1525 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1526 1527 /* 1528 * ... this will make it go away. 1529 */ 1530 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1531 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1532 } 1533 1534 /* 1535 * Arbitrate for access to the NVmem, if necessary 1536 * 1537 * Return value: 1538 * 0 on success 1539 * EAGAIN if the device is in use (retryable) 1540 * ENODEV if the NVmem device is missing or otherwise unusable 1541 */ 1542 static int bge_nvmem_acquire(bge_t *bgep); 1543 #pragma no_inline(bge_nvmem_acquire) 1544 1545 static int 1546 bge_nvmem_acquire(bge_t *bgep) 1547 { 1548 uint32_t regval; 1549 uint32_t tries; 1550 1551 ASSERT(mutex_owned(bgep->genlock)); 1552 1553 switch (bgep->chipid.nvtype) { 1554 case BGE_NVTYPE_NONE: 1555 case BGE_NVTYPE_UNKNOWN: 1556 /* 1557 * Access denied: no (recognisable) device fitted 1558 */ 1559 return (ENODEV); 1560 1561 case BGE_NVTYPE_SEEPROM: 1562 /* 1563 * Access granted: no arbitration needed (or possible) 1564 */ 1565 return (0); 1566 1567 case BGE_NVTYPE_LEGACY_SEEPROM: 1568 case BGE_NVTYPE_UNBUFFERED_FLASH: 1569 case BGE_NVTYPE_BUFFERED_FLASH: 1570 default: 1571 /* 1572 * Access conditional: conduct arbitration protocol 1573 */ 1574 break; 1575 } 1576 1577 /* 1578 * We're holding the per-port mutex <genlock>, so no-one other 1579 * thread can be attempting to access the NVmem through *this* 1580 * port. But it could be in use by the *other* port (of a 5704), 1581 * or by the chip's internal firmware, so we have to go through 1582 * the full (hardware) arbitration protocol ... 1583 * 1584 * Note that *because* we're holding <genlock>, the interrupt handler 1585 * won't be able to progress. So we're only willing to spin for a 1586 * fairly short time. Specifically: 1587 * 1588 * We *must* wait long enough for the hardware to resolve all 1589 * requests and determine the winner. Fortunately, this is 1590 * "almost instantaneous", even as observed by GHz CPUs. 1591 * 1592 * A successful access by another Solaris thread (via either 1593 * port) typically takes ~20us. So waiting a bit longer than 1594 * that will give a good chance of success, if the other user 1595 * *is* another thread on the other port. 1596 * 1597 * However, the internal firmware can hold on to the NVmem 1598 * for *much* longer: at least 10 milliseconds just after a 1599 * RESET, and maybe even longer if the NVmem actually contains 1600 * code to download and run on the internal CPUs. 1601 * 1602 * So, we'll allow 50us; if that's not enough then it's up to the 1603 * caller to retry later (hence the choice of return code EAGAIN). 1604 */ 1605 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1606 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1607 1608 for (tries = 0; tries < 50; ++tries) { 1609 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1610 if (regval & NVM_WON_REQ1) 1611 break; 1612 drv_usecwait(1); 1613 } 1614 1615 if (regval & NVM_WON_REQ1) { 1616 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1617 return (0); 1618 } 1619 1620 /* 1621 * Somebody else must be accessing the NVmem, so abandon our 1622 * attempt take control of it. The caller can try again later ... 1623 */ 1624 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1625 bge_nvmem_relinquish(bgep); 1626 return (EAGAIN); 1627 } 1628 1629 /* 1630 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1631 * write protect line in such a way that the NVmem is protected when 1632 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1633 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1634 * 1635 * Note: there's only one set of GPIO pins on a 5704, even though they 1636 * can be accessed through either port. So the chip has to resolve what 1637 * happens if the two ports program a single pin differently ... the rule 1638 * it uses is that if the ports disagree about the *direction* of a pin, 1639 * "output" wins over "input", but if they disagree about its *value* as 1640 * an output, then the pin is TRISTATED instead! In such a case, no-one 1641 * wins, and the external signal does whatever the external circuitry 1642 * defines as the default -- which we've assumed is the PROTECTED state. 1643 * So, we always change GPIO1 back to being an *input* whenever we're not 1644 * specifically using it to unprotect the NVmem. This allows either port 1645 * to update the NVmem, although obviously only one at a time! 1646 * 1647 * The caller should hold <genlock> and *also* have already acquired the 1648 * right to access the NVmem, via bge_nvmem_acquire() above. 1649 */ 1650 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1651 #pragma inline(bge_nvmem_protect) 1652 1653 static void 1654 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1655 { 1656 uint32_t regval; 1657 1658 ASSERT(mutex_owned(bgep->genlock)); 1659 1660 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1661 if (protect) { 1662 regval |= MLCR_MISC_PINS_OUTPUT_1; 1663 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1664 } else { 1665 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1666 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1667 } 1668 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1669 } 1670 1671 /* 1672 * Now put it all together ... 1673 * 1674 * Try to acquire control of the NVmem; if successful, then: 1675 * unprotect it (if we want to write to it) 1676 * perform the requested access 1677 * reprotect it (after a write) 1678 * relinquish control 1679 * 1680 * Return value: 1681 * 0 on success, 1682 * EAGAIN if the device is in use (retryable) 1683 * ENODATA on access timeout (maybe retryable: device may just be busy) 1684 * ENODEV if the NVmem device is missing or otherwise unusable 1685 * EPROTO on other h/w or s/w errors. 1686 */ 1687 static int 1688 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1689 { 1690 int err; 1691 1692 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1693 switch (cmd) { 1694 case BGE_SEE_READ: 1695 err = bge_seeprom_access(bgep, 1696 SEEPROM_ACCESS_READ, addr, dp); 1697 break; 1698 1699 case BGE_SEE_WRITE: 1700 bge_nvmem_protect(bgep, B_FALSE); 1701 err = bge_seeprom_access(bgep, 1702 SEEPROM_ACCESS_WRITE, addr, dp); 1703 bge_nvmem_protect(bgep, B_TRUE); 1704 break; 1705 1706 case BGE_FLASH_READ: 1707 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1708 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1709 bge_reg_set32(bgep, NVM_ACCESS_REG, 1710 NVM_ACCESS_ENABLE); 1711 } 1712 err = bge_flash_access(bgep, 1713 NVM_FLASH_CMD_RD, addr, dp); 1714 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1715 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1716 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1717 NVM_ACCESS_ENABLE); 1718 } 1719 break; 1720 1721 case BGE_FLASH_WRITE: 1722 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1723 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1724 bge_reg_set32(bgep, NVM_ACCESS_REG, 1725 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1726 } 1727 bge_nvmem_protect(bgep, B_FALSE); 1728 err = bge_flash_access(bgep, 1729 NVM_FLASH_CMD_WR, addr, dp); 1730 bge_nvmem_protect(bgep, B_TRUE); 1731 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1732 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1733 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1734 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1735 } 1736 1737 break; 1738 1739 default: 1740 _NOTE(NOTREACHED) 1741 break; 1742 } 1743 bge_nvmem_relinquish(bgep); 1744 } 1745 1746 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1747 return (err); 1748 } 1749 1750 /* 1751 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1752 */ 1753 static uint64_t bge_get_nvmac(bge_t *bgep); 1754 #pragma no_inline(bge_get_nvmac) 1755 1756 static uint64_t 1757 bge_get_nvmac(bge_t *bgep) 1758 { 1759 uint32_t mac_high; 1760 uint32_t mac_low; 1761 uint32_t addr; 1762 uint32_t cmd; 1763 uint64_t mac; 1764 1765 BGE_TRACE(("bge_get_nvmac($%p)", 1766 (void *)bgep)); 1767 1768 switch (bgep->chipid.nvtype) { 1769 case BGE_NVTYPE_NONE: 1770 case BGE_NVTYPE_UNKNOWN: 1771 default: 1772 return (0ULL); 1773 1774 case BGE_NVTYPE_SEEPROM: 1775 case BGE_NVTYPE_LEGACY_SEEPROM: 1776 cmd = BGE_SEE_READ; 1777 break; 1778 1779 case BGE_NVTYPE_UNBUFFERED_FLASH: 1780 case BGE_NVTYPE_BUFFERED_FLASH: 1781 cmd = BGE_FLASH_READ; 1782 break; 1783 } 1784 1785 addr = NVMEM_DATA_MAC_ADDRESS; 1786 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1787 return (0ULL); 1788 addr += 4; 1789 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1790 return (0ULL); 1791 1792 /* 1793 * The Broadcom chip is natively BIG-endian, so that's how the 1794 * MAC address is represented in NVmem. We may need to swap it 1795 * around on a little-endian host ... 1796 */ 1797 #ifdef _BIG_ENDIAN 1798 mac = mac_high; 1799 mac = mac << 32; 1800 mac |= mac_low; 1801 #else 1802 mac = BGE_BSWAP_32(mac_high); 1803 mac = mac << 32; 1804 mac |= BGE_BSWAP_32(mac_low); 1805 #endif /* _BIG_ENDIAN */ 1806 1807 return (mac); 1808 } 1809 1810 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1811 1812 /* 1813 * Dummy version for when we're not supporting NVmem access 1814 */ 1815 static uint64_t bge_get_nvmac(bge_t *bgep); 1816 #pragma inline(bge_get_nvmac) 1817 1818 static uint64_t 1819 bge_get_nvmac(bge_t *bgep) 1820 { 1821 _NOTE(ARGUNUSED(bgep)) 1822 return (0ULL); 1823 } 1824 1825 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1826 1827 /* 1828 * Determine the type of NVmem that is (or may be) attached to this chip, 1829 */ 1830 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1831 #pragma no_inline(bge_nvmem_id) 1832 1833 static enum bge_nvmem_type 1834 bge_nvmem_id(bge_t *bgep) 1835 { 1836 enum bge_nvmem_type nvtype; 1837 uint32_t config1; 1838 1839 BGE_TRACE(("bge_nvmem_id($%p)", 1840 (void *)bgep)); 1841 1842 switch (bgep->chipid.device) { 1843 default: 1844 /* 1845 * We shouldn't get here; it means we don't recognise 1846 * the chip, which means we don't know how to determine 1847 * what sort of NVmem (if any) it has. So we'll say 1848 * NONE, to disable the NVmem access code ... 1849 */ 1850 nvtype = BGE_NVTYPE_NONE; 1851 break; 1852 1853 case DEVICE_ID_5700: 1854 case DEVICE_ID_5700x: 1855 case DEVICE_ID_5701: 1856 /* 1857 * These devices support *only* SEEPROMs 1858 */ 1859 nvtype = BGE_NVTYPE_SEEPROM; 1860 break; 1861 1862 case DEVICE_ID_5702: 1863 case DEVICE_ID_5702fe: 1864 case DEVICE_ID_5703C: 1865 case DEVICE_ID_5703S: 1866 case DEVICE_ID_5704C: 1867 case DEVICE_ID_5704S: 1868 case DEVICE_ID_5704: 1869 case DEVICE_ID_5705M: 1870 case DEVICE_ID_5705C: 1871 case DEVICE_ID_5705_2: 1872 case DEVICE_ID_5706: 1873 case DEVICE_ID_5782: 1874 case DEVICE_ID_5787: 1875 case DEVICE_ID_5787M: 1876 case DEVICE_ID_5788: 1877 case DEVICE_ID_5789: 1878 case DEVICE_ID_5751: 1879 case DEVICE_ID_5751M: 1880 case DEVICE_ID_5752: 1881 case DEVICE_ID_5752M: 1882 case DEVICE_ID_5754: 1883 case DEVICE_ID_5755: 1884 case DEVICE_ID_5755M: 1885 case DEVICE_ID_5721: 1886 case DEVICE_ID_5714C: 1887 case DEVICE_ID_5714S: 1888 case DEVICE_ID_5715C: 1889 case DEVICE_ID_5715S: 1890 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1891 if (config1 & NVM_CFG1_FLASH_MODE) 1892 if (config1 & NVM_CFG1_BUFFERED_MODE) 1893 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1894 else 1895 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1896 else 1897 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1898 break; 1899 } 1900 1901 return (nvtype); 1902 } 1903 1904 #undef BGE_DBG 1905 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1906 1907 static void 1908 bge_init_recv_rule(bge_t *bgep) 1909 { 1910 bge_recv_rule_t *rulep; 1911 uint32_t i; 1912 1913 /* 1914 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1915 * 1. to direct UDP traffic, set: 1916 * rulep->control = RULE_PROTO_CONTROL; 1917 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1918 * 2. to direct ICMP traffic, set: 1919 * rulep->control = RULE_PROTO_CONTROL; 1920 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1921 * 3. to direct traffic by source ip, set: 1922 * rulep->control = RULE_SIP_CONTROL; 1923 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1924 */ 1925 rulep = bgep->recv_rules; 1926 rulep->control = RULE_PROTO_CONTROL; 1927 rulep->mask_value = RULE_TCP_MASK_VALUE; 1928 1929 /* 1930 * set receive rule registers 1931 */ 1932 rulep = bgep->recv_rules; 1933 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1934 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1935 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1936 } 1937 } 1938 1939 /* 1940 * Using the values captured by bge_chip_cfg_init(), and additional probes 1941 * as required, characterise the chip fully: determine the label by which 1942 * to refer to this chip, the correct settings for various registers, and 1943 * of course whether the device and/or subsystem are supported! 1944 */ 1945 int bge_chip_id_init(bge_t *bgep); 1946 #pragma no_inline(bge_chip_id_init) 1947 1948 int 1949 bge_chip_id_init(bge_t *bgep) 1950 { 1951 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1952 boolean_t sys_ok; 1953 boolean_t dev_ok; 1954 chip_id_t *cidp; 1955 uint32_t subid; 1956 char *devname; 1957 char *sysname; 1958 int *ids; 1959 int err; 1960 uint_t i; 1961 1962 sys_ok = dev_ok = B_FALSE; 1963 cidp = &bgep->chipid; 1964 1965 /* 1966 * Check the PCI device ID to determine the generic chip type and 1967 * select parameters that depend on this. 1968 * 1969 * Note: because the SPARC platforms in general don't fit the 1970 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1971 * as zero - which is why we use <asic_rev> rather than <revision> 1972 * below ... 1973 * 1974 * Note: in general we can't distinguish between the Copper/SerDes 1975 * versions by ID alone, as some Copper devices (e.g. some but not 1976 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1977 * treat them the same here, and the MII code works out the media 1978 * type later on ... 1979 */ 1980 cidp->mbuf_base = bge_mbuf_pool_base; 1981 cidp->mbuf_length = bge_mbuf_pool_len; 1982 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1983 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1984 cidp->pci_type = BGE_PCI_X; 1985 cidp->statistic_type = BGE_STAT_BLK; 1986 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1987 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1988 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1989 cidp->rx_ticks_norm = bge_rx_ticks_norm; 1990 cidp->rx_count_norm = bge_rx_count_norm; 1991 1992 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1993 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1994 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1995 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1996 1997 cidp->msi_enabled = B_FALSE; 1998 1999 switch (cidp->device) { 2000 case DEVICE_ID_5700: 2001 case DEVICE_ID_5700x: 2002 cidp->chip_label = 5700; 2003 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2004 break; 2005 2006 case DEVICE_ID_5701: 2007 cidp->chip_label = 5701; 2008 dev_ok = B_TRUE; 2009 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2010 break; 2011 2012 case DEVICE_ID_5702: 2013 case DEVICE_ID_5702fe: 2014 cidp->chip_label = 5702; 2015 dev_ok = B_TRUE; 2016 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2017 cidp->pci_type = BGE_PCI; 2018 break; 2019 2020 case DEVICE_ID_5703C: 2021 case DEVICE_ID_5703S: 2022 case DEVICE_ID_5703: 2023 /* 2024 * Revision A0 of the 5703/5793 had various errata 2025 * that we can't or don't work around, so it's not 2026 * supported, but all later versions are 2027 */ 2028 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 2029 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 2030 dev_ok = B_TRUE; 2031 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2032 break; 2033 2034 case DEVICE_ID_5704C: 2035 case DEVICE_ID_5704S: 2036 case DEVICE_ID_5704: 2037 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 2038 cidp->mbuf_base = bge_mbuf_pool_base_5704; 2039 cidp->mbuf_length = bge_mbuf_pool_len_5704; 2040 dev_ok = B_TRUE; 2041 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2042 break; 2043 2044 case DEVICE_ID_5705C: 2045 case DEVICE_ID_5705M: 2046 case DEVICE_ID_5705MA3: 2047 case DEVICE_ID_5705F: 2048 case DEVICE_ID_5705_2: 2049 case DEVICE_ID_5754: 2050 if (cidp->device == DEVICE_ID_5754) { 2051 cidp->chip_label = 5754; 2052 cidp->pci_type = BGE_PCI_E; 2053 } else { 2054 cidp->chip_label = 5705; 2055 cidp->pci_type = BGE_PCI; 2056 } 2057 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2058 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2059 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2060 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2061 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2062 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2063 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2064 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2065 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2066 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2067 cidp->statistic_type = BGE_STAT_REG; 2068 dev_ok = B_TRUE; 2069 break; 2070 2071 case DEVICE_ID_5753: 2072 cidp->chip_label = 5753; 2073 cidp->pci_type = BGE_PCI_E; 2074 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2075 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2076 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2077 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2078 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2079 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2080 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2081 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2082 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2083 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2084 cidp->statistic_type = BGE_STAT_REG; 2085 dev_ok = B_TRUE; 2086 break; 2087 2088 case DEVICE_ID_5755: 2089 case DEVICE_ID_5755M: 2090 cidp->chip_label = 5755; 2091 cidp->pci_type = BGE_PCI_E; 2092 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2093 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2094 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2095 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2096 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2097 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2098 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2099 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2100 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2101 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2102 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2103 cidp->statistic_type = BGE_STAT_REG; 2104 dev_ok = B_TRUE; 2105 break; 2106 2107 case DEVICE_ID_5787: 2108 case DEVICE_ID_5787M: 2109 cidp->chip_label = 5787; 2110 cidp->pci_type = BGE_PCI_E; 2111 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2112 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2113 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2114 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2115 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2116 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2117 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2118 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2119 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2120 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2121 cidp->statistic_type = BGE_STAT_REG; 2122 dev_ok = B_TRUE; 2123 break; 2124 2125 case DEVICE_ID_5706: 2126 cidp->chip_label = 5706; 2127 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2128 break; 2129 2130 case DEVICE_ID_5782: 2131 /* 2132 * Apart from the label, we treat this as a 5705(?) 2133 */ 2134 cidp->chip_label = 5782; 2135 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2136 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2137 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2138 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2139 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2140 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2141 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2142 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2143 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2144 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2145 cidp->statistic_type = BGE_STAT_REG; 2146 dev_ok = B_TRUE; 2147 break; 2148 2149 case DEVICE_ID_5788: 2150 /* 2151 * Apart from the label, we treat this as a 5705(?) 2152 */ 2153 cidp->chip_label = 5788; 2154 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2155 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2156 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2157 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2158 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2159 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2160 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2161 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2162 cidp->statistic_type = BGE_STAT_REG; 2163 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2164 dev_ok = B_TRUE; 2165 break; 2166 2167 case DEVICE_ID_5714C: 2168 if (cidp->revision >= REVISION_ID_5714_A2) 2169 cidp->msi_enabled = bge_enable_msi; 2170 /* FALLTHRU */ 2171 case DEVICE_ID_5714S: 2172 cidp->chip_label = 5714; 2173 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2174 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2175 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2176 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2177 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2178 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2179 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2180 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2181 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2182 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2183 cidp->pci_type = BGE_PCI_E; 2184 cidp->statistic_type = BGE_STAT_REG; 2185 dev_ok = B_TRUE; 2186 break; 2187 2188 case DEVICE_ID_5715C: 2189 case DEVICE_ID_5715S: 2190 cidp->chip_label = 5715; 2191 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2192 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2193 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2194 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2195 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2196 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2197 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2198 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2199 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2200 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2201 cidp->pci_type = BGE_PCI_E; 2202 cidp->statistic_type = BGE_STAT_REG; 2203 if (cidp->revision >= REVISION_ID_5715_A2) 2204 cidp->msi_enabled = bge_enable_msi; 2205 dev_ok = B_TRUE; 2206 break; 2207 2208 case DEVICE_ID_5721: 2209 cidp->chip_label = 5721; 2210 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2211 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2212 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2213 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2214 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2215 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2216 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2217 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2218 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2219 cidp->pci_type = BGE_PCI_E; 2220 cidp->statistic_type = BGE_STAT_REG; 2221 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2222 dev_ok = B_TRUE; 2223 break; 2224 2225 case DEVICE_ID_5751: 2226 case DEVICE_ID_5751M: 2227 cidp->chip_label = 5751; 2228 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2229 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2230 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2231 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2232 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2233 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2234 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2235 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2236 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2237 cidp->pci_type = BGE_PCI_E; 2238 cidp->statistic_type = BGE_STAT_REG; 2239 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2240 dev_ok = B_TRUE; 2241 break; 2242 2243 case DEVICE_ID_5752: 2244 case DEVICE_ID_5752M: 2245 cidp->chip_label = 5752; 2246 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2247 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2248 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2249 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2250 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2251 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2252 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2253 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2254 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2255 cidp->pci_type = BGE_PCI_E; 2256 cidp->statistic_type = BGE_STAT_REG; 2257 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2258 dev_ok = B_TRUE; 2259 break; 2260 2261 case DEVICE_ID_5789: 2262 cidp->chip_label = 5789; 2263 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2264 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2265 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2266 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2267 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2268 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2269 cidp->pci_type = BGE_PCI_E; 2270 cidp->statistic_type = BGE_STAT_REG; 2271 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2272 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2273 cidp->msi_enabled = B_TRUE; 2274 dev_ok = B_TRUE; 2275 break; 2276 2277 } 2278 2279 /* 2280 * Setup the default jumbo parameter. 2281 */ 2282 cidp->ethmax_size = ETHERMAX; 2283 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2284 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2285 2286 /* 2287 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2288 * setup below jumbo specific parameters. 2289 * 2290 * For BCM5714/5715, there is only one standard receive ring. So the 2291 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2292 * feature is enabled. 2293 */ 2294 if (bge_jumbo_enable && 2295 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2296 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2297 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2298 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2299 cidp->mbuf_lo_water_rdma = 2300 RDMA_MBUF_LOWAT_5714_JUMBO; 2301 cidp->mbuf_lo_water_rmac = 2302 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2303 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2304 cidp->jumbo_slots = 0; 2305 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2306 } else { 2307 cidp->mbuf_lo_water_rdma = 2308 RDMA_MBUF_LOWAT_JUMBO; 2309 cidp->mbuf_lo_water_rmac = 2310 MAC_RX_MBUF_LOWAT_JUMBO; 2311 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2312 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2313 } 2314 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2315 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2316 cidp->ethmax_size = cidp->default_mtu + 2317 sizeof (struct ether_header); 2318 } 2319 2320 /* 2321 * Identify the NV memory type: SEEPROM or Flash? 2322 */ 2323 cidp->nvtype = bge_nvmem_id(bgep); 2324 2325 /* 2326 * Now, we want to check whether this device is part of a 2327 * supported subsystem (e.g., on the motherboard of a Sun 2328 * branded platform). 2329 * 2330 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2331 */ 2332 if (cidp->subven == VENDOR_ID_SUN) 2333 sys_ok = B_TRUE; 2334 2335 /* 2336 * Rule 2: If it's on the list on known subsystems, then it's OK. 2337 * Note: 0x14e41647 should *not* appear in the list, but the code 2338 * doesn't enforce that. 2339 */ 2340 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2341 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2342 if (err == DDI_PROP_SUCCESS) { 2343 /* 2344 * Got the list; scan for a matching subsystem vendor/device 2345 */ 2346 subid = (cidp->subven << 16) | cidp->subdev; 2347 while (i--) 2348 if (ids[i] == subid) 2349 sys_ok = B_TRUE; 2350 ddi_prop_free(ids); 2351 } 2352 2353 /* 2354 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2355 * 2356 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2357 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2358 * we have to check specially for the exact device paths to the 2359 * motherboard devices on those platforms ;-( 2360 * 2361 * Note: we can't just use the "supported-subsystems" mechanism 2362 * above, because the entry would have to be 0x14e41647 -- which 2363 * would then accept *any* plugin card that *didn't* contain a 2364 * (valid) SEEPROM ;-( 2365 */ 2366 sysname = ddi_node_name(ddi_root_node()); 2367 devname = ddi_pathname(bgep->devinfo, buf); 2368 ASSERT(strlen(devname) > 0); 2369 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2370 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2371 sys_ok = B_TRUE; 2372 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2373 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2374 sys_ok = B_TRUE; 2375 2376 /* 2377 * Now check what we've discovered: is this truly a supported 2378 * chip on (the motherboard of) a supported platform? 2379 * 2380 * Possible problems here: 2381 * 1) it's a completely unheard-of chip (e.g. 5761) 2382 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2383 * 3) it's a chip we would support if it were on the motherboard 2384 * of a Sun platform, but this one isn't ;-( 2385 */ 2386 if (cidp->chip_label == 0) 2387 bge_problem(bgep, 2388 "Device 'pci%04x,%04x' not recognized (%d?)", 2389 cidp->vendor, cidp->device, cidp->device); 2390 else if (!dev_ok) 2391 bge_problem(bgep, 2392 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2393 cidp->vendor, cidp->device, cidp->chip_label, 2394 cidp->revision); 2395 #if BGE_DEBUGGING 2396 else if (!sys_ok) 2397 bge_problem(bgep, 2398 "%d-based subsystem 'pci%04x,%04x' not validated", 2399 cidp->chip_label, cidp->subven, cidp->subdev); 2400 #endif 2401 else 2402 cidp->flags |= CHIP_FLAG_SUPPORTED; 2403 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2404 return (EIO); 2405 return (0); 2406 } 2407 2408 void 2409 bge_chip_msi_trig(bge_t *bgep) 2410 { 2411 uint32_t regval; 2412 2413 regval = bgep->param_msi_cnt<<4; 2414 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2415 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2416 } 2417 2418 /* 2419 * Various registers that control the chip's internal engines (state 2420 * machines) have a <reset> and <enable> bits (fortunately, in the 2421 * same place in each such register :-). 2422 * 2423 * To reset the state machine, the <reset> bit must be written with 1; 2424 * it will then read back as 1 while the reset is in progress, but 2425 * self-clear to 0 when the reset completes. 2426 * 2427 * To enable a state machine, one must set the <enable> bit, which 2428 * will continue to read back as 0 until the state machine is running. 2429 * 2430 * To disable a state machine, the <enable> bit must be cleared, but 2431 * it will continue to read back as 1 until the state machine actually 2432 * stops. 2433 * 2434 * This routine implements polling for completion of a reset, enable 2435 * or disable operation, returning B_TRUE on success (bit reached the 2436 * required state) or B_FALSE on timeout (200*100us == 20ms). 2437 */ 2438 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2439 uint32_t mask, uint32_t val); 2440 #pragma no_inline(bge_chip_poll_engine) 2441 2442 static boolean_t 2443 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2444 uint32_t mask, uint32_t val) 2445 { 2446 uint32_t regval; 2447 uint32_t n; 2448 2449 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2450 (void *)bgep, regno, mask, val)); 2451 2452 for (n = 200; n; --n) { 2453 regval = bge_reg_get32(bgep, regno); 2454 if ((regval & mask) == val) 2455 return (B_TRUE); 2456 drv_usecwait(100); 2457 } 2458 2459 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2460 return (B_FALSE); 2461 } 2462 2463 /* 2464 * Various registers that control the chip's internal engines (state 2465 * machines) have a <reset> bit (fortunately, in the same place in 2466 * each such register :-). To reset the state machine, this bit must 2467 * be written with 1; it will then read back as 1 while the reset is 2468 * in progress, but self-clear to 0 when the reset completes. 2469 * 2470 * This code sets the bit, then polls for it to read back as zero. 2471 * The return value is B_TRUE on success (reset bit cleared itself), 2472 * or B_FALSE if the state machine didn't recover :( 2473 * 2474 * NOTE: the Core reset is similar to other resets, except that we 2475 * can't poll for completion, since the Core reset disables memory 2476 * access! So we just have to assume that it will all complete in 2477 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2478 */ 2479 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2480 #pragma no_inline(bge_chip_reset_engine) 2481 2482 static boolean_t 2483 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2484 { 2485 uint32_t regval; 2486 uint32_t val32; 2487 2488 regval = bge_reg_get32(bgep, regno); 2489 2490 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2491 (void *)bgep, regno)); 2492 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2493 regno, regval)); 2494 2495 regval |= STATE_MACHINE_RESET_BIT; 2496 2497 switch (regno) { 2498 case MISC_CONFIG_REG: 2499 /* 2500 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2501 * resetting PCIE block and bringing PCIE link down, bit 29 2502 * in the register needs to be set first, and then set it again 2503 * while the reset bit is written. 2504 * See:P500 of 57xx-PG102-RDS.pdf. 2505 */ 2506 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2507 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2508 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2509 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2510 if (bgep->chipid.pci_type == BGE_PCI_E) { 2511 if (bgep->chipid.asic_rev == 2512 MHCR_CHIP_REV_5751_A0 || 2513 bgep->chipid.asic_rev == 2514 MHCR_CHIP_REV_5721_A0 || 2515 bgep->chipid.asic_rev == 2516 MHCR_CHIP_REV_5755_A0) { 2517 val32 = bge_reg_get32(bgep, 2518 PHY_TEST_CTRL_REG); 2519 if (val32 == (PHY_PCIE_SCRAM_MODE | 2520 PHY_PCIE_LTASS_MODE)) 2521 bge_reg_put32(bgep, 2522 PHY_TEST_CTRL_REG, 2523 PHY_PCIE_SCRAM_MODE); 2524 val32 = pci_config_get32 2525 (bgep->cfg_handle, 2526 PCI_CONF_BGE_CLKCTL); 2527 val32 |= CLKCTL_PCIE_A0_FIX; 2528 pci_config_put32(bgep->cfg_handle, 2529 PCI_CONF_BGE_CLKCTL, val32); 2530 } 2531 bge_reg_set32(bgep, regno, 2532 MISC_CONFIG_GRC_RESET_DISABLE); 2533 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2534 } 2535 } 2536 2537 /* 2538 * Special case - causes Core reset 2539 * 2540 * On SPARC v9 we want to ensure that we don't start 2541 * timing until the I/O access has actually reached 2542 * the chip, otherwise we might make the next access 2543 * too early. And we can't just force the write out 2544 * by following it with a read (even to config space) 2545 * because that would cause the fault we're trying 2546 * to avoid. Hence the need for membar_sync() here. 2547 */ 2548 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2549 #ifdef __sparcv9 2550 membar_sync(); 2551 #endif /* __sparcv9 */ 2552 /* 2553 * On some platforms,system need about 300us for 2554 * link setup. 2555 */ 2556 drv_usecwait(300); 2557 2558 if (bgep->chipid.pci_type == BGE_PCI_E) { 2559 /* PCI-E device need more reset time */ 2560 drv_usecwait(120000); 2561 2562 /* Set PCIE max payload size and clear error status. */ 2563 if ((bgep->chipid.chip_label == 5721) || 2564 (bgep->chipid.chip_label == 5751) || 2565 (bgep->chipid.chip_label == 5752) || 2566 (bgep->chipid.chip_label == 5789)) { 2567 pci_config_put16(bgep->cfg_handle, 2568 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2569 pci_config_put16(bgep->cfg_handle, 2570 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2571 } 2572 } 2573 2574 BGE_PCICHK(bgep); 2575 return (B_TRUE); 2576 2577 default: 2578 bge_reg_put32(bgep, regno, regval); 2579 return (bge_chip_poll_engine(bgep, regno, 2580 STATE_MACHINE_RESET_BIT, 0)); 2581 } 2582 } 2583 2584 /* 2585 * Various registers that control the chip's internal engines (state 2586 * machines) have an <enable> bit (fortunately, in the same place in 2587 * each such register :-). To stop the state machine, this bit must 2588 * be written with 0, then polled to see when the state machine has 2589 * actually stopped. 2590 * 2591 * The return value is B_TRUE on success (enable bit cleared), or 2592 * B_FALSE if the state machine didn't stop :( 2593 */ 2594 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2595 uint32_t morebits); 2596 #pragma no_inline(bge_chip_disable_engine) 2597 2598 static boolean_t 2599 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2600 { 2601 uint32_t regval; 2602 2603 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2604 (void *)bgep, regno, morebits)); 2605 2606 switch (regno) { 2607 case FTQ_RESET_REG: 2608 /* 2609 * For Schumacher's bugfix CR6490108 2610 */ 2611 #ifdef BGE_IPMI_ASF 2612 #ifdef BGE_NETCONSOLE 2613 if (bgep->asf_enabled) 2614 return (B_TRUE); 2615 #endif 2616 #endif 2617 /* 2618 * Not quite like the others; it doesn't 2619 * have an <enable> bit, but instead we 2620 * have to set and then clear all the bits 2621 */ 2622 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2623 drv_usecwait(100); 2624 bge_reg_put32(bgep, regno, 0); 2625 return (B_TRUE); 2626 2627 default: 2628 regval = bge_reg_get32(bgep, regno); 2629 regval &= ~STATE_MACHINE_ENABLE_BIT; 2630 regval &= ~morebits; 2631 bge_reg_put32(bgep, regno, regval); 2632 return (bge_chip_poll_engine(bgep, regno, 2633 STATE_MACHINE_ENABLE_BIT, 0)); 2634 } 2635 } 2636 2637 /* 2638 * Various registers that control the chip's internal engines (state 2639 * machines) have an <enable> bit (fortunately, in the same place in 2640 * each such register :-). To start the state machine, this bit must 2641 * be written with 1, then polled to see when the state machine has 2642 * actually started. 2643 * 2644 * The return value is B_TRUE on success (enable bit set), or 2645 * B_FALSE if the state machine didn't start :( 2646 */ 2647 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2648 uint32_t morebits); 2649 #pragma no_inline(bge_chip_enable_engine) 2650 2651 static boolean_t 2652 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2653 { 2654 uint32_t regval; 2655 2656 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2657 (void *)bgep, regno, morebits)); 2658 2659 switch (regno) { 2660 case FTQ_RESET_REG: 2661 #ifdef BGE_IPMI_ASF 2662 #ifdef BGE_NETCONSOLE 2663 if (bgep->asf_enabled) 2664 return (B_TRUE); 2665 #endif 2666 #endif 2667 /* 2668 * Not quite like the others; it doesn't 2669 * have an <enable> bit, but instead we 2670 * have to set and then clear all the bits 2671 */ 2672 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2673 drv_usecwait(100); 2674 bge_reg_put32(bgep, regno, 0); 2675 return (B_TRUE); 2676 2677 default: 2678 regval = bge_reg_get32(bgep, regno); 2679 regval |= STATE_MACHINE_ENABLE_BIT; 2680 regval |= morebits; 2681 bge_reg_put32(bgep, regno, regval); 2682 return (bge_chip_poll_engine(bgep, regno, 2683 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2684 } 2685 } 2686 2687 /* 2688 * Reprogram the Ethernet, Transmit, and Receive MAC 2689 * modes to match the param_* variables 2690 */ 2691 void bge_sync_mac_modes(bge_t *bgep); 2692 #pragma no_inline(bge_sync_mac_modes) 2693 2694 void 2695 bge_sync_mac_modes(bge_t *bgep) 2696 { 2697 uint32_t macmode; 2698 uint32_t regval; 2699 2700 ASSERT(mutex_owned(bgep->genlock)); 2701 2702 /* 2703 * Reprogram the Ethernet MAC mode ... 2704 */ 2705 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2706 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2707 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2708 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2709 else 2710 macmode |= ETHERNET_MODE_LINK_POLARITY; 2711 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2712 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2713 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2714 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2715 else if (bgep->param_link_speed == 10 || bgep->param_link_speed == 100) 2716 macmode |= ETHERNET_MODE_PORTMODE_MII; 2717 else 2718 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2719 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2720 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2721 else 2722 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2723 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2724 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2725 else 2726 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2727 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2728 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2729 (void *)bgep, regval, macmode)); 2730 2731 /* 2732 * ... the Transmit MAC mode ... 2733 */ 2734 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2735 if (bgep->param_link_tx_pause) 2736 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2737 else 2738 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2739 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2740 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2741 (void *)bgep, regval, macmode)); 2742 2743 /* 2744 * ... and the Receive MAC mode 2745 */ 2746 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2747 if (bgep->param_link_rx_pause) 2748 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2749 else 2750 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2751 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2752 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2753 (void *)bgep, regval, macmode)); 2754 } 2755 2756 /* 2757 * bge_chip_sync() -- program the chip with the unicast MAC address, 2758 * the multicast hash table, the required level of promiscuity, and 2759 * the current loopback mode ... 2760 */ 2761 #ifdef BGE_IPMI_ASF 2762 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2763 #else 2764 int bge_chip_sync(bge_t *bgep); 2765 #endif 2766 #pragma no_inline(bge_chip_sync) 2767 2768 int 2769 #ifdef BGE_IPMI_ASF 2770 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2771 #else 2772 bge_chip_sync(bge_t *bgep) 2773 #endif 2774 { 2775 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2776 boolean_t promisc; 2777 uint64_t macaddr; 2778 uint32_t fill; 2779 int i, j; 2780 int retval = DDI_SUCCESS; 2781 2782 BGE_TRACE(("bge_chip_sync($%p)", 2783 (void *)bgep)); 2784 2785 ASSERT(mutex_owned(bgep->genlock)); 2786 2787 promisc = B_FALSE; 2788 fill = ~(uint32_t)0; 2789 2790 if (bgep->promisc) 2791 promisc = B_TRUE; 2792 else 2793 fill = (uint32_t)0; 2794 2795 /* 2796 * If the TX/RX MAC engines are already running, we should stop 2797 * them (and reset the RX engine) before changing the parameters. 2798 * If they're not running, this will have no effect ... 2799 * 2800 * NOTE: this is currently disabled by default because stopping 2801 * and restarting the Tx engine may cause an outgoing packet in 2802 * transit to be truncated. Also, stopping and restarting the 2803 * Rx engine seems to not work correctly on the 5705. Testing 2804 * has not (yet!) revealed any problems with NOT stopping and 2805 * restarting these engines (and Broadcom say their drivers don't 2806 * do this), but if it is found to cause problems, this variable 2807 * can be patched to re-enable the old behaviour ... 2808 */ 2809 if (bge_stop_start_on_sync) { 2810 #ifdef BGE_IPMI_ASF 2811 if (!bgep->asf_enabled) { 2812 if (!bge_chip_disable_engine(bgep, 2813 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2814 retval = DDI_FAILURE; 2815 } else { 2816 if (!bge_chip_disable_engine(bgep, 2817 RECEIVE_MAC_MODE_REG, 0)) 2818 retval = DDI_FAILURE; 2819 } 2820 #else 2821 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2822 RECEIVE_MODE_KEEP_VLAN_TAG)) 2823 retval = DDI_FAILURE; 2824 #endif 2825 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2826 retval = DDI_FAILURE; 2827 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2828 retval = DDI_FAILURE; 2829 } 2830 2831 /* 2832 * Reprogram the hashed multicast address table ... 2833 */ 2834 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2835 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 2836 2837 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2838 bge_reg_put32(bgep, MAC_HASH_REG(i), 2839 bgep->mcast_hash[i] | fill); 2840 2841 #ifdef BGE_IPMI_ASF 2842 if (!bgep->asf_enabled || !asf_keeplive) { 2843 #endif 2844 /* 2845 * Transform the MAC address(es) from host to chip format, then 2846 * reprogram the transmit random backoff seed and the unicast 2847 * MAC address(es) ... 2848 */ 2849 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2850 for (i = 0, fill = 0, macaddr = 0ull; 2851 i < ETHERADDRL; ++i) { 2852 macaddr <<= 8; 2853 macaddr |= bgep->curr_addr[j].addr[i]; 2854 fill += bgep->curr_addr[j].addr[i]; 2855 } 2856 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2857 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2858 } 2859 2860 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2861 (void *)bgep, macaddr)); 2862 #ifdef BGE_IPMI_ASF 2863 } 2864 #endif 2865 2866 /* 2867 * Set or clear the PROMISCUOUS mode bit 2868 */ 2869 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2870 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2871 2872 /* 2873 * Sync the rest of the MAC modes too ... 2874 */ 2875 bge_sync_mac_modes(bgep); 2876 2877 /* 2878 * Restart RX/TX MAC engines if required ... 2879 */ 2880 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2881 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2882 retval = DDI_FAILURE; 2883 #ifdef BGE_IPMI_ASF 2884 if (!bgep->asf_enabled) { 2885 if (!bge_chip_enable_engine(bgep, 2886 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2887 retval = DDI_FAILURE; 2888 } else { 2889 if (!bge_chip_enable_engine(bgep, 2890 RECEIVE_MAC_MODE_REG, 0)) 2891 retval = DDI_FAILURE; 2892 } 2893 #else 2894 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2895 RECEIVE_MODE_KEEP_VLAN_TAG)) 2896 retval = DDI_FAILURE; 2897 #endif 2898 } 2899 return (retval); 2900 } 2901 2902 /* 2903 * This array defines the sequence of state machine control registers 2904 * in which the <enable> bit must be cleared to bring the chip to a 2905 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2906 */ 2907 static bge_regno_t shutdown_engine_regs[] = { 2908 RECEIVE_MAC_MODE_REG, 2909 RCV_BD_INITIATOR_MODE_REG, 2910 RCV_LIST_PLACEMENT_MODE_REG, 2911 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2912 RCV_DATA_BD_INITIATOR_MODE_REG, 2913 RCV_DATA_COMPLETION_MODE_REG, 2914 RCV_BD_COMPLETION_MODE_REG, 2915 2916 SEND_BD_SELECTOR_MODE_REG, 2917 SEND_BD_INITIATOR_MODE_REG, 2918 SEND_DATA_INITIATOR_MODE_REG, 2919 READ_DMA_MODE_REG, 2920 SEND_DATA_COMPLETION_MODE_REG, 2921 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2922 SEND_BD_COMPLETION_MODE_REG, 2923 TRANSMIT_MAC_MODE_REG, 2924 2925 HOST_COALESCE_MODE_REG, 2926 WRITE_DMA_MODE_REG, 2927 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2928 FTQ_RESET_REG, /* special - see code */ 2929 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2930 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2931 BGE_REGNO_NONE /* terminator */ 2932 }; 2933 2934 /* 2935 * bge_chip_stop() -- stop all chip processing 2936 * 2937 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2938 * we've detected a problem internally; otherwise, this is a normal 2939 * (clean) stop (at user request i.e. the last STREAM has been closed). 2940 */ 2941 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2942 #pragma no_inline(bge_chip_stop) 2943 2944 void 2945 bge_chip_stop(bge_t *bgep, boolean_t fault) 2946 { 2947 bge_regno_t regno; 2948 bge_regno_t *rbp; 2949 boolean_t ok; 2950 2951 BGE_TRACE(("bge_chip_stop($%p)", 2952 (void *)bgep)); 2953 2954 ASSERT(mutex_owned(bgep->genlock)); 2955 2956 rbp = shutdown_engine_regs; 2957 /* 2958 * When driver try to shutdown the BCM5705/5788/5721/5751/ 2959 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 2960 * -ory arbiter should not be disabled. 2961 */ 2962 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 2963 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2964 ok &= bge_chip_disable_engine(bgep, regno, 0); 2965 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 2966 (regno != DMA_COMPLETION_MODE_REG) && 2967 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 2968 (regno != BUFFER_MANAGER_MODE_REG) && 2969 (regno != MEMORY_ARBITER_MODE_REG)) 2970 ok &= bge_chip_disable_engine(bgep, 2971 regno, 0); 2972 } 2973 2974 if (!ok && !fault) 2975 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 2976 2977 /* 2978 * Finally, disable (all) MAC events & clear the MAC status 2979 */ 2980 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 2981 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 2982 2983 /* 2984 * if we're stopping the chip because of a detected fault then do 2985 * appropriate actions 2986 */ 2987 if (fault) { 2988 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 2989 bgep->bge_chip_state = BGE_CHIP_FAULT; 2990 if (!bgep->manual_reset) 2991 ddi_fm_service_impact(bgep->devinfo, 2992 DDI_SERVICE_LOST); 2993 if (bgep->bge_dma_error) { 2994 /* 2995 * need to free buffers in case the fault was 2996 * due to a memory error in a buffer - got to 2997 * do a fair bit of tidying first 2998 */ 2999 if (bgep->progress & PROGRESS_KSTATS) { 3000 bge_fini_kstats(bgep); 3001 bgep->progress &= ~PROGRESS_KSTATS; 3002 } 3003 if (bgep->progress & PROGRESS_INTR) { 3004 bge_intr_disable(bgep); 3005 rw_enter(bgep->errlock, RW_WRITER); 3006 bge_fini_rings(bgep); 3007 rw_exit(bgep->errlock); 3008 bgep->progress &= ~PROGRESS_INTR; 3009 } 3010 if (bgep->progress & PROGRESS_BUFS) { 3011 bge_free_bufs(bgep); 3012 bgep->progress &= ~PROGRESS_BUFS; 3013 } 3014 bgep->bge_dma_error = B_FALSE; 3015 } 3016 } 3017 } else 3018 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3019 } 3020 3021 /* 3022 * Poll for completion of chip's ROM firmware; also, at least on the 3023 * first time through, find and return the hardware MAC address, if any. 3024 */ 3025 static uint64_t bge_poll_firmware(bge_t *bgep); 3026 #pragma no_inline(bge_poll_firmware) 3027 3028 static uint64_t 3029 bge_poll_firmware(bge_t *bgep) 3030 { 3031 uint64_t magic; 3032 uint64_t mac; 3033 uint32_t gen; 3034 uint32_t i; 3035 3036 /* 3037 * Step 19: poll for firmware completion (GENCOMM port set 3038 * to the ones complement of T3_MAGIC_NUMBER). 3039 * 3040 * While we're at it, we also read the MAC address register; 3041 * at some stage the firmware will load this with the 3042 * factory-set value. 3043 * 3044 * When both the magic number and the MAC address are set, 3045 * we're done; but we impose a time limit of one second 3046 * (1000*1000us) in case the firmware fails in some fashion 3047 * or the SEEPROM that provides that MAC address isn't fitted. 3048 * 3049 * After the first time through (chip state != INITIAL), we 3050 * don't need the MAC address to be set (we've already got it 3051 * or not, from the first time), so we don't wait for it, but 3052 * we still have to wait for the T3_MAGIC_NUMBER. 3053 * 3054 * Note: the magic number is only a 32-bit quantity, but the NIC 3055 * memory is 64-bit (and big-endian) internally. Addressing the 3056 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3057 * it work correctly on both big- and little-endian hosts. 3058 */ 3059 for (i = 0; i < 1000; ++i) { 3060 drv_usecwait(1000); 3061 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3062 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3063 #ifdef BGE_IPMI_ASF 3064 if (!bgep->asf_enabled) { 3065 #endif 3066 if (gen != ~T3_MAGIC_NUMBER) 3067 continue; 3068 #ifdef BGE_IPMI_ASF 3069 } 3070 #endif 3071 if (mac != 0ULL) 3072 break; 3073 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3074 break; 3075 } 3076 3077 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3078 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3079 (void *)bgep, gen, i)); 3080 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3081 mac, magic)); 3082 3083 return (mac); 3084 } 3085 3086 /* 3087 * Maximum times of trying to get the NVRAM access lock 3088 * by calling bge_nvmem_acquire() 3089 */ 3090 #define MAX_TRY_NVMEM_ACQUIRE 10000 3091 3092 #ifdef BGE_IPMI_ASF 3093 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3094 #else 3095 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3096 #endif 3097 #pragma no_inline(bge_chip_reset) 3098 3099 int 3100 #ifdef BGE_IPMI_ASF 3101 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3102 #else 3103 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3104 #endif 3105 { 3106 chip_id_t chipid; 3107 uint64_t mac; 3108 uint64_t magic; 3109 uint32_t modeflags; 3110 uint32_t mhcr; 3111 uint32_t sx0; 3112 uint32_t i, tries; 3113 #ifdef BGE_IPMI_ASF 3114 uint32_t mailbox; 3115 #endif 3116 int retval = DDI_SUCCESS; 3117 3118 BGE_TRACE(("bge_chip_reset($%p, %d)", 3119 (void *)bgep, enable_dma)); 3120 3121 ASSERT(mutex_owned(bgep->genlock)); 3122 3123 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3124 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3125 3126 /* 3127 * Do we need to stop the chip cleanly before resetting? 3128 */ 3129 switch (bgep->bge_chip_state) { 3130 default: 3131 _NOTE(NOTREACHED) 3132 return (DDI_FAILURE); 3133 3134 case BGE_CHIP_INITIAL: 3135 case BGE_CHIP_STOPPED: 3136 case BGE_CHIP_RESET: 3137 break; 3138 3139 case BGE_CHIP_RUNNING: 3140 case BGE_CHIP_ERROR: 3141 case BGE_CHIP_FAULT: 3142 bge_chip_stop(bgep, B_FALSE); 3143 break; 3144 } 3145 3146 #ifdef BGE_IPMI_ASF 3147 if (bgep->asf_enabled) { 3148 #ifdef __sparc 3149 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3150 MHCR_ENABLE_TAGGED_STATUS_MODE | 3151 MHCR_MASK_INTERRUPT_MODE | 3152 MHCR_MASK_PCI_INT_OUTPUT | 3153 MHCR_CLEAR_INTERRUPT_INTA | 3154 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3155 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3156 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3157 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3158 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3159 MEMORY_ARBITER_ENABLE); 3160 #endif 3161 if (asf_mode == ASF_MODE_INIT) { 3162 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3163 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3164 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3165 } 3166 } 3167 #endif 3168 /* 3169 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3170 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3171 * 3172 * Before reset Core clock,it is 3173 * also required to initialize the Memory Arbiter as specified in step9 3174 * and Misc Host Control Register as specified in step-13 3175 * Step 4-5: reset Core clock & wait for completion 3176 * Steps 6-8: are done by bge_chip_cfg_init() 3177 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3178 */ 3179 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3180 retval = DDI_FAILURE; 3181 3182 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3183 MHCR_ENABLE_TAGGED_STATUS_MODE | 3184 MHCR_MASK_INTERRUPT_MODE | 3185 MHCR_MASK_PCI_INT_OUTPUT | 3186 MHCR_CLEAR_INTERRUPT_INTA; 3187 #ifdef _BIG_ENDIAN 3188 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3189 #endif /* _BIG_ENDIAN */ 3190 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3191 #ifdef BGE_IPMI_ASF 3192 if (bgep->asf_enabled) 3193 bgep->asf_wordswapped = B_FALSE; 3194 #endif 3195 /* 3196 * NVRAM Corruption Workaround 3197 */ 3198 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3199 if (bge_nvmem_acquire(bgep) != EAGAIN) 3200 break; 3201 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3202 BGE_DEBUG(("%s: fail to acquire nvram lock", 3203 bgep->ifname)); 3204 3205 #ifdef BGE_IPMI_ASF 3206 if (!bgep->asf_enabled) { 3207 #endif 3208 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3209 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3210 #ifdef BGE_IPMI_ASF 3211 } 3212 #endif 3213 3214 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3215 retval = DDI_FAILURE; 3216 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3217 3218 /* 3219 * Step 8a: This may belong elsewhere, but BCM5721 needs 3220 * a bit set to avoid a fifo overflow/underflow bug. 3221 */ 3222 if ((bgep->chipid.chip_label == 5721) || 3223 (bgep->chipid.chip_label == 5751) || 3224 (bgep->chipid.chip_label == 5752) || 3225 (bgep->chipid.chip_label == 5755) || 3226 (bgep->chipid.chip_label == 5789)) 3227 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3228 3229 3230 /* 3231 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3232 * not be changed. 3233 */ 3234 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3235 retval = DDI_FAILURE; 3236 3237 /* 3238 * Steps 10-11: configure PIO endianness options and 3239 * enable indirect register access -- already done 3240 * Steps 12-13: enable writing to the PCI state & clock 3241 * control registers -- not required; we aren't going to 3242 * use those features. 3243 * Steps 14-15: Configure DMA endianness options. See 3244 * the comments on the setting of the MHCR above. 3245 */ 3246 #ifdef _BIG_ENDIAN 3247 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3248 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3249 #else 3250 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3251 #endif /* _BIG_ENDIAN */ 3252 #ifdef BGE_IPMI_ASF 3253 if (bgep->asf_enabled) 3254 modeflags |= MODE_HOST_STACK_UP; 3255 #endif 3256 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3257 3258 #ifdef BGE_IPMI_ASF 3259 if (bgep->asf_enabled) { 3260 #ifdef __sparc 3261 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3262 MEMORY_ARBITER_ENABLE | 3263 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3264 #endif 3265 3266 #ifdef BGE_NETCONSOLE 3267 if (!bgep->asf_newhandshake) { 3268 if ((asf_mode == ASF_MODE_INIT) || 3269 (asf_mode == ASF_MODE_POST_INIT)) { 3270 bge_asf_post_reset_old_mode(bgep, 3271 BGE_INIT_RESET); 3272 } else { 3273 bge_asf_post_reset_old_mode(bgep, 3274 BGE_SHUTDOWN_RESET); 3275 } 3276 } 3277 #endif 3278 3279 /* Wait for NVRAM init */ 3280 i = 0; 3281 drv_usecwait(5000); 3282 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3283 3284 while ((mailbox != (uint32_t) 3285 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3286 (i < 10000)) { 3287 drv_usecwait(100); 3288 mailbox = bge_nic_get32(bgep, 3289 BGE_FIRMWARE_MAILBOX); 3290 i++; 3291 } 3292 3293 #ifndef BGE_NETCONSOLE 3294 if (!bgep->asf_newhandshake) { 3295 if ((asf_mode == ASF_MODE_INIT) || 3296 (asf_mode == ASF_MODE_POST_INIT)) { 3297 3298 bge_asf_post_reset_old_mode(bgep, 3299 BGE_INIT_RESET); 3300 } else { 3301 bge_asf_post_reset_old_mode(bgep, 3302 BGE_SHUTDOWN_RESET); 3303 } 3304 } 3305 #endif 3306 } 3307 #endif 3308 /* 3309 * Steps 16-17: poll for firmware completion 3310 */ 3311 mac = bge_poll_firmware(bgep); 3312 3313 /* 3314 * Step 18: enable external memory -- doesn't apply. 3315 * 3316 * However we take the opportunity to set the MLCR anyway, as 3317 * this register also controls the SEEPROM auto-access method 3318 * which we may want to use later ... 3319 * 3320 * The proper value here depends on the way the chip is wired 3321 * into the circuit board, as this register *also* controls which 3322 * of the "Miscellaneous I/O" pins are driven as outputs and the 3323 * values driven onto those pins! 3324 * 3325 * See also step 74 in the PRM ... 3326 */ 3327 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3328 bgep->chipid.bge_mlcr_default); 3329 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3330 3331 /* 3332 * Step 20: clear the Ethernet MAC mode register 3333 */ 3334 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3335 3336 /* 3337 * Step 21: restore cache-line-size, latency timer, and 3338 * subsystem ID registers to their original values (not 3339 * those read into the local structure <chipid>, 'cos 3340 * that was after they were cleared by the RESET). 3341 * 3342 * Note: the Subsystem Vendor/Device ID registers are not 3343 * directly writable in config space, so we use the shadow 3344 * copy in "Page Zero" of register space to restore them 3345 * both in one go ... 3346 */ 3347 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3348 bgep->chipid.clsize); 3349 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3350 bgep->chipid.latency); 3351 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3352 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3353 3354 /* 3355 * The SEND INDEX registers should be reset to zero by the 3356 * global chip reset; if they're not, there'll be trouble 3357 * later on. 3358 */ 3359 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3360 if (sx0 != 0) { 3361 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3362 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3363 retval = DDI_FAILURE; 3364 } 3365 3366 /* Enable MSI code */ 3367 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3368 bge_reg_set32(bgep, MSI_MODE_REG, 3369 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3370 3371 /* 3372 * On the first time through, save the factory-set MAC address 3373 * (if any). If bge_poll_firmware() above didn't return one 3374 * (from a chip register) consider looking in the attached NV 3375 * memory device, if any. Once we have it, we save it in both 3376 * register-image (64-bit) and byte-array forms. All-zero and 3377 * all-one addresses are not valid, and we refuse to stash those. 3378 */ 3379 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3380 if (mac == 0ULL) 3381 mac = bge_get_nvmac(bgep); 3382 if (mac != 0ULL && mac != ~0ULL) { 3383 bgep->chipid.hw_mac_addr = mac; 3384 for (i = ETHERADDRL; i-- != 0; ) { 3385 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3386 mac >>= 8; 3387 } 3388 bgep->chipid.vendor_addr.set = B_TRUE; 3389 } 3390 } 3391 3392 #ifdef BGE_IPMI_ASF 3393 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3394 if (asf_mode != ASF_MODE_NONE) { 3395 if ((asf_mode == ASF_MODE_INIT) || 3396 (asf_mode == ASF_MODE_POST_INIT)) { 3397 3398 bge_asf_post_reset_new_mode(bgep, 3399 BGE_INIT_RESET); 3400 } else { 3401 bge_asf_post_reset_new_mode(bgep, 3402 BGE_SHUTDOWN_RESET); 3403 } 3404 } 3405 } 3406 #endif 3407 3408 /* 3409 * Record the new state 3410 */ 3411 bgep->chip_resets += 1; 3412 bgep->bge_chip_state = BGE_CHIP_RESET; 3413 return (retval); 3414 } 3415 3416 /* 3417 * bge_chip_start() -- start the chip transmitting and/or receiving, 3418 * including enabling interrupts 3419 */ 3420 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3421 #pragma no_inline(bge_chip_start) 3422 3423 int 3424 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3425 { 3426 uint32_t coalmode; 3427 uint32_t ledctl; 3428 uint32_t mtu; 3429 uint32_t maxring; 3430 uint32_t stats_mask; 3431 uint32_t dma_wrprio; 3432 uint64_t ring; 3433 int retval = DDI_SUCCESS; 3434 3435 BGE_TRACE(("bge_chip_start($%p)", 3436 (void *)bgep)); 3437 3438 ASSERT(mutex_owned(bgep->genlock)); 3439 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3440 3441 /* 3442 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3443 * The document specifies 95 separate steps to fully 3444 * initialise the chip!!!! 3445 * 3446 * The reset code above has already got us as far as step 3447 * 21, so we continue with ... 3448 * 3449 * Step 22: clear the MAC statistics block 3450 * (0x0300-0x0aff in NIC-local memory) 3451 */ 3452 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3453 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3454 NIC_MEM_STATISTICS_SIZE); 3455 3456 /* 3457 * Step 23: clear the status block (in host memory) 3458 */ 3459 DMA_ZERO(bgep->status_block); 3460 3461 /* 3462 * Step 24: set DMA read/write control register 3463 */ 3464 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3465 bgep->chipid.bge_dma_rwctrl); 3466 3467 /* 3468 * Step 25: Configure DMA endianness -- already done (16/17) 3469 * Step 26: Configure Host-Based Send Rings 3470 * Step 27: Indicate Host Stack Up 3471 */ 3472 bge_reg_set32(bgep, MODE_CONTROL_REG, 3473 MODE_HOST_SEND_BDS | 3474 MODE_HOST_STACK_UP); 3475 3476 /* 3477 * Step 28: Configure checksum options: 3478 * Solaris supports the hardware default checksum options. 3479 * 3480 * Workaround for Incorrect pseudo-header checksum calculation. 3481 */ 3482 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3483 bge_reg_set32(bgep, MODE_CONTROL_REG, 3484 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3485 3486 /* 3487 * Step 29: configure Timer Prescaler. The value is always the 3488 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3489 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3490 * for the whole chip! 3491 */ 3492 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3493 3494 /* 3495 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3496 * 3497 * If the mbuf_length is specified as 0, we just leave these at 3498 * their hardware defaults, rather than explicitly setting them. 3499 * As the Broadcom HRM,driver better not change the parameters 3500 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3501 */ 3502 if ((bgep->chipid.mbuf_length != 0) && 3503 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3504 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3505 bgep->chipid.mbuf_base); 3506 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3507 bgep->chipid.mbuf_length); 3508 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3509 DMAD_POOL_BASE_DEFAULT); 3510 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3511 DMAD_POOL_LENGTH_DEFAULT); 3512 } 3513 3514 /* 3515 * Step 32: configure MAC memory pool watermarks 3516 */ 3517 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3518 bgep->chipid.mbuf_lo_water_rdma); 3519 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3520 bgep->chipid.mbuf_lo_water_rmac); 3521 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3522 bgep->chipid.mbuf_hi_water); 3523 3524 /* 3525 * Step 33: configure DMA resource watermarks 3526 */ 3527 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3528 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3529 bge_dmad_lo_water); 3530 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3531 bge_dmad_hi_water); 3532 } 3533 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3534 3535 /* 3536 * Steps 34-36: enable buffer manager & internal h/w queues 3537 */ 3538 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3539 STATE_MACHINE_ATTN_ENABLE_BIT)) 3540 retval = DDI_FAILURE; 3541 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3542 retval = DDI_FAILURE; 3543 3544 /* 3545 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3546 */ 3547 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3548 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3549 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3550 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3551 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3552 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3553 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3554 } 3555 3556 /* 3557 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3558 */ 3559 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3560 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3561 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3562 bge_replenish_jumbo); 3563 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3564 bge_replenish_mini); 3565 } 3566 3567 /* 3568 * Steps 41-43: clear Send Ring Producer Indices and initialise 3569 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3570 */ 3571 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3572 maxring = BGE_SEND_RINGS_MAX; 3573 else 3574 maxring = BGE_SEND_RINGS_MAX_5705; 3575 for (ring = 0; ring < maxring; ++ring) { 3576 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3577 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3578 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3579 &bgep->send[ring].hw_rcb); 3580 } 3581 3582 /* 3583 * Steps 44-45: initialise Receive Return Rings 3584 * (0x0200-0x02ff in NIC-local memory) 3585 */ 3586 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3587 maxring = BGE_RECV_RINGS_MAX; 3588 else 3589 maxring = BGE_RECV_RINGS_MAX_5705; 3590 for (ring = 0; ring < maxring; ++ring) 3591 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3592 &bgep->recv[ring].hw_rcb); 3593 3594 /* 3595 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3596 */ 3597 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3598 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3599 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3600 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3601 } 3602 /* 3603 * Step 47: configure the MAC unicast address 3604 * Step 48: configure the random backoff seed 3605 * Step 96: set up multicast filters 3606 */ 3607 #ifdef BGE_IPMI_ASF 3608 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3609 #else 3610 if (bge_chip_sync(bgep) == DDI_FAILURE) 3611 #endif 3612 retval = DDI_FAILURE; 3613 3614 /* 3615 * Step 49: configure the MTU 3616 */ 3617 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3618 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3619 3620 /* 3621 * Step 50: configure the IPG et al 3622 */ 3623 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3624 3625 /* 3626 * Step 51: configure the default Rx Return Ring 3627 */ 3628 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3629 3630 /* 3631 * Steps 52-54: configure Receive List Placement, 3632 * and enable Receive List Placement Statistics 3633 */ 3634 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3635 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3636 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3637 case MHCR_CHIP_ASIC_REV_5700: 3638 case MHCR_CHIP_ASIC_REV_5701: 3639 case MHCR_CHIP_ASIC_REV_5703: 3640 case MHCR_CHIP_ASIC_REV_5704: 3641 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3642 break; 3643 case MHCR_CHIP_ASIC_REV_5705: 3644 break; 3645 default: 3646 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3647 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3648 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3649 break; 3650 } 3651 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3652 3653 if (bgep->chipid.rx_rings > 1) 3654 bge_init_recv_rule(bgep); 3655 3656 /* 3657 * Steps 55-56: enable Send Data Initiator Statistics 3658 */ 3659 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3660 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3661 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3662 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3663 } else { 3664 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3665 SEND_INIT_STATS_ENABLE); 3666 } 3667 /* 3668 * Steps 57-58: stop (?) the Host Coalescing Engine 3669 */ 3670 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3671 retval = DDI_FAILURE; 3672 3673 /* 3674 * Steps 59-62: initialise Host Coalescing parameters 3675 */ 3676 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3677 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3678 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3679 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3680 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3681 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3682 bge_tx_count_intr); 3683 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3684 bge_tx_ticks_intr); 3685 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3686 bge_rx_count_intr); 3687 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3688 bge_rx_ticks_intr); 3689 } 3690 3691 /* 3692 * Steps 63-64: initialise status block & statistics 3693 * host memory addresses 3694 * The statistic block does not exist in some chipsets 3695 * Step 65: initialise Statistics Coalescing Tick Counter 3696 */ 3697 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3698 bgep->status_block.cookie.dmac_laddress); 3699 3700 /* 3701 * Steps 66-67: initialise status block & statistics 3702 * NIC-local memory addresses 3703 */ 3704 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3705 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3706 bgep->statistics.cookie.dmac_laddress); 3707 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3708 STATISTICS_TICKS_DEFAULT); 3709 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3710 NIC_MEM_STATUS_BLOCK); 3711 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3712 NIC_MEM_STATISTICS); 3713 } 3714 3715 /* 3716 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3717 * Completion Engine, the Receive List Placement Engine, and the 3718 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3719 * and BCM5715. 3720 */ 3721 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3722 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3723 coalmode = COALESCE_64_BYTE_STATUS; 3724 else 3725 coalmode = 0; 3726 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3727 retval = DDI_FAILURE; 3728 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3729 STATE_MACHINE_ATTN_ENABLE_BIT)) 3730 retval = DDI_FAILURE; 3731 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3732 retval = DDI_FAILURE; 3733 3734 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3735 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3736 STATE_MACHINE_ATTN_ENABLE_BIT)) 3737 retval = DDI_FAILURE; 3738 3739 /* 3740 * Step 72: Enable MAC DMA engines 3741 * Step 73: Clear & enable MAC statistics 3742 */ 3743 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3744 ETHERNET_MODE_ENABLE_FHDE | 3745 ETHERNET_MODE_ENABLE_RDE | 3746 ETHERNET_MODE_ENABLE_TDE); 3747 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3748 ETHERNET_MODE_ENABLE_TX_STATS | 3749 ETHERNET_MODE_ENABLE_RX_STATS | 3750 ETHERNET_MODE_CLEAR_TX_STATS | 3751 ETHERNET_MODE_CLEAR_RX_STATS); 3752 3753 /* 3754 * Step 74: configure the MLCR (Miscellaneous Local Control 3755 * Register); not required, as we set up the MLCR in step 10 3756 * (part of the reset code) above. 3757 * 3758 * Step 75: clear Interrupt Mailbox 0 3759 */ 3760 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3761 3762 /* 3763 * Steps 76-87: Gentlemen, start your engines ... 3764 * 3765 * Enable the DMA Completion Engine, the Write DMA Engine, 3766 * the Read DMA Engine, Receive Data Completion Engine, 3767 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3768 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3769 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3770 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3771 * 3772 * Beware exhaust fumes? 3773 */ 3774 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3775 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3776 retval = DDI_FAILURE; 3777 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 3778 ALL_DMA_ATTN_BITS; 3779 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3780 MHCR_CHIP_ASIC_REV_5755) { 3781 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 3782 } 3783 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3784 dma_wrprio)) 3785 retval = DDI_FAILURE; 3786 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3787 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3788 retval = DDI_FAILURE; 3789 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3790 STATE_MACHINE_ATTN_ENABLE_BIT)) 3791 retval = DDI_FAILURE; 3792 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3793 if (!bge_chip_enable_engine(bgep, 3794 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3795 retval = DDI_FAILURE; 3796 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3797 retval = DDI_FAILURE; 3798 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3799 STATE_MACHINE_ATTN_ENABLE_BIT)) 3800 retval = DDI_FAILURE; 3801 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3802 RCV_BD_DISABLED_RING_ATTN)) 3803 retval = DDI_FAILURE; 3804 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3805 RCV_DATA_BD_ILL_RING_ATTN)) 3806 retval = DDI_FAILURE; 3807 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3808 retval = DDI_FAILURE; 3809 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3810 STATE_MACHINE_ATTN_ENABLE_BIT)) 3811 retval = DDI_FAILURE; 3812 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3813 STATE_MACHINE_ATTN_ENABLE_BIT)) 3814 retval = DDI_FAILURE; 3815 3816 /* 3817 * Step 88: download firmware -- doesn't apply 3818 * Steps 89-90: enable Transmit & Receive MAC Engines 3819 */ 3820 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3821 retval = DDI_FAILURE; 3822 #ifdef BGE_IPMI_ASF 3823 if (!bgep->asf_enabled) { 3824 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3825 RECEIVE_MODE_KEEP_VLAN_TAG)) 3826 retval = DDI_FAILURE; 3827 } else { 3828 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3829 retval = DDI_FAILURE; 3830 } 3831 #else 3832 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3833 RECEIVE_MODE_KEEP_VLAN_TAG)) 3834 retval = DDI_FAILURE; 3835 #endif 3836 3837 /* 3838 * Step 91: disable auto-polling of PHY status 3839 */ 3840 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3841 3842 /* 3843 * Step 92: configure D0 power state (not required) 3844 * Step 93: initialise LED control register () 3845 */ 3846 ledctl = LED_CONTROL_DEFAULT; 3847 switch (bgep->chipid.device) { 3848 case DEVICE_ID_5700: 3849 case DEVICE_ID_5700x: 3850 case DEVICE_ID_5701: 3851 /* 3852 * Switch to 5700 (MAC) mode on these older chips 3853 */ 3854 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3855 ledctl |= LED_CONTROL_LED_MODE_5700; 3856 break; 3857 3858 default: 3859 break; 3860 } 3861 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3862 3863 /* 3864 * Step 94: activate link 3865 */ 3866 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3867 3868 /* 3869 * Step 95: set up physical layer (PHY/SerDes) 3870 * restart autoneg (if required) 3871 */ 3872 if (reset_phys) 3873 if (bge_phys_update(bgep) == DDI_FAILURE) 3874 retval = DDI_FAILURE; 3875 3876 /* 3877 * Extra step (DSG): hand over all the Receive Buffers to the chip 3878 */ 3879 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3880 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3881 bgep->buff[ring].rf_next); 3882 3883 /* 3884 * MSI bits:The least significant MSI 16-bit word. 3885 * ISR will be triggered different. 3886 */ 3887 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3888 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3889 3890 /* 3891 * Extra step (DSG): select which interrupts are enabled 3892 * 3893 * Program the Ethernet MAC engine to signal attention on 3894 * Link Change events, then enable interrupts on MAC, DMA, 3895 * and FLOW attention signals. 3896 */ 3897 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3898 ETHERNET_EVENT_LINK_INT | 3899 ETHERNET_STATUS_PCS_ERROR_INT); 3900 #ifdef BGE_IPMI_ASF 3901 if (bgep->asf_enabled) { 3902 bge_reg_set32(bgep, MODE_CONTROL_REG, 3903 MODE_INT_ON_FLOW_ATTN | 3904 MODE_INT_ON_DMA_ATTN | 3905 MODE_HOST_STACK_UP| 3906 MODE_INT_ON_MAC_ATTN); 3907 } else { 3908 #endif 3909 bge_reg_set32(bgep, MODE_CONTROL_REG, 3910 MODE_INT_ON_FLOW_ATTN | 3911 MODE_INT_ON_DMA_ATTN | 3912 MODE_INT_ON_MAC_ATTN); 3913 #ifdef BGE_IPMI_ASF 3914 } 3915 #endif 3916 3917 /* 3918 * Step 97: enable PCI interrupts!!! 3919 */ 3920 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3921 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3922 MHCR_MASK_PCI_INT_OUTPUT); 3923 3924 /* 3925 * All done! 3926 */ 3927 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3928 return (retval); 3929 } 3930 3931 3932 /* 3933 * ========== Hardware interrupt handler ========== 3934 */ 3935 3936 #undef BGE_DBG 3937 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 3938 3939 /* 3940 * Sync the status block, then atomically clear the specified bits in 3941 * the <flags-and-tag> field of the status block. 3942 * the <flags> word of the status block, returning the value of the 3943 * <tag> and the <flags> before the bits were cleared. 3944 */ 3945 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 3946 #pragma inline(bge_status_sync) 3947 3948 static int 3949 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 3950 { 3951 bge_status_t *bsp; 3952 int retval; 3953 3954 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 3955 (void *)bgep, bits)); 3956 3957 ASSERT(bgep->bge_guard == BGE_GUARD); 3958 3959 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 3960 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 3961 if (retval != DDI_FM_OK) 3962 return (retval); 3963 3964 bsp = DMA_VPTR(bgep->status_block); 3965 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 3966 3967 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 3968 (void *)bgep, bits, *flags)); 3969 3970 return (retval); 3971 } 3972 3973 void bge_wake_factotum(bge_t *bgep); 3974 #pragma inline(bge_wake_factotum) 3975 3976 void 3977 bge_wake_factotum(bge_t *bgep) 3978 { 3979 mutex_enter(bgep->softintrlock); 3980 if (bgep->factotum_flag == 0) { 3981 bgep->factotum_flag = 1; 3982 ddi_trigger_softintr(bgep->factotum_id); 3983 } 3984 mutex_exit(bgep->softintrlock); 3985 } 3986 3987 /* 3988 * bge_intr() -- handle chip interrupts 3989 */ 3990 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 3991 #pragma no_inline(bge_intr) 3992 3993 uint_t 3994 bge_intr(caddr_t arg1, caddr_t arg2) 3995 { 3996 bge_t *bgep = (bge_t *)arg1; /* private device info */ 3997 bge_status_t *bsp; 3998 uint64_t flags; 3999 uint32_t regval; 4000 uint_t result; 4001 int retval, loop_cnt = 0; 4002 4003 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 4004 4005 /* 4006 * GLD v2 checks that s/w setup is complete before passing 4007 * interrupts to this routine, thus eliminating the old 4008 * (and well-known) race condition around ddi_add_intr() 4009 */ 4010 ASSERT(bgep->progress & PROGRESS_HWINT); 4011 4012 result = DDI_INTR_UNCLAIMED; 4013 mutex_enter(bgep->genlock); 4014 4015 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4016 /* 4017 * Check whether chip's says it's asserting #INTA; 4018 * if not, don't process or claim the interrupt. 4019 * 4020 * Note that the PCI signal is active low, so the 4021 * bit is *zero* when the interrupt is asserted. 4022 */ 4023 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 4024 if (regval & MLCR_INTA_STATE) { 4025 if (bge_check_acc_handle(bgep, bgep->io_handle) 4026 != DDI_FM_OK) 4027 goto chip_stop; 4028 mutex_exit(bgep->genlock); 4029 return (result); 4030 } 4031 4032 /* 4033 * Block further PCI interrupts ... 4034 */ 4035 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 4036 MHCR_MASK_PCI_INT_OUTPUT); 4037 4038 } else { 4039 /* 4040 * Check MSI status 4041 */ 4042 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 4043 if (regval & MSI_ERROR_ATTENTION) { 4044 BGE_REPORT((bgep, "msi error attention," 4045 " status=0x%x", regval)); 4046 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 4047 } 4048 } 4049 4050 result = DDI_INTR_CLAIMED; 4051 4052 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 4053 4054 /* 4055 * Sync the status block and grab the flags-n-tag from it. 4056 * We count the number of interrupts where there doesn't 4057 * seem to have been a DMA update of the status block; if 4058 * it *has* been updated, the counter will be cleared in 4059 * the while() loop below ... 4060 */ 4061 bgep->missed_dmas += 1; 4062 bsp = DMA_VPTR(bgep->status_block); 4063 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 4064 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 4065 /* 4066 * bge_chip_stop() may have freed dma area etc 4067 * while we were in this interrupt handler - 4068 * better not call bge_status_sync() 4069 */ 4070 (void) bge_check_acc_handle(bgep, 4071 bgep->io_handle); 4072 mutex_exit(bgep->genlock); 4073 return (DDI_INTR_CLAIMED); 4074 } 4075 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 4076 &flags); 4077 if (retval != DDI_FM_OK) { 4078 bgep->bge_dma_error = B_TRUE; 4079 goto chip_stop; 4080 } 4081 4082 if (!(flags & STATUS_FLAG_UPDATED)) 4083 break; 4084 4085 /* 4086 * Tell the chip that we're processing the interrupt 4087 */ 4088 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4089 INTERRUPT_MBOX_DISABLE(flags)); 4090 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4091 DDI_FM_OK) 4092 goto chip_stop; 4093 4094 /* 4095 * Drop the mutex while we: 4096 * Receive any newly-arrived packets 4097 * Recycle any newly-finished send buffers 4098 */ 4099 bgep->bge_intr_running = B_TRUE; 4100 mutex_exit(bgep->genlock); 4101 bge_receive(bgep, bsp); 4102 bge_recycle(bgep, bsp); 4103 mutex_enter(bgep->genlock); 4104 bgep->bge_intr_running = B_FALSE; 4105 4106 /* 4107 * Tell the chip we've finished processing, and 4108 * give it the tag that we got from the status 4109 * block earlier, so that it knows just how far 4110 * we've gone. If it's got more for us to do, 4111 * it will now update the status block and try 4112 * to assert an interrupt (but we've got the 4113 * #INTA blocked at present). If we see the 4114 * update, we'll loop around to do some more. 4115 * Eventually we'll get out of here ... 4116 */ 4117 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4118 INTERRUPT_MBOX_ENABLE(flags)); 4119 if (bgep->chipid.pci_type == BGE_PCI_E) 4120 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 4121 bgep->missed_dmas = 0; 4122 } 4123 4124 /* 4125 * Check for exceptional conditions that we need to handle 4126 * 4127 * Link status changed 4128 * Status block not updated 4129 */ 4130 if (flags & STATUS_FLAG_LINK_CHANGED) 4131 bge_wake_factotum(bgep); 4132 4133 if (bgep->missed_dmas) { 4134 /* 4135 * Probably due to the internal status tag not 4136 * being reset. Force a status block update now; 4137 * this should ensure that we get an update and 4138 * a new interrupt. After that, we should be in 4139 * sync again ... 4140 */ 4141 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4142 "not updated?", flags)); 4143 bgep->missed_updates++; 4144 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4145 COALESCE_NOW); 4146 4147 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4148 /* 4149 * If this happens multiple times in a row, 4150 * it means DMA is just not working. Maybe 4151 * the chip's failed, or maybe there's a 4152 * problem on the PCI bus or in the host-PCI 4153 * bridge (Tomatillo). 4154 * 4155 * At all events, we want to stop further 4156 * interrupts and let the recovery code take 4157 * over to see whether anything can be done 4158 * about it ... 4159 */ 4160 bge_fm_ereport(bgep, 4161 DDI_FM_DEVICE_BADINT_LIMIT); 4162 goto chip_stop; 4163 } 4164 } 4165 4166 /* 4167 * Reenable assertion of #INTA, unless there's a DMA fault 4168 */ 4169 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4170 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4171 MHCR_MASK_PCI_INT_OUTPUT); 4172 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4173 DDI_FM_OK) 4174 goto chip_stop; 4175 } 4176 4177 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4178 goto chip_stop; 4179 4180 mutex_exit(bgep->genlock); 4181 return (result); 4182 4183 chip_stop: 4184 #ifdef BGE_IPMI_ASF 4185 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4186 /* 4187 * We must stop ASF heart beat before 4188 * bge_chip_stop(), otherwise some 4189 * computers (ex. IBM HS20 blade 4190 * server) may crash. 4191 */ 4192 bge_asf_update_status(bgep); 4193 bge_asf_stop_timer(bgep); 4194 bgep->asf_status = ASF_STAT_STOP; 4195 4196 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4197 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4198 } 4199 #endif 4200 bge_chip_stop(bgep, B_TRUE); 4201 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4202 mutex_exit(bgep->genlock); 4203 return (result); 4204 } 4205 4206 /* 4207 * ========== Factotum, implemented as a softint handler ========== 4208 */ 4209 4210 #undef BGE_DBG 4211 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4212 4213 static void bge_factotum_error_handler(bge_t *bgep); 4214 #pragma no_inline(bge_factotum_error_handler) 4215 4216 static void 4217 bge_factotum_error_handler(bge_t *bgep) 4218 { 4219 uint32_t flow; 4220 uint32_t rdma; 4221 uint32_t wdma; 4222 uint32_t tmac; 4223 uint32_t rmac; 4224 uint32_t rxrs; 4225 uint32_t txrs = 0; 4226 4227 ASSERT(mutex_owned(bgep->genlock)); 4228 4229 /* 4230 * Read all the registers that show the possible 4231 * reasons for the ERROR bit to be asserted 4232 */ 4233 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4234 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4235 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4236 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4237 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4238 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4239 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4240 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4241 4242 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4243 (void *)bgep, flow, rdma, wdma)); 4244 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4245 (void *)bgep, tmac, rmac, rxrs, txrs)); 4246 4247 /* 4248 * For now, just clear all the errors ... 4249 */ 4250 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4251 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4252 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4253 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4254 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4255 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4256 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4257 } 4258 4259 /* 4260 * Handler for hardware link state change. 4261 * 4262 * When this routine is called, the hardware link state has changed 4263 * and the new state is reflected in the param_* variables. Here 4264 * we must update the softstate and reprogram the MAC to match. 4265 */ 4266 static void bge_factotum_link_handler(bge_t *bgep); 4267 #pragma no_inline(bge_factotum_link_handler) 4268 4269 static void 4270 bge_factotum_link_handler(bge_t *bgep) 4271 { 4272 ASSERT(mutex_owned(bgep->genlock)); 4273 4274 /* 4275 * Update the s/w link_state 4276 */ 4277 if (bgep->param_link_up) 4278 bgep->link_state = LINK_STATE_UP; 4279 else 4280 bgep->link_state = LINK_STATE_DOWN; 4281 4282 /* 4283 * Reprogram the MAC modes to match 4284 */ 4285 bge_sync_mac_modes(bgep); 4286 } 4287 4288 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4289 #pragma no_inline(bge_factotum_link_check) 4290 4291 static boolean_t 4292 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4293 { 4294 boolean_t check; 4295 uint64_t flags; 4296 uint32_t tmac_status; 4297 4298 ASSERT(mutex_owned(bgep->genlock)); 4299 4300 /* 4301 * Get & clear the writable status bits in the Tx status register 4302 * (some bits are write-1-to-clear, others are just readonly). 4303 */ 4304 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4305 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4306 4307 /* 4308 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4309 */ 4310 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4311 STATUS_FLAG_LINK_CHANGED, &flags); 4312 if (*dma_state != DDI_FM_OK) 4313 return (B_FALSE); 4314 4315 /* 4316 * Clear any errors flagged in the status block ... 4317 */ 4318 if (flags & STATUS_FLAG_ERROR) 4319 bge_factotum_error_handler(bgep); 4320 4321 /* 4322 * We need to check the link status if: 4323 * the status block says there's been a link change 4324 * or there's any discrepancy between the various 4325 * flags indicating the link state (link_state, 4326 * param_link_up, and the LINK STATE bit in the 4327 * Transmit MAC status register). 4328 */ 4329 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4330 switch (bgep->link_state) { 4331 case LINK_STATE_UP: 4332 check |= (bgep->param_link_up == B_FALSE); 4333 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4334 break; 4335 4336 case LINK_STATE_DOWN: 4337 check |= (bgep->param_link_up != B_FALSE); 4338 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4339 break; 4340 4341 default: 4342 check = B_TRUE; 4343 break; 4344 } 4345 4346 /* 4347 * If <check> is false, we're sure the link hasn't changed. 4348 * If true, however, it's not yet definitive; we have to call 4349 * bge_phys_check() to determine whether the link has settled 4350 * into a new state yet ... and if it has, then call the link 4351 * state change handler.But when the chip is 5700 in Dell 6650 4352 * ,even if check is false, the link may have changed.So we 4353 * have to call bge_phys_check() to determine the link state. 4354 */ 4355 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4356 check = bge_phys_check(bgep); 4357 if (check) 4358 bge_factotum_link_handler(bgep); 4359 } 4360 4361 return (check); 4362 } 4363 4364 /* 4365 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4366 */ 4367 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4368 #pragma no_inline(bge_factotum_stall_check) 4369 4370 static boolean_t 4371 bge_factotum_stall_check(bge_t *bgep) 4372 { 4373 uint32_t dogval; 4374 4375 ASSERT(mutex_owned(bgep->genlock)); 4376 4377 /* 4378 * Specific check for Tx stall ... 4379 * 4380 * The 'watchdog' counter is incremented whenever a packet 4381 * is queued, reset to 1 when some (but not all) buffers 4382 * are reclaimed, reset to 0 (disabled) when all buffers 4383 * are reclaimed, and shifted left here. If it exceeds the 4384 * threshold value, the chip is assumed to have stalled and 4385 * is put into the ERROR state. The factotum will then reset 4386 * it on the next pass. 4387 * 4388 * All of which should ensure that we don't get into a state 4389 * where packets are left pending indefinitely! 4390 */ 4391 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4392 if (dogval < bge_watchdog_count) 4393 return (B_FALSE); 4394 4395 #if !defined(BGE_NETCONSOLE) 4396 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4397 #endif 4398 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4399 return (B_TRUE); 4400 } 4401 4402 /* 4403 * The factotum is woken up when there's something to do that we'd rather 4404 * not do from inside a hardware interrupt handler or high-level cyclic. 4405 * Its two main tasks are: 4406 * reset & restart the chip after an error 4407 * check the link status whenever necessary 4408 */ 4409 uint_t bge_chip_factotum(caddr_t arg); 4410 #pragma no_inline(bge_chip_factotum) 4411 4412 uint_t 4413 bge_chip_factotum(caddr_t arg) 4414 { 4415 bge_t *bgep; 4416 uint_t result; 4417 boolean_t error; 4418 boolean_t linkchg; 4419 int dma_state; 4420 4421 bgep = (bge_t *)arg; 4422 4423 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4424 4425 mutex_enter(bgep->softintrlock); 4426 if (bgep->factotum_flag == 0) { 4427 mutex_exit(bgep->softintrlock); 4428 return (DDI_INTR_UNCLAIMED); 4429 } 4430 bgep->factotum_flag = 0; 4431 mutex_exit(bgep->softintrlock); 4432 4433 result = DDI_INTR_CLAIMED; 4434 error = B_FALSE; 4435 linkchg = B_FALSE; 4436 4437 mutex_enter(bgep->genlock); 4438 switch (bgep->bge_chip_state) { 4439 default: 4440 break; 4441 4442 case BGE_CHIP_RUNNING: 4443 linkchg = bge_factotum_link_check(bgep, &dma_state); 4444 error = bge_factotum_stall_check(bgep); 4445 if (dma_state != DDI_FM_OK) { 4446 bgep->bge_dma_error = B_TRUE; 4447 error = B_TRUE; 4448 } 4449 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4450 error = B_TRUE; 4451 if (error) 4452 bgep->bge_chip_state = BGE_CHIP_ERROR; 4453 break; 4454 4455 case BGE_CHIP_ERROR: 4456 error = B_TRUE; 4457 break; 4458 4459 case BGE_CHIP_FAULT: 4460 /* 4461 * Fault detected, time to reset ... 4462 */ 4463 if (bge_autorecover) { 4464 if (!(bgep->progress & PROGRESS_BUFS)) { 4465 /* 4466 * if we can't allocate the ring buffers, 4467 * try later 4468 */ 4469 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4470 mutex_exit(bgep->genlock); 4471 return (result); 4472 } 4473 bgep->progress |= PROGRESS_BUFS; 4474 } 4475 if (!(bgep->progress & PROGRESS_INTR)) { 4476 bge_init_rings(bgep); 4477 bge_intr_enable(bgep); 4478 bgep->progress |= PROGRESS_INTR; 4479 } 4480 if (!(bgep->progress & PROGRESS_KSTATS)) { 4481 bge_init_kstats(bgep, 4482 ddi_get_instance(bgep->devinfo)); 4483 bgep->progress |= PROGRESS_KSTATS; 4484 } 4485 4486 BGE_REPORT((bgep, "automatic recovery activated")); 4487 4488 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4489 bgep->bge_chip_state = BGE_CHIP_ERROR; 4490 error = B_TRUE; 4491 } 4492 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4493 DDI_FM_OK) { 4494 bgep->bge_chip_state = BGE_CHIP_ERROR; 4495 error = B_TRUE; 4496 } 4497 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4498 DDI_FM_OK) { 4499 bgep->bge_chip_state = BGE_CHIP_ERROR; 4500 error = B_TRUE; 4501 } 4502 if (error == B_FALSE) { 4503 #ifdef BGE_IPMI_ASF 4504 if (bgep->asf_enabled && 4505 bgep->asf_status != ASF_STAT_RUN) { 4506 bgep->asf_timeout_id = timeout( 4507 bge_asf_heartbeat, (void *)bgep, 4508 drv_usectohz( 4509 BGE_ASF_HEARTBEAT_INTERVAL)); 4510 bgep->asf_status = ASF_STAT_RUN; 4511 } 4512 #endif 4513 if (!bgep->manual_reset) { 4514 ddi_fm_service_impact(bgep->devinfo, 4515 DDI_SERVICE_RESTORED); 4516 } 4517 } 4518 } 4519 break; 4520 } 4521 4522 4523 /* 4524 * If an error is detected, stop the chip now, marking it as 4525 * faulty, so that it will be reset next time through ... 4526 * 4527 * Note that if intr_running is set, then bge_intr() has dropped 4528 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4529 * this point so have to wait until the next time the factotum runs. 4530 */ 4531 if (error && !bgep->bge_intr_running) { 4532 #ifdef BGE_IPMI_ASF 4533 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4534 /* 4535 * We must stop ASF heart beat before bge_chip_stop(), 4536 * otherwise some computers (ex. IBM HS20 blade server) 4537 * may crash. 4538 */ 4539 bge_asf_update_status(bgep); 4540 bge_asf_stop_timer(bgep); 4541 bgep->asf_status = ASF_STAT_STOP; 4542 4543 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4544 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4545 } 4546 #endif 4547 bge_chip_stop(bgep, B_TRUE); 4548 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4549 } 4550 mutex_exit(bgep->genlock); 4551 4552 /* 4553 * If the link state changed, tell the world about it. 4554 * Note: can't do this while still holding the mutex. 4555 */ 4556 if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT && 4557 bgep->link_state != LINK_STATE_UNKNOWN) 4558 linkchg = B_TRUE; 4559 else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT && 4560 bgep->link_state == LINK_STATE_DOWN) 4561 linkchg = B_FALSE; 4562 4563 if (linkchg) { 4564 mac_link_update(bgep->mh, bgep->link_state); 4565 bgep->link_update_timer = BGE_LINK_UPDATE_DONE; 4566 } 4567 if (bgep->manual_reset) { 4568 bgep->manual_reset = B_FALSE; 4569 } 4570 4571 return (result); 4572 } 4573 4574 /* 4575 * High-level cyclic handler 4576 * 4577 * This routine schedules a (low-level) softint callback to the 4578 * factotum, and prods the chip to update the status block (which 4579 * will cause a hardware interrupt when complete). 4580 */ 4581 void bge_chip_cyclic(void *arg); 4582 #pragma no_inline(bge_chip_cyclic) 4583 4584 void 4585 bge_chip_cyclic(void *arg) 4586 { 4587 bge_t *bgep; 4588 4589 bgep = arg; 4590 4591 switch (bgep->bge_chip_state) { 4592 default: 4593 return; 4594 4595 case BGE_CHIP_RUNNING: 4596 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4597 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4598 ddi_fm_service_impact(bgep->devinfo, 4599 DDI_SERVICE_UNAFFECTED); 4600 4601 if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT) 4602 bgep->link_update_timer++; 4603 4604 break; 4605 4606 case BGE_CHIP_FAULT: 4607 case BGE_CHIP_ERROR: 4608 break; 4609 } 4610 4611 bge_wake_factotum(bgep); 4612 } 4613 4614 4615 /* 4616 * ========== Ioctl subfunctions ========== 4617 */ 4618 4619 #undef BGE_DBG 4620 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4621 4622 #if BGE_DEBUGGING || BGE_DO_PPIO 4623 4624 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4625 #pragma no_inline(bge_chip_peek_cfg) 4626 4627 static void 4628 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4629 { 4630 uint64_t regval; 4631 uint64_t regno; 4632 4633 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4634 (void *)bgep, (void *)ppd)); 4635 4636 regno = ppd->pp_acc_offset; 4637 4638 switch (ppd->pp_acc_size) { 4639 case 1: 4640 regval = pci_config_get8(bgep->cfg_handle, regno); 4641 break; 4642 4643 case 2: 4644 regval = pci_config_get16(bgep->cfg_handle, regno); 4645 break; 4646 4647 case 4: 4648 regval = pci_config_get32(bgep->cfg_handle, regno); 4649 break; 4650 4651 case 8: 4652 regval = pci_config_get64(bgep->cfg_handle, regno); 4653 break; 4654 } 4655 4656 ppd->pp_acc_data = regval; 4657 } 4658 4659 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4660 #pragma no_inline(bge_chip_poke_cfg) 4661 4662 static void 4663 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4664 { 4665 uint64_t regval; 4666 uint64_t regno; 4667 4668 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4669 (void *)bgep, (void *)ppd)); 4670 4671 regno = ppd->pp_acc_offset; 4672 regval = ppd->pp_acc_data; 4673 4674 switch (ppd->pp_acc_size) { 4675 case 1: 4676 pci_config_put8(bgep->cfg_handle, regno, regval); 4677 break; 4678 4679 case 2: 4680 pci_config_put16(bgep->cfg_handle, regno, regval); 4681 break; 4682 4683 case 4: 4684 pci_config_put32(bgep->cfg_handle, regno, regval); 4685 break; 4686 4687 case 8: 4688 pci_config_put64(bgep->cfg_handle, regno, regval); 4689 break; 4690 } 4691 } 4692 4693 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4694 #pragma no_inline(bge_chip_peek_reg) 4695 4696 static void 4697 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4698 { 4699 uint64_t regval; 4700 void *regaddr; 4701 4702 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4703 (void *)bgep, (void *)ppd)); 4704 4705 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4706 4707 switch (ppd->pp_acc_size) { 4708 case 1: 4709 regval = ddi_get8(bgep->io_handle, regaddr); 4710 break; 4711 4712 case 2: 4713 regval = ddi_get16(bgep->io_handle, regaddr); 4714 break; 4715 4716 case 4: 4717 regval = ddi_get32(bgep->io_handle, regaddr); 4718 break; 4719 4720 case 8: 4721 regval = ddi_get64(bgep->io_handle, regaddr); 4722 break; 4723 } 4724 4725 ppd->pp_acc_data = regval; 4726 } 4727 4728 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4729 #pragma no_inline(bge_chip_peek_reg) 4730 4731 static void 4732 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4733 { 4734 uint64_t regval; 4735 void *regaddr; 4736 4737 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4738 (void *)bgep, (void *)ppd)); 4739 4740 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4741 regval = ppd->pp_acc_data; 4742 4743 switch (ppd->pp_acc_size) { 4744 case 1: 4745 ddi_put8(bgep->io_handle, regaddr, regval); 4746 break; 4747 4748 case 2: 4749 ddi_put16(bgep->io_handle, regaddr, regval); 4750 break; 4751 4752 case 4: 4753 ddi_put32(bgep->io_handle, regaddr, regval); 4754 break; 4755 4756 case 8: 4757 ddi_put64(bgep->io_handle, regaddr, regval); 4758 break; 4759 } 4760 BGE_PCICHK(bgep); 4761 } 4762 4763 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4764 #pragma no_inline(bge_chip_peek_nic) 4765 4766 static void 4767 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4768 { 4769 uint64_t regoff; 4770 uint64_t regval; 4771 void *regaddr; 4772 4773 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4774 (void *)bgep, (void *)ppd)); 4775 4776 regoff = ppd->pp_acc_offset; 4777 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4778 regoff &= MWBAR_GRANULE_MASK; 4779 regoff += NIC_MEM_WINDOW_OFFSET; 4780 regaddr = PIO_ADDR(bgep, regoff); 4781 4782 switch (ppd->pp_acc_size) { 4783 case 1: 4784 regval = ddi_get8(bgep->io_handle, regaddr); 4785 break; 4786 4787 case 2: 4788 regval = ddi_get16(bgep->io_handle, regaddr); 4789 break; 4790 4791 case 4: 4792 regval = ddi_get32(bgep->io_handle, regaddr); 4793 break; 4794 4795 case 8: 4796 regval = ddi_get64(bgep->io_handle, regaddr); 4797 break; 4798 } 4799 4800 ppd->pp_acc_data = regval; 4801 } 4802 4803 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4804 #pragma no_inline(bge_chip_poke_nic) 4805 4806 static void 4807 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4808 { 4809 uint64_t regoff; 4810 uint64_t regval; 4811 void *regaddr; 4812 4813 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4814 (void *)bgep, (void *)ppd)); 4815 4816 regoff = ppd->pp_acc_offset; 4817 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4818 regoff &= MWBAR_GRANULE_MASK; 4819 regoff += NIC_MEM_WINDOW_OFFSET; 4820 regaddr = PIO_ADDR(bgep, regoff); 4821 regval = ppd->pp_acc_data; 4822 4823 switch (ppd->pp_acc_size) { 4824 case 1: 4825 ddi_put8(bgep->io_handle, regaddr, regval); 4826 break; 4827 4828 case 2: 4829 ddi_put16(bgep->io_handle, regaddr, regval); 4830 break; 4831 4832 case 4: 4833 ddi_put32(bgep->io_handle, regaddr, regval); 4834 break; 4835 4836 case 8: 4837 ddi_put64(bgep->io_handle, regaddr, regval); 4838 break; 4839 } 4840 BGE_PCICHK(bgep); 4841 } 4842 4843 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4844 #pragma no_inline(bge_chip_peek_mii) 4845 4846 static void 4847 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4848 { 4849 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4850 (void *)bgep, (void *)ppd)); 4851 4852 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4853 } 4854 4855 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4856 #pragma no_inline(bge_chip_poke_mii) 4857 4858 static void 4859 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4860 { 4861 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4862 (void *)bgep, (void *)ppd)); 4863 4864 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4865 } 4866 4867 #if BGE_SEE_IO32 4868 4869 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4870 #pragma no_inline(bge_chip_peek_seeprom) 4871 4872 static void 4873 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4874 { 4875 uint32_t data; 4876 int err; 4877 4878 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4879 (void *)bgep, (void *)ppd)); 4880 4881 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4882 ppd->pp_acc_data = err ? ~0ull : data; 4883 } 4884 4885 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4886 #pragma no_inline(bge_chip_poke_seeprom) 4887 4888 static void 4889 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4890 { 4891 uint32_t data; 4892 4893 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4894 (void *)bgep, (void *)ppd)); 4895 4896 data = ppd->pp_acc_data; 4897 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4898 } 4899 #endif /* BGE_SEE_IO32 */ 4900 4901 #if BGE_FLASH_IO32 4902 4903 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4904 #pragma no_inline(bge_chip_peek_flash) 4905 4906 static void 4907 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4908 { 4909 uint32_t data; 4910 int err; 4911 4912 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4913 (void *)bgep, (void *)ppd)); 4914 4915 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4916 ppd->pp_acc_data = err ? ~0ull : data; 4917 } 4918 4919 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4920 #pragma no_inline(bge_chip_poke_flash) 4921 4922 static void 4923 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4924 { 4925 uint32_t data; 4926 4927 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4928 (void *)bgep, (void *)ppd)); 4929 4930 data = ppd->pp_acc_data; 4931 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 4932 ppd->pp_acc_offset, &data); 4933 } 4934 #endif /* BGE_FLASH_IO32 */ 4935 4936 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4937 #pragma no_inline(bge_chip_peek_mem) 4938 4939 static void 4940 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4941 { 4942 uint64_t regval; 4943 void *vaddr; 4944 4945 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 4946 (void *)bgep, (void *)ppd)); 4947 4948 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4949 4950 switch (ppd->pp_acc_size) { 4951 case 1: 4952 regval = *(uint8_t *)vaddr; 4953 break; 4954 4955 case 2: 4956 regval = *(uint16_t *)vaddr; 4957 break; 4958 4959 case 4: 4960 regval = *(uint32_t *)vaddr; 4961 break; 4962 4963 case 8: 4964 regval = *(uint64_t *)vaddr; 4965 break; 4966 } 4967 4968 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 4969 (void *)bgep, (void *)ppd, regval, vaddr)); 4970 4971 ppd->pp_acc_data = regval; 4972 } 4973 4974 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4975 #pragma no_inline(bge_chip_poke_mem) 4976 4977 static void 4978 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4979 { 4980 uint64_t regval; 4981 void *vaddr; 4982 4983 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 4984 (void *)bgep, (void *)ppd)); 4985 4986 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4987 regval = ppd->pp_acc_data; 4988 4989 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 4990 (void *)bgep, (void *)ppd, regval, vaddr)); 4991 4992 switch (ppd->pp_acc_size) { 4993 case 1: 4994 *(uint8_t *)vaddr = (uint8_t)regval; 4995 break; 4996 4997 case 2: 4998 *(uint16_t *)vaddr = (uint16_t)regval; 4999 break; 5000 5001 case 4: 5002 *(uint32_t *)vaddr = (uint32_t)regval; 5003 break; 5004 5005 case 8: 5006 *(uint64_t *)vaddr = (uint64_t)regval; 5007 break; 5008 } 5009 } 5010 5011 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5012 struct iocblk *iocp); 5013 #pragma no_inline(bge_pp_ioctl) 5014 5015 static enum ioc_reply 5016 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5017 { 5018 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 5019 bge_peekpoke_t *ppd; 5020 dma_area_t *areap; 5021 uint64_t sizemask; 5022 uint64_t mem_va; 5023 uint64_t maxoff; 5024 boolean_t peek; 5025 5026 switch (cmd) { 5027 default: 5028 /* NOTREACHED */ 5029 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 5030 return (IOC_INVAL); 5031 5032 case BGE_PEEK: 5033 peek = B_TRUE; 5034 break; 5035 5036 case BGE_POKE: 5037 peek = B_FALSE; 5038 break; 5039 } 5040 5041 /* 5042 * Validate format of ioctl 5043 */ 5044 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 5045 return (IOC_INVAL); 5046 if (mp->b_cont == NULL) 5047 return (IOC_INVAL); 5048 ppd = (bge_peekpoke_t *)mp->b_cont->b_rptr; 5049 5050 /* 5051 * Validate request parameters 5052 */ 5053 switch (ppd->pp_acc_space) { 5054 default: 5055 return (IOC_INVAL); 5056 5057 case BGE_PP_SPACE_CFG: 5058 /* 5059 * Config space 5060 */ 5061 sizemask = 8|4|2|1; 5062 mem_va = 0; 5063 maxoff = PCI_CONF_HDR_SIZE; 5064 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 5065 break; 5066 5067 case BGE_PP_SPACE_REG: 5068 /* 5069 * Memory-mapped I/O space 5070 */ 5071 sizemask = 8|4|2|1; 5072 mem_va = 0; 5073 maxoff = RIAAR_REGISTER_MAX; 5074 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 5075 break; 5076 5077 case BGE_PP_SPACE_NIC: 5078 /* 5079 * NIC on-chip memory 5080 */ 5081 sizemask = 8|4|2|1; 5082 mem_va = 0; 5083 maxoff = MWBAR_ONCHIP_MAX; 5084 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 5085 break; 5086 5087 case BGE_PP_SPACE_MII: 5088 /* 5089 * PHY's MII registers 5090 * NB: all PHY registers are two bytes, but the 5091 * addresses increment in ones (word addressing). 5092 * So we scale the address here, then undo the 5093 * transformation inside the peek/poke functions. 5094 */ 5095 ppd->pp_acc_offset *= 2; 5096 sizemask = 2; 5097 mem_va = 0; 5098 maxoff = (MII_MAXREG+1)*2; 5099 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5100 break; 5101 5102 #if BGE_SEE_IO32 5103 case BGE_PP_SPACE_SEEPROM: 5104 /* 5105 * Attached SEEPROM(s), if any. 5106 * NB: we use the high-order bits of the 'address' as 5107 * a device select to accommodate multiple SEEPROMS, 5108 * If each one is the maximum size (64kbytes), this 5109 * makes them appear contiguous. Otherwise, there may 5110 * be holes in the mapping. ENxS doesn't have any 5111 * SEEPROMs anyway ... 5112 */ 5113 sizemask = 4; 5114 mem_va = 0; 5115 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5116 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5117 break; 5118 #endif /* BGE_SEE_IO32 */ 5119 5120 #if BGE_FLASH_IO32 5121 case BGE_PP_SPACE_FLASH: 5122 /* 5123 * Attached Flash device (if any); a maximum of one device 5124 * is currently supported. But it can be up to 1MB (unlike 5125 * the 64k limit on SEEPROMs) so why would you need more ;-) 5126 */ 5127 sizemask = 4; 5128 mem_va = 0; 5129 maxoff = NVM_FLASH_ADDR_MASK; 5130 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5131 break; 5132 #endif /* BGE_FLASH_IO32 */ 5133 5134 case BGE_PP_SPACE_BGE: 5135 /* 5136 * BGE data structure! 5137 */ 5138 sizemask = 8|4|2|1; 5139 mem_va = (uintptr_t)bgep; 5140 maxoff = sizeof (*bgep); 5141 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5142 break; 5143 5144 case BGE_PP_SPACE_STATUS: 5145 case BGE_PP_SPACE_STATISTICS: 5146 case BGE_PP_SPACE_TXDESC: 5147 case BGE_PP_SPACE_TXBUFF: 5148 case BGE_PP_SPACE_RXDESC: 5149 case BGE_PP_SPACE_RXBUFF: 5150 /* 5151 * Various DMA_AREAs 5152 */ 5153 switch (ppd->pp_acc_space) { 5154 case BGE_PP_SPACE_TXDESC: 5155 areap = &bgep->tx_desc; 5156 break; 5157 case BGE_PP_SPACE_TXBUFF: 5158 areap = &bgep->tx_buff[0]; 5159 break; 5160 case BGE_PP_SPACE_RXDESC: 5161 areap = &bgep->rx_desc[0]; 5162 break; 5163 case BGE_PP_SPACE_RXBUFF: 5164 areap = &bgep->rx_buff[0]; 5165 break; 5166 case BGE_PP_SPACE_STATUS: 5167 areap = &bgep->status_block; 5168 break; 5169 case BGE_PP_SPACE_STATISTICS: 5170 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5171 areap = &bgep->statistics; 5172 break; 5173 } 5174 5175 sizemask = 8|4|2|1; 5176 mem_va = (uintptr_t)areap->mem_va; 5177 maxoff = areap->alength; 5178 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5179 break; 5180 } 5181 5182 switch (ppd->pp_acc_size) { 5183 default: 5184 return (IOC_INVAL); 5185 5186 case 8: 5187 case 4: 5188 case 2: 5189 case 1: 5190 if ((ppd->pp_acc_size & sizemask) == 0) 5191 return (IOC_INVAL); 5192 break; 5193 } 5194 5195 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5196 return (IOC_INVAL); 5197 5198 if (ppd->pp_acc_offset >= maxoff) 5199 return (IOC_INVAL); 5200 5201 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5202 return (IOC_INVAL); 5203 5204 /* 5205 * All OK - go do it! 5206 */ 5207 ppd->pp_acc_offset += mem_va; 5208 (*ppfn)(bgep, ppd); 5209 return (peek ? IOC_REPLY : IOC_ACK); 5210 } 5211 5212 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5213 struct iocblk *iocp); 5214 #pragma no_inline(bge_diag_ioctl) 5215 5216 static enum ioc_reply 5217 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5218 { 5219 ASSERT(mutex_owned(bgep->genlock)); 5220 5221 switch (cmd) { 5222 default: 5223 /* NOTREACHED */ 5224 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5225 return (IOC_INVAL); 5226 5227 case BGE_DIAG: 5228 /* 5229 * Currently a no-op 5230 */ 5231 return (IOC_ACK); 5232 5233 case BGE_PEEK: 5234 case BGE_POKE: 5235 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5236 5237 case BGE_PHY_RESET: 5238 return (IOC_RESTART_ACK); 5239 5240 case BGE_SOFT_RESET: 5241 case BGE_HARD_RESET: 5242 /* 5243 * Reset and reinitialise the 570x hardware 5244 */ 5245 bgep->bge_chip_state = BGE_CHIP_FAULT; 5246 ddi_trigger_softintr(bgep->factotum_id); 5247 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5248 return (IOC_ACK); 5249 } 5250 5251 /* NOTREACHED */ 5252 } 5253 5254 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5255 5256 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5257 struct iocblk *iocp); 5258 #pragma no_inline(bge_mii_ioctl) 5259 5260 static enum ioc_reply 5261 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5262 { 5263 struct bge_mii_rw *miirwp; 5264 5265 /* 5266 * Validate format of ioctl 5267 */ 5268 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5269 return (IOC_INVAL); 5270 if (mp->b_cont == NULL) 5271 return (IOC_INVAL); 5272 miirwp = (struct bge_mii_rw *)mp->b_cont->b_rptr; 5273 5274 /* 5275 * Validate request parameters ... 5276 */ 5277 if (miirwp->mii_reg > MII_MAXREG) 5278 return (IOC_INVAL); 5279 5280 switch (cmd) { 5281 default: 5282 /* NOTREACHED */ 5283 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5284 return (IOC_INVAL); 5285 5286 case BGE_MII_READ: 5287 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5288 return (IOC_REPLY); 5289 5290 case BGE_MII_WRITE: 5291 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5292 return (IOC_ACK); 5293 } 5294 5295 /* NOTREACHED */ 5296 } 5297 5298 #if BGE_SEE_IO32 5299 5300 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5301 struct iocblk *iocp); 5302 #pragma no_inline(bge_see_ioctl) 5303 5304 static enum ioc_reply 5305 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5306 { 5307 struct bge_see_rw *seerwp; 5308 5309 /* 5310 * Validate format of ioctl 5311 */ 5312 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5313 return (IOC_INVAL); 5314 if (mp->b_cont == NULL) 5315 return (IOC_INVAL); 5316 seerwp = (struct bge_see_rw *)mp->b_cont->b_rptr; 5317 5318 /* 5319 * Validate request parameters ... 5320 */ 5321 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5322 return (IOC_INVAL); 5323 5324 switch (cmd) { 5325 default: 5326 /* NOTREACHED */ 5327 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5328 return (IOC_INVAL); 5329 5330 case BGE_SEE_READ: 5331 case BGE_SEE_WRITE: 5332 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5333 seerwp->see_addr, &seerwp->see_data); 5334 return (IOC_REPLY); 5335 } 5336 5337 /* NOTREACHED */ 5338 } 5339 5340 #endif /* BGE_SEE_IO32 */ 5341 5342 #if BGE_FLASH_IO32 5343 5344 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5345 struct iocblk *iocp); 5346 #pragma no_inline(bge_flash_ioctl) 5347 5348 static enum ioc_reply 5349 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5350 { 5351 struct bge_flash_rw *flashrwp; 5352 5353 /* 5354 * Validate format of ioctl 5355 */ 5356 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5357 return (IOC_INVAL); 5358 if (mp->b_cont == NULL) 5359 return (IOC_INVAL); 5360 flashrwp = (struct bge_flash_rw *)mp->b_cont->b_rptr; 5361 5362 /* 5363 * Validate request parameters ... 5364 */ 5365 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5366 return (IOC_INVAL); 5367 5368 switch (cmd) { 5369 default: 5370 /* NOTREACHED */ 5371 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5372 return (IOC_INVAL); 5373 5374 case BGE_FLASH_READ: 5375 case BGE_FLASH_WRITE: 5376 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5377 flashrwp->flash_addr, &flashrwp->flash_data); 5378 return (IOC_REPLY); 5379 } 5380 5381 /* NOTREACHED */ 5382 } 5383 5384 #endif /* BGE_FLASH_IO32 */ 5385 5386 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5387 struct iocblk *iocp); 5388 #pragma no_inline(bge_chip_ioctl) 5389 5390 enum ioc_reply 5391 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5392 { 5393 int cmd; 5394 5395 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5396 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5397 5398 ASSERT(mutex_owned(bgep->genlock)); 5399 5400 cmd = iocp->ioc_cmd; 5401 switch (cmd) { 5402 default: 5403 /* NOTREACHED */ 5404 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5405 return (IOC_INVAL); 5406 5407 case BGE_DIAG: 5408 case BGE_PEEK: 5409 case BGE_POKE: 5410 case BGE_PHY_RESET: 5411 case BGE_SOFT_RESET: 5412 case BGE_HARD_RESET: 5413 #if BGE_DEBUGGING || BGE_DO_PPIO 5414 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5415 #else 5416 return (IOC_INVAL); 5417 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5418 5419 case BGE_MII_READ: 5420 case BGE_MII_WRITE: 5421 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5422 5423 #if BGE_SEE_IO32 5424 case BGE_SEE_READ: 5425 case BGE_SEE_WRITE: 5426 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5427 #endif /* BGE_SEE_IO32 */ 5428 5429 #if BGE_FLASH_IO32 5430 case BGE_FLASH_READ: 5431 case BGE_FLASH_WRITE: 5432 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5433 #endif /* BGE_FLASH_IO32 */ 5434 } 5435 5436 /* NOTREACHED */ 5437 } 5438 5439 void 5440 bge_chip_blank(void *arg, time_t ticks, uint_t count) 5441 { 5442 bge_t *bgep = arg; 5443 5444 mutex_enter(bgep->genlock); 5445 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5446 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5447 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5448 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5449 mutex_exit(bgep->genlock); 5450 } 5451 5452 #ifdef BGE_IPMI_ASF 5453 5454 uint32_t 5455 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5456 { 5457 uint32_t data; 5458 5459 #ifndef __sparc 5460 if (!bgep->asf_wordswapped) { 5461 /* a workaround word swap error */ 5462 if (addr & 4) 5463 addr = addr - 4; 5464 else 5465 addr = addr + 4; 5466 } 5467 #endif 5468 5469 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5470 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5471 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5472 5473 data = LE_32(data); 5474 return (data); 5475 } 5476 5477 void 5478 bge_asf_update_status(bge_t *bgep) 5479 { 5480 uint32_t event; 5481 5482 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5483 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5484 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5485 5486 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5487 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5488 } 5489 5490 5491 /* 5492 * The driver is supposed to notify ASF that the OS is still running 5493 * every three seconds, otherwise the management server may attempt 5494 * to reboot the machine. If it hasn't actually failed, this is 5495 * not a desirable result. However, this isn't running as a real-time 5496 * thread, and even if it were, it might not be able to generate the 5497 * heartbeat in a timely manner due to system load. As it isn't a 5498 * significant strain on the machine, we will set the interval to half 5499 * of the required value. 5500 */ 5501 void 5502 bge_asf_heartbeat(void *arg) 5503 { 5504 bge_t *bgep = (bge_t *)arg; 5505 5506 mutex_enter(bgep->genlock); 5507 bge_asf_update_status((bge_t *)bgep); 5508 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5509 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5510 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5511 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5512 mutex_exit(bgep->genlock); 5513 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5514 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5515 } 5516 5517 5518 void 5519 bge_asf_stop_timer(bge_t *bgep) 5520 { 5521 timeout_id_t tmp_id = 0; 5522 5523 while ((bgep->asf_timeout_id != 0) && 5524 (tmp_id != bgep->asf_timeout_id)) { 5525 tmp_id = bgep->asf_timeout_id; 5526 (void) untimeout(tmp_id); 5527 } 5528 bgep->asf_timeout_id = 0; 5529 } 5530 5531 5532 5533 /* 5534 * This function should be placed at the earliest position of bge_attach(). 5535 */ 5536 void 5537 bge_asf_get_config(bge_t *bgep) 5538 { 5539 uint32_t nicsig; 5540 uint32_t niccfg; 5541 5542 bgep->asf_enabled = B_FALSE; 5543 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5544 if (nicsig == BGE_NIC_DATA_SIG) { 5545 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5546 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5547 /* 5548 * Here, we don't consider BAXTER, because BGE haven't 5549 * supported BAXTER (that is 5752). Also, as I know, 5550 * BAXTER doesn't support ASF feature. 5551 */ 5552 bgep->asf_enabled = B_TRUE; 5553 else 5554 bgep->asf_enabled = B_FALSE; 5555 } else 5556 bgep->asf_enabled = B_FALSE; 5557 } 5558 5559 5560 void 5561 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5562 { 5563 uint32_t tries; 5564 uint32_t event; 5565 5566 ASSERT(bgep->asf_enabled); 5567 5568 /* Issues "pause firmware" command and wait for ACK */ 5569 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5570 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5571 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5572 5573 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5574 tries = 0; 5575 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5576 drv_usecwait(1); 5577 tries ++; 5578 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5579 } 5580 5581 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5582 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5583 5584 if (bgep->asf_newhandshake) { 5585 switch (mode) { 5586 case BGE_INIT_RESET: 5587 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5588 BGE_DRV_STATE_START); 5589 break; 5590 case BGE_SHUTDOWN_RESET: 5591 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5592 BGE_DRV_STATE_UNLOAD); 5593 break; 5594 case BGE_SUSPEND_RESET: 5595 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5596 BGE_DRV_STATE_SUSPEND); 5597 break; 5598 default: 5599 break; 5600 } 5601 } 5602 } 5603 5604 5605 void 5606 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5607 { 5608 switch (mode) { 5609 case BGE_INIT_RESET: 5610 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5611 BGE_DRV_STATE_START); 5612 break; 5613 case BGE_SHUTDOWN_RESET: 5614 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5615 BGE_DRV_STATE_UNLOAD); 5616 break; 5617 case BGE_SUSPEND_RESET: 5618 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5619 BGE_DRV_STATE_SUSPEND); 5620 break; 5621 default: 5622 break; 5623 } 5624 } 5625 5626 5627 void 5628 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5629 { 5630 switch (mode) { 5631 case BGE_INIT_RESET: 5632 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5633 BGE_DRV_STATE_START_DONE); 5634 break; 5635 case BGE_SHUTDOWN_RESET: 5636 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5637 BGE_DRV_STATE_UNLOAD_DONE); 5638 break; 5639 default: 5640 break; 5641 } 5642 } 5643 5644 #endif /* BGE_IPMI_ASF */ 5645