1 /* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting, Atheros 3 * Communications, Inc. All rights reserved. 4 * 5 * Use is subject to license terms. 6 * 7 * Redistribution and use in source and binary forms are permitted 8 * provided that the following conditions are met: 9 * 1. The materials contained herein are unmodified and are used 10 * unmodified. 11 * 2. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following NO 13 * ''WARRANTY'' disclaimer below (''Disclaimer''), without 14 * modification. 15 * 3. Redistributions in binary form must reproduce at minimum a 16 * disclaimer similar to the Disclaimer below and any redistribution 17 * must be conditioned upon including a substantially similar 18 * Disclaimer requirement for further binary redistribution. 19 * 4. Neither the names of the above-listed copyright holders nor the 20 * names of any contributors may be used to endorse or promote 21 * product derived from this software without specific prior written 22 * permission. 23 * 24 * NO WARRANTY 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, 28 * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE 30 * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 32 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 33 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 35 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGES. 37 * 38 */ 39 40 #ifndef _ATH_HAL_H 41 #define _ATH_HAL_H 42 43 /* 44 * ath_hal.h is released by Atheros and used to describe the Atheros 45 * Hardware Access Layer(HAL) interface. All kinds of data structures, 46 * constant definition, APIs declaration are defined here.Clients of 47 * the HAL call ath_hal_attach() to obtain a reference to an ath_hal 48 * structure for use with the device. Hardware-related operations that 49 * follow must call back into the HAL through interface, supplying the 50 * reference as the first parameter. 51 */ 52 53 #ifdef __cplusplus 54 extern "C" { 55 #endif 56 57 /* HAL version of this release */ 58 #define HAL_ABI_VERSION 0x08052700 /* YYMMDDnn */ 59 60 /* HAL data type definition */ 61 typedef void * HAL_SOFTC; /* pointer to driver/OS state */ 62 typedef void * HAL_BUS_TAG; /* opaque bus i/o id tag */ 63 typedef void * HAL_BUS_HANDLE; /* opaque bus i/o handle */ 64 typedef uint32_t HAL_BUS_ADDR; 65 typedef uint16_t HAL_CTRY_CODE; /* country code */ 66 typedef uint16_t HAL_REG_DOMAIN; /* regulatory domain code */ 67 68 #define HAL_NUM_TX_QUEUES 10 /* max number of tx queues */ 69 70 #define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ 71 #define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ 72 #define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ 73 74 #define CHANNEL_RAD_INT 0x00001 /* Radar interference detected on channel */ 75 #define CHANNEL_CW_INT 0x00002 /* CW interference detected on channel */ 76 #define CHANNEL_BUSY 0x00004 /* Busy, occupied or overlap with adjoin chan */ 77 #define CHANNEL_TURBO 0x00010 /* Turbo Channel */ 78 #define CHANNEL_CCK 0x00020 /* CCK channel */ 79 #define CHANNEL_OFDM 0x00040 /* OFDM channel */ 80 #define CHANNEL_2GHZ 0x00080 /* 2 GHz spectrum channel. */ 81 #define CHANNEL_5GHZ 0x00100 /* 5 GHz spectrum channel */ 82 #define CHANNEL_PASSIVE 0x00200 /* Only passive scan allowed in the channel */ 83 #define CHANNEL_DYN 0x00400 /* dynamic CCK-OFDM channel */ 84 #define CHANNEL_XR 0x00800 /* XR channel */ 85 #define CHANNEL_STURBO 0x02000 /* Static turbo, no 11a-only usage */ 86 #define CHANNEL_HALF 0x04000 /* Half rate channel */ 87 #define CHANNEL_QUARTER 0x08000 /* Quarter rate channel */ 88 #define CHANNEL_HT20 0x10000 /* 11n 20MHZ channel */ 89 #define CHANNEL_HT40PLUS 0x20000 /* 11n 40MHZ chan w/ ext chan above */ 90 #define CHANNEL_HT40MINUS 0x40000 /* 11n 40MHZ chan w/ ext chan below */ 91 92 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 93 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 94 #define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM) 95 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 96 #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 97 #define CHANNEL_ST (CHANNEL_T|CHANNEL_STURBO) 98 #define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) 99 #define CHANNEL_108A CHANNEL_T 100 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) 101 #define CHANNEL_G_HT20 (CHANNEL_G|CHANNEL_HT20) 102 #define CHANNEL_A_HT20 (CHANNEL_A|CHANNEL_HT20) 103 #define CHANNEL_G_HT40PLUS (CHANNEL_G_HT20|CHANNEL_HT40PLUS) 104 #define CHANNEL_A_HT40PLUS (CHANNEL_A_HT20|CHANNEL_HT40PLUS) 105 #define CHANNEL_A_HT40MINUS (CHANNEL_A_HT20|CHANNEL_HT40MINUS) 106 #define CHANNEL_ALL \ 107 (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_5GHZ|CHANNEL_2GHZ| \ 108 CHANNEL_TURBO|CHANNEL_HT20|CHANNEL_HT40PLUS|CHANNEL_HT40MINUS) 109 #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) 110 111 #define CHANNEL_COMPAT (CHANNEL_ALL_NOTURBO | CHANNEL_PASSIVE) 112 113 /* privFlags */ 114 /* 115 * Software use: channel interference used for AR as well as RADAR 116 * interference detection 117 */ 118 #define CHANNEL_INTERFERENCE 0x01 119 #define CHANNEL_DFS 0x02 /* DFS required on channel */ 120 #define CHANNEL_4MS_LIMIT 0x04 /* 4msec packet limit on this channel */ 121 #define CHANNEL_DFS_CLEAR 0x08 /* if channel has been checked DFS */ 122 123 #define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ 124 125 /* flags passed to tx descriptor setup methods */ 126 #define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */ 127 #define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */ 128 #define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */ 129 #define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */ 130 #define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */ 131 #define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */ 132 /* NB: this only affects frame, not any RTS/CTS */ 133 #define HAL_TXDESC_DURENA 0x0040 /* enable h/w write of duration field */ 134 #define HAL_TXDESC_EXT_ONLY 0x0080 /* send on ext channel only (11n) */ 135 #define HAL_TXDESC_EXT_AND_CTL 0x0100 /* send on ext + ctl channels (11n) */ 136 #define HAL_TXDESC_VMF 0x0200 /* virtual more frag */ 137 138 /* flags passed to rx descriptor setup methods */ 139 #define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */ 140 141 /* tx error flags */ 142 #define HAL_TXERR_XRETRY 0x01 /* excessive retries */ 143 #define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */ 144 #define HAL_TXERR_FIFO 0x04 /* fifo underrun */ 145 #define HAL_TXERR_XTXOP 0x08 /* txop exceeded */ 146 #define HAL_TXERR_DESC_CFG_ERR 0x10 /* Error in 20/40 desc config */ 147 #define HAL_TXERR_DATA_UNDERRUN 0x20 /* Tx buffer underrun */ 148 #define HAL_TXERR_DELIM_UNDERRUN 0x40 /* Tx delimiter underrun */ 149 #define HAL_TXSTAT_ALTRATE 0x80 /* alternate xmit rate used */ 150 151 /* bits found in ts_flags */ 152 #define HAL_TX_BA 0x01 /* Block Ack seen */ 153 #define HAL_TX_AGGR 0x02 /* Aggregate */ 154 155 /* rx error flags */ 156 #define HAL_RXERR_CRC 0x01 /* CRC error on frame */ 157 #define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */ 158 #define HAL_RXERR_FIFO 0x04 /* fifo overrun */ 159 #define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */ 160 #define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */ 161 162 /* bits found in rs_flags */ 163 #define HAL_RX_MORE 0x01 /* more descriptors follow */ 164 #define HAL_RX_MORE_AGGR 0x02 /* more frames in aggr */ 165 #define HAL_RX_GI 0x04 /* full gi */ 166 #define HAL_RX_2040 0x08 /* 40 Mhz */ 167 #define HAL_RX_DELIM_CRC_PRE 0x10 /* crc error in delimiter pre */ 168 #define HAL_RX_DELIM_CRC_POST 0x20 /* crc error in delim after */ 169 #define HAL_RX_DECRYPT_BUSY 0x40 /* decrypt was too slow */ 170 #define HAL_RX_DUP_FRAME 0x80 /* Dup frame rx'd on control channel */ 171 172 /* value found in rs_keyix to mark invalid entries */ 173 #define HAL_RXKEYIX_INVALID ((uint8_t)-1) 174 175 /* value used to specify no encryption key for xmit */ 176 #define HAL_TXKEYIX_INVALID ((uint32_t)-1) 177 178 /* compression definitions */ 179 #define HAL_COMP_BUF_MAX_SIZE 9216 /* 9k */ 180 #define HAL_COMP_BUF_ALIGN_SIZE 512 181 182 #define HAL_ANTENNA_MIN_MODE 0 183 #define HAL_ANTENNA_FIXED_A 1 184 #define HAL_ANTENNA_FIXED_B 2 185 #define HAL_ANTENNA_MAX_MODE 3 186 187 /* 188 * Status codes that may be returned by the HAL. Note that 189 * interfaces that return a status code set it only when an 190 * error occurs--i.e. you cannot check it for success. 191 */ 192 typedef enum { 193 HAL_OK = 0, /* No error */ 194 HAL_ENXIO = 1, /* No hardware present */ 195 HAL_ENOMEM = 2, /* Memory allocation failed */ 196 HAL_EIO = 3, /* Hardware didn't respond as expected */ 197 HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ 198 HAL_EEVERSION = 5, /* EEPROM version invalid */ 199 HAL_EELOCKED = 6, /* EEPROM unreadable */ 200 HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ 201 HAL_EEREAD = 8, /* EEPROM read problem */ 202 HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ 203 HAL_EESIZE = 10, /* EEPROM size not supported */ 204 HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ 205 HAL_EINVAL = 12, /* Invalid parameter to function */ 206 HAL_ENOTSUPP = 13, /* Hardware revision not supported */ 207 HAL_ESELFTEST = 14, /* Hardware self-test failed */ 208 HAL_EINPROGRESS = 15 /* Operation incomplete */ 209 } HAL_STATUS; 210 211 typedef enum { 212 AH_FALSE = 0, /* NB: lots of code assumes false is zero */ 213 AH_TRUE = 1 214 } HAL_BOOL; 215 216 typedef enum { 217 HAL_CAP_REG_DMN = 0, /* current regulatory domain */ 218 HAL_CAP_CIPHER = 1, /* hardware supports cipher */ 219 HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ 220 HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ 221 HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ 222 HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ 223 HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ 224 HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ 225 HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ 226 HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll */ 227 /* support */ 228 HAL_CAP_DIAG = 11, /* hardware diagnostic support */ 229 HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ 230 HAL_CAP_BURST = 13, /* hardware supports packet bursting */ 231 HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ 232 HAL_CAP_TXPOW = 15, /* global tx power limit */ 233 HAL_CAP_TPC = 16, /* per-packet tx power control */ 234 HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ 235 HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ 236 HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ 237 HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ 238 HAL_CAP_XR = 21, /* hardware has XR support */ 239 /* hardware can support TKIP MIC when WMM is turned on */ 240 HAL_CAP_WME_TKIPMIC = 22, 241 /* hardware can support half rate channels */ 242 HAL_CAP_CHAN_HALFRATE = 23, 243 /* hardware can support quarter rate channels */ 244 HAL_CAP_CHAN_QUARTERRATE = 24, 245 HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ 246 HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ 247 HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ 248 HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ 249 HAL_CAP_INTMIT = 29, /* interference mitigation */ 250 HAL_CAP_RXORN_FATAL = 30, /* HAL_INT_RXORN treated as fatal */ 251 HAL_CAP_HT = 31, /* hardware can support HT */ 252 HAL_CAP_NUMTXCHAIN = 32, /* TX chains supported */ 253 HAL_CAP_NUMRXCHAIN = 33, /* RX chains supported */ 254 HAL_CAP_RXTSTAMP_PREC = 34 /* rx desc tstamp precision (bits) */ 255 } HAL_CAPABILITY_TYPE; 256 257 /* 258 * "States" for setting the LED. These correspond to 259 * the possible 802.11 operational states and there may 260 * be a many-to-one mapping between these states and the 261 * actual hardware states for the LED's (i.e. the hardware 262 * may have fewer states). 263 */ 264 typedef enum { 265 HAL_LED_INIT = 0, 266 HAL_LED_SCAN = 1, 267 HAL_LED_AUTH = 2, 268 HAL_LED_ASSOC = 3, 269 HAL_LED_RUN = 4 270 } HAL_LED_STATE; 271 272 /* 273 * Transmit queue types/numbers. These are used to tag 274 * each transmit queue in the hardware and to identify a set 275 * of transmit queues for operations such as start/stop dma. 276 */ 277 typedef enum { 278 HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ 279 HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ 280 HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ 281 HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ 282 HAL_TX_QUEUE_UAPSD = 4 /* u-apsd power save xmit q */ 283 } HAL_TX_QUEUE; 284 285 286 /* 287 * Transmit queue subtype. These map directly to 288 * WME Access Categories (except for UPSD). Refer 289 * to Table 5 of the WME spec. 290 */ 291 typedef enum { 292 HAL_WME_AC_BK = 0, /* background access category */ 293 HAL_WME_AC_BE = 1, /* best effort access category */ 294 HAL_WME_AC_VI = 2, /* video access category */ 295 HAL_WME_AC_VO = 3, /* voice access category */ 296 HAL_WME_UPSD = 4, /* uplink power save */ 297 HAL_XR_DATA = 5 /* entended range data */ 298 } HAL_TX_QUEUE_SUBTYPE; 299 300 /* 301 * Transmit queue flags that control various 302 * operational parameters. 303 */ 304 typedef enum { 305 /* 306 * Per queue interrupt enables. When set the associated 307 * interrupt may be delivered for packets sent through 308 * the queue. Without these enabled no interrupts will 309 * be delivered for transmits through the queue. 310 * 311 * When 0x0001 is set, both TXQ_TXOKINT and TXQ_TXERRINT 312 * will be enabled. 313 */ 314 HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ 315 HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ 316 HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ 317 HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ 318 HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ 319 /* 320 * Enable hardware compression for packets sent through 321 * the queue. The compression buffer must be setup and 322 * packets must have a key entry marked in the tx descriptor. 323 */ 324 HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ 325 /* 326 * Disable queue when veol is hit or ready time expires. 327 * By default the queue is disabled only on reaching the 328 * physical end of queue (i.e. a null link ptr in the 329 * descriptor chain). 330 */ 331 HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, 332 /* 333 * Schedule frames on delivery of a DBA (DMA Beacon Alert) 334 * event. Frames will be transmitted only when this timer 335 * fires, e.g to transmit a beacon in ap or adhoc modes. 336 */ 337 HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ 338 /* 339 * Each transmit queue has a counter that is incremented 340 * each time the queue is enabled and decremented when 341 * the list of frames to transmit is traversed (or when 342 * the ready time for the queue expires). This counter 343 * must be non-zero for frames to be scheduled for 344 * transmission. The following controls disable bumping 345 * this counter under certain conditions. Typically this 346 * is used to gate frames based on the contents of another 347 * queue (e.g. CAB traffic may only follow a beacon frame). 348 * These are meaningful only when frames are scheduled 349 * with a non-ASAP policy (e.g. DBA-gated). 350 */ 351 HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ 352 HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ 353 354 /* 355 * Fragment burst backoff policy. Normally no backoff 356 * is done after a successful transmission, the next fragment 357 * is sent at SIFS. If this flag is set backoff is done 358 * after each fragment, regardless whether it was ack'd or 359 * not, after the backoff count reaches zero a normal channel 360 * access procedure is done before the next transmit (i.e. 361 * wait AIFS instead of SIFS). 362 */ 363 HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, 364 /* 365 * Disable post-tx backoff following each frame. 366 */ 367 HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ 368 /* 369 * DCU arbiter lockout control. This controls how 370 * lower priority tx queues are handled with respect 371 * to a specific queue when multiple queues have frames 372 * to send. No lockout means lower priority queues arbitrate 373 * concurrently with this queue. Intra-frame lockout 374 * means lower priority queues are locked out until the 375 * current frame transmits (e.g. including backoffs and bursting). 376 * Global lockout means nothing lower can arbitrary so 377 * long as there is traffic activity on this queue (frames, 378 * backoff, etc). 379 */ 380 HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ 381 HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ 382 383 HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ 384 HAL_TXQ_SEQNUM_INC_DIS = 0x00100000 /* disable seqnum increment */ 385 } HAL_TX_QUEUE_FLAGS; 386 387 typedef struct { 388 uint32_t tqi_ver; /* hal TXQ version */ 389 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ 390 HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ 391 uint32_t tqi_priority; /* (not used) */ 392 uint32_t tqi_aifs; /* AIFS shift */ 393 int32_t tqi_cwmin; /* cwMin shift */ 394 int32_t tqi_cwmax; /* cwMax shift */ 395 uint16_t tqi_shretry; /* rts retry limit */ 396 uint16_t tqi_lgretry; /* long retry limit(not used) */ 397 uint32_t tqi_cbrPeriod; 398 uint32_t tqi_cbrOverflowLimit; 399 uint32_t tqi_burstTime; 400 uint32_t tqi_readyTime; 401 uint32_t tqi_compBuf; /* compress buffer phys addr */ 402 } HAL_TXQ_INFO; 403 404 #define HAL_TQI_NONVAL 0xffff 405 406 /* token to use for aifs, cwmin, cwmax */ 407 #define HAL_TXQ_USEDEFAULT ((uint32_t)-1) 408 409 /* 410 * Transmit packet types. This belongs in ah_desc.h, but 411 * is here so we can give a proper type to various parameters 412 * (and not require everyone include the file). 413 * 414 * NB: These values are intentionally assigned for 415 * direct use when setting up h/w descriptors. 416 */ 417 typedef enum { 418 HAL_PKT_TYPE_NORMAL = 0, 419 HAL_PKT_TYPE_ATIM = 1, 420 HAL_PKT_TYPE_PSPOLL = 2, 421 HAL_PKT_TYPE_BEACON = 3, 422 HAL_PKT_TYPE_PROBE_RESP = 4, 423 HAL_PKT_TYPE_CHIRP = 5, 424 HAL_PKT_TYPE_GRP_POLL = 6, 425 HAL_PKT_TYPE_AMPDU = 7 426 } HAL_PKT_TYPE; 427 428 /* Rx Filter Frame Types */ 429 typedef enum { 430 HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ 431 HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ 432 HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ 433 HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ 434 HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ 435 HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ 436 HAL_RX_FILTER_XRPOLL = 0x00000040, /* Allow XR poll frmae */ 437 HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ 438 HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ 439 HAL_RX_FILTER_PHYRADAR = 0x00000200 /* Allow phy radar errors */ 440 } HAL_RX_FILTER; 441 442 typedef enum { 443 HAL_PM_AWAKE = 0, 444 HAL_PM_FULL_SLEEP = 1, 445 HAL_PM_NETWORK_SLEEP = 2, 446 HAL_PM_UNDEFINED = 3 447 } HAL_POWER_MODE; 448 449 /* 450 * NOTE WELL: 451 * These are mapped to take advantage of the common locations for many of 452 * the bits on all of the currently supported MAC chips. This is to make 453 * the ISR as efficient as possible, while still abstracting HW differences. 454 * When new hardware breaks this commonality this enumerated type, as well 455 * as the HAL functions using it, must be modified. All values are directly 456 * mapped unless commented otherwise. 457 */ 458 typedef enum { 459 HAL_INT_RX = 0x00000001, /* Non-common mapping */ 460 HAL_INT_RXDESC = 0x00000002, 461 HAL_INT_RXNOFRM = 0x00000008, 462 HAL_INT_RXEOL = 0x00000010, 463 HAL_INT_RXORN = 0x00000020, 464 HAL_INT_TX = 0x00000040, /* Non-common mapping */ 465 HAL_INT_TXDESC = 0x00000080, 466 HAL_INT_TXURN = 0x00000800, 467 HAL_INT_MIB = 0x00001000, 468 HAL_INT_RXPHY = 0x00004000, 469 HAL_INT_RXKCM = 0x00008000, 470 HAL_INT_SWBA = 0x00010000, 471 HAL_INT_BMISS = 0x00040000, 472 HAL_INT_BNR = 0x00100000, /* Non-common mapping */ 473 HAL_INT_TIM = 0x00200000, /* Non-common mapping */ 474 HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ 475 HAL_INT_DTIMSYNC = 0x00800000, /* Non-common mapping */ 476 HAL_INT_GPIO = 0x01000000, 477 HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ 478 HAL_INT_CST = 0x10000000, /* Non-common mapping */ 479 HAL_INT_GTT = 0x20000000, /* Non-common mapping */ 480 HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ 481 HAL_INT_GLOBAL = INT_MIN, /* Set/clear IER */ 482 HAL_INT_BMISC = HAL_INT_TIM 483 | HAL_INT_DTIM 484 | HAL_INT_DTIMSYNC 485 | HAL_INT_CABEND, 486 487 /* Interrupt bits that map directly to ISR/IMR bits */ 488 HAL_INT_COMMON = HAL_INT_RXNOFRM 489 | HAL_INT_RXDESC 490 | HAL_INT_RXEOL 491 | HAL_INT_RXORN 492 | HAL_INT_TXURN 493 | HAL_INT_TXDESC 494 | HAL_INT_MIB 495 | HAL_INT_RXPHY 496 | HAL_INT_RXKCM 497 | HAL_INT_SWBA 498 | HAL_INT_BMISS 499 | HAL_INT_GPIO, 500 } HAL_INT; 501 502 typedef enum { 503 HAL_RFGAIN_INACTIVE = 0, 504 HAL_RFGAIN_READ_REQUESTED = 1, 505 HAL_RFGAIN_NEED_CHANGE = 2 506 } HAL_RFGAIN; 507 508 typedef enum { 509 HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */ 510 HAL_PHYERR_TIMING = 1, /* Timing error */ 511 HAL_PHYERR_PARITY = 2, /* Illegal parity */ 512 HAL_PHYERR_RATE = 3, /* Illegal rate */ 513 HAL_PHYERR_LENGTH = 4, /* Illegal length */ 514 HAL_PHYERR_RADAR = 5, /* Radar detect */ 515 HAL_PHYERR_SERVICE = 6, /* Illegal service */ 516 HAL_PHYERR_TOR = 7, /* Transmit override receive */ 517 /* NB: these are specific to the 5212 */ 518 HAL_PHYERR_OFDM_TIMING = 17, /* */ 519 HAL_PHYERR_OFDM_SIGNAL_PARITY = 18, /* */ 520 HAL_PHYERR_OFDM_RATE_ILLEGAL = 19, /* */ 521 HAL_PHYERR_OFDM_LENGTH_ILLEGAL = 20, /* */ 522 HAL_PHYERR_OFDM_POWER_DROP = 21, /* */ 523 HAL_PHYERR_OFDM_SERVICE = 22, /* */ 524 HAL_PHYERR_OFDM_RESTART = 23, /* */ 525 HAL_PHYERR_CCK_TIMING = 25, /* */ 526 HAL_PHYERR_CCK_HEADER_CRC = 26, /* */ 527 HAL_PHYERR_CCK_RATE_ILLEGAL = 27, /* */ 528 HAL_PHYERR_CCK_SERVICE = 30, /* */ 529 HAL_PHYERR_CCK_RESTART = 31 /* */ 530 }HAL_PHYERR; 531 532 /* 533 * Channels are specified by frequency. 534 */ 535 typedef struct { 536 uint32_t channelFlags; 537 uint16_t channel; /* setting in Mhz */ 538 uint8_t privFlags; 539 int8_t maxRegTxPower; /* max regulatory tx power in dBm */ 540 int8_t maxTxPower; /* max true tx power in 0.5 dBm */ 541 int8_t minTxPower; /* min true tx power in 0.5 dBm */ 542 } HAL_CHANNEL; 543 544 545 typedef struct { 546 uint32_t ackrcv_bad; 547 uint32_t rts_bad; 548 uint32_t rts_good; 549 uint32_t fcs_bad; 550 uint32_t beacons; 551 } HAL_MIB_STATS; 552 553 554 enum { 555 CTRY_DEBUG = 0x1ff, /* debug country code */ 556 CTRY_DEFAULT = 0 /* default country code */ 557 }; 558 559 enum { 560 HAL_MODE_11A = 0x001, /* 11a channels */ 561 HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ 562 HAL_MODE_11B = 0x004, /* 11b channels */ 563 HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ 564 HAL_MODE_11G = 0x008, /* XXX historical */ 565 HAL_MODE_108G = 0x020, /* 11g+Turbo channels */ 566 HAL_MODE_108A = 0x040, /* 11a+Turbo channels */ 567 HAL_MODE_XR = 0x100, /* XR channels */ 568 HAL_MODE_11A_HALF_RATE = 0x200, /* 11A half rate channels */ 569 HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11A quarter rate channels */ 570 HAL_MODE_11NG_HT20 = 0x8000, 571 HAL_MODE_11NA_HT20 = 0x10000, 572 HAL_MODE_11NG_HT40PLUS = 0x20000, 573 HAL_MODE_11NG_HT40MINUS = 0x40000, 574 HAL_MODE_11NA_HT40PLUS = 0x80000, 575 HAL_MODE_11NA_HT40MINUS = 0x100000, 576 HAL_MODE_ALL = 0xffffff 577 }; 578 579 typedef struct { 580 int rateCount; /* NB: for proper padding */ 581 uint8_t rateCodeToIndex[144]; /* back mapping */ 582 struct { 583 uint8_t valid; /* valid for rate control use */ 584 uint8_t phy; /* CCK/OFDM/XR */ 585 uint32_t rateKbps; /* transfer rate in kbs */ 586 uint8_t rateCode; /* rate for h/w descriptors */ 587 /* mask for enabling short preamble in CCK rate code */ 588 uint8_t shortPreamble; 589 /* value for supported rates info element of MLME */ 590 uint8_t dot11Rate; 591 /* index of next lower basic rate; used for dur. calcs */ 592 uint8_t controlRate; 593 uint16_t lpAckDuration; /* long preamble ACK duration */ 594 uint16_t spAckDuration; /* short preamble ACK duration */ 595 } info[32]; 596 } HAL_RATE_TABLE; 597 598 typedef struct { 599 uint32_t rs_count; /* number of valid entries */ 600 uint8_t rs_rates[32]; /* rates */ 601 } HAL_RATE_SET; 602 603 /* 604 * 802.11n specific structures and enums 605 */ 606 typedef enum { 607 HAL_CHAINTYPE_TX = 1, /* Tx chain type */ 608 HAL_CHAINTYPE_RX = 2, /* RX chain type */ 609 } HAL_CHAIN_TYPE; 610 611 typedef struct { 612 uint_t Tries; 613 uint_t Rate; 614 uint_t PktDuration; 615 uint_t ChSel; 616 uint_t RateFlags; 617 #define HAL_RATESERIES_RTS_CTS 0x0001 /* use rts/cts w/this series */ 618 #define HAL_RATESERIES_2040 0x0002 /* use ext channel for series */ 619 #define HAL_RATESERIES_HALFGI 0x0004 /* use half-gi for series */ 620 } HAL_11N_RATE_SERIES; 621 622 typedef enum { 623 HAL_HT_MACMODE_20 = 0, /* 20 MHz operation */ 624 HAL_HT_MACMODE_2040 = 1 /* 20/40 MHz operation */ 625 } HAL_HT_MACMODE; 626 627 typedef enum { 628 HAL_HT_PHYMODE_20 = 0, /* 20 MHz operation */ 629 HAL_HT_PHYMODE_2040 = 1 /* 20/40 MHz operation */ 630 } HAL_HT_PHYMODE; 631 632 typedef enum { 633 HAL_HT_EXTPROTSPACING_20 = 0, /* 20 MHz spacing */ 634 HAL_HT_EXTPROTSPACING_25 = 1 /* 25 MHz spacing */ 635 } HAL_HT_EXTPROTSPACING; 636 637 typedef enum { 638 HAL_RX_CLEAR_CTL_LOW = 1, /* force control chan to appear busy */ 639 HAL_RX_CLEAR_EXT_LOW = 2 /* force ext chan to appear busy */ 640 } HAL_HT_RXCLEAR; 641 642 /* 643 * Antenna switch control. By default antenna selection 644 * enables multiple (2) antenna use. To force use of the 645 * A or B antenna only specify a fixed setting. Fixing 646 * the antenna will also disable any diversity support. 647 */ 648 typedef enum { 649 HAL_ANT_VARIABLE = 0, /* variable by programming */ 650 HAL_ANT_FIXED_A = 1, /* fixed antenna A */ 651 HAL_ANT_FIXED_B = 2 /* fixed antenna B */ 652 } HAL_ANT_SETTING; 653 654 typedef enum { 655 HAL_M_STA = 1, /* infrastructure station */ 656 HAL_M_IBSS = 0, /* IBSS (adhoc) station */ 657 HAL_M_HOSTAP = 6, /* Software Access Point */ 658 HAL_M_MONITOR = 8 /* Monitor mode */ 659 } HAL_OPMODE; 660 661 typedef struct { 662 uint8_t kv_type; /* one of HAL_CIPHER */ 663 uint8_t kv_pad; 664 uint16_t kv_len; /* length in bits */ 665 uint8_t kv_val[16]; /* enough for 128-bit keys */ 666 uint8_t kv_mic[8]; /* TKIP MIC key */ 667 uint8_t kv_txmic[8]; /* TKIP TX MIC key (optional) */ 668 } HAL_KEYVAL; 669 670 typedef enum { 671 HAL_CIPHER_WEP = 0, 672 HAL_CIPHER_AES_OCB = 1, 673 HAL_CIPHER_AES_CCM = 2, 674 HAL_CIPHER_CKIP = 3, 675 HAL_CIPHER_TKIP = 4, 676 HAL_CIPHER_CLR = 5, /* no encryption */ 677 678 HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ 679 } HAL_CIPHER; 680 681 enum { 682 HAL_SLOT_TIME_6 = 6, /* NB: for turbo mode */ 683 HAL_SLOT_TIME_9 = 9, 684 HAL_SLOT_TIME_20 = 20 685 }; 686 687 /* 688 * Per-station beacon timer state. Note that the specified 689 * beacon interval (given in TU's) can also include flags 690 * to force a TSF reset and to enable the beacon xmit logic. 691 * If bs_cfpmaxduration is non-zero the hardware is setup to 692 * coexist with a PCF-capable AP. 693 */ 694 typedef struct { 695 uint32_t bs_nexttbtt; /* next beacon in TU */ 696 uint32_t bs_nextdtim; /* next DTIM in TU */ 697 uint32_t bs_intval; /* beacon interval+flags */ 698 uint32_t bs_dtimperiod; 699 uint16_t bs_cfpperiod; /* CFP period in TU */ 700 uint16_t bs_cfpmaxduration; /* max CFP duration in TU */ 701 uint32_t bs_cfpnext; /* next CFP in TU */ 702 uint16_t bs_timoffset; /* byte offset to TIM bitmap */ 703 uint16_t bs_bmissthreshold; /* beacon miss threshold */ 704 uint32_t bs_sleepduration; /* max sleep duration */ 705 } HAL_BEACON_STATE; 706 707 /* 708 * Like HAL_BEACON_STATE but for non-station mode setup. 709 * NB: see above flag definitions 710 */ 711 typedef struct { 712 uint32_t bt_intval; /* beacon interval+flags */ 713 uint32_t bt_nexttbtt; /* next beacon in TU */ 714 uint32_t bt_nextatim; /* next ATIM in TU */ 715 uint32_t bt_nextdba; /* next DBA in 1/8th TU */ 716 uint32_t bt_nextswba; /* next SWBA in 1/8th TU */ 717 uint32_t bt_flags; /* timer enables */ 718 #define HAL_BEACON_TBTT_EN 0x00000001 719 #define HAL_BEACON_DBA_EN 0x00000002 720 #define HAL_BEACON_SWBA_EN 0x00000004 721 } HAL_BEACON_TIMERS; 722 723 /* 724 * Per-node statistics maintained by the driver for use in 725 * optimizing signal quality and other operational aspects. 726 */ 727 typedef struct { 728 uint32_t ns_avgbrssi; /* average beacon rssi */ 729 uint32_t ns_avgrssi; /* average data rssi */ 730 uint32_t ns_avgtxrssi; /* average tx rssi */ 731 } HAL_NODE_STATS; 732 733 /* 734 * Transmit descriptor status. This structure is filled 735 * in only after the tx descriptor process method finds a 736 * ``done'' descriptor; at which point it returns something 737 * other than HAL_EINPROGRESS. 738 * 739 * Note that ts_antenna may not be valid for all h/w. It 740 * should be used only if non-zero. 741 */ 742 struct ath_tx_status { 743 uint16_t ts_seqnum; /* h/w assigned sequence number */ 744 uint16_t ts_tstamp; /* h/w assigned timestamp */ 745 uint8_t ts_status; /* frame status, 0 => xmit ok */ 746 uint8_t ts_rate; /* h/w transmit rate index */ 747 int8_t ts_rssi; /* tx ack RSSI */ 748 uint8_t ts_shortretry; /* # short retries */ 749 uint8_t ts_longretry; /* # long retries */ 750 uint8_t ts_virtcol; /* virtual collision count */ 751 uint8_t ts_antenna; /* antenna information */ 752 uint8_t ts_finaltsi; /* final transmit series index */ 753 /* AH_SUPPORT_AR5416 */ /* 802.11n status */ 754 uint8_t ts_flags; /* misc flags */ 755 int8_t ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */ 756 int8_t ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */ 757 uint32_t ts_ba_low; /* blockack bitmap low */ 758 uint32_t ts_ba_high; /* blockack bitmap high */ 759 uint32_t ts_evm0; /* evm bytes */ 760 uint32_t ts_evm1; 761 uint32_t ts_evm2; 762 }; 763 764 765 /* 766 * Receive descriptor status. This structure is filled 767 * in only after the rx descriptor process method finds a 768 * ``done'' descriptor; at which point it returns something 769 * other than HAL_EINPROGRESS. 770 * 771 * If rx_status is zero, then the frame was received ok; 772 * otherwise the error information is indicated and rs_phyerr 773 * contains a phy error code if HAL_RXERR_PHY is set. In general 774 * the frame contents is undefined when an error occurred thought 775 * for some errors (e.g. a decryption error), it may be meaningful. 776 * 777 * Note that the receive timestamp is expanded using the TSF to 778 * at least 15 bits (regardless of what the h/w provides directly). 779 * Newer hardware supports a full 32-bits; use HAL_CAP_32TSTAMP to 780 * find out if the hardware is capable. 781 * 782 * rx_rssi is in units of dbm above the noise floor. This value 783 * is measured during the preamble and PLCP; i.e. with the initial 784 * 4us of detection. The noise floor is typically a consistent 785 * -96dBm absolute power in a 20MHz channel. 786 */ 787 struct ath_rx_status { 788 uint16_t rs_datalen; /* rx frame length */ 789 uint8_t rs_status; /* rx status, 0 => recv ok */ 790 uint8_t rs_phyerr; /* phy error code */ 791 int8_t rs_rssi; /* rx frame RSSI (xombined for 11n) */ 792 uint8_t rs_keyix; /* key cache index */ 793 uint8_t rs_rate; /* h/w receive rate index */ 794 uint8_t rs_more; /* see HAL_RXERR_XXX definition */ 795 uint32_t rs_tstamp; /* h/w assigned timestamp */ 796 uint32_t rs_antenna; /* antenna information */ 797 /* AH_SUPPORT_AR5416 */ /* 802.11n status */ 798 int8_t rs_rssi_ctl[3]; /* rx frame RSSI [ctl, chain 0-2] */ 799 int8_t rs_rssi_ext[3]; /* rx frame RSSI [ext, chain 0-2] */ 800 uint8_t rs_isaggr; /* is part of the aggregate */ 801 uint8_t rs_moreaggr; /* more frames in aggr to follow */ 802 uint8_t rs_num_delims; /* number of delims in aggr */ 803 uint8_t rs_flags; /* misc flags */ 804 uint32_t rs_evm0; /* evm bytes */ 805 uint32_t rs_evm1; 806 uint32_t rs_evm2; 807 }; 808 809 /* 810 * Definitions for the software frame/packet descriptors used by 811 * the Atheros HAL. This definition obscures hardware-specific 812 * details from the driver. Drivers are expected to fillin the 813 * portions of a descriptor that are not opaque then use HAL calls 814 * to complete the work. Status for completed frames is returned 815 * in a device-independent format. 816 */ 817 /* AH_SUPPORT_AR5416 */ 818 #define HAL_DESC_HW_SIZE 20 819 820 #pragma pack(1) 821 struct ath_desc { 822 /* 823 * The following definitions are passed directly 824 * the hardware and managed by the HAL. Drivers 825 * should not touch those elements marked opaque. 826 */ 827 uint32_t ds_link; /* phys address of next descriptor */ 828 uint32_t ds_data; /* phys address of data buffer */ 829 uint32_t ds_ctl0; /* opaque DMA control 0 */ 830 uint32_t ds_ctl1; /* opaque DMA control 1 */ 831 uint32_t ds_hw[HAL_DESC_HW_SIZE]; /* opaque h/w region */ 832 }; 833 834 struct ath_desc_status { 835 union { 836 struct ath_tx_status tx; /* xmit status */ 837 struct ath_rx_status rx; /* recv status */ 838 } ds_us; 839 }; 840 #pragma pack() 841 842 #define ds_txstat ds_us.tx 843 #define ds_rxstat ds_us.rx 844 845 /* 846 * Hardware Access Layer (HAL) API. 847 * 848 * Clients of the HAL call ath_hal_attach to obtain a reference to an 849 * ath_hal structure for use with the device. Hardware-related operations 850 * that follow must call back into the HAL through interface, supplying 851 * the reference as the first parameter. Note that before using the 852 * reference returned by ath_hal_attach the caller should verify the 853 * ABI version number. 854 */ 855 struct ath_hal { 856 uint32_t ah_magic; /* consistency check magic number */ 857 uint32_t ah_abi; /* HAL ABI version */ 858 uint16_t ah_devid; /* PCI device ID */ 859 uint16_t ah_subvendorid; /* PCI subvendor ID */ 860 HAL_SOFTC ah_sc; /* back pointer to driver/os state */ 861 HAL_BUS_TAG ah_st; /* params for register r+w */ 862 HAL_BUS_HANDLE ah_sh; 863 HAL_CTRY_CODE ah_countryCode; 864 865 uint32_t ah_macVersion; /* MAC version id */ 866 uint16_t ah_macRev; /* MAC revision */ 867 uint16_t ah_phyRev; /* PHY revision */ 868 /* NB: when only one radio is present the rev is in 5Ghz */ 869 uint16_t ah_analog5GhzRev; /* 5GHz radio revision */ 870 uint16_t ah_analog2GhzRev; /* 2GHz radio revision */ 871 872 const HAL_RATE_TABLE *(*ah_getRateTable)(struct ath_hal *, 873 uint32_t mode); 874 void (*ah_detach) (struct ath_hal *); 875 876 /* Reset functions */ 877 HAL_BOOL (*ah_reset) (struct ath_hal *, HAL_OPMODE, 878 HAL_CHANNEL *, HAL_BOOL bChannelChange, 879 HAL_STATUS *status); 880 HAL_BOOL (*ah_phyDisable) (struct ath_hal *); 881 HAL_BOOL (*ah_disable) (struct ath_hal *); 882 void (*ah_setPCUConfig) (struct ath_hal *); 883 HAL_BOOL (*ah_perCalibration) (struct ath_hal *, HAL_CHANNEL *, 884 HAL_BOOL *); 885 HAL_BOOL (*ah_setTxPowerLimit)(struct ath_hal *, uint32_t); 886 887 /* DFS support */ 888 HAL_BOOL (*ah_radarWait)(struct ath_hal *, HAL_CHANNEL *); 889 890 /* Transmit functions */ 891 HAL_BOOL (*ah_updateTxTrigLevel) (struct ath_hal *, 892 HAL_BOOL incTrigLevel); 893 int (*ah_setupTxQueue) (struct ath_hal *, HAL_TX_QUEUE, 894 const HAL_TXQ_INFO *qInfo); 895 HAL_BOOL (*ah_setTxQueueProps) (struct ath_hal *, int q, 896 const HAL_TXQ_INFO *qInfo); 897 HAL_BOOL (*ah_getTxQueueProps)(struct ath_hal *, int q, 898 HAL_TXQ_INFO *qInfo); 899 HAL_BOOL (*ah_releaseTxQueue) (struct ath_hal *ah, uint32_t q); 900 HAL_BOOL (*ah_resetTxQueue) (struct ath_hal *ah, uint32_t q); 901 uint32_t (*ah_getTxDP) (struct ath_hal *, uint32_t); 902 HAL_BOOL (*ah_setTxDP) (struct ath_hal *, uint32_t, uint32_t txdp); 903 uint32_t (*ah_numTxPending)(struct ath_hal *, uint32_t q); 904 HAL_BOOL (*ah_startTxDma) (struct ath_hal *, uint32_t); 905 HAL_BOOL (*ah_stopTxDma) (struct ath_hal *, uint32_t); 906 HAL_BOOL (*ah_setupTxDesc) (struct ath_hal *, struct ath_desc *, 907 uint32_t pktLen, uint32_t hdrLen, 908 HAL_PKT_TYPE type, uint32_t txPower, 909 uint32_t txRate0, uint32_t txTries0, 910 uint32_t keyIx, uint32_t antMode, 911 uint32_t flags, uint32_t rtsctsRate, 912 uint32_t rtsctsDuration, 913 uint32_t compicvLen, uint32_t compivLen, 914 uint32_t comp); 915 HAL_BOOL (*ah_setupXTxDesc) (struct ath_hal *, struct ath_desc *, 916 uint32_t txRate1, uint32_t txTries1, 917 uint32_t txRate2, uint32_t txTries2, 918 uint32_t txRate3, uint32_t txTries3); 919 HAL_BOOL (*ah_fillTxDesc) (struct ath_hal *, struct ath_desc *, 920 uint32_t segLen, HAL_BOOL firstSeg, 921 HAL_BOOL lastSeg, const struct ath_desc *); 922 HAL_STATUS (*ah_procTxDesc)(struct ath_hal *, struct ath_desc *, 923 struct ath_tx_status *); 924 void (*ah_getTxIntrQueue)(struct ath_hal *, uint32_t *); 925 void (*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc *); 926 927 /* Receive Functions */ 928 uint32_t (*ah_getRxDP) (struct ath_hal *); 929 void (*ah_setRxDP) (struct ath_hal *, uint32_t rxdp); 930 void (*ah_enableReceive) (struct ath_hal *); 931 HAL_BOOL (*ah_stopDmaReceive) (struct ath_hal *); 932 void (*ah_startPcuReceive) (struct ath_hal *); 933 void (*ah_stopPcuReceive) (struct ath_hal *); 934 void (*ah_setMulticastFilter) (struct ath_hal *, 935 uint32_t filter0, uint32_t filter1); 936 HAL_BOOL (*ah_setMulticastFilterIndex) (struct ath_hal *, 937 uint32_t index); 938 HAL_BOOL (*ah_clrMulticastFilterIndex) (struct ath_hal *, 939 uint32_t index); 940 uint32_t (*ah_getRxFilter) (struct ath_hal *); 941 void (*ah_setRxFilter) (struct ath_hal *, uint32_t); 942 HAL_BOOL (*ah_setupRxDesc) (struct ath_hal *, struct ath_desc *, 943 uint32_t size, uint32_t flags); 944 HAL_STATUS (*ah_procRxDesc) (struct ath_hal *, struct ath_desc *, 945 uint32_t phyAddr, struct ath_desc *next, 946 uint64_t tsf, struct ath_rx_status *); 947 void (*ah_rxMonitor) (struct ath_hal *, 948 const HAL_NODE_STATS *, HAL_CHANNEL *); 949 void (*ah_procMibEvent) (struct ath_hal *, 950 const HAL_NODE_STATS *); 951 952 /* Misc Functions */ 953 HAL_STATUS (*ah_getCapability) (struct ath_hal *, 954 HAL_CAPABILITY_TYPE, uint32_t capability, 955 uint32_t *result); 956 HAL_BOOL (*ah_setCapability) (struct ath_hal *, 957 HAL_CAPABILITY_TYPE, uint32_t capability, 958 uint32_t setting, HAL_STATUS *); 959 HAL_BOOL (*ah_getDiagState) (struct ath_hal *, int request, 960 const void *args, uint32_t argsize, 961 void **result, uint32_t *resultsize); 962 void (*ah_getMacAddress) (struct ath_hal *, uint8_t *); 963 HAL_BOOL (*ah_setMacAddress) (struct ath_hal *, const uint8_t *); 964 void (*ah_getBssIdMask)(struct ath_hal *, uint8_t *); 965 HAL_BOOL (*ah_setBssIdMask)(struct ath_hal *, const uint8_t *); 966 HAL_BOOL (*ah_setRegulatoryDomain) (struct ath_hal *, 967 uint16_t, HAL_STATUS *); 968 void (*ah_setLedState) (struct ath_hal *, HAL_LED_STATE); 969 void (*ah_writeAssocid) (struct ath_hal *, 970 const uint8_t *bssid, uint16_t assocId); 971 HAL_BOOL (*ah_gpioCfgOutput) (struct ath_hal *, uint32_t gpio); 972 HAL_BOOL (*ah_gpioCfgInput) (struct ath_hal *, uint32_t gpio); 973 uint32_t (*ah_gpioGet) (struct ath_hal *, uint32_t gpio); 974 HAL_BOOL (*ah_gpioSet) (struct ath_hal *, 975 uint32_t gpio, uint32_t val); 976 void (*ah_gpioSetIntr) (struct ath_hal *, uint32_t, uint32_t); 977 uint32_t (*ah_getTsf32) (struct ath_hal *); 978 uint64_t (*ah_getTsf64) (struct ath_hal *); 979 void (*ah_resetTsf) (struct ath_hal *); 980 HAL_BOOL (*ah_detectCardPresent) (struct ath_hal *); 981 void (*ah_updateMibCounters) (struct ath_hal *, HAL_MIB_STATS *); 982 HAL_RFGAIN (*ah_getRfGain) (struct ath_hal *); 983 uint32_t (*ah_getDefAntenna) (struct ath_hal *); 984 void (*ah_setDefAntenna) (struct ath_hal *, uint32_t); 985 HAL_ANT_SETTING (*ah_getAntennaSwitch) (struct ath_hal *); 986 HAL_BOOL (*ah_setAntennaSwitch) (struct ath_hal *, HAL_ANT_SETTING); 987 HAL_BOOL (*ah_setSifsTime) (struct ath_hal *, uint32_t); 988 uint32_t (*ah_getSifsTime) (struct ath_hal *); 989 HAL_BOOL (*ah_setSlotTime) (struct ath_hal *, uint32_t); 990 uint32_t (*ah_getSlotTime) (struct ath_hal *); 991 HAL_BOOL (*ah_setAckTimeout) (struct ath_hal *, uint32_t); 992 uint32_t (*ah_getAckTimeout) (struct ath_hal *); 993 HAL_BOOL (*ah_setAckCTSRate) (struct ath_hal *, uint32_t); 994 uint32_t (*ah_getAckCTSRate) (struct ath_hal *); 995 HAL_BOOL (*ah_setCTSTimeout) (struct ath_hal *, uint32_t); 996 uint32_t (*ah_getCTSTimeout) (struct ath_hal *); 997 HAL_BOOL (*ah_setDecompMask)(struct ath_hal *, uint16_t, int); 998 void (*ah_setCoverageClass)(struct ath_hal *, uint8_t, int); 999 /* Key Cache Functions */ 1000 uint32_t (*ah_getKeyCacheSize) (struct ath_hal *); 1001 HAL_BOOL (*ah_resetKeyCacheEntry) (struct ath_hal *, uint16_t); 1002 HAL_BOOL (*ah_isKeyCacheEntryValid) (struct ath_hal *, uint16_t); 1003 HAL_BOOL (*ah_setKeyCacheEntry) (struct ath_hal *, 1004 uint16_t, const HAL_KEYVAL *, 1005 const uint8_t *, int); 1006 HAL_BOOL (*ah_setKeyCacheEntryMac) (struct ath_hal *, 1007 uint16_t, const uint8_t *); 1008 1009 /* Power Management Functions */ 1010 HAL_BOOL (*ah_setPowerMode) (struct ath_hal *, 1011 HAL_POWER_MODE mode, int setChip); 1012 HAL_POWER_MODE (*ah_getPowerMode) (struct ath_hal *); 1013 int16_t (*ah_getChanNoise)(struct ath_hal *, HAL_CHANNEL *); 1014 1015 /* Beacon Management Functions */ 1016 void (*ah_setBeaconTimers) (struct ath_hal *, 1017 const HAL_BEACON_TIMERS *); 1018 /* NB: deprecated, use ah_setBeaconTimers instead */ 1019 void (*ah_beaconInit) (struct ath_hal *, 1020 uint32_t nexttbtt, uint32_t intval); 1021 void (*ah_setStationBeaconTimers) (struct ath_hal *, 1022 const HAL_BEACON_STATE *); 1023 void (*ah_resetStationBeaconTimers) (struct ath_hal *); 1024 1025 /* Interrupt functions */ 1026 HAL_BOOL (*ah_isInterruptPending) (struct ath_hal *); 1027 HAL_BOOL (*ah_getPendingInterrupts) (struct ath_hal *, HAL_INT *); 1028 HAL_INT (*ah_getInterrupts) (struct ath_hal *); 1029 HAL_INT (*ah_setInterrupts) (struct ath_hal *, HAL_INT); 1030 }; 1031 1032 /* 1033 * Check the PCI vendor ID and device ID against Atheros' values 1034 * and return a printable description for any Atheros hardware. 1035 * AH_NULL is returned if the ID's do not describe Atheros hardware. 1036 */ 1037 extern const char *ath_hal_probe(uint16_t vendorid, uint16_t devid); 1038 1039 /* 1040 * Attach the HAL for use with the specified device. The device is 1041 * defined by the PCI device ID. The caller provides an opaque pointer 1042 * to an upper-layer data structure (HAL_SOFTC) that is stored in the 1043 * HAL state block for later use. Hardware register accesses are done 1044 * using the specified bus tag and handle. On successful return a 1045 * reference to a state block is returned that must be supplied in all 1046 * subsequent HAL calls. Storage associated with this reference is 1047 * dynamically allocated and must be freed by calling the ah_detach 1048 * method when the client is done. If the attach operation fails a 1049 * null (AH_NULL) reference will be returned and a status code will 1050 * be returned if the status parameter is non-zero. 1051 */ 1052 extern struct ath_hal *ath_hal_attach(uint16_t devid, HAL_SOFTC, 1053 HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *status); 1054 1055 /* 1056 * Set the Vendor ID for Vendor SKU's which can modify the 1057 * channel properties returned by ath_hal_init_channels. 1058 * Return AH_TRUE if set succeeds 1059 */ 1060 extern HAL_BOOL ath_hal_setvendor(struct ath_hal *, uint32_t); 1061 1062 /* 1063 * Return a list of channels available for use with the hardware. 1064 * The list is based on what the hardware is capable of, the specified 1065 * country code, the modeSelect mask, and whether or not outdoor 1066 * channels are to be permitted. 1067 * 1068 * The channel list is returned in the supplied array. maxchans 1069 * defines the maximum size of this array. nchans contains the actual 1070 * number of channels returned. If a problem occurred or there were 1071 * no channels that met the criteria then AH_FALSE is returned. 1072 */ 1073 extern HAL_BOOL ath_hal_init_channels(struct ath_hal *, 1074 HAL_CHANNEL *chans, uint32_t maxchans, uint32_t *nchans, 1075 uint8_t *regclassids, uint32_t maxregids, uint32_t *nregids, 1076 HAL_CTRY_CODE cc, uint_t modeSelect, 1077 HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels); 1078 1079 /* 1080 * Calibrate noise floor data following a channel scan or similar. 1081 * This must be called prior retrieving noise floor data. 1082 */ 1083 extern void ath_hal_process_noisefloor(struct ath_hal *ah); 1084 1085 /* 1086 * Return bit mask of wireless modes supported by the hardware. 1087 */ 1088 extern uint32_t ath_hal_getwirelessmodes(struct ath_hal *, HAL_CTRY_CODE); 1089 1090 /* 1091 * Calculate the transmit duration of a frame. 1092 */ 1093 extern uint16_t ath_hal_computetxtime(struct ath_hal *, 1094 const HAL_RATE_TABLE *rates, uint32_t frameLen, 1095 uint16_t rateix, HAL_BOOL shortPreamble); 1096 1097 /* 1098 * Return if device is public safety. 1099 */ 1100 extern HAL_BOOL ath_hal_ispublicsafetysku(struct ath_hal *); 1101 1102 /* 1103 * Return if device is operating in 900 MHz band. 1104 */ 1105 extern HAL_BOOL ath_hal_isgsmsku(struct ath_hal *); 1106 1107 /* 1108 * Convert between IEEE channel number and channel frequency 1109 * using the specified channel flags; e.g. CHANNEL_2GHZ. 1110 */ 1111 extern int ath_hal_mhz2ieee(struct ath_hal *, uint32_t mhz, uint32_t flags); 1112 1113 /* 1114 * Return a version string for the HAL release. 1115 */ 1116 extern char ath_hal_version[]; 1117 1118 /* 1119 * Return a NULL-terminated array of build/configuration options. 1120 */ 1121 extern const char *ath_hal_buildopts[]; 1122 1123 /* 1124 * Macros to encapsulated HAL functions. 1125 */ 1126 #define ATH_HAL_RESET(_ah, _opmode, _chan, _outdoor, _pstatus) \ 1127 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 1128 #define ATH_HAL_PHYDISABLE(_ah) \ 1129 ((*(_ah)->ah_phyDisable)((_ah))) 1130 #define ATH_HAL_GETCAPABILITY(_ah, _cap, _param, _result) \ 1131 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 1132 #define ATH_HAL_SETCAPABILITY(_ah, _type, _cap, _param, _status) \ 1133 ((*(_ah)->ah_setCapability)((_ah), (_type), (_cap), (_param), \ 1134 (_status))) 1135 #define ATH_HAL_GETREGDOMAIN(_ah, _prd) \ 1136 ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_REG_DMN, 0, (_prd)) 1137 #define ATH_HAL_GETCOUNTRYCODE(_ah, _pcc) \ 1138 (*(_pcc) = (_ah)->ah_countryCode) 1139 #define ATH_HAL_GETRATETABLE(_ah, _mode) \ 1140 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 1141 #define ATH_HAL_GETMAC(_ah, _mac) \ 1142 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 1143 #define ATH_HAL_SETMAC(_ah, _mac) \ 1144 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 1145 #define ATH_HAL_INTRSET(_ah, _mask) \ 1146 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 1147 #define ATH_HAL_INTRGET(_ah) \ 1148 ((*(_ah)->ah_getInterrupts)((_ah))) 1149 #define ATH_HAL_INTRPEND(_ah) \ 1150 ((*(_ah)->ah_isInterruptPending)((_ah))) 1151 #define ATH_HAL_GETISR(_ah, _pmask) \ 1152 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 1153 #define ATH_HAL_UPDATETXTRIGLEVEL(_ah, _inc) \ 1154 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 1155 #define ATH_HAL_SETPOWER(_ah, _mode) \ 1156 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 1157 #define ATH_HAL_KEYRESET(_ah, _ix) \ 1158 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 1159 #define ATH_HAL_KEYSET(_ah, _ix, _pk, _mac) \ 1160 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 1161 #define ATH_HAL_KEYISVALID(_ah, _ix) \ 1162 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 1163 #define ATH_HAL_KEYSETMAC(_ah, _ix, _mac) \ 1164 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 1165 #define ATH_HAL_KEYCACHESIZE(_ah) \ 1166 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 1167 #define ATH_HAL_GETRXFILTER(_ah) \ 1168 ((*(_ah)->ah_getRxFilter)((_ah))) 1169 #define ATH_HAL_SETRXFILTER(_ah, _filter) \ 1170 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 1171 #define ATH_HAL_SETMCASTFILTER(_ah, _mfilt0, _mfilt1) \ 1172 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 1173 #define ATH_HAL_WAITFORBEACON(_ah, _bf) \ 1174 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 1175 #define ATH_HAL_PUTRXBUF(_ah, _bufaddr) \ 1176 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 1177 #define ATH_HAL_GETTSF32(_ah) \ 1178 ((*(_ah)->ah_getTsf32)((_ah))) 1179 #define ATH_HAL_GETTSF64(_ah) \ 1180 ((*(_ah)->ah_getTsf64)((_ah))) 1181 #define ATH_HAL_RESETTSF(_ah) \ 1182 ((*(_ah)->ah_resetTsf)((_ah))) 1183 #define ATH_HAL_RXENA(_ah) \ 1184 ((*(_ah)->ah_enableReceive)((_ah))) 1185 #define ATH_HAL_PUTTXBUF(_ah, _q, _bufaddr) \ 1186 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 1187 #define ATH_HAL_GETTXBUF(_ah, _q) \ 1188 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 1189 #define ATH_HAL_GETRXBUF(_ah) \ 1190 ((*(_ah)->ah_getRxDP)((_ah))) 1191 #define ATH_HAL_TXSTART(_ah, _q) \ 1192 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 1193 #define ATH_HAL_SETCHANNEL(_ah, _chan) \ 1194 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 1195 #define ATH_HAL_CALIBRATE(_ah, _chan, _iqcal) \ 1196 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 1197 #define ATH_HAL_SETLEDSTATE(_ah, _state) \ 1198 ((*(_ah)->ah_setLedState)((_ah), (_state))) 1199 #define ATH_HAL_BEACONINIT(_ah, _nextb, _bperiod) \ 1200 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 1201 #define ATH_HAL_BEACONRESET(_ah) \ 1202 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 1203 #define ATH_HAL_BEACONTIMERS(_ah, _beacon_state) \ 1204 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_beacon_state))) 1205 #define ATH_HAL_SETASSOCID(_ah, _bss, _associd) \ 1206 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 1207 #define ATH_HAL_SETOPMODE(_ah) \ 1208 ((*(_ah)->ah_setPCUConfig)((_ah))) 1209 #define ATH_HAL_STOPTXDMA(_ah, _qnum) \ 1210 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 1211 #define ATH_HAL_STOPPCURECV(_ah) \ 1212 ((*(_ah)->ah_stopPcuReceive)((_ah))) 1213 #define ATH_HAL_STARTPCURECV(_ah) \ 1214 ((*(_ah)->ah_startPcuReceive)((_ah))) 1215 #define ATH_HAL_STOPDMARECV(_ah) \ 1216 ((*(_ah)->ah_stopDmaReceive)((_ah))) 1217 #define ATH_HAL_DUMPSTATE(_ah) \ 1218 ((*(_ah)->ah_dumpState)((_ah))) 1219 #define ATH_HAL_DUMPEEPROM(_ah) \ 1220 ((*(_ah)->ah_dumpEeprom)((_ah))) 1221 #define ATH_HAL_DUMPRFGAIN(_ah) \ 1222 ((*(_ah)->ah_dumpRfGain)((_ah))) 1223 #define ATH_HAL_DUMPANI(_ah) \ 1224 ((*(_ah)->ah_dumpAni)((_ah))) 1225 #define ATH_HAL_SETUPTXQUEUE(_ah, _type, _irq) \ 1226 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 1227 #define ATH_HAL_RESETTXQUEUE(_ah, _q) \ 1228 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 1229 #define ATH_HAL_RELEASETXQUEUE(_ah, _q) \ 1230 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 1231 #define ATH_HAL_GETTXQUEUEPROPS(_ah, _q, _qi) \ 1232 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 1233 #define ATH_HAL_SETTXQUEUEPROPS(_ah, _q, _qi) \ 1234 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 1235 #define ATH_HAL_HASVEOL(_ah) \ 1236 (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 1237 #define ATH_HAL_GETRFGAIN(_ah) \ 1238 ((*(_ah)->ah_getRfGain)((_ah))) 1239 #define ATH_HAL_RXMONITOR(_ah, _arg, _chan) \ 1240 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 1241 #define ATH_HAL_SETSLOTTIME(_ah, _us) \ 1242 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 1243 #define ATH_HAL_SETUPBEACONDESC(_ah, _ds, _opmode, _flen, _hlen, \ 1244 _rate, _antmode) \ 1245 ((*(_ah)->ah_setupBeaconDesc)((_ah), (_ds), (_opmode), \ 1246 (_flen), (_hlen), (_rate), (_antmode))) 1247 #define ATH_HAL_SETUPRXDESC(_ah, _ds, _size, _intreq) \ 1248 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 1249 #define ATH_HAL_RXPROCDESC(_ah, _ds, _dspa, _dsnext, _rs) \ 1250 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 1251 #define ATH_HAL_SETUPTXDESC(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 1252 _txr0, _txtr0, _keyix, _ant, _flags, \ 1253 _rtsrate, _rtsdura) \ 1254 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 1255 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 1256 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 1257 #define ATH_HAL_SETUPXTXDESC(_ah, _ds, \ 1258 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 1259 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 1260 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 1261 #define ATH_HAL_FILLTXDESC(_ah, _ds, _l, _first, _last, _ath_desc) \ 1262 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), \ 1263 (_ath_desc))) 1264 #define ATH_HAL_TXPROCDESC(_ah, _ds, _ts) \ 1265 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 1266 #define ATH_HAL_CIPHERSUPPORTED(_ah, _cipher) \ 1267 (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 1268 #define ATH_HAL_HASTKIPSPLIT(_ah) \ 1269 (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 1270 #define ATH_HAL_GETTKIPSPLIT(_ah) \ 1271 (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 1272 #define ATH_HAL_SETTKIPSPLIT(_ah, _v) \ 1273 (ATH_HAL_SETCAPABILITY(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL)) 1274 #define ATH_HAL_HASRFSILENT(ah) \ 1275 (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 1276 #define ATH_HAL_GETRFKILL(_ah) \ 1277 (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 1278 #define ATH_HAL_SETRFKILL(_ah, _onoff) \ 1279 (ATH_HAL_SETCAPABILITY(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)) 1280 #define ATH_HAL_GETRFSILENT(_ah, _prfsilent) \ 1281 (ATH_HAL_GETCAPABILITY(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 1282 #define ATH_HAL_SETRFSILENT(_ah, _rfsilent) \ 1283 (ATH_HAL_SETCAPABILITY(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)) 1284 1285 #if HAL_ABI_VERSION < 0x05120700 1286 #define ATH_HAL_PROCESS_NOISEFLOOR(_ah) 1287 #define ATH_HAL_GETCHANNOISE(_ah, _c) (-96) 1288 #define HAL_CAP_TPC_ACK 100 1289 #define HAL_CAP_TPC_CTS 101 1290 #else 1291 #define ATH_HAL_GETCHANNOISE(_ah, _c) \ 1292 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 1293 #endif 1294 1295 #if HAL_ABI_VERSION < 0x05122200 1296 #define HAL_TXQ_TXOKINT_ENABLE TXQ_FLAG_TXOKINT_ENABLE 1297 #define HAL_TXQ_TXERRINT_ENABLE TXQ_FLAG_TXERRINT_ENABLE 1298 #define HAL_TXQ_TXDESCINT_ENABLE TXQ_FLAG_TXDESCINT_ENABLE 1299 #define HAL_TXQ_TXEOLINT_ENABLE TXQ_FLAG_TXEOLINT_ENABLE 1300 #define HAL_TXQ_TXURNINT_ENABLE TXQ_FLAG_TXURNINT_ENABLE 1301 #endif 1302 1303 #ifdef __cplusplus 1304 } 1305 #endif 1306 1307 #endif /* _ATH_HAL_H */ 1308