1 /* 2 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2008 Atheros Communications Inc. 8 * 9 * Permission to use, copy, modify, and/or distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 #include <sys/param.h> 23 #include <sys/types.h> 24 #include <sys/signal.h> 25 #include <sys/stream.h> 26 #include <sys/termio.h> 27 #include <sys/errno.h> 28 #include <sys/file.h> 29 #include <sys/cmn_err.h> 30 #include <sys/stropts.h> 31 #include <sys/strsubr.h> 32 #include <sys/strtty.h> 33 #include <sys/kbio.h> 34 #include <sys/cred.h> 35 #include <sys/stat.h> 36 #include <sys/consdev.h> 37 #include <sys/kmem.h> 38 #include <sys/modctl.h> 39 #include <sys/ddi.h> 40 #include <sys/sunddi.h> 41 #include <sys/pci.h> 42 #include <sys/errno.h> 43 #include <sys/mac_provider.h> 44 #include <sys/dlpi.h> 45 #include <sys/ethernet.h> 46 #include <sys/list.h> 47 #include <sys/byteorder.h> 48 #include <sys/strsun.h> 49 #include <sys/policy.h> 50 #include <inet/common.h> 51 #include <inet/nd.h> 52 #include <inet/mi.h> 53 #include <inet/wifi_ioctl.h> 54 #include <sys/mac_wifi.h> 55 56 #include "ath9k.h" 57 #include "core.h" 58 #include "reg.h" 59 #include "hw.h" 60 61 #define ARN_MAX_RSSI 63 /* max rssi */ 62 63 /* 64 * PIO access attributes for registers 65 */ 66 static ddi_device_acc_attr_t arn_reg_accattr = { 67 DDI_DEVICE_ATTR_V0, 68 DDI_STRUCTURE_LE_ACC, 69 DDI_STRICTORDER_ACC 70 }; 71 72 /* 73 * DMA access attributes for descriptors: NOT to be byte swapped. 74 */ 75 static ddi_device_acc_attr_t arn_desc_accattr = { 76 DDI_DEVICE_ATTR_V0, 77 DDI_STRUCTURE_LE_ACC, 78 DDI_STRICTORDER_ACC 79 }; 80 81 /* 82 * Describes the chip's DMA engine 83 */ 84 static ddi_dma_attr_t arn_dma_attr = { 85 DMA_ATTR_V0, /* version number */ 86 0, /* low address */ 87 0xffffffffU, /* high address */ 88 0x3ffffU, /* counter register max */ 89 1, /* alignment */ 90 0xFFF, /* burst sizes */ 91 1, /* minimum transfer size */ 92 0x3ffffU, /* max transfer size */ 93 0xffffffffU, /* address register max */ 94 1, /* no scatter-gather */ 95 1, /* granularity of device */ 96 0, /* DMA flags */ 97 }; 98 99 static ddi_dma_attr_t arn_desc_dma_attr = { 100 DMA_ATTR_V0, /* version number */ 101 0, /* low address */ 102 0xffffffffU, /* high address */ 103 0xffffffffU, /* counter register max */ 104 0x1000, /* alignment */ 105 0xFFF, /* burst sizes */ 106 1, /* minimum transfer size */ 107 0xffffffffU, /* max transfer size */ 108 0xffffffffU, /* address register max */ 109 1, /* no scatter-gather */ 110 1, /* granularity of device */ 111 0, /* DMA flags */ 112 }; 113 114 #define ATH_DEF_CACHE_BYTES 32 /* default cache line size */ 115 116 static kmutex_t arn_loglock; 117 static void *arn_soft_state_p = NULL; 118 /* scan interval, ms? */ 119 static int arn_dwelltime = 200; /* 150 */ 120 121 static int arn_m_stat(void *, uint_t, uint64_t *); 122 static int arn_m_start(void *); 123 static void arn_m_stop(void *); 124 static int arn_m_promisc(void *, boolean_t); 125 static int arn_m_multicst(void *, boolean_t, const uint8_t *); 126 static int arn_m_unicst(void *, const uint8_t *); 127 static mblk_t *arn_m_tx(void *, mblk_t *); 128 static void arn_m_ioctl(void *, queue_t *, mblk_t *); 129 static int arn_m_setprop(void *, const char *, mac_prop_id_t, 130 uint_t, const void *); 131 static int arn_m_getprop(void *, const char *, mac_prop_id_t, 132 uint_t, uint_t, void *, uint_t *); 133 134 /* MAC Callcack Functions */ 135 static mac_callbacks_t arn_m_callbacks = { 136 MC_IOCTL | MC_SETPROP | MC_GETPROP, 137 arn_m_stat, 138 arn_m_start, 139 arn_m_stop, 140 arn_m_promisc, 141 arn_m_multicst, 142 arn_m_unicst, 143 arn_m_tx, 144 arn_m_ioctl, 145 NULL, 146 NULL, 147 NULL, 148 arn_m_setprop, 149 arn_m_getprop 150 }; 151 152 /* 153 * ARN_DBG_HW 154 * ARN_DBG_REG_IO 155 * ARN_DBG_QUEUE 156 * ARN_DBG_EEPROM 157 * ARN_DBG_XMIT 158 * ARN_DBG_RECV 159 * ARN_DBG_CALIBRATE 160 * ARN_DBG_CHANNEL 161 * ARN_DBG_INTERRUPT 162 * ARN_DBG_REGULATORY 163 * ARN_DBG_ANI 164 * ARN_DBG_POWER_MGMT 165 * ARN_DBG_KEYCACHE 166 * ARN_DBG_BEACON 167 * ARN_DBG_RATE 168 * ARN_DBG_INIT 169 * ARN_DBG_ATTACH 170 * ARN_DBG_DEATCH 171 * ARN_DBG_AGGR 172 * ARN_DBG_RESET 173 * ARN_DBG_FATAL 174 * ARN_DBG_ANY 175 * ARN_DBG_ALL 176 */ 177 uint32_t arn_dbg_mask = 0; 178 179 /* 180 * Exception/warning cases not leading to panic. 181 */ 182 void 183 arn_problem(const int8_t *fmt, ...) 184 { 185 va_list args; 186 187 mutex_enter(&arn_loglock); 188 189 va_start(args, fmt); 190 vcmn_err(CE_WARN, fmt, args); 191 va_end(args); 192 193 mutex_exit(&arn_loglock); 194 } 195 196 /* 197 * Normal log information independent of debug. 198 */ 199 void 200 arn_log(const int8_t *fmt, ...) 201 { 202 va_list args; 203 204 mutex_enter(&arn_loglock); 205 206 va_start(args, fmt); 207 vcmn_err(CE_CONT, fmt, args); 208 va_end(args); 209 210 mutex_exit(&arn_loglock); 211 } 212 213 void 214 arn_dbg(uint32_t dbg_flags, const int8_t *fmt, ...) 215 { 216 va_list args; 217 218 if (dbg_flags & arn_dbg_mask) { 219 mutex_enter(&arn_loglock); 220 va_start(args, fmt); 221 vcmn_err(CE_CONT, fmt, args); 222 va_end(args); 223 mutex_exit(&arn_loglock); 224 } 225 } 226 227 /* 228 * Read and write, they both share the same lock. We do this to serialize 229 * reads and writes on Atheros 802.11n PCI devices only. This is required 230 * as the FIFO on these devices can only accept sanely 2 requests. After 231 * that the device goes bananas. Serializing the reads/writes prevents this 232 * from happening. 233 */ 234 void 235 arn_iowrite32(struct ath_hal *ah, uint32_t reg_offset, uint32_t val) 236 { 237 struct arn_softc *sc = ah->ah_sc; 238 if (ah->ah_config.serialize_regmode == SER_REG_MODE_ON) { 239 mutex_enter(&sc->sc_serial_rw); 240 ddi_put32(sc->sc_io_handle, 241 (uint32_t *)((uintptr_t)(sc->mem) + (reg_offset)), val); 242 mutex_exit(&sc->sc_serial_rw); 243 } else { 244 ddi_put32(sc->sc_io_handle, 245 (uint32_t *)((uintptr_t)(sc->mem) + (reg_offset)), val); 246 } 247 } 248 249 unsigned int 250 arn_ioread32(struct ath_hal *ah, uint32_t reg_offset) 251 { 252 uint32_t val; 253 struct arn_softc *sc = ah->ah_sc; 254 if (ah->ah_config.serialize_regmode == SER_REG_MODE_ON) { 255 mutex_enter(&sc->sc_serial_rw); 256 val = ddi_get32(sc->sc_io_handle, 257 (uint32_t *)((uintptr_t)(sc->mem) + (reg_offset))); 258 mutex_exit(&sc->sc_serial_rw); 259 } else { 260 val = ddi_get32(sc->sc_io_handle, 261 (uint32_t *)((uintptr_t)(sc->mem) + (reg_offset))); 262 } 263 264 return (val); 265 } 266 267 void 268 arn_rx_buf_link(struct arn_softc *sc, struct ath_buf *bf) 269 { 270 struct ath_desc *ds; 271 272 ds = bf->bf_desc; 273 ds->ds_link = bf->bf_daddr; 274 ds->ds_data = bf->bf_dma.cookie.dmac_address; 275 /* virtual addr of the beginning of the buffer. */ 276 ds->ds_vdata = bf->bf_dma.mem_va; 277 278 /* 279 * setup rx descriptors. The bf_dma.alength here tells the H/W 280 * how much data it can DMA to us and that we are prepared 281 * to process 282 */ 283 (void) ath9k_hw_setuprxdesc(sc->sc_ah, ds, 284 bf->bf_dma.alength, /* buffer size */ 285 0); 286 287 if (sc->sc_rxlink != NULL) 288 *sc->sc_rxlink = bf->bf_daddr; 289 sc->sc_rxlink = &ds->ds_link; 290 } 291 292 /* 293 * Allocate an area of memory and a DMA handle for accessing it 294 */ 295 static int 296 arn_alloc_dma_mem(dev_info_t *devinfo, ddi_dma_attr_t *dma_attr, size_t memsize, 297 ddi_device_acc_attr_t *attr_p, uint_t alloc_flags, 298 uint_t bind_flags, dma_area_t *dma_p) 299 { 300 int err; 301 302 /* 303 * Allocate handle 304 */ 305 err = ddi_dma_alloc_handle(devinfo, dma_attr, 306 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl); 307 if (err != DDI_SUCCESS) 308 return (DDI_FAILURE); 309 310 /* 311 * Allocate memory 312 */ 313 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p, 314 alloc_flags, DDI_DMA_SLEEP, NULL, &dma_p->mem_va, 315 &dma_p->alength, &dma_p->acc_hdl); 316 if (err != DDI_SUCCESS) 317 return (DDI_FAILURE); 318 319 /* 320 * Bind the two together 321 */ 322 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL, 323 dma_p->mem_va, dma_p->alength, bind_flags, 324 DDI_DMA_SLEEP, NULL, &dma_p->cookie, &dma_p->ncookies); 325 if (err != DDI_DMA_MAPPED) 326 return (DDI_FAILURE); 327 328 dma_p->nslots = ~0U; 329 dma_p->size = ~0U; 330 dma_p->token = ~0U; 331 dma_p->offset = 0; 332 return (DDI_SUCCESS); 333 } 334 335 /* 336 * Free one allocated area of DMAable memory 337 */ 338 static void 339 arn_free_dma_mem(dma_area_t *dma_p) 340 { 341 if (dma_p->dma_hdl != NULL) { 342 (void) ddi_dma_unbind_handle(dma_p->dma_hdl); 343 if (dma_p->acc_hdl != NULL) { 344 ddi_dma_mem_free(&dma_p->acc_hdl); 345 dma_p->acc_hdl = NULL; 346 } 347 ddi_dma_free_handle(&dma_p->dma_hdl); 348 dma_p->ncookies = 0; 349 dma_p->dma_hdl = NULL; 350 } 351 } 352 353 /* 354 * Initialize tx, rx. or beacon buffer list. Allocate DMA memory for 355 * each buffer. 356 */ 357 static int 358 arn_buflist_setup(dev_info_t *devinfo, struct arn_softc *sc, list_t *bflist, 359 struct ath_buf **pbf, struct ath_desc **pds, int nbuf, uint_t dmabflags) 360 { 361 int i, err; 362 struct ath_buf *bf = *pbf; 363 struct ath_desc *ds = *pds; 364 365 list_create(bflist, sizeof (struct ath_buf), 366 offsetof(struct ath_buf, bf_node)); 367 for (i = 0; i < nbuf; i++, bf++, ds++) { 368 bf->bf_desc = ds; 369 bf->bf_daddr = sc->sc_desc_dma.cookie.dmac_address + 370 ((uintptr_t)ds - (uintptr_t)sc->sc_desc); 371 list_insert_tail(bflist, bf); 372 373 /* alloc DMA memory */ 374 err = arn_alloc_dma_mem(devinfo, &arn_dma_attr, 375 sc->sc_dmabuf_size, &arn_desc_accattr, DDI_DMA_STREAMING, 376 dmabflags, &bf->bf_dma); 377 if (err != DDI_SUCCESS) 378 return (err); 379 } 380 *pbf = bf; 381 *pds = ds; 382 383 return (DDI_SUCCESS); 384 } 385 386 /* 387 * Destroy tx, rx or beacon buffer list. Free DMA memory. 388 */ 389 static void 390 arn_buflist_cleanup(list_t *buflist) 391 { 392 struct ath_buf *bf; 393 394 if (!buflist) 395 return; 396 397 bf = list_head(buflist); 398 while (bf != NULL) { 399 if (bf->bf_m != NULL) { 400 freemsg(bf->bf_m); 401 bf->bf_m = NULL; 402 } 403 /* Free DMA buffer */ 404 arn_free_dma_mem(&bf->bf_dma); 405 if (bf->bf_in != NULL) { 406 ieee80211_free_node(bf->bf_in); 407 bf->bf_in = NULL; 408 } 409 list_remove(buflist, bf); 410 bf = list_head(buflist); 411 } 412 list_destroy(buflist); 413 } 414 415 static void 416 arn_desc_free(struct arn_softc *sc) 417 { 418 arn_buflist_cleanup(&sc->sc_txbuf_list); 419 arn_buflist_cleanup(&sc->sc_rxbuf_list); 420 #ifdef ARN_IBSS 421 arn_buflist_cleanup(&sc->sc_bcbuf_list); 422 #endif 423 424 /* Free descriptor DMA buffer */ 425 arn_free_dma_mem(&sc->sc_desc_dma); 426 427 kmem_free((void *)sc->sc_vbufptr, sc->sc_vbuflen); 428 sc->sc_vbufptr = NULL; 429 } 430 431 static int 432 arn_desc_alloc(dev_info_t *devinfo, struct arn_softc *sc) 433 { 434 int err; 435 size_t size; 436 struct ath_desc *ds; 437 struct ath_buf *bf; 438 439 #ifdef ARN_IBSS 440 size = sizeof (struct ath_desc) * (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF); 441 #else 442 size = sizeof (struct ath_desc) * (ATH_TXBUF + ATH_RXBUF); 443 #endif 444 445 err = arn_alloc_dma_mem(devinfo, &arn_desc_dma_attr, size, 446 &arn_desc_accattr, DDI_DMA_CONSISTENT, 447 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &sc->sc_desc_dma); 448 449 /* virtual address of the first descriptor */ 450 sc->sc_desc = (struct ath_desc *)sc->sc_desc_dma.mem_va; 451 452 ds = sc->sc_desc; 453 ARN_DBG((ARN_DBG_INIT, "arn: arn_desc_alloc(): DMA map: " 454 "%p (%d) -> %p\n", 455 sc->sc_desc, sc->sc_desc_dma.alength, 456 sc->sc_desc_dma.cookie.dmac_address)); 457 458 /* allocate data structures to describe TX/RX DMA buffers */ 459 #ifdef ARN_IBSS 460 sc->sc_vbuflen = sizeof (struct ath_buf) * (ATH_TXBUF + ATH_RXBUF + 461 ATH_BCBUF); 462 #else 463 sc->sc_vbuflen = sizeof (struct ath_buf) * (ATH_TXBUF + ATH_RXBUF); 464 #endif 465 bf = (struct ath_buf *)kmem_zalloc(sc->sc_vbuflen, KM_SLEEP); 466 sc->sc_vbufptr = bf; 467 468 /* DMA buffer size for each TX/RX packet */ 469 sc->sc_dmabuf_size = roundup(1000 + sizeof (struct ieee80211_frame) + 470 IEEE80211_MTU + IEEE80211_CRC_LEN + 471 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + 472 IEEE80211_WEP_CRCLEN), sc->sc_cachelsz); 473 474 /* create RX buffer list */ 475 err = arn_buflist_setup(devinfo, sc, &sc->sc_rxbuf_list, &bf, &ds, 476 ATH_RXBUF, DDI_DMA_READ | DDI_DMA_STREAMING); 477 if (err != DDI_SUCCESS) { 478 arn_desc_free(sc); 479 return (err); 480 } 481 482 /* create TX buffer list */ 483 err = arn_buflist_setup(devinfo, sc, &sc->sc_txbuf_list, &bf, &ds, 484 ATH_TXBUF, DDI_DMA_STREAMING); 485 if (err != DDI_SUCCESS) { 486 arn_desc_free(sc); 487 return (err); 488 } 489 490 /* create beacon buffer list */ 491 #ifdef ARN_IBSS 492 err = arn_buflist_setup(devinfo, sc, &sc->sc_bcbuf_list, &bf, &ds, 493 ATH_BCBUF, DDI_DMA_STREAMING); 494 if (err != DDI_SUCCESS) { 495 arn_desc_free(sc); 496 return (err); 497 } 498 #endif 499 500 return (DDI_SUCCESS); 501 } 502 503 static struct ath_rate_table * 504 /* LINTED E_STATIC_UNUSED */ 505 arn_get_ratetable(struct arn_softc *sc, uint32_t mode) 506 { 507 struct ath_rate_table *rate_table = NULL; 508 509 switch (mode) { 510 case IEEE80211_MODE_11A: 511 rate_table = sc->hw_rate_table[ATH9K_MODE_11A]; 512 break; 513 case IEEE80211_MODE_11B: 514 rate_table = sc->hw_rate_table[ATH9K_MODE_11B]; 515 break; 516 case IEEE80211_MODE_11G: 517 rate_table = sc->hw_rate_table[ATH9K_MODE_11G]; 518 break; 519 #ifdef ARB_11N 520 case IEEE80211_MODE_11NA_HT20: 521 rate_table = sc->hw_rate_table[ATH9K_MODE_11NA_HT20]; 522 break; 523 case IEEE80211_MODE_11NG_HT20: 524 rate_table = sc->hw_rate_table[ATH9K_MODE_11NG_HT20]; 525 break; 526 case IEEE80211_MODE_11NA_HT40PLUS: 527 rate_table = sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS]; 528 break; 529 case IEEE80211_MODE_11NA_HT40MINUS: 530 rate_table = sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS]; 531 break; 532 case IEEE80211_MODE_11NG_HT40PLUS: 533 rate_table = sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS]; 534 break; 535 case IEEE80211_MODE_11NG_HT40MINUS: 536 rate_table = sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS]; 537 break; 538 #endif 539 default: 540 ARN_DBG((ARN_DBG_FATAL, "arn: arn_get_ratetable(): " 541 "invalid mode %u\n", mode)); 542 return (NULL); 543 } 544 545 return (rate_table); 546 547 } 548 549 static void 550 arn_setcurmode(struct arn_softc *sc, enum wireless_mode mode) 551 { 552 struct ath_rate_table *rt; 553 int i; 554 555 for (i = 0; i < sizeof (sc->asc_rixmap); i++) 556 sc->asc_rixmap[i] = 0xff; 557 558 rt = sc->hw_rate_table[mode]; 559 ASSERT(rt != NULL); 560 561 for (i = 0; i < rt->rate_cnt; i++) 562 sc->asc_rixmap[rt->info[i].dot11rate & 563 IEEE80211_RATE_VAL] = (uint8_t)i; /* LINT */ 564 565 sc->sc_currates = rt; 566 sc->sc_curmode = mode; 567 568 /* 569 * All protection frames are transmited at 2Mb/s for 570 * 11g, otherwise at 1Mb/s. 571 * XXX select protection rate index from rate table. 572 */ 573 sc->sc_protrix = (mode == ATH9K_MODE_11G ? 1 : 0); 574 } 575 576 static enum wireless_mode 577 arn_chan2mode(struct ath9k_channel *chan) 578 { 579 if (chan->chanmode == CHANNEL_A) 580 return (ATH9K_MODE_11A); 581 else if (chan->chanmode == CHANNEL_G) 582 return (ATH9K_MODE_11G); 583 else if (chan->chanmode == CHANNEL_B) 584 return (ATH9K_MODE_11B); 585 else if (chan->chanmode == CHANNEL_A_HT20) 586 return (ATH9K_MODE_11NA_HT20); 587 else if (chan->chanmode == CHANNEL_G_HT20) 588 return (ATH9K_MODE_11NG_HT20); 589 else if (chan->chanmode == CHANNEL_A_HT40PLUS) 590 return (ATH9K_MODE_11NA_HT40PLUS); 591 else if (chan->chanmode == CHANNEL_A_HT40MINUS) 592 return (ATH9K_MODE_11NA_HT40MINUS); 593 else if (chan->chanmode == CHANNEL_G_HT40PLUS) 594 return (ATH9K_MODE_11NG_HT40PLUS); 595 else if (chan->chanmode == CHANNEL_G_HT40MINUS) 596 return (ATH9K_MODE_11NG_HT40MINUS); 597 598 return (ATH9K_MODE_11B); 599 } 600 601 static void 602 arn_update_txpow(struct arn_softc *sc) 603 { 604 struct ath_hal *ah = sc->sc_ah; 605 uint32_t txpow; 606 607 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) { 608 (void) ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit); 609 /* read back in case value is clamped */ 610 (void) ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow); 611 sc->sc_curtxpow = (uint32_t)txpow; 612 } 613 } 614 615 static void 616 arn_setup_rates(struct arn_softc *sc, uint32_t mode) 617 { 618 int i, maxrates; 619 struct ath_rate_table *rate_table = NULL; 620 struct ieee80211_rateset *rateset; 621 ieee80211com_t *ic = (ieee80211com_t *)sc; 622 623 /* rate_table = arn_get_ratetable(sc, mode); */ 624 switch (mode) { 625 case IEEE80211_MODE_11A: 626 rate_table = sc->hw_rate_table[ATH9K_MODE_11A]; 627 break; 628 case IEEE80211_MODE_11B: 629 rate_table = sc->hw_rate_table[ATH9K_MODE_11B]; 630 break; 631 case IEEE80211_MODE_11G: 632 rate_table = sc->hw_rate_table[ATH9K_MODE_11G]; 633 break; 634 #ifdef ARN_11N 635 case IEEE80211_MODE_11NA_HT20: 636 rate_table = sc->hw_rate_table[ATH9K_MODE_11NA_HT20]; 637 break; 638 case IEEE80211_MODE_11NG_HT20: 639 rate_table = sc->hw_rate_table[ATH9K_MODE_11NG_HT20]; 640 break; 641 case IEEE80211_MODE_11NA_HT40PLUS: 642 rate_table = sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS]; 643 break; 644 case IEEE80211_MODE_11NA_HT40MINUS: 645 rate_table = sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS]; 646 break; 647 case IEEE80211_MODE_11NG_HT40PLUS: 648 rate_table = sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS]; 649 break; 650 case IEEE80211_MODE_11NG_HT40MINUS: 651 rate_table = sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS]; 652 break; 653 #endif 654 default: 655 ARN_DBG((ARN_DBG_RATE, "arn: arn_get_ratetable(): " 656 "invalid mode %u\n", mode)); 657 break; 658 } 659 if (rate_table == NULL) 660 return; 661 if (rate_table->rate_cnt > ATH_RATE_MAX) { 662 ARN_DBG((ARN_DBG_RATE, "arn: arn_rate_setup(): " 663 "rate table too small (%u > %u)\n", 664 rate_table->rate_cnt, IEEE80211_RATE_MAXSIZE)); 665 maxrates = ATH_RATE_MAX; 666 } else 667 maxrates = rate_table->rate_cnt; 668 669 ARN_DBG((ARN_DBG_RATE, "arn: arn_rate_setup(): " 670 "maxrates is %d\n", maxrates)); 671 672 rateset = &ic->ic_sup_rates[mode]; 673 for (i = 0; i < maxrates; i++) { 674 rateset->ir_rates[i] = rate_table->info[i].dot11rate; 675 ARN_DBG((ARN_DBG_RATE, "arn: arn_rate_setup(): " 676 "%d\n", rate_table->info[i].dot11rate)); 677 } 678 rateset->ir_nrates = (uint8_t)maxrates; /* ??? */ 679 } 680 681 static int 682 arn_setup_channels(struct arn_softc *sc) 683 { 684 struct ath_hal *ah = sc->sc_ah; 685 ieee80211com_t *ic = (ieee80211com_t *)sc; 686 int nchan, i, index; 687 uint8_t regclassids[ATH_REGCLASSIDS_MAX]; 688 uint32_t nregclass = 0; 689 struct ath9k_channel *c; 690 691 /* Fill in ah->ah_channels */ 692 if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (uint32_t *)&nchan, 693 regclassids, ATH_REGCLASSIDS_MAX, &nregclass, CTRY_DEFAULT, 694 B_FALSE, 1)) { 695 uint32_t rd = ah->ah_currentRD; 696 ARN_DBG((ARN_DBG_CHANNEL, "arn: arn_setup_channels(): " 697 "unable to collect channel list; " 698 "regdomain likely %u country code %u\n", 699 rd, CTRY_DEFAULT)); 700 return (EINVAL); 701 } 702 703 ARN_DBG((ARN_DBG_CHANNEL, "arn: arn_setup_channels(): " 704 "number of channel is %d\n", nchan)); 705 706 for (i = 0; i < nchan; i++) { 707 c = &ah->ah_channels[i]; 708 uint16_t flags; 709 index = ath9k_hw_mhz2ieee(ah, c->channel, c->channelFlags); 710 711 if (index > IEEE80211_CHAN_MAX) { 712 ARN_DBG((ARN_DBG_CHANNEL, 713 "arn: arn_setup_channels(): " 714 "bad hal channel %d (%u/%x) ignored\n", 715 index, c->channel, c->channelFlags)); 716 continue; 717 } 718 /* NB: flags are known to be compatible */ 719 if (index < 0) { 720 /* 721 * can't handle frequency <2400MHz (negative 722 * channels) right now 723 */ 724 ARN_DBG((ARN_DBG_CHANNEL, 725 "arn: arn_setup_channels(): " 726 "hal channel %d (%u/%x) " 727 "cannot be handled, ignored\n", 728 index, c->channel, c->channelFlags)); 729 continue; 730 } 731 732 /* 733 * Calculate net80211 flags; most are compatible 734 * but some need massaging. Note the static turbo 735 * conversion can be removed once net80211 is updated 736 * to understand static vs. dynamic turbo. 737 */ 738 739 flags = c->channelFlags & (CHANNEL_ALL | CHANNEL_PASSIVE); 740 741 if (ic->ic_sup_channels[index].ich_freq == 0) { 742 ic->ic_sup_channels[index].ich_freq = c->channel; 743 ic->ic_sup_channels[index].ich_flags = flags; 744 } else { 745 /* channels overlap; e.g. 11g and 11b */ 746 ic->ic_sup_channels[index].ich_flags |= flags; 747 } 748 if ((c->channelFlags & CHANNEL_G) == CHANNEL_G) { 749 sc->sc_have11g = 1; 750 ic->ic_caps |= IEEE80211_C_SHPREAMBLE | 751 IEEE80211_C_SHSLOT; /* short slot time */ 752 } 753 } 754 755 return (0); 756 } 757 758 uint32_t 759 arn_chan2flags(ieee80211com_t *isc, struct ieee80211_channel *chan) 760 { 761 static const uint32_t modeflags[] = { 762 0, /* IEEE80211_MODE_AUTO */ 763 CHANNEL_A, /* IEEE80211_MODE_11A */ 764 CHANNEL_B, /* IEEE80211_MODE_11B */ 765 CHANNEL_G, /* IEEE80211_MODE_11G */ 766 0, /* */ 767 0, /* */ 768 0 /* */ 769 }; 770 return (modeflags[ieee80211_chan2mode(isc, chan)]); 771 } 772 773 /* 774 * Update internal state after a channel change. 775 */ 776 void 777 arn_chan_change(struct arn_softc *sc, struct ieee80211_channel *chan) 778 { 779 struct ieee80211com *ic = &sc->sc_isc; 780 enum ieee80211_phymode mode; 781 enum wireless_mode wlmode; 782 783 /* 784 * Change channels and update the h/w rate map 785 * if we're switching; e.g. 11a to 11b/g. 786 */ 787 mode = ieee80211_chan2mode(ic, chan); 788 switch (mode) { 789 case IEEE80211_MODE_11A: 790 wlmode = ATH9K_MODE_11A; 791 break; 792 case IEEE80211_MODE_11B: 793 wlmode = ATH9K_MODE_11B; 794 break; 795 case IEEE80211_MODE_11G: 796 wlmode = ATH9K_MODE_11B; 797 break; 798 default: 799 break; 800 } 801 if (wlmode != sc->sc_curmode) 802 arn_setcurmode(sc, wlmode); 803 804 } 805 806 /* 807 * Set/change channels. If the channel is really being changed, it's done 808 * by reseting the chip. To accomplish this we must first cleanup any pending 809 * DMA, then restart stuff. 810 */ 811 static int 812 arn_set_channel(struct arn_softc *sc, struct ath9k_channel *hchan) 813 { 814 struct ath_hal *ah = sc->sc_ah; 815 ieee80211com_t *ic = &sc->sc_isc; 816 boolean_t fastcc = B_TRUE; 817 boolean_t stopped; 818 struct ieee80211_channel chan; 819 enum wireless_mode curmode; 820 821 if (sc->sc_flags & SC_OP_INVALID) 822 return (EIO); 823 824 if (hchan->channel != sc->sc_ah->ah_curchan->channel || 825 hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags || 826 (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) || 827 (sc->sc_flags & SC_OP_FULL_RESET)) { 828 int status; 829 830 /* 831 * This is only performed if the channel settings have 832 * actually changed. 833 * 834 * To switch channels clear any pending DMA operations; 835 * wait long enough for the RX fifo to drain, reset the 836 * hardware at the new frequency, and then re-enable 837 * the relevant bits of the h/w. 838 */ 839 (void) ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */ 840 arn_draintxq(sc, B_FALSE); /* clear pending tx frames */ 841 stopped = arn_stoprecv(sc); /* turn off frame recv */ 842 843 /* 844 * XXX: do not flush receive queue here. We don't want 845 * to flush data frames already in queue because of 846 * changing channel. 847 */ 848 849 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET)) 850 fastcc = B_FALSE; 851 852 ARN_DBG((ARN_DBG_CHANNEL, "arn: arn_set_channel(): " 853 "(%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n", 854 sc->sc_ah->ah_curchan->channel, 855 hchan->channel, hchan->channelFlags, sc->tx_chan_width)); 856 857 if (!ath9k_hw_reset(ah, hchan, sc->tx_chan_width, 858 sc->sc_tx_chainmask, sc->sc_rx_chainmask, 859 sc->sc_ht_extprotspacing, fastcc, &status)) { 860 ARN_DBG((ARN_DBG_FATAL, "arn: arn_set_channel(): " 861 "unable to reset channel %u (%uMhz) " 862 "flags 0x%x hal status %u\n", 863 ath9k_hw_mhz2ieee(ah, hchan->channel, 864 hchan->channelFlags), 865 hchan->channel, hchan->channelFlags, status)); 866 return (EIO); 867 } 868 869 sc->sc_curchan = *hchan; 870 871 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE; 872 sc->sc_flags &= ~SC_OP_FULL_RESET; 873 874 if (arn_startrecv(sc) != 0) { 875 arn_problem("arn: arn_set_channel(): " 876 "unable to restart recv logic\n"); 877 return (EIO); 878 } 879 880 chan.ich_freq = hchan->channel; 881 chan.ich_flags = hchan->channelFlags; 882 ic->ic_ibss_chan = &chan; 883 884 /* 885 * Change channels and update the h/w rate map 886 * if we're switching; e.g. 11a to 11b/g. 887 */ 888 curmode = arn_chan2mode(hchan); 889 if (curmode != sc->sc_curmode) 890 arn_setcurmode(sc, arn_chan2mode(hchan)); 891 892 arn_update_txpow(sc); 893 894 (void) ath9k_hw_set_interrupts(ah, sc->sc_imask); 895 } 896 897 return (0); 898 } 899 900 /* 901 * This routine performs the periodic noise floor calibration function 902 * that is used to adjust and optimize the chip performance. This 903 * takes environmental changes (location, temperature) into account. 904 * When the task is complete, it reschedules itself depending on the 905 * appropriate interval that was calculated. 906 */ 907 static void 908 arn_ani_calibrate(void *arg) 909 910 { 911 ieee80211com_t *ic = (ieee80211com_t *)arg; 912 struct arn_softc *sc = (struct arn_softc *)ic; 913 struct ath_hal *ah = sc->sc_ah; 914 boolean_t longcal = B_FALSE; 915 boolean_t shortcal = B_FALSE; 916 boolean_t aniflag = B_FALSE; 917 unsigned int timestamp = drv_hztousec(ddi_get_lbolt())/1000; 918 uint32_t cal_interval; 919 920 /* 921 * don't calibrate when we're scanning. 922 * we are most likely not on our home channel. 923 */ 924 if (ic->ic_state != IEEE80211_S_RUN) 925 goto settimer; 926 927 /* Long calibration runs independently of short calibration. */ 928 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) { 929 longcal = B_TRUE; 930 ARN_DBG((ARN_DBG_CALIBRATE, "arn: " 931 "%s: longcal @%lu\n", __func__, drv_hztousec)); 932 sc->sc_ani.sc_longcal_timer = timestamp; 933 } 934 935 /* Short calibration applies only while sc_caldone is FALSE */ 936 if (!sc->sc_ani.sc_caldone) { 937 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >= 938 ATH_SHORT_CALINTERVAL) { 939 shortcal = B_TRUE; 940 ARN_DBG((ARN_DBG_CALIBRATE, "arn: " 941 "%s: shortcal @%lu\n", 942 __func__, drv_hztousec)); 943 sc->sc_ani.sc_shortcal_timer = timestamp; 944 sc->sc_ani.sc_resetcal_timer = timestamp; 945 } 946 } else { 947 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >= 948 ATH_RESTART_CALINTERVAL) { 949 ath9k_hw_reset_calvalid(ah, ah->ah_curchan, 950 &sc->sc_ani.sc_caldone); 951 if (sc->sc_ani.sc_caldone) 952 sc->sc_ani.sc_resetcal_timer = timestamp; 953 } 954 } 955 956 /* Verify whether we must check ANI */ 957 if ((timestamp - sc->sc_ani.sc_checkani_timer) >= 958 ATH_ANI_POLLINTERVAL) { 959 aniflag = B_TRUE; 960 sc->sc_ani.sc_checkani_timer = timestamp; 961 } 962 963 /* Skip all processing if there's nothing to do. */ 964 if (longcal || shortcal || aniflag) { 965 /* Call ANI routine if necessary */ 966 if (aniflag) 967 ath9k_hw_ani_monitor(ah, &sc->sc_halstats, 968 ah->ah_curchan); 969 970 /* Perform calibration if necessary */ 971 if (longcal || shortcal) { 972 boolean_t iscaldone = B_FALSE; 973 974 if (ath9k_hw_calibrate(ah, ah->ah_curchan, 975 sc->sc_rx_chainmask, longcal, &iscaldone)) { 976 if (longcal) 977 sc->sc_ani.sc_noise_floor = 978 ath9k_hw_getchan_noise(ah, 979 ah->ah_curchan); 980 981 ARN_DBG((ARN_DBG_CALIBRATE, "arn: " 982 "%s: calibrate chan %u/%x nf: %d\n", 983 __func__, 984 ah->ah_curchan->channel, 985 ah->ah_curchan->channelFlags, 986 sc->sc_ani.sc_noise_floor)); 987 } else { 988 ARN_DBG((ARN_DBG_CALIBRATE, "arn: " 989 "%s: calibrate chan %u/%x failed\n", 990 __func__, 991 ah->ah_curchan->channel, 992 ah->ah_curchan->channelFlags)); 993 } 994 sc->sc_ani.sc_caldone = iscaldone; 995 } 996 } 997 998 settimer: 999 /* 1000 * Set timer interval based on previous results. 1001 * The interval must be the shortest necessary to satisfy ANI, 1002 * short calibration and long calibration. 1003 */ 1004 cal_interval = ATH_LONG_CALINTERVAL; 1005 if (sc->sc_ah->ah_config.enable_ani) 1006 cal_interval = 1007 min(cal_interval, (uint32_t)ATH_ANI_POLLINTERVAL); 1008 1009 if (!sc->sc_ani.sc_caldone) 1010 cal_interval = min(cal_interval, 1011 (uint32_t)ATH_SHORT_CALINTERVAL); 1012 1013 sc->sc_scan_timer = 0; 1014 sc->sc_scan_timer = timeout(arn_ani_calibrate, (void *)sc, 1015 drv_usectohz(cal_interval * 1000)); 1016 } 1017 1018 static void 1019 arn_stop_caltimer(struct arn_softc *sc) 1020 { 1021 timeout_id_t tmp_id = 0; 1022 1023 while ((sc->sc_cal_timer != 0) && (tmp_id != sc->sc_cal_timer)) { 1024 tmp_id = sc->sc_cal_timer; 1025 (void) untimeout(tmp_id); 1026 } 1027 sc->sc_cal_timer = 0; 1028 } 1029 1030 static uint_t 1031 arn_isr(caddr_t arg) 1032 { 1033 /* LINTED E_BAD_PTR_CAST_ALIGN */ 1034 struct arn_softc *sc = (struct arn_softc *)arg; 1035 struct ath_hal *ah = sc->sc_ah; 1036 enum ath9k_int status; 1037 ieee80211com_t *ic = (ieee80211com_t *)sc; 1038 1039 ARN_LOCK(sc); 1040 1041 if (sc->sc_flags & SC_OP_INVALID) { 1042 /* 1043 * The hardware is not ready/present, don't 1044 * touch anything. Note this can happen early 1045 * on if the IRQ is shared. 1046 */ 1047 ARN_UNLOCK(sc); 1048 return (DDI_INTR_UNCLAIMED); 1049 } 1050 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */ 1051 ARN_UNLOCK(sc); 1052 return (DDI_INTR_UNCLAIMED); 1053 } 1054 1055 /* 1056 * Figure out the reason(s) for the interrupt. Note 1057 * that the hal returns a pseudo-ISR that may include 1058 * bits we haven't explicitly enabled so we mask the 1059 * value to insure we only process bits we requested. 1060 */ 1061 (void) ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ 1062 1063 status &= sc->sc_imask; /* discard unasked-for bits */ 1064 1065 /* 1066 * If there are no status bits set, then this interrupt was not 1067 * for me (should have been caught above). 1068 */ 1069 if (!status) 1070 return (DDI_INTR_UNCLAIMED); 1071 1072 sc->sc_intrstatus = status; 1073 1074 if (status & ATH9K_INT_FATAL) { 1075 /* need a chip reset */ 1076 ARN_DBG((ARN_DBG_INTERRUPT, "arn: arn_isr(): " 1077 "ATH9K_INT_FATAL\n")); 1078 goto reset; 1079 } else if (status & ATH9K_INT_RXORN) { 1080 /* need a chip reset */ 1081 ARN_DBG((ARN_DBG_INTERRUPT, "arn: arn_isr(): " 1082 "ATH9K_INT_RXORN\n")); 1083 goto reset; 1084 } else { 1085 if (status & ATH9K_INT_RXEOL) { 1086 /* 1087 * NB: the hardware should re-read the link when 1088 * RXE bit is written, but it doesn't work 1089 * at least on older hardware revs. 1090 */ 1091 ARN_DBG((ARN_DBG_INTERRUPT, "arn: arn_isr(): " 1092 "ATH9K_INT_RXEOL\n")); 1093 sc->sc_rxlink = NULL; 1094 } 1095 if (status & ATH9K_INT_TXURN) { 1096 /* bump tx trigger level */ 1097 ARN_DBG((ARN_DBG_INTERRUPT, "arn: arn_isr(): " 1098 "ATH9K_INT_TXURN\n")); 1099 (void) ath9k_hw_updatetxtriglevel(ah, B_TRUE); 1100 } 1101 /* XXX: optimize this */ 1102 if (status & ATH9K_INT_RX) { 1103 ARN_DBG((ARN_DBG_INTERRUPT, "arn: arn_isr(): " 1104 "ATH9K_INT_RX\n")); 1105 sc->sc_rx_pend = 1; 1106 ddi_trigger_softintr(sc->sc_softint_id); 1107 } 1108 if (status & ATH9K_INT_TX) { 1109 ARN_DBG((ARN_DBG_INTERRUPT, "arn: arn_isr(): " 1110 "ATH9K_INT_TX\n")); 1111 if (ddi_taskq_dispatch(sc->sc_tq, 1112 arn_tx_int_proc, sc, DDI_NOSLEEP) != 1113 DDI_SUCCESS) { 1114 arn_problem("arn: arn_isr(): " 1115 "No memory for tx taskq\n"); 1116 } 1117 } 1118 #ifdef ARN_ATH9K_INT_MIB 1119 if (status & ATH9K_INT_MIB) { 1120 /* 1121 * Disable interrupts until we service the MIB 1122 * interrupt; otherwise it will continue to 1123 * fire. 1124 */ 1125 (void) ath9k_hw_set_interrupts(ah, 0); 1126 /* 1127 * Let the hal handle the event. We assume 1128 * it will clear whatever condition caused 1129 * the interrupt. 1130 */ 1131 ath9k_hw_procmibevent(ah, &sc->sc_halstats); 1132 (void) ath9k_hw_set_interrupts(ah, sc->sc_imask); 1133 ARN_DBG((ARN_DBG_INTERRUPT, "arn: arn_isr(): " 1134 "ATH9K_INT_MIB\n")); 1135 } 1136 #endif 1137 1138 #ifdef ARN_ATH9K_INT_TIM_TIMER 1139 if (status & ATH9K_INT_TIM_TIMER) { 1140 ARN_DBG((ARN_DBG_INTERRUPT, "arn: arn_isr(): " 1141 "ATH9K_INT_TIM_TIMER\n")); 1142 if (!(ah->ah_caps.hw_caps & 1143 ATH9K_HW_CAP_AUTOSLEEP)) { 1144 /* 1145 * Clear RxAbort bit so that we can 1146 * receive frames 1147 */ 1148 ath9k_hw_setrxabort(ah, 0); 1149 goto reset; 1150 } 1151 } 1152 #endif 1153 1154 if (status & ATH9K_INT_BMISS) { 1155 ARN_DBG((ARN_DBG_INTERRUPT, "arn: arn_isr(): " 1156 "ATH9K_INT_BMISS\n")); 1157 1158 if (ddi_taskq_dispatch(sc->sc_tq, arn_bmiss_proc, 1159 sc, DDI_NOSLEEP) != DDI_SUCCESS) { 1160 arn_problem("arn: arn_isr(): " 1161 "No memory available for bmiss taskq\n"); 1162 } 1163 } 1164 1165 #ifdef ARN_ATH9K_INT_CST 1166 /* carrier sense timeout */ 1167 if (status & ATH9K_INT_CST) { 1168 ARN_DBG((ARN_DBG_INTERRUPT, "arn: arn_isr(): " 1169 "ATH9K_INT_CST\n")); 1170 } 1171 #endif 1172 1173 ARN_UNLOCK(sc); 1174 1175 if (status & ATH9K_INT_SWBA) { 1176 ARN_DBG((ARN_DBG_INTERRUPT, "arn: arn_isr(): " 1177 "ATH9K_INT_SWBA\n")); 1178 /* This will occur only in Host-AP or Ad-Hoc mode */ 1179 return (DDI_INTR_CLAIMED); 1180 } 1181 } 1182 1183 return (DDI_INTR_CLAIMED); 1184 reset: 1185 ARN_DBG((ARN_DBG_INTERRUPT, "Rset for fatal err\n")); 1186 (void) arn_reset(ic); 1187 ARN_UNLOCK(sc); 1188 return (DDI_INTR_CLAIMED); 1189 } 1190 1191 static int 1192 arn_get_channel(struct arn_softc *sc, struct ieee80211_channel *chan) 1193 { 1194 int i; 1195 1196 for (i = 0; i < sc->sc_ah->ah_nchan; i++) { 1197 if (sc->sc_ah->ah_channels[i].channel == chan->ich_freq) 1198 return (i); 1199 } 1200 1201 return (-1); 1202 } 1203 1204 int 1205 arn_reset(ieee80211com_t *ic) 1206 { 1207 struct arn_softc *sc = (struct arn_softc *)ic; 1208 struct ath_hal *ah = sc->sc_ah; 1209 int status; 1210 int error = 0; 1211 1212 (void) ath9k_hw_set_interrupts(ah, 0); 1213 arn_draintxq(sc, 0); 1214 (void) arn_stoprecv(sc); 1215 1216 if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, sc->tx_chan_width, 1217 sc->sc_tx_chainmask, sc->sc_rx_chainmask, 1218 sc->sc_ht_extprotspacing, B_FALSE, &status)) { 1219 ARN_DBG((ARN_DBG_RESET, "arn: arn_reset(): " 1220 "unable to reset hardware; hal status %u\n", status)); 1221 error = EIO; 1222 } 1223 1224 if (arn_startrecv(sc) != 0) 1225 ARN_DBG((ARN_DBG_RESET, "arn: arn_reset(): " 1226 "unable to start recv logic\n")); 1227 1228 /* 1229 * We may be doing a reset in response to a request 1230 * that changes the channel so update any state that 1231 * might change as a result. 1232 */ 1233 arn_setcurmode(sc, arn_chan2mode(sc->sc_ah->ah_curchan)); 1234 1235 arn_update_txpow(sc); 1236 1237 if (sc->sc_flags & SC_OP_BEACONS) 1238 arn_beacon_config(sc); /* restart beacons */ 1239 1240 (void) ath9k_hw_set_interrupts(ah, sc->sc_imask); 1241 1242 return (error); 1243 } 1244 1245 int 1246 arn_get_hal_qnum(uint16_t queue, struct arn_softc *sc) 1247 { 1248 int qnum; 1249 1250 switch (queue) { 1251 case WME_AC_VO: 1252 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO]; 1253 break; 1254 case WME_AC_VI: 1255 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI]; 1256 break; 1257 case WME_AC_BE: 1258 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE]; 1259 break; 1260 case WME_AC_BK: 1261 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK]; 1262 break; 1263 default: 1264 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE]; 1265 break; 1266 } 1267 1268 return (qnum); 1269 } 1270 1271 static struct { 1272 uint32_t version; 1273 const char *name; 1274 } ath_mac_bb_names[] = { 1275 { AR_SREV_VERSION_5416_PCI, "5416" }, 1276 { AR_SREV_VERSION_5416_PCIE, "5418" }, 1277 { AR_SREV_VERSION_9100, "9100" }, 1278 { AR_SREV_VERSION_9160, "9160" }, 1279 { AR_SREV_VERSION_9280, "9280" }, 1280 { AR_SREV_VERSION_9285, "9285" } 1281 }; 1282 1283 static struct { 1284 uint16_t version; 1285 const char *name; 1286 } ath_rf_names[] = { 1287 { 0, "5133" }, 1288 { AR_RAD5133_SREV_MAJOR, "5133" }, 1289 { AR_RAD5122_SREV_MAJOR, "5122" }, 1290 { AR_RAD2133_SREV_MAJOR, "2133" }, 1291 { AR_RAD2122_SREV_MAJOR, "2122" } 1292 }; 1293 1294 /* 1295 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. 1296 */ 1297 1298 static const char * 1299 arn_mac_bb_name(uint32_t mac_bb_version) 1300 { 1301 int i; 1302 1303 for (i = 0; i < ARRAY_SIZE(ath_mac_bb_names); i++) { 1304 if (ath_mac_bb_names[i].version == mac_bb_version) { 1305 return (ath_mac_bb_names[i].name); 1306 } 1307 } 1308 1309 return ("????"); 1310 } 1311 1312 /* 1313 * Return the RF name. "????" is returned if the RF is unknown. 1314 */ 1315 1316 static const char * 1317 arn_rf_name(uint16_t rf_version) 1318 { 1319 int i; 1320 1321 for (i = 0; i < ARRAY_SIZE(ath_rf_names); i++) { 1322 if (ath_rf_names[i].version == rf_version) { 1323 return (ath_rf_names[i].name); 1324 } 1325 } 1326 1327 return ("????"); 1328 } 1329 1330 static void 1331 arn_next_scan(void *arg) 1332 { 1333 ieee80211com_t *ic = arg; 1334 struct arn_softc *sc = (struct arn_softc *)ic; 1335 1336 sc->sc_scan_timer = 0; 1337 if (ic->ic_state == IEEE80211_S_SCAN) { 1338 sc->sc_scan_timer = timeout(arn_next_scan, (void *)sc, 1339 drv_usectohz(arn_dwelltime * 1000)); 1340 ieee80211_next_scan(ic); 1341 } 1342 } 1343 1344 static void 1345 arn_stop_scantimer(struct arn_softc *sc) 1346 { 1347 timeout_id_t tmp_id = 0; 1348 1349 while ((sc->sc_scan_timer != 0) && (tmp_id != sc->sc_scan_timer)) { 1350 tmp_id = sc->sc_scan_timer; 1351 (void) untimeout(tmp_id); 1352 } 1353 sc->sc_scan_timer = 0; 1354 } 1355 1356 static int32_t 1357 arn_newstate(ieee80211com_t *ic, enum ieee80211_state nstate, int arg) 1358 { 1359 struct arn_softc *sc = (struct arn_softc *)ic; 1360 struct ath_hal *ah = sc->sc_ah; 1361 struct ieee80211_node *in; 1362 int32_t i, error; 1363 uint8_t *bssid; 1364 uint32_t rfilt; 1365 enum ieee80211_state ostate; 1366 struct ath9k_channel *channel; 1367 int pos; 1368 1369 /* Should set up & init LED here */ 1370 1371 if (sc->sc_flags & SC_OP_INVALID) 1372 return (0); 1373 1374 ostate = ic->ic_state; 1375 ARN_DBG((ARN_DBG_INIT, "arn: arn_newstate(): " 1376 "%x -> %x!\n", ostate, nstate)); 1377 1378 ARN_LOCK(sc); 1379 1380 if (nstate != IEEE80211_S_SCAN) 1381 arn_stop_scantimer(sc); 1382 if (nstate != IEEE80211_S_RUN) 1383 arn_stop_caltimer(sc); 1384 1385 /* Should set LED here */ 1386 1387 if (nstate == IEEE80211_S_INIT) { 1388 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); 1389 /* 1390 * Disable interrupts. 1391 */ 1392 (void) ath9k_hw_set_interrupts 1393 (ah, sc->sc_imask &~ ATH9K_INT_GLOBAL); 1394 1395 #ifdef ARN_IBSS 1396 if (ic->ic_opmode == IEEE80211_M_IBSS) { 1397 (void) ath9k_hw_stoptxdma(ah, sc->sc_beaconq); 1398 arn_beacon_return(sc); 1399 } 1400 #endif 1401 ARN_UNLOCK(sc); 1402 ieee80211_stop_watchdog(ic); 1403 goto done; 1404 } 1405 in = ic->ic_bss; 1406 1407 pos = arn_get_channel(sc, ic->ic_curchan); 1408 1409 if (pos == -1) { 1410 ARN_DBG((ARN_DBG_FATAL, "arn: " 1411 "%s: Invalid channel\n", __func__)); 1412 error = EINVAL; 1413 ARN_UNLOCK(sc); 1414 goto bad; 1415 } 1416 sc->tx_chan_width = ATH9K_HT_MACMODE_20; 1417 sc->sc_ah->ah_channels[pos].chanmode = 1418 arn_chan2flags(ic, ic->ic_curchan); 1419 channel = &sc->sc_ah->ah_channels[pos]; 1420 if (channel == NULL) { 1421 arn_problem("arn_newstate(): channel == NULL"); 1422 ARN_UNLOCK(sc); 1423 goto bad; 1424 } 1425 error = arn_set_channel(sc, channel); 1426 if (error != 0) { 1427 if (nstate != IEEE80211_S_SCAN) { 1428 ARN_UNLOCK(sc); 1429 ieee80211_reset_chan(ic); 1430 goto bad; 1431 } 1432 } 1433 1434 /* 1435 * Get the receive filter according to the 1436 * operating mode and state 1437 */ 1438 rfilt = arn_calcrxfilter(sc); 1439 1440 if (nstate == IEEE80211_S_SCAN) 1441 bssid = ic->ic_macaddr; 1442 else 1443 bssid = in->in_bssid; 1444 1445 ath9k_hw_setrxfilter(ah, rfilt); 1446 1447 if (nstate == IEEE80211_S_RUN && ic->ic_opmode != IEEE80211_M_IBSS) 1448 ath9k_hw_write_associd(ah, bssid, in->in_associd); 1449 else 1450 ath9k_hw_write_associd(ah, bssid, 0); 1451 1452 /* Check for WLAN_CAPABILITY_PRIVACY ? */ 1453 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 1454 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 1455 if (ath9k_hw_keyisvalid(ah, (uint16_t)i)) 1456 (void) ath9k_hw_keysetmac(ah, (uint16_t)i, 1457 bssid); 1458 } 1459 } 1460 1461 if (nstate == IEEE80211_S_RUN) { 1462 switch (ic->ic_opmode) { 1463 #ifdef ARN_IBSS 1464 case IEEE80211_M_IBSS: 1465 /* 1466 * Allocate and setup the beacon frame. 1467 * Stop any previous beacon DMA. 1468 */ 1469 (void) ath9k_hw_stoptxdma(ah, sc->sc_beaconq); 1470 arn_beacon_return(sc); 1471 error = arn_beacon_alloc(sc, in); 1472 if (error != 0) { 1473 ARN_UNLOCK(sc); 1474 goto bad; 1475 } 1476 /* 1477 * If joining an adhoc network defer beacon timer 1478 * configuration to the next beacon frame so we 1479 * have a current TSF to use. Otherwise we're 1480 * starting an ibss/bss so there's no need to delay. 1481 */ 1482 if (ic->ic_opmode == IEEE80211_M_IBSS && 1483 ic->ic_bss->in_tstamp.tsf != 0) { 1484 sc->sc_bsync = 1; 1485 } else { 1486 arn_beacon_config(sc); 1487 } 1488 break; 1489 #endif /* ARN_IBSS */ 1490 case IEEE80211_M_STA: 1491 if (ostate != IEEE80211_S_RUN) { 1492 /* 1493 * Defer beacon timer configuration to the next 1494 * beacon frame so we have a current TSF to use. 1495 * Any TSF collected when scanning is likely old 1496 */ 1497 #ifdef ARN_IBSS 1498 sc->sc_bsync = 1; 1499 #else 1500 /* Configure the beacon and sleep timers. */ 1501 arn_beacon_config(sc); 1502 #endif /* ARN_IBSS */ 1503 } 1504 break; 1505 default: 1506 break; 1507 } 1508 } else { 1509 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); 1510 (void) ath9k_hw_set_interrupts(ah, sc->sc_imask); 1511 } 1512 1513 /* 1514 * Reset the rate control state. 1515 */ 1516 arn_rate_ctl_reset(sc, nstate); 1517 1518 ARN_UNLOCK(sc); 1519 done: 1520 /* 1521 * Invoke the parent method to complete the work. 1522 */ 1523 error = sc->sc_newstate(ic, nstate, arg); 1524 1525 /* 1526 * Finally, start any timers. 1527 */ 1528 if (nstate == IEEE80211_S_RUN) { 1529 ieee80211_start_watchdog(ic, 1); 1530 ASSERT(sc->sc_cal_timer == 0); 1531 sc->sc_cal_timer = timeout(arn_ani_calibrate, (void *)sc, 1532 drv_usectohz(100 * 1000)); 1533 } else if ((nstate == IEEE80211_S_SCAN) && (ostate != nstate)) { 1534 /* start ap/neighbor scan timer */ 1535 /* ASSERT(sc->sc_scan_timer == 0); */ 1536 if (sc->sc_scan_timer != 0) { 1537 (void) untimeout(sc->sc_scan_timer); 1538 sc->sc_scan_timer = 0; 1539 } 1540 sc->sc_scan_timer = timeout(arn_next_scan, (void *)sc, 1541 drv_usectohz(arn_dwelltime * 1000)); 1542 } 1543 1544 bad: 1545 return (error); 1546 } 1547 1548 static void 1549 arn_watchdog(void *arg) 1550 { 1551 struct arn_softc *sc = arg; 1552 ieee80211com_t *ic = &sc->sc_isc; 1553 int ntimer = 0; 1554 1555 ARN_LOCK(sc); 1556 ic->ic_watchdog_timer = 0; 1557 if (sc->sc_flags & SC_OP_INVALID) { 1558 ARN_UNLOCK(sc); 1559 return; 1560 } 1561 1562 if (ic->ic_state == IEEE80211_S_RUN) { 1563 /* 1564 * Start the background rate control thread if we 1565 * are not configured to use a fixed xmit rate. 1566 */ 1567 if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) { 1568 sc->sc_stats.ast_rate_calls ++; 1569 if (ic->ic_opmode == IEEE80211_M_STA) 1570 arn_rate_ctl(ic, ic->ic_bss); 1571 else 1572 ieee80211_iterate_nodes(&ic->ic_sta, 1573 arn_rate_ctl, sc); 1574 } 1575 1576 ntimer = 1; 1577 } 1578 ARN_UNLOCK(sc); 1579 1580 ieee80211_watchdog(ic); 1581 if (ntimer != 0) 1582 ieee80211_start_watchdog(ic, ntimer); 1583 } 1584 1585 static struct ieee80211_node * 1586 arn_node_alloc(ieee80211com_t *ic) 1587 { 1588 struct ath_node *an; 1589 struct arn_softc *sc = (struct arn_softc *)ic; 1590 1591 an = kmem_zalloc(sizeof (struct ath_node), KM_SLEEP); 1592 arn_rate_update(sc, &an->an_node, 0); 1593 1594 return ((an != NULL) ? &an->an_node : NULL); 1595 } 1596 1597 static void 1598 arn_node_free(struct ieee80211_node *in) 1599 { 1600 ieee80211com_t *ic = in->in_ic; 1601 struct arn_softc *sc = (struct arn_softc *)ic; 1602 struct ath_buf *bf; 1603 struct ath_txq *txq; 1604 int32_t i; 1605 1606 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1607 if (ARN_TXQ_SETUP(sc, i)) { 1608 txq = &sc->sc_txq[i]; 1609 mutex_enter(&txq->axq_lock); 1610 bf = list_head(&txq->axq_list); 1611 while (bf != NULL) { 1612 if (bf->bf_in == in) { 1613 bf->bf_in = NULL; 1614 } 1615 bf = list_next(&txq->axq_list, bf); 1616 } 1617 mutex_exit(&txq->axq_lock); 1618 } 1619 } 1620 1621 ic->ic_node_cleanup(in); 1622 if (in->in_wpa_ie != NULL) 1623 ieee80211_free(in->in_wpa_ie); 1624 kmem_free(in, sizeof (struct ath_node)); 1625 } 1626 1627 /* 1628 * Allocate tx/rx key slots for TKIP. We allocate one slot for 1629 * each key. MIC is right after the decrypt/encrypt key. 1630 */ 1631 static uint16_t 1632 arn_key_alloc_pair(struct arn_softc *sc, ieee80211_keyix *txkeyix, 1633 ieee80211_keyix *rxkeyix) 1634 { 1635 uint16_t i, keyix; 1636 1637 ASSERT(!sc->sc_splitmic); 1638 for (i = 0; i < ARRAY_SIZE(sc->sc_keymap)/4; i++) { 1639 uint8_t b = sc->sc_keymap[i]; 1640 if (b == 0xff) 1641 continue; 1642 for (keyix = i * NBBY; keyix < (i + 1) * NBBY; 1643 keyix++, b >>= 1) { 1644 if ((b & 1) || is_set(keyix+64, sc->sc_keymap)) { 1645 /* full pair unavailable */ 1646 continue; 1647 } 1648 set_bit(keyix, sc->sc_keymap); 1649 set_bit(keyix+64, sc->sc_keymap); 1650 ARN_DBG((ARN_DBG_KEYCACHE, 1651 "arn_key_alloc_pair(): key pair %u,%u\n", 1652 keyix, keyix+64)); 1653 *txkeyix = *rxkeyix = keyix; 1654 return (1); 1655 } 1656 } 1657 ARN_DBG((ARN_DBG_KEYCACHE, "arn_key_alloc_pair():" 1658 " out of pair space\n")); 1659 1660 return (0); 1661 } 1662 1663 /* 1664 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1665 * each key, one for decrypt/encrypt and the other for the MIC. 1666 */ 1667 static int 1668 arn_key_alloc_2pair(struct arn_softc *sc, ieee80211_keyix *txkeyix, 1669 ieee80211_keyix *rxkeyix) 1670 { 1671 uint16_t i, keyix; 1672 1673 ASSERT(sc->sc_splitmic); 1674 for (i = 0; i < ARRAY_SIZE(sc->sc_keymap)/4; i++) { 1675 uint8_t b = sc->sc_keymap[i]; 1676 if (b != 0xff) { 1677 /* 1678 * One or more slots in this byte are free. 1679 */ 1680 keyix = i*NBBY; 1681 while (b & 1) { 1682 again: 1683 keyix++; 1684 b >>= 1; 1685 } 1686 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1687 if (is_set(keyix+32, sc->sc_keymap) || 1688 is_set(keyix+64, sc->sc_keymap) || 1689 is_set(keyix+32+64, sc->sc_keymap)) { 1690 /* full pair unavailable */ 1691 if (keyix == (i+1)*NBBY) { 1692 /* no slots were appropriate, advance */ 1693 continue; 1694 } 1695 goto again; 1696 } 1697 set_bit(keyix, sc->sc_keymap); 1698 set_bit(keyix+64, sc->sc_keymap); 1699 set_bit(keyix+32, sc->sc_keymap); 1700 set_bit(keyix+32+64, sc->sc_keymap); 1701 ARN_DBG((ARN_DBG_KEYCACHE, 1702 "arn_key_alloc_2pair(): key pair %u,%u %u,%u\n", 1703 keyix, keyix+64, 1704 keyix+32, keyix+32+64)); 1705 *txkeyix = *rxkeyix = keyix; 1706 return (1); 1707 } 1708 } 1709 ARN_DBG((ARN_DBG_KEYCACHE, "arn_key_alloc_2pair(): " 1710 " out of pair space\n")); 1711 1712 return (0); 1713 } 1714 /* 1715 * Allocate a single key cache slot. 1716 */ 1717 static int 1718 arn_key_alloc_single(struct arn_softc *sc, ieee80211_keyix *txkeyix, 1719 ieee80211_keyix *rxkeyix) 1720 { 1721 uint16_t i, keyix; 1722 1723 /* try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1724 for (i = 0; i < ARRAY_SIZE(sc->sc_keymap); i++) { 1725 uint8_t b = sc->sc_keymap[i]; 1726 1727 if (b != 0xff) { 1728 /* 1729 * One or more slots are free. 1730 */ 1731 keyix = i*NBBY; 1732 while (b & 1) 1733 keyix++, b >>= 1; 1734 set_bit(keyix, sc->sc_keymap); 1735 ARN_DBG((ARN_DBG_KEYCACHE, "arn_key_alloc_single(): " 1736 "key %u\n", keyix)); 1737 *txkeyix = *rxkeyix = keyix; 1738 return (1); 1739 } 1740 } 1741 return (0); 1742 } 1743 1744 /* 1745 * Allocate one or more key cache slots for a unicast key. The 1746 * key itself is needed only to identify the cipher. For hardware 1747 * TKIP with split cipher+MIC keys we allocate two key cache slot 1748 * pairs so that we can setup separate TX and RX MIC keys. Note 1749 * that the MIC key for a TKIP key at slot i is assumed by the 1750 * hardware to be at slot i+64. This limits TKIP keys to the first 1751 * 64 entries. 1752 */ 1753 /* ARGSUSED */ 1754 int 1755 arn_key_alloc(ieee80211com_t *ic, const struct ieee80211_key *k, 1756 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1757 { 1758 struct arn_softc *sc = (struct arn_softc *)ic; 1759 1760 /* 1761 * We allocate two pair for TKIP when using the h/w to do 1762 * the MIC. For everything else, including software crypto, 1763 * we allocate a single entry. Note that s/w crypto requires 1764 * a pass-through slot on the 5211 and 5212. The 5210 does 1765 * not support pass-through cache entries and we map all 1766 * those requests to slot 0. 1767 */ 1768 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1769 return (arn_key_alloc_single(sc, keyix, rxkeyix)); 1770 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1771 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 1772 if (sc->sc_splitmic) 1773 return (arn_key_alloc_2pair(sc, keyix, rxkeyix)); 1774 else 1775 return (arn_key_alloc_pair(sc, keyix, rxkeyix)); 1776 } else { 1777 return (arn_key_alloc_single(sc, keyix, rxkeyix)); 1778 } 1779 } 1780 1781 /* 1782 * Delete an entry in the key cache allocated by ath_key_alloc. 1783 */ 1784 int 1785 arn_key_delete(ieee80211com_t *ic, const struct ieee80211_key *k) 1786 { 1787 struct arn_softc *sc = (struct arn_softc *)ic; 1788 struct ath_hal *ah = sc->sc_ah; 1789 const struct ieee80211_cipher *cip = k->wk_cipher; 1790 ieee80211_keyix keyix = k->wk_keyix; 1791 1792 ARN_DBG((ARN_DBG_KEYCACHE, "arn_key_delete():" 1793 " delete key %u ic_cipher=0x%x\n", keyix, cip->ic_cipher)); 1794 1795 (void) ath9k_hw_keyreset(ah, keyix); 1796 /* 1797 * Handle split tx/rx keying required for TKIP with h/w MIC. 1798 */ 1799 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1800 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1801 (void) ath9k_hw_keyreset(ah, keyix+32); /* RX key */ 1802 1803 if (keyix >= IEEE80211_WEP_NKID) { 1804 /* 1805 * Don't touch keymap entries for global keys so 1806 * they are never considered for dynamic allocation. 1807 */ 1808 clr_bit(keyix, sc->sc_keymap); 1809 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1810 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 1811 /* 1812 * If splitmic is true +64 is TX key MIC, 1813 * else +64 is RX key + RX key MIC. 1814 */ 1815 clr_bit(keyix+64, sc->sc_keymap); 1816 if (sc->sc_splitmic) { 1817 /* Rx key */ 1818 clr_bit(keyix+32, sc->sc_keymap); 1819 /* RX key MIC */ 1820 clr_bit(keyix+32+64, sc->sc_keymap); 1821 } 1822 } 1823 } 1824 return (1); 1825 } 1826 1827 /* 1828 * Set a TKIP key into the hardware. This handles the 1829 * potential distribution of key state to multiple key 1830 * cache slots for TKIP. 1831 */ 1832 static int 1833 arn_keyset_tkip(struct arn_softc *sc, const struct ieee80211_key *k, 1834 struct ath9k_keyval *hk, const uint8_t mac[IEEE80211_ADDR_LEN]) 1835 { 1836 uint8_t *key_rxmic = NULL; 1837 uint8_t *key_txmic = NULL; 1838 uint8_t *key = (uint8_t *)&(k->wk_key[0]); 1839 struct ath_hal *ah = sc->sc_ah; 1840 1841 key_txmic = key + 16; 1842 key_rxmic = key + 24; 1843 1844 if (mac == NULL) { 1845 /* Group key installation */ 1846 (void) memcpy(hk->kv_mic, key_rxmic, sizeof (hk->kv_mic)); 1847 return (ath9k_hw_set_keycache_entry(ah, k->wk_keyix, hk, 1848 mac, B_FALSE)); 1849 } 1850 if (!sc->sc_splitmic) { 1851 /* 1852 * data key goes at first index, 1853 * the hal handles the MIC keys at index+64. 1854 */ 1855 (void) memcpy(hk->kv_mic, key_rxmic, sizeof (hk->kv_mic)); 1856 (void) memcpy(hk->kv_txmic, key_txmic, sizeof (hk->kv_txmic)); 1857 return (ath9k_hw_set_keycache_entry(ah, k->wk_keyix, hk, 1858 mac, B_FALSE)); 1859 } 1860 /* 1861 * TX key goes at first index, RX key at +32. 1862 * The hal handles the MIC keys at index+64. 1863 */ 1864 (void) memcpy(hk->kv_mic, key_txmic, sizeof (hk->kv_mic)); 1865 if (!(ath9k_hw_set_keycache_entry(ah, k->wk_keyix, hk, NULL, 1866 B_FALSE))) { 1867 /* Txmic entry failed. No need to proceed further */ 1868 ARN_DBG((ARN_DBG_KEYCACHE, 1869 "%s Setting TX MIC Key Failed\n", __func__)); 1870 return (0); 1871 } 1872 1873 (void) memcpy(hk->kv_mic, key_rxmic, sizeof (hk->kv_mic)); 1874 1875 /* XXX delete tx key on failure? */ 1876 return (ath9k_hw_set_keycache_entry(ah, k->wk_keyix, hk, mac, B_FALSE)); 1877 1878 } 1879 1880 int 1881 arn_key_set(ieee80211com_t *ic, const struct ieee80211_key *k, 1882 const uint8_t mac[IEEE80211_ADDR_LEN]) 1883 { 1884 struct arn_softc *sc = (struct arn_softc *)ic; 1885 const struct ieee80211_cipher *cip = k->wk_cipher; 1886 struct ath9k_keyval hk; 1887 1888 /* cipher table */ 1889 static const uint8_t ciphermap[] = { 1890 ATH9K_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1891 ATH9K_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1892 ATH9K_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1893 ATH9K_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1894 ATH9K_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1895 ATH9K_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1896 }; 1897 1898 bzero(&hk, sizeof (hk)); 1899 1900 /* 1901 * Software crypto uses a "clear key" so non-crypto 1902 * state kept in the key cache are maintainedd so that 1903 * rx frames have an entry to match. 1904 */ 1905 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1906 ASSERT(cip->ic_cipher < 6); 1907 hk.kv_type = ciphermap[cip->ic_cipher]; 1908 hk.kv_len = k->wk_keylen; 1909 bcopy(k->wk_key, hk.kv_val, k->wk_keylen); 1910 } else { 1911 hk.kv_type = ATH9K_CIPHER_CLR; 1912 } 1913 1914 if (hk.kv_type == ATH9K_CIPHER_TKIP && 1915 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) { 1916 return (arn_keyset_tkip(sc, k, &hk, mac)); 1917 } else { 1918 return (ath9k_hw_set_keycache_entry(sc->sc_ah, 1919 k->wk_keyix, &hk, mac, B_FALSE)); 1920 } 1921 } 1922 1923 /* 1924 * Enable/Disable short slot timing 1925 */ 1926 void 1927 arn_set_shortslot(ieee80211com_t *ic, int onoff) 1928 { 1929 struct ath_hal *ah = ((struct arn_softc *)ic)->sc_ah; 1930 1931 if (onoff) 1932 (void) ath9k_hw_setslottime(ah, ATH9K_SLOT_TIME_9); 1933 else 1934 (void) ath9k_hw_setslottime(ah, ATH9K_SLOT_TIME_20); 1935 } 1936 1937 static int 1938 arn_open(struct arn_softc *sc) 1939 { 1940 ieee80211com_t *ic = (ieee80211com_t *)sc; 1941 struct ieee80211_channel *curchan = ic->ic_curchan; 1942 struct ath9k_channel *init_channel; 1943 int error = 0, pos, status; 1944 1945 ARN_LOCK_ASSERT(sc); 1946 1947 pos = arn_get_channel(sc, curchan); 1948 if (pos == -1) { 1949 ARN_DBG((ARN_DBG_FATAL, "arn: " 1950 "%s: Invalid channel\n", __func__)); 1951 error = EINVAL; 1952 goto error; 1953 } 1954 1955 sc->tx_chan_width = ATH9K_HT_MACMODE_20; 1956 1957 if (sc->sc_curmode == ATH9K_MODE_11A) { 1958 sc->sc_ah->ah_channels[pos].chanmode = CHANNEL_A; 1959 } else { 1960 sc->sc_ah->ah_channels[pos].chanmode = CHANNEL_G; 1961 } 1962 1963 init_channel = &sc->sc_ah->ah_channels[pos]; 1964 1965 /* Reset SERDES registers */ 1966 ath9k_hw_configpcipowersave(sc->sc_ah, 0); 1967 1968 /* 1969 * The basic interface to setting the hardware in a good 1970 * state is ``reset''. On return the hardware is known to 1971 * be powered up and with interrupts disabled. This must 1972 * be followed by initialization of the appropriate bits 1973 * and then setup of the interrupt mask. 1974 */ 1975 if (!ath9k_hw_reset(sc->sc_ah, init_channel, 1976 sc->tx_chan_width, sc->sc_tx_chainmask, 1977 sc->sc_rx_chainmask, sc->sc_ht_extprotspacing, 1978 B_FALSE, &status)) { 1979 ARN_DBG((ARN_DBG_FATAL, "arn: " 1980 "%s: unable to reset hardware; hal status %u " 1981 "(freq %u flags 0x%x)\n", __func__, status, 1982 init_channel->channel, init_channel->channelFlags)); 1983 1984 error = EIO; 1985 goto error; 1986 } 1987 1988 /* 1989 * This is needed only to setup initial state 1990 * but it's best done after a reset. 1991 */ 1992 arn_update_txpow(sc); 1993 1994 /* 1995 * Setup the hardware after reset: 1996 * The receive engine is set going. 1997 * Frame transmit is handled entirely 1998 * in the frame output path; there's nothing to do 1999 * here except setup the interrupt mask. 2000 */ 2001 if (arn_startrecv(sc) != 0) { 2002 ARN_DBG((ARN_DBG_INIT, "arn: " 2003 "%s: unable to start recv logic\n", __func__)); 2004 error = EIO; 2005 goto error; 2006 } 2007 2008 /* Setup our intr mask. */ 2009 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX | 2010 ATH9K_INT_RXEOL | ATH9K_INT_RXORN | 2011 ATH9K_INT_FATAL | ATH9K_INT_GLOBAL; 2012 #ifdef ARN_ATH9K_HW_CAP_GTT 2013 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT) 2014 sc->sc_imask |= ATH9K_INT_GTT; 2015 #endif 2016 2017 #ifdef ARN_ATH9K_HW_CAP_GTT 2018 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) 2019 sc->sc_imask |= ATH9K_INT_CST; 2020 #endif 2021 2022 /* 2023 * Enable MIB interrupts when there are hardware phy counters. 2024 * Note we only do this (at the moment) for station mode. 2025 */ 2026 #ifdef ARN_ATH9K_INT_MIB 2027 if (ath9k_hw_phycounters(sc->sc_ah) && 2028 ((sc->sc_ah->ah_opmode == ATH9K_M_STA) || 2029 (sc->sc_ah->ah_opmode == ATH9K_M_IBSS))) 2030 sc->sc_imask |= ATH9K_INT_MIB; 2031 #endif 2032 /* 2033 * Some hardware processes the TIM IE and fires an 2034 * interrupt when the TIM bit is set. For hardware 2035 * that does, if not overridden by configuration, 2036 * enable the TIM interrupt when operating as station. 2037 */ 2038 #ifdef ARN_ATH9K_INT_TIM 2039 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) && 2040 (sc->sc_ah->ah_opmode == ATH9K_M_STA) && 2041 !sc->sc_config.swBeaconProcess) 2042 sc->sc_imask |= ATH9K_INT_TIM; 2043 #endif 2044 if (arn_chan2mode(init_channel) != sc->sc_curmode) 2045 arn_setcurmode(sc, arn_chan2mode(init_channel)); 2046 ARN_DBG((ARN_DBG_INIT, "arn: " 2047 "%s: current mode after arn_setcurmode is %d\n", 2048 __func__, sc->sc_curmode)); 2049 2050 sc->sc_isrunning = 1; 2051 2052 /* Disable BMISS interrupt when we're not associated */ 2053 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); 2054 (void) ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask); 2055 2056 return (0); 2057 2058 error: 2059 return (error); 2060 } 2061 2062 static void 2063 arn_close(struct arn_softc *sc) 2064 { 2065 ieee80211com_t *ic = (ieee80211com_t *)sc; 2066 struct ath_hal *ah = sc->sc_ah; 2067 2068 ARN_LOCK_ASSERT(sc); 2069 2070 if (!sc->sc_isrunning) 2071 return; 2072 2073 /* 2074 * Shutdown the hardware and driver 2075 * Note that some of this work is not possible if the 2076 * hardware is gone (invalid). 2077 */ 2078 ARN_UNLOCK(sc); 2079 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 2080 ieee80211_stop_watchdog(ic); 2081 ARN_LOCK(sc); 2082 2083 /* 2084 * make sure h/w will not generate any interrupt 2085 * before setting the invalid flag. 2086 */ 2087 (void) ath9k_hw_set_interrupts(ah, 0); 2088 2089 if (!(sc->sc_flags & SC_OP_INVALID)) { 2090 arn_draintxq(sc, 0); 2091 (void) arn_stoprecv(sc); 2092 (void) ath9k_hw_phy_disable(ah); 2093 } else { 2094 sc->sc_rxlink = NULL; 2095 } 2096 2097 sc->sc_isrunning = 0; 2098 } 2099 2100 /* 2101 * MAC callback functions 2102 */ 2103 static int 2104 arn_m_stat(void *arg, uint_t stat, uint64_t *val) 2105 { 2106 struct arn_softc *sc = arg; 2107 ieee80211com_t *ic = (ieee80211com_t *)sc; 2108 struct ieee80211_node *in; 2109 struct ieee80211_rateset *rs; 2110 2111 ARN_LOCK(sc); 2112 switch (stat) { 2113 case MAC_STAT_IFSPEED: 2114 in = ic->ic_bss; 2115 rs = &in->in_rates; 2116 *val = (rs->ir_rates[in->in_txrate] & IEEE80211_RATE_VAL) / 2 * 2117 1000000ull; 2118 break; 2119 case MAC_STAT_NOXMTBUF: 2120 *val = sc->sc_stats.ast_tx_nobuf + 2121 sc->sc_stats.ast_tx_nobufmgt; 2122 break; 2123 case MAC_STAT_IERRORS: 2124 *val = sc->sc_stats.ast_rx_tooshort; 2125 break; 2126 case MAC_STAT_RBYTES: 2127 *val = ic->ic_stats.is_rx_bytes; 2128 break; 2129 case MAC_STAT_IPACKETS: 2130 *val = ic->ic_stats.is_rx_frags; 2131 break; 2132 case MAC_STAT_OBYTES: 2133 *val = ic->ic_stats.is_tx_bytes; 2134 break; 2135 case MAC_STAT_OPACKETS: 2136 *val = ic->ic_stats.is_tx_frags; 2137 break; 2138 case MAC_STAT_OERRORS: 2139 case WIFI_STAT_TX_FAILED: 2140 *val = sc->sc_stats.ast_tx_fifoerr + 2141 sc->sc_stats.ast_tx_xretries + 2142 sc->sc_stats.ast_tx_discard; 2143 break; 2144 case WIFI_STAT_TX_RETRANS: 2145 *val = sc->sc_stats.ast_tx_xretries; 2146 break; 2147 case WIFI_STAT_FCS_ERRORS: 2148 *val = sc->sc_stats.ast_rx_crcerr; 2149 break; 2150 case WIFI_STAT_WEP_ERRORS: 2151 *val = sc->sc_stats.ast_rx_badcrypt; 2152 break; 2153 case WIFI_STAT_TX_FRAGS: 2154 case WIFI_STAT_MCAST_TX: 2155 case WIFI_STAT_RTS_SUCCESS: 2156 case WIFI_STAT_RTS_FAILURE: 2157 case WIFI_STAT_ACK_FAILURE: 2158 case WIFI_STAT_RX_FRAGS: 2159 case WIFI_STAT_MCAST_RX: 2160 case WIFI_STAT_RX_DUPS: 2161 ARN_UNLOCK(sc); 2162 return (ieee80211_stat(ic, stat, val)); 2163 default: 2164 ARN_UNLOCK(sc); 2165 return (ENOTSUP); 2166 } 2167 ARN_UNLOCK(sc); 2168 2169 return (0); 2170 } 2171 2172 int 2173 arn_m_start(void *arg) 2174 { 2175 struct arn_softc *sc = arg; 2176 int err = 0; 2177 2178 ARN_LOCK(sc); 2179 2180 /* 2181 * Stop anything previously setup. This is safe 2182 * whether this is the first time through or not. 2183 */ 2184 2185 arn_close(sc); 2186 2187 if ((err = arn_open(sc)) != 0) { 2188 ARN_UNLOCK(sc); 2189 return (err); 2190 } 2191 2192 /* H/W is reday now */ 2193 sc->sc_flags &= ~SC_OP_INVALID; 2194 2195 ARN_UNLOCK(sc); 2196 2197 return (0); 2198 } 2199 2200 static void 2201 arn_m_stop(void *arg) 2202 { 2203 struct arn_softc *sc = arg; 2204 2205 ARN_LOCK(sc); 2206 arn_close(sc); 2207 2208 /* disable HAL and put h/w to sleep */ 2209 (void) ath9k_hw_disable(sc->sc_ah); 2210 ath9k_hw_configpcipowersave(sc->sc_ah, 1); 2211 2212 /* XXX: hardware will not be ready in suspend state */ 2213 sc->sc_flags |= SC_OP_INVALID; 2214 ARN_UNLOCK(sc); 2215 } 2216 2217 static int 2218 arn_m_promisc(void *arg, boolean_t on) 2219 { 2220 struct arn_softc *sc = arg; 2221 struct ath_hal *ah = sc->sc_ah; 2222 uint32_t rfilt; 2223 2224 ARN_LOCK(sc); 2225 2226 rfilt = ath9k_hw_getrxfilter(ah); 2227 if (on) 2228 rfilt |= ATH9K_RX_FILTER_PROM; 2229 else 2230 rfilt &= ~ATH9K_RX_FILTER_PROM; 2231 sc->sc_promisc = on; 2232 ath9k_hw_setrxfilter(ah, rfilt); 2233 2234 ARN_UNLOCK(sc); 2235 2236 return (0); 2237 } 2238 2239 static int 2240 arn_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 2241 { 2242 struct arn_softc *sc = arg; 2243 struct ath_hal *ah = sc->sc_ah; 2244 uint32_t val, index, bit; 2245 uint8_t pos; 2246 uint32_t *mfilt = sc->sc_mcast_hash; 2247 2248 ARN_LOCK(sc); 2249 2250 /* calculate XOR of eight 6bit values */ 2251 val = ARN_LE_READ_32(mca + 0); 2252 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2253 val = ARN_LE_READ_32(mca + 3); 2254 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 2255 pos &= 0x3f; 2256 index = pos / 32; 2257 bit = 1 << (pos % 32); 2258 2259 if (add) { /* enable multicast */ 2260 sc->sc_mcast_refs[pos]++; 2261 mfilt[index] |= bit; 2262 } else { /* disable multicast */ 2263 if (--sc->sc_mcast_refs[pos] == 0) 2264 mfilt[index] &= ~bit; 2265 } 2266 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); 2267 2268 ARN_UNLOCK(sc); 2269 return (0); 2270 } 2271 2272 static int 2273 arn_m_unicst(void *arg, const uint8_t *macaddr) 2274 { 2275 struct arn_softc *sc = arg; 2276 struct ath_hal *ah = sc->sc_ah; 2277 ieee80211com_t *ic = (ieee80211com_t *)sc; 2278 2279 ARN_DBG((ARN_DBG_XMIT, "ath: ath_gld_saddr(): " 2280 "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", 2281 macaddr[0], macaddr[1], macaddr[2], 2282 macaddr[3], macaddr[4], macaddr[5])); 2283 2284 ARN_LOCK(sc); 2285 IEEE80211_ADDR_COPY(sc->sc_isc.ic_macaddr, macaddr); 2286 (void) ath9k_hw_setmac(ah, sc->sc_isc.ic_macaddr); 2287 (void) arn_reset(ic); 2288 ARN_UNLOCK(sc); 2289 return (0); 2290 } 2291 2292 static mblk_t * 2293 arn_m_tx(void *arg, mblk_t *mp) 2294 { 2295 struct arn_softc *sc = arg; 2296 int error = 0; 2297 mblk_t *next; 2298 ieee80211com_t *ic = (ieee80211com_t *)sc; 2299 2300 /* 2301 * No data frames go out unless we're associated; this 2302 * should not happen as the 802.11 layer does not enable 2303 * the xmit queue until we enter the RUN state. 2304 */ 2305 if (ic->ic_state != IEEE80211_S_RUN) { 2306 ARN_DBG((ARN_DBG_XMIT, "arn: arn_m_tx(): " 2307 "discard, state %u\n", ic->ic_state)); 2308 sc->sc_stats.ast_tx_discard++; 2309 freemsgchain(mp); 2310 return (NULL); 2311 } 2312 2313 while (mp != NULL) { 2314 next = mp->b_next; 2315 mp->b_next = NULL; 2316 error = arn_tx(ic, mp, IEEE80211_FC0_TYPE_DATA); 2317 if (error != 0) { 2318 mp->b_next = next; 2319 if (error == ENOMEM) { 2320 break; 2321 } else { 2322 freemsgchain(mp); 2323 return (NULL); 2324 } 2325 } 2326 mp = next; 2327 } 2328 2329 return (mp); 2330 } 2331 2332 static void 2333 arn_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 2334 { 2335 struct arn_softc *sc = arg; 2336 int32_t err; 2337 2338 err = ieee80211_ioctl(&sc->sc_isc, wq, mp); 2339 2340 ARN_LOCK(sc); 2341 if (err == ENETRESET) { 2342 if (!(sc->sc_flags & SC_OP_INVALID)) { 2343 ARN_UNLOCK(sc); 2344 2345 (void) arn_m_start(sc); 2346 2347 (void) ieee80211_new_state(&sc->sc_isc, 2348 IEEE80211_S_SCAN, -1); 2349 ARN_LOCK(sc); 2350 } 2351 } 2352 ARN_UNLOCK(sc); 2353 } 2354 2355 static int 2356 arn_m_setprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num, 2357 uint_t wldp_length, const void *wldp_buf) 2358 { 2359 struct arn_softc *sc = arg; 2360 int err; 2361 2362 err = ieee80211_setprop(&sc->sc_isc, pr_name, wldp_pr_num, 2363 wldp_length, wldp_buf); 2364 2365 ARN_LOCK(sc); 2366 2367 if (err == ENETRESET) { 2368 if (!(sc->sc_flags & SC_OP_INVALID)) { 2369 ARN_UNLOCK(sc); 2370 (void) arn_m_start(sc); 2371 (void) ieee80211_new_state(&sc->sc_isc, 2372 IEEE80211_S_SCAN, -1); 2373 ARN_LOCK(sc); 2374 } 2375 err = 0; 2376 } 2377 2378 ARN_UNLOCK(sc); 2379 2380 return (err); 2381 } 2382 2383 /* ARGSUSED */ 2384 static int 2385 arn_m_getprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num, 2386 uint_t pr_flags, uint_t wldp_length, void *wldp_buf, uint_t *perm) 2387 { 2388 struct arn_softc *sc = arg; 2389 int err = 0; 2390 2391 err = ieee80211_getprop(&sc->sc_isc, pr_name, wldp_pr_num, 2392 pr_flags, wldp_length, wldp_buf, perm); 2393 2394 return (err); 2395 } 2396 2397 /* return bus cachesize in 4B word units */ 2398 static void 2399 arn_pci_config_cachesize(struct arn_softc *sc) 2400 { 2401 uint8_t csz; 2402 2403 /* 2404 * Cache line size is used to size and align various 2405 * structures used to communicate with the hardware. 2406 */ 2407 csz = pci_config_get8(sc->sc_cfg_handle, PCI_CONF_CACHE_LINESZ); 2408 if (csz == 0) { 2409 /* 2410 * We must have this setup properly for rx buffer 2411 * DMA to work so force a reasonable value here if it 2412 * comes up zero. 2413 */ 2414 csz = ATH_DEF_CACHE_BYTES / sizeof (uint32_t); 2415 pci_config_put8(sc->sc_cfg_handle, PCI_CONF_CACHE_LINESZ, 2416 csz); 2417 } 2418 sc->sc_cachelsz = csz << 2; 2419 } 2420 2421 static int 2422 arn_pci_setup(struct arn_softc *sc) 2423 { 2424 uint16_t command; 2425 2426 /* 2427 * Enable memory mapping and bus mastering 2428 */ 2429 ASSERT(sc != NULL); 2430 command = pci_config_get16(sc->sc_cfg_handle, PCI_CONF_COMM); 2431 command |= PCI_COMM_MAE | PCI_COMM_ME; 2432 pci_config_put16(sc->sc_cfg_handle, PCI_CONF_COMM, command); 2433 command = pci_config_get16(sc->sc_cfg_handle, PCI_CONF_COMM); 2434 if ((command & PCI_COMM_MAE) == 0) { 2435 arn_problem("arn: arn_pci_setup(): " 2436 "failed to enable memory mapping\n"); 2437 return (EIO); 2438 } 2439 if ((command & PCI_COMM_ME) == 0) { 2440 arn_problem("arn: arn_pci_setup(): " 2441 "failed to enable bus mastering\n"); 2442 return (EIO); 2443 } 2444 ARN_DBG((ARN_DBG_INIT, "arn: arn_pci_setup(): " 2445 "set command reg to 0x%x \n", command)); 2446 2447 return (0); 2448 } 2449 2450 static void 2451 arn_get_hw_encap(struct arn_softc *sc) 2452 { 2453 ieee80211com_t *ic; 2454 struct ath_hal *ah; 2455 2456 ic = (ieee80211com_t *)sc; 2457 ah = sc->sc_ah; 2458 2459 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, 2460 ATH9K_CIPHER_AES_CCM, NULL)) 2461 ic->ic_caps |= IEEE80211_C_AES_CCM; 2462 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, 2463 ATH9K_CIPHER_AES_OCB, NULL)) 2464 ic->ic_caps |= IEEE80211_C_AES; 2465 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, 2466 ATH9K_CIPHER_TKIP, NULL)) 2467 ic->ic_caps |= IEEE80211_C_TKIP; 2468 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, 2469 ATH9K_CIPHER_WEP, NULL)) 2470 ic->ic_caps |= IEEE80211_C_WEP; 2471 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, 2472 ATH9K_CIPHER_MIC, NULL)) 2473 ic->ic_caps |= IEEE80211_C_TKIPMIC; 2474 } 2475 2476 static int 2477 arn_resume(dev_info_t *devinfo) 2478 { 2479 struct arn_softc *sc; 2480 int ret = DDI_SUCCESS; 2481 2482 sc = ddi_get_soft_state(arn_soft_state_p, ddi_get_instance(devinfo)); 2483 if (sc == NULL) { 2484 ARN_DBG((ARN_DBG_INIT, "ath: ath_resume(): " 2485 "failed to get soft state\n")); 2486 return (DDI_FAILURE); 2487 } 2488 2489 ARN_LOCK(sc); 2490 /* 2491 * Set up config space command register(s). Refuse 2492 * to resume on failure. 2493 */ 2494 if (arn_pci_setup(sc) != 0) { 2495 ARN_DBG((ARN_DBG_INIT, "ath: ath_resume(): " 2496 "ath_pci_setup() failed\n")); 2497 ARN_UNLOCK(sc); 2498 return (DDI_FAILURE); 2499 } 2500 2501 if (!(sc->sc_flags & SC_OP_INVALID)) 2502 ret = arn_open(sc); 2503 ARN_UNLOCK(sc); 2504 2505 return (ret); 2506 } 2507 2508 static int 2509 arn_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 2510 { 2511 struct arn_softc *sc; 2512 int instance; 2513 int status; 2514 int32_t err; 2515 uint16_t vendor_id; 2516 uint16_t device_id; 2517 uint32_t i; 2518 uint32_t val; 2519 char strbuf[32]; 2520 ieee80211com_t *ic; 2521 struct ath_hal *ah; 2522 wifi_data_t wd = { 0 }; 2523 mac_register_t *macp; 2524 2525 switch (cmd) { 2526 case DDI_ATTACH: 2527 break; 2528 case DDI_RESUME: 2529 return (arn_resume(devinfo)); 2530 default: 2531 return (DDI_FAILURE); 2532 } 2533 2534 instance = ddi_get_instance(devinfo); 2535 if (ddi_soft_state_zalloc(arn_soft_state_p, instance) != DDI_SUCCESS) { 2536 ARN_DBG((ARN_DBG_ATTACH, "arn: " 2537 "%s: Unable to alloc softstate\n", __func__)); 2538 return (DDI_FAILURE); 2539 } 2540 2541 sc = ddi_get_soft_state(arn_soft_state_p, ddi_get_instance(devinfo)); 2542 ic = (ieee80211com_t *)sc; 2543 sc->sc_dev = devinfo; 2544 2545 mutex_init(&sc->sc_genlock, NULL, MUTEX_DRIVER, NULL); 2546 mutex_init(&sc->sc_serial_rw, NULL, MUTEX_DRIVER, NULL); 2547 mutex_init(&sc->sc_txbuflock, NULL, MUTEX_DRIVER, NULL); 2548 mutex_init(&sc->sc_rxbuflock, NULL, MUTEX_DRIVER, NULL); 2549 mutex_init(&sc->sc_resched_lock, NULL, MUTEX_DRIVER, NULL); 2550 #ifdef ARN_IBSS 2551 mutex_init(&sc->sc_bcbuflock, NULL, MUTEX_DRIVER, NULL); 2552 #endif 2553 2554 sc->sc_flags |= SC_OP_INVALID; 2555 2556 err = pci_config_setup(devinfo, &sc->sc_cfg_handle); 2557 if (err != DDI_SUCCESS) { 2558 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2559 "pci_config_setup() failed")); 2560 goto attach_fail0; 2561 } 2562 2563 if (arn_pci_setup(sc) != 0) 2564 goto attach_fail1; 2565 2566 /* Cache line size set up */ 2567 arn_pci_config_cachesize(sc); 2568 2569 vendor_id = pci_config_get16(sc->sc_cfg_handle, PCI_CONF_VENID); 2570 device_id = pci_config_get16(sc->sc_cfg_handle, PCI_CONF_DEVID); 2571 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): vendor 0x%x, " 2572 "device id 0x%x, cache size %d\n", 2573 vendor_id, device_id, 2574 pci_config_get8(sc->sc_cfg_handle, PCI_CONF_CACHE_LINESZ))); 2575 2576 pci_config_put8(sc->sc_cfg_handle, PCI_CONF_LATENCY_TIMER, 0xa8); 2577 val = pci_config_get32(sc->sc_cfg_handle, 0x40); 2578 if ((val & 0x0000ff00) != 0) 2579 pci_config_put32(sc->sc_cfg_handle, 0x40, val & 0xffff00ff); 2580 2581 err = ddi_regs_map_setup(devinfo, 1, 2582 &sc->mem, 0, 0, &arn_reg_accattr, &sc->sc_io_handle); 2583 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2584 "regs map1 = %x err=%d\n", sc->mem, err)); 2585 if (err != DDI_SUCCESS) { 2586 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2587 "ddi_regs_map_setup() failed")); 2588 goto attach_fail1; 2589 } 2590 2591 ah = ath9k_hw_attach(device_id, sc, sc->mem, &status); 2592 if (ah == NULL) { 2593 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2594 "unable to attach hw: H/W status %u\n", 2595 status)); 2596 goto attach_fail2; 2597 } 2598 sc->sc_ah = ah; 2599 2600 ath9k_hw_getmac(ah, ic->ic_macaddr); 2601 2602 /* Get the hardware key cache size. */ 2603 sc->sc_keymax = ah->ah_caps.keycache_size; 2604 if (sc->sc_keymax > ATH_KEYMAX) { 2605 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2606 "Warning, using only %u entries in %u key cache\n", 2607 ATH_KEYMAX, sc->sc_keymax)); 2608 sc->sc_keymax = ATH_KEYMAX; 2609 } 2610 2611 /* 2612 * Reset the key cache since some parts do not 2613 * reset the contents on initial power up. 2614 */ 2615 for (i = 0; i < sc->sc_keymax; i++) 2616 (void) ath9k_hw_keyreset(ah, (uint16_t)i); 2617 /* 2618 * Mark key cache slots associated with global keys 2619 * as in use. If we knew TKIP was not to be used we 2620 * could leave the +32, +64, and +32+64 slots free. 2621 * XXX only for splitmic. 2622 */ 2623 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2624 set_bit(i, sc->sc_keymap); 2625 set_bit(i + 32, sc->sc_keymap); 2626 set_bit(i + 64, sc->sc_keymap); 2627 set_bit(i + 32 + 64, sc->sc_keymap); 2628 } 2629 2630 /* Collect the channel list using the default country code */ 2631 err = arn_setup_channels(sc); 2632 if (err == EINVAL) { 2633 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2634 "ERR:arn_setup_channels\n")); 2635 goto attach_fail3; 2636 } 2637 2638 /* default to STA mode */ 2639 sc->sc_ah->ah_opmode = ATH9K_M_STA; 2640 2641 /* Setup rate tables */ 2642 arn_rate_attach(sc); 2643 arn_setup_rates(sc, IEEE80211_MODE_11A); 2644 arn_setup_rates(sc, IEEE80211_MODE_11B); 2645 arn_setup_rates(sc, IEEE80211_MODE_11G); 2646 2647 /* Setup current mode here */ 2648 arn_setcurmode(sc, ATH9K_MODE_11G); 2649 2650 /* 802.11g features */ 2651 if (sc->sc_have11g) 2652 ic->ic_caps |= IEEE80211_C_SHPREAMBLE | 2653 IEEE80211_C_SHSLOT; /* short slot time */ 2654 2655 /* temp workaround */ 2656 sc->sc_mrretry = 1; 2657 2658 /* Setup tx/rx descriptors */ 2659 err = arn_desc_alloc(devinfo, sc); 2660 if (err != DDI_SUCCESS) { 2661 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2662 "failed to allocate descriptors: %d\n", err)); 2663 goto attach_fail3; 2664 } 2665 2666 if ((sc->sc_tq = ddi_taskq_create(devinfo, "ath_taskq", 1, 2667 TASKQ_DEFAULTPRI, 0)) == NULL) { 2668 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2669 "ERR:ddi_taskq_create\n")); 2670 goto attach_fail4; 2671 } 2672 2673 /* 2674 * Allocate hardware transmit queues: one queue for 2675 * beacon frames and one data queue for each QoS 2676 * priority. Note that the hal handles reseting 2677 * these queues at the needed time. 2678 */ 2679 #ifdef ARN_IBSS 2680 sc->sc_beaconq = arn_beaconq_setup(ah); 2681 if (sc->sc_beaconq == (-1)) { 2682 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2683 "unable to setup a beacon xmit queue\n")); 2684 goto attach_fail4; 2685 } 2686 #endif 2687 #ifdef ARN_HOSTAP 2688 sc->sc_cabq = arn_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); 2689 if (sc->sc_cabq == NULL) { 2690 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2691 "unable to setup CAB xmit queue\n")); 2692 goto attach_fail4; 2693 } 2694 2695 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME; 2696 ath_cabq_update(sc); 2697 #endif 2698 2699 for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++) 2700 sc->sc_haltype2q[i] = -1; 2701 2702 /* Setup data queues */ 2703 /* NB: ensure BK queue is the lowest priority h/w queue */ 2704 if (!arn_tx_setup(sc, ATH9K_WME_AC_BK)) { 2705 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2706 "unable to setup xmit queue for BK traffic\n")); 2707 goto attach_fail4; 2708 } 2709 if (!arn_tx_setup(sc, ATH9K_WME_AC_BE)) { 2710 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2711 "unable to setup xmit queue for BE traffic\n")); 2712 goto attach_fail4; 2713 } 2714 if (!arn_tx_setup(sc, ATH9K_WME_AC_VI)) { 2715 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2716 "unable to setup xmit queue for VI traffic\n")); 2717 goto attach_fail4; 2718 } 2719 if (!arn_tx_setup(sc, ATH9K_WME_AC_VO)) { 2720 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2721 "unable to setup xmit queue for VO traffic\n")); 2722 goto attach_fail4; 2723 } 2724 2725 /* 2726 * Initializes the noise floor to a reasonable default value. 2727 * Later on this will be updated during ANI processing. 2728 */ 2729 2730 sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR; 2731 2732 2733 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, 2734 ATH9K_CIPHER_TKIP, NULL)) { 2735 /* 2736 * Whether we should enable h/w TKIP MIC. 2737 * XXX: if we don't support WME TKIP MIC, then we wouldn't 2738 * report WMM capable, so it's always safe to turn on 2739 * TKIP MIC in this case. 2740 */ 2741 (void) ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC, 2742 0, 1, NULL); 2743 } 2744 2745 /* Get cipher releated capability information */ 2746 arn_get_hw_encap(sc); 2747 2748 /* 2749 * Check whether the separate key cache entries 2750 * are required to handle both tx+rx MIC keys. 2751 * With split mic keys the number of stations is limited 2752 * to 27 otherwise 59. 2753 */ 2754 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, 2755 ATH9K_CIPHER_TKIP, NULL) && 2756 ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, 2757 ATH9K_CIPHER_MIC, NULL) && 2758 ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT, 2759 0, NULL)) 2760 sc->sc_splitmic = 1; 2761 2762 /* turn on mcast key search if possible */ 2763 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL)) 2764 (void) ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1, 2765 1, NULL); 2766 2767 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX; 2768 sc->sc_config.txpowlimit_override = 0; 2769 2770 #ifdef ARN_11N 2771 /* 11n Capabilities */ 2772 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) { 2773 sc->sc_flags |= SC_OP_TXAGGR; 2774 sc->sc_flags |= SC_OP_RXAGGR; 2775 } 2776 #endif 2777 2778 #ifdef ARN_11N 2779 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask; 2780 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask; 2781 #else 2782 sc->sc_tx_chainmask = 1; 2783 sc->sc_rx_chainmask = 1; 2784 #endif 2785 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2786 "tx_chainmask = %d, rx_chainmask = %d\n", 2787 sc->sc_tx_chainmask, sc->sc_rx_chainmask)); 2788 2789 (void) ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, B_TRUE, NULL); 2790 sc->sc_defant = ath9k_hw_getdefantenna(ah); 2791 2792 ath9k_hw_getmac(ah, sc->sc_myaddr); 2793 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) { 2794 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask); 2795 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask); 2796 (void) ath9k_hw_setbssidmask(ah, sc->sc_bssidmask); 2797 } 2798 2799 /* set default value to short slot time */ 2800 sc->sc_slottime = ATH9K_SLOT_TIME_9; 2801 (void) ath9k_hw_setslottime(ah, ATH9K_SLOT_TIME_9); 2802 2803 /* initialize beacon slots */ 2804 for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++) 2805 sc->sc_bslot[i] = ATH_IF_ID_ANY; 2806 2807 /* save MISC configurations */ 2808 sc->sc_config.swBeaconProcess = 1; 2809 2810 2811 ic->ic_caps |= IEEE80211_C_WPA; /* Support WPA/WPA2 */ 2812 ic->ic_phytype = IEEE80211_T_OFDM; 2813 ic->ic_opmode = IEEE80211_M_STA; 2814 ic->ic_state = IEEE80211_S_INIT; 2815 ic->ic_maxrssi = ARN_MAX_RSSI; 2816 ic->ic_set_shortslot = arn_set_shortslot; 2817 ic->ic_xmit = arn_tx; 2818 ieee80211_attach(ic); 2819 2820 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2821 "ic->ic_curchan->ich_freq: %d\n", ic->ic_curchan->ich_freq)); 2822 2823 /* different instance has different WPA door */ 2824 (void) snprintf(ic->ic_wpadoor, MAX_IEEE80211STR, "%s_%s%d", WPA_DOOR, 2825 ddi_driver_name(devinfo), 2826 ddi_get_instance(devinfo)); 2827 2828 /* Override 80211 default routines */ 2829 ic->ic_reset = arn_reset; 2830 sc->sc_newstate = ic->ic_newstate; 2831 ic->ic_newstate = arn_newstate; 2832 #ifdef ARN_IBSS 2833 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 2834 ic->ic_recv_mgmt = arn_recv_mgmt; 2835 #endif 2836 ic->ic_watchdog = arn_watchdog; 2837 ic->ic_node_alloc = arn_node_alloc; 2838 ic->ic_node_free = arn_node_free; 2839 ic->ic_crypto.cs_key_alloc = arn_key_alloc; 2840 ic->ic_crypto.cs_key_delete = arn_key_delete; 2841 ic->ic_crypto.cs_key_set = arn_key_set; 2842 2843 ieee80211_media_init(ic); 2844 2845 /* 2846 * initialize default tx key 2847 */ 2848 ic->ic_def_txkey = 0; 2849 2850 sc->sc_rx_pend = 0; 2851 (void) ath9k_hw_set_interrupts(sc->sc_ah, 0); 2852 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, 2853 &sc->sc_softint_id, NULL, 0, arn_softint_handler, (caddr_t)sc); 2854 if (err != DDI_SUCCESS) { 2855 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2856 "ddi_add_softintr() failed....\n")); 2857 goto attach_fail5; 2858 } 2859 2860 if (ddi_get_iblock_cookie(devinfo, 0, &sc->sc_iblock) 2861 != DDI_SUCCESS) { 2862 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2863 "Can not get iblock cookie for INT\n")); 2864 goto attach_fail6; 2865 } 2866 2867 if (ddi_add_intr(devinfo, 0, NULL, NULL, arn_isr, 2868 (caddr_t)sc) != DDI_SUCCESS) { 2869 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2870 "Can not set intr for ARN driver\n")); 2871 goto attach_fail6; 2872 } 2873 2874 /* 2875 * Provide initial settings for the WiFi plugin; whenever this 2876 * information changes, we need to call mac_plugindata_update() 2877 */ 2878 wd.wd_opmode = ic->ic_opmode; 2879 wd.wd_secalloc = WIFI_SEC_NONE; 2880 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid); 2881 2882 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2883 "IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid)" 2884 "%.2x:%.2x:%.2x:%.2x:%.2x:%.2x\n", 2885 wd.wd_bssid[0], wd.wd_bssid[1], wd.wd_bssid[2], 2886 wd.wd_bssid[3], wd.wd_bssid[4], wd.wd_bssid[5])); 2887 2888 if ((macp = mac_alloc(MAC_VERSION)) == NULL) { 2889 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2890 "MAC version mismatch\n")); 2891 goto attach_fail7; 2892 } 2893 2894 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI; 2895 macp->m_driver = sc; 2896 macp->m_dip = devinfo; 2897 macp->m_src_addr = ic->ic_macaddr; 2898 macp->m_callbacks = &arn_m_callbacks; 2899 macp->m_min_sdu = 0; 2900 macp->m_max_sdu = IEEE80211_MTU; 2901 macp->m_pdata = &wd; 2902 macp->m_pdata_size = sizeof (wd); 2903 2904 err = mac_register(macp, &ic->ic_mach); 2905 mac_free(macp); 2906 if (err != 0) { 2907 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2908 "mac_register err %x\n", err)); 2909 goto attach_fail7; 2910 } 2911 2912 /* Create minor node of type DDI_NT_NET_WIFI */ 2913 (void) snprintf(strbuf, sizeof (strbuf), "%s%d", 2914 ARN_NODENAME, instance); 2915 err = ddi_create_minor_node(devinfo, strbuf, S_IFCHR, 2916 instance + 1, DDI_NT_NET_WIFI, 0); 2917 if (err != DDI_SUCCESS) 2918 ARN_DBG((ARN_DBG_ATTACH, "WARN: arn: arn_attach(): " 2919 "Create minor node failed - %d\n", err)); 2920 2921 mac_link_update(ic->ic_mach, LINK_STATE_DOWN); 2922 2923 sc->sc_promisc = B_FALSE; 2924 bzero(sc->sc_mcast_refs, sizeof (sc->sc_mcast_refs)); 2925 bzero(sc->sc_mcast_hash, sizeof (sc->sc_mcast_hash)); 2926 2927 ARN_DBG((ARN_DBG_ATTACH, "arn: arn_attach(): " 2928 "Atheros AR%s MAC/BB Rev:%x " 2929 "AR%s RF Rev:%x: mem=0x%lx\n", 2930 arn_mac_bb_name(ah->ah_macVersion), 2931 ah->ah_macRev, 2932 arn_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)), 2933 ah->ah_phyRev, 2934 (unsigned long)sc->mem)); 2935 2936 /* XXX: hardware will not be ready until arn_open() being called */ 2937 sc->sc_flags |= SC_OP_INVALID; 2938 sc->sc_isrunning = 0; 2939 2940 return (DDI_SUCCESS); 2941 2942 attach_fail7: 2943 ddi_remove_intr(devinfo, 0, sc->sc_iblock); 2944 attach_fail6: 2945 ddi_remove_softintr(sc->sc_softint_id); 2946 attach_fail5: 2947 (void) ieee80211_detach(ic); 2948 attach_fail4: 2949 arn_desc_free(sc); 2950 if (sc->sc_tq) 2951 ddi_taskq_destroy(sc->sc_tq); 2952 attach_fail3: 2953 ath9k_hw_detach(ah); 2954 attach_fail2: 2955 ddi_regs_map_free(&sc->sc_io_handle); 2956 attach_fail1: 2957 pci_config_teardown(&sc->sc_cfg_handle); 2958 attach_fail0: 2959 sc->sc_flags |= SC_OP_INVALID; 2960 /* cleanup tx queues */ 2961 mutex_destroy(&sc->sc_txbuflock); 2962 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2963 if (ARN_TXQ_SETUP(sc, i)) { 2964 /* arn_tx_cleanupq(asc, &asc->sc_txq[i]); */ 2965 mutex_destroy(&((&sc->sc_txq[i])->axq_lock)); 2966 } 2967 } 2968 mutex_destroy(&sc->sc_rxbuflock); 2969 mutex_destroy(&sc->sc_serial_rw); 2970 mutex_destroy(&sc->sc_genlock); 2971 mutex_destroy(&sc->sc_resched_lock); 2972 #ifdef ARN_IBSS 2973 mutex_destroy(&sc->sc_bcbuflock); 2974 #endif 2975 2976 ddi_soft_state_free(arn_soft_state_p, instance); 2977 2978 return (DDI_FAILURE); 2979 2980 } 2981 2982 /* 2983 * Suspend transmit/receive for powerdown 2984 */ 2985 static int 2986 arn_suspend(struct arn_softc *sc) 2987 { 2988 ARN_LOCK(sc); 2989 arn_close(sc); 2990 ARN_UNLOCK(sc); 2991 2992 return (DDI_SUCCESS); 2993 } 2994 2995 static int32_t 2996 arn_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 2997 { 2998 struct arn_softc *sc; 2999 int i; 3000 3001 sc = ddi_get_soft_state(arn_soft_state_p, ddi_get_instance(devinfo)); 3002 ASSERT(sc != NULL); 3003 3004 switch (cmd) { 3005 case DDI_DETACH: 3006 break; 3007 3008 case DDI_SUSPEND: 3009 return (arn_suspend(sc)); 3010 3011 default: 3012 return (DDI_FAILURE); 3013 } 3014 3015 if (mac_disable(sc->sc_isc.ic_mach) != 0) 3016 return (DDI_FAILURE); 3017 3018 arn_stop_scantimer(sc); 3019 arn_stop_caltimer(sc); 3020 3021 /* disable interrupts */ 3022 (void) ath9k_hw_set_interrupts(sc->sc_ah, 0); 3023 3024 /* 3025 * Unregister from the MAC layer subsystem 3026 */ 3027 (void) mac_unregister(sc->sc_isc.ic_mach); 3028 3029 /* free intterrupt resources */ 3030 ddi_remove_intr(devinfo, 0, sc->sc_iblock); 3031 ddi_remove_softintr(sc->sc_softint_id); 3032 3033 /* 3034 * NB: the order of these is important: 3035 * o call the 802.11 layer before detaching the hal to 3036 * insure callbacks into the driver to delete global 3037 * key cache entries can be handled 3038 * o reclaim the tx queue data structures after calling 3039 * the 802.11 layer as we'll get called back to reclaim 3040 * node state and potentially want to use them 3041 * o to cleanup the tx queues the hal is called, so detach 3042 * it last 3043 */ 3044 ieee80211_detach(&sc->sc_isc); 3045 3046 arn_desc_free(sc); 3047 3048 ddi_taskq_destroy(sc->sc_tq); 3049 3050 if (!(sc->sc_flags & SC_OP_INVALID)) 3051 (void) ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 3052 3053 /* cleanup tx queues */ 3054 mutex_destroy(&sc->sc_txbuflock); 3055 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 3056 if (ARN_TXQ_SETUP(sc, i)) { 3057 arn_tx_cleanupq(sc, &sc->sc_txq[i]); 3058 mutex_destroy(&((&sc->sc_txq[i])->axq_lock)); 3059 } 3060 } 3061 3062 ath9k_hw_detach(sc->sc_ah); 3063 3064 /* free io handle */ 3065 ddi_regs_map_free(&sc->sc_io_handle); 3066 pci_config_teardown(&sc->sc_cfg_handle); 3067 3068 /* destroy locks */ 3069 mutex_destroy(&sc->sc_genlock); 3070 mutex_destroy(&sc->sc_serial_rw); 3071 mutex_destroy(&sc->sc_rxbuflock); 3072 mutex_destroy(&sc->sc_resched_lock); 3073 #ifdef ARN_IBSS 3074 mutex_destroy(&sc->sc_bcbuflock); 3075 #endif 3076 3077 ddi_remove_minor_node(devinfo, NULL); 3078 ddi_soft_state_free(arn_soft_state_p, ddi_get_instance(devinfo)); 3079 3080 return (DDI_SUCCESS); 3081 } 3082 3083 /* 3084 * quiesce(9E) entry point. 3085 * 3086 * This function is called when the system is single-threaded at high 3087 * PIL with preemption disabled. Therefore, this function must not be 3088 * blocked. 3089 * 3090 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 3091 * DDI_FAILURE indicates an error condition and should almost never happen. 3092 */ 3093 static int32_t 3094 arn_quiesce(dev_info_t *devinfo) 3095 { 3096 struct arn_softc *sc; 3097 int i; 3098 struct ath_hal *ah; 3099 3100 sc = ddi_get_soft_state(arn_soft_state_p, ddi_get_instance(devinfo)); 3101 3102 if (sc == NULL || (ah = sc->sc_ah) == NULL) 3103 return (DDI_FAILURE); 3104 3105 /* 3106 * Disable interrupts 3107 */ 3108 (void) ath9k_hw_set_interrupts(ah, 0); 3109 3110 /* 3111 * Disable TX HW 3112 */ 3113 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 3114 if (ARN_TXQ_SETUP(sc, i)) 3115 (void) ath9k_hw_stoptxdma(ah, sc->sc_txq[i].axq_qnum); 3116 } 3117 3118 /* 3119 * Disable RX HW 3120 */ 3121 ath9k_hw_stoppcurecv(ah); 3122 ath9k_hw_setrxfilter(ah, 0); 3123 (void) ath9k_hw_stopdmarecv(ah); 3124 drv_usecwait(3000); 3125 3126 /* 3127 * Power down HW 3128 */ 3129 (void) ath9k_hw_phy_disable(ah); 3130 3131 return (DDI_SUCCESS); 3132 } 3133 3134 DDI_DEFINE_STREAM_OPS(arn_dev_ops, nulldev, nulldev, arn_attach, arn_detach, 3135 nodev, NULL, D_MP, NULL, arn_quiesce); 3136 3137 static struct modldrv arn_modldrv = { 3138 &mod_driverops, /* Type of module. This one is a driver */ 3139 "arn-Atheros 9000 series driver:vertion 1.0", /* short description */ 3140 &arn_dev_ops /* driver specific ops */ 3141 }; 3142 3143 static struct modlinkage modlinkage = { 3144 MODREV_1, (void *)&arn_modldrv, NULL 3145 }; 3146 3147 int 3148 _info(struct modinfo *modinfop) 3149 { 3150 return (mod_info(&modlinkage, modinfop)); 3151 } 3152 3153 int 3154 _init(void) 3155 { 3156 int status; 3157 3158 status = ddi_soft_state_init 3159 (&arn_soft_state_p, sizeof (struct arn_softc), 1); 3160 if (status != 0) 3161 return (status); 3162 3163 mutex_init(&arn_loglock, NULL, MUTEX_DRIVER, NULL); 3164 mac_init_ops(&arn_dev_ops, "arn"); 3165 status = mod_install(&modlinkage); 3166 if (status != 0) { 3167 mac_fini_ops(&arn_dev_ops); 3168 mutex_destroy(&arn_loglock); 3169 ddi_soft_state_fini(&arn_soft_state_p); 3170 } 3171 3172 return (status); 3173 } 3174 3175 int 3176 _fini(void) 3177 { 3178 int status; 3179 3180 status = mod_remove(&modlinkage); 3181 if (status == 0) { 3182 mac_fini_ops(&arn_dev_ops); 3183 mutex_destroy(&arn_loglock); 3184 ddi_soft_state_fini(&arn_soft_state_p); 3185 } 3186 return (status); 3187 } 3188