1 /* rtl8139.c - etherboot driver for the Realtek 8139 chipset 2 3 ported from the linux driver written by Donald Becker 4 by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999 5 6 This software may be used and distributed according to the terms 7 of the GNU Public License, incorporated herein by reference. 8 9 changes to the original driver: 10 - removed support for interrupts, switching to polling mode (yuck!) 11 - removed support for the 8129 chip (external MII) 12 13 */ 14 15 /*********************************************************************/ 16 /* Revision History */ 17 /*********************************************************************/ 18 19 /* 20 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap) 21 Put in virt_to_bus calls to allow Etherboot relocation. 22 23 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap) 24 Following email from Hyun-Joon Cha, added a disable routine, otherwise 25 NIC remains live and can crash the kernel later. 26 27 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub) 28 Shuffled things around, removed the leftovers from the 8129 support 29 that was in the Linux driver and added a bit more 8139 definitions. 30 Moved the 8K receive buffer to a fixed, available address outside the 31 0x98000-0x9ffff range. This is a bit of a hack, but currently the only 32 way to make room for the Etherboot features that need substantial amounts 33 of code like the ANSI console support. Currently the buffer is just below 34 0x10000, so this even conforms to the tagged boot image specification, 35 which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My 36 interpretation of this "reserved" is that Etherboot may do whatever it 37 likes, as long as its environment is kept intact (like the BIOS 38 variables). Hopefully fixed rtl_poll() once and for all. The symptoms 39 were that if Etherboot was left at the boot menu for several minutes, the 40 first eth_poll failed. Seems like I am the only person who does this. 41 First of all I fixed the debugging code and then set out for a long bug 42 hunting session. It took me about a week full time work - poking around 43 various places in the driver, reading Don Becker's and Jeff Garzik's Linux 44 driver and even the FreeBSD driver (what a piece of crap!) - and 45 eventually spotted the nasty thing: the transmit routine was acknowledging 46 each and every interrupt pending, including the RxOverrun and RxFIFIOver 47 interrupts. This confused the RTL8139 thoroughly. It destroyed the 48 Rx ring contents by dumping the 2K FIFO contents right where we wanted to 49 get the next packet. Oh well, what fun. 50 51 18 Jan 2000 mdc@thinguin.org (Marty Connor) 52 Drastically simplified error handling. Basically, if any error 53 in transmission or reception occurs, the card is reset. 54 Also, pointed all transmit descriptors to the same buffer to 55 save buffer space. This should decrease driver size and avoid 56 corruption because of exceeding 32K during runtime. 57 58 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de) 59 rtl_poll was quite broken: it used the RxOK interrupt flag instead 60 of the RxBufferEmpty flag which often resulted in very bad 61 transmission performace - below 1kBytes/s. 62 63 */ 64 65 #include "etherboot.h" 66 #include "nic.h" 67 #include "pci.h" 68 #include "timer.h" 69 70 #define RTL_TIMEOUT (1*TICKS_PER_SEC) 71 72 /* PCI Tuning Parameters 73 Threshold is bytes transferred to chip before transmission starts. */ 74 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ 75 #define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */ 76 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */ 77 #define TX_DMA_BURST 4 /* Calculate as 16<<val. */ 78 #define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */ 79 #define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */ 80 #define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */ 81 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX) 82 83 #undef DEBUG_TX 84 #undef DEBUG_RX 85 86 /* Symbolic offsets to registers. */ 87 enum RTL8139_registers { 88 MAC0=0, /* Ethernet hardware address. */ 89 MAR0=8, /* Multicast filter. */ 90 TxStatus0=0x10, /* Transmit status (four 32bit registers). */ 91 TxAddr0=0x20, /* Tx descriptors (also four 32bit). */ 92 RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36, 93 ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A, 94 IntrMask=0x3C, IntrStatus=0x3E, 95 TxConfig=0x40, RxConfig=0x44, 96 Timer=0x48, /* general-purpose counter. */ 97 RxMissed=0x4C, /* 24 bits valid, write clears. */ 98 Cfg9346=0x50, Config0=0x51, Config1=0x52, 99 TimerIntrReg=0x54, /* intr if gp counter reaches this value */ 100 MediaStatus=0x58, 101 Config3=0x59, 102 MultiIntr=0x5C, 103 RevisionID=0x5E, /* revision of the RTL8139 chip */ 104 TxSummary=0x60, 105 MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68, 106 NWayExpansion=0x6A, 107 DisconnectCnt=0x6C, FalseCarrierCnt=0x6E, 108 NWayTestReg=0x70, 109 RxCnt=0x72, /* packet received counter */ 110 CSCR=0x74, /* chip status and configuration register */ 111 PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */ 112 /* from 0x84 onwards are a number of power management/wakeup frame 113 * definitions we will probably never need to know about. */ 114 }; 115 116 enum RxEarlyStatusBits { 117 ERGood=0x08, ERBad=0x04, EROVW=0x02, EROK=0x01 118 }; 119 120 enum ChipCmdBits { 121 CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, }; 122 123 enum IntrMaskBits { 124 SERR=0x8000, TimeOut=0x4000, LenChg=0x2000, 125 FOVW=0x40, PUN_LinkChg=0x20, RXOVW=0x10, 126 TER=0x08, TOK=0x04, RER=0x02, ROK=0x01 127 }; 128 129 /* Interrupt register bits, using my own meaningful names. */ 130 enum IntrStatusBits { 131 PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000, 132 RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10, 133 TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01, 134 }; 135 enum TxStatusBits { 136 TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000, 137 TxOutOfWindow=0x20000000, TxAborted=0x40000000, 138 TxCarrierLost=0x80000000, 139 }; 140 enum RxStatusBits { 141 RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000, 142 RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004, 143 RxBadAlign=0x0002, RxStatusOK=0x0001, 144 }; 145 146 enum MediaStatusBits { 147 MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08, 148 MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01, 149 }; 150 151 enum MIIBMCRBits { 152 BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000, 153 BMCRRestartNWay=0x0200, BMCRDuplex=0x0100, 154 }; 155 156 enum CSCRBits { 157 CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800, 158 CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0, 159 CSCR_LinkDownCmd=0x0f3c0, 160 }; 161 162 /* Bits in RxConfig. */ 163 enum rx_mode_bits { 164 RxCfgWrap=0x80, 165 AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08, 166 AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01, 167 }; 168 169 static unsigned int cur_rx,cur_tx; 170 171 /* The RTL8139 can only transmit from a contiguous, aligned memory block. */ 172 static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4))); 173 static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4))); 174 175 static int rtl8139_probe(struct dev *dev, struct pci_device *pci); 176 static int read_eeprom(struct nic *nic, int location, int addr_len); 177 static void rtl_reset(struct nic *nic); 178 static void rtl_transmit(struct nic *nic, const char *destaddr, 179 unsigned int type, unsigned int len, const char *data); 180 static int rtl_poll(struct nic *nic, int retrieve); 181 static void rtl_disable(struct dev *); 182 static void rtl_irq(struct nic *nic, irq_action_t action); 183 184 185 static int rtl8139_probe(struct dev *dev, struct pci_device *pci) 186 { 187 struct nic *nic = (struct nic *)dev; 188 int i; 189 int speed10, fullduplex; 190 int addr_len; 191 unsigned short *ap = (unsigned short*)nic->node_addr; 192 193 /* There are enough "RTL8139" strings on the console already, so 194 * be brief and concentrate on the interesting pieces of info... */ 195 printf(" - "); 196 197 /* Mask the bit that says "this is an io addr" */ 198 nic->ioaddr = pci->ioaddr & ~3; 199 200 /* Copy IRQ from PCI information */ 201 nic->irqno = pci->irq; 202 203 adjust_pci_device(pci); 204 205 /* Bring the chip out of low-power mode. */ 206 outb(0x00, nic->ioaddr + Config1); 207 208 addr_len = read_eeprom(nic,0,8) == 0x8129 ? 8 : 6; 209 for (i = 0; i < 3; i++) 210 *ap++ = read_eeprom(nic,i + 7,addr_len); 211 212 speed10 = inb(nic->ioaddr + MediaStatus) & MSRSpeed10; 213 fullduplex = inw(nic->ioaddr + MII_BMCR) & BMCRDuplex; 214 printf("ioaddr %#hX, irq %d, addr %! %sMbps %s-duplex\n", nic->ioaddr, 215 nic->irqno, nic->node_addr, speed10 ? "10" : "100", 216 fullduplex ? "full" : "half"); 217 218 rtl_reset(nic); 219 220 if (inb(nic->ioaddr + MediaStatus) & MSRLinkFail) { 221 printf("Cable not connected or other link failure\n"); 222 return(0); 223 } 224 225 dev->disable = rtl_disable; 226 nic->poll = rtl_poll; 227 nic->transmit = rtl_transmit; 228 nic->irq = rtl_irq; 229 230 return 1; 231 } 232 233 /* Serial EEPROM section. */ 234 235 /* EEPROM_Ctrl bits. */ 236 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ 237 #define EE_CS 0x08 /* EEPROM chip select. */ 238 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ 239 #define EE_WRITE_0 0x00 240 #define EE_WRITE_1 0x02 241 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */ 242 #define EE_ENB (0x80 | EE_CS) 243 244 /* 245 Delay between EEPROM clock transitions. 246 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. 247 */ 248 249 #define eeprom_delay() inl(ee_addr) 250 251 /* The EEPROM commands include the alway-set leading bit. */ 252 #define EE_WRITE_CMD (5) 253 #define EE_READ_CMD (6) 254 #define EE_ERASE_CMD (7) 255 256 static int read_eeprom(struct nic *nic, int location, int addr_len) 257 { 258 int i; 259 unsigned int retval = 0; 260 long ee_addr = nic->ioaddr + Cfg9346; 261 int read_cmd = location | (EE_READ_CMD << addr_len); 262 263 outb(EE_ENB & ~EE_CS, ee_addr); 264 outb(EE_ENB, ee_addr); 265 eeprom_delay(); 266 267 /* Shift the read command bits out. */ 268 for (i = 4 + addr_len; i >= 0; i--) { 269 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 270 outb(EE_ENB | dataval, ee_addr); 271 eeprom_delay(); 272 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); 273 eeprom_delay(); 274 } 275 outb(EE_ENB, ee_addr); 276 eeprom_delay(); 277 278 for (i = 16; i > 0; i--) { 279 outb(EE_ENB | EE_SHIFT_CLK, ee_addr); 280 eeprom_delay(); 281 retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0); 282 outb(EE_ENB, ee_addr); 283 eeprom_delay(); 284 } 285 286 /* Terminate the EEPROM access. */ 287 outb(~EE_CS, ee_addr); 288 eeprom_delay(); 289 return retval; 290 } 291 292 static const unsigned int rtl8139_rx_config = 293 (RX_BUF_LEN_IDX << 11) | 294 (RX_FIFO_THRESH << 13) | 295 (RX_DMA_BURST << 8); 296 297 static void set_rx_mode(struct nic *nic) { 298 unsigned int mc_filter[2]; 299 int rx_mode; 300 /* !IFF_PROMISC */ 301 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 302 mc_filter[1] = mc_filter[0] = 0xffffffff; 303 304 outl(rtl8139_rx_config | rx_mode, nic->ioaddr + RxConfig); 305 306 outl(mc_filter[0], nic->ioaddr + MAR0 + 0); 307 outl(mc_filter[1], nic->ioaddr + MAR0 + 4); 308 } 309 310 static void rtl_reset(struct nic* nic) 311 { 312 int i; 313 314 outb(CmdReset, nic->ioaddr + ChipCmd); 315 316 cur_rx = 0; 317 cur_tx = 0; 318 319 /* Give the chip 10ms to finish the reset. */ 320 load_timer2(10*TICKS_PER_MS); 321 while ((inb(nic->ioaddr + ChipCmd) & CmdReset) != 0 && 322 timer2_running()) 323 /* wait */; 324 325 for (i = 0; i < ETH_ALEN; i++) 326 outb(nic->node_addr[i], nic->ioaddr + MAC0 + i); 327 328 /* Must enable Tx/Rx before setting transfer thresholds! */ 329 outb(CmdRxEnb | CmdTxEnb, nic->ioaddr + ChipCmd); 330 outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8), 331 nic->ioaddr + RxConfig); /* accept no frames yet! */ 332 outl((TX_DMA_BURST<<8)|0x03000000, nic->ioaddr + TxConfig); 333 334 /* The Linux driver changes Config1 here to use a different LED pattern 335 * for half duplex or full/autodetect duplex (for full/autodetect, the 336 * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses 337 * TX/RX, Link100, Link10). This is messy, because it doesn't match 338 * the inscription on the mounting bracket. It should not be changed 339 * from the configuration EEPROM default, because the card manufacturer 340 * should have set that to match the card. */ 341 342 #ifdef DEBUG_RX 343 printf("rx ring address is %X\n",(unsigned long)rx_ring); 344 #endif 345 outl((unsigned long)virt_to_bus(rx_ring), nic->ioaddr + RxBuf); 346 347 348 349 /* If we add multicast support, the MAR0 register would have to be 350 * initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot 351 * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */ 352 353 outb(CmdRxEnb | CmdTxEnb, nic->ioaddr + ChipCmd); 354 355 outl(rtl8139_rx_config, nic->ioaddr + RxConfig); 356 357 /* Start the chip's Tx and Rx process. */ 358 outl(0, nic->ioaddr + RxMissed); 359 360 /* set_rx_mode */ 361 set_rx_mode(nic); 362 363 /* Disable all known interrupts by setting the interrupt mask. */ 364 outw(0, nic->ioaddr + IntrMask); 365 } 366 367 static void rtl_transmit(struct nic *nic, const char *destaddr, 368 unsigned int type, unsigned int len, const char *data) 369 { 370 unsigned int status, to, nstype; 371 unsigned long txstatus; 372 373 /* nstype assignment moved up here to avoid gcc 3.0.3 compiler bug */ 374 nstype = htons(type); 375 memcpy(tx_buffer, destaddr, ETH_ALEN); 376 memcpy(tx_buffer + ETH_ALEN, nic->node_addr, ETH_ALEN); 377 memcpy(tx_buffer + 2 * ETH_ALEN, &nstype, 2); 378 memcpy(tx_buffer + ETH_HLEN, data, len); 379 380 len += ETH_HLEN; 381 #ifdef DEBUG_TX 382 printf("sending %d bytes ethtype %hX\n", len, type); 383 #endif 384 385 /* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4 386 * bytes are sent automatically for the FCS, totalling to 64 bytes). */ 387 while (len < ETH_ZLEN) { 388 tx_buffer[len++] = '\0'; 389 } 390 391 outl((unsigned long)virt_to_bus(tx_buffer), nic->ioaddr + TxAddr0 + cur_tx*4); 392 outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len, 393 nic->ioaddr + TxStatus0 + cur_tx*4); 394 395 to = currticks() + RTL_TIMEOUT; 396 397 do { 398 status = inw(nic->ioaddr + IntrStatus); 399 /* Only acknlowledge interrupt sources we can properly handle 400 * here - the RxOverflow/RxFIFOOver MUST be handled in the 401 * rtl_poll() function. */ 402 outw(status & (TxOK | TxErr | PCIErr), nic->ioaddr + IntrStatus); 403 if ((status & (TxOK | TxErr | PCIErr)) != 0) break; 404 } while (currticks() < to); 405 406 txstatus = inl(nic->ioaddr+ TxStatus0 + cur_tx*4); 407 408 if (status & TxOK) { 409 cur_tx = (cur_tx + 1) % NUM_TX_DESC; 410 #ifdef DEBUG_TX 411 printf("tx done (%d ticks), status %hX txstatus %X\n", 412 to-currticks(), status, txstatus); 413 #endif 414 } else { 415 #ifdef DEBUG_TX 416 printf("tx timeout/error (%d ticks), status %hX txstatus %X\n", 417 currticks()-to, status, txstatus); 418 #endif 419 rtl_reset(nic); 420 } 421 } 422 423 static int rtl_poll(struct nic *nic, int retrieve) 424 { 425 unsigned int status; 426 unsigned int ring_offs; 427 unsigned int rx_size, rx_status; 428 429 if (inb(nic->ioaddr + ChipCmd) & RxBufEmpty) { 430 return 0; 431 } 432 433 /* There is a packet ready */ 434 if ( ! retrieve ) return 1; 435 436 status = inw(nic->ioaddr + IntrStatus); 437 /* See below for the rest of the interrupt acknowledges. */ 438 outw(status & ~(RxFIFOOver | RxOverflow | RxOK), nic->ioaddr + IntrStatus); 439 440 #ifdef DEBUG_RX 441 printf("rtl_poll: int %hX ", status); 442 #endif 443 444 ring_offs = cur_rx % RX_BUF_LEN; 445 rx_status = *(unsigned int*)(rx_ring + ring_offs); 446 rx_size = rx_status >> 16; 447 rx_status &= 0xffff; 448 449 if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) || 450 (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) { 451 printf("rx error %hX\n", rx_status); 452 rtl_reset(nic); /* this clears all interrupts still pending */ 453 return 0; 454 } 455 456 /* Received a good packet */ 457 nic->packetlen = rx_size - 4; /* no one cares about the FCS */ 458 if (ring_offs+4+rx_size-4 > RX_BUF_LEN) { 459 int semi_count = RX_BUF_LEN - ring_offs - 4; 460 461 memcpy(nic->packet, rx_ring + ring_offs + 4, semi_count); 462 memcpy(nic->packet+semi_count, rx_ring, rx_size-4-semi_count); 463 #ifdef DEBUG_RX 464 printf("rx packet %d+%d bytes", semi_count,rx_size-4-semi_count); 465 #endif 466 } else { 467 memcpy(nic->packet, rx_ring + ring_offs + 4, nic->packetlen); 468 #ifdef DEBUG_RX 469 printf("rx packet %d bytes", rx_size-4); 470 #endif 471 } 472 #ifdef DEBUG_RX 473 printf(" at %X type %hhX%hhX rxstatus %hX\n", 474 (unsigned long)(rx_ring+ring_offs+4), 475 nic->packet[12], nic->packet[13], rx_status); 476 #endif 477 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3; 478 outw(cur_rx - 16, nic->ioaddr + RxBufPtr); 479 /* See RTL8139 Programming Guide V0.1 for the official handling of 480 * Rx overflow situations. The document itself contains basically no 481 * usable information, except for a few exception handling rules. */ 482 outw(status & (RxFIFOOver | RxOverflow | RxOK), nic->ioaddr + IntrStatus); 483 return 1; 484 } 485 486 static void rtl_irq(struct nic *nic, irq_action_t action) 487 { 488 unsigned int mask; 489 /* Bit of a guess as to which interrupts we should allow */ 490 unsigned int interested = ROK | RER | RXOVW | FOVW | SERR; 491 492 switch ( action ) { 493 case DISABLE : 494 case ENABLE : 495 mask = inw(nic->ioaddr + IntrMask); 496 mask = mask & ~interested; 497 if ( action == ENABLE ) mask = mask | interested; 498 outw(mask, nic->ioaddr + IntrMask); 499 break; 500 case FORCE : 501 /* Apparently writing a 1 to this read-only bit of a 502 * read-only and otherwise unrelated register will 503 * force an interrupt. If you ever want to see how 504 * not to write a datasheet, read the one for the 505 * RTL8139... 506 */ 507 outb(EROK, nic->ioaddr + RxEarlyStatus); 508 break; 509 } 510 } 511 512 static void rtl_disable(struct dev *dev) 513 { 514 struct nic *nic = (struct nic *)dev; 515 /* merge reset and disable */ 516 rtl_reset(nic); 517 518 /* reset the chip */ 519 outb(CmdReset, nic->ioaddr + ChipCmd); 520 521 /* 10 ms timeout */ 522 load_timer2(10*TICKS_PER_MS); 523 while ((inb(nic->ioaddr + ChipCmd) & CmdReset) != 0 && timer2_running()) 524 /* wait */; 525 } 526 527 static struct pci_id rtl8139_nics[] = { 528 PCI_ROM(0x10ec, 0x8129, "rtl8129", "Realtek 8129"), 529 PCI_ROM(0x10ec, 0x8139, "rtl8139", "Realtek 8139"), 530 PCI_ROM(0x10ec, 0x8138, "rtl8139b", "Realtek 8139B"), 531 PCI_ROM(0x1186, 0x1300, "dfe538", "DFE530TX+/DFE538TX"), 532 PCI_ROM(0x1113, 0x1211, "smc1211-1", "SMC EZ10/100"), 533 PCI_ROM(0x1112, 0x1211, "smc1211", "SMC EZ10/100"), 534 PCI_ROM(0x1500, 0x1360, "delta8139", "Delta Electronics 8139"), 535 PCI_ROM(0x4033, 0x1360, "addtron8139", "Addtron Technology 8139"), 536 PCI_ROM(0x1186, 0x1340, "dfe690txd", "D-Link DFE690TXD"), 537 PCI_ROM(0x13d1, 0xab06, "fe2000vx", "AboCom FE2000VX"), 538 PCI_ROM(0x1259, 0xa117, "allied8139", "Allied Telesyn 8139"), 539 PCI_ROM(0x14ea, 0xab06, "fnw3603tx", "Planex FNW-3603-TX"), 540 PCI_ROM(0x14ea, 0xab07, "fnw3800tx", "Planex FNW-3800-TX"), 541 PCI_ROM(0xffff, 0x8139, "clone-rtl8139", "Cloned 8139"), 542 }; 543 544 struct pci_driver rtl8139_driver = { 545 .type = NIC_DRIVER, 546 .name = "RTL8139", 547 .probe = rtl8139_probe, 548 .ids = rtl8139_nics, 549 .id_count = sizeof(rtl8139_nics)/sizeof(rtl8139_nics[0]), 550 .class = 0, 551 }; 552