1 #if !defined(PCI_H) && defined(CONFIG_PCI) 2 #define PCI_H 3 4 /* 5 ** Support for NE2000 PCI clones added David Monro June 1997 6 ** Generalised for other PCI NICs by Ken Yap July 1997 7 ** 8 ** Most of this is taken from: 9 ** 10 ** /usr/src/linux/drivers/pci/pci.c 11 ** /usr/src/linux/include/linux/pci.h 12 ** /usr/src/linux/arch/i386/bios32.c 13 ** /usr/src/linux/include/linux/bios32.h 14 ** /usr/src/linux/drivers/net/ne.c 15 */ 16 17 /* 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License as 20 * published by the Free Software Foundation; either version 2, or (at 21 * your option) any later version. 22 */ 23 24 #include "pci_ids.h" 25 26 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 27 #define PCI_COMMAND_MEM 0x2 /* Enable response in mem space */ 28 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 29 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 30 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 31 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 32 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 33 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 34 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 35 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 36 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 37 38 #define PCIBIOS_PCI_FUNCTION_ID 0xb1XX 39 #define PCIBIOS_PCI_BIOS_PRESENT 0xb101 40 #define PCIBIOS_FIND_PCI_DEVICE 0xb102 41 #define PCIBIOS_FIND_PCI_CLASS_CODE 0xb103 42 #define PCIBIOS_GENERATE_SPECIAL_CYCLE 0xb106 43 #define PCIBIOS_READ_CONFIG_BYTE 0xb108 44 #define PCIBIOS_READ_CONFIG_WORD 0xb109 45 #define PCIBIOS_READ_CONFIG_DWORD 0xb10a 46 #define PCIBIOS_WRITE_CONFIG_BYTE 0xb10b 47 #define PCIBIOS_WRITE_CONFIG_WORD 0xb10c 48 #define PCIBIOS_WRITE_CONFIG_DWORD 0xb10d 49 50 #define PCI_VENDOR_ID 0x00 /* 16 bits */ 51 #define PCI_DEVICE_ID 0x02 /* 16 bits */ 52 #define PCI_COMMAND 0x04 /* 16 bits */ 53 54 #define PCI_STATUS 0x06 /* 16 bits */ 55 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 56 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ 57 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 58 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 59 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 60 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 61 #define PCI_STATUS_DEVSEL_FAST 0x000 62 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 63 #define PCI_STATUS_DEVSEL_SLOW 0x400 64 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 65 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 66 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 67 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 68 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 69 70 #define PCI_REVISION 0x08 /* 8 bits */ 71 #define PCI_REVISION_ID 0x08 /* 8 bits */ 72 #define PCI_CLASS_REVISION 0x08 /* 32 bits */ 73 #define PCI_CLASS_CODE 0x0b /* 8 bits */ 74 #define PCI_SUBCLASS_CODE 0x0a /* 8 bits */ 75 #define PCI_HEADER_TYPE 0x0e /* 8 bits */ 76 #define PCI_HEADER_TYPE_NORMAL 0 77 #define PCI_HEADER_TYPE_BRIDGE 1 78 #define PCI_HEADER_TYPE_CARDBUS 2 79 80 81 /* Header type 0 (normal devices) */ 82 #define PCI_CARDBUS_CIS 0x28 83 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 84 #define PCI_SUBSYSTEM_ID 0x2e 85 86 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 87 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits */ 88 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits */ 89 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 90 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 91 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 92 93 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 94 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 95 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 96 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 97 98 #ifndef PCI_BASE_ADDRESS_IO_MASK 99 #define PCI_BASE_ADDRESS_IO_MASK (~0x03) 100 #endif 101 #ifndef PCI_BASE_ADDRESS_MEM_MASK 102 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0f) 103 #endif 104 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 105 #define PCI_ROM_ADDRESS 0x30 /* 32 bits */ 106 #define PCI_ROM_ADDRESS_ENABLE 0x01 /* Write 1 to enable ROM, 107 bits 31..11 are address, 108 10..2 are reserved */ 109 110 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 111 112 #define PCI_INTERRUPT_LINE 0x3c /* IRQ number (0-15) */ 113 #define PCI_INTERRUPT_PIN 0x3d /* IRQ pin on PCI bus (A-D) */ 114 115 /* Header type 1 (PCI-to-PCI bridges) */ 116 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 117 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 118 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 119 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 120 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 121 #define PCI_IO_LIMIT 0x1d 122 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ 123 #define PCI_IO_RANGE_TYPE_16 0x00 124 #define PCI_IO_RANGE_TYPE_32 0x01 125 #define PCI_IO_RANGE_MASK ~0x0f 126 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 127 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 128 #define PCI_MEMORY_LIMIT 0x22 129 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f 130 #define PCI_MEMORY_RANGE_MASK ~0x0f 131 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 132 #define PCI_PREF_MEMORY_LIMIT 0x26 133 #define PCI_PREF_RANGE_TYPE_MASK 0x0f 134 #define PCI_PREF_RANGE_TYPE_32 0x00 135 #define PCI_PREF_RANGE_TYPE_64 0x01 136 #define PCI_PREF_RANGE_MASK ~0x0f 137 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 138 #define PCI_PREF_LIMIT_UPPER32 0x2c 139 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 140 #define PCI_IO_LIMIT_UPPER16 0x32 141 /* 0x34 same as for htype 0 */ 142 /* 0x35-0x3b is reserved */ 143 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 144 /* 0x3c-0x3d are same as for htype 0 */ 145 #define PCI_BRIDGE_CONTROL 0x3e 146 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 147 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 148 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 149 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 150 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 151 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 152 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 153 154 #define PCI_CB_CAPABILITY_LIST 0x14 155 156 /* Capability lists */ 157 158 #define PCI_CAP_LIST_ID 0 /* Capability ID */ 159 #define PCI_CAP_ID_PM 0x01 /* Power Management */ 160 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 161 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 162 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 163 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 164 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 165 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 166 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 167 #define PCI_CAP_SIZEOF 4 168 169 /* Power Management Registers */ 170 171 #define PCI_PM_PMC 2 /* PM Capabilities Register */ 172 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 173 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 174 #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ 175 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 176 #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */ 177 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 178 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 179 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 180 #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */ 181 #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */ 182 #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */ 183 #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ 184 #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */ 185 #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ 186 #define PCI_PM_CTRL 4 /* PM control and status register */ 187 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 188 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 189 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 190 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 191 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 192 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 193 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 194 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 195 #define PCI_PM_DATA_REGISTER 7 /* (??) */ 196 #define PCI_PM_SIZEOF 8 197 198 /* AGP registers */ 199 200 #define PCI_AGP_VERSION 2 /* BCD version number */ 201 #define PCI_AGP_RFU 3 /* Rest of capability flags */ 202 #define PCI_AGP_STATUS 4 /* Status register */ 203 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 204 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 205 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 206 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 207 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 208 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 209 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 210 #define PCI_AGP_COMMAND 8 /* Control register */ 211 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 212 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 213 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 214 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 215 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 216 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 217 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ 218 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ 219 #define PCI_AGP_SIZEOF 12 220 221 /* Slot Identification */ 222 223 #define PCI_SID_ESR 2 /* Expansion Slot Register */ 224 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 225 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 226 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 227 228 /* Message Signalled Interrupts registers */ 229 230 #define PCI_MSI_FLAGS 2 /* Various flags */ 231 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ 232 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ 233 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ 234 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ 235 #define PCI_MSI_RFU 3 /* Rest of capability flags */ 236 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 237 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 238 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 239 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 240 241 #define PCI_SLOT(devfn) ((devfn) >> 3) 242 #define PCI_FUNC(devfn) ((devfn) & 0x07) 243 244 #define BIOS32_SIGNATURE (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24)) 245 246 /* PCI signature: "PCI " */ 247 #define PCI_SIGNATURE (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24)) 248 249 /* PCI service signature: "$PCI" */ 250 #define PCI_SERVICE (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24)) 251 252 union bios32 { 253 struct { 254 unsigned long signature; /* _32_ */ 255 unsigned long entry; /* 32 bit physical address */ 256 unsigned char revision; /* Revision level, 0 */ 257 unsigned char length; /* Length in paragraphs should be 01 */ 258 unsigned char checksum; /* All bytes must add up to zero */ 259 unsigned char reserved[5]; /* Must be zero */ 260 } fields; 261 char chars[16]; 262 }; 263 264 struct pci_device; 265 struct dev; 266 typedef int (*pci_probe_t)(struct dev *, struct pci_device *); 267 268 struct pci_device { 269 uint32_t class; 270 uint16_t vendor, dev_id; 271 const char *name; 272 /* membase and ioaddr are silly and depricated */ 273 unsigned int membase; 274 unsigned int ioaddr; 275 unsigned int romaddr; 276 unsigned char irq; 277 unsigned char devfn; 278 unsigned char bus; 279 unsigned char use_specified; 280 const struct pci_driver *driver; 281 }; 282 283 extern void scan_pci_bus(int type, struct pci_device *dev); 284 extern void find_pci(int type, struct pci_device *dev); 285 286 extern int pcibios_read_config_byte(unsigned int bus, unsigned int device_fn, unsigned int where, uint8_t *value); 287 extern int pcibios_write_config_byte (unsigned int bus, unsigned int device_fn, unsigned int where, uint8_t value); 288 extern int pcibios_read_config_word(unsigned int bus, unsigned int device_fn, unsigned int where, uint16_t *value); 289 extern int pcibios_write_config_word (unsigned int bus, unsigned int device_fn, unsigned int where, uint16_t value); 290 extern int pcibios_read_config_dword(unsigned int bus, unsigned int device_fn, unsigned int where, uint32_t *value); 291 extern int pcibios_write_config_dword(unsigned int bus, unsigned int device_fn, unsigned int where, uint32_t value); 292 extern unsigned long pcibios_bus_base(unsigned int bus); 293 extern void adjust_pci_device(struct pci_device *p); 294 295 296 static inline int 297 pci_read_config_byte(struct pci_device *dev, unsigned int where, uint8_t *value) 298 { 299 return pcibios_read_config_byte(dev->bus, dev->devfn, where, value); 300 } 301 static inline int 302 pci_write_config_byte(struct pci_device *dev, unsigned int where, uint8_t value) 303 { 304 return pcibios_write_config_byte(dev->bus, dev->devfn, where, value); 305 } 306 static inline int 307 pci_read_config_word(struct pci_device *dev, unsigned int where, uint16_t *value) 308 { 309 return pcibios_read_config_word(dev->bus, dev->devfn, where, value); 310 } 311 static inline int 312 pci_write_config_word(struct pci_device *dev, unsigned int where, uint16_t value) 313 { 314 return pcibios_write_config_word(dev->bus, dev->devfn, where, value); 315 } 316 static inline int 317 pci_read_config_dword(struct pci_device *dev, unsigned int where, uint32_t *value) 318 { 319 return pcibios_read_config_dword(dev->bus, dev->devfn, where, value); 320 } 321 static inline int 322 pci_write_config_dword(struct pci_device *dev, unsigned int where, uint32_t value) 323 { 324 return pcibios_write_config_dword(dev->bus, dev->devfn, where, value); 325 } 326 327 /* Helper functions to find the size of a pci bar */ 328 extern unsigned long pci_bar_start(struct pci_device *dev, unsigned int bar); 329 extern unsigned long pci_bar_size(struct pci_device *dev, unsigned int bar); 330 /* Helper function to find pci capabilities */ 331 extern int pci_find_capability(struct pci_device *dev, int cap); 332 struct pci_id { 333 unsigned short vendor, dev_id; 334 const char *name; 335 }; 336 337 struct dev; 338 /* Most pci drivers will use this */ 339 struct pci_driver { 340 int type; 341 const char *name; 342 pci_probe_t probe; 343 struct pci_id *ids; 344 int id_count; 345 346 /* On a few occasions the hardware is standardized enough that 347 * we only need to know the class of the device and not the exact 348 * type to drive the device correctly. If this is the case 349 * set a class value other than 0. 350 */ 351 unsigned short class; 352 }; 353 354 #define PCI_ROM(VENDOR_ID, DEVICE_ID, IMAGE, DESCRIPTION) \ 355 { VENDOR_ID, DEVICE_ID, IMAGE, } 356 357 #endif /* PCI_H */ 358