1 /* 2 * 3 * CDDL HEADER START 4 * 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright (c) 2011, Joyent, Inc. All rights reserved. 25 */ 26 27 /* 28 * Copyright (c) 2010, Intel Corporation. 29 * All rights reserved. 30 */ 31 32 /* Copyright (c) 1988 AT&T */ 33 /* All Rights Reserved */ 34 35 36 #include "dis_tables.h" 37 38 /* BEGIN CSTYLED */ 39 40 /* 41 * Disassembly begins in dis_distable, which is equivalent to the One-byte 42 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The 43 * decoding loops then traverse out through the other tables as necessary to 44 * decode a given instruction. 45 * 46 * The behavior of this file can be controlled by one of the following flags: 47 * 48 * DIS_TEXT Include text for disassembly 49 * DIS_MEM Include memory-size calculations 50 * 51 * Either or both of these can be defined. 52 * 53 * This file is not, and will never be, cstyled. If anything, the tables should 54 * be taken out another tab stop or two so nothing overlaps. 55 */ 56 57 /* 58 * These functions must be provided for the consumer to do disassembly. 59 */ 60 #ifdef DIS_TEXT 61 extern char *strncpy(char *, const char *, size_t); 62 extern size_t strlen(const char *); 63 extern int strcmp(const char *, const char *); 64 extern int strncmp(const char *, const char *, size_t); 65 extern size_t strlcat(char *, const char *, size_t); 66 #endif 67 68 69 #define TERM 0 /* used to indicate that the 'indirect' */ 70 /* field terminates - no pointer. */ 71 72 /* Used to decode instructions. */ 73 typedef struct instable { 74 struct instable *it_indirect; /* for decode op codes */ 75 uchar_t it_adrmode; 76 #ifdef DIS_TEXT 77 char it_name[NCPS]; 78 uint_t it_suffix:1; /* mnem + "w", "l", or "d" */ 79 #endif 80 #ifdef DIS_MEM 81 uint_t it_size:16; 82 #endif 83 uint_t it_invalid64:1; /* opcode invalid in amd64 */ 84 uint_t it_always64:1; /* 64 bit when in 64 bit mode */ 85 uint_t it_invalid32:1; /* invalid in IA32 */ 86 uint_t it_stackop:1; /* push/pop stack operation */ 87 } instable_t; 88 89 /* 90 * Instruction formats. 91 */ 92 enum { 93 UNKNOWN, 94 MRw, 95 IMlw, 96 IMw, 97 IR, 98 OA, 99 AO, 100 MS, 101 SM, 102 Mv, 103 Mw, 104 M, /* register or memory */ 105 MG9, /* register or memory in group 9 (prefix optional) */ 106 Mb, /* register or memory, always byte sized */ 107 MO, /* memory only (no registers) */ 108 PREF, 109 SWAPGS, 110 MONITOR_MWAIT, 111 R, 112 RA, 113 SEG, 114 MR, 115 RM, 116 RM_66r, /* RM, but with a required 0x66 prefix */ 117 IA, 118 MA, 119 SD, 120 AD, 121 SA, 122 D, 123 INM, 124 SO, 125 BD, 126 I, 127 P, 128 V, 129 DSHIFT, /* for double shift that has an 8-bit immediate */ 130 U, 131 OVERRIDE, 132 NORM, /* instructions w/o ModR/M byte, no memory access */ 133 IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */ 134 O, /* for call */ 135 JTAB, /* jump table */ 136 IMUL, /* for 186 iimul instr */ 137 CBW, /* so data16 can be evaluated for cbw and variants */ 138 MvI, /* for 186 logicals */ 139 ENTER, /* for 186 enter instr */ 140 RMw, /* for 286 arpl instr */ 141 Ib, /* for push immediate byte */ 142 F, /* for 287 instructions */ 143 FF, /* for 287 instructions */ 144 FFC, /* for 287 instructions */ 145 DM, /* 16-bit data */ 146 AM, /* 16-bit addr */ 147 LSEG, /* for 3-bit seg reg encoding */ 148 MIb, /* for 386 logicals */ 149 SREG, /* for 386 special registers */ 150 PREFIX, /* a REP instruction prefix */ 151 LOCK, /* a LOCK instruction prefix */ 152 INT3, /* The int 3 instruction, which has a fake operand */ 153 INTx, /* The normal int instruction, with explicit int num */ 154 DSHIFTcl, /* for double shift that implicitly uses %cl */ 155 CWD, /* so data16 can be evaluated for cwd and variants */ 156 RET, /* single immediate 16-bit operand */ 157 MOVZ, /* for movs and movz, with different size operands */ 158 CRC32, /* for crc32, with different size operands */ 159 XADDB, /* for xaddb */ 160 MOVSXZ, /* AMD64 mov sign extend 32 to 64 bit instruction */ 161 MOVBE, /* movbe instruction */ 162 163 /* 164 * MMX/SIMD addressing modes. 165 */ 166 167 MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */ 168 MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */ 169 MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */ 170 MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */ 171 MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */ 172 MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */ 173 MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */ 174 MMOPM_66o, /* MMX/SIMD-Int 0x66 optional mm/mem -> mm,imm8 */ 175 MMOPRM, /* Prefixable MMX/SIMD-Int r32/mem -> mm,imm8 */ 176 MMOSH, /* Prefixable MMX mm,imm8 */ 177 MM, /* MMX/SIMD-Int mm/mem -> mm */ 178 MMS, /* MMX/SIMD-Int mm -> mm/mem */ 179 MMSH, /* MMX mm,imm8 */ 180 XMMO, /* Prefixable SIMD xmm/mem -> xmm */ 181 XMMOS, /* Prefixable SIMD xmm -> xmm/mem */ 182 XMMOPM, /* Prefixable SIMD xmm/mem w/to xmm,imm8 */ 183 XMMOMX, /* Prefixable SIMD mm/mem -> xmm */ 184 XMMOX3, /* Prefixable SIMD xmm -> r32 */ 185 XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */ 186 XMMOM, /* Prefixable SIMD xmm -> mem */ 187 XMMOMS, /* Prefixable SIMD mem -> xmm */ 188 XMM, /* SIMD xmm/mem -> xmm */ 189 XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */ 190 XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */ 191 XMMXIMPL, /* SIMD xmm -> xmm (mem) */ 192 XMM3P, /* SIMD xmm -> r32,imm8 */ 193 XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8 */ 194 XMMP, /* SIMD xmm/mem w/to xmm,imm8 */ 195 XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */ 196 XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */ 197 XMMPRM, /* SIMD r32/mem -> xmm,imm8 */ 198 XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */ 199 XMMS, /* SIMD xmm -> xmm/mem */ 200 XMMM, /* SIMD mem -> xmm */ 201 XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */ 202 XMMMS, /* SIMD xmm -> mem */ 203 XMM3MX, /* SIMD r32/mem -> xmm */ 204 XMM3MXS, /* SIMD xmm -> r32/mem */ 205 XMMSH, /* SIMD xmm,imm8 */ 206 XMMXM3, /* SIMD xmm/mem -> r32 */ 207 XMMX3, /* SIMD xmm -> r32 */ 208 XMMXMM, /* SIMD xmm/mem -> mm */ 209 XMMMX, /* SIMD mm -> xmm */ 210 XMMXM, /* SIMD xmm -> mm */ 211 XMMX2I, /* SIMD xmm -> xmm, imm, imm */ 212 XMM2I, /* SIMD xmm, imm, imm */ 213 XMMFENCE, /* SIMD lfence or mfence */ 214 XMMSFNC, /* SIMD sfence (none or mem) */ 215 XGETBV_XSETBV, 216 VEX_NONE, /* VEX no operand */ 217 VEX_MO, /* VEX mod_rm -> implicit reg */ 218 VEX_RMrX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 219 VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 220 VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */ 221 VEX_MX, /* VEX mod_rm -> mod_reg */ 222 VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */ 223 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */ 224 VEX_MR, /* VEX mod_rm -> mod_reg */ 225 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */ 226 VEX_RX, /* VEX mod_reg -> mod_rm */ 227 VEX_RR, /* VEX mod_rm -> mod_reg */ 228 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */ 229 VEX_RM, /* VEX mod_reg -> mod_rm */ 230 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 231 VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 232 VMx, /* vmcall/vmlaunch/vmresume/vmxoff */ 233 VMxo, /* VMx instruction with optional prefix */ 234 SVM /* AMD SVM instructions */ 235 }; 236 237 /* 238 * VEX prefixes 239 */ 240 #define VEX_2bytes 0xC5 /* the first byte of two-byte form */ 241 #define VEX_3bytes 0xC4 /* the first byte of three-byte form */ 242 243 #define FILL 0x90 /* Fill byte used for alignment (nop) */ 244 245 /* 246 ** Register numbers for the i386 247 */ 248 #define EAX_REGNO 0 249 #define ECX_REGNO 1 250 #define EDX_REGNO 2 251 #define EBX_REGNO 3 252 #define ESP_REGNO 4 253 #define EBP_REGNO 5 254 #define ESI_REGNO 6 255 #define EDI_REGNO 7 256 257 /* 258 * modes for immediate values 259 */ 260 #define MODE_NONE 0 261 #define MODE_IPREL 1 /* signed IP relative value */ 262 #define MODE_SIGNED 2 /* sign extended immediate */ 263 #define MODE_IMPLIED 3 /* constant value implied from opcode */ 264 #define MODE_OFFSET 4 /* offset part of an address */ 265 #define MODE_RIPREL 5 /* like IPREL, but from %rip (amd64) */ 266 267 /* 268 * The letters used in these macros are: 269 * IND - indirect to another to another table 270 * "T" - means to Terminate indirections (this is the final opcode) 271 * "S" - means "operand length suffix required" 272 * "NS" - means "no suffix" which is the operand length suffix of the opcode 273 * "Z" - means instruction size arg required 274 * "u" - means the opcode is invalid in IA32 but valid in amd64 275 * "x" - means the opcode is invalid in amd64, but not IA32 276 * "y" - means the operand size is always 64 bits in 64 bit mode 277 * "p" - means push/pop stack operation 278 */ 279 280 #if defined(DIS_TEXT) && defined(DIS_MEM) 281 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0} 282 #define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0} 283 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0} 284 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0} 285 #define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0} 286 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0} 287 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1} 288 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0} 289 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0} 290 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0} 291 #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0} 292 #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0} 293 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1} 294 #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0} 295 #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0} 296 #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0} 297 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 298 #elif defined(DIS_TEXT) 299 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0} 300 #define INDx(table) {(instable_t *)table, 0, "", 0, 1, 0, 0, 0} 301 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0} 302 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0} 303 #define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0} 304 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0} 305 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1} 306 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0} 307 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0} 308 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0} 309 #define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0} 310 #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0} 311 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1} 312 #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0} 313 #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0} 314 #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0} 315 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 316 #elif defined(DIS_MEM) 317 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0} 318 #define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0} 319 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 320 #define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0} 321 #define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 322 #define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1} 323 #define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 324 #define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 325 #define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 326 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 327 #define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 328 #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 329 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1} 330 #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 331 #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0} 332 #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 333 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0} 334 #else 335 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0} 336 #define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0} 337 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0} 338 #define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0} 339 #define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0} 340 #define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1} 341 #define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0} 342 #define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 343 #define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 344 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0} 345 #define TSx(name, amode) {TERM, amode, 1, 0, 0, 0} 346 #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0} 347 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1} 348 #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 349 #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0} 350 #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 351 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0} 352 #endif 353 354 #ifdef DIS_TEXT 355 /* 356 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode 357 */ 358 const char *const dis_addr16[3][8] = { 359 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "", 360 "(%bx)", 361 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)", 362 "(%bx)", 363 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)", 364 "(%bx)", 365 }; 366 367 368 /* 369 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2 370 */ 371 const char *const dis_addr32_mode0[16] = { 372 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)", 373 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)" 374 }; 375 376 const char *const dis_addr32_mode12[16] = { 377 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)", 378 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)" 379 }; 380 381 /* 382 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2 383 */ 384 const char *const dis_addr64_mode0[16] = { 385 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)", "(%rdi)", 386 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)" 387 }; 388 const char *const dis_addr64_mode12[16] = { 389 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)", "(%rdi)", 390 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)" 391 }; 392 393 /* 394 * decode for scale from SIB byte 395 */ 396 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" }; 397 398 /* 399 * register decoding for normal references to registers (ie. not addressing) 400 */ 401 const char *const dis_REG8[16] = { 402 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", 403 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 404 }; 405 406 const char *const dis_REG8_REX[16] = { 407 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", 408 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 409 }; 410 411 const char *const dis_REG16[16] = { 412 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", 413 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" 414 }; 415 416 const char *const dis_REG32[16] = { 417 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 418 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" 419 }; 420 421 const char *const dis_REG64[16] = { 422 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 423 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" 424 }; 425 426 const char *const dis_DEBUGREG[16] = { 427 "%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7", 428 "%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15" 429 }; 430 431 const char *const dis_CONTROLREG[16] = { 432 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?", 433 "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?" 434 }; 435 436 const char *const dis_TESTREG[16] = { 437 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7", 438 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7" 439 }; 440 441 const char *const dis_MMREG[16] = { 442 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7", 443 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7" 444 }; 445 446 const char *const dis_XMMREG[16] = { 447 "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7", 448 "%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15" 449 }; 450 451 const char *const dis_YMMREG[16] = { 452 "%ymm0", "%ymm1", "%ymm2", "%ymm3", "%ymm4", "%ymm5", "%ymm6", "%ymm7", 453 "%ymm8", "%ymm9", "%ymm10", "%ymm11", "%ymm12", "%ymm13", "%ymm14", "%ymm15" 454 }; 455 456 const char *const dis_SEGREG[16] = { 457 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>", 458 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>" 459 }; 460 461 /* 462 * SIMD predicate suffixes 463 */ 464 const char *const dis_PREDSUFFIX[8] = { 465 "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord" 466 }; 467 468 const char *const dis_AVXvgrp7[3][8] = { 469 /*0 1 2 3 4 5 6 7*/ 470 /*71*/ {"", "", "vpsrlw", "", "vpsraw", "", "vpsllw", ""}, 471 /*72*/ {"", "", "vpsrld", "", "vpsrad", "", "vpslld", ""}, 472 /*73*/ {"", "", "vpsrlq", "vpsrldq", "", "", "vpsllq", "vpslldq"} 473 }; 474 475 #endif /* DIS_TEXT */ 476 477 /* 478 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63) 479 */ 480 const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ); 481 482 /* 483 * "decode table" for pause and clflush instructions 484 */ 485 const instable_t dis_opPause = TNS("pause", NORM); 486 487 /* 488 * Decode table for 0x0F00 opcodes 489 */ 490 const instable_t dis_op0F00[8] = { 491 492 /* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M), TNSy("ltr",M), 493 /* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID, INVALID, 494 }; 495 496 497 /* 498 * Decode table for 0x0F01 opcodes 499 */ 500 const instable_t dis_op0F01[8] = { 501 502 /* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6), 503 /* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS), 504 }; 505 506 /* 507 * Decode table for 0x0F18 opcodes -- SIMD prefetch 508 */ 509 const instable_t dis_op0F18[8] = { 510 511 /* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF), 512 /* [4] */ INVALID, INVALID, INVALID, INVALID, 513 }; 514 515 /* 516 * Decode table for 0x0FAE opcodes -- SIMD state save/restore 517 */ 518 const instable_t dis_op0FAE[8] = { 519 /* [0] */ TNSZ("fxsave",M,512), TNSZ("fxrstor",M,512), TNS("ldmxcsr",M), TNS("stmxcsr",M), 520 /* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC), 521 }; 522 523 /* 524 * Decode table for 0x0FBA opcodes 525 */ 526 527 const instable_t dis_op0FBA[8] = { 528 529 /* [0] */ INVALID, INVALID, INVALID, INVALID, 530 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb), 531 }; 532 533 /* 534 * Decode table for 0x0FC7 opcode (group 9) 535 */ 536 537 const instable_t dis_op0FC7[8] = { 538 539 /* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, INVALID, 540 /* [4] */ INVALID, INVALID, TNS("vmptrld",MG9), TNS("vmptrst",MG9), 541 }; 542 543 /* 544 * Decode table for 0x0FC7 opcode with 0x66 prefix 545 */ 546 547 const instable_t dis_op660FC7[8] = { 548 549 /* [0] */ INVALID, INVALID, INVALID, INVALID, 550 /* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID, 551 }; 552 553 /* 554 * Decode table for 0x0FC7 opcode with 0xF3 prefix 555 */ 556 557 const instable_t dis_opF30FC7[8] = { 558 559 /* [0] */ INVALID, INVALID, INVALID, INVALID, 560 /* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID, 561 }; 562 563 /* 564 * Decode table for 0x0FC8 opcode -- 486 bswap instruction 565 * 566 *bit pattern: 0000 1111 1100 1reg 567 */ 568 const instable_t dis_op0FC8[4] = { 569 /* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID, 570 }; 571 572 /* 573 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions 574 */ 575 const instable_t dis_op0F7123[4][8] = { 576 { 577 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 578 /* .4 */ INVALID, INVALID, INVALID, INVALID, 579 }, { 580 /* [71].0 */ INVALID, INVALID, TNS("psrlw",MMOSH), INVALID, 581 /* .4 */ TNS("psraw",MMOSH), INVALID, TNS("psllw",MMOSH), INVALID, 582 }, { 583 /* [72].0 */ INVALID, INVALID, TNS("psrld",MMOSH), INVALID, 584 /* .4 */ TNS("psrad",MMOSH), INVALID, TNS("pslld",MMOSH), INVALID, 585 }, { 586 /* [73].0 */ INVALID, INVALID, TNS("psrlq",MMOSH), TNS("INVALID",MMOSH), 587 /* .4 */ INVALID, INVALID, TNS("psllq",MMOSH), TNS("INVALID",MMOSH), 588 } }; 589 590 /* 591 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes. 592 */ 593 const instable_t dis_opSIMD7123[32] = { 594 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 595 /* .4 */ INVALID, INVALID, INVALID, INVALID, 596 597 /* [71].0 */ INVALID, INVALID, TNS("psrlw",XMMSH), INVALID, 598 /* .4 */ TNS("psraw",XMMSH), INVALID, TNS("psllw",XMMSH), INVALID, 599 600 /* [72].0 */ INVALID, INVALID, TNS("psrld",XMMSH), INVALID, 601 /* .4 */ TNS("psrad",XMMSH), INVALID, TNS("pslld",XMMSH), INVALID, 602 603 /* [73].0 */ INVALID, INVALID, TNS("psrlq",XMMSH), TNS("psrldq",XMMSH), 604 /* .4 */ INVALID, INVALID, TNS("psllq",XMMSH), TNS("pslldq",XMMSH), 605 }; 606 607 /* 608 * SIMD instructions have been wedged into the existing IA32 instruction 609 * set through the use of prefixes. That is, while 0xf0 0x58 may be 610 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different 611 * instruction - addss. At present, three prefixes have been coopted in 612 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The 613 * following tables are used to provide the prefixed instruction names. 614 * The arrays are sparse, but they're fast. 615 */ 616 617 /* 618 * Decode table for SIMD instructions with the address size (0x66) prefix. 619 */ 620 const instable_t dis_opSIMDdata16[256] = { 621 /* [00] */ INVALID, INVALID, INVALID, INVALID, 622 /* [04] */ INVALID, INVALID, INVALID, INVALID, 623 /* [08] */ INVALID, INVALID, INVALID, INVALID, 624 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 625 626 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8), 627 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8), 628 /* [18] */ INVALID, INVALID, INVALID, INVALID, 629 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 630 631 /* [20] */ INVALID, INVALID, INVALID, INVALID, 632 /* [24] */ INVALID, INVALID, INVALID, INVALID, 633 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16), 634 /* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8), 635 636 /* [30] */ INVALID, INVALID, INVALID, INVALID, 637 /* [34] */ INVALID, INVALID, INVALID, INVALID, 638 /* [38] */ INVALID, INVALID, INVALID, INVALID, 639 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 640 641 /* [40] */ INVALID, INVALID, INVALID, INVALID, 642 /* [44] */ INVALID, INVALID, INVALID, INVALID, 643 /* [48] */ INVALID, INVALID, INVALID, INVALID, 644 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 645 646 /* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID, INVALID, 647 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16), 648 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16), 649 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16), 650 651 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16), 652 /* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16), 653 /* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16), 654 /* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16), 655 656 /* [70] */ TNSZ("pshufd",XMMP,16), INVALID, INVALID, INVALID, 657 /* [74] */ TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID, 658 /* [78] */ TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID, INVALID, 659 /* [7C] */ INVALID, INVALID, TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16), 660 661 /* [80] */ INVALID, INVALID, INVALID, INVALID, 662 /* [84] */ INVALID, INVALID, INVALID, INVALID, 663 /* [88] */ INVALID, INVALID, INVALID, INVALID, 664 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 665 666 /* [90] */ INVALID, INVALID, INVALID, INVALID, 667 /* [94] */ INVALID, INVALID, INVALID, INVALID, 668 /* [98] */ INVALID, INVALID, INVALID, INVALID, 669 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 670 671 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 672 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 673 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 674 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 675 676 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 677 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 678 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 679 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 680 681 /* [C0] */ INVALID, INVALID, TNSZ("cmppd",XMMP,16), INVALID, 682 /* [C4] */ TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P), TNSZ("shufpd",XMMP,16), INVALID, 683 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 684 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 685 686 /* [D0] */ INVALID, TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16), 687 /* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3), 688 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16), 689 /* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16), 690 691 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16), 692 /* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16), 693 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16), 694 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16), 695 696 /* [F0] */ INVALID, TNSZ("psllw",XMM,16), TNSZ("pslld",XMM,16), TNSZ("psllq",XMM,16), 697 /* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16), 698 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16), 699 /* [FC] */ TNSZ("paddb",XMM,16), TNSZ("paddw",XMM,16), TNSZ("paddd",XMM,16), INVALID, 700 }; 701 702 const instable_t dis_opAVX660F[256] = { 703 /* [00] */ INVALID, INVALID, INVALID, INVALID, 704 /* [04] */ INVALID, INVALID, INVALID, INVALID, 705 /* [08] */ INVALID, INVALID, INVALID, INVALID, 706 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 707 708 /* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8), 709 /* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8), 710 /* [18] */ INVALID, INVALID, INVALID, INVALID, 711 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 712 713 /* [20] */ INVALID, INVALID, INVALID, INVALID, 714 /* [24] */ INVALID, INVALID, INVALID, INVALID, 715 /* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16), 716 /* [2C] */ INVALID, INVALID, TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8), 717 718 /* [30] */ INVALID, INVALID, INVALID, INVALID, 719 /* [34] */ INVALID, INVALID, INVALID, INVALID, 720 /* [38] */ INVALID, INVALID, INVALID, INVALID, 721 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 722 723 /* [40] */ INVALID, INVALID, INVALID, INVALID, 724 /* [44] */ INVALID, INVALID, INVALID, INVALID, 725 /* [48] */ INVALID, INVALID, INVALID, INVALID, 726 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 727 728 /* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16), INVALID, INVALID, 729 /* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16), 730 /* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16), 731 /* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16), 732 733 /* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16), 734 /* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16), 735 /* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16), 736 /* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16), 737 738 /* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16), 739 /* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID, 740 /* [78] */ INVALID, INVALID, INVALID, INVALID, 741 /* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16), 742 743 /* [80] */ INVALID, INVALID, INVALID, INVALID, 744 /* [84] */ INVALID, INVALID, INVALID, INVALID, 745 /* [88] */ INVALID, INVALID, INVALID, INVALID, 746 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 747 748 /* [90] */ INVALID, INVALID, INVALID, INVALID, 749 /* [94] */ INVALID, INVALID, INVALID, INVALID, 750 /* [98] */ INVALID, INVALID, INVALID, INVALID, 751 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 752 753 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 754 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 755 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 756 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 757 758 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 759 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 760 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 761 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 762 763 /* [C0] */ INVALID, INVALID, TNSZ("vcmppd",VEX_RMRX,16), INVALID, 764 /* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID, 765 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 766 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 767 768 /* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16), 769 /* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR), 770 /* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16), 771 /* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16), 772 773 /* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16), 774 /* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16), 775 /* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16), 776 /* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16), 777 778 /* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16), 779 /* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX), 780 /* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16), 781 /* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID, 782 }; 783 784 /* 785 * Decode table for SIMD instructions with the repnz (0xf2) prefix. 786 */ 787 const instable_t dis_opSIMDrepnz[256] = { 788 /* [00] */ INVALID, INVALID, INVALID, INVALID, 789 /* [04] */ INVALID, INVALID, INVALID, INVALID, 790 /* [08] */ INVALID, INVALID, INVALID, INVALID, 791 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 792 793 /* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8), INVALID, INVALID, 794 /* [14] */ INVALID, INVALID, INVALID, INVALID, 795 /* [18] */ INVALID, INVALID, INVALID, INVALID, 796 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 797 798 /* [20] */ INVALID, INVALID, INVALID, INVALID, 799 /* [24] */ INVALID, INVALID, INVALID, INVALID, 800 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8), 801 /* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID, INVALID, 802 803 /* [30] */ INVALID, INVALID, INVALID, INVALID, 804 /* [34] */ INVALID, INVALID, INVALID, INVALID, 805 /* [38] */ INVALID, INVALID, INVALID, INVALID, 806 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 807 808 /* [40] */ INVALID, INVALID, INVALID, INVALID, 809 /* [44] */ INVALID, INVALID, INVALID, INVALID, 810 /* [48] */ INVALID, INVALID, INVALID, INVALID, 811 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 812 813 /* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID, INVALID, 814 /* [54] */ INVALID, INVALID, INVALID, INVALID, 815 /* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8), TNSZ("cvtsd2ss",XMM,8), INVALID, 816 /* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8), TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8), 817 818 /* [60] */ INVALID, INVALID, INVALID, INVALID, 819 /* [64] */ INVALID, INVALID, INVALID, INVALID, 820 /* [68] */ INVALID, INVALID, INVALID, INVALID, 821 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 822 823 /* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID, INVALID, 824 /* [74] */ INVALID, INVALID, INVALID, INVALID, 825 /* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID, INVALID, 826 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 827 828 /* [80] */ INVALID, INVALID, INVALID, INVALID, 829 /* [84] */ INVALID, INVALID, INVALID, INVALID, 830 /* [88] */ INVALID, INVALID, INVALID, INVALID, 831 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 832 833 /* [90] */ INVALID, INVALID, INVALID, INVALID, 834 /* [94] */ INVALID, INVALID, INVALID, INVALID, 835 /* [98] */ INVALID, INVALID, INVALID, INVALID, 836 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 837 838 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 839 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 840 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 841 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 842 843 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 844 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 845 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 846 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 847 848 /* [C0] */ INVALID, INVALID, TNSZ("cmpsd",XMMP,8), INVALID, 849 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 850 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 851 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 852 853 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 854 /* [D4] */ INVALID, INVALID, TNS("movdq2q",XMMXM), INVALID, 855 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 856 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 857 858 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 859 /* [E4] */ INVALID, INVALID, TNSZ("cvtpd2dq",XMM,16),INVALID, 860 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 861 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 862 863 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 864 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 865 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 866 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 867 }; 868 869 const instable_t dis_opAVXF20F[256] = { 870 /* [00] */ INVALID, INVALID, INVALID, INVALID, 871 /* [04] */ INVALID, INVALID, INVALID, INVALID, 872 /* [08] */ INVALID, INVALID, INVALID, INVALID, 873 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 874 875 /* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID, 876 /* [14] */ INVALID, INVALID, INVALID, INVALID, 877 /* [18] */ INVALID, INVALID, INVALID, INVALID, 878 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 879 880 /* [20] */ INVALID, INVALID, INVALID, INVALID, 881 /* [24] */ INVALID, INVALID, INVALID, INVALID, 882 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID, 883 /* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID, INVALID, 884 885 /* [30] */ INVALID, INVALID, INVALID, INVALID, 886 /* [34] */ INVALID, INVALID, INVALID, INVALID, 887 /* [38] */ INVALID, INVALID, INVALID, INVALID, 888 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 889 890 /* [40] */ INVALID, INVALID, INVALID, INVALID, 891 /* [44] */ INVALID, INVALID, INVALID, INVALID, 892 /* [48] */ INVALID, INVALID, INVALID, INVALID, 893 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 894 895 /* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8), INVALID, INVALID, 896 /* [54] */ INVALID, INVALID, INVALID, INVALID, 897 /* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID, 898 /* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8), 899 900 /* [60] */ INVALID, INVALID, INVALID, INVALID, 901 /* [64] */ INVALID, INVALID, INVALID, INVALID, 902 /* [68] */ INVALID, INVALID, INVALID, INVALID, 903 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 904 905 /* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID, INVALID, 906 /* [74] */ INVALID, INVALID, INVALID, INVALID, 907 /* [78] */ INVALID, INVALID, INVALID, INVALID, 908 /* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8), INVALID, INVALID, 909 910 /* [80] */ INVALID, INVALID, INVALID, INVALID, 911 /* [84] */ INVALID, INVALID, INVALID, INVALID, 912 /* [88] */ INVALID, INVALID, INVALID, INVALID, 913 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 914 915 /* [90] */ INVALID, INVALID, INVALID, INVALID, 916 /* [94] */ INVALID, INVALID, INVALID, INVALID, 917 /* [98] */ INVALID, INVALID, INVALID, INVALID, 918 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 919 920 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 921 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 922 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 923 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 924 925 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 926 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 927 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 928 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 929 930 /* [C0] */ INVALID, INVALID, TNSZ("vcmpsd",VEX_RMRX,8), INVALID, 931 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 932 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 933 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 934 935 /* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID, INVALID, INVALID, 936 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 937 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 938 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 939 940 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 941 /* [E4] */ INVALID, INVALID, TNSZ("vcvtpd2dq",VEX_MX,16),INVALID, 942 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 943 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 944 945 /* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID, INVALID, INVALID, 946 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 947 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 948 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 949 }; 950 951 /* 952 * Decode table for SIMD instructions with the repz (0xf3) prefix. 953 */ 954 const instable_t dis_opSIMDrepz[256] = { 955 /* [00] */ INVALID, INVALID, INVALID, INVALID, 956 /* [04] */ INVALID, INVALID, INVALID, INVALID, 957 /* [08] */ INVALID, INVALID, INVALID, INVALID, 958 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 959 960 /* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4), INVALID, INVALID, 961 /* [14] */ INVALID, INVALID, INVALID, INVALID, 962 /* [18] */ INVALID, INVALID, INVALID, INVALID, 963 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 964 965 /* [20] */ INVALID, INVALID, INVALID, INVALID, 966 /* [24] */ INVALID, INVALID, INVALID, INVALID, 967 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4), 968 /* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID, INVALID, 969 970 /* [30] */ INVALID, INVALID, INVALID, INVALID, 971 /* [34] */ INVALID, INVALID, INVALID, INVALID, 972 /* [38] */ INVALID, INVALID, INVALID, INVALID, 973 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 974 975 /* [40] */ INVALID, INVALID, INVALID, INVALID, 976 /* [44] */ INVALID, INVALID, INVALID, INVALID, 977 /* [48] */ INVALID, INVALID, INVALID, INVALID, 978 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 979 980 /* [50] */ INVALID, TNSZ("sqrtss",XMM,4), TNSZ("rsqrtss",XMM,4), TNSZ("rcpss",XMM,4), 981 /* [54] */ INVALID, INVALID, INVALID, INVALID, 982 /* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16), 983 /* [5C] */ TNSZ("subss",XMM,4), TNSZ("minss",XMM,4), TNSZ("divss",XMM,4), TNSZ("maxss",XMM,4), 984 985 /* [60] */ INVALID, INVALID, INVALID, INVALID, 986 /* [64] */ INVALID, INVALID, INVALID, INVALID, 987 /* [68] */ INVALID, INVALID, INVALID, INVALID, 988 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("movdqu",XMM,16), 989 990 /* [70] */ TNSZ("pshufhw",XMMP,16),INVALID, INVALID, INVALID, 991 /* [74] */ INVALID, INVALID, INVALID, INVALID, 992 /* [78] */ INVALID, INVALID, INVALID, INVALID, 993 /* [7C] */ INVALID, INVALID, TNSZ("movq",XMM,8), TNSZ("movdqu",XMMS,16), 994 995 /* [80] */ INVALID, INVALID, INVALID, INVALID, 996 /* [84] */ INVALID, INVALID, INVALID, INVALID, 997 /* [88] */ INVALID, INVALID, INVALID, INVALID, 998 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 999 1000 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1001 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1002 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1003 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1004 1005 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1006 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1007 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1008 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1009 1010 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1011 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1012 /* [B8] */ TS("popcnt",MRw), INVALID, INVALID, INVALID, 1013 /* [BC] */ INVALID, TS("lzcnt",MRw), INVALID, INVALID, 1014 1015 /* [C0] */ INVALID, INVALID, TNSZ("cmpss",XMMP,4), INVALID, 1016 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1017 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1018 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1019 1020 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1021 /* [D4] */ INVALID, INVALID, TNS("movq2dq",XMMMX), INVALID, 1022 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1023 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1024 1025 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1026 /* [E4] */ INVALID, INVALID, TNSZ("cvtdq2pd",XMM,8), INVALID, 1027 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1028 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1029 1030 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1031 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1032 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1033 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1034 }; 1035 1036 const instable_t dis_opAVXF30F[256] = { 1037 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1038 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1039 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1040 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1041 1042 /* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID, 1043 /* [14] */ INVALID, INVALID, TNSZ("vmovshdup",VEX_MX,4), INVALID, 1044 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1045 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1046 1047 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1048 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1049 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID, 1050 /* [2C] */ TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID, INVALID, 1051 1052 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1053 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1054 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1055 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1056 1057 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1058 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1059 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1060 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1061 1062 /* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4), 1063 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1064 /* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16), 1065 /* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4), 1066 1067 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1068 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1069 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1070 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("vmovdqu",VEX_MX,16), 1071 1072 /* [70] */ TNSZ("vpshufhw",VEX_MXI,16),INVALID, INVALID, INVALID, 1073 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1074 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1075 /* [7C] */ INVALID, INVALID, TNSZ("vmovq",VEX_MX,8), TNSZ("vmovdqu",VEX_RX,16), 1076 1077 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1078 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1079 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1080 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1081 1082 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1083 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1084 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1085 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1086 1087 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1088 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1089 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1090 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1091 1092 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1093 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1094 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1095 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1096 1097 /* [C0] */ INVALID, INVALID, TNSZ("vcmpss",VEX_RMRX,4), INVALID, 1098 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1099 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1100 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1101 1102 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1103 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1104 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1105 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1106 1107 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1108 /* [E4] */ INVALID, INVALID, TNSZ("vcvtdq2pd",VEX_MX,8), INVALID, 1109 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1110 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1111 1112 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1113 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1114 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1115 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1116 }; 1117 /* 1118 * The following two tables are used to encode crc32 and movbe 1119 * since they share the same opcodes. 1120 */ 1121 const instable_t dis_op0F38F0[2] = { 1122 /* [00] */ TNS("crc32b",CRC32), 1123 TS("movbe",MOVBE), 1124 }; 1125 1126 const instable_t dis_op0F38F1[2] = { 1127 /* [00] */ TS("crc32",CRC32), 1128 TS("movbe",MOVBE), 1129 }; 1130 1131 const instable_t dis_op0F38[256] = { 1132 /* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16), 1133 /* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16), 1134 /* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16), 1135 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1136 1137 /* [10] */ TNSZ("pblendvb",XMM_66r,16),INVALID, INVALID, INVALID, 1138 /* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16), 1139 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1140 /* [1C] */ TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID, 1141 1142 /* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16), 1143 /* [24] */ TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID, INVALID, 1144 /* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16), 1145 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1146 1147 /* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16), 1148 /* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16), 1149 /* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16), 1150 /* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16), 1151 1152 /* [40] */ TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID, INVALID, 1153 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1154 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1155 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1156 1157 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1158 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1159 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1160 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1161 1162 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1163 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1164 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1165 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1166 1167 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1168 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1169 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1170 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1171 1172 /* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),INVALID, INVALID, 1173 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1174 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1175 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1176 1177 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1178 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1179 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1180 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1181 1182 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1183 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1184 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1185 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1186 1187 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1188 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1189 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1190 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1191 1192 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1193 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1194 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1195 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1196 1197 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1198 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1199 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("aesimc",XMM_66r,16), 1200 /* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16), 1201 1202 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1203 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1204 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1205 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1206 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 1207 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1208 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1209 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1210 }; 1211 1212 const instable_t dis_opAVX660F38[256] = { 1213 /* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16), 1214 /* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16), 1215 /* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16), 1216 /* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16), 1217 1218 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1219 /* [14] */ INVALID, INVALID, INVALID, TNSZ("vptest",VEX_RRI,16), 1220 /* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID, 1221 /* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID, 1222 1223 /* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16), 1224 /* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID, 1225 /* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16), 1226 /* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16), 1227 1228 /* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16), 1229 /* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),INVALID, TNSZ("vpcmpgtq",VEX_RMrX,16), 1230 /* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16), 1231 /* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16), 1232 1233 /* [40] */ TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID, INVALID, 1234 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1235 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1236 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1237 1238 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1239 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1240 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1241 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1242 1243 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1244 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1245 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1246 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1247 1248 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1249 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1250 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1251 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1252 1253 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1254 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1255 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1256 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1257 1258 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1259 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1260 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1261 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1262 1263 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1264 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1265 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1266 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1267 1268 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1269 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1270 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1271 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1272 1273 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1274 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1275 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1276 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1277 1278 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1279 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1280 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("vaesimc",VEX_MX,16), 1281 /* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16), 1282 1283 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1284 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1285 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1286 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1287 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 1288 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1289 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1290 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1291 }; 1292 1293 const instable_t dis_op0F3A[256] = { 1294 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1295 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1296 /* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16), 1297 /* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16), 1298 1299 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1300 /* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16), 1301 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1302 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1303 1304 /* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID, 1305 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1306 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1307 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1308 1309 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1310 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1311 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1312 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1313 1314 /* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID, 1315 /* [44] */ TNSZ("pclmulqdq",XMMP_66r,16),INVALID, INVALID, INVALID, 1316 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1317 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1318 1319 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1320 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1321 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1322 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1323 1324 /* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16), 1325 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1326 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1327 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1328 1329 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1330 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1331 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1332 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1333 1334 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1335 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1336 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1337 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1338 1339 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1340 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1341 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1342 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1343 1344 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1345 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1346 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1347 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1348 1349 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1350 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1351 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1352 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1353 1354 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1355 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1356 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1357 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1358 1359 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1360 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1361 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1362 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("aeskeygenassist",XMMP_66r,16), 1363 1364 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1365 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1366 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1367 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1368 1369 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1370 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1371 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1372 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1373 }; 1374 1375 const instable_t dis_opAVX660F3A[256] = { 1376 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1377 /* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID, 1378 /* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16), 1379 /* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16), 1380 1381 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1382 /* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16), 1383 /* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID, 1384 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1385 1386 /* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID, 1387 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1388 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1389 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1390 1391 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1392 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1393 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1394 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1395 1396 /* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID, 1397 /* [44] */ TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID, INVALID, INVALID, 1398 /* [48] */ INVALID, INVALID, TNSZ("vblendvps",VEX_RMRX,8), TNSZ("vblendvpd",VEX_RMRX,16), 1399 /* [4C] */ TNSZ("vpblendvb",VEX_RMRX,16),INVALID, INVALID, INVALID, 1400 1401 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1402 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1403 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1404 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1405 1406 /* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16), 1407 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1408 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1409 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1410 1411 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1412 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1413 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1414 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1415 1416 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1417 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1418 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1419 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1420 1421 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1422 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1423 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1424 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1425 1426 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1427 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1428 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1429 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1430 1431 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1432 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1433 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1434 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1435 1436 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1437 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1438 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1439 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1440 1441 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1442 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1443 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1444 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("vaeskeygenassist",VEX_MXI,16), 1445 1446 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1447 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1448 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1449 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1450 1451 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1452 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1453 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1454 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1455 }; 1456 1457 /* 1458 * Decode table for 0x0F opcodes 1459 */ 1460 1461 const instable_t dis_op0F[16][16] = { 1462 { 1463 /* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR), 1464 /* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM), 1465 /* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM), 1466 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1467 }, { 1468 /* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8), 1469 /* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8), 1470 /* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID, 1471 /* [1C] */ INVALID, INVALID, INVALID, TS("nop",Mw), 1472 }, { 1473 /* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), 1474 /* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID, 1475 /* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16), 1476 /* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4), 1477 }, { 1478 /* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM), 1479 /* [34] */ TNSx("sysenter",NORM), TNSx("sysexit",NORM), INVALID, INVALID, 1480 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1481 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1482 }, { 1483 /* [40] */ TS("cmovx.o",MR), TS("cmovx.no",MR), TS("cmovx.b",MR), TS("cmovx.ae",MR), 1484 /* [44] */ TS("cmovx.e",MR), TS("cmovx.ne",MR), TS("cmovx.be",MR), TS("cmovx.a",MR), 1485 /* [48] */ TS("cmovx.s",MR), TS("cmovx.ns",MR), TS("cmovx.pe",MR), TS("cmovx.po",MR), 1486 /* [4C] */ TS("cmovx.l",MR), TS("cmovx.ge",MR), TS("cmovx.le",MR), TS("cmovx.g",MR), 1487 }, { 1488 /* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16), 1489 /* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16), 1490 /* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16), 1491 /* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16), 1492 }, { 1493 /* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8), 1494 /* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8), 1495 /* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8), 1496 /* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8), 1497 }, { 1498 /* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR), 1499 /* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM), 1500 /* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID, 1501 /* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8), 1502 }, { 1503 /* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D), 1504 /* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D), 1505 /* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D), 1506 /* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D), 1507 }, { 1508 /* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb), 1509 /* [94] */ TNS("sete",Mb), TNS("setne",Mb), TNS("setbe",Mb), TNS("seta",Mb), 1510 /* [98] */ TNS("sets",Mb), TNS("setns",Mb), TNS("setp",Mb), TNS("setnp",Mb), 1511 /* [9C] */ TNS("setl",Mb), TNS("setge",Mb), TNS("setle",Mb), TNS("setg",Mb), 1512 }, { 1513 /* [A0] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("cpuid",NORM), TS("bt",RMw), 1514 /* [A4] */ TS("shld",DSHIFT), TS("shld",DSHIFTcl), INVALID, INVALID, 1515 /* [A8] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("rsm",NORM), TS("bts",RMw), 1516 /* [AC] */ TS("shrd",DSHIFT), TS("shrd",DSHIFTcl), IND(dis_op0FAE), TS("imul",MRw), 1517 }, { 1518 /* [B0] */ TNS("cmpxchgb",RMw), TS("cmpxchg",RMw), TS("lss",MR), TS("btr",RMw), 1519 /* [B4] */ TS("lfs",MR), TS("lgs",MR), TS("movzb",MOVZ), TNS("movzwl",MOVZ), 1520 /* [B8] */ TNS("INVALID",MRw), INVALID, IND(dis_op0FBA), TS("btc",RMw), 1521 /* [BC] */ TS("bsf",MRw), TS("bsr",MRw), TS("movsb",MOVZ), TNS("movswl",MOVZ), 1522 }, { 1523 /* [C0] */ TNS("xaddb",XADDB), TS("xadd",RMw), TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM), 1524 /* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7), 1525 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1526 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1527 }, { 1528 /* [D0] */ INVALID, TNSZ("psrlw",MMO,8), TNSZ("psrld",MMO,8), TNSZ("psrlq",MMO,8), 1529 /* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3), 1530 /* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8), 1531 /* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8), 1532 }, { 1533 /* [E0] */ TNSZ("pavgb",MMO,8), TNSZ("psraw",MMO,8), TNSZ("psrad",MMO,8), TNSZ("pavgw",MMO,8), 1534 /* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8), 1535 /* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8), 1536 /* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8), 1537 }, { 1538 /* [F0] */ INVALID, TNSZ("psllw",MMO,8), TNSZ("pslld",MMO,8), TNSZ("psllq",MMO,8), 1539 /* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8), 1540 /* [F8] */ TNSZ("psubb",MMO,8), TNSZ("psubw",MMO,8), TNSZ("psubd",MMO,8), TNSZ("psubq",MMO,8), 1541 /* [FC] */ TNSZ("paddb",MMO,8), TNSZ("paddw",MMO,8), TNSZ("paddd",MMO,8), INVALID, 1542 } }; 1543 1544 const instable_t dis_opAVX0F[16][16] = { 1545 { 1546 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1547 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1548 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1549 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1550 }, { 1551 /* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8), 1552 /* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8), 1553 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1554 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1555 }, { 1556 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1557 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1558 /* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16), 1559 /* [2C] */ INVALID, INVALID, TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4), 1560 }, { 1561 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1562 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1563 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1564 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1565 }, { 1566 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1567 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1568 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1569 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1570 }, { 1571 /* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16), 1572 /* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16), 1573 /* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16), 1574 /* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16), 1575 }, { 1576 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1577 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1578 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1579 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1580 }, { 1581 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1582 /* [74] */ INVALID, INVALID, INVALID, TNS("vzeroupper", VEX_NONE), 1583 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1584 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1585 }, { 1586 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1587 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1588 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1589 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1590 }, { 1591 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1592 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1593 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1594 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1595 }, { 1596 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1597 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1598 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1599 /* [AC] */ INVALID, INVALID, TNSZ("vldmxcsr",VEX_MO,2), INVALID, 1600 }, { 1601 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1602 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1603 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1604 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1605 }, { 1606 /* [C0] */ INVALID, INVALID, TNSZ("vcmpps",VEX_RMRX,16),INVALID, 1607 /* [C4] */ INVALID, INVALID, TNSZ("vshufps",VEX_RMRX,16),INVALID, 1608 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1609 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1610 }, { 1611 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1612 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1613 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1614 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1615 }, { 1616 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1617 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1618 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1619 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1620 }, { 1621 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1622 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1623 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1624 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1625 } }; 1626 1627 /* 1628 * Decode table for 0x80 opcodes 1629 */ 1630 1631 const instable_t dis_op80[8] = { 1632 1633 /* [0] */ TNS("addb",IMlw), TNS("orb",IMw), TNS("adcb",IMlw), TNS("sbbb",IMlw), 1634 /* [4] */ TNS("andb",IMw), TNS("subb",IMlw), TNS("xorb",IMw), TNS("cmpb",IMlw), 1635 }; 1636 1637 1638 /* 1639 * Decode table for 0x81 opcodes. 1640 */ 1641 1642 const instable_t dis_op81[8] = { 1643 1644 /* [0] */ TS("add",IMlw), TS("or",IMw), TS("adc",IMlw), TS("sbb",IMlw), 1645 /* [4] */ TS("and",IMw), TS("sub",IMlw), TS("xor",IMw), TS("cmp",IMlw), 1646 }; 1647 1648 1649 /* 1650 * Decode table for 0x82 opcodes. 1651 */ 1652 1653 const instable_t dis_op82[8] = { 1654 1655 /* [0] */ TNSx("addb",IMlw), TNSx("orb",IMlw), TNSx("adcb",IMlw), TNSx("sbbb",IMlw), 1656 /* [4] */ TNSx("andb",IMlw), TNSx("subb",IMlw), TNSx("xorb",IMlw), TNSx("cmpb",IMlw), 1657 }; 1658 /* 1659 * Decode table for 0x83 opcodes. 1660 */ 1661 1662 const instable_t dis_op83[8] = { 1663 1664 /* [0] */ TS("add",IMlw), TS("or",IMlw), TS("adc",IMlw), TS("sbb",IMlw), 1665 /* [4] */ TS("and",IMlw), TS("sub",IMlw), TS("xor",IMlw), TS("cmp",IMlw), 1666 }; 1667 1668 /* 1669 * Decode table for 0xC0 opcodes. 1670 */ 1671 1672 const instable_t dis_opC0[8] = { 1673 1674 /* [0] */ TNS("rolb",MvI), TNS("rorb",MvI), TNS("rclb",MvI), TNS("rcrb",MvI), 1675 /* [4] */ TNS("shlb",MvI), TNS("shrb",MvI), INVALID, TNS("sarb",MvI), 1676 }; 1677 1678 /* 1679 * Decode table for 0xD0 opcodes. 1680 */ 1681 1682 const instable_t dis_opD0[8] = { 1683 1684 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 1685 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 1686 }; 1687 1688 /* 1689 * Decode table for 0xC1 opcodes. 1690 * 186 instruction set 1691 */ 1692 1693 const instable_t dis_opC1[8] = { 1694 1695 /* [0] */ TS("rol",MvI), TS("ror",MvI), TS("rcl",MvI), TS("rcr",MvI), 1696 /* [4] */ TS("shl",MvI), TS("shr",MvI), TS("sal",MvI), TS("sar",MvI), 1697 }; 1698 1699 /* 1700 * Decode table for 0xD1 opcodes. 1701 */ 1702 1703 const instable_t dis_opD1[8] = { 1704 1705 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 1706 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("sal",Mv), TS("sar",Mv), 1707 }; 1708 1709 1710 /* 1711 * Decode table for 0xD2 opcodes. 1712 */ 1713 1714 const instable_t dis_opD2[8] = { 1715 1716 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 1717 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 1718 }; 1719 /* 1720 * Decode table for 0xD3 opcodes. 1721 */ 1722 1723 const instable_t dis_opD3[8] = { 1724 1725 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 1726 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("salb",Mv), TS("sar",Mv), 1727 }; 1728 1729 1730 /* 1731 * Decode table for 0xF6 opcodes. 1732 */ 1733 1734 const instable_t dis_opF6[8] = { 1735 1736 /* [0] */ TNS("testb",IMw), TNS("testb",IMw), TNS("notb",Mw), TNS("negb",Mw), 1737 /* [4] */ TNS("mulb",MA), TNS("imulb",MA), TNS("divb",MA), TNS("idivb",MA), 1738 }; 1739 1740 1741 /* 1742 * Decode table for 0xF7 opcodes. 1743 */ 1744 1745 const instable_t dis_opF7[8] = { 1746 1747 /* [0] */ TS("test",IMw), TS("test",IMw), TS("not",Mw), TS("neg",Mw), 1748 /* [4] */ TS("mul",MA), TS("imul",MA), TS("div",MA), TS("idiv",MA), 1749 }; 1750 1751 1752 /* 1753 * Decode table for 0xFE opcodes. 1754 */ 1755 1756 const instable_t dis_opFE[8] = { 1757 1758 /* [0] */ TNS("incb",Mw), TNS("decb",Mw), INVALID, INVALID, 1759 /* [4] */ INVALID, INVALID, INVALID, INVALID, 1760 }; 1761 /* 1762 * Decode table for 0xFF opcodes. 1763 */ 1764 1765 const instable_t dis_opFF[8] = { 1766 1767 /* [0] */ TS("inc",Mw), TS("dec",Mw), TNSyp("call",INM), TNS("lcall",INM), 1768 /* [4] */ TNSy("jmp",INM), TNS("ljmp",INM), TSp("push",M), INVALID, 1769 }; 1770 1771 /* for 287 instructions, which are a mess to decode */ 1772 1773 const instable_t dis_opFP1n2[8][8] = { 1774 { 1775 /* bit pattern: 1101 1xxx MODxx xR/M */ 1776 /* [0,0] */ TNS("fadds",M), TNS("fmuls",M), TNS("fcoms",M), TNS("fcomps",M), 1777 /* [0,4] */ TNS("fsubs",M), TNS("fsubrs",M), TNS("fdivs",M), TNS("fdivrs",M), 1778 }, { 1779 /* [1,0] */ TNS("flds",M), INVALID, TNS("fsts",M), TNS("fstps",M), 1780 /* [1,4] */ TNSZ("fldenv",M,28), TNSZ("fldcw",M,2), TNSZ("fnstenv",M,28), TNSZ("fnstcw",M,2), 1781 }, { 1782 /* [2,0] */ TNS("fiaddl",M), TNS("fimull",M), TNS("ficoml",M), TNS("ficompl",M), 1783 /* [2,4] */ TNS("fisubl",M), TNS("fisubrl",M), TNS("fidivl",M), TNS("fidivrl",M), 1784 }, { 1785 /* [3,0] */ TNS("fildl",M), INVALID, TNS("fistl",M), TNS("fistpl",M), 1786 /* [3,4] */ INVALID, TNSZ("fldt",M,10), INVALID, TNSZ("fstpt",M,10), 1787 }, { 1788 /* [4,0] */ TNSZ("faddl",M,8), TNSZ("fmull",M,8), TNSZ("fcoml",M,8), TNSZ("fcompl",M,8), 1789 /* [4,1] */ TNSZ("fsubl",M,8), TNSZ("fsubrl",M,8), TNSZ("fdivl",M,8), TNSZ("fdivrl",M,8), 1790 }, { 1791 /* [5,0] */ TNSZ("fldl",M,8), INVALID, TNSZ("fstl",M,8), TNSZ("fstpl",M,8), 1792 /* [5,4] */ TNSZ("frstor",M,108), INVALID, TNSZ("fnsave",M,108), TNSZ("fnstsw",M,2), 1793 }, { 1794 /* [6,0] */ TNSZ("fiadd",M,2), TNSZ("fimul",M,2), TNSZ("ficom",M,2), TNSZ("ficomp",M,2), 1795 /* [6,4] */ TNSZ("fisub",M,2), TNSZ("fisubr",M,2), TNSZ("fidiv",M,2), TNSZ("fidivr",M,2), 1796 }, { 1797 /* [7,0] */ TNSZ("fild",M,2), INVALID, TNSZ("fist",M,2), TNSZ("fistp",M,2), 1798 /* [7,4] */ TNSZ("fbld",M,10), TNSZ("fildll",M,8), TNSZ("fbstp",M,10), TNSZ("fistpll",M,8), 1799 } }; 1800 1801 const instable_t dis_opFP3[8][8] = { 1802 { 1803 /* bit pattern: 1101 1xxx 11xx xREG */ 1804 /* [0,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 1805 /* [0,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 1806 }, { 1807 /* [1,0] */ TNS("fld",F), TNS("fxch",F), TNS("fnop",NORM), TNS("fstp",F), 1808 /* [1,4] */ INVALID, INVALID, INVALID, INVALID, 1809 }, { 1810 /* [2,0] */ INVALID, INVALID, INVALID, INVALID, 1811 /* [2,4] */ INVALID, TNS("fucompp",NORM), INVALID, INVALID, 1812 }, { 1813 /* [3,0] */ INVALID, INVALID, INVALID, INVALID, 1814 /* [3,4] */ INVALID, INVALID, INVALID, INVALID, 1815 }, { 1816 /* [4,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 1817 /* [4,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 1818 }, { 1819 /* [5,0] */ TNS("ffree",F), TNS("fxch",F), TNS("fst",F), TNS("fstp",F), 1820 /* [5,4] */ TNS("fucom",F), TNS("fucomp",F), INVALID, INVALID, 1821 }, { 1822 /* [6,0] */ TNS("faddp",FF), TNS("fmulp",FF), TNS("fcomp",F), TNS("fcompp",NORM), 1823 /* [6,4] */ TNS("fsubp",FF), TNS("fsubrp",FF), TNS("fdivp",FF), TNS("fdivrp",FF), 1824 }, { 1825 /* [7,0] */ TNS("ffreep",F), TNS("fxch",F), TNS("fstp",F), TNS("fstp",F), 1826 /* [7,4] */ TNS("fnstsw",M), TNS("fucomip",FFC), TNS("fcomip",FFC), INVALID, 1827 } }; 1828 1829 const instable_t dis_opFP4[4][8] = { 1830 { 1831 /* bit pattern: 1101 1001 111x xxxx */ 1832 /* [0,0] */ TNS("fchs",NORM), TNS("fabs",NORM), INVALID, INVALID, 1833 /* [0,4] */ TNS("ftst",NORM), TNS("fxam",NORM), TNS("ftstp",NORM), INVALID, 1834 }, { 1835 /* [1,0] */ TNS("fld1",NORM), TNS("fldl2t",NORM), TNS("fldl2e",NORM), TNS("fldpi",NORM), 1836 /* [1,4] */ TNS("fldlg2",NORM), TNS("fldln2",NORM), TNS("fldz",NORM), INVALID, 1837 }, { 1838 /* [2,0] */ TNS("f2xm1",NORM), TNS("fyl2x",NORM), TNS("fptan",NORM), TNS("fpatan",NORM), 1839 /* [2,4] */ TNS("fxtract",NORM), TNS("fprem1",NORM), TNS("fdecstp",NORM), TNS("fincstp",NORM), 1840 }, { 1841 /* [3,0] */ TNS("fprem",NORM), TNS("fyl2xp1",NORM), TNS("fsqrt",NORM), TNS("fsincos",NORM), 1842 /* [3,4] */ TNS("frndint",NORM), TNS("fscale",NORM), TNS("fsin",NORM), TNS("fcos",NORM), 1843 } }; 1844 1845 const instable_t dis_opFP5[8] = { 1846 /* bit pattern: 1101 1011 111x xxxx */ 1847 /* [0] */ TNS("feni",NORM), TNS("fdisi",NORM), TNS("fnclex",NORM), TNS("fninit",NORM), 1848 /* [4] */ TNS("fsetpm",NORM), TNS("frstpm",NORM), INVALID, INVALID, 1849 }; 1850 1851 const instable_t dis_opFP6[8] = { 1852 /* bit pattern: 1101 1011 11yy yxxx */ 1853 /* [00] */ TNS("fcmov.nb",FF), TNS("fcmov.ne",FF), TNS("fcmov.nbe",FF), TNS("fcmov.nu",FF), 1854 /* [04] */ INVALID, TNS("fucomi",F), TNS("fcomi",F), INVALID, 1855 }; 1856 1857 const instable_t dis_opFP7[8] = { 1858 /* bit pattern: 1101 1010 11yy yxxx */ 1859 /* [00] */ TNS("fcmov.b",FF), TNS("fcmov.e",FF), TNS("fcmov.be",FF), TNS("fcmov.u",FF), 1860 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1861 }; 1862 1863 /* 1864 * Main decode table for the op codes. The first two nibbles 1865 * will be used as an index into the table. If there is a 1866 * a need to further decode an instruction, the array to be 1867 * referenced is indicated with the other two entries being 1868 * empty. 1869 */ 1870 1871 const instable_t dis_distable[16][16] = { 1872 { 1873 /* [0,0] */ TNS("addb",RMw), TS("add",RMw), TNS("addb",MRw), TS("add",MRw), 1874 /* [0,4] */ TNS("addb",IA), TS("add",IA), TSx("push",SEG), TSx("pop",SEG), 1875 /* [0,8] */ TNS("orb",RMw), TS("or",RMw), TNS("orb",MRw), TS("or",MRw), 1876 /* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F), 1877 }, { 1878 /* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw), 1879 /* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG), 1880 /* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw), 1881 /* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG), 1882 }, { 1883 /* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw), 1884 /* [2,4] */ TNS("andb",IA), TS("and",IA), TNSx("%es:",OVERRIDE), TNSx("daa",NORM), 1885 /* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw), 1886 /* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM), 1887 }, { 1888 /* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw), 1889 /* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNSx("%ss:",OVERRIDE), TNSx("aaa",NORM), 1890 /* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw), 1891 /* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNSx("%ds:",OVERRIDE), TNSx("aas",NORM), 1892 }, { 1893 /* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 1894 /* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 1895 /* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 1896 /* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 1897 }, { 1898 /* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 1899 /* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 1900 /* [5,8] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 1901 /* [5,C] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 1902 }, { 1903 /* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",MR), TNS("arpl",RMw), 1904 /* [6,4] */ TNS("%fs:",OVERRIDE), TNS("%gs:",OVERRIDE), TNS("data16",DM), TNS("addr16",AM), 1905 /* [6,8] */ TSp("push",I), TS("imul",IMUL), TSp("push",Ib), TS("imul",IMUL), 1906 /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4), 1907 }, { 1908 /* [7,0] */ TNSy("jo",BD), TNSy("jno",BD), TNSy("jb",BD), TNSy("jae",BD), 1909 /* [7,4] */ TNSy("je",BD), TNSy("jne",BD), TNSy("jbe",BD), TNSy("ja",BD), 1910 /* [7,8] */ TNSy("js",BD), TNSy("jns",BD), TNSy("jp",BD), TNSy("jnp",BD), 1911 /* [7,C] */ TNSy("jl",BD), TNSy("jge",BD), TNSy("jle",BD), TNSy("jg",BD), 1912 }, { 1913 /* [8,0] */ IND(dis_op80), IND(dis_op81), INDx(dis_op82), IND(dis_op83), 1914 /* [8,4] */ TNS("testb",RMw), TS("test",RMw), TNS("xchgb",RMw), TS("xchg",RMw), 1915 /* [8,8] */ TNS("movb",RMw), TS("mov",RMw), TNS("movb",MRw), TS("mov",MRw), 1916 /* [8,C] */ TNS("movw",SM), TS("lea",MR), TNS("movw",MS), TSp("pop",M), 1917 }, { 1918 /* [9,0] */ TNS("nop",NORM), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 1919 /* [9,4] */ TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 1920 /* [9,8] */ TNS("cXtX",CBW), TNS("cXtX",CWD), TNSx("lcall",SO), TNS("fwait",NORM), 1921 /* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNSx("sahf",NORM), TNSx("lahf",NORM), 1922 }, { 1923 /* [A,0] */ TNS("movb",OA), TS("mov",OA), TNS("movb",AO), TS("mov",AO), 1924 /* [A,4] */ TNSZ("movsb",SD,1), TS("movs",SD), TNSZ("cmpsb",SD,1), TS("cmps",SD), 1925 /* [A,8] */ TNS("testb",IA), TS("test",IA), TNS("stosb",AD), TS("stos",AD), 1926 /* [A,C] */ TNS("lodsb",SA), TS("lods",SA), TNS("scasb",AD), TS("scas",AD), 1927 }, { 1928 /* [B,0] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 1929 /* [B,4] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 1930 /* [B,8] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 1931 /* [B,C] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 1932 }, { 1933 /* [C,0] */ IND(dis_opC0), IND(dis_opC1), TNSyp("ret",RET), TNSyp("ret",NORM), 1934 /* [C,4] */ TNSx("les",MR), TNSx("lds",MR), TNS("movb",IMw), TS("mov",IMw), 1935 /* [C,8] */ TNSyp("enter",ENTER), TNSyp("leave",NORM), TNS("lret",RET), TNS("lret",NORM), 1936 /* [C,C] */ TNS("int",INT3), TNS("int",INTx), TNSx("into",NORM), TNS("iret",NORM), 1937 }, { 1938 /* [D,0] */ IND(dis_opD0), IND(dis_opD1), IND(dis_opD2), IND(dis_opD3), 1939 /* [D,4] */ TNSx("aam",U), TNSx("aad",U), TNSx("falc",NORM), TNSZ("xlat",IMPLMEM,1), 1940 1941 /* 287 instructions. Note that although the indirect field */ 1942 /* indicates opFP1n2 for further decoding, this is not necessarily */ 1943 /* the case since the opFP arrays are not partitioned according to key1 */ 1944 /* and key2. opFP1n2 is given only to indicate that we haven't */ 1945 /* finished decoding the instruction. */ 1946 /* [D,8] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 1947 /* [D,C] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 1948 }, { 1949 /* [E,0] */ TNSy("loopnz",BD), TNSy("loopz",BD), TNSy("loop",BD), TNSy("jcxz",BD), 1950 /* [E,4] */ TNS("inb",P), TS("in",P), TNS("outb",P), TS("out",P), 1951 /* [E,8] */ TNSyp("call",D), TNSy("jmp",D), TNSx("ljmp",SO), TNSy("jmp",BD), 1952 /* [E,C] */ TNS("inb",V), TS("in",V), TNS("outb",V), TS("out",V), 1953 }, { 1954 /* [F,0] */ TNS("lock",LOCK), TNS("icebp", NORM), TNS("repnz",PREFIX), TNS("repz",PREFIX), 1955 /* [F,4] */ TNS("hlt",NORM), TNS("cmc",NORM), IND(dis_opF6), IND(dis_opF7), 1956 /* [F,8] */ TNS("clc",NORM), TNS("stc",NORM), TNS("cli",NORM), TNS("sti",NORM), 1957 /* [F,C] */ TNS("cld",NORM), TNS("std",NORM), IND(dis_opFE), IND(dis_opFF), 1958 } }; 1959 1960 /* END CSTYLED */ 1961 1962 /* 1963 * common functions to decode and disassemble an x86 or amd64 instruction 1964 */ 1965 1966 /* 1967 * These are the individual fields of a REX prefix. Note that a REX 1968 * prefix with none of these set is still needed to: 1969 * - use the MOVSXD (sign extend 32 to 64 bits) instruction 1970 * - access the %sil, %dil, %bpl, %spl registers 1971 */ 1972 #define REX_W 0x08 /* 64 bit operand size when set */ 1973 #define REX_R 0x04 /* high order bit extension of ModRM reg field */ 1974 #define REX_X 0x02 /* high order bit extension of SIB index field */ 1975 #define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */ 1976 1977 /* 1978 * These are the individual fields of a VEX prefix. 1979 */ 1980 #define VEX_R 0x08 /* REX.R in 1's complement form */ 1981 #define VEX_X 0x04 /* REX.X in 1's complement form */ 1982 #define VEX_B 0x02 /* REX.B in 1's complement form */ 1983 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */ 1984 #define VEX_L 0x04 1985 #define VEX_W 0x08 /* opcode specific, use like REX.W */ 1986 #define VEX_m 0x1F /* VEX m-mmmm field */ 1987 #define VEX_v 0x78 /* VEX register specifier */ 1988 #define VEX_p 0x03 /* VEX pp field, opcode extension */ 1989 1990 /* VEX m-mmmm field, only used by three bytes prefix */ 1991 #define VEX_m_0F 0x01 /* implied 0F leading opcode byte */ 1992 #define VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */ 1993 #define VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */ 1994 1995 /* VEX pp field, providing equivalent functionality of a SIMD prefix */ 1996 #define VEX_p_66 0x01 1997 #define VEX_p_F3 0x02 1998 #define VEX_p_F2 0x03 1999 2000 /* 2001 * Even in 64 bit mode, usually only 4 byte immediate operands are supported. 2002 */ 2003 static int isize[] = {1, 2, 4, 4}; 2004 static int isize64[] = {1, 2, 4, 8}; 2005 2006 /* 2007 * Just a bunch of useful macros. 2008 */ 2009 #define WBIT(x) (x & 0x1) /* to get w bit */ 2010 #define REGNO(x) (x & 0x7) /* to get 3 bit register */ 2011 #define VBIT(x) ((x)>>1 & 0x1) /* to get 'v' bit */ 2012 #define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1) 2013 #define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1) 2014 2015 #define REG_ONLY 3 /* mode to indicate a register operand (not memory) */ 2016 2017 #define BYTE_OPND 0 /* w-bit value indicating byte register */ 2018 #define LONG_OPND 1 /* w-bit value indicating opnd_size register */ 2019 #define MM_OPND 2 /* "value" used to indicate a mmx reg */ 2020 #define XMM_OPND 3 /* "value" used to indicate a xmm reg */ 2021 #define SEG_OPND 4 /* "value" used to indicate a segment reg */ 2022 #define CONTROL_OPND 5 /* "value" used to indicate a control reg */ 2023 #define DEBUG_OPND 6 /* "value" used to indicate a debug reg */ 2024 #define TEST_OPND 7 /* "value" used to indicate a test reg */ 2025 #define WORD_OPND 8 /* w-bit value indicating word size reg */ 2026 #define YMM_OPND 9 /* "value" used to indicate a ymm reg */ 2027 2028 /* 2029 * Get the next byte and separate the op code into the high and low nibbles. 2030 */ 2031 static int 2032 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low) 2033 { 2034 int byte; 2035 2036 /* 2037 * x86 instructions have a maximum length of 15 bytes. Bail out if 2038 * we try to read more. 2039 */ 2040 if (x->d86_len >= 15) 2041 return (x->d86_error = 1); 2042 2043 if (x->d86_error) 2044 return (1); 2045 byte = x->d86_get_byte(x->d86_data); 2046 if (byte < 0) 2047 return (x->d86_error = 1); 2048 x->d86_bytes[x->d86_len++] = byte; 2049 *low = byte & 0xf; /* ----xxxx low 4 bits */ 2050 *high = byte >> 4 & 0xf; /* xxxx---- bits 7 to 4 */ 2051 return (0); 2052 } 2053 2054 /* 2055 * Get and decode an SIB (scaled index base) byte 2056 */ 2057 static void 2058 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base) 2059 { 2060 int byte; 2061 2062 if (x->d86_error) 2063 return; 2064 2065 byte = x->d86_get_byte(x->d86_data); 2066 if (byte < 0) { 2067 x->d86_error = 1; 2068 return; 2069 } 2070 x->d86_bytes[x->d86_len++] = byte; 2071 2072 *base = byte & 0x7; 2073 *index = (byte >> 3) & 0x7; 2074 *ss = (byte >> 6) & 0x3; 2075 } 2076 2077 /* 2078 * Get the byte following the op code and separate it into the 2079 * mode, register, and r/m fields. 2080 */ 2081 static void 2082 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m) 2083 { 2084 if (x->d86_got_modrm == 0) { 2085 if (x->d86_rmindex == -1) 2086 x->d86_rmindex = x->d86_len; 2087 dtrace_get_SIB(x, mode, reg, r_m); 2088 x->d86_got_modrm = 1; 2089 } 2090 } 2091 2092 /* 2093 * Adjust register selection based on any REX prefix bits present. 2094 */ 2095 /*ARGSUSED*/ 2096 static void 2097 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m) 2098 { 2099 if (reg != NULL && r_m == NULL) { 2100 if (rex_prefix & REX_B) 2101 *reg += 8; 2102 } else { 2103 if (reg != NULL && (REX_R & rex_prefix) != 0) 2104 *reg += 8; 2105 if (r_m != NULL && (REX_B & rex_prefix) != 0) 2106 *r_m += 8; 2107 } 2108 } 2109 2110 /* 2111 * Adjust register selection based on any VEX prefix bits present. 2112 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix 2113 */ 2114 /*ARGSUSED*/ 2115 static void 2116 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m) 2117 { 2118 if (reg != NULL && r_m == NULL) { 2119 if (!(vex_byte1 & VEX_B)) 2120 *reg += 8; 2121 } else { 2122 if (reg != NULL && ((VEX_R & vex_byte1) == 0)) 2123 *reg += 8; 2124 if (r_m != NULL && ((VEX_B & vex_byte1) == 0)) 2125 *r_m += 8; 2126 } 2127 } 2128 2129 /* 2130 * Get an immediate operand of the given size, with sign extension. 2131 */ 2132 static void 2133 dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex) 2134 { 2135 int i; 2136 int byte; 2137 int valsize; 2138 2139 if (x->d86_numopnds < opindex + 1) 2140 x->d86_numopnds = opindex + 1; 2141 2142 switch (wbit) { 2143 case BYTE_OPND: 2144 valsize = 1; 2145 break; 2146 case LONG_OPND: 2147 if (x->d86_opnd_size == SIZE16) 2148 valsize = 2; 2149 else if (x->d86_opnd_size == SIZE32) 2150 valsize = 4; 2151 else 2152 valsize = 8; 2153 break; 2154 case MM_OPND: 2155 case XMM_OPND: 2156 case YMM_OPND: 2157 case SEG_OPND: 2158 case CONTROL_OPND: 2159 case DEBUG_OPND: 2160 case TEST_OPND: 2161 valsize = size; 2162 break; 2163 case WORD_OPND: 2164 valsize = 2; 2165 break; 2166 } 2167 if (valsize < size) 2168 valsize = size; 2169 2170 if (x->d86_error) 2171 return; 2172 x->d86_opnd[opindex].d86_value = 0; 2173 for (i = 0; i < size; ++i) { 2174 byte = x->d86_get_byte(x->d86_data); 2175 if (byte < 0) { 2176 x->d86_error = 1; 2177 return; 2178 } 2179 x->d86_bytes[x->d86_len++] = byte; 2180 x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8); 2181 } 2182 /* Do sign extension */ 2183 if (x->d86_bytes[x->d86_len - 1] & 0x80) { 2184 for (; i < sizeof (uint64_t); i++) 2185 x->d86_opnd[opindex].d86_value |= 2186 (uint64_t)0xff << (i * 8); 2187 } 2188 #ifdef DIS_TEXT 2189 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 2190 x->d86_opnd[opindex].d86_value_size = valsize; 2191 x->d86_imm_bytes += size; 2192 #endif 2193 } 2194 2195 /* 2196 * Get an ip relative operand of the given size, with sign extension. 2197 */ 2198 static void 2199 dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex) 2200 { 2201 dtrace_imm_opnd(x, wbit, size, opindex); 2202 #ifdef DIS_TEXT 2203 x->d86_opnd[opindex].d86_mode = MODE_IPREL; 2204 #endif 2205 } 2206 2207 /* 2208 * Check to see if there is a segment override prefix pending. 2209 * If so, print it in the current 'operand' location and set 2210 * the override flag back to false. 2211 */ 2212 /*ARGSUSED*/ 2213 static void 2214 dtrace_check_override(dis86_t *x, int opindex) 2215 { 2216 #ifdef DIS_TEXT 2217 if (x->d86_seg_prefix) { 2218 (void) strlcat(x->d86_opnd[opindex].d86_prefix, 2219 x->d86_seg_prefix, PFIXLEN); 2220 } 2221 #endif 2222 x->d86_seg_prefix = NULL; 2223 } 2224 2225 2226 /* 2227 * Process a single instruction Register or Memory operand. 2228 * 2229 * mode = addressing mode from ModRM byte 2230 * r_m = r_m (or reg if mode == 3) field from ModRM byte 2231 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use. 2232 * o = index of operand that we are processing (0, 1 or 2) 2233 * 2234 * the value of reg or r_m must have already been adjusted for any REX prefix. 2235 */ 2236 /*ARGSUSED*/ 2237 static void 2238 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex) 2239 { 2240 int have_SIB = 0; /* flag presence of scale-index-byte */ 2241 uint_t ss; /* scale-factor from opcode */ 2242 uint_t index; /* index register number */ 2243 uint_t base; /* base register number */ 2244 int dispsize; /* size of displacement in bytes */ 2245 #ifdef DIS_TEXT 2246 char *opnd = x->d86_opnd[opindex].d86_opnd; 2247 #endif 2248 2249 if (x->d86_numopnds < opindex + 1) 2250 x->d86_numopnds = opindex + 1; 2251 2252 if (x->d86_error) 2253 return; 2254 2255 /* 2256 * first handle a simple register 2257 */ 2258 if (mode == REG_ONLY) { 2259 #ifdef DIS_TEXT 2260 switch (wbit) { 2261 case MM_OPND: 2262 (void) strlcat(opnd, dis_MMREG[r_m], OPLEN); 2263 break; 2264 case XMM_OPND: 2265 (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN); 2266 break; 2267 case YMM_OPND: 2268 (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN); 2269 break; 2270 case SEG_OPND: 2271 (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN); 2272 break; 2273 case CONTROL_OPND: 2274 (void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN); 2275 break; 2276 case DEBUG_OPND: 2277 (void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN); 2278 break; 2279 case TEST_OPND: 2280 (void) strlcat(opnd, dis_TESTREG[r_m], OPLEN); 2281 break; 2282 case BYTE_OPND: 2283 if (x->d86_rex_prefix == 0) 2284 (void) strlcat(opnd, dis_REG8[r_m], OPLEN); 2285 else 2286 (void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN); 2287 break; 2288 case WORD_OPND: 2289 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 2290 break; 2291 case LONG_OPND: 2292 if (x->d86_opnd_size == SIZE16) 2293 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 2294 else if (x->d86_opnd_size == SIZE32) 2295 (void) strlcat(opnd, dis_REG32[r_m], OPLEN); 2296 else 2297 (void) strlcat(opnd, dis_REG64[r_m], OPLEN); 2298 break; 2299 } 2300 #endif /* DIS_TEXT */ 2301 return; 2302 } 2303 2304 /* 2305 * if symbolic representation, skip override prefix, if any 2306 */ 2307 dtrace_check_override(x, opindex); 2308 2309 /* 2310 * Handle 16 bit memory references first, since they decode 2311 * the mode values more simply. 2312 * mode 1 is r_m + 8 bit displacement 2313 * mode 2 is r_m + 16 bit displacement 2314 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp 2315 */ 2316 if (x->d86_addr_size == SIZE16) { 2317 if ((mode == 0 && r_m == 6) || mode == 2) 2318 dtrace_imm_opnd(x, WORD_OPND, 2, opindex); 2319 else if (mode == 1) 2320 dtrace_imm_opnd(x, BYTE_OPND, 1, opindex); 2321 #ifdef DIS_TEXT 2322 if (mode == 0 && r_m == 6) 2323 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 2324 else if (mode == 0) 2325 x->d86_opnd[opindex].d86_mode = MODE_NONE; 2326 else 2327 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 2328 (void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN); 2329 #endif 2330 return; 2331 } 2332 2333 /* 2334 * 32 and 64 bit addressing modes are more complex since they 2335 * can involve an SIB (scaled index and base) byte to decode. 2336 */ 2337 if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8) { 2338 have_SIB = 1; 2339 dtrace_get_SIB(x, &ss, &index, &base); 2340 if (x->d86_error) 2341 return; 2342 if (base != 5 || mode != 0) 2343 if (x->d86_rex_prefix & REX_B) 2344 base += 8; 2345 if (x->d86_rex_prefix & REX_X) 2346 index += 8; 2347 } else { 2348 base = r_m; 2349 } 2350 2351 /* 2352 * Compute the displacement size and get its bytes 2353 */ 2354 dispsize = 0; 2355 2356 if (mode == 1) 2357 dispsize = 1; 2358 else if (mode == 2) 2359 dispsize = 4; 2360 else if ((r_m & 7) == EBP_REGNO || 2361 (have_SIB && (base & 7) == EBP_REGNO)) 2362 dispsize = 4; 2363 2364 if (dispsize > 0) { 2365 dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND, 2366 dispsize, opindex); 2367 if (x->d86_error) 2368 return; 2369 } 2370 2371 #ifdef DIS_TEXT 2372 if (dispsize > 0) 2373 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 2374 2375 if (have_SIB == 0) { 2376 if (x->d86_mode == SIZE32) { 2377 if (mode == 0) 2378 (void) strlcat(opnd, dis_addr32_mode0[r_m], 2379 OPLEN); 2380 else 2381 (void) strlcat(opnd, dis_addr32_mode12[r_m], 2382 OPLEN); 2383 } else { 2384 if (mode == 0) { 2385 (void) strlcat(opnd, dis_addr64_mode0[r_m], 2386 OPLEN); 2387 if (r_m == 5) { 2388 x->d86_opnd[opindex].d86_mode = 2389 MODE_RIPREL; 2390 } 2391 } else { 2392 (void) strlcat(opnd, dis_addr64_mode12[r_m], 2393 OPLEN); 2394 } 2395 } 2396 } else { 2397 uint_t need_paren = 0; 2398 char **regs; 2399 if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */ 2400 regs = (char **)dis_REG32; 2401 else 2402 regs = (char **)dis_REG64; 2403 2404 /* 2405 * print the base (if any) 2406 */ 2407 if (base == EBP_REGNO && mode == 0) { 2408 if (index != ESP_REGNO) { 2409 (void) strlcat(opnd, "(", OPLEN); 2410 need_paren = 1; 2411 } 2412 } else { 2413 (void) strlcat(opnd, "(", OPLEN); 2414 (void) strlcat(opnd, regs[base], OPLEN); 2415 need_paren = 1; 2416 } 2417 2418 /* 2419 * print the index (if any) 2420 */ 2421 if (index != ESP_REGNO) { 2422 (void) strlcat(opnd, ",", OPLEN); 2423 (void) strlcat(opnd, regs[index], OPLEN); 2424 (void) strlcat(opnd, dis_scale_factor[ss], OPLEN); 2425 } else 2426 if (need_paren) 2427 (void) strlcat(opnd, ")", OPLEN); 2428 } 2429 #endif 2430 } 2431 2432 /* 2433 * Operand sequence for standard instruction involving one register 2434 * and one register/memory operand. 2435 * wbit indicates a byte(0) or opnd_size(1) operation 2436 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r") 2437 */ 2438 #define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \ 2439 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2440 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2441 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 2442 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \ 2443 } 2444 2445 /* 2446 * Similar to above, but allows for the two operands to be of different 2447 * classes (ie. wbit). 2448 * wbit is for the r_m operand 2449 * w2 is for the reg operand 2450 */ 2451 #define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \ 2452 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2453 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2454 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 2455 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \ 2456 } 2457 2458 /* 2459 * Similar, but for 2 operands plus an immediate. 2460 * vbit indicates direction 2461 * 0 for "opcode imm, r, r_m" or 2462 * 1 for "opcode imm, r_m, r" 2463 */ 2464 #define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \ 2465 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2466 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2467 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \ 2468 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \ 2469 dtrace_imm_opnd(x, wbit, immsize, 0); \ 2470 } 2471 2472 /* 2473 * Similar, but for 2 operands plus two immediates. 2474 */ 2475 #define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \ 2476 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2477 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2478 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 2479 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \ 2480 dtrace_imm_opnd(x, wbit, immsize, 1); \ 2481 dtrace_imm_opnd(x, wbit, immsize, 0); \ 2482 } 2483 2484 /* 2485 * 1 operands plus two immediates. 2486 */ 2487 #define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \ 2488 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2489 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2490 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 2491 dtrace_imm_opnd(x, wbit, immsize, 1); \ 2492 dtrace_imm_opnd(x, wbit, immsize, 0); \ 2493 } 2494 2495 /* 2496 * Dissassemble a single x86 or amd64 instruction. 2497 * 2498 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64) 2499 * for interpreting instructions. 2500 * 2501 * returns non-zero for bad opcode 2502 */ 2503 int 2504 dtrace_disx86(dis86_t *x, uint_t cpu_mode) 2505 { 2506 instable_t *dp; /* decode table being used */ 2507 #ifdef DIS_TEXT 2508 uint_t i; 2509 #endif 2510 #ifdef DIS_MEM 2511 uint_t nomem = 0; 2512 #define NOMEM (nomem = 1) 2513 #else 2514 #define NOMEM /* nothing */ 2515 #endif 2516 uint_t opnd_size; /* SIZE16, SIZE32 or SIZE64 */ 2517 uint_t addr_size; /* SIZE16, SIZE32 or SIZE64 */ 2518 uint_t wbit; /* opcode wbit, 0 is 8 bit, !0 for opnd_size */ 2519 uint_t w2; /* wbit value for second operand */ 2520 uint_t vbit; 2521 uint_t mode = 0; /* mode value from ModRM byte */ 2522 uint_t reg; /* reg value from ModRM byte */ 2523 uint_t r_m; /* r_m value from ModRM byte */ 2524 2525 uint_t opcode1; /* high nibble of 1st byte */ 2526 uint_t opcode2; /* low nibble of 1st byte */ 2527 uint_t opcode3; /* extra opcode bits usually from ModRM byte */ 2528 uint_t opcode4; /* high nibble of 2nd byte */ 2529 uint_t opcode5; /* low nibble of 2nd byte */ 2530 uint_t opcode6; /* high nibble of 3rd byte */ 2531 uint_t opcode7; /* low nibble of 3rd byte */ 2532 uint_t opcode_bytes = 1; 2533 2534 /* 2535 * legacy prefixes come in 5 flavors, you should have only one of each 2536 */ 2537 uint_t opnd_size_prefix = 0; 2538 uint_t addr_size_prefix = 0; 2539 uint_t segment_prefix = 0; 2540 uint_t lock_prefix = 0; 2541 uint_t rep_prefix = 0; 2542 uint_t rex_prefix = 0; /* amd64 register extension prefix */ 2543 2544 /* 2545 * Intel VEX instruction encoding prefix and fields 2546 */ 2547 2548 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */ 2549 uint_t vex_prefix = 0; 2550 2551 /* 2552 * VEX prefix byte 1, includes vex.r, vex.x and vex.b 2553 * (for 3 bytes prefix) 2554 */ 2555 uint_t vex_byte1 = 0; 2556 2557 /* 2558 * For 32-bit mode, it should prefetch the next byte to 2559 * distinguish between AVX and les/lds 2560 */ 2561 uint_t vex_prefetch = 0; 2562 2563 uint_t vex_m = 0; 2564 uint_t vex_v = 0; 2565 uint_t vex_p = 0; 2566 uint_t vex_R = 1; 2567 uint_t vex_X = 1; 2568 uint_t vex_B = 1; 2569 uint_t vex_W = 0; 2570 uint_t vex_L; 2571 2572 2573 size_t off; 2574 2575 instable_t dp_mmx; 2576 2577 x->d86_len = 0; 2578 x->d86_rmindex = -1; 2579 x->d86_error = 0; 2580 #ifdef DIS_TEXT 2581 x->d86_numopnds = 0; 2582 x->d86_seg_prefix = NULL; 2583 x->d86_mnem[0] = 0; 2584 for (i = 0; i < 4; ++i) { 2585 x->d86_opnd[i].d86_opnd[0] = 0; 2586 x->d86_opnd[i].d86_prefix[0] = 0; 2587 x->d86_opnd[i].d86_value_size = 0; 2588 x->d86_opnd[i].d86_value = 0; 2589 x->d86_opnd[i].d86_mode = MODE_NONE; 2590 } 2591 #endif 2592 x->d86_rex_prefix = 0; 2593 x->d86_got_modrm = 0; 2594 x->d86_memsize = 0; 2595 2596 if (cpu_mode == SIZE16) { 2597 opnd_size = SIZE16; 2598 addr_size = SIZE16; 2599 } else if (cpu_mode == SIZE32) { 2600 opnd_size = SIZE32; 2601 addr_size = SIZE32; 2602 } else { 2603 opnd_size = SIZE32; 2604 addr_size = SIZE64; 2605 } 2606 2607 /* 2608 * Get one opcode byte and check for zero padding that follows 2609 * jump tables. 2610 */ 2611 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 2612 goto error; 2613 2614 if (opcode1 == 0 && opcode2 == 0 && 2615 x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) { 2616 #ifdef DIS_TEXT 2617 (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN); 2618 #endif 2619 goto done; 2620 } 2621 2622 /* 2623 * Gather up legacy x86 prefix bytes. 2624 */ 2625 for (;;) { 2626 uint_t *which_prefix = NULL; 2627 2628 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 2629 2630 switch (dp->it_adrmode) { 2631 case PREFIX: 2632 which_prefix = &rep_prefix; 2633 break; 2634 case LOCK: 2635 which_prefix = &lock_prefix; 2636 break; 2637 case OVERRIDE: 2638 which_prefix = &segment_prefix; 2639 #ifdef DIS_TEXT 2640 x->d86_seg_prefix = (char *)dp->it_name; 2641 #endif 2642 if (dp->it_invalid64 && cpu_mode == SIZE64) 2643 goto error; 2644 break; 2645 case AM: 2646 which_prefix = &addr_size_prefix; 2647 break; 2648 case DM: 2649 which_prefix = &opnd_size_prefix; 2650 break; 2651 } 2652 if (which_prefix == NULL) 2653 break; 2654 *which_prefix = (opcode1 << 4) | opcode2; 2655 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 2656 goto error; 2657 } 2658 2659 /* 2660 * Handle amd64 mode PREFIX values. 2661 * Some of the segment prefixes are no-ops. (only FS/GS actually work) 2662 * We might have a REX prefix (opcodes 0x40-0x4f) 2663 */ 2664 if (cpu_mode == SIZE64) { 2665 if (segment_prefix != 0x64 && segment_prefix != 0x65) 2666 segment_prefix = 0; 2667 2668 if (opcode1 == 0x4) { 2669 rex_prefix = (opcode1 << 4) | opcode2; 2670 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 2671 goto error; 2672 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 2673 } else if (opcode1 == 0xC && 2674 (opcode2 == 0x4 || opcode2 == 0x5)) { 2675 /* AVX instructions */ 2676 vex_prefix = (opcode1 << 4) | opcode2; 2677 x->d86_rex_prefix = 0x40; 2678 } 2679 } else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) { 2680 /* LDS, LES or AVX */ 2681 dtrace_get_modrm(x, &mode, ®, &r_m); 2682 vex_prefetch = 1; 2683 2684 if (mode == REG_ONLY) { 2685 /* AVX */ 2686 vex_prefix = (opcode1 << 4) | opcode2; 2687 x->d86_rex_prefix = 0x40; 2688 opcode3 = (((mode << 3) | reg)>>1) & 0x0F; 2689 opcode4 = ((reg << 3) | r_m) & 0x0F; 2690 } 2691 } 2692 2693 if (vex_prefix == VEX_2bytes) { 2694 if (!vex_prefetch) { 2695 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 2696 goto error; 2697 } 2698 vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3; 2699 vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2; 2700 vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3; 2701 vex_p = opcode4 & VEX_p; 2702 /* 2703 * The vex.x and vex.b bits are not defined in two bytes 2704 * mode vex prefix, their default values are 1 2705 */ 2706 vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B; 2707 2708 if (vex_R == 0) 2709 x->d86_rex_prefix |= REX_R; 2710 2711 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 2712 goto error; 2713 2714 switch (vex_p) { 2715 case VEX_p_66: 2716 dp = (instable_t *) 2717 &dis_opAVX660F[(opcode1 << 4) | opcode2]; 2718 break; 2719 case VEX_p_F3: 2720 dp = (instable_t *) 2721 &dis_opAVXF30F[(opcode1 << 4) | opcode2]; 2722 break; 2723 case VEX_p_F2: 2724 dp = (instable_t *) 2725 &dis_opAVXF20F [(opcode1 << 4) | opcode2]; 2726 break; 2727 default: 2728 dp = (instable_t *) 2729 &dis_opAVX0F[opcode1][opcode2]; 2730 2731 } 2732 2733 } else if (vex_prefix == VEX_3bytes) { 2734 if (!vex_prefetch) { 2735 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 2736 goto error; 2737 } 2738 vex_R = (opcode3 & VEX_R) >> 3; 2739 vex_X = (opcode3 & VEX_X) >> 2; 2740 vex_B = (opcode3 & VEX_B) >> 1; 2741 vex_m = (((opcode3 << 4) | opcode4) & VEX_m); 2742 vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B); 2743 2744 if (vex_R == 0) 2745 x->d86_rex_prefix |= REX_R; 2746 if (vex_X == 0) 2747 x->d86_rex_prefix |= REX_X; 2748 if (vex_B == 0) 2749 x->d86_rex_prefix |= REX_B; 2750 2751 if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0) 2752 goto error; 2753 vex_W = (opcode5 & VEX_W) >> 3; 2754 vex_L = (opcode6 & VEX_L) >> 2; 2755 vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3; 2756 vex_p = opcode6 & VEX_p; 2757 2758 if (vex_W) 2759 x->d86_rex_prefix |= REX_W; 2760 2761 /* Only these three vex_m values valid; others are reserved */ 2762 if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) && 2763 (vex_m != VEX_m_0F3A)) 2764 goto error; 2765 2766 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 2767 goto error; 2768 2769 switch (vex_p) { 2770 case VEX_p_66: 2771 if (vex_m == VEX_m_0F) { 2772 dp = (instable_t *) 2773 &dis_opAVX660F 2774 [(opcode1 << 4) | opcode2]; 2775 } else if (vex_m == VEX_m_0F38) { 2776 dp = (instable_t *) 2777 &dis_opAVX660F38 2778 [(opcode1 << 4) | opcode2]; 2779 } else if (vex_m == VEX_m_0F3A) { 2780 dp = (instable_t *) 2781 &dis_opAVX660F3A 2782 [(opcode1 << 4) | opcode2]; 2783 } else { 2784 goto error; 2785 } 2786 break; 2787 case VEX_p_F3: 2788 if (vex_m == VEX_m_0F) { 2789 dp = (instable_t *) 2790 &dis_opAVXF30F 2791 [(opcode1 << 4) | opcode2]; 2792 } else { 2793 goto error; 2794 } 2795 break; 2796 case VEX_p_F2: 2797 if (vex_m == VEX_m_0F) { 2798 dp = (instable_t *) 2799 &dis_opAVXF20F 2800 [(opcode1 << 4) | opcode2]; 2801 } else { 2802 goto error; 2803 } 2804 break; 2805 default: 2806 dp = (instable_t *) 2807 &dis_opAVX0F[opcode1][opcode2]; 2808 2809 } 2810 } 2811 if (vex_prefix) { 2812 if (vex_L) 2813 wbit = YMM_OPND; 2814 else 2815 wbit = XMM_OPND; 2816 } 2817 2818 /* 2819 * Deal with selection of operand and address size now. 2820 * Note that the REX.W bit being set causes opnd_size_prefix to be 2821 * ignored. 2822 */ 2823 if (cpu_mode == SIZE64) { 2824 if ((rex_prefix & REX_W) || vex_W) 2825 opnd_size = SIZE64; 2826 else if (opnd_size_prefix) 2827 opnd_size = SIZE16; 2828 2829 if (addr_size_prefix) 2830 addr_size = SIZE32; 2831 } else if (cpu_mode == SIZE32) { 2832 if (opnd_size_prefix) 2833 opnd_size = SIZE16; 2834 if (addr_size_prefix) 2835 addr_size = SIZE16; 2836 } else { 2837 if (opnd_size_prefix) 2838 opnd_size = SIZE32; 2839 if (addr_size_prefix) 2840 addr_size = SIZE32; 2841 } 2842 /* 2843 * The pause instruction - a repz'd nop. This doesn't fit 2844 * with any of the other prefix goop added for SSE, so we'll 2845 * special-case it here. 2846 */ 2847 if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) { 2848 rep_prefix = 0; 2849 dp = (instable_t *)&dis_opPause; 2850 } 2851 2852 /* 2853 * Some 386 instructions have 2 bytes of opcode before the mod_r/m 2854 * byte so we may need to perform a table indirection. 2855 */ 2856 if (dp->it_indirect == (instable_t *)dis_op0F) { 2857 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 2858 goto error; 2859 opcode_bytes = 2; 2860 if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) { 2861 uint_t subcode; 2862 2863 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 2864 goto error; 2865 opcode_bytes = 3; 2866 subcode = ((opcode6 & 0x3) << 1) | 2867 ((opcode7 & 0x8) >> 3); 2868 dp = (instable_t *)&dis_op0F7123[opcode5][subcode]; 2869 } else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) { 2870 dp = (instable_t *)&dis_op0FC8[0]; 2871 } else if ((opcode4 == 0x3) && (opcode5 == 0xA)) { 2872 opcode_bytes = 3; 2873 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 2874 goto error; 2875 if (opnd_size == SIZE16) 2876 opnd_size = SIZE32; 2877 2878 dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7]; 2879 #ifdef DIS_TEXT 2880 if (strcmp(dp->it_name, "INVALID") == 0) 2881 goto error; 2882 #endif 2883 switch (dp->it_adrmode) { 2884 case XMMP_66r: 2885 case XMMPRM_66r: 2886 case XMM3PM_66r: 2887 if (opnd_size_prefix == 0) { 2888 goto error; 2889 } 2890 break; 2891 case XMMP_66o: 2892 if (opnd_size_prefix == 0) { 2893 /* SSSE3 MMX instructions */ 2894 dp_mmx = *dp; 2895 dp = &dp_mmx; 2896 dp->it_adrmode = MMOPM_66o; 2897 #ifdef DIS_MEM 2898 dp->it_size = 8; 2899 #endif 2900 } 2901 break; 2902 default: 2903 goto error; 2904 } 2905 } else if ((opcode4 == 0x3) && (opcode5 == 0x8)) { 2906 opcode_bytes = 3; 2907 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 2908 goto error; 2909 dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7]; 2910 2911 /* 2912 * Both crc32 and movbe have the same 3rd opcode 2913 * byte of either 0xF0 or 0xF1, so we use another 2914 * indirection to distinguish between the two. 2915 */ 2916 if (dp->it_indirect == (instable_t *)dis_op0F38F0 || 2917 dp->it_indirect == (instable_t *)dis_op0F38F1) { 2918 2919 dp = dp->it_indirect; 2920 if (rep_prefix != 0xF2) { 2921 /* It is movbe */ 2922 dp++; 2923 } 2924 } 2925 #ifdef DIS_TEXT 2926 if (strcmp(dp->it_name, "INVALID") == 0) 2927 goto error; 2928 #endif 2929 switch (dp->it_adrmode) { 2930 case RM_66r: 2931 case XMM_66r: 2932 case XMMM_66r: 2933 if (opnd_size_prefix == 0) { 2934 goto error; 2935 } 2936 break; 2937 case XMM_66o: 2938 if (opnd_size_prefix == 0) { 2939 /* SSSE3 MMX instructions */ 2940 dp_mmx = *dp; 2941 dp = &dp_mmx; 2942 dp->it_adrmode = MM; 2943 #ifdef DIS_MEM 2944 dp->it_size = 8; 2945 #endif 2946 } 2947 break; 2948 case CRC32: 2949 if (rep_prefix != 0xF2) { 2950 goto error; 2951 } 2952 rep_prefix = 0; 2953 break; 2954 case MOVBE: 2955 if (rep_prefix != 0x0) { 2956 goto error; 2957 } 2958 break; 2959 default: 2960 goto error; 2961 } 2962 } else { 2963 dp = (instable_t *)&dis_op0F[opcode4][opcode5]; 2964 } 2965 } 2966 2967 /* 2968 * If still not at a TERM decode entry, then a ModRM byte 2969 * exists and its fields further decode the instruction. 2970 */ 2971 x->d86_got_modrm = 0; 2972 if (dp->it_indirect != TERM) { 2973 dtrace_get_modrm(x, &mode, &opcode3, &r_m); 2974 if (x->d86_error) 2975 goto error; 2976 reg = opcode3; 2977 2978 /* 2979 * decode 287 instructions (D8-DF) from opcodeN 2980 */ 2981 if (opcode1 == 0xD && opcode2 >= 0x8) { 2982 if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4) 2983 dp = (instable_t *)&dis_opFP5[r_m]; 2984 else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4) 2985 dp = (instable_t *)&dis_opFP7[opcode3]; 2986 else if (opcode2 == 0xB && mode == 0x3) 2987 dp = (instable_t *)&dis_opFP6[opcode3]; 2988 else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4) 2989 dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m]; 2990 else if (mode == 0x3) 2991 dp = (instable_t *) 2992 &dis_opFP3[opcode2 - 8][opcode3]; 2993 else 2994 dp = (instable_t *) 2995 &dis_opFP1n2[opcode2 - 8][opcode3]; 2996 } else { 2997 dp = (instable_t *)dp->it_indirect + opcode3; 2998 } 2999 } 3000 3001 /* 3002 * In amd64 bit mode, ARPL opcode is changed to MOVSXD 3003 * (sign extend 32bit to 64 bit) 3004 */ 3005 if ((vex_prefix == 0) && cpu_mode == SIZE64 && 3006 opcode1 == 0x6 && opcode2 == 0x3) 3007 dp = (instable_t *)&dis_opMOVSLD; 3008 3009 /* 3010 * at this point we should have a correct (or invalid) opcode 3011 */ 3012 if (cpu_mode == SIZE64 && dp->it_invalid64 || 3013 cpu_mode != SIZE64 && dp->it_invalid32) 3014 goto error; 3015 if (dp->it_indirect != TERM) 3016 goto error; 3017 3018 /* 3019 * deal with MMX/SSE opcodes which are changed by prefixes 3020 */ 3021 switch (dp->it_adrmode) { 3022 case MMO: 3023 case MMOIMPL: 3024 case MMO3P: 3025 case MMOM3: 3026 case MMOMS: 3027 case MMOPM: 3028 case MMOPRM: 3029 case MMOS: 3030 case XMMO: 3031 case XMMOM: 3032 case XMMOMS: 3033 case XMMOPM: 3034 case XMMOS: 3035 case XMMOMX: 3036 case XMMOX3: 3037 case XMMOXMM: 3038 /* 3039 * This is horrible. Some SIMD instructions take the 3040 * form 0x0F 0x?? ..., which is easily decoded using the 3041 * existing tables. Other SIMD instructions use various 3042 * prefix bytes to overload existing instructions. For 3043 * Example, addps is F0, 58, whereas addss is F3 (repz), 3044 * F0, 58. Presumably someone got a raise for this. 3045 * 3046 * If we see one of the instructions which can be 3047 * modified in this way (if we've got one of the SIMDO* 3048 * address modes), we'll check to see if the last prefix 3049 * was a repz. If it was, we strip the prefix from the 3050 * mnemonic, and we indirect using the dis_opSIMDrepz 3051 * table. 3052 */ 3053 3054 /* 3055 * Calculate our offset in dis_op0F 3056 */ 3057 if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F)) 3058 goto error; 3059 3060 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 3061 sizeof (instable_t); 3062 3063 /* 3064 * Rewrite if this instruction used one of the magic prefixes. 3065 */ 3066 if (rep_prefix) { 3067 if (rep_prefix == 0xf2) 3068 dp = (instable_t *)&dis_opSIMDrepnz[off]; 3069 else 3070 dp = (instable_t *)&dis_opSIMDrepz[off]; 3071 rep_prefix = 0; 3072 } else if (opnd_size_prefix) { 3073 dp = (instable_t *)&dis_opSIMDdata16[off]; 3074 opnd_size_prefix = 0; 3075 if (opnd_size == SIZE16) 3076 opnd_size = SIZE32; 3077 } 3078 break; 3079 3080 case MG9: 3081 /* 3082 * More horribleness: the group 9 (0xF0 0xC7) instructions are 3083 * allowed an optional prefix of 0x66 or 0xF3. This is similar 3084 * to the SIMD business described above, but with a different 3085 * addressing mode (and an indirect table), so we deal with it 3086 * separately (if similarly). 3087 */ 3088 3089 /* 3090 * Calculate our offset in dis_op0FC7 (the group 9 table) 3091 */ 3092 if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7)) 3093 goto error; 3094 3095 off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) / 3096 sizeof (instable_t); 3097 3098 /* 3099 * Rewrite if this instruction used one of the magic prefixes. 3100 */ 3101 if (rep_prefix) { 3102 if (rep_prefix == 0xf3) 3103 dp = (instable_t *)&dis_opF30FC7[off]; 3104 else 3105 goto error; 3106 rep_prefix = 0; 3107 } else if (opnd_size_prefix) { 3108 dp = (instable_t *)&dis_op660FC7[off]; 3109 opnd_size_prefix = 0; 3110 if (opnd_size == SIZE16) 3111 opnd_size = SIZE32; 3112 } 3113 break; 3114 3115 3116 case MMOSH: 3117 /* 3118 * As with the "normal" SIMD instructions, the MMX 3119 * shuffle instructions are overloaded. These 3120 * instructions, however, are special in that they use 3121 * an extra byte, and thus an extra table. As of this 3122 * writing, they only use the opnd_size prefix. 3123 */ 3124 3125 /* 3126 * Calculate our offset in dis_op0F7123 3127 */ 3128 if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 > 3129 sizeof (dis_op0F7123)) 3130 goto error; 3131 3132 if (opnd_size_prefix) { 3133 off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) / 3134 sizeof (instable_t); 3135 dp = (instable_t *)&dis_opSIMD7123[off]; 3136 opnd_size_prefix = 0; 3137 if (opnd_size == SIZE16) 3138 opnd_size = SIZE32; 3139 } 3140 break; 3141 case MRw: 3142 if (rep_prefix) { 3143 if (rep_prefix == 0xf3) { 3144 3145 /* 3146 * Calculate our offset in dis_op0F 3147 */ 3148 if ((uintptr_t)dp - (uintptr_t)dis_op0F 3149 > sizeof (dis_op0F)) 3150 goto error; 3151 3152 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 3153 sizeof (instable_t); 3154 3155 dp = (instable_t *)&dis_opSIMDrepz[off]; 3156 rep_prefix = 0; 3157 } else { 3158 goto error; 3159 } 3160 } 3161 break; 3162 } 3163 3164 /* 3165 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64. 3166 */ 3167 if (cpu_mode == SIZE64) 3168 if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop)) 3169 opnd_size = SIZE64; 3170 3171 #ifdef DIS_TEXT 3172 /* 3173 * At this point most instructions can format the opcode mnemonic 3174 * including the prefixes. 3175 */ 3176 if (lock_prefix) 3177 (void) strlcat(x->d86_mnem, "lock ", OPLEN); 3178 3179 if (rep_prefix == 0xf2) 3180 (void) strlcat(x->d86_mnem, "repnz ", OPLEN); 3181 else if (rep_prefix == 0xf3) 3182 (void) strlcat(x->d86_mnem, "repz ", OPLEN); 3183 3184 if (cpu_mode == SIZE64 && addr_size_prefix) 3185 (void) strlcat(x->d86_mnem, "addr32 ", OPLEN); 3186 3187 if (dp->it_adrmode != CBW && 3188 dp->it_adrmode != CWD && 3189 dp->it_adrmode != XMMSFNC) { 3190 if (strcmp(dp->it_name, "INVALID") == 0) 3191 goto error; 3192 (void) strlcat(x->d86_mnem, dp->it_name, OPLEN); 3193 if (dp->it_suffix) { 3194 char *types[] = {"", "w", "l", "q"}; 3195 if (opcode_bytes == 2 && opcode4 == 4) { 3196 /* It's a cmovx.yy. Replace the suffix x */ 3197 for (i = 5; i < OPLEN; i++) { 3198 if (x->d86_mnem[i] == '.') 3199 break; 3200 } 3201 x->d86_mnem[i - 1] = *types[opnd_size]; 3202 } else if ((opnd_size == 2) && (opcode_bytes == 3) && 3203 ((opcode6 == 1 && opcode7 == 6) || 3204 (opcode6 == 2 && opcode7 == 2))) { 3205 /* 3206 * To handle PINSRD and PEXTRD 3207 */ 3208 (void) strlcat(x->d86_mnem, "d", OPLEN); 3209 } else { 3210 (void) strlcat(x->d86_mnem, types[opnd_size], 3211 OPLEN); 3212 } 3213 } 3214 } 3215 #endif 3216 3217 /* 3218 * Process operands based on the addressing modes. 3219 */ 3220 x->d86_mode = cpu_mode; 3221 /* 3222 * In vex mode the rex_prefix has no meaning 3223 */ 3224 if (!vex_prefix) 3225 x->d86_rex_prefix = rex_prefix; 3226 x->d86_opnd_size = opnd_size; 3227 x->d86_addr_size = addr_size; 3228 vbit = 0; /* initialize for mem/reg -> reg */ 3229 switch (dp->it_adrmode) { 3230 /* 3231 * amd64 instruction to sign extend 32 bit reg/mem operands 3232 * into 64 bit register values 3233 */ 3234 case MOVSXZ: 3235 #ifdef DIS_TEXT 3236 if (rex_prefix == 0) 3237 (void) strncpy(x->d86_mnem, "movzld", OPLEN); 3238 #endif 3239 dtrace_get_modrm(x, &mode, ®, &r_m); 3240 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3241 x->d86_opnd_size = SIZE64; 3242 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3243 x->d86_opnd_size = opnd_size = SIZE32; 3244 wbit = LONG_OPND; 3245 dtrace_get_operand(x, mode, r_m, wbit, 0); 3246 break; 3247 3248 /* 3249 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF) 3250 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7) 3251 * wbit lives in 2nd byte, note that operands 3252 * are different sized 3253 */ 3254 case MOVZ: 3255 if (rex_prefix & REX_W) { 3256 /* target register size = 64 bit */ 3257 x->d86_mnem[5] = 'q'; 3258 } 3259 dtrace_get_modrm(x, &mode, ®, &r_m); 3260 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3261 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3262 x->d86_opnd_size = opnd_size = SIZE16; 3263 wbit = WBIT(opcode5); 3264 dtrace_get_operand(x, mode, r_m, wbit, 0); 3265 break; 3266 case CRC32: 3267 opnd_size = SIZE32; 3268 if (rex_prefix & REX_W) 3269 opnd_size = SIZE64; 3270 x->d86_opnd_size = opnd_size; 3271 3272 dtrace_get_modrm(x, &mode, ®, &r_m); 3273 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3274 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3275 wbit = WBIT(opcode7); 3276 if (opnd_size_prefix) 3277 x->d86_opnd_size = opnd_size = SIZE16; 3278 dtrace_get_operand(x, mode, r_m, wbit, 0); 3279 break; 3280 case MOVBE: 3281 opnd_size = SIZE32; 3282 if (rex_prefix & REX_W) 3283 opnd_size = SIZE64; 3284 x->d86_opnd_size = opnd_size; 3285 3286 dtrace_get_modrm(x, &mode, ®, &r_m); 3287 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3288 wbit = WBIT(opcode7); 3289 if (opnd_size_prefix) 3290 x->d86_opnd_size = opnd_size = SIZE16; 3291 if (wbit) { 3292 /* reg -> mem */ 3293 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 3294 dtrace_get_operand(x, mode, r_m, wbit, 1); 3295 } else { 3296 /* mem -> reg */ 3297 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3298 dtrace_get_operand(x, mode, r_m, wbit, 0); 3299 } 3300 break; 3301 3302 /* 3303 * imul instruction, with either 8-bit or longer immediate 3304 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s) 3305 */ 3306 case IMUL: 3307 wbit = LONG_OPND; 3308 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 3309 OPSIZE(opnd_size, opcode2 == 0x9), 1); 3310 break; 3311 3312 /* memory or register operand to register, with 'w' bit */ 3313 case MRw: 3314 wbit = WBIT(opcode2); 3315 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 3316 break; 3317 3318 /* register to memory or register operand, with 'w' bit */ 3319 /* arpl happens to fit here also because it is odd */ 3320 case RMw: 3321 if (opcode_bytes == 2) 3322 wbit = WBIT(opcode5); 3323 else 3324 wbit = WBIT(opcode2); 3325 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 3326 break; 3327 3328 /* xaddb instruction */ 3329 case XADDB: 3330 wbit = 0; 3331 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 3332 break; 3333 3334 /* MMX register to memory or register operand */ 3335 case MMS: 3336 case MMOS: 3337 #ifdef DIS_TEXT 3338 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 3339 #else 3340 wbit = LONG_OPND; 3341 #endif 3342 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 3343 break; 3344 3345 /* MMX register to memory */ 3346 case MMOMS: 3347 dtrace_get_modrm(x, &mode, ®, &r_m); 3348 if (mode == REG_ONLY) 3349 goto error; 3350 wbit = MM_OPND; 3351 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 3352 break; 3353 3354 /* Double shift. Has immediate operand specifying the shift. */ 3355 case DSHIFT: 3356 wbit = LONG_OPND; 3357 dtrace_get_modrm(x, &mode, ®, &r_m); 3358 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3359 dtrace_get_operand(x, mode, r_m, wbit, 2); 3360 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3361 dtrace_imm_opnd(x, wbit, 1, 0); 3362 break; 3363 3364 /* 3365 * Double shift. With no immediate operand, specifies using %cl. 3366 */ 3367 case DSHIFTcl: 3368 wbit = LONG_OPND; 3369 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 3370 break; 3371 3372 /* immediate to memory or register operand */ 3373 case IMlw: 3374 wbit = WBIT(opcode2); 3375 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3376 dtrace_get_operand(x, mode, r_m, wbit, 1); 3377 /* 3378 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83 3379 */ 3380 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0); 3381 break; 3382 3383 /* immediate to memory or register operand with the */ 3384 /* 'w' bit present */ 3385 case IMw: 3386 wbit = WBIT(opcode2); 3387 dtrace_get_modrm(x, &mode, ®, &r_m); 3388 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3389 dtrace_get_operand(x, mode, r_m, wbit, 1); 3390 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 3391 break; 3392 3393 /* immediate to register with register in low 3 bits */ 3394 /* of op code */ 3395 case IR: 3396 /* w-bit here (with regs) is bit 3 */ 3397 wbit = opcode2 >>3 & 0x1; 3398 reg = REGNO(opcode2); 3399 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 3400 mode = REG_ONLY; 3401 r_m = reg; 3402 dtrace_get_operand(x, mode, r_m, wbit, 1); 3403 dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0); 3404 break; 3405 3406 /* MMX immediate shift of register */ 3407 case MMSH: 3408 case MMOSH: 3409 wbit = MM_OPND; 3410 goto mm_shift; /* in next case */ 3411 3412 /* SIMD immediate shift of register */ 3413 case XMMSH: 3414 wbit = XMM_OPND; 3415 mm_shift: 3416 reg = REGNO(opcode7); 3417 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 3418 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 3419 dtrace_imm_opnd(x, wbit, 1, 0); 3420 NOMEM; 3421 break; 3422 3423 /* accumulator to memory operand */ 3424 case AO: 3425 vbit = 1; 3426 /*FALLTHROUGH*/ 3427 3428 /* memory operand to accumulator */ 3429 case OA: 3430 wbit = WBIT(opcode2); 3431 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit); 3432 dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit); 3433 #ifdef DIS_TEXT 3434 x->d86_opnd[vbit].d86_mode = MODE_OFFSET; 3435 #endif 3436 break; 3437 3438 3439 /* segment register to memory or register operand */ 3440 case SM: 3441 vbit = 1; 3442 /*FALLTHROUGH*/ 3443 3444 /* memory or register operand to segment register */ 3445 case MS: 3446 dtrace_get_modrm(x, &mode, ®, &r_m); 3447 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3448 dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit); 3449 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit); 3450 break; 3451 3452 /* 3453 * rotate or shift instructions, which may shift by 1 or 3454 * consult the cl register, depending on the 'v' bit 3455 */ 3456 case Mv: 3457 vbit = VBIT(opcode2); 3458 wbit = WBIT(opcode2); 3459 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3460 dtrace_get_operand(x, mode, r_m, wbit, 1); 3461 #ifdef DIS_TEXT 3462 if (vbit) { 3463 (void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN); 3464 } else { 3465 x->d86_opnd[0].d86_mode = MODE_SIGNED; 3466 x->d86_opnd[0].d86_value_size = 1; 3467 x->d86_opnd[0].d86_value = 1; 3468 } 3469 #endif 3470 break; 3471 /* 3472 * immediate rotate or shift instructions 3473 */ 3474 case MvI: 3475 wbit = WBIT(opcode2); 3476 normal_imm_mem: 3477 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3478 dtrace_get_operand(x, mode, r_m, wbit, 1); 3479 dtrace_imm_opnd(x, wbit, 1, 0); 3480 break; 3481 3482 /* bit test instructions */ 3483 case MIb: 3484 wbit = LONG_OPND; 3485 goto normal_imm_mem; 3486 3487 /* single memory or register operand with 'w' bit present */ 3488 case Mw: 3489 wbit = WBIT(opcode2); 3490 just_mem: 3491 dtrace_get_modrm(x, &mode, ®, &r_m); 3492 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3493 dtrace_get_operand(x, mode, r_m, wbit, 0); 3494 break; 3495 3496 case SWAPGS: 3497 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) { 3498 #ifdef DIS_TEXT 3499 (void) strncpy(x->d86_mnem, "swapgs", OPLEN); 3500 #endif 3501 NOMEM; 3502 break; 3503 } 3504 /*FALLTHROUGH*/ 3505 3506 /* prefetch instruction - memory operand, but no memory acess */ 3507 case PREF: 3508 NOMEM; 3509 /*FALLTHROUGH*/ 3510 3511 /* single memory or register operand */ 3512 case M: 3513 case MG9: 3514 wbit = LONG_OPND; 3515 goto just_mem; 3516 3517 /* single memory or register byte operand */ 3518 case Mb: 3519 wbit = BYTE_OPND; 3520 goto just_mem; 3521 3522 case VMx: 3523 if (mode == 3) { 3524 #ifdef DIS_TEXT 3525 char *vminstr; 3526 3527 switch (r_m) { 3528 case 1: 3529 vminstr = "vmcall"; 3530 break; 3531 case 2: 3532 vminstr = "vmlaunch"; 3533 break; 3534 case 3: 3535 vminstr = "vmresume"; 3536 break; 3537 case 4: 3538 vminstr = "vmxoff"; 3539 break; 3540 default: 3541 goto error; 3542 } 3543 3544 (void) strncpy(x->d86_mnem, vminstr, OPLEN); 3545 #else 3546 if (r_m < 1 || r_m > 4) 3547 goto error; 3548 #endif 3549 3550 NOMEM; 3551 break; 3552 } 3553 /*FALLTHROUGH*/ 3554 case SVM: 3555 if (mode == 3) { 3556 #if DIS_TEXT 3557 char *vinstr; 3558 3559 switch (r_m) { 3560 case 0: 3561 vinstr = "vmrun"; 3562 break; 3563 case 1: 3564 vinstr = "vmmcall"; 3565 break; 3566 case 2: 3567 vinstr = "vmload"; 3568 break; 3569 case 3: 3570 vinstr = "vmsave"; 3571 break; 3572 case 4: 3573 vinstr = "stgi"; 3574 break; 3575 case 5: 3576 vinstr = "clgi"; 3577 break; 3578 case 6: 3579 vinstr = "skinit"; 3580 break; 3581 case 7: 3582 vinstr = "invlpga"; 3583 break; 3584 } 3585 3586 (void) strncpy(x->d86_mnem, vinstr, OPLEN); 3587 #endif 3588 NOMEM; 3589 break; 3590 } 3591 /*FALLTHROUGH*/ 3592 case MONITOR_MWAIT: 3593 if (mode == 3) { 3594 if (r_m == 0) { 3595 #ifdef DIS_TEXT 3596 (void) strncpy(x->d86_mnem, "monitor", OPLEN); 3597 #endif 3598 NOMEM; 3599 break; 3600 } else if (r_m == 1) { 3601 #ifdef DIS_TEXT 3602 (void) strncpy(x->d86_mnem, "mwait", OPLEN); 3603 #endif 3604 NOMEM; 3605 break; 3606 } else { 3607 goto error; 3608 } 3609 } 3610 /*FALLTHROUGH*/ 3611 case XGETBV_XSETBV: 3612 if (mode == 3) { 3613 if (r_m == 0) { 3614 #ifdef DIS_TEXT 3615 (void) strncpy(x->d86_mnem, "xgetbv", OPLEN); 3616 #endif 3617 NOMEM; 3618 break; 3619 } else if (r_m == 1) { 3620 #ifdef DIS_TEXT 3621 (void) strncpy(x->d86_mnem, "xsetbv", OPLEN); 3622 #endif 3623 NOMEM; 3624 break; 3625 } else { 3626 goto error; 3627 } 3628 3629 } 3630 /*FALLTHROUGH*/ 3631 case MO: 3632 /* Similar to M, but only memory (no direct registers) */ 3633 wbit = LONG_OPND; 3634 dtrace_get_modrm(x, &mode, ®, &r_m); 3635 if (mode == 3) 3636 goto error; 3637 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3638 dtrace_get_operand(x, mode, r_m, wbit, 0); 3639 break; 3640 3641 /* move special register to register or reverse if vbit */ 3642 case SREG: 3643 switch (opcode5) { 3644 3645 case 2: 3646 vbit = 1; 3647 /*FALLTHROUGH*/ 3648 case 0: 3649 wbit = CONTROL_OPND; 3650 break; 3651 3652 case 3: 3653 vbit = 1; 3654 /*FALLTHROUGH*/ 3655 case 1: 3656 wbit = DEBUG_OPND; 3657 break; 3658 3659 case 6: 3660 vbit = 1; 3661 /*FALLTHROUGH*/ 3662 case 4: 3663 wbit = TEST_OPND; 3664 break; 3665 3666 } 3667 dtrace_get_modrm(x, &mode, ®, &r_m); 3668 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3669 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit); 3670 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit); 3671 NOMEM; 3672 break; 3673 3674 /* 3675 * single register operand with register in the low 3 3676 * bits of op code 3677 */ 3678 case R: 3679 if (opcode_bytes == 2) 3680 reg = REGNO(opcode5); 3681 else 3682 reg = REGNO(opcode2); 3683 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 3684 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 3685 NOMEM; 3686 break; 3687 3688 /* 3689 * register to accumulator with register in the low 3 3690 * bits of op code, xchg instructions 3691 */ 3692 case RA: 3693 NOMEM; 3694 reg = REGNO(opcode2); 3695 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 3696 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 3697 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1); 3698 break; 3699 3700 /* 3701 * single segment register operand, with register in 3702 * bits 3-4 of op code byte 3703 */ 3704 case SEG: 3705 NOMEM; 3706 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3; 3707 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 3708 break; 3709 3710 /* 3711 * single segment register operand, with register in 3712 * bits 3-5 of op code 3713 */ 3714 case LSEG: 3715 NOMEM; 3716 /* long seg reg from opcode */ 3717 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7; 3718 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 3719 break; 3720 3721 /* memory or register operand to register */ 3722 case MR: 3723 if (vex_prefetch) 3724 x->d86_got_modrm = 1; 3725 wbit = LONG_OPND; 3726 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 3727 break; 3728 3729 case RM: 3730 case RM_66r: 3731 wbit = LONG_OPND; 3732 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 3733 break; 3734 3735 /* MMX/SIMD-Int memory or mm reg to mm reg */ 3736 case MM: 3737 case MMO: 3738 #ifdef DIS_TEXT 3739 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 3740 #else 3741 wbit = LONG_OPND; 3742 #endif 3743 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 3744 break; 3745 3746 case MMOIMPL: 3747 #ifdef DIS_TEXT 3748 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 3749 #else 3750 wbit = LONG_OPND; 3751 #endif 3752 dtrace_get_modrm(x, &mode, ®, &r_m); 3753 if (mode != REG_ONLY) 3754 goto error; 3755 3756 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3757 dtrace_get_operand(x, mode, r_m, wbit, 0); 3758 dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1); 3759 mode = 0; /* change for memory access size... */ 3760 break; 3761 3762 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */ 3763 case MMO3P: 3764 wbit = MM_OPND; 3765 goto xmm3p; 3766 case XMM3P: 3767 wbit = XMM_OPND; 3768 xmm3p: 3769 dtrace_get_modrm(x, &mode, ®, &r_m); 3770 if (mode != REG_ONLY) 3771 goto error; 3772 3773 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1, 3774 1); 3775 NOMEM; 3776 break; 3777 3778 case XMM3PM_66r: 3779 THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND, 3780 1, 0); 3781 break; 3782 3783 /* MMX/SIMD-Int predicated r32/mem to mm reg */ 3784 case MMOPRM: 3785 wbit = LONG_OPND; 3786 w2 = MM_OPND; 3787 goto xmmprm; 3788 case XMMPRM: 3789 case XMMPRM_66r: 3790 wbit = LONG_OPND; 3791 w2 = XMM_OPND; 3792 xmmprm: 3793 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1); 3794 break; 3795 3796 /* MMX/SIMD-Int predicated mm/mem to mm reg */ 3797 case MMOPM: 3798 case MMOPM_66o: 3799 wbit = w2 = MM_OPND; 3800 goto xmmprm; 3801 3802 /* MMX/SIMD-Int mm reg to r32 */ 3803 case MMOM3: 3804 NOMEM; 3805 dtrace_get_modrm(x, &mode, ®, &r_m); 3806 if (mode != REG_ONLY) 3807 goto error; 3808 wbit = MM_OPND; 3809 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 3810 break; 3811 3812 /* SIMD memory or xmm reg operand to xmm reg */ 3813 case XMM: 3814 case XMM_66o: 3815 case XMM_66r: 3816 case XMMO: 3817 case XMMXIMPL: 3818 wbit = XMM_OPND; 3819 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 3820 3821 if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY) 3822 goto error; 3823 3824 #ifdef DIS_TEXT 3825 /* 3826 * movlps and movhlps share opcodes. They differ in the 3827 * addressing modes allowed for their operands. 3828 * movhps and movlhps behave similarly. 3829 */ 3830 if (mode == REG_ONLY) { 3831 if (strcmp(dp->it_name, "movlps") == 0) 3832 (void) strncpy(x->d86_mnem, "movhlps", OPLEN); 3833 else if (strcmp(dp->it_name, "movhps") == 0) 3834 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 3835 } 3836 #endif 3837 if (dp->it_adrmode == XMMXIMPL) 3838 mode = 0; /* change for memory access size... */ 3839 break; 3840 3841 /* SIMD xmm reg to memory or xmm reg */ 3842 case XMMS: 3843 case XMMOS: 3844 case XMMMS: 3845 case XMMOMS: 3846 dtrace_get_modrm(x, &mode, ®, &r_m); 3847 #ifdef DIS_TEXT 3848 if ((strcmp(dp->it_name, "movlps") == 0 || 3849 strcmp(dp->it_name, "movhps") == 0 || 3850 strcmp(dp->it_name, "movntps") == 0) && 3851 mode == REG_ONLY) 3852 goto error; 3853 #endif 3854 wbit = XMM_OPND; 3855 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 3856 break; 3857 3858 /* SIMD memory to xmm reg */ 3859 case XMMM: 3860 case XMMM_66r: 3861 case XMMOM: 3862 wbit = XMM_OPND; 3863 dtrace_get_modrm(x, &mode, ®, &r_m); 3864 #ifdef DIS_TEXT 3865 if (mode == REG_ONLY) { 3866 if (strcmp(dp->it_name, "movhps") == 0) 3867 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 3868 else 3869 goto error; 3870 } 3871 #endif 3872 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 3873 break; 3874 3875 /* SIMD memory or r32 to xmm reg */ 3876 case XMM3MX: 3877 wbit = LONG_OPND; 3878 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 3879 break; 3880 3881 case XMM3MXS: 3882 wbit = LONG_OPND; 3883 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 3884 break; 3885 3886 /* SIMD memory or mm reg to xmm reg */ 3887 case XMMOMX: 3888 /* SIMD mm to xmm */ 3889 case XMMMX: 3890 wbit = MM_OPND; 3891 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 3892 break; 3893 3894 /* SIMD memory or xmm reg to mm reg */ 3895 case XMMXMM: 3896 case XMMOXMM: 3897 case XMMXM: 3898 wbit = XMM_OPND; 3899 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 3900 break; 3901 3902 3903 /* SIMD memory or xmm reg to r32 */ 3904 case XMMXM3: 3905 wbit = XMM_OPND; 3906 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 3907 break; 3908 3909 /* SIMD xmm to r32 */ 3910 case XMMX3: 3911 case XMMOX3: 3912 dtrace_get_modrm(x, &mode, ®, &r_m); 3913 if (mode != REG_ONLY) 3914 goto error; 3915 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3916 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 3917 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3918 NOMEM; 3919 break; 3920 3921 /* SIMD predicated memory or xmm reg with/to xmm reg */ 3922 case XMMP: 3923 case XMMP_66r: 3924 case XMMP_66o: 3925 case XMMOPM: 3926 wbit = XMM_OPND; 3927 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1, 3928 1); 3929 3930 #ifdef DIS_TEXT 3931 /* 3932 * cmpps and cmpss vary their instruction name based 3933 * on the value of imm8. Other XMMP instructions, 3934 * such as shufps, require explicit specification of 3935 * the predicate. 3936 */ 3937 if (dp->it_name[0] == 'c' && 3938 dp->it_name[1] == 'm' && 3939 dp->it_name[2] == 'p' && 3940 strlen(dp->it_name) == 5) { 3941 uchar_t pred = x->d86_opnd[0].d86_value & 0xff; 3942 3943 if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *))) 3944 goto error; 3945 3946 (void) strncpy(x->d86_mnem, "cmp", OPLEN); 3947 (void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred], 3948 OPLEN); 3949 (void) strlcat(x->d86_mnem, 3950 dp->it_name + strlen(dp->it_name) - 2, 3951 OPLEN); 3952 x->d86_opnd[0] = x->d86_opnd[1]; 3953 x->d86_opnd[1] = x->d86_opnd[2]; 3954 x->d86_numopnds = 2; 3955 } 3956 #endif 3957 break; 3958 3959 case XMMX2I: 3960 FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND, 3961 1); 3962 NOMEM; 3963 break; 3964 3965 case XMM2I: 3966 ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1); 3967 NOMEM; 3968 break; 3969 3970 /* immediate operand to accumulator */ 3971 case IA: 3972 wbit = WBIT(opcode2); 3973 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 3974 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 3975 NOMEM; 3976 break; 3977 3978 /* memory or register operand to accumulator */ 3979 case MA: 3980 wbit = WBIT(opcode2); 3981 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3982 dtrace_get_operand(x, mode, r_m, wbit, 0); 3983 break; 3984 3985 /* si register to di register used to reference memory */ 3986 case SD: 3987 #ifdef DIS_TEXT 3988 dtrace_check_override(x, 0); 3989 x->d86_numopnds = 2; 3990 if (addr_size == SIZE64) { 3991 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 3992 OPLEN); 3993 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 3994 OPLEN); 3995 } else if (addr_size == SIZE32) { 3996 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 3997 OPLEN); 3998 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 3999 OPLEN); 4000 } else { 4001 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 4002 OPLEN); 4003 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 4004 OPLEN); 4005 } 4006 #endif 4007 wbit = LONG_OPND; 4008 break; 4009 4010 /* accumulator to di register */ 4011 case AD: 4012 wbit = WBIT(opcode2); 4013 #ifdef DIS_TEXT 4014 dtrace_check_override(x, 1); 4015 x->d86_numopnds = 2; 4016 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0); 4017 if (addr_size == SIZE64) 4018 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 4019 OPLEN); 4020 else if (addr_size == SIZE32) 4021 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 4022 OPLEN); 4023 else 4024 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 4025 OPLEN); 4026 #endif 4027 break; 4028 4029 /* si register to accumulator */ 4030 case SA: 4031 wbit = WBIT(opcode2); 4032 #ifdef DIS_TEXT 4033 dtrace_check_override(x, 0); 4034 x->d86_numopnds = 2; 4035 if (addr_size == SIZE64) 4036 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 4037 OPLEN); 4038 else if (addr_size == SIZE32) 4039 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 4040 OPLEN); 4041 else 4042 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 4043 OPLEN); 4044 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 4045 #endif 4046 break; 4047 4048 /* 4049 * single operand, a 16/32 bit displacement 4050 */ 4051 case D: 4052 wbit = LONG_OPND; 4053 dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 4054 NOMEM; 4055 break; 4056 4057 /* jmp/call indirect to memory or register operand */ 4058 case INM: 4059 #ifdef DIS_TEXT 4060 (void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN); 4061 #endif 4062 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4063 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 4064 wbit = LONG_OPND; 4065 break; 4066 4067 /* 4068 * for long jumps and long calls -- a new code segment 4069 * register and an offset in IP -- stored in object 4070 * code in reverse order. Note - not valid in amd64 4071 */ 4072 case SO: 4073 dtrace_check_override(x, 1); 4074 wbit = LONG_OPND; 4075 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1); 4076 #ifdef DIS_TEXT 4077 x->d86_opnd[1].d86_mode = MODE_SIGNED; 4078 #endif 4079 /* will now get segment operand */ 4080 dtrace_imm_opnd(x, wbit, 2, 0); 4081 break; 4082 4083 /* 4084 * jmp/call. single operand, 8 bit displacement. 4085 * added to current EIP in 'compofff' 4086 */ 4087 case BD: 4088 dtrace_disp_opnd(x, BYTE_OPND, 1, 0); 4089 NOMEM; 4090 break; 4091 4092 /* single 32/16 bit immediate operand */ 4093 case I: 4094 wbit = LONG_OPND; 4095 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 4096 break; 4097 4098 /* single 8 bit immediate operand */ 4099 case Ib: 4100 wbit = LONG_OPND; 4101 dtrace_imm_opnd(x, wbit, 1, 0); 4102 break; 4103 4104 case ENTER: 4105 wbit = LONG_OPND; 4106 dtrace_imm_opnd(x, wbit, 2, 0); 4107 dtrace_imm_opnd(x, wbit, 1, 1); 4108 switch (opnd_size) { 4109 case SIZE64: 4110 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8; 4111 break; 4112 case SIZE32: 4113 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4; 4114 break; 4115 case SIZE16: 4116 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2; 4117 break; 4118 } 4119 4120 break; 4121 4122 /* 16-bit immediate operand */ 4123 case RET: 4124 wbit = LONG_OPND; 4125 dtrace_imm_opnd(x, wbit, 2, 0); 4126 break; 4127 4128 /* single 8 bit port operand */ 4129 case P: 4130 dtrace_check_override(x, 0); 4131 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 4132 NOMEM; 4133 break; 4134 4135 /* single operand, dx register (variable port instruction) */ 4136 case V: 4137 x->d86_numopnds = 1; 4138 dtrace_check_override(x, 0); 4139 #ifdef DIS_TEXT 4140 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN); 4141 #endif 4142 NOMEM; 4143 break; 4144 4145 /* 4146 * The int instruction, which has two forms: 4147 * int 3 (breakpoint) or 4148 * int n, where n is indicated in the subsequent 4149 * byte (format Ib). The int 3 instruction (opcode 0xCC), 4150 * where, although the 3 looks like an operand, 4151 * it is implied by the opcode. It must be converted 4152 * to the correct base and output. 4153 */ 4154 case INT3: 4155 #ifdef DIS_TEXT 4156 x->d86_numopnds = 1; 4157 x->d86_opnd[0].d86_mode = MODE_SIGNED; 4158 x->d86_opnd[0].d86_value_size = 1; 4159 x->d86_opnd[0].d86_value = 3; 4160 #endif 4161 NOMEM; 4162 break; 4163 4164 /* single 8 bit immediate operand */ 4165 case INTx: 4166 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 4167 NOMEM; 4168 break; 4169 4170 /* an unused byte must be discarded */ 4171 case U: 4172 if (x->d86_get_byte(x->d86_data) < 0) 4173 goto error; 4174 x->d86_len++; 4175 NOMEM; 4176 break; 4177 4178 case CBW: 4179 #ifdef DIS_TEXT 4180 if (opnd_size == SIZE16) 4181 (void) strlcat(x->d86_mnem, "cbtw", OPLEN); 4182 else if (opnd_size == SIZE32) 4183 (void) strlcat(x->d86_mnem, "cwtl", OPLEN); 4184 else 4185 (void) strlcat(x->d86_mnem, "cltq", OPLEN); 4186 #endif 4187 wbit = LONG_OPND; 4188 NOMEM; 4189 break; 4190 4191 case CWD: 4192 #ifdef DIS_TEXT 4193 if (opnd_size == SIZE16) 4194 (void) strlcat(x->d86_mnem, "cwtd", OPLEN); 4195 else if (opnd_size == SIZE32) 4196 (void) strlcat(x->d86_mnem, "cltd", OPLEN); 4197 else 4198 (void) strlcat(x->d86_mnem, "cqtd", OPLEN); 4199 #endif 4200 wbit = LONG_OPND; 4201 NOMEM; 4202 break; 4203 4204 case XMMSFNC: 4205 /* 4206 * sfence is sfence if mode is REG_ONLY. If mode isn't 4207 * REG_ONLY, mnemonic should be 'clflush'. 4208 */ 4209 dtrace_get_modrm(x, &mode, ®, &r_m); 4210 4211 /* sfence doesn't take operands */ 4212 #ifdef DIS_TEXT 4213 if (mode == REG_ONLY) { 4214 (void) strlcat(x->d86_mnem, "sfence", OPLEN); 4215 } else { 4216 (void) strlcat(x->d86_mnem, "clflush", OPLEN); 4217 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4218 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 4219 NOMEM; 4220 } 4221 #else 4222 if (mode != REG_ONLY) { 4223 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4224 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 4225 NOMEM; 4226 } 4227 #endif 4228 break; 4229 4230 /* 4231 * no disassembly, the mnemonic was all there was so go on 4232 */ 4233 case NORM: 4234 if (dp->it_invalid32 && cpu_mode != SIZE64) 4235 goto error; 4236 NOMEM; 4237 /*FALLTHROUGH*/ 4238 case IMPLMEM: 4239 break; 4240 4241 case XMMFENCE: 4242 /* 4243 * XRSTOR and LFENCE share the same opcode but differ in mode 4244 */ 4245 dtrace_get_modrm(x, &mode, ®, &r_m); 4246 4247 if (mode == REG_ONLY) { 4248 /* 4249 * Only the following exact byte sequences are allowed: 4250 * 4251 * 0f ae e8 lfence 4252 * 0f ae f0 mfence 4253 */ 4254 if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 && 4255 (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0) 4256 goto error; 4257 } else { 4258 #ifdef DIS_TEXT 4259 (void) strncpy(x->d86_mnem, "xrstor", OPLEN); 4260 #endif 4261 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4262 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 4263 } 4264 break; 4265 4266 /* float reg */ 4267 case F: 4268 #ifdef DIS_TEXT 4269 x->d86_numopnds = 1; 4270 (void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN); 4271 x->d86_opnd[0].d86_opnd[4] = r_m + '0'; 4272 #endif 4273 NOMEM; 4274 break; 4275 4276 /* float reg to float reg, with ret bit present */ 4277 case FF: 4278 vbit = opcode2 >> 2 & 0x1; /* vbit = 1: st -> st(i) */ 4279 /*FALLTHROUGH*/ 4280 case FFC: /* case for vbit always = 0 */ 4281 #ifdef DIS_TEXT 4282 x->d86_numopnds = 2; 4283 (void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN); 4284 (void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN); 4285 x->d86_opnd[vbit].d86_opnd[4] = r_m + '0'; 4286 #endif 4287 NOMEM; 4288 break; 4289 4290 /* AVX instructions */ 4291 case VEX_MO: 4292 /* op(ModR/M.r/m) */ 4293 x->d86_numopnds = 1; 4294 dtrace_get_modrm(x, &mode, ®, &r_m); 4295 #ifdef DIS_TEXT 4296 if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3)) 4297 (void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN); 4298 #endif 4299 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4300 dtrace_get_operand(x, mode, r_m, wbit, 0); 4301 break; 4302 case VEX_RMrX: 4303 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */ 4304 x->d86_numopnds = 3; 4305 dtrace_get_modrm(x, &mode, ®, &r_m); 4306 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4307 4308 if (mode != REG_ONLY) { 4309 if ((dp == &dis_opAVXF20F[0x10]) || 4310 (dp == &dis_opAVXF30F[0x10])) { 4311 /* vmovsd <m64>, <xmm> */ 4312 /* or vmovss <m64>, <xmm> */ 4313 x->d86_numopnds = 2; 4314 goto L_VEX_MX; 4315 } 4316 } 4317 4318 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 4319 /* 4320 * VEX prefix uses the 1's complement form to encode the 4321 * XMM/YMM regs 4322 */ 4323 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 4324 4325 if ((dp == &dis_opAVXF20F[0x2A]) || 4326 (dp == &dis_opAVXF30F[0x2A])) { 4327 /* 4328 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>, 4329 * <xmm>, <xmm> 4330 */ 4331 wbit = LONG_OPND; 4332 } 4333 #ifdef DIS_TEXT 4334 else if ((mode == REG_ONLY) && 4335 (dp == &dis_opAVX0F[0x1][0x6])) { /* vmovlhps */ 4336 (void) strncpy(x->d86_mnem, "vmovlhps", OPLEN); 4337 } else if ((mode == REG_ONLY) && 4338 (dp == &dis_opAVX0F[0x1][0x2])) { /* vmovhlps */ 4339 (void) strncpy(x->d86_mnem, "vmovhlps", OPLEN); 4340 } 4341 #endif 4342 dtrace_get_operand(x, mode, r_m, wbit, 0); 4343 4344 break; 4345 4346 case VEX_RRX: 4347 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 4348 x->d86_numopnds = 3; 4349 4350 dtrace_get_modrm(x, &mode, ®, &r_m); 4351 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4352 4353 if (mode != REG_ONLY) { 4354 if ((dp == &dis_opAVXF20F[0x11]) || 4355 (dp == &dis_opAVXF30F[0x11])) { 4356 /* vmovsd <xmm>, <m64> */ 4357 /* or vmovss <xmm>, <m64> */ 4358 x->d86_numopnds = 2; 4359 goto L_VEX_RM; 4360 } 4361 } 4362 4363 dtrace_get_operand(x, mode, r_m, wbit, 2); 4364 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 4365 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 4366 break; 4367 4368 case VEX_RMRX: 4369 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */ 4370 x->d86_numopnds = 4; 4371 4372 dtrace_get_modrm(x, &mode, ®, &r_m); 4373 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4374 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3); 4375 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 4376 if (dp == &dis_opAVX660F3A[0x18]) { 4377 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */ 4378 dtrace_get_operand(x, mode, r_m, XMM_OPND, 1); 4379 } else if ((dp == &dis_opAVX660F3A[0x20]) || 4380 (dp == & dis_opAVX660F[0xC4])) { 4381 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */ 4382 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */ 4383 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 4384 } else if (dp == &dis_opAVX660F3A[0x22]) { 4385 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */ 4386 #ifdef DIS_TEXT 4387 if (vex_W) 4388 x->d86_mnem[6] = 'q'; 4389 #endif 4390 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 4391 } else { 4392 dtrace_get_operand(x, mode, r_m, wbit, 1); 4393 } 4394 4395 /* one byte immediate number */ 4396 dtrace_imm_opnd(x, wbit, 1, 0); 4397 4398 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */ 4399 if ((dp == &dis_opAVX660F3A[0x4A]) || 4400 (dp == &dis_opAVX660F3A[0x4B]) || 4401 (dp == &dis_opAVX660F3A[0x4C])) { 4402 #ifdef DIS_TEXT 4403 int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4; 4404 #endif 4405 x->d86_opnd[0].d86_mode = MODE_NONE; 4406 #ifdef DIS_TEXT 4407 if (vex_L) 4408 (void) strncpy(x->d86_opnd[0].d86_opnd, 4409 dis_YMMREG[regnum], OPLEN); 4410 else 4411 (void) strncpy(x->d86_opnd[0].d86_opnd, 4412 dis_XMMREG[regnum], OPLEN); 4413 #endif 4414 } 4415 break; 4416 4417 case VEX_MX: 4418 /* ModR/M.reg := op(ModR/M.rm) */ 4419 x->d86_numopnds = 2; 4420 4421 dtrace_get_modrm(x, &mode, ®, &r_m); 4422 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4423 L_VEX_MX: 4424 4425 if ((dp == &dis_opAVXF20F[0xE6]) || 4426 (dp == &dis_opAVX660F[0x5A]) || 4427 (dp == &dis_opAVX660F[0xE6])) { 4428 /* vcvtpd2dq <ymm>, <xmm> */ 4429 /* or vcvtpd2ps <ymm>, <xmm> */ 4430 /* or vcvttpd2dq <ymm>, <xmm> */ 4431 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1); 4432 dtrace_get_operand(x, mode, r_m, wbit, 0); 4433 } else if ((dp == &dis_opAVXF30F[0xE6]) || 4434 (dp == &dis_opAVX0F[0x5][0xA])) { 4435 /* vcvtdq2pd <xmm>, <ymm> */ 4436 /* or vcvtps2pd <xmm>, <ymm> */ 4437 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4438 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 4439 } else if (dp == &dis_opAVX660F[0x6E]) { 4440 /* vmovd/q <reg/mem 32/64>, <xmm> */ 4441 #ifdef DIS_TEXT 4442 if (vex_W) 4443 x->d86_mnem[4] = 'q'; 4444 #endif 4445 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4446 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 4447 } else { 4448 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4449 dtrace_get_operand(x, mode, r_m, wbit, 0); 4450 } 4451 4452 break; 4453 4454 case VEX_MXI: 4455 /* ModR/M.reg := op(ModR/M.rm, imm8) */ 4456 x->d86_numopnds = 3; 4457 4458 dtrace_get_modrm(x, &mode, ®, &r_m); 4459 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4460 4461 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 4462 dtrace_get_operand(x, mode, r_m, wbit, 1); 4463 4464 /* one byte immediate number */ 4465 dtrace_imm_opnd(x, wbit, 1, 0); 4466 break; 4467 4468 case VEX_XXI: 4469 /* VEX.vvvv := op(ModR/M.rm, imm8) */ 4470 x->d86_numopnds = 3; 4471 4472 dtrace_get_modrm(x, &mode, ®, &r_m); 4473 #ifdef DIS_TEXT 4474 (void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg], 4475 OPLEN); 4476 #endif 4477 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4478 4479 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 4480 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1); 4481 4482 /* one byte immediate number */ 4483 dtrace_imm_opnd(x, wbit, 1, 0); 4484 break; 4485 4486 case VEX_MR: 4487 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */ 4488 if (dp == &dis_opAVX660F[0xC5]) { 4489 /* vpextrw <imm8>, <xmm>, <reg> */ 4490 x->d86_numopnds = 2; 4491 vbit = 2; 4492 } else { 4493 x->d86_numopnds = 2; 4494 vbit = 1; 4495 } 4496 4497 dtrace_get_modrm(x, &mode, ®, &r_m); 4498 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4499 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit); 4500 dtrace_get_operand(x, mode, r_m, wbit, vbit - 1); 4501 4502 if (vbit == 2) 4503 dtrace_imm_opnd(x, wbit, 1, 0); 4504 4505 break; 4506 4507 case VEX_RRI: 4508 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */ 4509 x->d86_numopnds = 2; 4510 4511 dtrace_get_modrm(x, &mode, ®, &r_m); 4512 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4513 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4514 dtrace_get_operand(x, mode, r_m, wbit, 0); 4515 break; 4516 4517 case VEX_RX: 4518 /* ModR/M.rm := op(ModR/M.reg) */ 4519 if (dp == &dis_opAVX660F3A[0x19]) { /* vextractf128 */ 4520 x->d86_numopnds = 3; 4521 4522 dtrace_get_modrm(x, &mode, ®, &r_m); 4523 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4524 4525 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 4526 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4527 4528 /* one byte immediate number */ 4529 dtrace_imm_opnd(x, wbit, 1, 0); 4530 break; 4531 } 4532 4533 x->d86_numopnds = 2; 4534 4535 dtrace_get_modrm(x, &mode, ®, &r_m); 4536 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4537 dtrace_get_operand(x, mode, r_m, wbit, 1); 4538 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 4539 break; 4540 4541 case VEX_RR: 4542 /* ModR/M.rm := op(ModR/M.reg) */ 4543 x->d86_numopnds = 2; 4544 4545 dtrace_get_modrm(x, &mode, ®, &r_m); 4546 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4547 4548 if (dp == &dis_opAVX660F[0x7E]) { 4549 /* vmovd/q <reg/mem 32/64>, <xmm> */ 4550 #ifdef DIS_TEXT 4551 if (vex_W) 4552 x->d86_mnem[4] = 'q'; 4553 #endif 4554 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 4555 } else 4556 dtrace_get_operand(x, mode, r_m, wbit, 1); 4557 4558 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 4559 break; 4560 4561 case VEX_RRi: 4562 /* ModR/M.rm := op(ModR/M.reg, imm) */ 4563 x->d86_numopnds = 3; 4564 4565 dtrace_get_modrm(x, &mode, ®, &r_m); 4566 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4567 4568 #ifdef DIS_TEXT 4569 if (dp == &dis_opAVX660F3A[0x16]) { 4570 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */ 4571 if (vex_W) 4572 x->d86_mnem[6] = 'q'; 4573 } 4574 #endif 4575 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 4576 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4577 4578 /* one byte immediate number */ 4579 dtrace_imm_opnd(x, wbit, 1, 0); 4580 break; 4581 4582 case VEX_RM: 4583 /* ModR/M.rm := op(ModR/M.reg) */ 4584 if (dp == &dis_opAVX660F3A[0x17]) { /* vextractps */ 4585 x->d86_numopnds = 3; 4586 4587 dtrace_get_modrm(x, &mode, ®, &r_m); 4588 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4589 4590 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 4591 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4592 /* one byte immediate number */ 4593 dtrace_imm_opnd(x, wbit, 1, 0); 4594 break; 4595 } 4596 x->d86_numopnds = 2; 4597 4598 dtrace_get_modrm(x, &mode, ®, &r_m); 4599 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4600 L_VEX_RM: 4601 vbit = 1; 4602 dtrace_get_operand(x, mode, r_m, wbit, vbit); 4603 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1); 4604 4605 break; 4606 4607 case VEX_RRM: 4608 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 4609 x->d86_numopnds = 3; 4610 4611 dtrace_get_modrm(x, &mode, ®, &r_m); 4612 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4613 dtrace_get_operand(x, mode, r_m, wbit, 2); 4614 /* VEX use the 1's complement form encode the XMM/YMM regs */ 4615 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 4616 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 4617 break; 4618 4619 case VEX_RMX: 4620 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */ 4621 x->d86_numopnds = 3; 4622 4623 dtrace_get_modrm(x, &mode, ®, &r_m); 4624 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4625 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 4626 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 4627 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0); 4628 break; 4629 4630 case VEX_NONE: 4631 #ifdef DIS_TEXT 4632 if (vex_L) 4633 (void) strncpy(x->d86_mnem, "vzeroall", OPLEN); 4634 #endif 4635 break; 4636 /* an invalid op code */ 4637 case AM: 4638 case DM: 4639 case OVERRIDE: 4640 case PREFIX: 4641 case UNKNOWN: 4642 NOMEM; 4643 default: 4644 goto error; 4645 } /* end switch */ 4646 if (x->d86_error) 4647 goto error; 4648 4649 done: 4650 #ifdef DIS_MEM 4651 /* 4652 * compute the size of any memory accessed by the instruction 4653 */ 4654 if (x->d86_memsize != 0) { 4655 return (0); 4656 } else if (dp->it_stackop) { 4657 switch (opnd_size) { 4658 case SIZE16: 4659 x->d86_memsize = 2; 4660 break; 4661 case SIZE32: 4662 x->d86_memsize = 4; 4663 break; 4664 case SIZE64: 4665 x->d86_memsize = 8; 4666 break; 4667 } 4668 } else if (nomem || mode == REG_ONLY) { 4669 x->d86_memsize = 0; 4670 4671 } else if (dp->it_size != 0) { 4672 /* 4673 * In 64 bit mode descriptor table entries 4674 * go up to 10 bytes and popf/pushf are always 8 bytes 4675 */ 4676 if (x->d86_mode == SIZE64 && dp->it_size == 6) 4677 x->d86_memsize = 10; 4678 else if (x->d86_mode == SIZE64 && opcode1 == 0x9 && 4679 (opcode2 == 0xc || opcode2 == 0xd)) 4680 x->d86_memsize = 8; 4681 else 4682 x->d86_memsize = dp->it_size; 4683 4684 } else if (wbit == 0) { 4685 x->d86_memsize = 1; 4686 4687 } else if (wbit == LONG_OPND) { 4688 if (opnd_size == SIZE64) 4689 x->d86_memsize = 8; 4690 else if (opnd_size == SIZE32) 4691 x->d86_memsize = 4; 4692 else 4693 x->d86_memsize = 2; 4694 4695 } else if (wbit == SEG_OPND) { 4696 x->d86_memsize = 4; 4697 4698 } else { 4699 x->d86_memsize = 8; 4700 } 4701 #endif 4702 return (0); 4703 4704 error: 4705 #ifdef DIS_TEXT 4706 (void) strlcat(x->d86_mnem, "undef", OPLEN); 4707 #endif 4708 return (1); 4709 } 4710 4711 #ifdef DIS_TEXT 4712 4713 /* 4714 * Some instructions should have immediate operands printed 4715 * as unsigned integers. We compare against this table. 4716 */ 4717 static char *unsigned_ops[] = { 4718 "or", "and", "xor", "test", "in", "out", "lcall", "ljmp", 4719 "rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl", 4720 0 4721 }; 4722 4723 4724 static int 4725 isunsigned_op(char *opcode) 4726 { 4727 char *where; 4728 int i; 4729 int is_unsigned = 0; 4730 4731 /* 4732 * Work back to start of last mnemonic, since we may have 4733 * prefixes on some opcodes. 4734 */ 4735 where = opcode + strlen(opcode) - 1; 4736 while (where > opcode && *where != ' ') 4737 --where; 4738 if (*where == ' ') 4739 ++where; 4740 4741 for (i = 0; unsigned_ops[i]; ++i) { 4742 if (strncmp(where, unsigned_ops[i], 4743 strlen(unsigned_ops[i]))) 4744 continue; 4745 is_unsigned = 1; 4746 break; 4747 } 4748 return (is_unsigned); 4749 } 4750 4751 /* 4752 * Print a numeric immediate into end of buf, maximum length buflen. 4753 * The immediate may be an address or a displacement. Mask is set 4754 * for address size. If the immediate is a "small negative", or 4755 * if it's a negative displacement of any magnitude, print as -<absval>. 4756 * Respect the "octal" flag. "Small negative" is defined as "in the 4757 * interval [NEG_LIMIT, 0)". 4758 * 4759 * Also, "isunsigned_op()" instructions never print negatives. 4760 * 4761 * Return whether we decided to print a negative value or not. 4762 */ 4763 4764 #define NEG_LIMIT -255 4765 enum {IMM, DISP}; 4766 enum {POS, TRY_NEG}; 4767 4768 static int 4769 print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf, 4770 size_t buflen, int disp, int try_neg) 4771 { 4772 int curlen; 4773 int64_t sv = (int64_t)usv; 4774 int octal = dis->d86_flags & DIS_F_OCTAL; 4775 4776 curlen = strlen(buf); 4777 4778 if (try_neg == TRY_NEG && sv < 0 && 4779 (disp || sv >= NEG_LIMIT) && 4780 !isunsigned_op(dis->d86_mnem)) { 4781 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 4782 octal ? "-0%llo" : "-0x%llx", (-sv) & mask); 4783 return (1); 4784 } else { 4785 if (disp == DISP) 4786 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 4787 octal ? "+0%llo" : "+0x%llx", usv & mask); 4788 else 4789 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 4790 octal ? "0%llo" : "0x%llx", usv & mask); 4791 return (0); 4792 4793 } 4794 } 4795 4796 4797 static int 4798 log2(int size) 4799 { 4800 switch (size) { 4801 case 1: return (0); 4802 case 2: return (1); 4803 case 4: return (2); 4804 case 8: return (3); 4805 } 4806 return (0); 4807 } 4808 4809 /* ARGSUSED */ 4810 void 4811 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf, 4812 size_t buflen) 4813 { 4814 uint64_t reltgt = 0; 4815 uint64_t tgt = 0; 4816 int curlen; 4817 int (*lookup)(void *, uint64_t, char *, size_t); 4818 int i; 4819 int64_t sv; 4820 uint64_t usv, mask, save_mask, save_usv; 4821 static uint64_t masks[] = 4822 {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL}; 4823 save_usv = 0; 4824 4825 dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem); 4826 4827 /* 4828 * For PC-relative jumps, the pc is really the next pc after executing 4829 * this instruction, so increment it appropriately. 4830 */ 4831 pc += dis->d86_len; 4832 4833 for (i = 0; i < dis->d86_numopnds; i++) { 4834 d86opnd_t *op = &dis->d86_opnd[i]; 4835 4836 if (i != 0) 4837 (void) strlcat(buf, ",", buflen); 4838 4839 (void) strlcat(buf, op->d86_prefix, buflen); 4840 4841 /* 4842 * sv is for the signed, possibly-truncated immediate or 4843 * displacement; usv retains the original size and 4844 * unsignedness for symbol lookup. 4845 */ 4846 4847 sv = usv = op->d86_value; 4848 4849 /* 4850 * About masks: for immediates that represent 4851 * addresses, the appropriate display size is 4852 * the effective address size of the instruction. 4853 * This includes MODE_OFFSET, MODE_IPREL, and 4854 * MODE_RIPREL. Immediates that are simply 4855 * immediate values should display in the operand's 4856 * size, however, since they don't represent addresses. 4857 */ 4858 4859 /* d86_addr_size is SIZEnn, which is log2(real size) */ 4860 mask = masks[dis->d86_addr_size]; 4861 4862 /* d86_value_size and d86_imm_bytes are in bytes */ 4863 if (op->d86_mode == MODE_SIGNED || 4864 op->d86_mode == MODE_IMPLIED) 4865 mask = masks[log2(op->d86_value_size)]; 4866 4867 switch (op->d86_mode) { 4868 4869 case MODE_NONE: 4870 4871 (void) strlcat(buf, op->d86_opnd, buflen); 4872 break; 4873 4874 case MODE_SIGNED: 4875 case MODE_IMPLIED: 4876 case MODE_OFFSET: 4877 4878 tgt = usv; 4879 4880 if (dis->d86_seg_prefix) 4881 (void) strlcat(buf, dis->d86_seg_prefix, 4882 buflen); 4883 4884 if (op->d86_mode == MODE_SIGNED || 4885 op->d86_mode == MODE_IMPLIED) { 4886 (void) strlcat(buf, "$", buflen); 4887 } 4888 4889 if (print_imm(dis, usv, mask, buf, buflen, 4890 IMM, TRY_NEG) && 4891 (op->d86_mode == MODE_SIGNED || 4892 op->d86_mode == MODE_IMPLIED)) { 4893 4894 /* 4895 * We printed a negative value for an 4896 * immediate that wasn't a 4897 * displacement. Note that fact so we can 4898 * print the positive value as an 4899 * annotation. 4900 */ 4901 4902 save_usv = usv; 4903 save_mask = mask; 4904 } 4905 (void) strlcat(buf, op->d86_opnd, buflen); 4906 4907 break; 4908 4909 case MODE_IPREL: 4910 case MODE_RIPREL: 4911 4912 reltgt = pc + sv; 4913 4914 switch (mode) { 4915 case SIZE16: 4916 reltgt = (uint16_t)reltgt; 4917 break; 4918 case SIZE32: 4919 reltgt = (uint32_t)reltgt; 4920 break; 4921 } 4922 4923 (void) print_imm(dis, usv, mask, buf, buflen, 4924 DISP, TRY_NEG); 4925 4926 if (op->d86_mode == MODE_RIPREL) 4927 (void) strlcat(buf, "(%rip)", buflen); 4928 break; 4929 } 4930 } 4931 4932 /* 4933 * The symbol lookups may result in false positives, 4934 * particularly on object files, where small numbers may match 4935 * the 0-relative non-relocated addresses of symbols. 4936 */ 4937 4938 lookup = dis->d86_sym_lookup; 4939 if (tgt != 0) { 4940 if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 && 4941 lookup(dis->d86_data, tgt, NULL, 0) == 0) { 4942 (void) strlcat(buf, "\t<", buflen); 4943 curlen = strlen(buf); 4944 lookup(dis->d86_data, tgt, buf + curlen, 4945 buflen - curlen); 4946 (void) strlcat(buf, ">", buflen); 4947 } 4948 4949 /* 4950 * If we printed a negative immediate above, print the 4951 * positive in case our heuristic was unhelpful 4952 */ 4953 if (save_usv) { 4954 (void) strlcat(buf, "\t<", buflen); 4955 (void) print_imm(dis, save_usv, save_mask, buf, buflen, 4956 IMM, POS); 4957 (void) strlcat(buf, ">", buflen); 4958 } 4959 } 4960 4961 if (reltgt != 0) { 4962 /* Print symbol or effective address for reltgt */ 4963 4964 (void) strlcat(buf, "\t<", buflen); 4965 curlen = strlen(buf); 4966 lookup(dis->d86_data, reltgt, buf + curlen, 4967 buflen - curlen); 4968 (void) strlcat(buf, ">", buflen); 4969 } 4970 } 4971 4972 #endif /* DIS_TEXT */ 4973